aboutsummaryrefslogtreecommitdiffstats
path: root/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2252-drm-amd-include-cleanup-vega10-dce-header-files.patch
diff options
context:
space:
mode:
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2252-drm-amd-include-cleanup-vega10-dce-header-files.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2252-drm-amd-include-cleanup-vega10-dce-header-files.patch175709
1 files changed, 175709 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2252-drm-amd-include-cleanup-vega10-dce-header-files.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2252-drm-amd-include-cleanup-vega10-dce-header-files.patch
new file mode 100644
index 00000000..80caf18e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2252-drm-amd-include-cleanup-vega10-dce-header-files.patch
@@ -0,0 +1,175709 @@
+From e0cb5aaa4724ed45175ef44a84bc84d683440a90 Mon Sep 17 00:00:00 2001
+From: Feifei Xu <Feifei.Xu@amd.com>
+Date: Wed, 22 Nov 2017 17:48:28 +0800
+Subject: [PATCH 2252/4131] drm/amd/include:cleanup vega10 dce header files.
+
+Cleanup asic_reg/vega10/DC folder.Remove unused dce_12_0_default.h.
+
+Change-Id: I3bc9789765cd06eb90da0f40790d2d90e1839441
+Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 +-
+ .../amd/display/dc/dce120/dce120_hw_sequencer.c | 4 +-
+ .../drm/amd/display/dc/dce120/dce120_resource.c | 4 +-
+ .../display/dc/dce120/dce120_timing_generator.c | 4 +-
+ .../amd/display/dc/gpio/dce120/hw_factory_dce120.c | 4 +-
+ .../display/dc/gpio/dce120/hw_translate_dce120.c | 4 +-
+ .../amd/display/dc/i2caux/dce120/i2caux_dce120.c | 4 +-
+ .../amd/display/dc/irq/dce120/irq_service_dce120.c | 4 +-
+ .../drm/amd/include/asic_reg/dce/dce_12_0_offset.h | 18193 ++++++
+ .../amd/include/asic_reg/dce/dce_12_0_sh_mask.h | 64636 +++++++++++++++++++
+ .../include/asic_reg/vega10/DC/dce_12_0_default.h | 9868 ---
+ .../include/asic_reg/vega10/DC/dce_12_0_offset.h | 18193 ------
+ .../include/asic_reg/vega10/DC/dce_12_0_sh_mask.h | 64636 -------------------
+ 13 files changed, 82845 insertions(+), 92713 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h
+ create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h
+ delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_default.h
+ delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_offset.h
+ delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_sh_mask.h
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 432c3da..94d88f2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -29,8 +29,8 @@
+ #include "hdp/hdp_4_0_offset.h"
+ #include "hdp/hdp_4_0_sh_mask.h"
+ #include "vega10/GC/gc_9_0_sh_mask.h"
+-#include "vega10/DC/dce_12_0_offset.h"
+-#include "vega10/DC/dce_12_0_sh_mask.h"
++#include "dce/dce_12_0_offset.h"
++#include "dce/dce_12_0_sh_mask.h"
+ #include "vega10/vega10_enum.h"
+ #include "vega10/MMHUB/mmhub_1_0_offset.h"
+ #include "athub/athub_1_0_offset.h"
+diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
+index 91301b4..5566749 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
+@@ -33,8 +33,8 @@
+ #include "dce110/dce110_hw_sequencer.h"
+
+ /* include DCE12.0 register header files */
+-#include "vega10/DC/dce_12_0_offset.h"
+-#include "vega10/DC/dce_12_0_sh_mask.h"
++#include "dce/dce_12_0_offset.h"
++#include "dce/dce_12_0_sh_mask.h"
+ #include "vega10/soc15ip.h"
+ #include "reg_helper.h"
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+index d4e9627..c96e61a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+@@ -54,8 +54,8 @@
+ #include "dce/dce_abm.h"
+ #include "dce/dce_dmcu.h"
+
+-#include "vega10/DC/dce_12_0_offset.h"
+-#include "vega10/DC/dce_12_0_sh_mask.h"
++#include "dce/dce_12_0_offset.h"
++#include "dce/dce_12_0_sh_mask.h"
+ #include "vega10/soc15ip.h"
+ #include "vega10/NBIO/nbio_6_1_offset.h"
+ #include "reg_helper.h"
+diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+index 58a070d..a104f7b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+@@ -25,8 +25,8 @@
+
+ #include "dm_services.h"
+
+-#include "vega10/DC/dce_12_0_offset.h"
+-#include "vega10/DC/dce_12_0_sh_mask.h"
++#include "dce/dce_12_0_offset.h"
++#include "dce/dce_12_0_sh_mask.h"
+ #include "vega10/soc15ip.h"
+
+ #include "dc_types.h"
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c b/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c
+index 4ced9a7..d8b70d1 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c
+@@ -34,8 +34,8 @@
+
+ #include "hw_factory_dce120.h"
+
+-#include "vega10/DC/dce_12_0_offset.h"
+-#include "vega10/DC/dce_12_0_sh_mask.h"
++#include "dce/dce_12_0_offset.h"
++#include "dce/dce_12_0_sh_mask.h"
+ #include "vega10/soc15ip.h"
+
+ #define block HPD
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c b/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
+index af3843a..0d0bc44 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
+@@ -33,8 +33,8 @@
+ #include "include/gpio_types.h"
+ #include "../hw_translate.h"
+
+-#include "vega10/DC/dce_12_0_offset.h"
+-#include "vega10/DC/dce_12_0_sh_mask.h"
++#include "dce/dce_12_0_offset.h"
++#include "dce/dce_12_0_sh_mask.h"
+ #include "vega10/soc15ip.h"
+
+ /* begin *********************
+diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c
+index 9119829..4565d6bd 100644
+--- a/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c
++++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c
+@@ -36,8 +36,8 @@
+ #include "../dce110/aux_engine_dce110.h"
+ #include "../dce110/i2caux_dce110.h"
+
+-#include "vega10/DC/dce_12_0_offset.h"
+-#include "vega10/DC/dce_12_0_sh_mask.h"
++#include "dce/dce_12_0_offset.h"
++#include "dce/dce_12_0_sh_mask.h"
+ #include "vega10/soc15ip.h"
+
+ /* begin *********************
+diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
+index 3871633..7199ca4 100644
+--- a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
++++ b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
+@@ -30,8 +30,8 @@
+ #include "irq_service_dce120.h"
+ #include "../dce110/irq_service_dce110.h"
+
+-#include "vega10/DC/dce_12_0_offset.h"
+-#include "vega10/DC/dce_12_0_sh_mask.h"
++#include "dce/dce_12_0_offset.h"
++#include "dce/dce_12_0_sh_mask.h"
+ #include "vega10/soc15ip.h"
+
+ #include "ivsrcid/ivsrcid_vislands30.h"
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h
+new file mode 100644
+index 0000000..75b660d
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h
+@@ -0,0 +1,18193 @@
++/*
++ * Copyright (C) 2017 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++#ifndef _dce_12_0_OFFSET_HEADER
++#define _dce_12_0_OFFSET_HEADER
++
++
++
++// addressBlock: dce_dc_dispdec_VGA_MEM_WRITE_PAGE_ADDR
++// base address: 0x48
++#define mmdispdec_VGA_MEM_WRITE_PAGE_ADDR 0x0012
++#define mmdispdec_VGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
++
++
++// addressBlock: dce_dc_dispdec_VGA_MEM_READ_PAGE_ADDR
++// base address: 0x4c
++#define mmdispdec_VGA_MEM_READ_PAGE_ADDR 0x0014
++#define mmdispdec_VGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
++
++
++// addressBlock: dce_dc_dc_perfmon0_dispdec
++// base address: 0x0
++#define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x0020
++#define mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2
++#define mmDC_PERFMON0_PERFCOUNTER_CNTL2 0x0021
++#define mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2
++#define mmDC_PERFMON0_PERFCOUNTER_STATE 0x0022
++#define mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2
++#define mmDC_PERFMON0_PERFMON_CNTL 0x0023
++#define mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2
++#define mmDC_PERFMON0_PERFMON_CNTL2 0x0024
++#define mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2
++#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x0025
++#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
++#define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x0026
++#define mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2
++#define mmDC_PERFMON0_PERFMON_HI 0x0027
++#define mmDC_PERFMON0_PERFMON_HI_BASE_IDX 2
++#define mmDC_PERFMON0_PERFMON_LOW 0x0028
++#define mmDC_PERFMON0_PERFMON_LOW_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dc_perfmon13_dispdec
++// base address: 0x30
++#define mmDC_PERFMON13_PERFCOUNTER_CNTL 0x002c
++#define mmDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX 2
++#define mmDC_PERFMON13_PERFCOUNTER_CNTL2 0x002d
++#define mmDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX 2
++#define mmDC_PERFMON13_PERFCOUNTER_STATE 0x002e
++#define mmDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX 2
++#define mmDC_PERFMON13_PERFMON_CNTL 0x002f
++#define mmDC_PERFMON13_PERFMON_CNTL_BASE_IDX 2
++#define mmDC_PERFMON13_PERFMON_CNTL2 0x0030
++#define mmDC_PERFMON13_PERFMON_CNTL2_BASE_IDX 2
++#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0x0031
++#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
++#define mmDC_PERFMON13_PERFMON_CVALUE_LOW 0x0032
++#define mmDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX 2
++#define mmDC_PERFMON13_PERFMON_HI 0x0033
++#define mmDC_PERFMON13_PERFMON_HI_BASE_IDX 2
++#define mmDC_PERFMON13_PERFMON_LOW 0x0034
++#define mmDC_PERFMON13_PERFMON_LOW_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dc_displaypllregs_dispdec
++// base address: 0x0
++#define mmPPLL_VREG_CFG 0x0038
++#define mmPPLL_VREG_CFG_BASE_IDX 2
++#define mmPPLL_MODE_CNTL 0x0039
++#define mmPPLL_MODE_CNTL_BASE_IDX 2
++#define mmPPLL_FREQ_CTRL0 0x003a
++#define mmPPLL_FREQ_CTRL0_BASE_IDX 2
++#define mmPPLL_FREQ_CTRL1 0x003b
++#define mmPPLL_FREQ_CTRL1_BASE_IDX 2
++#define mmPPLL_FREQ_CTRL2 0x003c
++#define mmPPLL_FREQ_CTRL2_BASE_IDX 2
++#define mmPPLL_FREQ_CTRL3 0x003d
++#define mmPPLL_FREQ_CTRL3_BASE_IDX 2
++#define mmPPLL_BW_CTRL_COARSE 0x003e
++#define mmPPLL_BW_CTRL_COARSE_BASE_IDX 2
++#define mmPPLL_BW_CTRL_FINE 0x0040
++#define mmPPLL_BW_CTRL_FINE_BASE_IDX 2
++#define mmPPLL_CAL_CTRL 0x0041
++#define mmPPLL_CAL_CTRL_BASE_IDX 2
++#define mmPPLL_LOOP_CTRL 0x0042
++#define mmPPLL_LOOP_CTRL_BASE_IDX 2
++#define mmPPLL_REFCLK_CNTL 0x0050
++#define mmPPLL_REFCLK_CNTL_BASE_IDX 2
++#define mmPPLL_CLKOUT_CNTL 0x0051
++#define mmPPLL_CLKOUT_CNTL_BASE_IDX 2
++#define mmPPLL_DFT_CNTL 0x0052
++#define mmPPLL_DFT_CNTL_BASE_IDX 2
++#define mmPPLL_ANALOG_CNTL 0x0053
++#define mmPPLL_ANALOG_CNTL_BASE_IDX 2
++#define mmPPLL_POSTDIV 0x0054
++#define mmPPLL_POSTDIV_BASE_IDX 2
++#define mmPPLL_OBSERVE0 0x0059
++#define mmPPLL_OBSERVE0_BASE_IDX 2
++#define mmPPLL_OBSERVE1 0x005a
++#define mmPPLL_OBSERVE1_BASE_IDX 2
++#define mmPPLL_UPDATE_CNTL 0x005c
++#define mmPPLL_UPDATE_CNTL_BASE_IDX 2
++#define mmPPLL_OBSERVE0_OUT 0x005d
++#define mmPPLL_OBSERVE0_OUT_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dccg_pll0_dispdec
++// base address: 0x0
++#define mmPLL_MACRO_CNTL_RESERVED0 0x0038
++#define mmPLL_MACRO_CNTL_RESERVED0_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED1 0x0039
++#define mmPLL_MACRO_CNTL_RESERVED1_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED2 0x003a
++#define mmPLL_MACRO_CNTL_RESERVED2_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED3 0x003b
++#define mmPLL_MACRO_CNTL_RESERVED3_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED4 0x003c
++#define mmPLL_MACRO_CNTL_RESERVED4_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED5 0x003d
++#define mmPLL_MACRO_CNTL_RESERVED5_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED6 0x003e
++#define mmPLL_MACRO_CNTL_RESERVED6_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED7 0x003f
++#define mmPLL_MACRO_CNTL_RESERVED7_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED8 0x0040
++#define mmPLL_MACRO_CNTL_RESERVED8_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED9 0x0041
++#define mmPLL_MACRO_CNTL_RESERVED9_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED10 0x0042
++#define mmPLL_MACRO_CNTL_RESERVED10_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED11 0x0043
++#define mmPLL_MACRO_CNTL_RESERVED11_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED12 0x0044
++#define mmPLL_MACRO_CNTL_RESERVED12_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED13 0x0045
++#define mmPLL_MACRO_CNTL_RESERVED13_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED14 0x0046
++#define mmPLL_MACRO_CNTL_RESERVED14_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED15 0x0047
++#define mmPLL_MACRO_CNTL_RESERVED15_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED16 0x0048
++#define mmPLL_MACRO_CNTL_RESERVED16_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED17 0x0049
++#define mmPLL_MACRO_CNTL_RESERVED17_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED18 0x004a
++#define mmPLL_MACRO_CNTL_RESERVED18_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED19 0x004b
++#define mmPLL_MACRO_CNTL_RESERVED19_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED20 0x004c
++#define mmPLL_MACRO_CNTL_RESERVED20_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED21 0x004d
++#define mmPLL_MACRO_CNTL_RESERVED21_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED22 0x004e
++#define mmPLL_MACRO_CNTL_RESERVED22_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED23 0x004f
++#define mmPLL_MACRO_CNTL_RESERVED23_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED24 0x0050
++#define mmPLL_MACRO_CNTL_RESERVED24_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED25 0x0051
++#define mmPLL_MACRO_CNTL_RESERVED25_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED26 0x0052
++#define mmPLL_MACRO_CNTL_RESERVED26_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED27 0x0053
++#define mmPLL_MACRO_CNTL_RESERVED27_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED28 0x0054
++#define mmPLL_MACRO_CNTL_RESERVED28_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED29 0x0055
++#define mmPLL_MACRO_CNTL_RESERVED29_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED30 0x0056
++#define mmPLL_MACRO_CNTL_RESERVED30_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED31 0x0057
++#define mmPLL_MACRO_CNTL_RESERVED31_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED32 0x0058
++#define mmPLL_MACRO_CNTL_RESERVED32_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED33 0x0059
++#define mmPLL_MACRO_CNTL_RESERVED33_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED34 0x005a
++#define mmPLL_MACRO_CNTL_RESERVED34_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED35 0x005b
++#define mmPLL_MACRO_CNTL_RESERVED35_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED36 0x005c
++#define mmPLL_MACRO_CNTL_RESERVED36_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED37 0x005d
++#define mmPLL_MACRO_CNTL_RESERVED37_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED38 0x005e
++#define mmPLL_MACRO_CNTL_RESERVED38_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED39 0x005f
++#define mmPLL_MACRO_CNTL_RESERVED39_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED40 0x0060
++#define mmPLL_MACRO_CNTL_RESERVED40_BASE_IDX 2
++#define mmPLL_MACRO_CNTL_RESERVED41 0x0061
++#define mmPLL_MACRO_CNTL_RESERVED41_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dc_perfmon1_dispdec
++// base address: 0x598
++#define mmDC_PERFMON1_PERFCOUNTER_CNTL 0x0186
++#define mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2
++#define mmDC_PERFMON1_PERFCOUNTER_CNTL2 0x0187
++#define mmDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX 2
++#define mmDC_PERFMON1_PERFCOUNTER_STATE 0x0188
++#define mmDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX 2
++#define mmDC_PERFMON1_PERFMON_CNTL 0x0189
++#define mmDC_PERFMON1_PERFMON_CNTL_BASE_IDX 2
++#define mmDC_PERFMON1_PERFMON_CNTL2 0x018a
++#define mmDC_PERFMON1_PERFMON_CNTL2_BASE_IDX 2
++#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x018b
++#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
++#define mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x018c
++#define mmDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX 2
++#define mmDC_PERFMON1_PERFMON_HI 0x018d
++#define mmDC_PERFMON1_PERFMON_HI_BASE_IDX 2
++#define mmDC_PERFMON1_PERFMON_LOW 0x018e
++#define mmDC_PERFMON1_PERFMON_LOW_BASE_IDX 2
++
++
++// addressBlock: dce_dc_mcif_wb0_dispdec
++// base address: 0x0
++#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL 0x0272
++#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2
++#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R 0x0273
++#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2
++#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS 0x0274
++#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2
++#define mmMCIF_WB0_MCIF_WB_BUF_PITCH 0x0275
++#define mmMCIF_WB0_MCIF_WB_BUF_PITCH_BASE_IDX 2
++#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS 0x0276
++#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS_BASE_IDX 2
++#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2 0x0277
++#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2
++#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS 0x0278
++#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS_BASE_IDX 2
++#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2 0x0279
++#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2
++#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS 0x027a
++#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS_BASE_IDX 2
++#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2 0x027b
++#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2
++#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS 0x027c
++#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS_BASE_IDX 2
++#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2 0x027d
++#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2
++#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL 0x027e
++#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2
++#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE 0x027f
++#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE_BASE_IDX 2
++#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y 0x0282
++#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2
++#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x0283
++#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2
++#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C 0x0284
++#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2
++#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x0285
++#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2
++#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y 0x0286
++#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2
++#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x0287
++#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2
++#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C 0x0288
++#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2
++#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x0289
++#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2
++#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y 0x028a
++#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2
++#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x028b
++#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2
++#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C 0x028c
++#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2
++#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x028d
++#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2
++#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y 0x028e
++#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2
++#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x028f
++#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2
++#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C 0x0290
++#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2
++#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x0291
++#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2
++#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL 0x0292
++#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2
++#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x0293
++#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2
++#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL 0x0294
++#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2
++#define mmMCIF_WB0_MCIF_WB_WATERMARK 0x0295
++#define mmMCIF_WB0_MCIF_WB_WATERMARK_BASE_IDX 2
++#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL 0x0296
++#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2
++#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL 0x0297
++#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2
++#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL 0x0298
++#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2
++#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL 0x0299
++#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2
++#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE 0x029b
++#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2
++#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE 0x029c
++#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2
++
++
++// addressBlock: dce_dc_mcif_wb1_dispdec
++// base address: 0x100
++#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL 0x02b2
++#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2
++#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R 0x02b3
++#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2
++#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS 0x02b4
++#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2
++#define mmMCIF_WB1_MCIF_WB_BUF_PITCH 0x02b5
++#define mmMCIF_WB1_MCIF_WB_BUF_PITCH_BASE_IDX 2
++#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS 0x02b6
++#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS_BASE_IDX 2
++#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2 0x02b7
++#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2
++#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS 0x02b8
++#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS_BASE_IDX 2
++#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2 0x02b9
++#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2
++#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS 0x02ba
++#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS_BASE_IDX 2
++#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2 0x02bb
++#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2
++#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS 0x02bc
++#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS_BASE_IDX 2
++#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2 0x02bd
++#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2
++#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL 0x02be
++#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2
++#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE 0x02bf
++#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE_BASE_IDX 2
++#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y 0x02c2
++#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2
++#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x02c3
++#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2
++#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C 0x02c4
++#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2
++#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x02c5
++#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2
++#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y 0x02c6
++#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2
++#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x02c7
++#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2
++#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C 0x02c8
++#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2
++#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x02c9
++#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2
++#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y 0x02ca
++#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2
++#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x02cb
++#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2
++#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C 0x02cc
++#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2
++#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x02cd
++#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2
++#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y 0x02ce
++#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2
++#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x02cf
++#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2
++#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C 0x02d0
++#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2
++#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x02d1
++#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2
++#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL 0x02d2
++#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2
++#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02d3
++#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2
++#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL 0x02d4
++#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2
++#define mmMCIF_WB1_MCIF_WB_WATERMARK 0x02d5
++#define mmMCIF_WB1_MCIF_WB_WATERMARK_BASE_IDX 2
++#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL 0x02d6
++#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2
++#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL 0x02d7
++#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2
++#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL 0x02d8
++#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2
++#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL 0x02d9
++#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2
++#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE 0x02db
++#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2
++#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE 0x02dc
++#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2
++
++
++// addressBlock: dce_dc_mcif_wb2_dispdec
++// base address: 0x200
++#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL 0x02f2
++#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2
++#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R 0x02f3
++#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2
++#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS 0x02f4
++#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2
++#define mmMCIF_WB2_MCIF_WB_BUF_PITCH 0x02f5
++#define mmMCIF_WB2_MCIF_WB_BUF_PITCH_BASE_IDX 2
++#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS 0x02f6
++#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS_BASE_IDX 2
++#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2 0x02f7
++#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2
++#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS 0x02f8
++#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS_BASE_IDX 2
++#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2 0x02f9
++#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2
++#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS 0x02fa
++#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS_BASE_IDX 2
++#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2 0x02fb
++#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2
++#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS 0x02fc
++#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS_BASE_IDX 2
++#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2 0x02fd
++#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2
++#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL 0x02fe
++#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2
++#define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE 0x02ff
++#define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE_BASE_IDX 2
++#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y 0x0302
++#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2
++#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x0303
++#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2
++#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C 0x0304
++#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2
++#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x0305
++#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2
++#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y 0x0306
++#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2
++#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x0307
++#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2
++#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C 0x0308
++#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2
++#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x0309
++#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2
++#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y 0x030a
++#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2
++#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x030b
++#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2
++#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C 0x030c
++#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2
++#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x030d
++#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2
++#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y 0x030e
++#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2
++#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x030f
++#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2
++#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C 0x0310
++#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2
++#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x0311
++#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2
++#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL 0x0312
++#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2
++#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x0313
++#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2
++#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL 0x0314
++#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2
++#define mmMCIF_WB2_MCIF_WB_WATERMARK 0x0315
++#define mmMCIF_WB2_MCIF_WB_WATERMARK_BASE_IDX 2
++#define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL 0x0316
++#define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2
++#define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL 0x0317
++#define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2
++#define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL 0x0318
++#define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2
++#define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL 0x0319
++#define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2
++#define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE 0x031b
++#define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2
++#define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE 0x031c
++#define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2
++
++
++// addressBlock: dce_dc_cwb0_dispdec
++// base address: 0x0
++#define mmCWB0_CWB_CTRL 0x0332
++#define mmCWB0_CWB_CTRL_BASE_IDX 2
++#define mmCWB0_CWB_FENCE_PAR0 0x0334
++#define mmCWB0_CWB_FENCE_PAR0_BASE_IDX 2
++#define mmCWB0_CWB_FENCE_PAR1 0x0335
++#define mmCWB0_CWB_FENCE_PAR1_BASE_IDX 2
++#define mmCWB0_CWB_CRC_CTRL 0x0339
++#define mmCWB0_CWB_CRC_CTRL_BASE_IDX 2
++#define mmCWB0_CWB_CRC_RED_GREEN_MASK 0x033a
++#define mmCWB0_CWB_CRC_RED_GREEN_MASK_BASE_IDX 2
++#define mmCWB0_CWB_CRC_BLUE_MASK 0x033b
++#define mmCWB0_CWB_CRC_BLUE_MASK_BASE_IDX 2
++#define mmCWB0_CWB_CRC_RED_GREEN_RESULT 0x033c
++#define mmCWB0_CWB_CRC_RED_GREEN_RESULT_BASE_IDX 2
++#define mmCWB0_CWB_CRC_BLUE_RESULT 0x033d
++#define mmCWB0_CWB_CRC_BLUE_RESULT_BASE_IDX 2
++
++
++// addressBlock: dce_dc_cwb1_dispdec
++// base address: 0x60
++#define mmCWB1_CWB_CTRL 0x034a
++#define mmCWB1_CWB_CTRL_BASE_IDX 2
++#define mmCWB1_CWB_FENCE_PAR0 0x034c
++#define mmCWB1_CWB_FENCE_PAR0_BASE_IDX 2
++#define mmCWB1_CWB_FENCE_PAR1 0x034d
++#define mmCWB1_CWB_FENCE_PAR1_BASE_IDX 2
++#define mmCWB1_CWB_CRC_CTRL 0x0351
++#define mmCWB1_CWB_CRC_CTRL_BASE_IDX 2
++#define mmCWB1_CWB_CRC_RED_GREEN_MASK 0x0352
++#define mmCWB1_CWB_CRC_RED_GREEN_MASK_BASE_IDX 2
++#define mmCWB1_CWB_CRC_BLUE_MASK 0x0353
++#define mmCWB1_CWB_CRC_BLUE_MASK_BASE_IDX 2
++#define mmCWB1_CWB_CRC_RED_GREEN_RESULT 0x0354
++#define mmCWB1_CWB_CRC_RED_GREEN_RESULT_BASE_IDX 2
++#define mmCWB1_CWB_CRC_BLUE_RESULT 0x0355
++#define mmCWB1_CWB_CRC_BLUE_RESULT_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dc_perfmon9_dispdec
++// base address: 0xd08
++#define mmDC_PERFMON9_PERFCOUNTER_CNTL 0x0362
++#define mmDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX 2
++#define mmDC_PERFMON9_PERFCOUNTER_CNTL2 0x0363
++#define mmDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX 2
++#define mmDC_PERFMON9_PERFCOUNTER_STATE 0x0364
++#define mmDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX 2
++#define mmDC_PERFMON9_PERFMON_CNTL 0x0365
++#define mmDC_PERFMON9_PERFMON_CNTL_BASE_IDX 2
++#define mmDC_PERFMON9_PERFMON_CNTL2 0x0366
++#define mmDC_PERFMON9_PERFMON_CNTL2_BASE_IDX 2
++#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x0367
++#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
++#define mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x0368
++#define mmDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX 2
++#define mmDC_PERFMON9_PERFMON_HI 0x0369
++#define mmDC_PERFMON9_PERFMON_HI_BASE_IDX 2
++#define mmDC_PERFMON9_PERFMON_LOW 0x036a
++#define mmDC_PERFMON9_PERFMON_LOW_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dispdec
++// base address: 0x0
++#define mmVGA_MEM_WRITE_PAGE_ADDR 0x0000
++#define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
++#define mmVGA_MEM_READ_PAGE_ADDR 0x0001
++#define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
++#define mmVGA_RENDER_CONTROL 0x0000
++#define mmVGA_RENDER_CONTROL_BASE_IDX 1
++#define mmVGA_SEQUENCER_RESET_CONTROL 0x0001
++#define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX 1
++#define mmVGA_MODE_CONTROL 0x0002
++#define mmVGA_MODE_CONTROL_BASE_IDX 1
++#define mmVGA_SURFACE_PITCH_SELECT 0x0003
++#define mmVGA_SURFACE_PITCH_SELECT_BASE_IDX 1
++#define mmVGA_MEMORY_BASE_ADDRESS 0x0004
++#define mmVGA_MEMORY_BASE_ADDRESS_BASE_IDX 1
++#define mmVGA_DISPBUF1_SURFACE_ADDR 0x0006
++#define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX 1
++#define mmVGA_DISPBUF2_SURFACE_ADDR 0x0008
++#define mmVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX 1
++#define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0x0009
++#define mmVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX 1
++#define mmVGA_HDP_CONTROL 0x000a
++#define mmVGA_HDP_CONTROL_BASE_IDX 1
++#define mmVGA_CACHE_CONTROL 0x000b
++#define mmVGA_CACHE_CONTROL_BASE_IDX 1
++#define mmD1VGA_CONTROL 0x000c
++#define mmD1VGA_CONTROL_BASE_IDX 1
++#define mmD2VGA_CONTROL 0x000e
++#define mmD2VGA_CONTROL_BASE_IDX 1
++#define mmVGA_STATUS 0x0010
++#define mmVGA_STATUS_BASE_IDX 1
++#define mmVGA_INTERRUPT_CONTROL 0x0011
++#define mmVGA_INTERRUPT_CONTROL_BASE_IDX 1
++#define mmVGA_STATUS_CLEAR 0x0012
++#define mmVGA_STATUS_CLEAR_BASE_IDX 1
++#define mmVGA_INTERRUPT_STATUS 0x0013
++#define mmVGA_INTERRUPT_STATUS_BASE_IDX 1
++#define mmVGA_MAIN_CONTROL 0x0014
++#define mmVGA_MAIN_CONTROL_BASE_IDX 1
++#define mmVGA_TEST_CONTROL 0x0015
++#define mmVGA_TEST_CONTROL_BASE_IDX 1
++#define mmVGA_QOS_CTRL 0x0018
++#define mmVGA_QOS_CTRL_BASE_IDX 1
++#define mmCRTC8_IDX 0x002d
++#define mmCRTC8_IDX_BASE_IDX 1
++#define mmCRTC8_DATA 0x002d
++#define mmCRTC8_DATA_BASE_IDX 1
++#define mmGENFC_WT 0x002e
++#define mmGENFC_WT_BASE_IDX 1
++#define mmGENS1 0x002e
++#define mmGENS1_BASE_IDX 1
++#define mmATTRDW 0x0030
++#define mmATTRDW_BASE_IDX 1
++#define mmATTRX 0x0030
++#define mmATTRX_BASE_IDX 1
++#define mmATTRDR 0x0030
++#define mmATTRDR_BASE_IDX 1
++#define mmGENMO_WT 0x0030
++#define mmGENMO_WT_BASE_IDX 1
++#define mmGENS0 0x0030
++#define mmGENS0_BASE_IDX 1
++#define mmGENENB 0x0030
++#define mmGENENB_BASE_IDX 1
++#define mmSEQ8_IDX 0x0031
++#define mmSEQ8_IDX_BASE_IDX 1
++#define mmSEQ8_DATA 0x0031
++#define mmSEQ8_DATA_BASE_IDX 1
++#define mmDAC_MASK 0x0031
++#define mmDAC_MASK_BASE_IDX 1
++#define mmDAC_R_INDEX 0x0031
++#define mmDAC_R_INDEX_BASE_IDX 1
++#define mmDAC_W_INDEX 0x0032
++#define mmDAC_W_INDEX_BASE_IDX 1
++#define mmDAC_DATA 0x0032
++#define mmDAC_DATA_BASE_IDX 1
++#define mmGENFC_RD 0x0032
++#define mmGENFC_RD_BASE_IDX 1
++#define mmGENMO_RD 0x0033
++#define mmGENMO_RD_BASE_IDX 1
++#define mmGRPH8_IDX 0x0033
++#define mmGRPH8_IDX_BASE_IDX 1
++#define mmGRPH8_DATA 0x0033
++#define mmGRPH8_DATA_BASE_IDX 1
++#define mmCRTC8_IDX_1 0x0035
++#define mmCRTC8_IDX_1_BASE_IDX 1
++#define mmCRTC8_DATA_1 0x0035
++#define mmCRTC8_DATA_1_BASE_IDX 1
++#define mmGENFC_WT_1 0x0036
++#define mmGENFC_WT_1_BASE_IDX 1
++#define mmGENS1_1 0x0036
++#define mmGENS1_1_BASE_IDX 1
++#define mmD3VGA_CONTROL 0x0038
++#define mmD3VGA_CONTROL_BASE_IDX 1
++#define mmD4VGA_CONTROL 0x0039
++#define mmD4VGA_CONTROL_BASE_IDX 1
++#define mmD5VGA_CONTROL 0x003a
++#define mmD5VGA_CONTROL_BASE_IDX 1
++#define mmD6VGA_CONTROL 0x003b
++#define mmD6VGA_CONTROL_BASE_IDX 1
++#define mmVGA_SOURCE_SELECT 0x003c
++#define mmVGA_SOURCE_SELECT_BASE_IDX 1
++#define mmPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
++#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1
++#define mmPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
++#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1
++#define mmPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042
++#define mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1
++#define mmPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043
++#define mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1
++#define mmDCFEV0_CRTC_PIXEL_RATE_CNTL 0x0044
++#define mmDCFEV0_CRTC_PIXEL_RATE_CNTL_BASE_IDX 1
++#define mmDCFEV1_CRTC_PIXEL_RATE_CNTL 0x0045
++#define mmDCFEV1_CRTC_PIXEL_RATE_CNTL_BASE_IDX 1
++#define mmSYMCLKLPA_CLOCK_ENABLE 0x0046
++#define mmSYMCLKLPA_CLOCK_ENABLE_BASE_IDX 1
++#define mmSYMCLKLPB_CLOCK_ENABLE 0x0047
++#define mmSYMCLKLPB_CLOCK_ENABLE_BASE_IDX 1
++#define mmDPREFCLK_CGTT_BLK_CTRL_REG 0x0048
++#define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
++#define mmREFCLK_CNTL 0x0049
++#define mmREFCLK_CNTL_BASE_IDX 1
++#define mmMIPI_CLK_CNTL 0x004a
++#define mmMIPI_CLK_CNTL_BASE_IDX 1
++#define mmREFCLK_CGTT_BLK_CTRL_REG 0x004b
++#define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
++#define mmPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c
++#define mmPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1
++#define mmDCCG_PERFMON_CNTL2 0x004e
++#define mmDCCG_PERFMON_CNTL2_BASE_IDX 1
++#define mmDSICLK_CGTT_BLK_CTRL_REG 0x004f
++#define mmDSICLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
++#define mmDCCG_CBUS_WRCMD_DELAY 0x0050
++#define mmDCCG_CBUS_WRCMD_DELAY_BASE_IDX 1
++#define mmDCCG_DS_DTO_INCR 0x0053
++#define mmDCCG_DS_DTO_INCR_BASE_IDX 1
++#define mmDCCG_DS_DTO_MODULO 0x0054
++#define mmDCCG_DS_DTO_MODULO_BASE_IDX 1
++#define mmDCCG_DS_CNTL 0x0055
++#define mmDCCG_DS_CNTL_BASE_IDX 1
++#define mmDCCG_DS_HW_CAL_INTERVAL 0x0056
++#define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1
++#define mmSYMCLKG_CLOCK_ENABLE 0x0057
++#define mmSYMCLKG_CLOCK_ENABLE_BASE_IDX 1
++#define mmDPREFCLK_CNTL 0x0058
++#define mmDPREFCLK_CNTL_BASE_IDX 1
++#define mmAOMCLK0_CNTL 0x0059
++#define mmAOMCLK0_CNTL_BASE_IDX 1
++#define mmAOMCLK1_CNTL 0x005a
++#define mmAOMCLK1_CNTL_BASE_IDX 1
++#define mmAOMCLK2_CNTL 0x005b
++#define mmAOMCLK2_CNTL_BASE_IDX 1
++#define mmDCCG_AUDIO_DTO2_PHASE 0x005c
++#define mmDCCG_AUDIO_DTO2_PHASE_BASE_IDX 1
++#define mmDCCG_AUDIO_DTO2_MODULO 0x005d
++#define mmDCCG_AUDIO_DTO2_MODULO_BASE_IDX 1
++#define mmDCE_VERSION 0x005e
++#define mmDCE_VERSION_BASE_IDX 1
++#define mmPHYPLLG_PIXCLK_RESYNC_CNTL 0x005f
++#define mmPHYPLLG_PIXCLK_RESYNC_CNTL_BASE_IDX 1
++#define mmDCCG_GTC_CNTL 0x0060
++#define mmDCCG_GTC_CNTL_BASE_IDX 1
++#define mmDCCG_GTC_DTO_INCR 0x0061
++#define mmDCCG_GTC_DTO_INCR_BASE_IDX 1
++#define mmDCCG_GTC_DTO_MODULO 0x0062
++#define mmDCCG_GTC_DTO_MODULO_BASE_IDX 1
++#define mmDCCG_GTC_CURRENT 0x0063
++#define mmDCCG_GTC_CURRENT_BASE_IDX 1
++#define mmDENTIST_DISPCLK_CNTL 0x0064
++#define mmDENTIST_DISPCLK_CNTL_BASE_IDX 1
++#define mmMIPI_DTO_CNTL 0x0065
++#define mmMIPI_DTO_CNTL_BASE_IDX 1
++#define mmMIPI_DTO_PHASE 0x0066
++#define mmMIPI_DTO_PHASE_BASE_IDX 1
++#define mmMIPI_DTO_MODULO 0x0067
++#define mmMIPI_DTO_MODULO_BASE_IDX 1
++#define mmDAC_CLK_ENABLE 0x0068
++#define mmDAC_CLK_ENABLE_BASE_IDX 1
++#define mmDVO_CLK_ENABLE 0x0069
++#define mmDVO_CLK_ENABLE_BASE_IDX 1
++#define mmAVSYNC_COUNTER_WRITE 0x006a
++#define mmAVSYNC_COUNTER_WRITE_BASE_IDX 1
++#define mmAVSYNC_COUNTER_CONTROL 0x006b
++#define mmAVSYNC_COUNTER_CONTROL_BASE_IDX 1
++#define mmDMCU_SMU_INTERRUPT_CNTL 0x006c
++#define mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX 1
++#define mmSMU_CONTROL 0x006d
++#define mmSMU_CONTROL_BASE_IDX 1
++#define mmSMU_INTERRUPT_CONTROL 0x006e
++#define mmSMU_INTERRUPT_CONTROL_BASE_IDX 1
++#define mmAVSYNC_COUNTER_READ 0x006f
++#define mmAVSYNC_COUNTER_READ_BASE_IDX 1
++#define mmMILLISECOND_TIME_BASE_DIV 0x0070
++#define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX 1
++#define mmDISPCLK_FREQ_CHANGE_CNTL 0x0071
++#define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1
++#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072
++#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1
++#define mmDCCG_PERFMON_CNTL 0x0073
++#define mmDCCG_PERFMON_CNTL_BASE_IDX 1
++#define mmDCCG_GATE_DISABLE_CNTL 0x0074
++#define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX 1
++#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x0075
++#define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
++#define mmSCLK_CGTT_BLK_CTRL_REG 0x0076
++#define mmSCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
++#define mmDCCG_CAC_STATUS 0x0077
++#define mmDCCG_CAC_STATUS_BASE_IDX 1
++#define mmPIXCLK1_RESYNC_CNTL 0x0078
++#define mmPIXCLK1_RESYNC_CNTL_BASE_IDX 1
++#define mmPIXCLK2_RESYNC_CNTL 0x0079
++#define mmPIXCLK2_RESYNC_CNTL_BASE_IDX 1
++#define mmPIXCLK0_RESYNC_CNTL 0x007a
++#define mmPIXCLK0_RESYNC_CNTL_BASE_IDX 1
++#define mmMICROSECOND_TIME_BASE_DIV 0x007b
++#define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX 1
++#define mmDCCG_GATE_DISABLE_CNTL2 0x007c
++#define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1
++#define mmSYMCLK_CGTT_BLK_CTRL_REG 0x007d
++#define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
++#define mmPHYPLLF_PIXCLK_RESYNC_CNTL 0x007e
++#define mmPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX 1
++#define mmDCCG_DISP_CNTL_REG 0x007f
++#define mmDCCG_DISP_CNTL_REG_BASE_IDX 1
++#define mmCRTC0_PIXEL_RATE_CNTL 0x0080
++#define mmCRTC0_PIXEL_RATE_CNTL_BASE_IDX 1
++#define mmDP_DTO0_PHASE 0x0081
++#define mmDP_DTO0_PHASE_BASE_IDX 1
++#define mmDP_DTO0_MODULO 0x0082
++#define mmDP_DTO0_MODULO_BASE_IDX 1
++#define mmCRTC0_PHYPLL_PIXEL_RATE_CNTL 0x0083
++#define mmCRTC0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
++#define mmCRTC1_PIXEL_RATE_CNTL 0x0084
++#define mmCRTC1_PIXEL_RATE_CNTL_BASE_IDX 1
++#define mmDP_DTO1_PHASE 0x0085
++#define mmDP_DTO1_PHASE_BASE_IDX 1
++#define mmDP_DTO1_MODULO 0x0086
++#define mmDP_DTO1_MODULO_BASE_IDX 1
++#define mmCRTC1_PHYPLL_PIXEL_RATE_CNTL 0x0087
++#define mmCRTC1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
++#define mmCRTC2_PIXEL_RATE_CNTL 0x0088
++#define mmCRTC2_PIXEL_RATE_CNTL_BASE_IDX 1
++#define mmDP_DTO2_PHASE 0x0089
++#define mmDP_DTO2_PHASE_BASE_IDX 1
++#define mmDP_DTO2_MODULO 0x008a
++#define mmDP_DTO2_MODULO_BASE_IDX 1
++#define mmCRTC2_PHYPLL_PIXEL_RATE_CNTL 0x008b
++#define mmCRTC2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
++#define mmCRTC3_PIXEL_RATE_CNTL 0x008c
++#define mmCRTC3_PIXEL_RATE_CNTL_BASE_IDX 1
++#define mmDP_DTO3_PHASE 0x008d
++#define mmDP_DTO3_PHASE_BASE_IDX 1
++#define mmDP_DTO3_MODULO 0x008e
++#define mmDP_DTO3_MODULO_BASE_IDX 1
++#define mmCRTC3_PHYPLL_PIXEL_RATE_CNTL 0x008f
++#define mmCRTC3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
++#define mmCRTC4_PIXEL_RATE_CNTL 0x0090
++#define mmCRTC4_PIXEL_RATE_CNTL_BASE_IDX 1
++#define mmDP_DTO4_PHASE 0x0091
++#define mmDP_DTO4_PHASE_BASE_IDX 1
++#define mmDP_DTO4_MODULO 0x0092
++#define mmDP_DTO4_MODULO_BASE_IDX 1
++#define mmCRTC4_PHYPLL_PIXEL_RATE_CNTL 0x0093
++#define mmCRTC4_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
++#define mmCRTC5_PIXEL_RATE_CNTL 0x0094
++#define mmCRTC5_PIXEL_RATE_CNTL_BASE_IDX 1
++#define mmDP_DTO5_PHASE 0x0095
++#define mmDP_DTO5_PHASE_BASE_IDX 1
++#define mmDP_DTO5_MODULO 0x0096
++#define mmDP_DTO5_MODULO_BASE_IDX 1
++#define mmCRTC5_PHYPLL_PIXEL_RATE_CNTL 0x0097
++#define mmCRTC5_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
++#define mmDCCG_SOFT_RESET 0x009f
++#define mmDCCG_SOFT_RESET_BASE_IDX 1
++#define mmSYMCLKA_CLOCK_ENABLE 0x00a0
++#define mmSYMCLKA_CLOCK_ENABLE_BASE_IDX 1
++#define mmSYMCLKB_CLOCK_ENABLE 0x00a1
++#define mmSYMCLKB_CLOCK_ENABLE_BASE_IDX 1
++#define mmSYMCLKC_CLOCK_ENABLE 0x00a2
++#define mmSYMCLKC_CLOCK_ENABLE_BASE_IDX 1
++#define mmSYMCLKD_CLOCK_ENABLE 0x00a3
++#define mmSYMCLKD_CLOCK_ENABLE_BASE_IDX 1
++#define mmSYMCLKE_CLOCK_ENABLE 0x00a4
++#define mmSYMCLKE_CLOCK_ENABLE_BASE_IDX 1
++#define mmSYMCLKF_CLOCK_ENABLE 0x00a5
++#define mmSYMCLKF_CLOCK_ENABLE_BASE_IDX 1
++#define mmDVOACLKD_CNTL 0x00a8
++#define mmDVOACLKD_CNTL_BASE_IDX 1
++#define mmDVOACLKC_MVP_CNTL 0x00a9
++#define mmDVOACLKC_MVP_CNTL_BASE_IDX 1
++#define mmDVOACLKC_CNTL 0x00aa
++#define mmDVOACLKC_CNTL_BASE_IDX 1
++#define mmDCCG_AUDIO_DTO_SOURCE 0x00ab
++#define mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1
++#define mmDCCG_AUDIO_DTO0_PHASE 0x00ac
++#define mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1
++#define mmDCCG_AUDIO_DTO0_MODULE 0x00ad
++#define mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1
++#define mmDCCG_AUDIO_DTO1_PHASE 0x00ae
++#define mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1
++#define mmDCCG_AUDIO_DTO1_MODULE 0x00af
++#define mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1
++#define mmDCCG_TEST_CLK_SEL 0x00be
++#define mmDCCG_TEST_CLK_SEL_BASE_IDX 1
++#define mmFBC_CNTL 0x0062
++#define mmFBC_CNTL_BASE_IDX 2
++#define mmFBC_IDLE_FORCE_CLEAR_MASK 0x0064
++#define mmFBC_IDLE_FORCE_CLEAR_MASK_BASE_IDX 2
++#define mmFBC_START_STOP_DELAY 0x0065
++#define mmFBC_START_STOP_DELAY_BASE_IDX 2
++#define mmFBC_COMP_CNTL 0x0066
++#define mmFBC_COMP_CNTL_BASE_IDX 2
++#define mmFBC_COMP_MODE 0x0067
++#define mmFBC_COMP_MODE_BASE_IDX 2
++#define mmFBC_IND_LUT0 0x006b
++#define mmFBC_IND_LUT0_BASE_IDX 2
++#define mmFBC_IND_LUT1 0x006c
++#define mmFBC_IND_LUT1_BASE_IDX 2
++#define mmFBC_IND_LUT2 0x006d
++#define mmFBC_IND_LUT2_BASE_IDX 2
++#define mmFBC_IND_LUT3 0x006e
++#define mmFBC_IND_LUT3_BASE_IDX 2
++#define mmFBC_IND_LUT4 0x006f
++#define mmFBC_IND_LUT4_BASE_IDX 2
++#define mmFBC_IND_LUT5 0x0070
++#define mmFBC_IND_LUT5_BASE_IDX 2
++#define mmFBC_IND_LUT6 0x0071
++#define mmFBC_IND_LUT6_BASE_IDX 2
++#define mmFBC_IND_LUT7 0x0072
++#define mmFBC_IND_LUT7_BASE_IDX 2
++#define mmFBC_IND_LUT8 0x0073
++#define mmFBC_IND_LUT8_BASE_IDX 2
++#define mmFBC_IND_LUT9 0x0074
++#define mmFBC_IND_LUT9_BASE_IDX 2
++#define mmFBC_IND_LUT10 0x0075
++#define mmFBC_IND_LUT10_BASE_IDX 2
++#define mmFBC_IND_LUT11 0x0076
++#define mmFBC_IND_LUT11_BASE_IDX 2
++#define mmFBC_IND_LUT12 0x0077
++#define mmFBC_IND_LUT12_BASE_IDX 2
++#define mmFBC_IND_LUT13 0x0078
++#define mmFBC_IND_LUT13_BASE_IDX 2
++#define mmFBC_IND_LUT14 0x0079
++#define mmFBC_IND_LUT14_BASE_IDX 2
++#define mmFBC_IND_LUT15 0x007a
++#define mmFBC_IND_LUT15_BASE_IDX 2
++#define mmFBC_CSM_REGION_OFFSET_01 0x007b
++#define mmFBC_CSM_REGION_OFFSET_01_BASE_IDX 2
++#define mmFBC_CSM_REGION_OFFSET_23 0x007c
++#define mmFBC_CSM_REGION_OFFSET_23_BASE_IDX 2
++#define mmFBC_CLIENT_REGION_MASK 0x007d
++#define mmFBC_CLIENT_REGION_MASK_BASE_IDX 2
++#define mmFBC_DEBUG_COMP 0x007e
++#define mmFBC_DEBUG_COMP_BASE_IDX 2
++#define mmFBC_MISC 0x0084
++#define mmFBC_MISC_BASE_IDX 2
++#define mmFBC_STATUS 0x0085
++#define mmFBC_STATUS_BASE_IDX 2
++#define mmFBC_ALPHA_CNTL 0x0088
++#define mmFBC_ALPHA_CNTL_BASE_IDX 2
++#define mmFBC_ALPHA_RGB_OVERRIDE 0x0089
++#define mmFBC_ALPHA_RGB_OVERRIDE_BASE_IDX 2
++#define mmPIPE0_PG_CONFIG 0x008e
++#define mmPIPE0_PG_CONFIG_BASE_IDX 2
++#define mmPIPE0_PG_ENABLE 0x008f
++#define mmPIPE0_PG_ENABLE_BASE_IDX 2
++#define mmPIPE0_PG_STATUS 0x0090
++#define mmPIPE0_PG_STATUS_BASE_IDX 2
++#define mmPIPE1_PG_CONFIG 0x0091
++#define mmPIPE1_PG_CONFIG_BASE_IDX 2
++#define mmPIPE1_PG_ENABLE 0x0092
++#define mmPIPE1_PG_ENABLE_BASE_IDX 2
++#define mmPIPE1_PG_STATUS 0x0093
++#define mmPIPE1_PG_STATUS_BASE_IDX 2
++#define mmPIPE2_PG_CONFIG 0x0094
++#define mmPIPE2_PG_CONFIG_BASE_IDX 2
++#define mmPIPE2_PG_ENABLE 0x0095
++#define mmPIPE2_PG_ENABLE_BASE_IDX 2
++#define mmPIPE2_PG_STATUS 0x0096
++#define mmPIPE2_PG_STATUS_BASE_IDX 2
++#define mmPIPE3_PG_CONFIG 0x0097
++#define mmPIPE3_PG_CONFIG_BASE_IDX 2
++#define mmPIPE3_PG_ENABLE 0x0098
++#define mmPIPE3_PG_ENABLE_BASE_IDX 2
++#define mmPIPE3_PG_STATUS 0x0099
++#define mmPIPE3_PG_STATUS_BASE_IDX 2
++#define mmPIPE4_PG_CONFIG 0x009a
++#define mmPIPE4_PG_CONFIG_BASE_IDX 2
++#define mmPIPE4_PG_ENABLE 0x009b
++#define mmPIPE4_PG_ENABLE_BASE_IDX 2
++#define mmPIPE4_PG_STATUS 0x009c
++#define mmPIPE4_PG_STATUS_BASE_IDX 2
++#define mmPIPE5_PG_CONFIG 0x009d
++#define mmPIPE5_PG_CONFIG_BASE_IDX 2
++#define mmPIPE5_PG_ENABLE 0x009e
++#define mmPIPE5_PG_ENABLE_BASE_IDX 2
++#define mmPIPE5_PG_STATUS 0x009f
++#define mmPIPE5_PG_STATUS_BASE_IDX 2
++#define mmDSI_PG_CONFIG 0x00a0
++#define mmDSI_PG_CONFIG_BASE_IDX 2
++#define mmDSI_PG_ENABLE 0x00a1
++#define mmDSI_PG_ENABLE_BASE_IDX 2
++#define mmDSI_PG_STATUS 0x00a2
++#define mmDSI_PG_STATUS_BASE_IDX 2
++#define mmDCFEV0_PG_CONFIG 0x00a3
++#define mmDCFEV0_PG_CONFIG_BASE_IDX 2
++#define mmDCFEV0_PG_ENABLE 0x00a4
++#define mmDCFEV0_PG_ENABLE_BASE_IDX 2
++#define mmDCFEV0_PG_STATUS 0x00a5
++#define mmDCFEV0_PG_STATUS_BASE_IDX 2
++#define mmDCPG_INTERRUPT_STATUS 0x00a6
++#define mmDCPG_INTERRUPT_STATUS_BASE_IDX 2
++#define mmDCPG_INTERRUPT_CONTROL 0x00a7
++#define mmDCPG_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmDCPG_INTERRUPT_CONTROL2 0x00a8
++#define mmDCPG_INTERRUPT_CONTROL2_BASE_IDX 2
++#define mmDCFEV1_PG_CONFIG 0x00a9
++#define mmDCFEV1_PG_CONFIG_BASE_IDX 2
++#define mmDCFEV1_PG_ENABLE 0x00aa
++#define mmDCFEV1_PG_ENABLE_BASE_IDX 2
++#define mmDCFEV1_PG_STATUS 0x00ab
++#define mmDCFEV1_PG_STATUS_BASE_IDX 2
++#define mmDC_IP_REQUEST_CNTL 0x00ac
++#define mmDC_IP_REQUEST_CNTL_BASE_IDX 2
++#define mmDC_PGCNTL_STATUS_REG 0x00ad
++#define mmDC_PGCNTL_STATUS_REG_BASE_IDX 2
++#define mmDMIFV_STATUS 0x00c3
++#define mmDMIFV_STATUS_BASE_IDX 2
++#define mmDMIF_CONTROL 0x00c4
++#define mmDMIF_CONTROL_BASE_IDX 2
++#define mmDMIF_STATUS 0x00c5
++#define mmDMIF_STATUS_BASE_IDX 2
++#define mmDMIF_ARBITRATION_CONTROL 0x00c7
++#define mmDMIF_ARBITRATION_CONTROL_BASE_IDX 2
++#define mmPIPE0_ARBITRATION_CONTROL3 0x00c8
++#define mmPIPE0_ARBITRATION_CONTROL3_BASE_IDX 2
++#define mmPIPE1_ARBITRATION_CONTROL3 0x00c9
++#define mmPIPE1_ARBITRATION_CONTROL3_BASE_IDX 2
++#define mmPIPE2_ARBITRATION_CONTROL3 0x00ca
++#define mmPIPE2_ARBITRATION_CONTROL3_BASE_IDX 2
++#define mmPIPE3_ARBITRATION_CONTROL3 0x00cb
++#define mmPIPE3_ARBITRATION_CONTROL3_BASE_IDX 2
++#define mmPIPE4_ARBITRATION_CONTROL3 0x00cc
++#define mmPIPE4_ARBITRATION_CONTROL3_BASE_IDX 2
++#define mmPIPE5_ARBITRATION_CONTROL3 0x00cd
++#define mmPIPE5_ARBITRATION_CONTROL3_BASE_IDX 2
++#define mmDMIF_P_VMID 0x00ce
++#define mmDMIF_P_VMID_BASE_IDX 2
++#define mmDMIF_ADDR_CALC 0x00d1
++#define mmDMIF_ADDR_CALC_BASE_IDX 2
++#define mmDMIF_STATUS2 0x00d2
++#define mmDMIF_STATUS2_BASE_IDX 2
++#define mmPIPE0_MAX_REQUESTS 0x00d3
++#define mmPIPE0_MAX_REQUESTS_BASE_IDX 2
++#define mmPIPE1_MAX_REQUESTS 0x00d4
++#define mmPIPE1_MAX_REQUESTS_BASE_IDX 2
++#define mmPIPE2_MAX_REQUESTS 0x00d5
++#define mmPIPE2_MAX_REQUESTS_BASE_IDX 2
++#define mmPIPE3_MAX_REQUESTS 0x00d6
++#define mmPIPE3_MAX_REQUESTS_BASE_IDX 2
++#define mmPIPE4_MAX_REQUESTS 0x00d7
++#define mmPIPE4_MAX_REQUESTS_BASE_IDX 2
++#define mmPIPE5_MAX_REQUESTS 0x00d8
++#define mmPIPE5_MAX_REQUESTS_BASE_IDX 2
++#define mmLOW_POWER_TILING_CONTROL 0x00d9
++#define mmLOW_POWER_TILING_CONTROL_BASE_IDX 2
++#define mmMCIF_CONTROL 0x00da
++#define mmMCIF_CONTROL_BASE_IDX 2
++#define mmMCIF_WRITE_COMBINE_CONTROL 0x00db
++#define mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX 2
++#define mmMCIF_PHASE0_OUTSTANDING_COUNTER 0x00de
++#define mmMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2
++#define mmCC_DC_PIPE_DIS 0x00e0
++#define mmCC_DC_PIPE_DIS_BASE_IDX 2
++#define mmSMU_WM_CONTROL 0x00e1
++#define mmSMU_WM_CONTROL_BASE_IDX 2
++#define mmRBBMIF_TIMEOUT 0x00e2
++#define mmRBBMIF_TIMEOUT_BASE_IDX 2
++#define mmRBBMIF_STATUS 0x00e3
++#define mmRBBMIF_STATUS_BASE_IDX 2
++#define mmRBBMIF_TIMEOUT_DIS 0x00e4
++#define mmRBBMIF_TIMEOUT_DIS_BASE_IDX 2
++#define mmDCI_MEM_PWR_STATUS 0x00e5
++#define mmDCI_MEM_PWR_STATUS_BASE_IDX 2
++#define mmDCI_MEM_PWR_STATUS2 0x00e6
++#define mmDCI_MEM_PWR_STATUS2_BASE_IDX 2
++#define mmDCI_CLK_CNTL 0x00e7
++#define mmDCI_CLK_CNTL_BASE_IDX 2
++#define mmDCI_CLK_CNTL2 0x00e8
++#define mmDCI_CLK_CNTL2_BASE_IDX 2
++#define mmDCI_MEM_PWR_CNTL 0x00e9
++#define mmDCI_MEM_PWR_CNTL_BASE_IDX 2
++#define mmDCI_MEM_PWR_CNTL2 0x00ea
++#define mmDCI_MEM_PWR_CNTL2_BASE_IDX 2
++#define mmDCI_MEM_PWR_CNTL3 0x00eb
++#define mmDCI_MEM_PWR_CNTL3_BASE_IDX 2
++#define mmPIPE0_DMIF_BUFFER_CONTROL 0x00ef
++#define mmPIPE0_DMIF_BUFFER_CONTROL_BASE_IDX 2
++#define mmPIPE1_DMIF_BUFFER_CONTROL 0x00f0
++#define mmPIPE1_DMIF_BUFFER_CONTROL_BASE_IDX 2
++#define mmPIPE2_DMIF_BUFFER_CONTROL 0x00f1
++#define mmPIPE2_DMIF_BUFFER_CONTROL_BASE_IDX 2
++#define mmPIPE3_DMIF_BUFFER_CONTROL 0x00f2
++#define mmPIPE3_DMIF_BUFFER_CONTROL_BASE_IDX 2
++#define mmPIPE4_DMIF_BUFFER_CONTROL 0x00f3
++#define mmPIPE4_DMIF_BUFFER_CONTROL_BASE_IDX 2
++#define mmPIPE5_DMIF_BUFFER_CONTROL 0x00f4
++#define mmPIPE5_DMIF_BUFFER_CONTROL_BASE_IDX 2
++#define mmRBBMIF_STATUS_FLAG 0x00f5
++#define mmRBBMIF_STATUS_FLAG_BASE_IDX 2
++#define mmDCI_SOFT_RESET 0x00f6
++#define mmDCI_SOFT_RESET_BASE_IDX 2
++#define mmDMIF_URG_OVERRIDE 0x00f7
++#define mmDMIF_URG_OVERRIDE_BASE_IDX 2
++#define mmPIPE6_ARBITRATION_CONTROL3 0x00f8
++#define mmPIPE6_ARBITRATION_CONTROL3_BASE_IDX 2
++#define mmPIPE7_ARBITRATION_CONTROL3 0x00f9
++#define mmPIPE7_ARBITRATION_CONTROL3_BASE_IDX 2
++#define mmPIPE6_MAX_REQUESTS 0x00fa
++#define mmPIPE6_MAX_REQUESTS_BASE_IDX 2
++#define mmPIPE7_MAX_REQUESTS 0x00fb
++#define mmPIPE7_MAX_REQUESTS_BASE_IDX 2
++#define mmDVMM_REG_RD_STATUS 0x00fc
++#define mmDVMM_REG_RD_STATUS_BASE_IDX 2
++#define mmDVMM_REG_RD_DATA 0x00fd
++#define mmDVMM_REG_RD_DATA_BASE_IDX 2
++#define mmDVMM_PTE_REQ 0x00fe
++#define mmDVMM_PTE_REQ_BASE_IDX 2
++#define mmDVMM_CNTL 0x00ff
++#define mmDVMM_CNTL_BASE_IDX 2
++#define mmDVMM_FAULT_STATUS 0x0100
++#define mmDVMM_FAULT_STATUS_BASE_IDX 2
++#define mmDVMM_FAULT_ADDR 0x0101
++#define mmDVMM_FAULT_ADDR_BASE_IDX 2
++#define mmFMON_CTRL 0x0102
++#define mmFMON_CTRL_BASE_IDX 2
++#define mmDVMM_PTE_PGMEM_CONTROL 0x0103
++#define mmDVMM_PTE_PGMEM_CONTROL_BASE_IDX 2
++#define mmDVMM_PTE_PGMEM_STATE 0x0104
++#define mmDVMM_PTE_PGMEM_STATE_BASE_IDX 2
++#define mmMCIF_PHASE1_OUTSTANDING_COUNTER 0x0105
++#define mmMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2
++#define mmMCIF_PHASE2_OUTSTANDING_COUNTER 0x0106
++#define mmMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX 2
++#define mmMCIF_WB_PHASE0_OUTSTANDING_COUNTER 0x0107
++#define mmMCIF_WB_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2
++#define mmMCIF_WB_PHASE1_OUTSTANDING_COUNTER 0x0108
++#define mmMCIF_WB_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2
++#define mmDCI_MEM_PWR_CNTL4 0x0109
++#define mmDCI_MEM_PWR_CNTL4_BASE_IDX 2
++#define mmMCIF_WB_MISC_CTRL 0x010a
++#define mmMCIF_WB_MISC_CTRL_BASE_IDX 2
++#define mmDCI_MEM_PWR_STATUS3 0x010b
++#define mmDCI_MEM_PWR_STATUS3_BASE_IDX 2
++#define mmDMIF_CURSOR_CONTROL 0x010c
++#define mmDMIF_CURSOR_CONTROL_BASE_IDX 2
++#define mmDMIF_CURSOR_MEM_CONTROL 0x010d
++#define mmDMIF_CURSOR_MEM_CONTROL_BASE_IDX 2
++#define mmDCHUB_FB_LOCATION 0x0126
++#define mmDCHUB_FB_LOCATION_BASE_IDX 2
++#define mmDCHUB_FB_OFFSET 0x0127
++#define mmDCHUB_FB_OFFSET_BASE_IDX 2
++#define mmDCHUB_AGP_BASE 0x0128
++#define mmDCHUB_AGP_BASE_BASE_IDX 2
++#define mmDCHUB_AGP_BOT 0x0129
++#define mmDCHUB_AGP_BOT_BASE_IDX 2
++#define mmDCHUB_AGP_TOP 0x012a
++#define mmDCHUB_AGP_TOP_BASE_IDX 2
++#define mmDCHUB_DRAM_APER_BASE 0x012b
++#define mmDCHUB_DRAM_APER_BASE_BASE_IDX 2
++#define mmDCHUB_DRAM_APER_DEF 0x012c
++#define mmDCHUB_DRAM_APER_DEF_BASE_IDX 2
++#define mmDCHUB_DRAM_APER_TOP 0x012d
++#define mmDCHUB_DRAM_APER_TOP_BASE_IDX 2
++#define mmDCHUB_CONTROL_STATUS 0x012e
++#define mmDCHUB_CONTROL_STATUS_BASE_IDX 2
++#define mmWB_ENABLE 0x0212
++#define mmWB_ENABLE_BASE_IDX 2
++#define mmWB_EC_CONFIG 0x0213
++#define mmWB_EC_CONFIG_BASE_IDX 2
++#define mmCNV_MODE 0x0214
++#define mmCNV_MODE_BASE_IDX 2
++#define mmCNV_WINDOW_START 0x0215
++#define mmCNV_WINDOW_START_BASE_IDX 2
++#define mmCNV_WINDOW_SIZE 0x0216
++#define mmCNV_WINDOW_SIZE_BASE_IDX 2
++#define mmCNV_UPDATE 0x0217
++#define mmCNV_UPDATE_BASE_IDX 2
++#define mmCNV_SOURCE_SIZE 0x0218
++#define mmCNV_SOURCE_SIZE_BASE_IDX 2
++#define mmCNV_CSC_CONTROL 0x0219
++#define mmCNV_CSC_CONTROL_BASE_IDX 2
++#define mmCNV_CSC_C11_C12 0x021a
++#define mmCNV_CSC_C11_C12_BASE_IDX 2
++#define mmCNV_CSC_C13_C14 0x021b
++#define mmCNV_CSC_C13_C14_BASE_IDX 2
++#define mmCNV_CSC_C21_C22 0x021c
++#define mmCNV_CSC_C21_C22_BASE_IDX 2
++#define mmCNV_CSC_C23_C24 0x021d
++#define mmCNV_CSC_C23_C24_BASE_IDX 2
++#define mmCNV_CSC_C31_C32 0x021e
++#define mmCNV_CSC_C31_C32_BASE_IDX 2
++#define mmCNV_CSC_C33_C34 0x021f
++#define mmCNV_CSC_C33_C34_BASE_IDX 2
++#define mmCNV_CSC_ROUND_OFFSET_R 0x0220
++#define mmCNV_CSC_ROUND_OFFSET_R_BASE_IDX 2
++#define mmCNV_CSC_ROUND_OFFSET_G 0x0221
++#define mmCNV_CSC_ROUND_OFFSET_G_BASE_IDX 2
++#define mmCNV_CSC_ROUND_OFFSET_B 0x0222
++#define mmCNV_CSC_ROUND_OFFSET_B_BASE_IDX 2
++#define mmCNV_CSC_CLAMP_R 0x0223
++#define mmCNV_CSC_CLAMP_R_BASE_IDX 2
++#define mmCNV_CSC_CLAMP_G 0x0224
++#define mmCNV_CSC_CLAMP_G_BASE_IDX 2
++#define mmCNV_CSC_CLAMP_B 0x0225
++#define mmCNV_CSC_CLAMP_B_BASE_IDX 2
++#define mmCNV_TEST_CNTL 0x0226
++#define mmCNV_TEST_CNTL_BASE_IDX 2
++#define mmCNV_TEST_CRC_RED 0x0227
++#define mmCNV_TEST_CRC_RED_BASE_IDX 2
++#define mmCNV_TEST_CRC_GREEN 0x0228
++#define mmCNV_TEST_CRC_GREEN_BASE_IDX 2
++#define mmCNV_TEST_CRC_BLUE 0x0229
++#define mmCNV_TEST_CRC_BLUE_BASE_IDX 2
++#define mmCNV_INPUT_SELECT 0x022d
++#define mmCNV_INPUT_SELECT_BASE_IDX 2
++#define mmWB_SOFT_RESET 0x0230
++#define mmWB_SOFT_RESET_BASE_IDX 2
++#define mmWB_WARM_UP_MODE_CTL1 0x0231
++#define mmWB_WARM_UP_MODE_CTL1_BASE_IDX 2
++#define mmWB_WARM_UP_MODE_CTL2 0x0232
++#define mmWB_WARM_UP_MODE_CTL2_BASE_IDX 2
++#define mmWBSCL_COEF_RAM_SELECT 0x0242
++#define mmWBSCL_COEF_RAM_SELECT_BASE_IDX 2
++#define mmWBSCL_COEF_RAM_TAP_DATA 0x0243
++#define mmWBSCL_COEF_RAM_TAP_DATA_BASE_IDX 2
++#define mmWBSCL_MODE 0x0244
++#define mmWBSCL_MODE_BASE_IDX 2
++#define mmWBSCL_TAP_CONTROL 0x0245
++#define mmWBSCL_TAP_CONTROL_BASE_IDX 2
++#define mmWBSCL_DEST_SIZE 0x0246
++#define mmWBSCL_DEST_SIZE_BASE_IDX 2
++#define mmWBSCL_HORZ_FILTER_SCALE_RATIO 0x0247
++#define mmWBSCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
++#define mmWBSCL_HORZ_FILTER_INIT_Y_RGB 0x0248
++#define mmWBSCL_HORZ_FILTER_INIT_Y_RGB_BASE_IDX 2
++#define mmWBSCL_HORZ_FILTER_INIT_CBCR 0x0249
++#define mmWBSCL_HORZ_FILTER_INIT_CBCR_BASE_IDX 2
++#define mmWBSCL_VERT_FILTER_SCALE_RATIO 0x024a
++#define mmWBSCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
++#define mmWBSCL_VERT_FILTER_INIT_Y_RGB 0x024b
++#define mmWBSCL_VERT_FILTER_INIT_Y_RGB_BASE_IDX 2
++#define mmWBSCL_VERT_FILTER_INIT_CBCR 0x024c
++#define mmWBSCL_VERT_FILTER_INIT_CBCR_BASE_IDX 2
++#define mmWBSCL_ROUND_OFFSET 0x024d
++#define mmWBSCL_ROUND_OFFSET_BASE_IDX 2
++#define mmWBSCL_CLAMP 0x024e
++#define mmWBSCL_CLAMP_BASE_IDX 2
++#define mmWBSCL_OVERFLOW_STATUS 0x024f
++#define mmWBSCL_OVERFLOW_STATUS_BASE_IDX 2
++#define mmWBSCL_COEF_RAM_CONFLICT_STATUS 0x0250
++#define mmWBSCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
++#define mmWBSCL_OUTSIDE_PIX_STRATEGY 0x0251
++#define mmWBSCL_OUTSIDE_PIX_STRATEGY_BASE_IDX 2
++#define mmWBSCL_TEST_CNTL 0x0252
++#define mmWBSCL_TEST_CNTL_BASE_IDX 2
++#define mmWBSCL_TEST_CRC_RED 0x0253
++#define mmWBSCL_TEST_CRC_RED_BASE_IDX 2
++#define mmWBSCL_TEST_CRC_GREEN 0x0254
++#define mmWBSCL_TEST_CRC_GREEN_BASE_IDX 2
++#define mmWBSCL_TEST_CRC_BLUE 0x0255
++#define mmWBSCL_TEST_CRC_BLUE_BASE_IDX 2
++#define mmWBSCL_BACKPRESSURE_CNT_EN 0x0256
++#define mmWBSCL_BACKPRESSURE_CNT_EN_BASE_IDX 2
++#define mmWB_MCIF_BACKPRESSURE_CNT 0x0257
++#define mmWB_MCIF_BACKPRESSURE_CNT_BASE_IDX 2
++#define mmWBSCL_RAM_SHUTDOWN 0x025a
++#define mmWBSCL_RAM_SHUTDOWN_BASE_IDX 2
++#define mmDMCU_CTRL 0x03b6
++#define mmDMCU_CTRL_BASE_IDX 2
++#define mmDMCU_STATUS 0x03b7
++#define mmDMCU_STATUS_BASE_IDX 2
++#define mmDMCU_PC_START_ADDR 0x03b8
++#define mmDMCU_PC_START_ADDR_BASE_IDX 2
++#define mmDMCU_FW_START_ADDR 0x03b9
++#define mmDMCU_FW_START_ADDR_BASE_IDX 2
++#define mmDMCU_FW_END_ADDR 0x03ba
++#define mmDMCU_FW_END_ADDR_BASE_IDX 2
++#define mmDMCU_FW_ISR_START_ADDR 0x03bb
++#define mmDMCU_FW_ISR_START_ADDR_BASE_IDX 2
++#define mmDMCU_FW_CS_HI 0x03bc
++#define mmDMCU_FW_CS_HI_BASE_IDX 2
++#define mmDMCU_FW_CS_LO 0x03bd
++#define mmDMCU_FW_CS_LO_BASE_IDX 2
++#define mmDMCU_RAM_ACCESS_CTRL 0x03be
++#define mmDMCU_RAM_ACCESS_CTRL_BASE_IDX 2
++#define mmDMCU_ERAM_WR_CTRL 0x03bf
++#define mmDMCU_ERAM_WR_CTRL_BASE_IDX 2
++#define mmDMCU_ERAM_WR_DATA 0x03c0
++#define mmDMCU_ERAM_WR_DATA_BASE_IDX 2
++#define mmDMCU_ERAM_RD_CTRL 0x03c1
++#define mmDMCU_ERAM_RD_CTRL_BASE_IDX 2
++#define mmDMCU_ERAM_RD_DATA 0x03c2
++#define mmDMCU_ERAM_RD_DATA_BASE_IDX 2
++#define mmDMCU_IRAM_WR_CTRL 0x03c3
++#define mmDMCU_IRAM_WR_CTRL_BASE_IDX 2
++#define mmDMCU_IRAM_WR_DATA 0x03c4
++#define mmDMCU_IRAM_WR_DATA_BASE_IDX 2
++#define mmDMCU_IRAM_RD_CTRL 0x03c5
++#define mmDMCU_IRAM_RD_CTRL_BASE_IDX 2
++#define mmDMCU_IRAM_RD_DATA 0x03c6
++#define mmDMCU_IRAM_RD_DATA_BASE_IDX 2
++#define mmDMCU_EVENT_TRIGGER 0x03c7
++#define mmDMCU_EVENT_TRIGGER_BASE_IDX 2
++#define mmDMCU_UC_INTERNAL_INT_STATUS 0x03c8
++#define mmDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX 2
++#define mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x03c9
++#define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX 2
++#define mmDMCU_INTERRUPT_STATUS 0x03ca
++#define mmDMCU_INTERRUPT_STATUS_BASE_IDX 2
++#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x03cb
++#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX 2
++#define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x03cc
++#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX 2
++#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x03cd
++#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX 2
++#define mmDC_DMCU_SCRATCH 0x03ce
++#define mmDC_DMCU_SCRATCH_BASE_IDX 2
++#define mmDMCU_INT_CNT 0x03cf
++#define mmDMCU_INT_CNT_BASE_IDX 2
++#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x03d0
++#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX 2
++#define mmDMCU_UC_CLK_GATING_CNTL 0x03d1
++#define mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX 2
++#define mmMASTER_COMM_DATA_REG1 0x03d2
++#define mmMASTER_COMM_DATA_REG1_BASE_IDX 2
++#define mmMASTER_COMM_DATA_REG2 0x03d3
++#define mmMASTER_COMM_DATA_REG2_BASE_IDX 2
++#define mmMASTER_COMM_DATA_REG3 0x03d4
++#define mmMASTER_COMM_DATA_REG3_BASE_IDX 2
++#define mmMASTER_COMM_CMD_REG 0x03d5
++#define mmMASTER_COMM_CMD_REG_BASE_IDX 2
++#define mmMASTER_COMM_CNTL_REG 0x03d6
++#define mmMASTER_COMM_CNTL_REG_BASE_IDX 2
++#define mmSLAVE_COMM_DATA_REG1 0x03d7
++#define mmSLAVE_COMM_DATA_REG1_BASE_IDX 2
++#define mmSLAVE_COMM_DATA_REG2 0x03d8
++#define mmSLAVE_COMM_DATA_REG2_BASE_IDX 2
++#define mmSLAVE_COMM_DATA_REG3 0x03d9
++#define mmSLAVE_COMM_DATA_REG3_BASE_IDX 2
++#define mmSLAVE_COMM_CMD_REG 0x03da
++#define mmSLAVE_COMM_CMD_REG_BASE_IDX 2
++#define mmSLAVE_COMM_CNTL_REG 0x03db
++#define mmSLAVE_COMM_CNTL_REG_BASE_IDX 2
++#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x03de
++#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 2
++#define mmBL1_PWM_USER_LEVEL 0x03df
++#define mmBL1_PWM_USER_LEVEL_BASE_IDX 2
++#define mmBL1_PWM_TARGET_ABM_LEVEL 0x03e0
++#define mmBL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 2
++#define mmBL1_PWM_CURRENT_ABM_LEVEL 0x03e1
++#define mmBL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 2
++#define mmBL1_PWM_FINAL_DUTY_CYCLE 0x03e2
++#define mmBL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 2
++#define mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x03e3
++#define mmBL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 2
++#define mmBL1_PWM_ABM_CNTL 0x03e4
++#define mmBL1_PWM_ABM_CNTL_BASE_IDX 2
++#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x03e5
++#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 2
++#define mmBL1_PWM_GRP2_REG_LOCK 0x03e6
++#define mmBL1_PWM_GRP2_REG_LOCK_BASE_IDX 2
++#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x03e7
++#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX 2
++#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x03e8
++#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX 2
++#define mmDMCU_INTERRUPT_STATUS_1 0x03e9
++#define mmDMCU_INTERRUPT_STATUS_1_BASE_IDX 2
++#define mmDMCU_DPRX_INTERRUPT_STATUS1 0x03ea
++#define mmDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX 2
++#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x03eb
++#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2
++#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x03ec
++#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2
++#define mmDC_ABM1_CNTL 0x03ee
++#define mmDC_ABM1_CNTL_BASE_IDX 2
++#define mmDC_ABM1_IPCSC_COEFF_SEL 0x03ef
++#define mmDC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 2
++#define mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x03f0
++#define mmDC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 2
++#define mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x03f1
++#define mmDC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 2
++#define mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x03f2
++#define mmDC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 2
++#define mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x03f3
++#define mmDC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 2
++#define mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x03f4
++#define mmDC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 2
++#define mmDC_ABM1_ACE_THRES_12 0x03f5
++#define mmDC_ABM1_ACE_THRES_12_BASE_IDX 2
++#define mmDC_ABM1_ACE_THRES_34 0x03f6
++#define mmDC_ABM1_ACE_THRES_34_BASE_IDX 2
++#define mmDC_ABM1_ACE_CNTL_MISC 0x03f7
++#define mmDC_ABM1_ACE_CNTL_MISC_BASE_IDX 2
++#define mmDMCU_PERFMON_INTERRUPT_STATUS5 0x03f8
++#define mmDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX 2
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x03f9
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX 2
++#define mmDMCU_PERFMON_INTERRUPT_STATUS1 0x03fa
++#define mmDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX 2
++#define mmDMCU_PERFMON_INTERRUPT_STATUS2 0x03fb
++#define mmDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX 2
++#define mmDMCU_PERFMON_INTERRUPT_STATUS3 0x03fc
++#define mmDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX 2
++#define mmDMCU_PERFMON_INTERRUPT_STATUS4 0x03fd
++#define mmDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX 2
++#define mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x0400
++#define mmDC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 2
++#define mmDC_ABM1_HG_MISC_CTRL 0x0401
++#define mmDC_ABM1_HG_MISC_CTRL_BASE_IDX 2
++#define mmDC_ABM1_LS_SUM_OF_LUMA 0x0402
++#define mmDC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 2
++#define mmDC_ABM1_LS_MIN_MAX_LUMA 0x0403
++#define mmDC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 2
++#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0404
++#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 2
++#define mmDC_ABM1_LS_PIXEL_COUNT 0x0405
++#define mmDC_ABM1_LS_PIXEL_COUNT_BASE_IDX 2
++#define mmDC_ABM1_LS_OVR_SCAN_BIN 0x0406
++#define mmDC_ABM1_LS_OVR_SCAN_BIN_BASE_IDX 2
++#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0407
++#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 2
++#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0408
++#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 2
++#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0409
++#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 2
++#define mmDC_ABM1_HG_SAMPLE_RATE 0x040a
++#define mmDC_ABM1_HG_SAMPLE_RATE_BASE_IDX 2
++#define mmDC_ABM1_LS_SAMPLE_RATE 0x040b
++#define mmDC_ABM1_LS_SAMPLE_RATE_BASE_IDX 2
++#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x040c
++#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 2
++#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x040d
++#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 2
++#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x040e
++#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 2
++#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x040f
++#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 2
++#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0410
++#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 2
++#define mmDC_ABM1_HG_RESULT_1 0x0411
++#define mmDC_ABM1_HG_RESULT_1_BASE_IDX 2
++#define mmDC_ABM1_HG_RESULT_2 0x0412
++#define mmDC_ABM1_HG_RESULT_2_BASE_IDX 2
++#define mmDC_ABM1_HG_RESULT_3 0x0413
++#define mmDC_ABM1_HG_RESULT_3_BASE_IDX 2
++#define mmDC_ABM1_HG_RESULT_4 0x0414
++#define mmDC_ABM1_HG_RESULT_4_BASE_IDX 2
++#define mmDC_ABM1_HG_RESULT_5 0x0415
++#define mmDC_ABM1_HG_RESULT_5_BASE_IDX 2
++#define mmDC_ABM1_HG_RESULT_6 0x0416
++#define mmDC_ABM1_HG_RESULT_6_BASE_IDX 2
++#define mmDC_ABM1_HG_RESULT_7 0x0417
++#define mmDC_ABM1_HG_RESULT_7_BASE_IDX 2
++#define mmDC_ABM1_HG_RESULT_8 0x0418
++#define mmDC_ABM1_HG_RESULT_8_BASE_IDX 2
++#define mmDC_ABM1_HG_RESULT_9 0x0419
++#define mmDC_ABM1_HG_RESULT_9_BASE_IDX 2
++#define mmDC_ABM1_HG_RESULT_10 0x041a
++#define mmDC_ABM1_HG_RESULT_10_BASE_IDX 2
++#define mmDC_ABM1_HG_RESULT_11 0x041b
++#define mmDC_ABM1_HG_RESULT_11_BASE_IDX 2
++#define mmDC_ABM1_HG_RESULT_12 0x041c
++#define mmDC_ABM1_HG_RESULT_12_BASE_IDX 2
++#define mmDC_ABM1_HG_RESULT_13 0x041d
++#define mmDC_ABM1_HG_RESULT_13_BASE_IDX 2
++#define mmDC_ABM1_HG_RESULT_14 0x041e
++#define mmDC_ABM1_HG_RESULT_14_BASE_IDX 2
++#define mmDC_ABM1_HG_RESULT_15 0x041f
++#define mmDC_ABM1_HG_RESULT_15_BASE_IDX 2
++#define mmDC_ABM1_HG_RESULT_16 0x0420
++#define mmDC_ABM1_HG_RESULT_16_BASE_IDX 2
++#define mmDC_ABM1_HG_RESULT_17 0x0421
++#define mmDC_ABM1_HG_RESULT_17_BASE_IDX 2
++#define mmDC_ABM1_HG_RESULT_18 0x0422
++#define mmDC_ABM1_HG_RESULT_18_BASE_IDX 2
++#define mmDC_ABM1_HG_RESULT_19 0x0423
++#define mmDC_ABM1_HG_RESULT_19_BASE_IDX 2
++#define mmDC_ABM1_HG_RESULT_20 0x0424
++#define mmDC_ABM1_HG_RESULT_20_BASE_IDX 2
++#define mmDC_ABM1_HG_RESULT_21 0x0425
++#define mmDC_ABM1_HG_RESULT_21_BASE_IDX 2
++#define mmDC_ABM1_HG_RESULT_22 0x0426
++#define mmDC_ABM1_HG_RESULT_22_BASE_IDX 2
++#define mmDC_ABM1_HG_RESULT_23 0x0427
++#define mmDC_ABM1_HG_RESULT_23_BASE_IDX 2
++#define mmDC_ABM1_HG_RESULT_24 0x0428
++#define mmDC_ABM1_HG_RESULT_24_BASE_IDX 2
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x0429
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX 2
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x042a
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x042b
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX 2
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x042c
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX 2
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x042d
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX 2
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x042e
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x042f
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX 2
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x0430
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX 2
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x0431
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX 2
++#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE 0x0451
++#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE_BASE_IDX 2
++#define mmDC_ABM1_BL_MASTER_LOCK 0x0452
++#define mmDC_ABM1_BL_MASTER_LOCK_BASE_IDX 2
++#define mmAZALIA_CONTROLLER_CLOCK_GATING 0x04bc
++#define mmAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2
++#define mmAZALIA_AUDIO_DTO 0x04bd
++#define mmAZALIA_AUDIO_DTO_BASE_IDX 2
++#define mmAZALIA_AUDIO_DTO_CONTROL 0x04be
++#define mmAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2
++#define mmAZALIA_SOCCLK_CONTROL 0x04bf
++#define mmAZALIA_SOCCLK_CONTROL_BASE_IDX 2
++#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x04c0
++#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2
++#define mmAZALIA_DATA_DMA_CONTROL 0x04c1
++#define mmAZALIA_DATA_DMA_CONTROL_BASE_IDX 2
++#define mmAZALIA_BDL_DMA_CONTROL 0x04c2
++#define mmAZALIA_BDL_DMA_CONTROL_BASE_IDX 2
++#define mmAZALIA_RIRB_AND_DP_CONTROL 0x04c3
++#define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2
++#define mmAZALIA_CORB_DMA_CONTROL 0x04c4
++#define mmAZALIA_CORB_DMA_CONTROL_BASE_IDX 2
++#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x04cb
++#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX 2
++#define mmAZALIA_CYCLIC_BUFFER_SYNC 0x04cc
++#define mmAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX 2
++#define mmAZALIA_GLOBAL_CAPABILITIES 0x04cd
++#define mmAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2
++#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x04ce
++#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2
++#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x04cf
++#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2
++#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x04d0
++#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2
++#define mmAZALIA_INPUT_CRC0_CONTROL0 0x04d3
++#define mmAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2
++#define mmAZALIA_INPUT_CRC0_CONTROL1 0x04d4
++#define mmAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2
++#define mmAZALIA_INPUT_CRC0_CONTROL2 0x04d5
++#define mmAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2
++#define mmAZALIA_INPUT_CRC0_CONTROL3 0x04d6
++#define mmAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2
++#define mmAZALIA_INPUT_CRC0_RESULT 0x04d7
++#define mmAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2
++#define mmAZALIA_INPUT_CRC1_CONTROL0 0x04d8
++#define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2
++#define mmAZALIA_INPUT_CRC1_CONTROL1 0x04d9
++#define mmAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2
++#define mmAZALIA_INPUT_CRC1_CONTROL2 0x04da
++#define mmAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2
++#define mmAZALIA_INPUT_CRC1_CONTROL3 0x04db
++#define mmAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2
++#define mmAZALIA_INPUT_CRC1_RESULT 0x04dc
++#define mmAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2
++#define mmAZALIA_CRC0_CONTROL0 0x04dd
++#define mmAZALIA_CRC0_CONTROL0_BASE_IDX 2
++#define mmAZALIA_CRC0_CONTROL1 0x04de
++#define mmAZALIA_CRC0_CONTROL1_BASE_IDX 2
++#define mmAZALIA_CRC0_CONTROL2 0x04df
++#define mmAZALIA_CRC0_CONTROL2_BASE_IDX 2
++#define mmAZALIA_CRC0_CONTROL3 0x04e0
++#define mmAZALIA_CRC0_CONTROL3_BASE_IDX 2
++#define mmAZALIA_CRC0_RESULT 0x04e1
++#define mmAZALIA_CRC0_RESULT_BASE_IDX 2
++#define mmAZALIA_CRC1_CONTROL0 0x04e2
++#define mmAZALIA_CRC1_CONTROL0_BASE_IDX 2
++#define mmAZALIA_CRC1_CONTROL1 0x04e3
++#define mmAZALIA_CRC1_CONTROL1_BASE_IDX 2
++#define mmAZALIA_CRC1_CONTROL2 0x04e4
++#define mmAZALIA_CRC1_CONTROL2_BASE_IDX 2
++#define mmAZALIA_CRC1_CONTROL3 0x04e5
++#define mmAZALIA_CRC1_CONTROL3_BASE_IDX 2
++#define mmAZALIA_CRC1_RESULT 0x04e6
++#define mmAZALIA_CRC1_RESULT_BASE_IDX 2
++#define mmAZALIA_MEM_PWR_CTRL 0x04e8
++#define mmAZALIA_MEM_PWR_CTRL_BASE_IDX 2
++#define mmAZALIA_MEM_PWR_STATUS 0x04e9
++#define mmAZALIA_MEM_PWR_STATUS_BASE_IDX 2
++#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0500
++#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2
++#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0501
++#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2
++#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0502
++#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2
++#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0503
++#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2
++#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x0504
++#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2
++#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x0505
++#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2
++#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x0506
++#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2
++#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x0507
++#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2
++#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x0508
++#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2
++#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x0509
++#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2
++#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x050a
++#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2
++#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x050b
++#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2
++#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x050c
++#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2
++#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x050d
++#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2
++#define mmAZALIA_F0_GTC_GROUP_OFFSET0 0x050f
++#define mmAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX 2
++#define mmAZALIA_F0_GTC_GROUP_OFFSET1 0x0510
++#define mmAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX 2
++#define mmAZALIA_F0_GTC_GROUP_OFFSET2 0x0511
++#define mmAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX 2
++#define mmAZALIA_F0_GTC_GROUP_OFFSET3 0x0512
++#define mmAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX 2
++#define mmAZALIA_F0_GTC_GROUP_OFFSET4 0x0513
++#define mmAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX 2
++#define mmAZALIA_F0_GTC_GROUP_OFFSET5 0x0514
++#define mmAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX 2
++#define mmAZALIA_F0_GTC_GROUP_OFFSET6 0x0515
++#define mmAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX 2
++#define mmREG_DC_AUDIO_PORT_CONNECTIVITY 0x0516
++#define mmREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2
++#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0517
++#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2
++#define mmDAC_ENABLE 0x155a
++#define mmDAC_ENABLE_BASE_IDX 2
++#define mmDAC_SOURCE_SELECT 0x155b
++#define mmDAC_SOURCE_SELECT_BASE_IDX 2
++#define mmDAC_CRC_EN 0x155c
++#define mmDAC_CRC_EN_BASE_IDX 2
++#define mmDAC_CRC_CONTROL 0x155d
++#define mmDAC_CRC_CONTROL_BASE_IDX 2
++#define mmDAC_CRC_SIG_RGB_MASK 0x155e
++#define mmDAC_CRC_SIG_RGB_MASK_BASE_IDX 2
++#define mmDAC_CRC_SIG_CONTROL_MASK 0x155f
++#define mmDAC_CRC_SIG_CONTROL_MASK_BASE_IDX 2
++#define mmDAC_CRC_SIG_RGB 0x1560
++#define mmDAC_CRC_SIG_RGB_BASE_IDX 2
++#define mmDAC_CRC_SIG_CONTROL 0x1561
++#define mmDAC_CRC_SIG_CONTROL_BASE_IDX 2
++#define mmDAC_SYNC_TRISTATE_CONTROL 0x1562
++#define mmDAC_SYNC_TRISTATE_CONTROL_BASE_IDX 2
++#define mmDAC_STEREOSYNC_SELECT 0x1563
++#define mmDAC_STEREOSYNC_SELECT_BASE_IDX 2
++#define mmDAC_AUTODETECT_CONTROL 0x1564
++#define mmDAC_AUTODETECT_CONTROL_BASE_IDX 2
++#define mmDAC_AUTODETECT_CONTROL2 0x1565
++#define mmDAC_AUTODETECT_CONTROL2_BASE_IDX 2
++#define mmDAC_AUTODETECT_CONTROL3 0x1566
++#define mmDAC_AUTODETECT_CONTROL3_BASE_IDX 2
++#define mmDAC_AUTODETECT_STATUS 0x1567
++#define mmDAC_AUTODETECT_STATUS_BASE_IDX 2
++#define mmDAC_AUTODETECT_INT_CONTROL 0x1568
++#define mmDAC_AUTODETECT_INT_CONTROL_BASE_IDX 2
++#define mmDAC_FORCE_OUTPUT_CNTL 0x1569
++#define mmDAC_FORCE_OUTPUT_CNTL_BASE_IDX 2
++#define mmDAC_FORCE_DATA 0x156a
++#define mmDAC_FORCE_DATA_BASE_IDX 2
++#define mmDAC_POWERDOWN 0x156b
++#define mmDAC_POWERDOWN_BASE_IDX 2
++#define mmDAC_CONTROL 0x156c
++#define mmDAC_CONTROL_BASE_IDX 2
++#define mmDAC_COMPARATOR_ENABLE 0x156d
++#define mmDAC_COMPARATOR_ENABLE_BASE_IDX 2
++#define mmDAC_COMPARATOR_OUTPUT 0x156e
++#define mmDAC_COMPARATOR_OUTPUT_BASE_IDX 2
++#define mmDAC_PWR_CNTL 0x156f
++#define mmDAC_PWR_CNTL_BASE_IDX 2
++#define mmDAC_DFT_CONFIG 0x1570
++#define mmDAC_DFT_CONFIG_BASE_IDX 2
++#define mmDAC_FIFO_STATUS 0x1571
++#define mmDAC_FIFO_STATUS_BASE_IDX 2
++#define mmDC_I2C_CONTROL 0x1584
++#define mmDC_I2C_CONTROL_BASE_IDX 2
++#define mmDC_I2C_ARBITRATION 0x1585
++#define mmDC_I2C_ARBITRATION_BASE_IDX 2
++#define mmDC_I2C_INTERRUPT_CONTROL 0x1586
++#define mmDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmDC_I2C_SW_STATUS 0x1587
++#define mmDC_I2C_SW_STATUS_BASE_IDX 2
++#define mmDC_I2C_DDC1_HW_STATUS 0x1588
++#define mmDC_I2C_DDC1_HW_STATUS_BASE_IDX 2
++#define mmDC_I2C_DDC2_HW_STATUS 0x1589
++#define mmDC_I2C_DDC2_HW_STATUS_BASE_IDX 2
++#define mmDC_I2C_DDC3_HW_STATUS 0x158a
++#define mmDC_I2C_DDC3_HW_STATUS_BASE_IDX 2
++#define mmDC_I2C_DDC4_HW_STATUS 0x158b
++#define mmDC_I2C_DDC4_HW_STATUS_BASE_IDX 2
++#define mmDC_I2C_DDC5_HW_STATUS 0x158c
++#define mmDC_I2C_DDC5_HW_STATUS_BASE_IDX 2
++#define mmDC_I2C_DDC6_HW_STATUS 0x158d
++#define mmDC_I2C_DDC6_HW_STATUS_BASE_IDX 2
++#define mmDC_I2C_DDC1_SPEED 0x158e
++#define mmDC_I2C_DDC1_SPEED_BASE_IDX 2
++#define mmDC_I2C_DDC1_SETUP 0x158f
++#define mmDC_I2C_DDC1_SETUP_BASE_IDX 2
++#define mmDC_I2C_DDC2_SPEED 0x1590
++#define mmDC_I2C_DDC2_SPEED_BASE_IDX 2
++#define mmDC_I2C_DDC2_SETUP 0x1591
++#define mmDC_I2C_DDC2_SETUP_BASE_IDX 2
++#define mmDC_I2C_DDC3_SPEED 0x1592
++#define mmDC_I2C_DDC3_SPEED_BASE_IDX 2
++#define mmDC_I2C_DDC3_SETUP 0x1593
++#define mmDC_I2C_DDC3_SETUP_BASE_IDX 2
++#define mmDC_I2C_DDC4_SPEED 0x1594
++#define mmDC_I2C_DDC4_SPEED_BASE_IDX 2
++#define mmDC_I2C_DDC4_SETUP 0x1595
++#define mmDC_I2C_DDC4_SETUP_BASE_IDX 2
++#define mmDC_I2C_DDC5_SPEED 0x1596
++#define mmDC_I2C_DDC5_SPEED_BASE_IDX 2
++#define mmDC_I2C_DDC5_SETUP 0x1597
++#define mmDC_I2C_DDC5_SETUP_BASE_IDX 2
++#define mmDC_I2C_DDC6_SPEED 0x1598
++#define mmDC_I2C_DDC6_SPEED_BASE_IDX 2
++#define mmDC_I2C_DDC6_SETUP 0x1599
++#define mmDC_I2C_DDC6_SETUP_BASE_IDX 2
++#define mmDC_I2C_TRANSACTION0 0x159a
++#define mmDC_I2C_TRANSACTION0_BASE_IDX 2
++#define mmDC_I2C_TRANSACTION1 0x159b
++#define mmDC_I2C_TRANSACTION1_BASE_IDX 2
++#define mmDC_I2C_TRANSACTION2 0x159c
++#define mmDC_I2C_TRANSACTION2_BASE_IDX 2
++#define mmDC_I2C_TRANSACTION3 0x159d
++#define mmDC_I2C_TRANSACTION3_BASE_IDX 2
++#define mmDC_I2C_DATA 0x159e
++#define mmDC_I2C_DATA_BASE_IDX 2
++#define mmDC_I2C_DDCVGA_HW_STATUS 0x159f
++#define mmDC_I2C_DDCVGA_HW_STATUS_BASE_IDX 2
++#define mmDC_I2C_DDCVGA_SPEED 0x15a0
++#define mmDC_I2C_DDCVGA_SPEED_BASE_IDX 2
++#define mmDC_I2C_DDCVGA_SETUP 0x15a1
++#define mmDC_I2C_DDCVGA_SETUP_BASE_IDX 2
++#define mmDC_I2C_EDID_DETECT_CTRL 0x15a2
++#define mmDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2
++#define mmDC_I2C_READ_REQUEST_INTERRUPT 0x15a3
++#define mmDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2
++#define mmGENERIC_I2C_CONTROL 0x15a4
++#define mmGENERIC_I2C_CONTROL_BASE_IDX 2
++#define mmGENERIC_I2C_INTERRUPT_CONTROL 0x15a5
++#define mmGENERIC_I2C_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmGENERIC_I2C_STATUS 0x15a6
++#define mmGENERIC_I2C_STATUS_BASE_IDX 2
++#define mmGENERIC_I2C_SPEED 0x15a7
++#define mmGENERIC_I2C_SPEED_BASE_IDX 2
++#define mmGENERIC_I2C_SETUP 0x15a8
++#define mmGENERIC_I2C_SETUP_BASE_IDX 2
++#define mmGENERIC_I2C_TRANSACTION 0x15a9
++#define mmGENERIC_I2C_TRANSACTION_BASE_IDX 2
++#define mmGENERIC_I2C_DATA 0x15aa
++#define mmGENERIC_I2C_DATA_BASE_IDX 2
++#define mmGENERIC_I2C_PIN_SELECTION 0x15ab
++#define mmGENERIC_I2C_PIN_SELECTION_BASE_IDX 2
++#define mmDCO_SCRATCH0 0x15b6
++#define mmDCO_SCRATCH0_BASE_IDX 2
++#define mmDCO_SCRATCH1 0x15b7
++#define mmDCO_SCRATCH1_BASE_IDX 2
++#define mmDCO_SCRATCH2 0x15b8
++#define mmDCO_SCRATCH2_BASE_IDX 2
++#define mmDCO_SCRATCH3 0x15b9
++#define mmDCO_SCRATCH3_BASE_IDX 2
++#define mmDCO_SCRATCH4 0x15ba
++#define mmDCO_SCRATCH4_BASE_IDX 2
++#define mmDCO_SCRATCH5 0x15bb
++#define mmDCO_SCRATCH5_BASE_IDX 2
++#define mmDCO_SCRATCH6 0x15bc
++#define mmDCO_SCRATCH6_BASE_IDX 2
++#define mmDCO_SCRATCH7 0x15bd
++#define mmDCO_SCRATCH7_BASE_IDX 2
++#define mmDCE_VCE_CONTROL 0x15be
++#define mmDCE_VCE_CONTROL_BASE_IDX 2
++#define mmDISP_INTERRUPT_STATUS 0x15bf
++#define mmDISP_INTERRUPT_STATUS_BASE_IDX 2
++#define mmDISP_INTERRUPT_STATUS_CONTINUE 0x15c0
++#define mmDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2
++#define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x15c1
++#define mmDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2
++#define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x15c2
++#define mmDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2
++#define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x15c3
++#define mmDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2
++#define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x15c4
++#define mmDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2
++#define mmDISP_INTERRUPT_STATUS_CONTINUE6 0x15c5
++#define mmDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2
++#define mmDISP_INTERRUPT_STATUS_CONTINUE7 0x15c6
++#define mmDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2
++#define mmDISP_INTERRUPT_STATUS_CONTINUE8 0x15c7
++#define mmDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2
++#define mmDISP_INTERRUPT_STATUS_CONTINUE9 0x15c8
++#define mmDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2
++#define mmDCO_MEM_PWR_STATUS 0x15c9
++#define mmDCO_MEM_PWR_STATUS_BASE_IDX 2
++#define mmDCO_MEM_PWR_CTRL 0x15ca
++#define mmDCO_MEM_PWR_CTRL_BASE_IDX 2
++#define mmDCO_MEM_PWR_CTRL2 0x15cb
++#define mmDCO_MEM_PWR_CTRL2_BASE_IDX 2
++#define mmDCO_CLK_CNTL 0x15cc
++#define mmDCO_CLK_CNTL_BASE_IDX 2
++#define mmDCO_POWER_MANAGEMENT_CNTL 0x15d0
++#define mmDCO_POWER_MANAGEMENT_CNTL_BASE_IDX 2
++#define mmDIG_SOFT_RESET_2 0x15d2
++#define mmDIG_SOFT_RESET_2_BASE_IDX 2
++#define mmDCO_STEREOSYNC_SEL 0x15d6
++#define mmDCO_STEREOSYNC_SEL_BASE_IDX 2
++#define mmDCO_SOFT_RESET 0x15d9
++#define mmDCO_SOFT_RESET_BASE_IDX 2
++#define mmDIG_SOFT_RESET 0x15da
++#define mmDIG_SOFT_RESET_BASE_IDX 2
++#define mmDCO_MEM_PWR_STATUS1 0x15dc
++#define mmDCO_MEM_PWR_STATUS1_BASE_IDX 2
++#define mmDISP_INTERRUPT_STATUS_CONTINUE10 0x15dd
++#define mmDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2
++#define mmDCO_CLK_CNTL2 0x15de
++#define mmDCO_CLK_CNTL2_BASE_IDX 2
++#define mmDCO_CLK_CNTL3 0x15df
++#define mmDCO_CLK_CNTL3_BASE_IDX 2
++#define mmDCO_HDMI_RXSTATUS_TIMER_CONTROL 0x15eb
++#define mmDCO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2
++#define mmDCO_PSP_INTERRUPT_STATUS 0x15ec
++#define mmDCO_PSP_INTERRUPT_STATUS_BASE_IDX 2
++#define mmDCO_PSP_INTERRUPT_CLEAR 0x15ed
++#define mmDCO_PSP_INTERRUPT_CLEAR_BASE_IDX 2
++#define mmDCO_GENERIC_INTERRUPT_MESSAGE 0x15ee
++#define mmDCO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX 2
++#define mmDCO_GENERIC_INTERRUPT_CLEAR 0x15ef
++#define mmDCO_GENERIC_INTERRUPT_CLEAR_BASE_IDX 2
++#define mmFMT_MEMORY0_CONTROL 0x15f0
++#define mmFMT_MEMORY0_CONTROL_BASE_IDX 2
++#define mmFMT_MEMORY1_CONTROL 0x15f1
++#define mmFMT_MEMORY1_CONTROL_BASE_IDX 2
++#define mmFMT_MEMORY2_CONTROL 0x15f2
++#define mmFMT_MEMORY2_CONTROL_BASE_IDX 2
++#define mmFMT_MEMORY3_CONTROL 0x15f3
++#define mmFMT_MEMORY3_CONTROL_BASE_IDX 2
++#define mmFMT_MEMORY4_CONTROL 0x15f4
++#define mmFMT_MEMORY4_CONTROL_BASE_IDX 2
++#define mmFMT_MEMORY5_CONTROL 0x15f5
++#define mmFMT_MEMORY5_CONTROL_BASE_IDX 2
++#define mmDISP_INTERRUPT_STATUS_CONTINUE11 0x15f6
++#define mmDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2
++#define mmDC_GENERICA 0x207e
++#define mmDC_GENERICA_BASE_IDX 2
++#define mmDC_GENERICB 0x207f
++#define mmDC_GENERICB_BASE_IDX 2
++#define mmDC_PAD_EXTERN_SIG 0x2080
++#define mmDC_PAD_EXTERN_SIG_BASE_IDX 2
++#define mmDC_REF_CLK_CNTL 0x2081
++#define mmDC_REF_CLK_CNTL_BASE_IDX 2
++#define mmDC_GPIO_DEBUG 0x2082
++#define mmDC_GPIO_DEBUG_BASE_IDX 2
++#define mmUNIPHYA_LINK_CNTL 0x2083
++#define mmUNIPHYA_LINK_CNTL_BASE_IDX 2
++#define mmUNIPHYA_CHANNEL_XBAR_CNTL 0x2084
++#define mmUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2
++#define mmUNIPHYB_LINK_CNTL 0x2085
++#define mmUNIPHYB_LINK_CNTL_BASE_IDX 2
++#define mmUNIPHYB_CHANNEL_XBAR_CNTL 0x2086
++#define mmUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2
++#define mmUNIPHYC_LINK_CNTL 0x2087
++#define mmUNIPHYC_LINK_CNTL_BASE_IDX 2
++#define mmUNIPHYC_CHANNEL_XBAR_CNTL 0x2088
++#define mmUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2
++#define mmUNIPHYD_LINK_CNTL 0x2089
++#define mmUNIPHYD_LINK_CNTL_BASE_IDX 2
++#define mmUNIPHYD_CHANNEL_XBAR_CNTL 0x208a
++#define mmUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2
++#define mmUNIPHYE_LINK_CNTL 0x208b
++#define mmUNIPHYE_LINK_CNTL_BASE_IDX 2
++#define mmUNIPHYE_CHANNEL_XBAR_CNTL 0x208c
++#define mmUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2
++#define mmUNIPHYF_LINK_CNTL 0x208d
++#define mmUNIPHYF_LINK_CNTL_BASE_IDX 2
++#define mmUNIPHYF_CHANNEL_XBAR_CNTL 0x208e
++#define mmUNIPHYF_CHANNEL_XBAR_CNTL_BASE_IDX 2
++#define mmUNIPHYG_LINK_CNTL 0x208f
++#define mmUNIPHYG_LINK_CNTL_BASE_IDX 2
++#define mmUNIPHYG_CHANNEL_XBAR_CNTL 0x2090
++#define mmUNIPHYG_CHANNEL_XBAR_CNTL_BASE_IDX 2
++#define mmDCIO_WRCMD_DELAY 0x2094
++#define mmDCIO_WRCMD_DELAY_BASE_IDX 2
++#define mmDC_DVODATA_CONFIG 0x2098
++#define mmDC_DVODATA_CONFIG_BASE_IDX 2
++#define mmLVTMA_PWRSEQ_CNTL 0x2099
++#define mmLVTMA_PWRSEQ_CNTL_BASE_IDX 2
++#define mmLVTMA_PWRSEQ_STATE 0x209a
++#define mmLVTMA_PWRSEQ_STATE_BASE_IDX 2
++#define mmLVTMA_PWRSEQ_REF_DIV 0x209b
++#define mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX 2
++#define mmLVTMA_PWRSEQ_DELAY1 0x209c
++#define mmLVTMA_PWRSEQ_DELAY1_BASE_IDX 2
++#define mmLVTMA_PWRSEQ_DELAY2 0x209d
++#define mmLVTMA_PWRSEQ_DELAY2_BASE_IDX 2
++#define mmBL_PWM_CNTL 0x209e
++#define mmBL_PWM_CNTL_BASE_IDX 2
++#define mmBL_PWM_CNTL2 0x209f
++#define mmBL_PWM_CNTL2_BASE_IDX 2
++#define mmBL_PWM_PERIOD_CNTL 0x20a0
++#define mmBL_PWM_PERIOD_CNTL_BASE_IDX 2
++#define mmBL_PWM_GRP1_REG_LOCK 0x20a1
++#define mmBL_PWM_GRP1_REG_LOCK_BASE_IDX 2
++#define mmDCIO_GSL_GENLK_PAD_CNTL 0x20a2
++#define mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2
++#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x20a3
++#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2
++#define mmDCIO_GSL0_CNTL 0x20a4
++#define mmDCIO_GSL0_CNTL_BASE_IDX 2
++#define mmDCIO_GSL1_CNTL 0x20a5
++#define mmDCIO_GSL1_CNTL_BASE_IDX 2
++#define mmDCIO_GSL2_CNTL 0x20a6
++#define mmDCIO_GSL2_CNTL_BASE_IDX 2
++#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x20a7
++#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2
++#define mmDC_GPU_TIMER_START_POSITION_P_FLIP 0x20a8
++#define mmDC_GPU_TIMER_START_POSITION_P_FLIP_BASE_IDX 2
++#define mmDC_GPU_TIMER_READ 0x20a9
++#define mmDC_GPU_TIMER_READ_BASE_IDX 2
++#define mmDC_GPU_TIMER_READ_CNTL 0x20aa
++#define mmDC_GPU_TIMER_READ_CNTL_BASE_IDX 2
++#define mmDCIO_CLOCK_CNTL 0x20ab
++#define mmDCIO_CLOCK_CNTL_BASE_IDX 2
++#define mmDCO_DCFE_EXT_VSYNC_CNTL 0x20ae
++#define mmDCO_DCFE_EXT_VSYNC_CNTL_BASE_IDX 2
++#define mmDCIO_SOFT_RESET 0x20b4
++#define mmDCIO_SOFT_RESET_BASE_IDX 2
++#define mmDCIO_DPHY_SEL 0x20b5
++#define mmDCIO_DPHY_SEL_BASE_IDX 2
++#define mmUNIPHY_IMPCAL_LINKA 0x20b6
++#define mmUNIPHY_IMPCAL_LINKA_BASE_IDX 2
++#define mmUNIPHY_IMPCAL_LINKB 0x20b7
++#define mmUNIPHY_IMPCAL_LINKB_BASE_IDX 2
++#define mmUNIPHY_IMPCAL_PERIOD 0x20b8
++#define mmUNIPHY_IMPCAL_PERIOD_BASE_IDX 2
++#define mmAUXP_IMPCAL 0x20b9
++#define mmAUXP_IMPCAL_BASE_IDX 2
++#define mmAUXN_IMPCAL 0x20ba
++#define mmAUXN_IMPCAL_BASE_IDX 2
++#define mmDCIO_IMPCAL_CNTL 0x20bb
++#define mmDCIO_IMPCAL_CNTL_BASE_IDX 2
++#define mmUNIPHY_IMPCAL_PSW_AB 0x20bc
++#define mmUNIPHY_IMPCAL_PSW_AB_BASE_IDX 2
++#define mmUNIPHY_IMPCAL_LINKC 0x20bd
++#define mmUNIPHY_IMPCAL_LINKC_BASE_IDX 2
++#define mmUNIPHY_IMPCAL_LINKD 0x20be
++#define mmUNIPHY_IMPCAL_LINKD_BASE_IDX 2
++#define mmDCIO_IMPCAL_CNTL_CD 0x20bf
++#define mmDCIO_IMPCAL_CNTL_CD_BASE_IDX 2
++#define mmUNIPHY_IMPCAL_PSW_CD 0x20c0
++#define mmUNIPHY_IMPCAL_PSW_CD_BASE_IDX 2
++#define mmUNIPHY_IMPCAL_LINKE 0x20c1
++#define mmUNIPHY_IMPCAL_LINKE_BASE_IDX 2
++#define mmUNIPHY_IMPCAL_LINKF 0x20c2
++#define mmUNIPHY_IMPCAL_LINKF_BASE_IDX 2
++#define mmDCIO_IMPCAL_CNTL_EF 0x20c3
++#define mmDCIO_IMPCAL_CNTL_EF_BASE_IDX 2
++#define mmUNIPHY_IMPCAL_PSW_EF 0x20c4
++#define mmUNIPHY_IMPCAL_PSW_EF_BASE_IDX 2
++#define mmUNIPHYLPA_LINK_CNTL 0x20c5
++#define mmUNIPHYLPA_LINK_CNTL_BASE_IDX 2
++#define mmUNIPHYLPB_LINK_CNTL 0x20c6
++#define mmUNIPHYLPB_LINK_CNTL_BASE_IDX 2
++#define mmUNIPHYLPA_CHANNEL_XBAR_CNTL 0x20c7
++#define mmUNIPHYLPA_CHANNEL_XBAR_CNTL_BASE_IDX 2
++#define mmUNIPHYLPB_CHANNEL_XBAR_CNTL 0x20c8
++#define mmUNIPHYLPB_CHANNEL_XBAR_CNTL_BASE_IDX 2
++#define mmDCIO_DPCS_TX_INTERRUPT 0x20c9
++#define mmDCIO_DPCS_TX_INTERRUPT_BASE_IDX 2
++#define mmDCIO_DPCS_RX_INTERRUPT 0x20ca
++#define mmDCIO_DPCS_RX_INTERRUPT_BASE_IDX 2
++#define mmDCIO_SEMAPHORE0 0x20cb
++#define mmDCIO_SEMAPHORE0_BASE_IDX 2
++#define mmDCIO_SEMAPHORE1 0x20cc
++#define mmDCIO_SEMAPHORE1_BASE_IDX 2
++#define mmDCIO_SEMAPHORE2 0x20cd
++#define mmDCIO_SEMAPHORE2_BASE_IDX 2
++#define mmDCIO_SEMAPHORE3 0x20ce
++#define mmDCIO_SEMAPHORE3_BASE_IDX 2
++#define mmDCIO_SEMAPHORE4 0x20cf
++#define mmDCIO_SEMAPHORE4_BASE_IDX 2
++#define mmDCIO_SEMAPHORE5 0x20d0
++#define mmDCIO_SEMAPHORE5_BASE_IDX 2
++#define mmDCIO_SEMAPHORE6 0x20d1
++#define mmDCIO_SEMAPHORE6_BASE_IDX 2
++#define mmDCIO_SEMAPHORE7 0x20d2
++#define mmDCIO_SEMAPHORE7_BASE_IDX 2
++#define mmDC_GPIO_GENERIC_MASK 0x20de
++#define mmDC_GPIO_GENERIC_MASK_BASE_IDX 2
++#define mmDC_GPIO_GENERIC_A 0x20df
++#define mmDC_GPIO_GENERIC_A_BASE_IDX 2
++#define mmDC_GPIO_GENERIC_EN 0x20e0
++#define mmDC_GPIO_GENERIC_EN_BASE_IDX 2
++#define mmDC_GPIO_GENERIC_Y 0x20e1
++#define mmDC_GPIO_GENERIC_Y_BASE_IDX 2
++#define mmDC_GPIO_DVODATA_MASK 0x20e2
++#define mmDC_GPIO_DVODATA_MASK_BASE_IDX 2
++#define mmDC_GPIO_DVODATA_A 0x20e3
++#define mmDC_GPIO_DVODATA_A_BASE_IDX 2
++#define mmDC_GPIO_DVODATA_EN 0x20e4
++#define mmDC_GPIO_DVODATA_EN_BASE_IDX 2
++#define mmDC_GPIO_DVODATA_Y 0x20e5
++#define mmDC_GPIO_DVODATA_Y_BASE_IDX 2
++#define mmDC_GPIO_DDC1_MASK 0x20e6
++#define mmDC_GPIO_DDC1_MASK_BASE_IDX 2
++#define mmDC_GPIO_DDC1_A 0x20e7
++#define mmDC_GPIO_DDC1_A_BASE_IDX 2
++#define mmDC_GPIO_DDC1_EN 0x20e8
++#define mmDC_GPIO_DDC1_EN_BASE_IDX 2
++#define mmDC_GPIO_DDC1_Y 0x20e9
++#define mmDC_GPIO_DDC1_Y_BASE_IDX 2
++#define mmDC_GPIO_DDC2_MASK 0x20ea
++#define mmDC_GPIO_DDC2_MASK_BASE_IDX 2
++#define mmDC_GPIO_DDC2_A 0x20eb
++#define mmDC_GPIO_DDC2_A_BASE_IDX 2
++#define mmDC_GPIO_DDC2_EN 0x20ec
++#define mmDC_GPIO_DDC2_EN_BASE_IDX 2
++#define mmDC_GPIO_DDC2_Y 0x20ed
++#define mmDC_GPIO_DDC2_Y_BASE_IDX 2
++#define mmDC_GPIO_DDC3_MASK 0x20ee
++#define mmDC_GPIO_DDC3_MASK_BASE_IDX 2
++#define mmDC_GPIO_DDC3_A 0x20ef
++#define mmDC_GPIO_DDC3_A_BASE_IDX 2
++#define mmDC_GPIO_DDC3_EN 0x20f0
++#define mmDC_GPIO_DDC3_EN_BASE_IDX 2
++#define mmDC_GPIO_DDC3_Y 0x20f1
++#define mmDC_GPIO_DDC3_Y_BASE_IDX 2
++#define mmDC_GPIO_DDC4_MASK 0x20f2
++#define mmDC_GPIO_DDC4_MASK_BASE_IDX 2
++#define mmDC_GPIO_DDC4_A 0x20f3
++#define mmDC_GPIO_DDC4_A_BASE_IDX 2
++#define mmDC_GPIO_DDC4_EN 0x20f4
++#define mmDC_GPIO_DDC4_EN_BASE_IDX 2
++#define mmDC_GPIO_DDC4_Y 0x20f5
++#define mmDC_GPIO_DDC4_Y_BASE_IDX 2
++#define mmDC_GPIO_DDC5_MASK 0x20f6
++#define mmDC_GPIO_DDC5_MASK_BASE_IDX 2
++#define mmDC_GPIO_DDC5_A 0x20f7
++#define mmDC_GPIO_DDC5_A_BASE_IDX 2
++#define mmDC_GPIO_DDC5_EN 0x20f8
++#define mmDC_GPIO_DDC5_EN_BASE_IDX 2
++#define mmDC_GPIO_DDC5_Y 0x20f9
++#define mmDC_GPIO_DDC5_Y_BASE_IDX 2
++#define mmDC_GPIO_DDC6_MASK 0x20fa
++#define mmDC_GPIO_DDC6_MASK_BASE_IDX 2
++#define mmDC_GPIO_DDC6_A 0x20fb
++#define mmDC_GPIO_DDC6_A_BASE_IDX 2
++#define mmDC_GPIO_DDC6_EN 0x20fc
++#define mmDC_GPIO_DDC6_EN_BASE_IDX 2
++#define mmDC_GPIO_DDC6_Y 0x20fd
++#define mmDC_GPIO_DDC6_Y_BASE_IDX 2
++#define mmDC_GPIO_DDCVGA_MASK 0x20fe
++#define mmDC_GPIO_DDCVGA_MASK_BASE_IDX 2
++#define mmDC_GPIO_DDCVGA_A 0x20ff
++#define mmDC_GPIO_DDCVGA_A_BASE_IDX 2
++#define mmDC_GPIO_DDCVGA_EN 0x2100
++#define mmDC_GPIO_DDCVGA_EN_BASE_IDX 2
++#define mmDC_GPIO_DDCVGA_Y 0x2101
++#define mmDC_GPIO_DDCVGA_Y_BASE_IDX 2
++#define mmDC_GPIO_SYNCA_MASK 0x2102
++#define mmDC_GPIO_SYNCA_MASK_BASE_IDX 2
++#define mmDC_GPIO_SYNCA_A 0x2103
++#define mmDC_GPIO_SYNCA_A_BASE_IDX 2
++#define mmDC_GPIO_SYNCA_EN 0x2104
++#define mmDC_GPIO_SYNCA_EN_BASE_IDX 2
++#define mmDC_GPIO_SYNCA_Y 0x2105
++#define mmDC_GPIO_SYNCA_Y_BASE_IDX 2
++#define mmDC_GPIO_GENLK_MASK 0x2106
++#define mmDC_GPIO_GENLK_MASK_BASE_IDX 2
++#define mmDC_GPIO_GENLK_A 0x2107
++#define mmDC_GPIO_GENLK_A_BASE_IDX 2
++#define mmDC_GPIO_GENLK_EN 0x2108
++#define mmDC_GPIO_GENLK_EN_BASE_IDX 2
++#define mmDC_GPIO_GENLK_Y 0x2109
++#define mmDC_GPIO_GENLK_Y_BASE_IDX 2
++#define mmDC_GPIO_HPD_MASK 0x210a
++#define mmDC_GPIO_HPD_MASK_BASE_IDX 2
++#define mmDC_GPIO_HPD_A 0x210b
++#define mmDC_GPIO_HPD_A_BASE_IDX 2
++#define mmDC_GPIO_HPD_EN 0x210c
++#define mmDC_GPIO_HPD_EN_BASE_IDX 2
++#define mmDC_GPIO_HPD_Y 0x210d
++#define mmDC_GPIO_HPD_Y_BASE_IDX 2
++#define mmDC_GPIO_PWRSEQ_MASK 0x210e
++#define mmDC_GPIO_PWRSEQ_MASK_BASE_IDX 2
++#define mmDC_GPIO_PWRSEQ_A 0x210f
++#define mmDC_GPIO_PWRSEQ_A_BASE_IDX 2
++#define mmDC_GPIO_PWRSEQ_EN 0x2110
++#define mmDC_GPIO_PWRSEQ_EN_BASE_IDX 2
++#define mmDC_GPIO_PWRSEQ_Y 0x2111
++#define mmDC_GPIO_PWRSEQ_Y_BASE_IDX 2
++#define mmDC_GPIO_PAD_STRENGTH_1 0x2112
++#define mmDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2
++#define mmDC_GPIO_PAD_STRENGTH_2 0x2113
++#define mmDC_GPIO_PAD_STRENGTH_2_BASE_IDX 2
++#define mmPHY_AUX_CNTL 0x2115
++#define mmPHY_AUX_CNTL_BASE_IDX 2
++#define mmDC_GPIO_I2CPAD_MASK 0x2116
++#define mmDC_GPIO_I2CPAD_MASK_BASE_IDX 2
++#define mmDC_GPIO_I2CPAD_A 0x2117
++#define mmDC_GPIO_I2CPAD_A_BASE_IDX 2
++#define mmDC_GPIO_I2CPAD_EN 0x2118
++#define mmDC_GPIO_I2CPAD_EN_BASE_IDX 2
++#define mmDC_GPIO_I2CPAD_Y 0x2119
++#define mmDC_GPIO_I2CPAD_Y_BASE_IDX 2
++#define mmDC_GPIO_I2CPAD_STRENGTH 0x211a
++#define mmDC_GPIO_I2CPAD_STRENGTH_BASE_IDX 2
++#define mmDVO_STRENGTH_CONTROL 0x211b
++#define mmDVO_STRENGTH_CONTROL_BASE_IDX 2
++#define mmDVO_VREF_CONTROL 0x211c
++#define mmDVO_VREF_CONTROL_BASE_IDX 2
++#define mmDVO_SKEW_ADJUST 0x211d
++#define mmDVO_SKEW_ADJUST_BASE_IDX 2
++#define mmDC_GPIO_I2S_SPDIF_MASK 0x2126
++#define mmDC_GPIO_I2S_SPDIF_MASK_BASE_IDX 2
++#define mmDC_GPIO_I2S_SPDIF_A 0x2127
++#define mmDC_GPIO_I2S_SPDIF_A_BASE_IDX 2
++#define mmDC_GPIO_I2S_SPDIF_EN 0x2128
++#define mmDC_GPIO_I2S_SPDIF_EN_BASE_IDX 2
++#define mmDC_GPIO_I2S_SPDIF_Y 0x2129
++#define mmDC_GPIO_I2S_SPDIF_Y_BASE_IDX 2
++#define mmDC_GPIO_I2S_SPDIF_STRENGTH 0x212a
++#define mmDC_GPIO_I2S_SPDIF_STRENGTH_BASE_IDX 2
++#define mmDC_GPIO_TX12_EN 0x212b
++#define mmDC_GPIO_TX12_EN_BASE_IDX 2
++#define mmDC_GPIO_AUX_CTRL_0 0x212c
++#define mmDC_GPIO_AUX_CTRL_0_BASE_IDX 2
++#define mmDC_GPIO_AUX_CTRL_1 0x212d
++#define mmDC_GPIO_AUX_CTRL_1_BASE_IDX 2
++#define mmDC_GPIO_AUX_CTRL_2 0x212e
++#define mmDC_GPIO_AUX_CTRL_2_BASE_IDX 2
++#define mmDC_GPIO_RXEN 0x212f
++#define mmDC_GPIO_RXEN_BASE_IDX 2
++#define mmBPHYC_DAC_MACRO_CNTL 0x2136
++#define mmBPHYC_DAC_MACRO_CNTL_BASE_IDX 2
++#define mmDAC_MACRO_CNTL_RESERVED0 0x2136
++#define mmDAC_MACRO_CNTL_RESERVED0_BASE_IDX 2
++#define mmBPHYC_DAC_AUTO_CALIB_CONTROL 0x2137
++#define mmBPHYC_DAC_AUTO_CALIB_CONTROL_BASE_IDX 2
++#define mmDAC_MACRO_CNTL_RESERVED1 0x2137
++#define mmDAC_MACRO_CNTL_RESERVED1_BASE_IDX 2
++#define mmDAC_MACRO_CNTL_RESERVED2 0x2138
++#define mmDAC_MACRO_CNTL_RESERVED2_BASE_IDX 2
++#define mmDAC_MACRO_CNTL_RESERVED3 0x2139
++#define mmDAC_MACRO_CNTL_RESERVED3_BASE_IDX 2
++#define mmDISP_DSI_DUAL_CTRL 0x277e
++#define mmDISP_DSI_DUAL_CTRL_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED0 0x283e
++#define mmDPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED1 0x283f
++#define mmDPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED2 0x2840
++#define mmDPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED3 0x2841
++#define mmDPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED4 0x2842
++#define mmDPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED5 0x2843
++#define mmDPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED6 0x2844
++#define mmDPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED7 0x2845
++#define mmDPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED8 0x2846
++#define mmDPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED9 0x2847
++#define mmDPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED10 0x2848
++#define mmDPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED11 0x2849
++#define mmDPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED12 0x284a
++#define mmDPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED13 0x284b
++#define mmDPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED14 0x284c
++#define mmDPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED15 0x284d
++#define mmDPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED16 0x284e
++#define mmDPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED17 0x284f
++#define mmDPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED18 0x2850
++#define mmDPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED19 0x2851
++#define mmDPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED20 0x2852
++#define mmDPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED21 0x2853
++#define mmDPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED22 0x2854
++#define mmDPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED23 0x2855
++#define mmDPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED24 0x2856
++#define mmDPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED25 0x2857
++#define mmDPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED26 0x2858
++#define mmDPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED27 0x2859
++#define mmDPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED28 0x285a
++#define mmDPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED29 0x285b
++#define mmDPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED30 0x285c
++#define mmDPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED31 0x285d
++#define mmDPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED32 0x285e
++#define mmDPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED33 0x285f
++#define mmDPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED34 0x2860
++#define mmDPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED35 0x2861
++#define mmDPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED36 0x2862
++#define mmDPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED37 0x2863
++#define mmDPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED38 0x2864
++#define mmDPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED39 0x2865
++#define mmDPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED40 0x2866
++#define mmDPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED41 0x2867
++#define mmDPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED42 0x2868
++#define mmDPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED43 0x2869
++#define mmDPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED44 0x286a
++#define mmDPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED45 0x286b
++#define mmDPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED46 0x286c
++#define mmDPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED47 0x286d
++#define mmDPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED48 0x286e
++#define mmDPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED49 0x286f
++#define mmDPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED50 0x2870
++#define mmDPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED51 0x2871
++#define mmDPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED52 0x2872
++#define mmDPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED53 0x2873
++#define mmDPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED54 0x2874
++#define mmDPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED55 0x2875
++#define mmDPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED56 0x2876
++#define mmDPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED57 0x2877
++#define mmDPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED58 0x2878
++#define mmDPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED59 0x2879
++#define mmDPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED60 0x287a
++#define mmDPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED61 0x287b
++#define mmDPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED62 0x287c
++#define mmDPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
++#define mmDPHY_MACRO_CNTL_RESERVED63 0x287d
++#define mmDPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
++#define mmDPRX_AUX_REFERENCE_PULSE_DIV 0x2a7e
++#define mmDPRX_AUX_REFERENCE_PULSE_DIV_BASE_IDX 2
++#define mmDPRX_AUX_CONTROL 0x2a7f
++#define mmDPRX_AUX_CONTROL_BASE_IDX 2
++#define mmDPRX_AUX_HPD_CONTROL1 0x2a80
++#define mmDPRX_AUX_HPD_CONTROL1_BASE_IDX 2
++#define mmDPRX_AUX_HPD_CONTROL2 0x2a81
++#define mmDPRX_AUX_HPD_CONTROL2_BASE_IDX 2
++#define mmDPRX_AUX_RX_STATUS 0x2a82
++#define mmDPRX_AUX_RX_STATUS_BASE_IDX 2
++#define mmDPRX_AUX_RX_ERROR_MASK 0x2a83
++#define mmDPRX_AUX_RX_ERROR_MASK_BASE_IDX 2
++#define mmDPRX_AUX_DPHY_TX_REF_CONTROL 0x2a84
++#define mmDPRX_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
++#define mmDPRX_AUX_DPHY_TX_CONTROL 0x2a85
++#define mmDPRX_AUX_DPHY_TX_CONTROL_BASE_IDX 2
++#define mmDPRX_AUX_DPHY_RX_CONTROL0 0x2a86
++#define mmDPRX_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
++#define mmDPRX_AUX_DPHY_RX_CONTROL1 0x2a87
++#define mmDPRX_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
++#define mmDPRX_AUX_DPHY_TX_STATUS 0x2a88
++#define mmDPRX_AUX_DPHY_TX_STATUS_BASE_IDX 2
++#define mmDPRX_AUX_DPHY_RX_STATUS 0x2a89
++#define mmDPRX_AUX_DPHY_RX_STATUS_BASE_IDX 2
++#define mmDPRX_AUX_DMCU_HW_INT_STATUS 0x2a8a
++#define mmDPRX_AUX_DMCU_HW_INT_STATUS_BASE_IDX 2
++#define mmDPRX_AUX_DMCU_HW_INT_ACK 0x2a8b
++#define mmDPRX_AUX_DMCU_HW_INT_ACK_BASE_IDX 2
++#define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT1 0x2a8c
++#define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT1_BASE_IDX 2
++#define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT2 0x2a8d
++#define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT2_BASE_IDX 2
++#define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT1 0x2a8e
++#define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT1_BASE_IDX 2
++#define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT2 0x2a8f
++#define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT2_BASE_IDX 2
++#define mmDPRX_AUX_AUX_BUF_INDEX 0x2a90
++#define mmDPRX_AUX_AUX_BUF_INDEX_BASE_IDX 2
++#define mmDPRX_AUX_AUX_BUF_DATA 0x2a91
++#define mmDPRX_AUX_AUX_BUF_DATA_BASE_IDX 2
++#define mmDPRX_AUX_EDID_INDEX 0x2a92
++#define mmDPRX_AUX_EDID_INDEX_BASE_IDX 2
++#define mmDPRX_AUX_EDID_DATA 0x2a93
++#define mmDPRX_AUX_EDID_DATA_BASE_IDX 2
++#define mmDPRX_AUX_DPCD_INDEX1 0x2a94
++#define mmDPRX_AUX_DPCD_INDEX1_BASE_IDX 2
++#define mmDPRX_AUX_DPCD_DATA1 0x2a95
++#define mmDPRX_AUX_DPCD_DATA1_BASE_IDX 2
++#define mmDPRX_AUX_DPCD_INDEX2 0x2a96
++#define mmDPRX_AUX_DPCD_INDEX2_BASE_IDX 2
++#define mmDPRX_AUX_DPCD_DATA2 0x2a97
++#define mmDPRX_AUX_DPCD_DATA2_BASE_IDX 2
++#define mmDPRX_AUX_MSG_INDEX1 0x2a98
++#define mmDPRX_AUX_MSG_INDEX1_BASE_IDX 2
++#define mmDPRX_AUX_MSG_DATA1 0x2a99
++#define mmDPRX_AUX_MSG_DATA1_BASE_IDX 2
++#define mmDPRX_AUX_MSG_INDEX2 0x2a9a
++#define mmDPRX_AUX_MSG_INDEX2_BASE_IDX 2
++#define mmDPRX_AUX_MSG_DATA2 0x2a9b
++#define mmDPRX_AUX_MSG_DATA2_BASE_IDX 2
++#define mmDPRX_AUX_KSV_INDEX1 0x2a9c
++#define mmDPRX_AUX_KSV_INDEX1_BASE_IDX 2
++#define mmDPRX_AUX_KSV_DATA1 0x2a9d
++#define mmDPRX_AUX_KSV_DATA1_BASE_IDX 2
++#define mmDPRX_AUX_KSV_INDEX2 0x2a9e
++#define mmDPRX_AUX_KSV_INDEX2_BASE_IDX 2
++#define mmDPRX_AUX_KSV_DATA2 0x2a9f
++#define mmDPRX_AUX_KSV_DATA2_BASE_IDX 2
++#define mmDPRX_AUX_MSG_TIMEOUT_CONTROL 0x2aa0
++#define mmDPRX_AUX_MSG_TIMEOUT_CONTROL_BASE_IDX 2
++#define mmDPRX_AUX_MSG_BUF_CONTROL1 0x2aa1
++#define mmDPRX_AUX_MSG_BUF_CONTROL1_BASE_IDX 2
++#define mmDPRX_AUX_MSG_BUF_CONTROL2 0x2aa2
++#define mmDPRX_AUX_MSG_BUF_CONTROL2_BASE_IDX 2
++#define mmDPRX_AUX_SCRATCH1 0x2aa3
++#define mmDPRX_AUX_SCRATCH1_BASE_IDX 2
++#define mmDPRX_AUX_SCRATCH2 0x2aa4
++#define mmDPRX_AUX_SCRATCH2_BASE_IDX 2
++#define mmDPRX_AUX_MSG1_PENDING 0x2aa5
++#define mmDPRX_AUX_MSG1_PENDING_BASE_IDX 2
++#define mmDPRX_AUX_MSG2_PENDING 0x2aa6
++#define mmDPRX_AUX_MSG2_PENDING_BASE_IDX 2
++#define mmDPRX_AUX_MSG3_PENDING 0x2aa7
++#define mmDPRX_AUX_MSG3_PENDING_BASE_IDX 2
++#define mmDPRX_AUX_MSG4_PENDING 0x2aa8
++#define mmDPRX_AUX_MSG4_PENDING_BASE_IDX 2
++#define mmDPRX_DPHY_DPCD_LANE_COUNT_SET 0x2afe
++#define mmDPRX_DPHY_DPCD_LANE_COUNT_SET_BASE_IDX 2
++#define mmDPRX_DPHY_DPCD_TRAINING_PATTERN_SET 0x2aff
++#define mmDPRX_DPHY_DPCD_TRAINING_PATTERN_SET_BASE_IDX 2
++#define mmDPRX_DPHY_DPCD_MSTM_CTRL 0x2b00
++#define mmDPRX_DPHY_DPCD_MSTM_CTRL_BASE_IDX 2
++#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_SET 0x2b01
++#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_SET_BASE_IDX 2
++#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS 0x2b02
++#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS_BASE_IDX 2
++#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_SET 0x2b03
++#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_SET_BASE_IDX 2
++#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS 0x2b04
++#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS_BASE_IDX 2
++#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_SET 0x2b05
++#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_SET_BASE_IDX 2
++#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS 0x2b06
++#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS_BASE_IDX 2
++#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_SET 0x2b07
++#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_SET_BASE_IDX 2
++#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS 0x2b08
++#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS_BASE_IDX 2
++#define mmDPRX_DPHY_READY 0x2b09
++#define mmDPRX_DPHY_READY_BASE_IDX 2
++#define mmDPRX_DPHY_COMMA_STATUS 0x2b0b
++#define mmDPRX_DPHY_COMMA_STATUS_BASE_IDX 2
++#define mmDPRX_DPHY_LANE_ALIGN_ERROR_STATUS_UPDATED 0x2b0c
++#define mmDPRX_DPHY_LANE_ALIGN_ERROR_STATUS_UPDATED_BASE_IDX 2
++#define mmDPRX_DPHY_LANE_ALIGN_STATUS_UPDATED 0x2b0d
++#define mmDPRX_DPHY_LANE_ALIGN_STATUS_UPDATED_BASE_IDX 2
++#define mmDPRX_DPHY_ERROR_THRESH_A_LANE0 0x2b0f
++#define mmDPRX_DPHY_ERROR_THRESH_A_LANE0_BASE_IDX 2
++#define mmDPRX_DPHY_ERROR_COUNT_A_LANE0 0x2b11
++#define mmDPRX_DPHY_ERROR_COUNT_A_LANE0_BASE_IDX 2
++#define mmDPRX_DPHY_ERROR_COUNT_B_LANE0 0x2b12
++#define mmDPRX_DPHY_ERROR_COUNT_B_LANE0_BASE_IDX 2
++#define mmDPRX_DPHY_ERROR_COUNT_C_LANE0 0x2b13
++#define mmDPRX_DPHY_ERROR_COUNT_C_LANE0_BASE_IDX 2
++#define mmDPRX_DPHY_ERROR_THRESH_A_LANE1 0x2b14
++#define mmDPRX_DPHY_ERROR_THRESH_A_LANE1_BASE_IDX 2
++#define mmDPRX_DPHY_ERROR_COUNT_A_LANE1 0x2b16
++#define mmDPRX_DPHY_ERROR_COUNT_A_LANE1_BASE_IDX 2
++#define mmDPRX_DPHY_ERROR_COUNT_B_LANE1 0x2b17
++#define mmDPRX_DPHY_ERROR_COUNT_B_LANE1_BASE_IDX 2
++#define mmDPRX_DPHY_ERROR_COUNT_C_LANE1 0x2b18
++#define mmDPRX_DPHY_ERROR_COUNT_C_LANE1_BASE_IDX 2
++#define mmDPRX_DPHY_ERROR_THRESH_A_LANE2 0x2b19
++#define mmDPRX_DPHY_ERROR_THRESH_A_LANE2_BASE_IDX 2
++#define mmDPRX_DPHY_ERROR_COUNT_A_LANE2 0x2b1b
++#define mmDPRX_DPHY_ERROR_COUNT_A_LANE2_BASE_IDX 2
++#define mmDPRX_DPHY_ERROR_COUNT_B_LANE2 0x2b1c
++#define mmDPRX_DPHY_ERROR_COUNT_B_LANE2_BASE_IDX 2
++#define mmDPRX_DPHY_ERROR_COUNT_C_LANE2 0x2b1d
++#define mmDPRX_DPHY_ERROR_COUNT_C_LANE2_BASE_IDX 2
++#define mmDPRX_DPHY_ERROR_THRESH_A_LANE3 0x2b1e
++#define mmDPRX_DPHY_ERROR_THRESH_A_LANE3_BASE_IDX 2
++#define mmDPRX_DPHY_ERROR_COUNT_A_LANE3 0x2b20
++#define mmDPRX_DPHY_ERROR_COUNT_A_LANE3_BASE_IDX 2
++#define mmDPRX_DPHY_ERROR_COUNT_B_LANE3 0x2b21
++#define mmDPRX_DPHY_ERROR_COUNT_B_LANE3_BASE_IDX 2
++#define mmDPRX_DPHY_ERROR_COUNT_C_LANE3 0x2b22
++#define mmDPRX_DPHY_ERROR_COUNT_C_LANE3_BASE_IDX 2
++#define mmDPRX_DPHY_BS_ERROR_THRESH_GLOBAL 0x2b24
++#define mmDPRX_DPHY_BS_ERROR_THRESH_GLOBAL_BASE_IDX 2
++#define mmDPRX_DPHY_SR_ERROR_COUNT_A 0x2b25
++#define mmDPRX_DPHY_SR_ERROR_COUNT_A_BASE_IDX 2
++#define mmDPRX_DPHY_BS_ERROR_COUNT_A 0x2b27
++#define mmDPRX_DPHY_BS_ERROR_COUNT_A_BASE_IDX 2
++#define mmDPRX_DPHY_BS_ERROR_COUNT_B 0x2b28
++#define mmDPRX_DPHY_BS_ERROR_COUNT_B_BASE_IDX 2
++#define mmDPRX_DPHY_LANESETUP0 0x2b2d
++#define mmDPRX_DPHY_LANESETUP0_BASE_IDX 2
++#define mmDPRX_DPHY_LANESETUP1 0x2b2e
++#define mmDPRX_DPHY_LANESETUP1_BASE_IDX 2
++#define mmDPRX_DPHY_LFSRADV 0x2b31
++#define mmDPRX_DPHY_LFSRADV_BASE_IDX 2
++#define mmDPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT 0x2b32
++#define mmDPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT_BASE_IDX 2
++#define mmDPRX_DPHY_SET_ENABLE 0x2b33
++#define mmDPRX_DPHY_SET_ENABLE_BASE_IDX 2
++#define mmDPRX_DPHY_ECF_LSB 0x2b34
++#define mmDPRX_DPHY_ECF_LSB_BASE_IDX 2
++#define mmDPRX_DPHY_ECF_MSB 0x2b35
++#define mmDPRX_DPHY_ECF_MSB_BASE_IDX 2
++#define mmDPRX_DPHY_ENHANCED_FRAME_EN 0x2b36
++#define mmDPRX_DPHY_ENHANCED_FRAME_EN_BASE_IDX 2
++#define mmDPRX_DPHY_MTP_HEADER_COUNT_FORCE 0x2b3c
++#define mmDPRX_DPHY_MTP_HEADER_COUNT_FORCE_BASE_IDX 2
++#define mmDPRX_DPHY_DYNAMIC_DESKEW_DATA 0x2b3d
++#define mmDPRX_DPHY_DYNAMIC_DESKEW_DATA_BASE_IDX 2
++#define mmDPRX_DPHY_DYNAMIC_DESKEW_CONTROL 0x2b3e
++#define mmDPRX_DPHY_DYNAMIC_DESKEW_CONTROL_BASE_IDX 2
++#define mmDPRX_DPHY_BYPASS 0x2b3f
++#define mmDPRX_DPHY_BYPASS_BASE_IDX 2
++#define mmDPRX_DPHY_INT_RESET 0x2b40
++#define mmDPRX_DPHY_INT_RESET_BASE_IDX 2
++#define mmDPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS 0x2b41
++#define mmDPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS_BASE_IDX 2
++#define mmDPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS 0x2b43
++#define mmDPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS_BASE_IDX 2
++#define mmDPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS 0x2b44
++#define mmDPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS_BASE_IDX 2
++#define mmDPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS 0x2b46
++#define mmDPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS_BASE_IDX 2
++#define mmDPRX_DPHY_DETECT_SR_LOCK_STATUS 0x2b48
++#define mmDPRX_DPHY_DETECT_SR_LOCK_STATUS_BASE_IDX 2
++#define mmDPRX_DPHY_LOSS_OF_ALIGN_STATUS 0x2b49
++#define mmDPRX_DPHY_LOSS_OF_ALIGN_STATUS_BASE_IDX 2
++#define mmDPRX_DPHY_LOSS_OF_DESKEW_STATUS 0x2b4a
++#define mmDPRX_DPHY_LOSS_OF_DESKEW_STATUS_BASE_IDX 2
++#define mmDPRX_DPHY_EXCESSIVE_ERROR_STATUS 0x2b4b
++#define mmDPRX_DPHY_EXCESSIVE_ERROR_STATUS_BASE_IDX 2
++#define mmDPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS 0x2b4c
++#define mmDPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS_BASE_IDX 2
++#define mmDPRX_DPHY_SPARE 0x2b4d
++#define mmDPRX_DPHY_SPARE_BASE_IDX 2
++#define mmDCRX_GATE_DISABLE_CNTL 0x2b6e
++#define mmDCRX_GATE_DISABLE_CNTL_BASE_IDX 2
++#define mmDCRX_SOFT_RESET 0x2b6f
++#define mmDCRX_SOFT_RESET_BASE_IDX 2
++#define mmDCRX_LIGHT_SLEEP_CNTL 0x2b70
++#define mmDCRX_LIGHT_SLEEP_CNTL_BASE_IDX 2
++#define mmDCRX_DISPCLK_GATE_CNTL 0x2b73
++#define mmDCRX_DISPCLK_GATE_CNTL_BASE_IDX 2
++#define mmDCRX_CLK_CNTL 0x2b74
++#define mmDCRX_CLK_CNTL_BASE_IDX 2
++#define mmDCRX_TEST_CLK_CNTL 0x2b75
++#define mmDCRX_TEST_CLK_CNTL_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED0 0x2c06
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED1 0x2c07
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED2 0x2c08
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED3 0x2c09
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED4 0x2c0a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED5 0x2c0b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED6 0x2c0c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED7 0x2c0d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED8 0x2c0e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED9 0x2c0f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED10 0x2c10
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED11 0x2c11
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED12 0x2c12
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED13 0x2c13
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED14 0x2c14
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED15 0x2c15
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED16 0x2c16
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED17 0x2c17
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED18 0x2c18
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED19 0x2c19
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED20 0x2c1a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED21 0x2c1b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED22 0x2c1c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED23 0x2c1d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED24 0x2c1e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED25 0x2c1f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED26 0x2c20
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED27 0x2c21
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED28 0x2c22
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED29 0x2c23
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED30 0x2c24
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED31 0x2c25
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED32 0x2c26
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED33 0x2c27
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED34 0x2c28
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED35 0x2c29
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED36 0x2c2a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED37 0x2c2b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED38 0x2c2c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED39 0x2c2d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED40 0x2c2e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED41 0x2c2f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED42 0x2c30
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED43 0x2c31
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED44 0x2c32
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED45 0x2c33
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED46 0x2c34
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED47 0x2c35
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED48 0x2c36
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED49 0x2c37
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED50 0x2c38
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED51 0x2c39
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED52 0x2c3a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED53 0x2c3b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED54 0x2c3c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED55 0x2c3d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED56 0x2c3e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED57 0x2c3f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED58 0x2c40
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED59 0x2c41
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED60 0x2c42
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED61 0x2c43
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED62 0x2c44
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED63 0x2c45
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED64 0x2c46
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED65 0x2c47
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED66 0x2c48
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED67 0x2c49
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED68 0x2c4a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED69 0x2c4b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED70 0x2c4c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED71 0x2c4d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED72 0x2c4e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED73 0x2c4f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED74 0x2c50
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED75 0x2c51
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED76 0x2c52
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED77 0x2c53
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED78 0x2c54
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED79 0x2c55
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED80 0x2c56
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED81 0x2c57
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED82 0x2c58
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED83 0x2c59
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED84 0x2c5a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED85 0x2c5b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED86 0x2c5c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED87 0x2c5d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED88 0x2c5e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED89 0x2c5f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED90 0x2c60
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED91 0x2c61
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED92 0x2c62
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED93 0x2c63
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED94 0x2c64
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED95 0x2c65
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED96 0x2c66
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED97 0x2c67
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED98 0x2c68
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED99 0x2c69
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED100 0x2c6a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED101 0x2c6b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED102 0x2c6c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED103 0x2c6d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED104 0x2c6e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED105 0x2c6f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED106 0x2c70
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED107 0x2c71
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED108 0x2c72
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED109 0x2c73
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED110 0x2c74
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED111 0x2c75
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED112 0x2c76
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED113 0x2c77
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED114 0x2c78
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED115 0x2c79
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED116 0x2c7a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED117 0x2c7b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED118 0x2c7c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED119 0x2c7d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED120 0x2c7e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED121 0x2c7f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED122 0x2c80
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED123 0x2c81
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED124 0x2c82
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED125 0x2c83
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED126 0x2c84
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED127 0x2c85
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED128 0x2c86
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED129 0x2c87
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED130 0x2c88
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED131 0x2c89
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED132 0x2c8a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED133 0x2c8b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED134 0x2c8c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED135 0x2c8d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED136 0x2c8e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED137 0x2c8f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED138 0x2c90
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED139 0x2c91
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED140 0x2c92
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED141 0x2c93
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED142 0x2c94
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED143 0x2c95
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED144 0x2c96
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED145 0x2c97
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED146 0x2c98
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED147 0x2c99
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED148 0x2c9a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED149 0x2c9b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED150 0x2c9c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED151 0x2c9d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED152 0x2c9e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED153 0x2c9f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED154 0x2ca0
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED155 0x2ca1
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED156 0x2ca2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED157 0x2ca3
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED158 0x2ca4
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED159 0x2ca5
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED160 0x2ca6
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED160_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED161 0x2ca7
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED161_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED162 0x2ca8
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED162_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED163 0x2ca9
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED163_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED164 0x2caa
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED164_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED165 0x2cab
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED165_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED166 0x2cac
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED166_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED167 0x2cad
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED167_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED168 0x2cae
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED168_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED169 0x2caf
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED169_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED170 0x2cb0
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED170_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED171 0x2cb1
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED171_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED172 0x2cb2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED172_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED173 0x2cb3
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED173_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED174 0x2cb4
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED174_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED175 0x2cb5
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED175_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED176 0x2cb6
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED176_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED177 0x2cb7
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED177_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED178 0x2cb8
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED178_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED179 0x2cb9
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED179_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED180 0x2cba
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED180_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED181 0x2cbb
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED181_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED182 0x2cbc
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED182_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED183 0x2cbd
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED183_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED184 0x2cbe
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED184_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED185 0x2cbf
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED185_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED186 0x2cc0
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED186_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED187 0x2cc1
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED187_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED188 0x2cc2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED188_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED189 0x2cc3
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED189_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED190 0x2cc4
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED190_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED191 0x2cc5
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED191_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED192 0x2cc6
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED192_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED193 0x2cc7
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED193_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED194 0x2cc8
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED194_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED195 0x2cc9
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED195_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED196 0x2cca
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED196_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED197 0x2ccb
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED197_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED198 0x2ccc
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED198_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED199 0x2ccd
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED199_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED200 0x2cce
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED200_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED201 0x2ccf
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED201_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED202 0x2cd0
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED202_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED203 0x2cd1
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED203_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED204 0x2cd2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED204_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED205 0x2cd3
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED205_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED206 0x2cd4
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED206_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED207 0x2cd5
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED207_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED208 0x2cd6
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED208_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED209 0x2cd7
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED209_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED210 0x2cd8
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED210_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED211 0x2cd9
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED211_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED212 0x2cda
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED212_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED213 0x2cdb
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED213_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED214 0x2cdc
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED214_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED215 0x2cdd
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED215_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED216 0x2cde
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED216_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED217 0x2cdf
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED217_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED218 0x2ce0
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED218_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED219 0x2ce1
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED219_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED220 0x2ce2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED220_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED221 0x2ce3
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED221_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED222 0x2ce4
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED222_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED223 0x2ce5
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED223_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED224 0x2ce6
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED224_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED225 0x2ce7
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED225_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED226 0x2ce8
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED226_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED227 0x2ce9
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED227_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED228 0x2cea
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED228_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED229 0x2ceb
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED229_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED230 0x2cec
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED230_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED231 0x2ced
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED231_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED232 0x2cee
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED232_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED233 0x2cef
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED233_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED234 0x2cf0
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED234_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED235 0x2cf1
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED235_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED236 0x2cf2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED236_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED237 0x2cf3
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED237_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED238 0x2cf4
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED238_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED239 0x2cf5
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED239_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED240 0x2cf6
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED240_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED241 0x2cf7
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED241_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED242 0x2cf8
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED242_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED243 0x2cf9
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED243_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED244 0x2cfa
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED244_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED245 0x2cfb
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED245_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED246 0x2cfc
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED246_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED247 0x2cfd
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED247_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED248 0x2cfe
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED248_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED249 0x2cff
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED249_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED250 0x2d00
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED250_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED251 0x2d01
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED251_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED252 0x2d02
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED252_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED253 0x2d03
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED253_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED254 0x2d04
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED254_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED255 0x2d05
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED255_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED256 0x2d06
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED256_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED257 0x2d07
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED257_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED258 0x2d08
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED258_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED259 0x2d09
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED259_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED260 0x2d0a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED260_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED261 0x2d0b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED261_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED262 0x2d0c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED262_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED263 0x2d0d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED263_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED264 0x2d0e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED264_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED265 0x2d0f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED265_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED266 0x2d10
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED266_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED267 0x2d11
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED267_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED268 0x2d12
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED268_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED269 0x2d13
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED269_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED270 0x2d14
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED270_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED271 0x2d15
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED271_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED272 0x2d16
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED272_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED273 0x2d17
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED273_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED274 0x2d18
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED274_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED275 0x2d19
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED275_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED276 0x2d1a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED276_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED277 0x2d1b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED277_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED278 0x2d1c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED278_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED279 0x2d1d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED279_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED280 0x2d1e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED280_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED281 0x2d1f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED281_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED282 0x2d20
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED282_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED283 0x2d21
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED283_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED284 0x2d22
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED284_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED285 0x2d23
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED285_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED286 0x2d24
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED286_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED287 0x2d25
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED287_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED288 0x2d26
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED288_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED289 0x2d27
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED289_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED290 0x2d28
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED290_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED291 0x2d29
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED291_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED292 0x2d2a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED292_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED293 0x2d2b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED293_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED294 0x2d2c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED294_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED295 0x2d2d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED295_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED296 0x2d2e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED296_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED297 0x2d2f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED297_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED298 0x2d30
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED298_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED299 0x2d31
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED299_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED300 0x2d32
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED300_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED301 0x2d33
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED301_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED302 0x2d34
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED302_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED303 0x2d35
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED303_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED304 0x2d36
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED304_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED305 0x2d37
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED305_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED306 0x2d38
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED306_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED307 0x2d39
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED307_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED308 0x2d3a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED308_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED309 0x2d3b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED309_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED310 0x2d3c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED310_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED311 0x2d3d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED311_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED312 0x2d3e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED312_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED313 0x2d3f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED313_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED314 0x2d40
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED314_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED315 0x2d41
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED315_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED316 0x2d42
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED316_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED317 0x2d43
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED317_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED318 0x2d44
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED318_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED319 0x2d45
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED319_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED320 0x2d46
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED320_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED321 0x2d47
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED321_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED322 0x2d48
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED322_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED323 0x2d49
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED323_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED324 0x2d4a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED324_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED325 0x2d4b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED325_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED326 0x2d4c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED326_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED327 0x2d4d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED327_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED328 0x2d4e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED328_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED329 0x2d4f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED329_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED330 0x2d50
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED330_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED331 0x2d51
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED331_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED332 0x2d52
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED332_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED333 0x2d53
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED333_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED334 0x2d54
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED334_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED335 0x2d55
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED335_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED336 0x2d56
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED336_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED337 0x2d57
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED337_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED338 0x2d58
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED338_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED339 0x2d59
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED339_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED340 0x2d5a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED340_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED341 0x2d5b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED341_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED342 0x2d5c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED342_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED343 0x2d5d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED343_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED344 0x2d5e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED344_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED345 0x2d5f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED345_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED346 0x2d60
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED346_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED347 0x2d61
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED347_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED348 0x2d62
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED348_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED349 0x2d63
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED349_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED350 0x2d64
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED350_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED351 0x2d65
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED351_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED352 0x2d66
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED352_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED353 0x2d67
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED353_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED354 0x2d68
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED354_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED355 0x2d69
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED355_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED356 0x2d6a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED356_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED357 0x2d6b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED357_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED358 0x2d6c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED358_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED359 0x2d6d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED359_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED360 0x2d6e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED360_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED361 0x2d6f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED361_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED362 0x2d70
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED362_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED363 0x2d71
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED363_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED364 0x2d72
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED364_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED365 0x2d73
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED365_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED366 0x2d74
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED366_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED367 0x2d75
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED367_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED368 0x2d76
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED368_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED369 0x2d77
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED369_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED370 0x2d78
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED370_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED371 0x2d79
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED371_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED372 0x2d7a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED372_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED373 0x2d7b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED373_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED374 0x2d7c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED374_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED375 0x2d7d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED375_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED376 0x2d7e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED376_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED377 0x2d7f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED377_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED378 0x2d80
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED378_BASE_IDX 2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED379 0x2d81
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED379_BASE_IDX 2
++#define mmI2S0_CNTL 0x2d82
++#define mmI2S0_CNTL_BASE_IDX 2
++#define mmSPDIF0_CNTL 0x2d83
++#define mmSPDIF0_CNTL_BASE_IDX 2
++#define mmI2S1_CNTL 0x2d84
++#define mmI2S1_CNTL_BASE_IDX 2
++#define mmSPDIF1_CNTL 0x2d85
++#define mmSPDIF1_CNTL_BASE_IDX 2
++#define mmI2S0_STATUS 0x2d86
++#define mmI2S0_STATUS_BASE_IDX 2
++#define mmI2S1_STATUS 0x2d87
++#define mmI2S1_STATUS_BASE_IDX 2
++#define mmI2S0_CRC_TEST_CNTL 0x2d8a
++#define mmI2S0_CRC_TEST_CNTL_BASE_IDX 2
++#define mmI2S0_CRC_TEST_DATA_01 0x2d8b
++#define mmI2S0_CRC_TEST_DATA_01_BASE_IDX 2
++#define mmI2S0_CRC_TEST_DATA_23 0x2d8c
++#define mmI2S0_CRC_TEST_DATA_23_BASE_IDX 2
++#define mmI2S1_CRC_TEST_CNTL 0x2d8d
++#define mmI2S1_CRC_TEST_CNTL_BASE_IDX 2
++#define mmI2S1_CRC_TEST_DATA_0 0x2d8e
++#define mmI2S1_CRC_TEST_DATA_0_BASE_IDX 2
++#define mmSPDIF0_CRC_TEST_CNTL 0x2d8f
++#define mmSPDIF0_CRC_TEST_CNTL_BASE_IDX 2
++#define mmSPDIF0_CRC_TEST_DATA_0 0x2d90
++#define mmSPDIF0_CRC_TEST_DATA_0_BASE_IDX 2
++#define mmSPDIF1_CRC_TEST_CNTL 0x2d91
++#define mmSPDIF1_CRC_TEST_CNTL_BASE_IDX 2
++#define mmSPDIF1_CRC_TEST_DATA 0x2d92
++#define mmSPDIF1_CRC_TEST_DATA_BASE_IDX 2
++#define mmCRC_I2S_CONT_REPEAT_NUM 0x2d93
++#define mmCRC_I2S_CONT_REPEAT_NUM_BASE_IDX 2
++#define mmCRC_SPDIF_CONT_REPEAT_NUM 0x2d94
++#define mmCRC_SPDIF_CONT_REPEAT_NUM_BASE_IDX 2
++#define mmZCAL_MACRO_CNTL_RESERVED0 0x2d96
++#define mmZCAL_MACRO_CNTL_RESERVED0_BASE_IDX 2
++#define mmZCAL_MACRO_CNTL_RESERVED1 0x2d97
++#define mmZCAL_MACRO_CNTL_RESERVED1_BASE_IDX 2
++#define mmZCAL_MACRO_CNTL_RESERVED2 0x2d98
++#define mmZCAL_MACRO_CNTL_RESERVED2_BASE_IDX 2
++#define mmZCAL_MACRO_CNTL_RESERVED3 0x2d99
++#define mmZCAL_MACRO_CNTL_RESERVED3_BASE_IDX 2
++#define mmZCAL_MACRO_CNTL_RESERVED4 0x2d9a
++#define mmZCAL_MACRO_CNTL_RESERVED4_BASE_IDX 2
++
++
++// addressBlock: dce_dc_azf0stream0_dispdec
++// base address: 0x0
++#define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x0458
++#define mmAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2
++#define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x0459
++#define mmAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2
++
++
++// addressBlock: dce_dc_azf0stream1_dispdec
++// base address: 0x8
++#define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x045a
++#define mmAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2
++#define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x045b
++#define mmAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2
++
++
++// addressBlock: dce_dc_azf0stream2_dispdec
++// base address: 0x10
++#define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x045c
++#define mmAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2
++#define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x045d
++#define mmAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2
++
++
++// addressBlock: dce_dc_azf0stream3_dispdec
++// base address: 0x18
++#define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x045e
++#define mmAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2
++#define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x045f
++#define mmAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2
++
++
++// addressBlock: dce_dc_azf0stream4_dispdec
++// base address: 0x20
++#define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x0460
++#define mmAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2
++#define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x0461
++#define mmAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2
++
++
++// addressBlock: dce_dc_azf0stream5_dispdec
++// base address: 0x28
++#define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x0462
++#define mmAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2
++#define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x0463
++#define mmAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2
++
++
++// addressBlock: dce_dc_azf0stream6_dispdec
++// base address: 0x30
++#define mmAZF0STREAM6_AZALIA_STREAM_INDEX 0x0464
++#define mmAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2
++#define mmAZF0STREAM6_AZALIA_STREAM_DATA 0x0465
++#define mmAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2
++
++
++// addressBlock: dce_dc_azf0stream7_dispdec
++// base address: 0x38
++#define mmAZF0STREAM7_AZALIA_STREAM_INDEX 0x0466
++#define mmAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2
++#define mmAZF0STREAM7_AZALIA_STREAM_DATA 0x0467
++#define mmAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2
++
++
++// addressBlock: dce_dc_azf0endpoint0_dispdec
++// base address: 0x0
++#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0480
++#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
++#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0481
++#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
++
++
++// addressBlock: dce_dc_azf0endpoint1_dispdec
++// base address: 0x18
++#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0486
++#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
++#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0487
++#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
++
++
++// addressBlock: dce_dc_azf0endpoint2_dispdec
++// base address: 0x30
++#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x048c
++#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
++#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x048d
++#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
++
++
++// addressBlock: dce_dc_azf0endpoint3_dispdec
++// base address: 0x48
++#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0492
++#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
++#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0493
++#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
++
++
++// addressBlock: dce_dc_azf0endpoint4_dispdec
++// base address: 0x60
++#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0498
++#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
++#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0499
++#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
++
++
++// addressBlock: dce_dc_azf0endpoint5_dispdec
++// base address: 0x78
++#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x049e
++#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
++#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x049f
++#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
++
++
++// addressBlock: dce_dc_azf0endpoint6_dispdec
++// base address: 0x90
++#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x04a4
++#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
++#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x04a5
++#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
++
++
++// addressBlock: dce_dc_azf0endpoint7_dispdec
++// base address: 0xa8
++#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x04aa
++#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
++#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x04ab
++#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
++
++
++// addressBlock: dce_dc_azf0stream8_dispdec
++// base address: 0x320
++#define mmAZF0STREAM8_AZALIA_STREAM_INDEX 0x0520
++#define mmAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2
++#define mmAZF0STREAM8_AZALIA_STREAM_DATA 0x0521
++#define mmAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2
++
++
++// addressBlock: dce_dc_azf0stream9_dispdec
++// base address: 0x328
++#define mmAZF0STREAM9_AZALIA_STREAM_INDEX 0x0522
++#define mmAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2
++#define mmAZF0STREAM9_AZALIA_STREAM_DATA 0x0523
++#define mmAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2
++
++
++// addressBlock: dce_dc_azf0stream10_dispdec
++// base address: 0x330
++#define mmAZF0STREAM10_AZALIA_STREAM_INDEX 0x0524
++#define mmAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2
++#define mmAZF0STREAM10_AZALIA_STREAM_DATA 0x0525
++#define mmAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2
++
++
++// addressBlock: dce_dc_azf0stream11_dispdec
++// base address: 0x338
++#define mmAZF0STREAM11_AZALIA_STREAM_INDEX 0x0526
++#define mmAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2
++#define mmAZF0STREAM11_AZALIA_STREAM_DATA 0x0527
++#define mmAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2
++
++
++// addressBlock: dce_dc_azf0stream12_dispdec
++// base address: 0x340
++#define mmAZF0STREAM12_AZALIA_STREAM_INDEX 0x0528
++#define mmAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2
++#define mmAZF0STREAM12_AZALIA_STREAM_DATA 0x0529
++#define mmAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2
++
++
++// addressBlock: dce_dc_azf0stream13_dispdec
++// base address: 0x348
++#define mmAZF0STREAM13_AZALIA_STREAM_INDEX 0x052a
++#define mmAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2
++#define mmAZF0STREAM13_AZALIA_STREAM_DATA 0x052b
++#define mmAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2
++
++
++// addressBlock: dce_dc_azf0stream14_dispdec
++// base address: 0x350
++#define mmAZF0STREAM14_AZALIA_STREAM_INDEX 0x052c
++#define mmAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2
++#define mmAZF0STREAM14_AZALIA_STREAM_DATA 0x052d
++#define mmAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2
++
++
++// addressBlock: dce_dc_azf0stream15_dispdec
++// base address: 0x358
++#define mmAZF0STREAM15_AZALIA_STREAM_INDEX 0x052e
++#define mmAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2
++#define mmAZF0STREAM15_AZALIA_STREAM_DATA 0x052f
++#define mmAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2
++
++
++// addressBlock: dce_dc_azf0inputendpoint0_dispdec
++// base address: 0x0
++#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0534
++#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
++#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0535
++#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
++
++
++// addressBlock: dce_dc_azf0inputendpoint1_dispdec
++// base address: 0x10
++#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0538
++#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
++#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0539
++#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
++
++
++// addressBlock: dce_dc_azf0inputendpoint2_dispdec
++// base address: 0x20
++#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x053c
++#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
++#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x053d
++#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
++
++
++// addressBlock: dce_dc_azf0inputendpoint3_dispdec
++// base address: 0x30
++#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0540
++#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
++#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0541
++#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
++
++
++// addressBlock: dce_dc_azf0inputendpoint4_dispdec
++// base address: 0x40
++#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0544
++#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
++#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0545
++#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
++
++
++// addressBlock: dce_dc_azf0inputendpoint5_dispdec
++// base address: 0x50
++#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0548
++#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
++#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0549
++#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
++
++
++// addressBlock: dce_dc_azf0inputendpoint6_dispdec
++// base address: 0x60
++#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x054c
++#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
++#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x054d
++#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
++
++
++// addressBlock: dce_dc_azf0inputendpoint7_dispdec
++// base address: 0x70
++#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0550
++#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
++#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0551
++#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dcp0_dispdec
++// base address: 0x0
++#define mmDCP0_GRPH_ENABLE 0x055a
++#define mmDCP0_GRPH_ENABLE_BASE_IDX 2
++#define mmDCP0_GRPH_CONTROL 0x055b
++#define mmDCP0_GRPH_CONTROL_BASE_IDX 2
++#define mmDCP0_GRPH_LUT_10BIT_BYPASS 0x055c
++#define mmDCP0_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2
++#define mmDCP0_GRPH_SWAP_CNTL 0x055d
++#define mmDCP0_GRPH_SWAP_CNTL_BASE_IDX 2
++#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS 0x055e
++#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
++#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS 0x055f
++#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
++#define mmDCP0_GRPH_PITCH 0x0560
++#define mmDCP0_GRPH_PITCH_BASE_IDX 2
++#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0561
++#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
++#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0562
++#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
++#define mmDCP0_GRPH_SURFACE_OFFSET_X 0x0563
++#define mmDCP0_GRPH_SURFACE_OFFSET_X_BASE_IDX 2
++#define mmDCP0_GRPH_SURFACE_OFFSET_Y 0x0564
++#define mmDCP0_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2
++#define mmDCP0_GRPH_X_START 0x0565
++#define mmDCP0_GRPH_X_START_BASE_IDX 2
++#define mmDCP0_GRPH_Y_START 0x0566
++#define mmDCP0_GRPH_Y_START_BASE_IDX 2
++#define mmDCP0_GRPH_X_END 0x0567
++#define mmDCP0_GRPH_X_END_BASE_IDX 2
++#define mmDCP0_GRPH_Y_END 0x0568
++#define mmDCP0_GRPH_Y_END_BASE_IDX 2
++#define mmDCP0_INPUT_GAMMA_CONTROL 0x0569
++#define mmDCP0_INPUT_GAMMA_CONTROL_BASE_IDX 2
++#define mmDCP0_GRPH_UPDATE 0x056a
++#define mmDCP0_GRPH_UPDATE_BASE_IDX 2
++#define mmDCP0_GRPH_FLIP_CONTROL 0x056b
++#define mmDCP0_GRPH_FLIP_CONTROL_BASE_IDX 2
++#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE 0x056c
++#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2
++#define mmDCP0_GRPH_DFQ_CONTROL 0x056d
++#define mmDCP0_GRPH_DFQ_CONTROL_BASE_IDX 2
++#define mmDCP0_GRPH_DFQ_STATUS 0x056e
++#define mmDCP0_GRPH_DFQ_STATUS_BASE_IDX 2
++#define mmDCP0_GRPH_INTERRUPT_STATUS 0x056f
++#define mmDCP0_GRPH_INTERRUPT_STATUS_BASE_IDX 2
++#define mmDCP0_GRPH_INTERRUPT_CONTROL 0x0570
++#define mmDCP0_GRPH_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0571
++#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2
++#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS 0x0572
++#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2
++#define mmDCP0_GRPH_COMPRESS_PITCH 0x0573
++#define mmDCP0_GRPH_COMPRESS_PITCH_BASE_IDX 2
++#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0574
++#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2
++#define mmDCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0575
++#define mmDCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2
++#define mmDCP0_PRESCALE_GRPH_CONTROL 0x0576
++#define mmDCP0_PRESCALE_GRPH_CONTROL_BASE_IDX 2
++#define mmDCP0_PRESCALE_VALUES_GRPH_R 0x0577
++#define mmDCP0_PRESCALE_VALUES_GRPH_R_BASE_IDX 2
++#define mmDCP0_PRESCALE_VALUES_GRPH_G 0x0578
++#define mmDCP0_PRESCALE_VALUES_GRPH_G_BASE_IDX 2
++#define mmDCP0_PRESCALE_VALUES_GRPH_B 0x0579
++#define mmDCP0_PRESCALE_VALUES_GRPH_B_BASE_IDX 2
++#define mmDCP0_INPUT_CSC_CONTROL 0x057a
++#define mmDCP0_INPUT_CSC_CONTROL_BASE_IDX 2
++#define mmDCP0_INPUT_CSC_C11_C12 0x057b
++#define mmDCP0_INPUT_CSC_C11_C12_BASE_IDX 2
++#define mmDCP0_INPUT_CSC_C13_C14 0x057c
++#define mmDCP0_INPUT_CSC_C13_C14_BASE_IDX 2
++#define mmDCP0_INPUT_CSC_C21_C22 0x057d
++#define mmDCP0_INPUT_CSC_C21_C22_BASE_IDX 2
++#define mmDCP0_INPUT_CSC_C23_C24 0x057e
++#define mmDCP0_INPUT_CSC_C23_C24_BASE_IDX 2
++#define mmDCP0_INPUT_CSC_C31_C32 0x057f
++#define mmDCP0_INPUT_CSC_C31_C32_BASE_IDX 2
++#define mmDCP0_INPUT_CSC_C33_C34 0x0580
++#define mmDCP0_INPUT_CSC_C33_C34_BASE_IDX 2
++#define mmDCP0_OUTPUT_CSC_CONTROL 0x0581
++#define mmDCP0_OUTPUT_CSC_CONTROL_BASE_IDX 2
++#define mmDCP0_OUTPUT_CSC_C11_C12 0x0582
++#define mmDCP0_OUTPUT_CSC_C11_C12_BASE_IDX 2
++#define mmDCP0_OUTPUT_CSC_C13_C14 0x0583
++#define mmDCP0_OUTPUT_CSC_C13_C14_BASE_IDX 2
++#define mmDCP0_OUTPUT_CSC_C21_C22 0x0584
++#define mmDCP0_OUTPUT_CSC_C21_C22_BASE_IDX 2
++#define mmDCP0_OUTPUT_CSC_C23_C24 0x0585
++#define mmDCP0_OUTPUT_CSC_C23_C24_BASE_IDX 2
++#define mmDCP0_OUTPUT_CSC_C31_C32 0x0586
++#define mmDCP0_OUTPUT_CSC_C31_C32_BASE_IDX 2
++#define mmDCP0_OUTPUT_CSC_C33_C34 0x0587
++#define mmDCP0_OUTPUT_CSC_C33_C34_BASE_IDX 2
++#define mmDCP0_COMM_MATRIXA_TRANS_C11_C12 0x0588
++#define mmDCP0_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2
++#define mmDCP0_COMM_MATRIXA_TRANS_C13_C14 0x0589
++#define mmDCP0_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2
++#define mmDCP0_COMM_MATRIXA_TRANS_C21_C22 0x058a
++#define mmDCP0_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2
++#define mmDCP0_COMM_MATRIXA_TRANS_C23_C24 0x058b
++#define mmDCP0_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2
++#define mmDCP0_COMM_MATRIXA_TRANS_C31_C32 0x058c
++#define mmDCP0_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2
++#define mmDCP0_COMM_MATRIXA_TRANS_C33_C34 0x058d
++#define mmDCP0_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2
++#define mmDCP0_COMM_MATRIXB_TRANS_C11_C12 0x058e
++#define mmDCP0_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2
++#define mmDCP0_COMM_MATRIXB_TRANS_C13_C14 0x058f
++#define mmDCP0_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2
++#define mmDCP0_COMM_MATRIXB_TRANS_C21_C22 0x0590
++#define mmDCP0_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2
++#define mmDCP0_COMM_MATRIXB_TRANS_C23_C24 0x0591
++#define mmDCP0_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2
++#define mmDCP0_COMM_MATRIXB_TRANS_C31_C32 0x0592
++#define mmDCP0_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2
++#define mmDCP0_COMM_MATRIXB_TRANS_C33_C34 0x0593
++#define mmDCP0_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2
++#define mmDCP0_DENORM_CONTROL 0x0594
++#define mmDCP0_DENORM_CONTROL_BASE_IDX 2
++#define mmDCP0_OUT_ROUND_CONTROL 0x0595
++#define mmDCP0_OUT_ROUND_CONTROL_BASE_IDX 2
++#define mmDCP0_OUT_CLAMP_CONTROL_R_CR 0x0596
++#define mmDCP0_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2
++#define mmDCP0_OUT_CLAMP_CONTROL_G_Y 0x0597
++#define mmDCP0_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2
++#define mmDCP0_OUT_CLAMP_CONTROL_B_CB 0x0598
++#define mmDCP0_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2
++#define mmDCP0_KEY_CONTROL 0x0599
++#define mmDCP0_KEY_CONTROL_BASE_IDX 2
++#define mmDCP0_KEY_RANGE_ALPHA 0x059a
++#define mmDCP0_KEY_RANGE_ALPHA_BASE_IDX 2
++#define mmDCP0_KEY_RANGE_RED 0x059b
++#define mmDCP0_KEY_RANGE_RED_BASE_IDX 2
++#define mmDCP0_KEY_RANGE_GREEN 0x059c
++#define mmDCP0_KEY_RANGE_GREEN_BASE_IDX 2
++#define mmDCP0_KEY_RANGE_BLUE 0x059d
++#define mmDCP0_KEY_RANGE_BLUE_BASE_IDX 2
++#define mmDCP0_DEGAMMA_CONTROL 0x059e
++#define mmDCP0_DEGAMMA_CONTROL_BASE_IDX 2
++#define mmDCP0_GAMUT_REMAP_CONTROL 0x059f
++#define mmDCP0_GAMUT_REMAP_CONTROL_BASE_IDX 2
++#define mmDCP0_GAMUT_REMAP_C11_C12 0x05a0
++#define mmDCP0_GAMUT_REMAP_C11_C12_BASE_IDX 2
++#define mmDCP0_GAMUT_REMAP_C13_C14 0x05a1
++#define mmDCP0_GAMUT_REMAP_C13_C14_BASE_IDX 2
++#define mmDCP0_GAMUT_REMAP_C21_C22 0x05a2
++#define mmDCP0_GAMUT_REMAP_C21_C22_BASE_IDX 2
++#define mmDCP0_GAMUT_REMAP_C23_C24 0x05a3
++#define mmDCP0_GAMUT_REMAP_C23_C24_BASE_IDX 2
++#define mmDCP0_GAMUT_REMAP_C31_C32 0x05a4
++#define mmDCP0_GAMUT_REMAP_C31_C32_BASE_IDX 2
++#define mmDCP0_GAMUT_REMAP_C33_C34 0x05a5
++#define mmDCP0_GAMUT_REMAP_C33_C34_BASE_IDX 2
++#define mmDCP0_DCP_SPATIAL_DITHER_CNTL 0x05a6
++#define mmDCP0_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2
++#define mmDCP0_DCP_RANDOM_SEEDS 0x05a7
++#define mmDCP0_DCP_RANDOM_SEEDS_BASE_IDX 2
++#define mmDCP0_DCP_FP_CONVERTED_FIELD 0x05a8
++#define mmDCP0_DCP_FP_CONVERTED_FIELD_BASE_IDX 2
++#define mmDCP0_CUR_CONTROL 0x05a9
++#define mmDCP0_CUR_CONTROL_BASE_IDX 2
++#define mmDCP0_CUR_SURFACE_ADDRESS 0x05aa
++#define mmDCP0_CUR_SURFACE_ADDRESS_BASE_IDX 2
++#define mmDCP0_CUR_SIZE 0x05ab
++#define mmDCP0_CUR_SIZE_BASE_IDX 2
++#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH 0x05ac
++#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
++#define mmDCP0_CUR_POSITION 0x05ad
++#define mmDCP0_CUR_POSITION_BASE_IDX 2
++#define mmDCP0_CUR_HOT_SPOT 0x05ae
++#define mmDCP0_CUR_HOT_SPOT_BASE_IDX 2
++#define mmDCP0_CUR_COLOR1 0x05af
++#define mmDCP0_CUR_COLOR1_BASE_IDX 2
++#define mmDCP0_CUR_COLOR2 0x05b0
++#define mmDCP0_CUR_COLOR2_BASE_IDX 2
++#define mmDCP0_CUR_UPDATE 0x05b1
++#define mmDCP0_CUR_UPDATE_BASE_IDX 2
++#define mmDCP0_CUR_REQUEST_FILTER_CNTL 0x05bb
++#define mmDCP0_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2
++#define mmDCP0_CUR_STEREO_CONTROL 0x05bc
++#define mmDCP0_CUR_STEREO_CONTROL_BASE_IDX 2
++#define mmDCP0_DC_LUT_RW_MODE 0x05be
++#define mmDCP0_DC_LUT_RW_MODE_BASE_IDX 2
++#define mmDCP0_DC_LUT_RW_INDEX 0x05bf
++#define mmDCP0_DC_LUT_RW_INDEX_BASE_IDX 2
++#define mmDCP0_DC_LUT_SEQ_COLOR 0x05c0
++#define mmDCP0_DC_LUT_SEQ_COLOR_BASE_IDX 2
++#define mmDCP0_DC_LUT_PWL_DATA 0x05c1
++#define mmDCP0_DC_LUT_PWL_DATA_BASE_IDX 2
++#define mmDCP0_DC_LUT_30_COLOR 0x05c2
++#define mmDCP0_DC_LUT_30_COLOR_BASE_IDX 2
++#define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE 0x05c3
++#define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2
++#define mmDCP0_DC_LUT_WRITE_EN_MASK 0x05c4
++#define mmDCP0_DC_LUT_WRITE_EN_MASK_BASE_IDX 2
++#define mmDCP0_DC_LUT_AUTOFILL 0x05c5
++#define mmDCP0_DC_LUT_AUTOFILL_BASE_IDX 2
++#define mmDCP0_DC_LUT_CONTROL 0x05c6
++#define mmDCP0_DC_LUT_CONTROL_BASE_IDX 2
++#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE 0x05c7
++#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2
++#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN 0x05c8
++#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2
++#define mmDCP0_DC_LUT_BLACK_OFFSET_RED 0x05c9
++#define mmDCP0_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2
++#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE 0x05ca
++#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2
++#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN 0x05cb
++#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2
++#define mmDCP0_DC_LUT_WHITE_OFFSET_RED 0x05cc
++#define mmDCP0_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2
++#define mmDCP0_DCP_CRC_CONTROL 0x05cd
++#define mmDCP0_DCP_CRC_CONTROL_BASE_IDX 2
++#define mmDCP0_DCP_CRC_MASK 0x05ce
++#define mmDCP0_DCP_CRC_MASK_BASE_IDX 2
++#define mmDCP0_DCP_CRC_CURRENT 0x05cf
++#define mmDCP0_DCP_CRC_CURRENT_BASE_IDX 2
++#define mmDCP0_DVMM_PTE_CONTROL 0x05d0
++#define mmDCP0_DVMM_PTE_CONTROL_BASE_IDX 2
++#define mmDCP0_DCP_CRC_LAST 0x05d1
++#define mmDCP0_DCP_CRC_LAST_BASE_IDX 2
++#define mmDCP0_DVMM_PTE_ARB_CONTROL 0x05d2
++#define mmDCP0_DVMM_PTE_ARB_CONTROL_BASE_IDX 2
++#define mmDCP0_GRPH_FLIP_RATE_CNTL 0x05d4
++#define mmDCP0_GRPH_FLIP_RATE_CNTL_BASE_IDX 2
++#define mmDCP0_DCP_GSL_CONTROL 0x05d5
++#define mmDCP0_DCP_GSL_CONTROL_BASE_IDX 2
++#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x05d6
++#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2
++#define mmDCP0_GRPH_STEREOSYNC_FLIP 0x05dc
++#define mmDCP0_GRPH_STEREOSYNC_FLIP_BASE_IDX 2
++#define mmDCP0_HW_ROTATION 0x05de
++#define mmDCP0_HW_ROTATION_BASE_IDX 2
++#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x05df
++#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2
++#define mmDCP0_REGAMMA_CONTROL 0x05e0
++#define mmDCP0_REGAMMA_CONTROL_BASE_IDX 2
++#define mmDCP0_REGAMMA_LUT_INDEX 0x05e1
++#define mmDCP0_REGAMMA_LUT_INDEX_BASE_IDX 2
++#define mmDCP0_REGAMMA_LUT_DATA 0x05e2
++#define mmDCP0_REGAMMA_LUT_DATA_BASE_IDX 2
++#define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK 0x05e3
++#define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2
++#define mmDCP0_REGAMMA_CNTLA_START_CNTL 0x05e4
++#define mmDCP0_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2
++#define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL 0x05e5
++#define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2
++#define mmDCP0_REGAMMA_CNTLA_END_CNTL1 0x05e6
++#define mmDCP0_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2
++#define mmDCP0_REGAMMA_CNTLA_END_CNTL2 0x05e7
++#define mmDCP0_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2
++#define mmDCP0_REGAMMA_CNTLA_REGION_0_1 0x05e8
++#define mmDCP0_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2
++#define mmDCP0_REGAMMA_CNTLA_REGION_2_3 0x05e9
++#define mmDCP0_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2
++#define mmDCP0_REGAMMA_CNTLA_REGION_4_5 0x05ea
++#define mmDCP0_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2
++#define mmDCP0_REGAMMA_CNTLA_REGION_6_7 0x05eb
++#define mmDCP0_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2
++#define mmDCP0_REGAMMA_CNTLA_REGION_8_9 0x05ec
++#define mmDCP0_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2
++#define mmDCP0_REGAMMA_CNTLA_REGION_10_11 0x05ed
++#define mmDCP0_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2
++#define mmDCP0_REGAMMA_CNTLA_REGION_12_13 0x05ee
++#define mmDCP0_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2
++#define mmDCP0_REGAMMA_CNTLA_REGION_14_15 0x05ef
++#define mmDCP0_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2
++#define mmDCP0_REGAMMA_CNTLB_START_CNTL 0x05f0
++#define mmDCP0_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2
++#define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL 0x05f1
++#define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2
++#define mmDCP0_REGAMMA_CNTLB_END_CNTL1 0x05f2
++#define mmDCP0_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2
++#define mmDCP0_REGAMMA_CNTLB_END_CNTL2 0x05f3
++#define mmDCP0_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2
++#define mmDCP0_REGAMMA_CNTLB_REGION_0_1 0x05f4
++#define mmDCP0_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2
++#define mmDCP0_REGAMMA_CNTLB_REGION_2_3 0x05f5
++#define mmDCP0_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2
++#define mmDCP0_REGAMMA_CNTLB_REGION_4_5 0x05f6
++#define mmDCP0_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2
++#define mmDCP0_REGAMMA_CNTLB_REGION_6_7 0x05f7
++#define mmDCP0_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2
++#define mmDCP0_REGAMMA_CNTLB_REGION_8_9 0x05f8
++#define mmDCP0_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2
++#define mmDCP0_REGAMMA_CNTLB_REGION_10_11 0x05f9
++#define mmDCP0_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2
++#define mmDCP0_REGAMMA_CNTLB_REGION_12_13 0x05fa
++#define mmDCP0_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2
++#define mmDCP0_REGAMMA_CNTLB_REGION_14_15 0x05fb
++#define mmDCP0_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2
++#define mmDCP0_ALPHA_CONTROL 0x05fc
++#define mmDCP0_ALPHA_CONTROL_BASE_IDX 2
++#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x05fd
++#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2
++#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x05fe
++#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
++#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x05ff
++#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2
++#define mmDCP0_GRPH_XDMA_FLIP_TIMEOUT 0x0600
++#define mmDCP0_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2
++#define mmDCP0_GRPH_XDMA_FLIP_AVG_DELAY 0x0601
++#define mmDCP0_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2
++#define mmDCP0_GRPH_SURFACE_COUNTER_CONTROL 0x0602
++#define mmDCP0_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2
++#define mmDCP0_GRPH_SURFACE_COUNTER_OUTPUT 0x0603
++#define mmDCP0_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2
++
++
++// addressBlock: dce_dc_lb0_dispdec
++// base address: 0x0
++#define mmLB0_LB_DATA_FORMAT 0x061a
++#define mmLB0_LB_DATA_FORMAT_BASE_IDX 2
++#define mmLB0_LB_MEMORY_CTRL 0x061b
++#define mmLB0_LB_MEMORY_CTRL_BASE_IDX 2
++#define mmLB0_LB_MEMORY_SIZE_STATUS 0x061c
++#define mmLB0_LB_MEMORY_SIZE_STATUS_BASE_IDX 2
++#define mmLB0_LB_DESKTOP_HEIGHT 0x061d
++#define mmLB0_LB_DESKTOP_HEIGHT_BASE_IDX 2
++#define mmLB0_LB_VLINE_START_END 0x061e
++#define mmLB0_LB_VLINE_START_END_BASE_IDX 2
++#define mmLB0_LB_VLINE2_START_END 0x061f
++#define mmLB0_LB_VLINE2_START_END_BASE_IDX 2
++#define mmLB0_LB_V_COUNTER 0x0620
++#define mmLB0_LB_V_COUNTER_BASE_IDX 2
++#define mmLB0_LB_SNAPSHOT_V_COUNTER 0x0621
++#define mmLB0_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2
++#define mmLB0_LB_INTERRUPT_MASK 0x0622
++#define mmLB0_LB_INTERRUPT_MASK_BASE_IDX 2
++#define mmLB0_LB_VLINE_STATUS 0x0623
++#define mmLB0_LB_VLINE_STATUS_BASE_IDX 2
++#define mmLB0_LB_VLINE2_STATUS 0x0624
++#define mmLB0_LB_VLINE2_STATUS_BASE_IDX 2
++#define mmLB0_LB_VBLANK_STATUS 0x0625
++#define mmLB0_LB_VBLANK_STATUS_BASE_IDX 2
++#define mmLB0_LB_SYNC_RESET_SEL 0x0626
++#define mmLB0_LB_SYNC_RESET_SEL_BASE_IDX 2
++#define mmLB0_LB_BLACK_KEYER_R_CR 0x0627
++#define mmLB0_LB_BLACK_KEYER_R_CR_BASE_IDX 2
++#define mmLB0_LB_BLACK_KEYER_G_Y 0x0628
++#define mmLB0_LB_BLACK_KEYER_G_Y_BASE_IDX 2
++#define mmLB0_LB_BLACK_KEYER_B_CB 0x0629
++#define mmLB0_LB_BLACK_KEYER_B_CB_BASE_IDX 2
++#define mmLB0_LB_KEYER_COLOR_CTRL 0x062a
++#define mmLB0_LB_KEYER_COLOR_CTRL_BASE_IDX 2
++#define mmLB0_LB_KEYER_COLOR_R_CR 0x062b
++#define mmLB0_LB_KEYER_COLOR_R_CR_BASE_IDX 2
++#define mmLB0_LB_KEYER_COLOR_G_Y 0x062c
++#define mmLB0_LB_KEYER_COLOR_G_Y_BASE_IDX 2
++#define mmLB0_LB_KEYER_COLOR_B_CB 0x062d
++#define mmLB0_LB_KEYER_COLOR_B_CB_BASE_IDX 2
++#define mmLB0_LB_KEYER_COLOR_REP_R_CR 0x062e
++#define mmLB0_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2
++#define mmLB0_LB_KEYER_COLOR_REP_G_Y 0x062f
++#define mmLB0_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2
++#define mmLB0_LB_KEYER_COLOR_REP_B_CB 0x0630
++#define mmLB0_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2
++#define mmLB0_LB_BUFFER_LEVEL_STATUS 0x0631
++#define mmLB0_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2
++#define mmLB0_LB_BUFFER_URGENCY_CTRL 0x0632
++#define mmLB0_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2
++#define mmLB0_LB_BUFFER_URGENCY_STATUS 0x0633
++#define mmLB0_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2
++#define mmLB0_LB_BUFFER_STATUS 0x0634
++#define mmLB0_LB_BUFFER_STATUS_BASE_IDX 2
++#define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0x0635
++#define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2
++#define mmLB0_MVP_AFR_FLIP_MODE 0x0636
++#define mmLB0_MVP_AFR_FLIP_MODE_BASE_IDX 2
++#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0x0637
++#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2
++#define mmLB0_MVP_FLIP_LINE_NUM_INSERT 0x0638
++#define mmLB0_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2
++#define mmLB0_DC_MVP_LB_CONTROL 0x0639
++#define mmLB0_DC_MVP_LB_CONTROL_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dcfe0_dispdec
++// base address: 0x0
++#define mmDCFE0_DCFE_CLOCK_CONTROL 0x065a
++#define mmDCFE0_DCFE_CLOCK_CONTROL_BASE_IDX 2
++#define mmDCFE0_DCFE_SOFT_RESET 0x065b
++#define mmDCFE0_DCFE_SOFT_RESET_BASE_IDX 2
++#define mmDCFE0_DCFE_MEM_PWR_CTRL 0x065d
++#define mmDCFE0_DCFE_MEM_PWR_CTRL_BASE_IDX 2
++#define mmDCFE0_DCFE_MEM_PWR_CTRL2 0x065e
++#define mmDCFE0_DCFE_MEM_PWR_CTRL2_BASE_IDX 2
++#define mmDCFE0_DCFE_MEM_PWR_STATUS 0x065f
++#define mmDCFE0_DCFE_MEM_PWR_STATUS_BASE_IDX 2
++#define mmDCFE0_DCFE_MISC 0x0660
++#define mmDCFE0_DCFE_MISC_BASE_IDX 2
++#define mmDCFE0_DCFE_FLUSH 0x0661
++#define mmDCFE0_DCFE_FLUSH_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dc_perfmon3_dispdec
++// base address: 0x1938
++#define mmDC_PERFMON3_PERFCOUNTER_CNTL 0x066e
++#define mmDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX 2
++#define mmDC_PERFMON3_PERFCOUNTER_CNTL2 0x066f
++#define mmDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX 2
++#define mmDC_PERFMON3_PERFCOUNTER_STATE 0x0670
++#define mmDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX 2
++#define mmDC_PERFMON3_PERFMON_CNTL 0x0671
++#define mmDC_PERFMON3_PERFMON_CNTL_BASE_IDX 2
++#define mmDC_PERFMON3_PERFMON_CNTL2 0x0672
++#define mmDC_PERFMON3_PERFMON_CNTL2_BASE_IDX 2
++#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x0673
++#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
++#define mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x0674
++#define mmDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX 2
++#define mmDC_PERFMON3_PERFMON_HI 0x0675
++#define mmDC_PERFMON3_PERFMON_HI_BASE_IDX 2
++#define mmDC_PERFMON3_PERFMON_LOW 0x0676
++#define mmDC_PERFMON3_PERFMON_LOW_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dmif_pg0_dispdec
++// base address: 0x0
++#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 0x067a
++#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
++#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 0x067b
++#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
++#define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 0x067c
++#define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2
++#define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL 0x067d
++#define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2
++#define mmDMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL 0x067e
++#define mmDMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2
++#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL 0x067f
++#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2
++#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL2 0x0680
++#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2
++#define mmDMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL 0x0681
++#define mmDMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2
++#define mmDMIF_PG0_DPG_REPEATER_PROGRAM 0x0682
++#define mmDMIF_PG0_DPG_REPEATER_PROGRAM_BASE_IDX 2
++#define mmDMIF_PG0_DPG_CHK_PRE_PROC_CNTL 0x0686
++#define mmDMIF_PG0_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2
++#define mmDMIF_PG0_DPG_DVMM_STATUS 0x0687
++#define mmDMIF_PG0_DPG_DVMM_STATUS_BASE_IDX 2
++
++
++// addressBlock: dce_dc_scl0_dispdec
++// base address: 0x0
++#define mmSCL0_SCL_COEF_RAM_SELECT 0x069a
++#define mmSCL0_SCL_COEF_RAM_SELECT_BASE_IDX 2
++#define mmSCL0_SCL_COEF_RAM_TAP_DATA 0x069b
++#define mmSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
++#define mmSCL0_SCL_MODE 0x069c
++#define mmSCL0_SCL_MODE_BASE_IDX 2
++#define mmSCL0_SCL_TAP_CONTROL 0x069d
++#define mmSCL0_SCL_TAP_CONTROL_BASE_IDX 2
++#define mmSCL0_SCL_CONTROL 0x069e
++#define mmSCL0_SCL_CONTROL_BASE_IDX 2
++#define mmSCL0_SCL_BYPASS_CONTROL 0x069f
++#define mmSCL0_SCL_BYPASS_CONTROL_BASE_IDX 2
++#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x06a0
++#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
++#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL 0x06a1
++#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2
++#define mmSCL0_SCL_HORZ_FILTER_CONTROL 0x06a2
++#define mmSCL0_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2
++#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x06a3
++#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
++#define mmSCL0_SCL_HORZ_FILTER_INIT 0x06a4
++#define mmSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2
++#define mmSCL0_SCL_VERT_FILTER_CONTROL 0x06a5
++#define mmSCL0_SCL_VERT_FILTER_CONTROL_BASE_IDX 2
++#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x06a6
++#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
++#define mmSCL0_SCL_VERT_FILTER_INIT 0x06a7
++#define mmSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2
++#define mmSCL0_SCL_VERT_FILTER_INIT_BOT 0x06a8
++#define mmSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
++#define mmSCL0_SCL_ROUND_OFFSET 0x06a9
++#define mmSCL0_SCL_ROUND_OFFSET_BASE_IDX 2
++#define mmSCL0_SCL_UPDATE 0x06aa
++#define mmSCL0_SCL_UPDATE_BASE_IDX 2
++#define mmSCL0_SCL_F_SHARP_CONTROL 0x06ab
++#define mmSCL0_SCL_F_SHARP_CONTROL_BASE_IDX 2
++#define mmSCL0_SCL_ALU_CONTROL 0x06ac
++#define mmSCL0_SCL_ALU_CONTROL_BASE_IDX 2
++#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0x06ad
++#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
++#define mmSCL0_VIEWPORT_START_SECONDARY 0x06ae
++#define mmSCL0_VIEWPORT_START_SECONDARY_BASE_IDX 2
++#define mmSCL0_VIEWPORT_START 0x06af
++#define mmSCL0_VIEWPORT_START_BASE_IDX 2
++#define mmSCL0_VIEWPORT_SIZE 0x06b0
++#define mmSCL0_VIEWPORT_SIZE_BASE_IDX 2
++#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT 0x06b1
++#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
++#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM 0x06b2
++#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
++#define mmSCL0_SCL_MODE_CHANGE_DET1 0x06b3
++#define mmSCL0_SCL_MODE_CHANGE_DET1_BASE_IDX 2
++#define mmSCL0_SCL_MODE_CHANGE_DET2 0x06b4
++#define mmSCL0_SCL_MODE_CHANGE_DET2_BASE_IDX 2
++#define mmSCL0_SCL_MODE_CHANGE_DET3 0x06b5
++#define mmSCL0_SCL_MODE_CHANGE_DET3_BASE_IDX 2
++#define mmSCL0_SCL_MODE_CHANGE_MASK 0x06b6
++#define mmSCL0_SCL_MODE_CHANGE_MASK_BASE_IDX 2
++
++
++// addressBlock: dce_dc_blnd0_dispdec
++// base address: 0x0
++#define mmBLND0_BLND_CONTROL 0x06c7
++#define mmBLND0_BLND_CONTROL_BASE_IDX 2
++#define mmBLND0_BLND_SM_CONTROL2 0x06c8
++#define mmBLND0_BLND_SM_CONTROL2_BASE_IDX 2
++#define mmBLND0_BLND_CONTROL2 0x06c9
++#define mmBLND0_BLND_CONTROL2_BASE_IDX 2
++#define mmBLND0_BLND_UPDATE 0x06ca
++#define mmBLND0_BLND_UPDATE_BASE_IDX 2
++#define mmBLND0_BLND_UNDERFLOW_INTERRUPT 0x06cb
++#define mmBLND0_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2
++#define mmBLND0_BLND_V_UPDATE_LOCK 0x06cc
++#define mmBLND0_BLND_V_UPDATE_LOCK_BASE_IDX 2
++#define mmBLND0_BLND_REG_UPDATE_STATUS 0x06cd
++#define mmBLND0_BLND_REG_UPDATE_STATUS_BASE_IDX 2
++
++
++// addressBlock: dce_dc_crtc0_dispdec
++// base address: 0x0
++#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM 0x06d2
++#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2
++#define mmCRTC0_CRTC_H_TOTAL 0x06d3
++#define mmCRTC0_CRTC_H_TOTAL_BASE_IDX 2
++#define mmCRTC0_CRTC_H_BLANK_START_END 0x06d4
++#define mmCRTC0_CRTC_H_BLANK_START_END_BASE_IDX 2
++#define mmCRTC0_CRTC_H_SYNC_A 0x06d5
++#define mmCRTC0_CRTC_H_SYNC_A_BASE_IDX 2
++#define mmCRTC0_CRTC_H_SYNC_A_CNTL 0x06d6
++#define mmCRTC0_CRTC_H_SYNC_A_CNTL_BASE_IDX 2
++#define mmCRTC0_CRTC_H_SYNC_B 0x06d7
++#define mmCRTC0_CRTC_H_SYNC_B_BASE_IDX 2
++#define mmCRTC0_CRTC_H_SYNC_B_CNTL 0x06d8
++#define mmCRTC0_CRTC_H_SYNC_B_CNTL_BASE_IDX 2
++#define mmCRTC0_CRTC_VBI_END 0x06d9
++#define mmCRTC0_CRTC_VBI_END_BASE_IDX 2
++#define mmCRTC0_CRTC_V_TOTAL 0x06da
++#define mmCRTC0_CRTC_V_TOTAL_BASE_IDX 2
++#define mmCRTC0_CRTC_V_TOTAL_MIN 0x06db
++#define mmCRTC0_CRTC_V_TOTAL_MIN_BASE_IDX 2
++#define mmCRTC0_CRTC_V_TOTAL_MAX 0x06dc
++#define mmCRTC0_CRTC_V_TOTAL_MAX_BASE_IDX 2
++#define mmCRTC0_CRTC_V_TOTAL_CONTROL 0x06dd
++#define mmCRTC0_CRTC_V_TOTAL_CONTROL_BASE_IDX 2
++#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS 0x06de
++#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2
++#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS 0x06df
++#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2
++#define mmCRTC0_CRTC_V_BLANK_START_END 0x06e0
++#define mmCRTC0_CRTC_V_BLANK_START_END_BASE_IDX 2
++#define mmCRTC0_CRTC_V_SYNC_A 0x06e1
++#define mmCRTC0_CRTC_V_SYNC_A_BASE_IDX 2
++#define mmCRTC0_CRTC_V_SYNC_A_CNTL 0x06e2
++#define mmCRTC0_CRTC_V_SYNC_A_CNTL_BASE_IDX 2
++#define mmCRTC0_CRTC_V_SYNC_B 0x06e3
++#define mmCRTC0_CRTC_V_SYNC_B_BASE_IDX 2
++#define mmCRTC0_CRTC_V_SYNC_B_CNTL 0x06e4
++#define mmCRTC0_CRTC_V_SYNC_B_CNTL_BASE_IDX 2
++#define mmCRTC0_CRTC_DTMTEST_CNTL 0x06e5
++#define mmCRTC0_CRTC_DTMTEST_CNTL_BASE_IDX 2
++#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION 0x06e6
++#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2
++#define mmCRTC0_CRTC_TRIGA_CNTL 0x06e7
++#define mmCRTC0_CRTC_TRIGA_CNTL_BASE_IDX 2
++#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG 0x06e8
++#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2
++#define mmCRTC0_CRTC_TRIGB_CNTL 0x06e9
++#define mmCRTC0_CRTC_TRIGB_CNTL_BASE_IDX 2
++#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG 0x06ea
++#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2
++#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL 0x06eb
++#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
++#define mmCRTC0_CRTC_FLOW_CONTROL 0x06ec
++#define mmCRTC0_CRTC_FLOW_CONTROL_BASE_IDX 2
++#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE 0x06ed
++#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
++#define mmCRTC0_CRTC_AVSYNC_COUNTER 0x06ee
++#define mmCRTC0_CRTC_AVSYNC_COUNTER_BASE_IDX 2
++#define mmCRTC0_CRTC_CONTROL 0x06ef
++#define mmCRTC0_CRTC_CONTROL_BASE_IDX 2
++#define mmCRTC0_CRTC_BLANK_CONTROL 0x06f0
++#define mmCRTC0_CRTC_BLANK_CONTROL_BASE_IDX 2
++#define mmCRTC0_CRTC_INTERLACE_CONTROL 0x06f1
++#define mmCRTC0_CRTC_INTERLACE_CONTROL_BASE_IDX 2
++#define mmCRTC0_CRTC_INTERLACE_STATUS 0x06f2
++#define mmCRTC0_CRTC_INTERLACE_STATUS_BASE_IDX 2
++#define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL 0x06f3
++#define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2
++#define mmCRTC0_CRTC_PIXEL_DATA_READBACK0 0x06f4
++#define mmCRTC0_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2
++#define mmCRTC0_CRTC_PIXEL_DATA_READBACK1 0x06f5
++#define mmCRTC0_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2
++#define mmCRTC0_CRTC_STATUS 0x06f6
++#define mmCRTC0_CRTC_STATUS_BASE_IDX 2
++#define mmCRTC0_CRTC_STATUS_POSITION 0x06f7
++#define mmCRTC0_CRTC_STATUS_POSITION_BASE_IDX 2
++#define mmCRTC0_CRTC_NOM_VERT_POSITION 0x06f8
++#define mmCRTC0_CRTC_NOM_VERT_POSITION_BASE_IDX 2
++#define mmCRTC0_CRTC_STATUS_FRAME_COUNT 0x06f9
++#define mmCRTC0_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2
++#define mmCRTC0_CRTC_STATUS_VF_COUNT 0x06fa
++#define mmCRTC0_CRTC_STATUS_VF_COUNT_BASE_IDX 2
++#define mmCRTC0_CRTC_STATUS_HV_COUNT 0x06fb
++#define mmCRTC0_CRTC_STATUS_HV_COUNT_BASE_IDX 2
++#define mmCRTC0_CRTC_COUNT_CONTROL 0x06fc
++#define mmCRTC0_CRTC_COUNT_CONTROL_BASE_IDX 2
++#define mmCRTC0_CRTC_COUNT_RESET 0x06fd
++#define mmCRTC0_CRTC_COUNT_RESET_BASE_IDX 2
++#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x06fe
++#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
++#define mmCRTC0_CRTC_VERT_SYNC_CONTROL 0x06ff
++#define mmCRTC0_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2
++#define mmCRTC0_CRTC_STEREO_STATUS 0x0700
++#define mmCRTC0_CRTC_STEREO_STATUS_BASE_IDX 2
++#define mmCRTC0_CRTC_STEREO_CONTROL 0x0701
++#define mmCRTC0_CRTC_STEREO_CONTROL_BASE_IDX 2
++#define mmCRTC0_CRTC_SNAPSHOT_STATUS 0x0702
++#define mmCRTC0_CRTC_SNAPSHOT_STATUS_BASE_IDX 2
++#define mmCRTC0_CRTC_SNAPSHOT_CONTROL 0x0703
++#define mmCRTC0_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2
++#define mmCRTC0_CRTC_SNAPSHOT_POSITION 0x0704
++#define mmCRTC0_CRTC_SNAPSHOT_POSITION_BASE_IDX 2
++#define mmCRTC0_CRTC_SNAPSHOT_FRAME 0x0705
++#define mmCRTC0_CRTC_SNAPSHOT_FRAME_BASE_IDX 2
++#define mmCRTC0_CRTC_START_LINE_CONTROL 0x0706
++#define mmCRTC0_CRTC_START_LINE_CONTROL_BASE_IDX 2
++#define mmCRTC0_CRTC_INTERRUPT_CONTROL 0x0707
++#define mmCRTC0_CRTC_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmCRTC0_CRTC_UPDATE_LOCK 0x0708
++#define mmCRTC0_CRTC_UPDATE_LOCK_BASE_IDX 2
++#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL 0x0709
++#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
++#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x070a
++#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2
++#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x070b
++#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2
++#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS 0x070c
++#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2
++#define mmCRTC0_CRTC_TEST_PATTERN_COLOR 0x070d
++#define mmCRTC0_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2
++#define mmCRTC0_CRTC_MASTER_UPDATE_LOCK 0x070e
++#define mmCRTC0_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2
++#define mmCRTC0_CRTC_MASTER_UPDATE_MODE 0x070f
++#define mmCRTC0_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2
++#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT 0x0710
++#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2
++#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x0711
++#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2
++#define mmCRTC0_CRTC_MVP_STATUS 0x0712
++#define mmCRTC0_CRTC_MVP_STATUS_BASE_IDX 2
++#define mmCRTC0_CRTC_MASTER_EN 0x0713
++#define mmCRTC0_CRTC_MASTER_EN_BASE_IDX 2
++#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT 0x0714
++#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2
++#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS 0x0715
++#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2
++#define mmCRTC0_CRTC_OVERSCAN_COLOR 0x0717
++#define mmCRTC0_CRTC_OVERSCAN_COLOR_BASE_IDX 2
++#define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT 0x0718
++#define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2
++#define mmCRTC0_CRTC_BLANK_DATA_COLOR 0x0719
++#define mmCRTC0_CRTC_BLANK_DATA_COLOR_BASE_IDX 2
++#define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT 0x071a
++#define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2
++#define mmCRTC0_CRTC_BLACK_COLOR 0x071b
++#define mmCRTC0_CRTC_BLACK_COLOR_BASE_IDX 2
++#define mmCRTC0_CRTC_BLACK_COLOR_EXT 0x071c
++#define mmCRTC0_CRTC_BLACK_COLOR_EXT_BASE_IDX 2
++#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION 0x071d
++#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
++#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x071e
++#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
++#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION 0x071f
++#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
++#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x0720
++#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
++#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION 0x0721
++#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
++#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x0722
++#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
++#define mmCRTC0_CRTC_CRC_CNTL 0x0723
++#define mmCRTC0_CRTC_CRC_CNTL_BASE_IDX 2
++#define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL 0x0724
++#define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
++#define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL 0x0725
++#define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
++#define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL 0x0726
++#define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
++#define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL 0x0727
++#define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
++#define mmCRTC0_CRTC_CRC0_DATA_RG 0x0728
++#define mmCRTC0_CRTC_CRC0_DATA_RG_BASE_IDX 2
++#define mmCRTC0_CRTC_CRC0_DATA_B 0x0729
++#define mmCRTC0_CRTC_CRC0_DATA_B_BASE_IDX 2
++#define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL 0x072a
++#define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
++#define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL 0x072b
++#define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
++#define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL 0x072c
++#define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
++#define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL 0x072d
++#define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
++#define mmCRTC0_CRTC_CRC1_DATA_RG 0x072e
++#define mmCRTC0_CRTC_CRC1_DATA_RG_BASE_IDX 2
++#define mmCRTC0_CRTC_CRC1_DATA_B 0x072f
++#define mmCRTC0_CRTC_CRC1_DATA_B_BASE_IDX 2
++#define mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL 0x0730
++#define mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2
++#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x0731
++#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2
++#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x0732
++#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2
++#define mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x0733
++#define mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x0734
++#define mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x0735
++#define mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL 0x0736
++#define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2
++#define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL 0x0737
++#define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2
++#define mmCRTC0_CRTC_GSL_VSYNC_GAP 0x0738
++#define mmCRTC0_CRTC_GSL_VSYNC_GAP_BASE_IDX 2
++#define mmCRTC0_CRTC_GSL_WINDOW 0x0739
++#define mmCRTC0_CRTC_GSL_WINDOW_BASE_IDX 2
++#define mmCRTC0_CRTC_GSL_CONTROL 0x073a
++#define mmCRTC0_CRTC_GSL_CONTROL_BASE_IDX 2
++#define mmCRTC0_CRTC_RANGE_TIMING_INT_STATUS 0x073d
++#define mmCRTC0_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2
++#define mmCRTC0_CRTC_DRR_CONTROL 0x073e
++#define mmCRTC0_CRTC_DRR_CONTROL_BASE_IDX 2
++
++
++// addressBlock: dce_dc_fmt0_dispdec
++// base address: 0x0
++#define mmFMT0_FMT_CLAMP_COMPONENT_R 0x0742
++#define mmFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
++#define mmFMT0_FMT_CLAMP_COMPONENT_G 0x0743
++#define mmFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
++#define mmFMT0_FMT_CLAMP_COMPONENT_B 0x0744
++#define mmFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
++#define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x0745
++#define mmFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
++#define mmFMT0_FMT_CONTROL 0x0746
++#define mmFMT0_FMT_CONTROL_BASE_IDX 2
++#define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x0747
++#define mmFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
++#define mmFMT0_FMT_DITHER_RAND_R_SEED 0x0748
++#define mmFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
++#define mmFMT0_FMT_DITHER_RAND_G_SEED 0x0749
++#define mmFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
++#define mmFMT0_FMT_DITHER_RAND_B_SEED 0x074a
++#define mmFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
++#define mmFMT0_FMT_CLAMP_CNTL 0x074e
++#define mmFMT0_FMT_CLAMP_CNTL_BASE_IDX 2
++#define mmFMT0_FMT_CRC_CNTL 0x074f
++#define mmFMT0_FMT_CRC_CNTL_BASE_IDX 2
++#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK 0x0750
++#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
++#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x0751
++#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
++#define mmFMT0_FMT_CRC_SIG_RED_GREEN 0x0752
++#define mmFMT0_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2
++#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL 0x0753
++#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2
++#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x0754
++#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
++#define mmFMT0_FMT_420_HBLANK_EARLY_START 0x0755
++#define mmFMT0_FMT_420_HBLANK_EARLY_START_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dcp1_dispdec
++// base address: 0x800
++#define mmDCP1_GRPH_ENABLE 0x075a
++#define mmDCP1_GRPH_ENABLE_BASE_IDX 2
++#define mmDCP1_GRPH_CONTROL 0x075b
++#define mmDCP1_GRPH_CONTROL_BASE_IDX 2
++#define mmDCP1_GRPH_LUT_10BIT_BYPASS 0x075c
++#define mmDCP1_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2
++#define mmDCP1_GRPH_SWAP_CNTL 0x075d
++#define mmDCP1_GRPH_SWAP_CNTL_BASE_IDX 2
++#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS 0x075e
++#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
++#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS 0x075f
++#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
++#define mmDCP1_GRPH_PITCH 0x0760
++#define mmDCP1_GRPH_PITCH_BASE_IDX 2
++#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0761
++#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
++#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0762
++#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
++#define mmDCP1_GRPH_SURFACE_OFFSET_X 0x0763
++#define mmDCP1_GRPH_SURFACE_OFFSET_X_BASE_IDX 2
++#define mmDCP1_GRPH_SURFACE_OFFSET_Y 0x0764
++#define mmDCP1_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2
++#define mmDCP1_GRPH_X_START 0x0765
++#define mmDCP1_GRPH_X_START_BASE_IDX 2
++#define mmDCP1_GRPH_Y_START 0x0766
++#define mmDCP1_GRPH_Y_START_BASE_IDX 2
++#define mmDCP1_GRPH_X_END 0x0767
++#define mmDCP1_GRPH_X_END_BASE_IDX 2
++#define mmDCP1_GRPH_Y_END 0x0768
++#define mmDCP1_GRPH_Y_END_BASE_IDX 2
++#define mmDCP1_INPUT_GAMMA_CONTROL 0x0769
++#define mmDCP1_INPUT_GAMMA_CONTROL_BASE_IDX 2
++#define mmDCP1_GRPH_UPDATE 0x076a
++#define mmDCP1_GRPH_UPDATE_BASE_IDX 2
++#define mmDCP1_GRPH_FLIP_CONTROL 0x076b
++#define mmDCP1_GRPH_FLIP_CONTROL_BASE_IDX 2
++#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE 0x076c
++#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2
++#define mmDCP1_GRPH_DFQ_CONTROL 0x076d
++#define mmDCP1_GRPH_DFQ_CONTROL_BASE_IDX 2
++#define mmDCP1_GRPH_DFQ_STATUS 0x076e
++#define mmDCP1_GRPH_DFQ_STATUS_BASE_IDX 2
++#define mmDCP1_GRPH_INTERRUPT_STATUS 0x076f
++#define mmDCP1_GRPH_INTERRUPT_STATUS_BASE_IDX 2
++#define mmDCP1_GRPH_INTERRUPT_CONTROL 0x0770
++#define mmDCP1_GRPH_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0771
++#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2
++#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS 0x0772
++#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2
++#define mmDCP1_GRPH_COMPRESS_PITCH 0x0773
++#define mmDCP1_GRPH_COMPRESS_PITCH_BASE_IDX 2
++#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0774
++#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2
++#define mmDCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0775
++#define mmDCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2
++#define mmDCP1_PRESCALE_GRPH_CONTROL 0x0776
++#define mmDCP1_PRESCALE_GRPH_CONTROL_BASE_IDX 2
++#define mmDCP1_PRESCALE_VALUES_GRPH_R 0x0777
++#define mmDCP1_PRESCALE_VALUES_GRPH_R_BASE_IDX 2
++#define mmDCP1_PRESCALE_VALUES_GRPH_G 0x0778
++#define mmDCP1_PRESCALE_VALUES_GRPH_G_BASE_IDX 2
++#define mmDCP1_PRESCALE_VALUES_GRPH_B 0x0779
++#define mmDCP1_PRESCALE_VALUES_GRPH_B_BASE_IDX 2
++#define mmDCP1_INPUT_CSC_CONTROL 0x077a
++#define mmDCP1_INPUT_CSC_CONTROL_BASE_IDX 2
++#define mmDCP1_INPUT_CSC_C11_C12 0x077b
++#define mmDCP1_INPUT_CSC_C11_C12_BASE_IDX 2
++#define mmDCP1_INPUT_CSC_C13_C14 0x077c
++#define mmDCP1_INPUT_CSC_C13_C14_BASE_IDX 2
++#define mmDCP1_INPUT_CSC_C21_C22 0x077d
++#define mmDCP1_INPUT_CSC_C21_C22_BASE_IDX 2
++#define mmDCP1_INPUT_CSC_C23_C24 0x077e
++#define mmDCP1_INPUT_CSC_C23_C24_BASE_IDX 2
++#define mmDCP1_INPUT_CSC_C31_C32 0x077f
++#define mmDCP1_INPUT_CSC_C31_C32_BASE_IDX 2
++#define mmDCP1_INPUT_CSC_C33_C34 0x0780
++#define mmDCP1_INPUT_CSC_C33_C34_BASE_IDX 2
++#define mmDCP1_OUTPUT_CSC_CONTROL 0x0781
++#define mmDCP1_OUTPUT_CSC_CONTROL_BASE_IDX 2
++#define mmDCP1_OUTPUT_CSC_C11_C12 0x0782
++#define mmDCP1_OUTPUT_CSC_C11_C12_BASE_IDX 2
++#define mmDCP1_OUTPUT_CSC_C13_C14 0x0783
++#define mmDCP1_OUTPUT_CSC_C13_C14_BASE_IDX 2
++#define mmDCP1_OUTPUT_CSC_C21_C22 0x0784
++#define mmDCP1_OUTPUT_CSC_C21_C22_BASE_IDX 2
++#define mmDCP1_OUTPUT_CSC_C23_C24 0x0785
++#define mmDCP1_OUTPUT_CSC_C23_C24_BASE_IDX 2
++#define mmDCP1_OUTPUT_CSC_C31_C32 0x0786
++#define mmDCP1_OUTPUT_CSC_C31_C32_BASE_IDX 2
++#define mmDCP1_OUTPUT_CSC_C33_C34 0x0787
++#define mmDCP1_OUTPUT_CSC_C33_C34_BASE_IDX 2
++#define mmDCP1_COMM_MATRIXA_TRANS_C11_C12 0x0788
++#define mmDCP1_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2
++#define mmDCP1_COMM_MATRIXA_TRANS_C13_C14 0x0789
++#define mmDCP1_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2
++#define mmDCP1_COMM_MATRIXA_TRANS_C21_C22 0x078a
++#define mmDCP1_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2
++#define mmDCP1_COMM_MATRIXA_TRANS_C23_C24 0x078b
++#define mmDCP1_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2
++#define mmDCP1_COMM_MATRIXA_TRANS_C31_C32 0x078c
++#define mmDCP1_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2
++#define mmDCP1_COMM_MATRIXA_TRANS_C33_C34 0x078d
++#define mmDCP1_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2
++#define mmDCP1_COMM_MATRIXB_TRANS_C11_C12 0x078e
++#define mmDCP1_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2
++#define mmDCP1_COMM_MATRIXB_TRANS_C13_C14 0x078f
++#define mmDCP1_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2
++#define mmDCP1_COMM_MATRIXB_TRANS_C21_C22 0x0790
++#define mmDCP1_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2
++#define mmDCP1_COMM_MATRIXB_TRANS_C23_C24 0x0791
++#define mmDCP1_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2
++#define mmDCP1_COMM_MATRIXB_TRANS_C31_C32 0x0792
++#define mmDCP1_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2
++#define mmDCP1_COMM_MATRIXB_TRANS_C33_C34 0x0793
++#define mmDCP1_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2
++#define mmDCP1_DENORM_CONTROL 0x0794
++#define mmDCP1_DENORM_CONTROL_BASE_IDX 2
++#define mmDCP1_OUT_ROUND_CONTROL 0x0795
++#define mmDCP1_OUT_ROUND_CONTROL_BASE_IDX 2
++#define mmDCP1_OUT_CLAMP_CONTROL_R_CR 0x0796
++#define mmDCP1_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2
++#define mmDCP1_OUT_CLAMP_CONTROL_G_Y 0x0797
++#define mmDCP1_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2
++#define mmDCP1_OUT_CLAMP_CONTROL_B_CB 0x0798
++#define mmDCP1_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2
++#define mmDCP1_KEY_CONTROL 0x0799
++#define mmDCP1_KEY_CONTROL_BASE_IDX 2
++#define mmDCP1_KEY_RANGE_ALPHA 0x079a
++#define mmDCP1_KEY_RANGE_ALPHA_BASE_IDX 2
++#define mmDCP1_KEY_RANGE_RED 0x079b
++#define mmDCP1_KEY_RANGE_RED_BASE_IDX 2
++#define mmDCP1_KEY_RANGE_GREEN 0x079c
++#define mmDCP1_KEY_RANGE_GREEN_BASE_IDX 2
++#define mmDCP1_KEY_RANGE_BLUE 0x079d
++#define mmDCP1_KEY_RANGE_BLUE_BASE_IDX 2
++#define mmDCP1_DEGAMMA_CONTROL 0x079e
++#define mmDCP1_DEGAMMA_CONTROL_BASE_IDX 2
++#define mmDCP1_GAMUT_REMAP_CONTROL 0x079f
++#define mmDCP1_GAMUT_REMAP_CONTROL_BASE_IDX 2
++#define mmDCP1_GAMUT_REMAP_C11_C12 0x07a0
++#define mmDCP1_GAMUT_REMAP_C11_C12_BASE_IDX 2
++#define mmDCP1_GAMUT_REMAP_C13_C14 0x07a1
++#define mmDCP1_GAMUT_REMAP_C13_C14_BASE_IDX 2
++#define mmDCP1_GAMUT_REMAP_C21_C22 0x07a2
++#define mmDCP1_GAMUT_REMAP_C21_C22_BASE_IDX 2
++#define mmDCP1_GAMUT_REMAP_C23_C24 0x07a3
++#define mmDCP1_GAMUT_REMAP_C23_C24_BASE_IDX 2
++#define mmDCP1_GAMUT_REMAP_C31_C32 0x07a4
++#define mmDCP1_GAMUT_REMAP_C31_C32_BASE_IDX 2
++#define mmDCP1_GAMUT_REMAP_C33_C34 0x07a5
++#define mmDCP1_GAMUT_REMAP_C33_C34_BASE_IDX 2
++#define mmDCP1_DCP_SPATIAL_DITHER_CNTL 0x07a6
++#define mmDCP1_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2
++#define mmDCP1_DCP_RANDOM_SEEDS 0x07a7
++#define mmDCP1_DCP_RANDOM_SEEDS_BASE_IDX 2
++#define mmDCP1_DCP_FP_CONVERTED_FIELD 0x07a8
++#define mmDCP1_DCP_FP_CONVERTED_FIELD_BASE_IDX 2
++#define mmDCP1_CUR_CONTROL 0x07a9
++#define mmDCP1_CUR_CONTROL_BASE_IDX 2
++#define mmDCP1_CUR_SURFACE_ADDRESS 0x07aa
++#define mmDCP1_CUR_SURFACE_ADDRESS_BASE_IDX 2
++#define mmDCP1_CUR_SIZE 0x07ab
++#define mmDCP1_CUR_SIZE_BASE_IDX 2
++#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH 0x07ac
++#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
++#define mmDCP1_CUR_POSITION 0x07ad
++#define mmDCP1_CUR_POSITION_BASE_IDX 2
++#define mmDCP1_CUR_HOT_SPOT 0x07ae
++#define mmDCP1_CUR_HOT_SPOT_BASE_IDX 2
++#define mmDCP1_CUR_COLOR1 0x07af
++#define mmDCP1_CUR_COLOR1_BASE_IDX 2
++#define mmDCP1_CUR_COLOR2 0x07b0
++#define mmDCP1_CUR_COLOR2_BASE_IDX 2
++#define mmDCP1_CUR_UPDATE 0x07b1
++#define mmDCP1_CUR_UPDATE_BASE_IDX 2
++#define mmDCP1_CUR_REQUEST_FILTER_CNTL 0x07bb
++#define mmDCP1_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2
++#define mmDCP1_CUR_STEREO_CONTROL 0x07bc
++#define mmDCP1_CUR_STEREO_CONTROL_BASE_IDX 2
++#define mmDCP1_DC_LUT_RW_MODE 0x07be
++#define mmDCP1_DC_LUT_RW_MODE_BASE_IDX 2
++#define mmDCP1_DC_LUT_RW_INDEX 0x07bf
++#define mmDCP1_DC_LUT_RW_INDEX_BASE_IDX 2
++#define mmDCP1_DC_LUT_SEQ_COLOR 0x07c0
++#define mmDCP1_DC_LUT_SEQ_COLOR_BASE_IDX 2
++#define mmDCP1_DC_LUT_PWL_DATA 0x07c1
++#define mmDCP1_DC_LUT_PWL_DATA_BASE_IDX 2
++#define mmDCP1_DC_LUT_30_COLOR 0x07c2
++#define mmDCP1_DC_LUT_30_COLOR_BASE_IDX 2
++#define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE 0x07c3
++#define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2
++#define mmDCP1_DC_LUT_WRITE_EN_MASK 0x07c4
++#define mmDCP1_DC_LUT_WRITE_EN_MASK_BASE_IDX 2
++#define mmDCP1_DC_LUT_AUTOFILL 0x07c5
++#define mmDCP1_DC_LUT_AUTOFILL_BASE_IDX 2
++#define mmDCP1_DC_LUT_CONTROL 0x07c6
++#define mmDCP1_DC_LUT_CONTROL_BASE_IDX 2
++#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE 0x07c7
++#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2
++#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN 0x07c8
++#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2
++#define mmDCP1_DC_LUT_BLACK_OFFSET_RED 0x07c9
++#define mmDCP1_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2
++#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE 0x07ca
++#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2
++#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN 0x07cb
++#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2
++#define mmDCP1_DC_LUT_WHITE_OFFSET_RED 0x07cc
++#define mmDCP1_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2
++#define mmDCP1_DCP_CRC_CONTROL 0x07cd
++#define mmDCP1_DCP_CRC_CONTROL_BASE_IDX 2
++#define mmDCP1_DCP_CRC_MASK 0x07ce
++#define mmDCP1_DCP_CRC_MASK_BASE_IDX 2
++#define mmDCP1_DCP_CRC_CURRENT 0x07cf
++#define mmDCP1_DCP_CRC_CURRENT_BASE_IDX 2
++#define mmDCP1_DVMM_PTE_CONTROL 0x07d0
++#define mmDCP1_DVMM_PTE_CONTROL_BASE_IDX 2
++#define mmDCP1_DCP_CRC_LAST 0x07d1
++#define mmDCP1_DCP_CRC_LAST_BASE_IDX 2
++#define mmDCP1_DVMM_PTE_ARB_CONTROL 0x07d2
++#define mmDCP1_DVMM_PTE_ARB_CONTROL_BASE_IDX 2
++#define mmDCP1_GRPH_FLIP_RATE_CNTL 0x07d4
++#define mmDCP1_GRPH_FLIP_RATE_CNTL_BASE_IDX 2
++#define mmDCP1_DCP_GSL_CONTROL 0x07d5
++#define mmDCP1_DCP_GSL_CONTROL_BASE_IDX 2
++#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x07d6
++#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2
++#define mmDCP1_GRPH_STEREOSYNC_FLIP 0x07dc
++#define mmDCP1_GRPH_STEREOSYNC_FLIP_BASE_IDX 2
++#define mmDCP1_HW_ROTATION 0x07de
++#define mmDCP1_HW_ROTATION_BASE_IDX 2
++#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x07df
++#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2
++#define mmDCP1_REGAMMA_CONTROL 0x07e0
++#define mmDCP1_REGAMMA_CONTROL_BASE_IDX 2
++#define mmDCP1_REGAMMA_LUT_INDEX 0x07e1
++#define mmDCP1_REGAMMA_LUT_INDEX_BASE_IDX 2
++#define mmDCP1_REGAMMA_LUT_DATA 0x07e2
++#define mmDCP1_REGAMMA_LUT_DATA_BASE_IDX 2
++#define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK 0x07e3
++#define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2
++#define mmDCP1_REGAMMA_CNTLA_START_CNTL 0x07e4
++#define mmDCP1_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2
++#define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL 0x07e5
++#define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2
++#define mmDCP1_REGAMMA_CNTLA_END_CNTL1 0x07e6
++#define mmDCP1_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2
++#define mmDCP1_REGAMMA_CNTLA_END_CNTL2 0x07e7
++#define mmDCP1_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2
++#define mmDCP1_REGAMMA_CNTLA_REGION_0_1 0x07e8
++#define mmDCP1_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2
++#define mmDCP1_REGAMMA_CNTLA_REGION_2_3 0x07e9
++#define mmDCP1_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2
++#define mmDCP1_REGAMMA_CNTLA_REGION_4_5 0x07ea
++#define mmDCP1_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2
++#define mmDCP1_REGAMMA_CNTLA_REGION_6_7 0x07eb
++#define mmDCP1_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2
++#define mmDCP1_REGAMMA_CNTLA_REGION_8_9 0x07ec
++#define mmDCP1_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2
++#define mmDCP1_REGAMMA_CNTLA_REGION_10_11 0x07ed
++#define mmDCP1_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2
++#define mmDCP1_REGAMMA_CNTLA_REGION_12_13 0x07ee
++#define mmDCP1_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2
++#define mmDCP1_REGAMMA_CNTLA_REGION_14_15 0x07ef
++#define mmDCP1_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2
++#define mmDCP1_REGAMMA_CNTLB_START_CNTL 0x07f0
++#define mmDCP1_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2
++#define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL 0x07f1
++#define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2
++#define mmDCP1_REGAMMA_CNTLB_END_CNTL1 0x07f2
++#define mmDCP1_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2
++#define mmDCP1_REGAMMA_CNTLB_END_CNTL2 0x07f3
++#define mmDCP1_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2
++#define mmDCP1_REGAMMA_CNTLB_REGION_0_1 0x07f4
++#define mmDCP1_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2
++#define mmDCP1_REGAMMA_CNTLB_REGION_2_3 0x07f5
++#define mmDCP1_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2
++#define mmDCP1_REGAMMA_CNTLB_REGION_4_5 0x07f6
++#define mmDCP1_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2
++#define mmDCP1_REGAMMA_CNTLB_REGION_6_7 0x07f7
++#define mmDCP1_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2
++#define mmDCP1_REGAMMA_CNTLB_REGION_8_9 0x07f8
++#define mmDCP1_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2
++#define mmDCP1_REGAMMA_CNTLB_REGION_10_11 0x07f9
++#define mmDCP1_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2
++#define mmDCP1_REGAMMA_CNTLB_REGION_12_13 0x07fa
++#define mmDCP1_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2
++#define mmDCP1_REGAMMA_CNTLB_REGION_14_15 0x07fb
++#define mmDCP1_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2
++#define mmDCP1_ALPHA_CONTROL 0x07fc
++#define mmDCP1_ALPHA_CONTROL_BASE_IDX 2
++#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x07fd
++#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2
++#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x07fe
++#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
++#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x07ff
++#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2
++#define mmDCP1_GRPH_XDMA_FLIP_TIMEOUT 0x0800
++#define mmDCP1_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2
++#define mmDCP1_GRPH_XDMA_FLIP_AVG_DELAY 0x0801
++#define mmDCP1_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2
++#define mmDCP1_GRPH_SURFACE_COUNTER_CONTROL 0x0802
++#define mmDCP1_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2
++#define mmDCP1_GRPH_SURFACE_COUNTER_OUTPUT 0x0803
++#define mmDCP1_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2
++
++
++// addressBlock: dce_dc_lb1_dispdec
++// base address: 0x800
++#define mmLB1_LB_DATA_FORMAT 0x081a
++#define mmLB1_LB_DATA_FORMAT_BASE_IDX 2
++#define mmLB1_LB_MEMORY_CTRL 0x081b
++#define mmLB1_LB_MEMORY_CTRL_BASE_IDX 2
++#define mmLB1_LB_MEMORY_SIZE_STATUS 0x081c
++#define mmLB1_LB_MEMORY_SIZE_STATUS_BASE_IDX 2
++#define mmLB1_LB_DESKTOP_HEIGHT 0x081d
++#define mmLB1_LB_DESKTOP_HEIGHT_BASE_IDX 2
++#define mmLB1_LB_VLINE_START_END 0x081e
++#define mmLB1_LB_VLINE_START_END_BASE_IDX 2
++#define mmLB1_LB_VLINE2_START_END 0x081f
++#define mmLB1_LB_VLINE2_START_END_BASE_IDX 2
++#define mmLB1_LB_V_COUNTER 0x0820
++#define mmLB1_LB_V_COUNTER_BASE_IDX 2
++#define mmLB1_LB_SNAPSHOT_V_COUNTER 0x0821
++#define mmLB1_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2
++#define mmLB1_LB_INTERRUPT_MASK 0x0822
++#define mmLB1_LB_INTERRUPT_MASK_BASE_IDX 2
++#define mmLB1_LB_VLINE_STATUS 0x0823
++#define mmLB1_LB_VLINE_STATUS_BASE_IDX 2
++#define mmLB1_LB_VLINE2_STATUS 0x0824
++#define mmLB1_LB_VLINE2_STATUS_BASE_IDX 2
++#define mmLB1_LB_VBLANK_STATUS 0x0825
++#define mmLB1_LB_VBLANK_STATUS_BASE_IDX 2
++#define mmLB1_LB_SYNC_RESET_SEL 0x0826
++#define mmLB1_LB_SYNC_RESET_SEL_BASE_IDX 2
++#define mmLB1_LB_BLACK_KEYER_R_CR 0x0827
++#define mmLB1_LB_BLACK_KEYER_R_CR_BASE_IDX 2
++#define mmLB1_LB_BLACK_KEYER_G_Y 0x0828
++#define mmLB1_LB_BLACK_KEYER_G_Y_BASE_IDX 2
++#define mmLB1_LB_BLACK_KEYER_B_CB 0x0829
++#define mmLB1_LB_BLACK_KEYER_B_CB_BASE_IDX 2
++#define mmLB1_LB_KEYER_COLOR_CTRL 0x082a
++#define mmLB1_LB_KEYER_COLOR_CTRL_BASE_IDX 2
++#define mmLB1_LB_KEYER_COLOR_R_CR 0x082b
++#define mmLB1_LB_KEYER_COLOR_R_CR_BASE_IDX 2
++#define mmLB1_LB_KEYER_COLOR_G_Y 0x082c
++#define mmLB1_LB_KEYER_COLOR_G_Y_BASE_IDX 2
++#define mmLB1_LB_KEYER_COLOR_B_CB 0x082d
++#define mmLB1_LB_KEYER_COLOR_B_CB_BASE_IDX 2
++#define mmLB1_LB_KEYER_COLOR_REP_R_CR 0x082e
++#define mmLB1_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2
++#define mmLB1_LB_KEYER_COLOR_REP_G_Y 0x082f
++#define mmLB1_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2
++#define mmLB1_LB_KEYER_COLOR_REP_B_CB 0x0830
++#define mmLB1_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2
++#define mmLB1_LB_BUFFER_LEVEL_STATUS 0x0831
++#define mmLB1_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2
++#define mmLB1_LB_BUFFER_URGENCY_CTRL 0x0832
++#define mmLB1_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2
++#define mmLB1_LB_BUFFER_URGENCY_STATUS 0x0833
++#define mmLB1_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2
++#define mmLB1_LB_BUFFER_STATUS 0x0834
++#define mmLB1_LB_BUFFER_STATUS_BASE_IDX 2
++#define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0x0835
++#define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2
++#define mmLB1_MVP_AFR_FLIP_MODE 0x0836
++#define mmLB1_MVP_AFR_FLIP_MODE_BASE_IDX 2
++#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0x0837
++#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2
++#define mmLB1_MVP_FLIP_LINE_NUM_INSERT 0x0838
++#define mmLB1_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2
++#define mmLB1_DC_MVP_LB_CONTROL 0x0839
++#define mmLB1_DC_MVP_LB_CONTROL_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dcfe1_dispdec
++// base address: 0x800
++#define mmDCFE1_DCFE_CLOCK_CONTROL 0x085a
++#define mmDCFE1_DCFE_CLOCK_CONTROL_BASE_IDX 2
++#define mmDCFE1_DCFE_SOFT_RESET 0x085b
++#define mmDCFE1_DCFE_SOFT_RESET_BASE_IDX 2
++#define mmDCFE1_DCFE_MEM_PWR_CTRL 0x085d
++#define mmDCFE1_DCFE_MEM_PWR_CTRL_BASE_IDX 2
++#define mmDCFE1_DCFE_MEM_PWR_CTRL2 0x085e
++#define mmDCFE1_DCFE_MEM_PWR_CTRL2_BASE_IDX 2
++#define mmDCFE1_DCFE_MEM_PWR_STATUS 0x085f
++#define mmDCFE1_DCFE_MEM_PWR_STATUS_BASE_IDX 2
++#define mmDCFE1_DCFE_MISC 0x0860
++#define mmDCFE1_DCFE_MISC_BASE_IDX 2
++#define mmDCFE1_DCFE_FLUSH 0x0861
++#define mmDCFE1_DCFE_FLUSH_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dc_perfmon4_dispdec
++// base address: 0x2138
++#define mmDC_PERFMON4_PERFCOUNTER_CNTL 0x086e
++#define mmDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX 2
++#define mmDC_PERFMON4_PERFCOUNTER_CNTL2 0x086f
++#define mmDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX 2
++#define mmDC_PERFMON4_PERFCOUNTER_STATE 0x0870
++#define mmDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX 2
++#define mmDC_PERFMON4_PERFMON_CNTL 0x0871
++#define mmDC_PERFMON4_PERFMON_CNTL_BASE_IDX 2
++#define mmDC_PERFMON4_PERFMON_CNTL2 0x0872
++#define mmDC_PERFMON4_PERFMON_CNTL2_BASE_IDX 2
++#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x0873
++#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
++#define mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x0874
++#define mmDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX 2
++#define mmDC_PERFMON4_PERFMON_HI 0x0875
++#define mmDC_PERFMON4_PERFMON_HI_BASE_IDX 2
++#define mmDC_PERFMON4_PERFMON_LOW 0x0876
++#define mmDC_PERFMON4_PERFMON_LOW_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dmif_pg1_dispdec
++// base address: 0x800
++#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 0x087a
++#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
++#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 0x087b
++#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
++#define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 0x087c
++#define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2
++#define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL 0x087d
++#define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2
++#define mmDMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL 0x087e
++#define mmDMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2
++#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL 0x087f
++#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2
++#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL2 0x0880
++#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2
++#define mmDMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL 0x0881
++#define mmDMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2
++#define mmDMIF_PG1_DPG_REPEATER_PROGRAM 0x0882
++#define mmDMIF_PG1_DPG_REPEATER_PROGRAM_BASE_IDX 2
++#define mmDMIF_PG1_DPG_CHK_PRE_PROC_CNTL 0x0886
++#define mmDMIF_PG1_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2
++#define mmDMIF_PG1_DPG_DVMM_STATUS 0x0887
++#define mmDMIF_PG1_DPG_DVMM_STATUS_BASE_IDX 2
++
++
++// addressBlock: dce_dc_scl1_dispdec
++// base address: 0x800
++#define mmSCL1_SCL_COEF_RAM_SELECT 0x089a
++#define mmSCL1_SCL_COEF_RAM_SELECT_BASE_IDX 2
++#define mmSCL1_SCL_COEF_RAM_TAP_DATA 0x089b
++#define mmSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
++#define mmSCL1_SCL_MODE 0x089c
++#define mmSCL1_SCL_MODE_BASE_IDX 2
++#define mmSCL1_SCL_TAP_CONTROL 0x089d
++#define mmSCL1_SCL_TAP_CONTROL_BASE_IDX 2
++#define mmSCL1_SCL_CONTROL 0x089e
++#define mmSCL1_SCL_CONTROL_BASE_IDX 2
++#define mmSCL1_SCL_BYPASS_CONTROL 0x089f
++#define mmSCL1_SCL_BYPASS_CONTROL_BASE_IDX 2
++#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x08a0
++#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
++#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL 0x08a1
++#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2
++#define mmSCL1_SCL_HORZ_FILTER_CONTROL 0x08a2
++#define mmSCL1_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2
++#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x08a3
++#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
++#define mmSCL1_SCL_HORZ_FILTER_INIT 0x08a4
++#define mmSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2
++#define mmSCL1_SCL_VERT_FILTER_CONTROL 0x08a5
++#define mmSCL1_SCL_VERT_FILTER_CONTROL_BASE_IDX 2
++#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x08a6
++#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
++#define mmSCL1_SCL_VERT_FILTER_INIT 0x08a7
++#define mmSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2
++#define mmSCL1_SCL_VERT_FILTER_INIT_BOT 0x08a8
++#define mmSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
++#define mmSCL1_SCL_ROUND_OFFSET 0x08a9
++#define mmSCL1_SCL_ROUND_OFFSET_BASE_IDX 2
++#define mmSCL1_SCL_UPDATE 0x08aa
++#define mmSCL1_SCL_UPDATE_BASE_IDX 2
++#define mmSCL1_SCL_F_SHARP_CONTROL 0x08ab
++#define mmSCL1_SCL_F_SHARP_CONTROL_BASE_IDX 2
++#define mmSCL1_SCL_ALU_CONTROL 0x08ac
++#define mmSCL1_SCL_ALU_CONTROL_BASE_IDX 2
++#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0x08ad
++#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
++#define mmSCL1_VIEWPORT_START_SECONDARY 0x08ae
++#define mmSCL1_VIEWPORT_START_SECONDARY_BASE_IDX 2
++#define mmSCL1_VIEWPORT_START 0x08af
++#define mmSCL1_VIEWPORT_START_BASE_IDX 2
++#define mmSCL1_VIEWPORT_SIZE 0x08b0
++#define mmSCL1_VIEWPORT_SIZE_BASE_IDX 2
++#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT 0x08b1
++#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
++#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM 0x08b2
++#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
++#define mmSCL1_SCL_MODE_CHANGE_DET1 0x08b3
++#define mmSCL1_SCL_MODE_CHANGE_DET1_BASE_IDX 2
++#define mmSCL1_SCL_MODE_CHANGE_DET2 0x08b4
++#define mmSCL1_SCL_MODE_CHANGE_DET2_BASE_IDX 2
++#define mmSCL1_SCL_MODE_CHANGE_DET3 0x08b5
++#define mmSCL1_SCL_MODE_CHANGE_DET3_BASE_IDX 2
++#define mmSCL1_SCL_MODE_CHANGE_MASK 0x08b6
++#define mmSCL1_SCL_MODE_CHANGE_MASK_BASE_IDX 2
++
++
++// addressBlock: dce_dc_blnd1_dispdec
++// base address: 0x800
++#define mmBLND1_BLND_CONTROL 0x08c7
++#define mmBLND1_BLND_CONTROL_BASE_IDX 2
++#define mmBLND1_BLND_SM_CONTROL2 0x08c8
++#define mmBLND1_BLND_SM_CONTROL2_BASE_IDX 2
++#define mmBLND1_BLND_CONTROL2 0x08c9
++#define mmBLND1_BLND_CONTROL2_BASE_IDX 2
++#define mmBLND1_BLND_UPDATE 0x08ca
++#define mmBLND1_BLND_UPDATE_BASE_IDX 2
++#define mmBLND1_BLND_UNDERFLOW_INTERRUPT 0x08cb
++#define mmBLND1_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2
++#define mmBLND1_BLND_V_UPDATE_LOCK 0x08cc
++#define mmBLND1_BLND_V_UPDATE_LOCK_BASE_IDX 2
++#define mmBLND1_BLND_REG_UPDATE_STATUS 0x08cd
++#define mmBLND1_BLND_REG_UPDATE_STATUS_BASE_IDX 2
++
++
++// addressBlock: dce_dc_crtc1_dispdec
++// base address: 0x800
++#define mmCRTC1_CRTC_H_BLANK_EARLY_NUM 0x08d2
++#define mmCRTC1_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2
++#define mmCRTC1_CRTC_H_TOTAL 0x08d3
++#define mmCRTC1_CRTC_H_TOTAL_BASE_IDX 2
++#define mmCRTC1_CRTC_H_BLANK_START_END 0x08d4
++#define mmCRTC1_CRTC_H_BLANK_START_END_BASE_IDX 2
++#define mmCRTC1_CRTC_H_SYNC_A 0x08d5
++#define mmCRTC1_CRTC_H_SYNC_A_BASE_IDX 2
++#define mmCRTC1_CRTC_H_SYNC_A_CNTL 0x08d6
++#define mmCRTC1_CRTC_H_SYNC_A_CNTL_BASE_IDX 2
++#define mmCRTC1_CRTC_H_SYNC_B 0x08d7
++#define mmCRTC1_CRTC_H_SYNC_B_BASE_IDX 2
++#define mmCRTC1_CRTC_H_SYNC_B_CNTL 0x08d8
++#define mmCRTC1_CRTC_H_SYNC_B_CNTL_BASE_IDX 2
++#define mmCRTC1_CRTC_VBI_END 0x08d9
++#define mmCRTC1_CRTC_VBI_END_BASE_IDX 2
++#define mmCRTC1_CRTC_V_TOTAL 0x08da
++#define mmCRTC1_CRTC_V_TOTAL_BASE_IDX 2
++#define mmCRTC1_CRTC_V_TOTAL_MIN 0x08db
++#define mmCRTC1_CRTC_V_TOTAL_MIN_BASE_IDX 2
++#define mmCRTC1_CRTC_V_TOTAL_MAX 0x08dc
++#define mmCRTC1_CRTC_V_TOTAL_MAX_BASE_IDX 2
++#define mmCRTC1_CRTC_V_TOTAL_CONTROL 0x08dd
++#define mmCRTC1_CRTC_V_TOTAL_CONTROL_BASE_IDX 2
++#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS 0x08de
++#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2
++#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS 0x08df
++#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2
++#define mmCRTC1_CRTC_V_BLANK_START_END 0x08e0
++#define mmCRTC1_CRTC_V_BLANK_START_END_BASE_IDX 2
++#define mmCRTC1_CRTC_V_SYNC_A 0x08e1
++#define mmCRTC1_CRTC_V_SYNC_A_BASE_IDX 2
++#define mmCRTC1_CRTC_V_SYNC_A_CNTL 0x08e2
++#define mmCRTC1_CRTC_V_SYNC_A_CNTL_BASE_IDX 2
++#define mmCRTC1_CRTC_V_SYNC_B 0x08e3
++#define mmCRTC1_CRTC_V_SYNC_B_BASE_IDX 2
++#define mmCRTC1_CRTC_V_SYNC_B_CNTL 0x08e4
++#define mmCRTC1_CRTC_V_SYNC_B_CNTL_BASE_IDX 2
++#define mmCRTC1_CRTC_DTMTEST_CNTL 0x08e5
++#define mmCRTC1_CRTC_DTMTEST_CNTL_BASE_IDX 2
++#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION 0x08e6
++#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2
++#define mmCRTC1_CRTC_TRIGA_CNTL 0x08e7
++#define mmCRTC1_CRTC_TRIGA_CNTL_BASE_IDX 2
++#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG 0x08e8
++#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2
++#define mmCRTC1_CRTC_TRIGB_CNTL 0x08e9
++#define mmCRTC1_CRTC_TRIGB_CNTL_BASE_IDX 2
++#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG 0x08ea
++#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2
++#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL 0x08eb
++#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
++#define mmCRTC1_CRTC_FLOW_CONTROL 0x08ec
++#define mmCRTC1_CRTC_FLOW_CONTROL_BASE_IDX 2
++#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE 0x08ed
++#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
++#define mmCRTC1_CRTC_AVSYNC_COUNTER 0x08ee
++#define mmCRTC1_CRTC_AVSYNC_COUNTER_BASE_IDX 2
++#define mmCRTC1_CRTC_CONTROL 0x08ef
++#define mmCRTC1_CRTC_CONTROL_BASE_IDX 2
++#define mmCRTC1_CRTC_BLANK_CONTROL 0x08f0
++#define mmCRTC1_CRTC_BLANK_CONTROL_BASE_IDX 2
++#define mmCRTC1_CRTC_INTERLACE_CONTROL 0x08f1
++#define mmCRTC1_CRTC_INTERLACE_CONTROL_BASE_IDX 2
++#define mmCRTC1_CRTC_INTERLACE_STATUS 0x08f2
++#define mmCRTC1_CRTC_INTERLACE_STATUS_BASE_IDX 2
++#define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL 0x08f3
++#define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2
++#define mmCRTC1_CRTC_PIXEL_DATA_READBACK0 0x08f4
++#define mmCRTC1_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2
++#define mmCRTC1_CRTC_PIXEL_DATA_READBACK1 0x08f5
++#define mmCRTC1_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2
++#define mmCRTC1_CRTC_STATUS 0x08f6
++#define mmCRTC1_CRTC_STATUS_BASE_IDX 2
++#define mmCRTC1_CRTC_STATUS_POSITION 0x08f7
++#define mmCRTC1_CRTC_STATUS_POSITION_BASE_IDX 2
++#define mmCRTC1_CRTC_NOM_VERT_POSITION 0x08f8
++#define mmCRTC1_CRTC_NOM_VERT_POSITION_BASE_IDX 2
++#define mmCRTC1_CRTC_STATUS_FRAME_COUNT 0x08f9
++#define mmCRTC1_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2
++#define mmCRTC1_CRTC_STATUS_VF_COUNT 0x08fa
++#define mmCRTC1_CRTC_STATUS_VF_COUNT_BASE_IDX 2
++#define mmCRTC1_CRTC_STATUS_HV_COUNT 0x08fb
++#define mmCRTC1_CRTC_STATUS_HV_COUNT_BASE_IDX 2
++#define mmCRTC1_CRTC_COUNT_CONTROL 0x08fc
++#define mmCRTC1_CRTC_COUNT_CONTROL_BASE_IDX 2
++#define mmCRTC1_CRTC_COUNT_RESET 0x08fd
++#define mmCRTC1_CRTC_COUNT_RESET_BASE_IDX 2
++#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x08fe
++#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
++#define mmCRTC1_CRTC_VERT_SYNC_CONTROL 0x08ff
++#define mmCRTC1_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2
++#define mmCRTC1_CRTC_STEREO_STATUS 0x0900
++#define mmCRTC1_CRTC_STEREO_STATUS_BASE_IDX 2
++#define mmCRTC1_CRTC_STEREO_CONTROL 0x0901
++#define mmCRTC1_CRTC_STEREO_CONTROL_BASE_IDX 2
++#define mmCRTC1_CRTC_SNAPSHOT_STATUS 0x0902
++#define mmCRTC1_CRTC_SNAPSHOT_STATUS_BASE_IDX 2
++#define mmCRTC1_CRTC_SNAPSHOT_CONTROL 0x0903
++#define mmCRTC1_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2
++#define mmCRTC1_CRTC_SNAPSHOT_POSITION 0x0904
++#define mmCRTC1_CRTC_SNAPSHOT_POSITION_BASE_IDX 2
++#define mmCRTC1_CRTC_SNAPSHOT_FRAME 0x0905
++#define mmCRTC1_CRTC_SNAPSHOT_FRAME_BASE_IDX 2
++#define mmCRTC1_CRTC_START_LINE_CONTROL 0x0906
++#define mmCRTC1_CRTC_START_LINE_CONTROL_BASE_IDX 2
++#define mmCRTC1_CRTC_INTERRUPT_CONTROL 0x0907
++#define mmCRTC1_CRTC_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmCRTC1_CRTC_UPDATE_LOCK 0x0908
++#define mmCRTC1_CRTC_UPDATE_LOCK_BASE_IDX 2
++#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL 0x0909
++#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
++#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x090a
++#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2
++#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL 0x090b
++#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2
++#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS 0x090c
++#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2
++#define mmCRTC1_CRTC_TEST_PATTERN_COLOR 0x090d
++#define mmCRTC1_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2
++#define mmCRTC1_CRTC_MASTER_UPDATE_LOCK 0x090e
++#define mmCRTC1_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2
++#define mmCRTC1_CRTC_MASTER_UPDATE_MODE 0x090f
++#define mmCRTC1_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2
++#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT 0x0910
++#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2
++#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x0911
++#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2
++#define mmCRTC1_CRTC_MVP_STATUS 0x0912
++#define mmCRTC1_CRTC_MVP_STATUS_BASE_IDX 2
++#define mmCRTC1_CRTC_MASTER_EN 0x0913
++#define mmCRTC1_CRTC_MASTER_EN_BASE_IDX 2
++#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT 0x0914
++#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2
++#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS 0x0915
++#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2
++#define mmCRTC1_CRTC_OVERSCAN_COLOR 0x0917
++#define mmCRTC1_CRTC_OVERSCAN_COLOR_BASE_IDX 2
++#define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT 0x0918
++#define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2
++#define mmCRTC1_CRTC_BLANK_DATA_COLOR 0x0919
++#define mmCRTC1_CRTC_BLANK_DATA_COLOR_BASE_IDX 2
++#define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT 0x091a
++#define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2
++#define mmCRTC1_CRTC_BLACK_COLOR 0x091b
++#define mmCRTC1_CRTC_BLACK_COLOR_BASE_IDX 2
++#define mmCRTC1_CRTC_BLACK_COLOR_EXT 0x091c
++#define mmCRTC1_CRTC_BLACK_COLOR_EXT_BASE_IDX 2
++#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION 0x091d
++#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
++#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x091e
++#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
++#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION 0x091f
++#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
++#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x0920
++#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
++#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION 0x0921
++#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
++#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x0922
++#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
++#define mmCRTC1_CRTC_CRC_CNTL 0x0923
++#define mmCRTC1_CRTC_CRC_CNTL_BASE_IDX 2
++#define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL 0x0924
++#define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
++#define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL 0x0925
++#define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
++#define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL 0x0926
++#define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
++#define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL 0x0927
++#define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
++#define mmCRTC1_CRTC_CRC0_DATA_RG 0x0928
++#define mmCRTC1_CRTC_CRC0_DATA_RG_BASE_IDX 2
++#define mmCRTC1_CRTC_CRC0_DATA_B 0x0929
++#define mmCRTC1_CRTC_CRC0_DATA_B_BASE_IDX 2
++#define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL 0x092a
++#define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
++#define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL 0x092b
++#define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
++#define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL 0x092c
++#define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
++#define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL 0x092d
++#define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
++#define mmCRTC1_CRTC_CRC1_DATA_RG 0x092e
++#define mmCRTC1_CRTC_CRC1_DATA_RG_BASE_IDX 2
++#define mmCRTC1_CRTC_CRC1_DATA_B 0x092f
++#define mmCRTC1_CRTC_CRC1_DATA_B_BASE_IDX 2
++#define mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL 0x0930
++#define mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2
++#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x0931
++#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2
++#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x0932
++#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2
++#define mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x0933
++#define mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x0934
++#define mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x0935
++#define mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL 0x0936
++#define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2
++#define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL 0x0937
++#define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2
++#define mmCRTC1_CRTC_GSL_VSYNC_GAP 0x0938
++#define mmCRTC1_CRTC_GSL_VSYNC_GAP_BASE_IDX 2
++#define mmCRTC1_CRTC_GSL_WINDOW 0x0939
++#define mmCRTC1_CRTC_GSL_WINDOW_BASE_IDX 2
++#define mmCRTC1_CRTC_GSL_CONTROL 0x093a
++#define mmCRTC1_CRTC_GSL_CONTROL_BASE_IDX 2
++#define mmCRTC1_CRTC_RANGE_TIMING_INT_STATUS 0x093d
++#define mmCRTC1_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2
++#define mmCRTC1_CRTC_DRR_CONTROL 0x093e
++#define mmCRTC1_CRTC_DRR_CONTROL_BASE_IDX 2
++
++
++// addressBlock: dce_dc_fmt1_dispdec
++// base address: 0x800
++#define mmFMT1_FMT_CLAMP_COMPONENT_R 0x0942
++#define mmFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
++#define mmFMT1_FMT_CLAMP_COMPONENT_G 0x0943
++#define mmFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
++#define mmFMT1_FMT_CLAMP_COMPONENT_B 0x0944
++#define mmFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
++#define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x0945
++#define mmFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
++#define mmFMT1_FMT_CONTROL 0x0946
++#define mmFMT1_FMT_CONTROL_BASE_IDX 2
++#define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x0947
++#define mmFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
++#define mmFMT1_FMT_DITHER_RAND_R_SEED 0x0948
++#define mmFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
++#define mmFMT1_FMT_DITHER_RAND_G_SEED 0x0949
++#define mmFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
++#define mmFMT1_FMT_DITHER_RAND_B_SEED 0x094a
++#define mmFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
++#define mmFMT1_FMT_CLAMP_CNTL 0x094e
++#define mmFMT1_FMT_CLAMP_CNTL_BASE_IDX 2
++#define mmFMT1_FMT_CRC_CNTL 0x094f
++#define mmFMT1_FMT_CRC_CNTL_BASE_IDX 2
++#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK 0x0950
++#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
++#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x0951
++#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
++#define mmFMT1_FMT_CRC_SIG_RED_GREEN 0x0952
++#define mmFMT1_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2
++#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL 0x0953
++#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2
++#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x0954
++#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
++#define mmFMT1_FMT_420_HBLANK_EARLY_START 0x0955
++#define mmFMT1_FMT_420_HBLANK_EARLY_START_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dcp2_dispdec
++// base address: 0x1000
++#define mmDCP2_GRPH_ENABLE 0x095a
++#define mmDCP2_GRPH_ENABLE_BASE_IDX 2
++#define mmDCP2_GRPH_CONTROL 0x095b
++#define mmDCP2_GRPH_CONTROL_BASE_IDX 2
++#define mmDCP2_GRPH_LUT_10BIT_BYPASS 0x095c
++#define mmDCP2_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2
++#define mmDCP2_GRPH_SWAP_CNTL 0x095d
++#define mmDCP2_GRPH_SWAP_CNTL_BASE_IDX 2
++#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS 0x095e
++#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
++#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS 0x095f
++#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
++#define mmDCP2_GRPH_PITCH 0x0960
++#define mmDCP2_GRPH_PITCH_BASE_IDX 2
++#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0961
++#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
++#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0962
++#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
++#define mmDCP2_GRPH_SURFACE_OFFSET_X 0x0963
++#define mmDCP2_GRPH_SURFACE_OFFSET_X_BASE_IDX 2
++#define mmDCP2_GRPH_SURFACE_OFFSET_Y 0x0964
++#define mmDCP2_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2
++#define mmDCP2_GRPH_X_START 0x0965
++#define mmDCP2_GRPH_X_START_BASE_IDX 2
++#define mmDCP2_GRPH_Y_START 0x0966
++#define mmDCP2_GRPH_Y_START_BASE_IDX 2
++#define mmDCP2_GRPH_X_END 0x0967
++#define mmDCP2_GRPH_X_END_BASE_IDX 2
++#define mmDCP2_GRPH_Y_END 0x0968
++#define mmDCP2_GRPH_Y_END_BASE_IDX 2
++#define mmDCP2_INPUT_GAMMA_CONTROL 0x0969
++#define mmDCP2_INPUT_GAMMA_CONTROL_BASE_IDX 2
++#define mmDCP2_GRPH_UPDATE 0x096a
++#define mmDCP2_GRPH_UPDATE_BASE_IDX 2
++#define mmDCP2_GRPH_FLIP_CONTROL 0x096b
++#define mmDCP2_GRPH_FLIP_CONTROL_BASE_IDX 2
++#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE 0x096c
++#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2
++#define mmDCP2_GRPH_DFQ_CONTROL 0x096d
++#define mmDCP2_GRPH_DFQ_CONTROL_BASE_IDX 2
++#define mmDCP2_GRPH_DFQ_STATUS 0x096e
++#define mmDCP2_GRPH_DFQ_STATUS_BASE_IDX 2
++#define mmDCP2_GRPH_INTERRUPT_STATUS 0x096f
++#define mmDCP2_GRPH_INTERRUPT_STATUS_BASE_IDX 2
++#define mmDCP2_GRPH_INTERRUPT_CONTROL 0x0970
++#define mmDCP2_GRPH_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0971
++#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2
++#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS 0x0972
++#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2
++#define mmDCP2_GRPH_COMPRESS_PITCH 0x0973
++#define mmDCP2_GRPH_COMPRESS_PITCH_BASE_IDX 2
++#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0974
++#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2
++#define mmDCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0975
++#define mmDCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2
++#define mmDCP2_PRESCALE_GRPH_CONTROL 0x0976
++#define mmDCP2_PRESCALE_GRPH_CONTROL_BASE_IDX 2
++#define mmDCP2_PRESCALE_VALUES_GRPH_R 0x0977
++#define mmDCP2_PRESCALE_VALUES_GRPH_R_BASE_IDX 2
++#define mmDCP2_PRESCALE_VALUES_GRPH_G 0x0978
++#define mmDCP2_PRESCALE_VALUES_GRPH_G_BASE_IDX 2
++#define mmDCP2_PRESCALE_VALUES_GRPH_B 0x0979
++#define mmDCP2_PRESCALE_VALUES_GRPH_B_BASE_IDX 2
++#define mmDCP2_INPUT_CSC_CONTROL 0x097a
++#define mmDCP2_INPUT_CSC_CONTROL_BASE_IDX 2
++#define mmDCP2_INPUT_CSC_C11_C12 0x097b
++#define mmDCP2_INPUT_CSC_C11_C12_BASE_IDX 2
++#define mmDCP2_INPUT_CSC_C13_C14 0x097c
++#define mmDCP2_INPUT_CSC_C13_C14_BASE_IDX 2
++#define mmDCP2_INPUT_CSC_C21_C22 0x097d
++#define mmDCP2_INPUT_CSC_C21_C22_BASE_IDX 2
++#define mmDCP2_INPUT_CSC_C23_C24 0x097e
++#define mmDCP2_INPUT_CSC_C23_C24_BASE_IDX 2
++#define mmDCP2_INPUT_CSC_C31_C32 0x097f
++#define mmDCP2_INPUT_CSC_C31_C32_BASE_IDX 2
++#define mmDCP2_INPUT_CSC_C33_C34 0x0980
++#define mmDCP2_INPUT_CSC_C33_C34_BASE_IDX 2
++#define mmDCP2_OUTPUT_CSC_CONTROL 0x0981
++#define mmDCP2_OUTPUT_CSC_CONTROL_BASE_IDX 2
++#define mmDCP2_OUTPUT_CSC_C11_C12 0x0982
++#define mmDCP2_OUTPUT_CSC_C11_C12_BASE_IDX 2
++#define mmDCP2_OUTPUT_CSC_C13_C14 0x0983
++#define mmDCP2_OUTPUT_CSC_C13_C14_BASE_IDX 2
++#define mmDCP2_OUTPUT_CSC_C21_C22 0x0984
++#define mmDCP2_OUTPUT_CSC_C21_C22_BASE_IDX 2
++#define mmDCP2_OUTPUT_CSC_C23_C24 0x0985
++#define mmDCP2_OUTPUT_CSC_C23_C24_BASE_IDX 2
++#define mmDCP2_OUTPUT_CSC_C31_C32 0x0986
++#define mmDCP2_OUTPUT_CSC_C31_C32_BASE_IDX 2
++#define mmDCP2_OUTPUT_CSC_C33_C34 0x0987
++#define mmDCP2_OUTPUT_CSC_C33_C34_BASE_IDX 2
++#define mmDCP2_COMM_MATRIXA_TRANS_C11_C12 0x0988
++#define mmDCP2_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2
++#define mmDCP2_COMM_MATRIXA_TRANS_C13_C14 0x0989
++#define mmDCP2_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2
++#define mmDCP2_COMM_MATRIXA_TRANS_C21_C22 0x098a
++#define mmDCP2_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2
++#define mmDCP2_COMM_MATRIXA_TRANS_C23_C24 0x098b
++#define mmDCP2_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2
++#define mmDCP2_COMM_MATRIXA_TRANS_C31_C32 0x098c
++#define mmDCP2_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2
++#define mmDCP2_COMM_MATRIXA_TRANS_C33_C34 0x098d
++#define mmDCP2_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2
++#define mmDCP2_COMM_MATRIXB_TRANS_C11_C12 0x098e
++#define mmDCP2_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2
++#define mmDCP2_COMM_MATRIXB_TRANS_C13_C14 0x098f
++#define mmDCP2_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2
++#define mmDCP2_COMM_MATRIXB_TRANS_C21_C22 0x0990
++#define mmDCP2_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2
++#define mmDCP2_COMM_MATRIXB_TRANS_C23_C24 0x0991
++#define mmDCP2_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2
++#define mmDCP2_COMM_MATRIXB_TRANS_C31_C32 0x0992
++#define mmDCP2_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2
++#define mmDCP2_COMM_MATRIXB_TRANS_C33_C34 0x0993
++#define mmDCP2_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2
++#define mmDCP2_DENORM_CONTROL 0x0994
++#define mmDCP2_DENORM_CONTROL_BASE_IDX 2
++#define mmDCP2_OUT_ROUND_CONTROL 0x0995
++#define mmDCP2_OUT_ROUND_CONTROL_BASE_IDX 2
++#define mmDCP2_OUT_CLAMP_CONTROL_R_CR 0x0996
++#define mmDCP2_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2
++#define mmDCP2_OUT_CLAMP_CONTROL_G_Y 0x0997
++#define mmDCP2_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2
++#define mmDCP2_OUT_CLAMP_CONTROL_B_CB 0x0998
++#define mmDCP2_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2
++#define mmDCP2_KEY_CONTROL 0x0999
++#define mmDCP2_KEY_CONTROL_BASE_IDX 2
++#define mmDCP2_KEY_RANGE_ALPHA 0x099a
++#define mmDCP2_KEY_RANGE_ALPHA_BASE_IDX 2
++#define mmDCP2_KEY_RANGE_RED 0x099b
++#define mmDCP2_KEY_RANGE_RED_BASE_IDX 2
++#define mmDCP2_KEY_RANGE_GREEN 0x099c
++#define mmDCP2_KEY_RANGE_GREEN_BASE_IDX 2
++#define mmDCP2_KEY_RANGE_BLUE 0x099d
++#define mmDCP2_KEY_RANGE_BLUE_BASE_IDX 2
++#define mmDCP2_DEGAMMA_CONTROL 0x099e
++#define mmDCP2_DEGAMMA_CONTROL_BASE_IDX 2
++#define mmDCP2_GAMUT_REMAP_CONTROL 0x099f
++#define mmDCP2_GAMUT_REMAP_CONTROL_BASE_IDX 2
++#define mmDCP2_GAMUT_REMAP_C11_C12 0x09a0
++#define mmDCP2_GAMUT_REMAP_C11_C12_BASE_IDX 2
++#define mmDCP2_GAMUT_REMAP_C13_C14 0x09a1
++#define mmDCP2_GAMUT_REMAP_C13_C14_BASE_IDX 2
++#define mmDCP2_GAMUT_REMAP_C21_C22 0x09a2
++#define mmDCP2_GAMUT_REMAP_C21_C22_BASE_IDX 2
++#define mmDCP2_GAMUT_REMAP_C23_C24 0x09a3
++#define mmDCP2_GAMUT_REMAP_C23_C24_BASE_IDX 2
++#define mmDCP2_GAMUT_REMAP_C31_C32 0x09a4
++#define mmDCP2_GAMUT_REMAP_C31_C32_BASE_IDX 2
++#define mmDCP2_GAMUT_REMAP_C33_C34 0x09a5
++#define mmDCP2_GAMUT_REMAP_C33_C34_BASE_IDX 2
++#define mmDCP2_DCP_SPATIAL_DITHER_CNTL 0x09a6
++#define mmDCP2_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2
++#define mmDCP2_DCP_RANDOM_SEEDS 0x09a7
++#define mmDCP2_DCP_RANDOM_SEEDS_BASE_IDX 2
++#define mmDCP2_DCP_FP_CONVERTED_FIELD 0x09a8
++#define mmDCP2_DCP_FP_CONVERTED_FIELD_BASE_IDX 2
++#define mmDCP2_CUR_CONTROL 0x09a9
++#define mmDCP2_CUR_CONTROL_BASE_IDX 2
++#define mmDCP2_CUR_SURFACE_ADDRESS 0x09aa
++#define mmDCP2_CUR_SURFACE_ADDRESS_BASE_IDX 2
++#define mmDCP2_CUR_SIZE 0x09ab
++#define mmDCP2_CUR_SIZE_BASE_IDX 2
++#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH 0x09ac
++#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
++#define mmDCP2_CUR_POSITION 0x09ad
++#define mmDCP2_CUR_POSITION_BASE_IDX 2
++#define mmDCP2_CUR_HOT_SPOT 0x09ae
++#define mmDCP2_CUR_HOT_SPOT_BASE_IDX 2
++#define mmDCP2_CUR_COLOR1 0x09af
++#define mmDCP2_CUR_COLOR1_BASE_IDX 2
++#define mmDCP2_CUR_COLOR2 0x09b0
++#define mmDCP2_CUR_COLOR2_BASE_IDX 2
++#define mmDCP2_CUR_UPDATE 0x09b1
++#define mmDCP2_CUR_UPDATE_BASE_IDX 2
++#define mmDCP2_CUR_REQUEST_FILTER_CNTL 0x09bb
++#define mmDCP2_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2
++#define mmDCP2_CUR_STEREO_CONTROL 0x09bc
++#define mmDCP2_CUR_STEREO_CONTROL_BASE_IDX 2
++#define mmDCP2_DC_LUT_RW_MODE 0x09be
++#define mmDCP2_DC_LUT_RW_MODE_BASE_IDX 2
++#define mmDCP2_DC_LUT_RW_INDEX 0x09bf
++#define mmDCP2_DC_LUT_RW_INDEX_BASE_IDX 2
++#define mmDCP2_DC_LUT_SEQ_COLOR 0x09c0
++#define mmDCP2_DC_LUT_SEQ_COLOR_BASE_IDX 2
++#define mmDCP2_DC_LUT_PWL_DATA 0x09c1
++#define mmDCP2_DC_LUT_PWL_DATA_BASE_IDX 2
++#define mmDCP2_DC_LUT_30_COLOR 0x09c2
++#define mmDCP2_DC_LUT_30_COLOR_BASE_IDX 2
++#define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE 0x09c3
++#define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2
++#define mmDCP2_DC_LUT_WRITE_EN_MASK 0x09c4
++#define mmDCP2_DC_LUT_WRITE_EN_MASK_BASE_IDX 2
++#define mmDCP2_DC_LUT_AUTOFILL 0x09c5
++#define mmDCP2_DC_LUT_AUTOFILL_BASE_IDX 2
++#define mmDCP2_DC_LUT_CONTROL 0x09c6
++#define mmDCP2_DC_LUT_CONTROL_BASE_IDX 2
++#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE 0x09c7
++#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2
++#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN 0x09c8
++#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2
++#define mmDCP2_DC_LUT_BLACK_OFFSET_RED 0x09c9
++#define mmDCP2_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2
++#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE 0x09ca
++#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2
++#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN 0x09cb
++#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2
++#define mmDCP2_DC_LUT_WHITE_OFFSET_RED 0x09cc
++#define mmDCP2_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2
++#define mmDCP2_DCP_CRC_CONTROL 0x09cd
++#define mmDCP2_DCP_CRC_CONTROL_BASE_IDX 2
++#define mmDCP2_DCP_CRC_MASK 0x09ce
++#define mmDCP2_DCP_CRC_MASK_BASE_IDX 2
++#define mmDCP2_DCP_CRC_CURRENT 0x09cf
++#define mmDCP2_DCP_CRC_CURRENT_BASE_IDX 2
++#define mmDCP2_DVMM_PTE_CONTROL 0x09d0
++#define mmDCP2_DVMM_PTE_CONTROL_BASE_IDX 2
++#define mmDCP2_DCP_CRC_LAST 0x09d1
++#define mmDCP2_DCP_CRC_LAST_BASE_IDX 2
++#define mmDCP2_DVMM_PTE_ARB_CONTROL 0x09d2
++#define mmDCP2_DVMM_PTE_ARB_CONTROL_BASE_IDX 2
++#define mmDCP2_GRPH_FLIP_RATE_CNTL 0x09d4
++#define mmDCP2_GRPH_FLIP_RATE_CNTL_BASE_IDX 2
++#define mmDCP2_DCP_GSL_CONTROL 0x09d5
++#define mmDCP2_DCP_GSL_CONTROL_BASE_IDX 2
++#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x09d6
++#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2
++#define mmDCP2_GRPH_STEREOSYNC_FLIP 0x09dc
++#define mmDCP2_GRPH_STEREOSYNC_FLIP_BASE_IDX 2
++#define mmDCP2_HW_ROTATION 0x09de
++#define mmDCP2_HW_ROTATION_BASE_IDX 2
++#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x09df
++#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2
++#define mmDCP2_REGAMMA_CONTROL 0x09e0
++#define mmDCP2_REGAMMA_CONTROL_BASE_IDX 2
++#define mmDCP2_REGAMMA_LUT_INDEX 0x09e1
++#define mmDCP2_REGAMMA_LUT_INDEX_BASE_IDX 2
++#define mmDCP2_REGAMMA_LUT_DATA 0x09e2
++#define mmDCP2_REGAMMA_LUT_DATA_BASE_IDX 2
++#define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK 0x09e3
++#define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2
++#define mmDCP2_REGAMMA_CNTLA_START_CNTL 0x09e4
++#define mmDCP2_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2
++#define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL 0x09e5
++#define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2
++#define mmDCP2_REGAMMA_CNTLA_END_CNTL1 0x09e6
++#define mmDCP2_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2
++#define mmDCP2_REGAMMA_CNTLA_END_CNTL2 0x09e7
++#define mmDCP2_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2
++#define mmDCP2_REGAMMA_CNTLA_REGION_0_1 0x09e8
++#define mmDCP2_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2
++#define mmDCP2_REGAMMA_CNTLA_REGION_2_3 0x09e9
++#define mmDCP2_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2
++#define mmDCP2_REGAMMA_CNTLA_REGION_4_5 0x09ea
++#define mmDCP2_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2
++#define mmDCP2_REGAMMA_CNTLA_REGION_6_7 0x09eb
++#define mmDCP2_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2
++#define mmDCP2_REGAMMA_CNTLA_REGION_8_9 0x09ec
++#define mmDCP2_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2
++#define mmDCP2_REGAMMA_CNTLA_REGION_10_11 0x09ed
++#define mmDCP2_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2
++#define mmDCP2_REGAMMA_CNTLA_REGION_12_13 0x09ee
++#define mmDCP2_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2
++#define mmDCP2_REGAMMA_CNTLA_REGION_14_15 0x09ef
++#define mmDCP2_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2
++#define mmDCP2_REGAMMA_CNTLB_START_CNTL 0x09f0
++#define mmDCP2_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2
++#define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL 0x09f1
++#define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2
++#define mmDCP2_REGAMMA_CNTLB_END_CNTL1 0x09f2
++#define mmDCP2_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2
++#define mmDCP2_REGAMMA_CNTLB_END_CNTL2 0x09f3
++#define mmDCP2_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2
++#define mmDCP2_REGAMMA_CNTLB_REGION_0_1 0x09f4
++#define mmDCP2_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2
++#define mmDCP2_REGAMMA_CNTLB_REGION_2_3 0x09f5
++#define mmDCP2_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2
++#define mmDCP2_REGAMMA_CNTLB_REGION_4_5 0x09f6
++#define mmDCP2_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2
++#define mmDCP2_REGAMMA_CNTLB_REGION_6_7 0x09f7
++#define mmDCP2_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2
++#define mmDCP2_REGAMMA_CNTLB_REGION_8_9 0x09f8
++#define mmDCP2_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2
++#define mmDCP2_REGAMMA_CNTLB_REGION_10_11 0x09f9
++#define mmDCP2_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2
++#define mmDCP2_REGAMMA_CNTLB_REGION_12_13 0x09fa
++#define mmDCP2_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2
++#define mmDCP2_REGAMMA_CNTLB_REGION_14_15 0x09fb
++#define mmDCP2_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2
++#define mmDCP2_ALPHA_CONTROL 0x09fc
++#define mmDCP2_ALPHA_CONTROL_BASE_IDX 2
++#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x09fd
++#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2
++#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x09fe
++#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
++#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x09ff
++#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2
++#define mmDCP2_GRPH_XDMA_FLIP_TIMEOUT 0x0a00
++#define mmDCP2_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2
++#define mmDCP2_GRPH_XDMA_FLIP_AVG_DELAY 0x0a01
++#define mmDCP2_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2
++#define mmDCP2_GRPH_SURFACE_COUNTER_CONTROL 0x0a02
++#define mmDCP2_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2
++#define mmDCP2_GRPH_SURFACE_COUNTER_OUTPUT 0x0a03
++#define mmDCP2_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2
++
++
++// addressBlock: dce_dc_lb2_dispdec
++// base address: 0x1000
++#define mmLB2_LB_DATA_FORMAT 0x0a1a
++#define mmLB2_LB_DATA_FORMAT_BASE_IDX 2
++#define mmLB2_LB_MEMORY_CTRL 0x0a1b
++#define mmLB2_LB_MEMORY_CTRL_BASE_IDX 2
++#define mmLB2_LB_MEMORY_SIZE_STATUS 0x0a1c
++#define mmLB2_LB_MEMORY_SIZE_STATUS_BASE_IDX 2
++#define mmLB2_LB_DESKTOP_HEIGHT 0x0a1d
++#define mmLB2_LB_DESKTOP_HEIGHT_BASE_IDX 2
++#define mmLB2_LB_VLINE_START_END 0x0a1e
++#define mmLB2_LB_VLINE_START_END_BASE_IDX 2
++#define mmLB2_LB_VLINE2_START_END 0x0a1f
++#define mmLB2_LB_VLINE2_START_END_BASE_IDX 2
++#define mmLB2_LB_V_COUNTER 0x0a20
++#define mmLB2_LB_V_COUNTER_BASE_IDX 2
++#define mmLB2_LB_SNAPSHOT_V_COUNTER 0x0a21
++#define mmLB2_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2
++#define mmLB2_LB_INTERRUPT_MASK 0x0a22
++#define mmLB2_LB_INTERRUPT_MASK_BASE_IDX 2
++#define mmLB2_LB_VLINE_STATUS 0x0a23
++#define mmLB2_LB_VLINE_STATUS_BASE_IDX 2
++#define mmLB2_LB_VLINE2_STATUS 0x0a24
++#define mmLB2_LB_VLINE2_STATUS_BASE_IDX 2
++#define mmLB2_LB_VBLANK_STATUS 0x0a25
++#define mmLB2_LB_VBLANK_STATUS_BASE_IDX 2
++#define mmLB2_LB_SYNC_RESET_SEL 0x0a26
++#define mmLB2_LB_SYNC_RESET_SEL_BASE_IDX 2
++#define mmLB2_LB_BLACK_KEYER_R_CR 0x0a27
++#define mmLB2_LB_BLACK_KEYER_R_CR_BASE_IDX 2
++#define mmLB2_LB_BLACK_KEYER_G_Y 0x0a28
++#define mmLB2_LB_BLACK_KEYER_G_Y_BASE_IDX 2
++#define mmLB2_LB_BLACK_KEYER_B_CB 0x0a29
++#define mmLB2_LB_BLACK_KEYER_B_CB_BASE_IDX 2
++#define mmLB2_LB_KEYER_COLOR_CTRL 0x0a2a
++#define mmLB2_LB_KEYER_COLOR_CTRL_BASE_IDX 2
++#define mmLB2_LB_KEYER_COLOR_R_CR 0x0a2b
++#define mmLB2_LB_KEYER_COLOR_R_CR_BASE_IDX 2
++#define mmLB2_LB_KEYER_COLOR_G_Y 0x0a2c
++#define mmLB2_LB_KEYER_COLOR_G_Y_BASE_IDX 2
++#define mmLB2_LB_KEYER_COLOR_B_CB 0x0a2d
++#define mmLB2_LB_KEYER_COLOR_B_CB_BASE_IDX 2
++#define mmLB2_LB_KEYER_COLOR_REP_R_CR 0x0a2e
++#define mmLB2_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2
++#define mmLB2_LB_KEYER_COLOR_REP_G_Y 0x0a2f
++#define mmLB2_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2
++#define mmLB2_LB_KEYER_COLOR_REP_B_CB 0x0a30
++#define mmLB2_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2
++#define mmLB2_LB_BUFFER_LEVEL_STATUS 0x0a31
++#define mmLB2_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2
++#define mmLB2_LB_BUFFER_URGENCY_CTRL 0x0a32
++#define mmLB2_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2
++#define mmLB2_LB_BUFFER_URGENCY_STATUS 0x0a33
++#define mmLB2_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2
++#define mmLB2_LB_BUFFER_STATUS 0x0a34
++#define mmLB2_LB_BUFFER_STATUS_BASE_IDX 2
++#define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0x0a35
++#define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2
++#define mmLB2_MVP_AFR_FLIP_MODE 0x0a36
++#define mmLB2_MVP_AFR_FLIP_MODE_BASE_IDX 2
++#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0x0a37
++#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2
++#define mmLB2_MVP_FLIP_LINE_NUM_INSERT 0x0a38
++#define mmLB2_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2
++#define mmLB2_DC_MVP_LB_CONTROL 0x0a39
++#define mmLB2_DC_MVP_LB_CONTROL_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dcfe2_dispdec
++// base address: 0x1000
++#define mmDCFE2_DCFE_CLOCK_CONTROL 0x0a5a
++#define mmDCFE2_DCFE_CLOCK_CONTROL_BASE_IDX 2
++#define mmDCFE2_DCFE_SOFT_RESET 0x0a5b
++#define mmDCFE2_DCFE_SOFT_RESET_BASE_IDX 2
++#define mmDCFE2_DCFE_MEM_PWR_CTRL 0x0a5d
++#define mmDCFE2_DCFE_MEM_PWR_CTRL_BASE_IDX 2
++#define mmDCFE2_DCFE_MEM_PWR_CTRL2 0x0a5e
++#define mmDCFE2_DCFE_MEM_PWR_CTRL2_BASE_IDX 2
++#define mmDCFE2_DCFE_MEM_PWR_STATUS 0x0a5f
++#define mmDCFE2_DCFE_MEM_PWR_STATUS_BASE_IDX 2
++#define mmDCFE2_DCFE_MISC 0x0a60
++#define mmDCFE2_DCFE_MISC_BASE_IDX 2
++#define mmDCFE2_DCFE_FLUSH 0x0a61
++#define mmDCFE2_DCFE_FLUSH_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dc_perfmon5_dispdec
++// base address: 0x2938
++#define mmDC_PERFMON5_PERFCOUNTER_CNTL 0x0a6e
++#define mmDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX 2
++#define mmDC_PERFMON5_PERFCOUNTER_CNTL2 0x0a6f
++#define mmDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX 2
++#define mmDC_PERFMON5_PERFCOUNTER_STATE 0x0a70
++#define mmDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX 2
++#define mmDC_PERFMON5_PERFMON_CNTL 0x0a71
++#define mmDC_PERFMON5_PERFMON_CNTL_BASE_IDX 2
++#define mmDC_PERFMON5_PERFMON_CNTL2 0x0a72
++#define mmDC_PERFMON5_PERFMON_CNTL2_BASE_IDX 2
++#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x0a73
++#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
++#define mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x0a74
++#define mmDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX 2
++#define mmDC_PERFMON5_PERFMON_HI 0x0a75
++#define mmDC_PERFMON5_PERFMON_HI_BASE_IDX 2
++#define mmDC_PERFMON5_PERFMON_LOW 0x0a76
++#define mmDC_PERFMON5_PERFMON_LOW_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dmif_pg2_dispdec
++// base address: 0x1000
++#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 0x0a7a
++#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
++#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 0x0a7b
++#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
++#define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 0x0a7c
++#define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2
++#define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL 0x0a7d
++#define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2
++#define mmDMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL 0x0a7e
++#define mmDMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2
++#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL 0x0a7f
++#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2
++#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL2 0x0a80
++#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2
++#define mmDMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL 0x0a81
++#define mmDMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2
++#define mmDMIF_PG2_DPG_REPEATER_PROGRAM 0x0a82
++#define mmDMIF_PG2_DPG_REPEATER_PROGRAM_BASE_IDX 2
++#define mmDMIF_PG2_DPG_CHK_PRE_PROC_CNTL 0x0a86
++#define mmDMIF_PG2_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2
++#define mmDMIF_PG2_DPG_DVMM_STATUS 0x0a87
++#define mmDMIF_PG2_DPG_DVMM_STATUS_BASE_IDX 2
++
++
++// addressBlock: dce_dc_scl2_dispdec
++// base address: 0x1000
++#define mmSCL2_SCL_COEF_RAM_SELECT 0x0a9a
++#define mmSCL2_SCL_COEF_RAM_SELECT_BASE_IDX 2
++#define mmSCL2_SCL_COEF_RAM_TAP_DATA 0x0a9b
++#define mmSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
++#define mmSCL2_SCL_MODE 0x0a9c
++#define mmSCL2_SCL_MODE_BASE_IDX 2
++#define mmSCL2_SCL_TAP_CONTROL 0x0a9d
++#define mmSCL2_SCL_TAP_CONTROL_BASE_IDX 2
++#define mmSCL2_SCL_CONTROL 0x0a9e
++#define mmSCL2_SCL_CONTROL_BASE_IDX 2
++#define mmSCL2_SCL_BYPASS_CONTROL 0x0a9f
++#define mmSCL2_SCL_BYPASS_CONTROL_BASE_IDX 2
++#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0aa0
++#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
++#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL 0x0aa1
++#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2
++#define mmSCL2_SCL_HORZ_FILTER_CONTROL 0x0aa2
++#define mmSCL2_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2
++#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0aa3
++#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
++#define mmSCL2_SCL_HORZ_FILTER_INIT 0x0aa4
++#define mmSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2
++#define mmSCL2_SCL_VERT_FILTER_CONTROL 0x0aa5
++#define mmSCL2_SCL_VERT_FILTER_CONTROL_BASE_IDX 2
++#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0aa6
++#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
++#define mmSCL2_SCL_VERT_FILTER_INIT 0x0aa7
++#define mmSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2
++#define mmSCL2_SCL_VERT_FILTER_INIT_BOT 0x0aa8
++#define mmSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
++#define mmSCL2_SCL_ROUND_OFFSET 0x0aa9
++#define mmSCL2_SCL_ROUND_OFFSET_BASE_IDX 2
++#define mmSCL2_SCL_UPDATE 0x0aaa
++#define mmSCL2_SCL_UPDATE_BASE_IDX 2
++#define mmSCL2_SCL_F_SHARP_CONTROL 0x0aab
++#define mmSCL2_SCL_F_SHARP_CONTROL_BASE_IDX 2
++#define mmSCL2_SCL_ALU_CONTROL 0x0aac
++#define mmSCL2_SCL_ALU_CONTROL_BASE_IDX 2
++#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0x0aad
++#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
++#define mmSCL2_VIEWPORT_START_SECONDARY 0x0aae
++#define mmSCL2_VIEWPORT_START_SECONDARY_BASE_IDX 2
++#define mmSCL2_VIEWPORT_START 0x0aaf
++#define mmSCL2_VIEWPORT_START_BASE_IDX 2
++#define mmSCL2_VIEWPORT_SIZE 0x0ab0
++#define mmSCL2_VIEWPORT_SIZE_BASE_IDX 2
++#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT 0x0ab1
++#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
++#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM 0x0ab2
++#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
++#define mmSCL2_SCL_MODE_CHANGE_DET1 0x0ab3
++#define mmSCL2_SCL_MODE_CHANGE_DET1_BASE_IDX 2
++#define mmSCL2_SCL_MODE_CHANGE_DET2 0x0ab4
++#define mmSCL2_SCL_MODE_CHANGE_DET2_BASE_IDX 2
++#define mmSCL2_SCL_MODE_CHANGE_DET3 0x0ab5
++#define mmSCL2_SCL_MODE_CHANGE_DET3_BASE_IDX 2
++#define mmSCL2_SCL_MODE_CHANGE_MASK 0x0ab6
++#define mmSCL2_SCL_MODE_CHANGE_MASK_BASE_IDX 2
++
++
++// addressBlock: dce_dc_blnd2_dispdec
++// base address: 0x1000
++#define mmBLND2_BLND_CONTROL 0x0ac7
++#define mmBLND2_BLND_CONTROL_BASE_IDX 2
++#define mmBLND2_BLND_SM_CONTROL2 0x0ac8
++#define mmBLND2_BLND_SM_CONTROL2_BASE_IDX 2
++#define mmBLND2_BLND_CONTROL2 0x0ac9
++#define mmBLND2_BLND_CONTROL2_BASE_IDX 2
++#define mmBLND2_BLND_UPDATE 0x0aca
++#define mmBLND2_BLND_UPDATE_BASE_IDX 2
++#define mmBLND2_BLND_UNDERFLOW_INTERRUPT 0x0acb
++#define mmBLND2_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2
++#define mmBLND2_BLND_V_UPDATE_LOCK 0x0acc
++#define mmBLND2_BLND_V_UPDATE_LOCK_BASE_IDX 2
++#define mmBLND2_BLND_REG_UPDATE_STATUS 0x0acd
++#define mmBLND2_BLND_REG_UPDATE_STATUS_BASE_IDX 2
++
++
++// addressBlock: dce_dc_crtc2_dispdec
++// base address: 0x1000
++#define mmCRTC2_CRTC_H_BLANK_EARLY_NUM 0x0ad2
++#define mmCRTC2_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2
++#define mmCRTC2_CRTC_H_TOTAL 0x0ad3
++#define mmCRTC2_CRTC_H_TOTAL_BASE_IDX 2
++#define mmCRTC2_CRTC_H_BLANK_START_END 0x0ad4
++#define mmCRTC2_CRTC_H_BLANK_START_END_BASE_IDX 2
++#define mmCRTC2_CRTC_H_SYNC_A 0x0ad5
++#define mmCRTC2_CRTC_H_SYNC_A_BASE_IDX 2
++#define mmCRTC2_CRTC_H_SYNC_A_CNTL 0x0ad6
++#define mmCRTC2_CRTC_H_SYNC_A_CNTL_BASE_IDX 2
++#define mmCRTC2_CRTC_H_SYNC_B 0x0ad7
++#define mmCRTC2_CRTC_H_SYNC_B_BASE_IDX 2
++#define mmCRTC2_CRTC_H_SYNC_B_CNTL 0x0ad8
++#define mmCRTC2_CRTC_H_SYNC_B_CNTL_BASE_IDX 2
++#define mmCRTC2_CRTC_VBI_END 0x0ad9
++#define mmCRTC2_CRTC_VBI_END_BASE_IDX 2
++#define mmCRTC2_CRTC_V_TOTAL 0x0ada
++#define mmCRTC2_CRTC_V_TOTAL_BASE_IDX 2
++#define mmCRTC2_CRTC_V_TOTAL_MIN 0x0adb
++#define mmCRTC2_CRTC_V_TOTAL_MIN_BASE_IDX 2
++#define mmCRTC2_CRTC_V_TOTAL_MAX 0x0adc
++#define mmCRTC2_CRTC_V_TOTAL_MAX_BASE_IDX 2
++#define mmCRTC2_CRTC_V_TOTAL_CONTROL 0x0add
++#define mmCRTC2_CRTC_V_TOTAL_CONTROL_BASE_IDX 2
++#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS 0x0ade
++#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2
++#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS 0x0adf
++#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2
++#define mmCRTC2_CRTC_V_BLANK_START_END 0x0ae0
++#define mmCRTC2_CRTC_V_BLANK_START_END_BASE_IDX 2
++#define mmCRTC2_CRTC_V_SYNC_A 0x0ae1
++#define mmCRTC2_CRTC_V_SYNC_A_BASE_IDX 2
++#define mmCRTC2_CRTC_V_SYNC_A_CNTL 0x0ae2
++#define mmCRTC2_CRTC_V_SYNC_A_CNTL_BASE_IDX 2
++#define mmCRTC2_CRTC_V_SYNC_B 0x0ae3
++#define mmCRTC2_CRTC_V_SYNC_B_BASE_IDX 2
++#define mmCRTC2_CRTC_V_SYNC_B_CNTL 0x0ae4
++#define mmCRTC2_CRTC_V_SYNC_B_CNTL_BASE_IDX 2
++#define mmCRTC2_CRTC_DTMTEST_CNTL 0x0ae5
++#define mmCRTC2_CRTC_DTMTEST_CNTL_BASE_IDX 2
++#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION 0x0ae6
++#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2
++#define mmCRTC2_CRTC_TRIGA_CNTL 0x0ae7
++#define mmCRTC2_CRTC_TRIGA_CNTL_BASE_IDX 2
++#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG 0x0ae8
++#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2
++#define mmCRTC2_CRTC_TRIGB_CNTL 0x0ae9
++#define mmCRTC2_CRTC_TRIGB_CNTL_BASE_IDX 2
++#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG 0x0aea
++#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2
++#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL 0x0aeb
++#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
++#define mmCRTC2_CRTC_FLOW_CONTROL 0x0aec
++#define mmCRTC2_CRTC_FLOW_CONTROL_BASE_IDX 2
++#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE 0x0aed
++#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
++#define mmCRTC2_CRTC_AVSYNC_COUNTER 0x0aee
++#define mmCRTC2_CRTC_AVSYNC_COUNTER_BASE_IDX 2
++#define mmCRTC2_CRTC_CONTROL 0x0aef
++#define mmCRTC2_CRTC_CONTROL_BASE_IDX 2
++#define mmCRTC2_CRTC_BLANK_CONTROL 0x0af0
++#define mmCRTC2_CRTC_BLANK_CONTROL_BASE_IDX 2
++#define mmCRTC2_CRTC_INTERLACE_CONTROL 0x0af1
++#define mmCRTC2_CRTC_INTERLACE_CONTROL_BASE_IDX 2
++#define mmCRTC2_CRTC_INTERLACE_STATUS 0x0af2
++#define mmCRTC2_CRTC_INTERLACE_STATUS_BASE_IDX 2
++#define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL 0x0af3
++#define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2
++#define mmCRTC2_CRTC_PIXEL_DATA_READBACK0 0x0af4
++#define mmCRTC2_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2
++#define mmCRTC2_CRTC_PIXEL_DATA_READBACK1 0x0af5
++#define mmCRTC2_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2
++#define mmCRTC2_CRTC_STATUS 0x0af6
++#define mmCRTC2_CRTC_STATUS_BASE_IDX 2
++#define mmCRTC2_CRTC_STATUS_POSITION 0x0af7
++#define mmCRTC2_CRTC_STATUS_POSITION_BASE_IDX 2
++#define mmCRTC2_CRTC_NOM_VERT_POSITION 0x0af8
++#define mmCRTC2_CRTC_NOM_VERT_POSITION_BASE_IDX 2
++#define mmCRTC2_CRTC_STATUS_FRAME_COUNT 0x0af9
++#define mmCRTC2_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2
++#define mmCRTC2_CRTC_STATUS_VF_COUNT 0x0afa
++#define mmCRTC2_CRTC_STATUS_VF_COUNT_BASE_IDX 2
++#define mmCRTC2_CRTC_STATUS_HV_COUNT 0x0afb
++#define mmCRTC2_CRTC_STATUS_HV_COUNT_BASE_IDX 2
++#define mmCRTC2_CRTC_COUNT_CONTROL 0x0afc
++#define mmCRTC2_CRTC_COUNT_CONTROL_BASE_IDX 2
++#define mmCRTC2_CRTC_COUNT_RESET 0x0afd
++#define mmCRTC2_CRTC_COUNT_RESET_BASE_IDX 2
++#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x0afe
++#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
++#define mmCRTC2_CRTC_VERT_SYNC_CONTROL 0x0aff
++#define mmCRTC2_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2
++#define mmCRTC2_CRTC_STEREO_STATUS 0x0b00
++#define mmCRTC2_CRTC_STEREO_STATUS_BASE_IDX 2
++#define mmCRTC2_CRTC_STEREO_CONTROL 0x0b01
++#define mmCRTC2_CRTC_STEREO_CONTROL_BASE_IDX 2
++#define mmCRTC2_CRTC_SNAPSHOT_STATUS 0x0b02
++#define mmCRTC2_CRTC_SNAPSHOT_STATUS_BASE_IDX 2
++#define mmCRTC2_CRTC_SNAPSHOT_CONTROL 0x0b03
++#define mmCRTC2_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2
++#define mmCRTC2_CRTC_SNAPSHOT_POSITION 0x0b04
++#define mmCRTC2_CRTC_SNAPSHOT_POSITION_BASE_IDX 2
++#define mmCRTC2_CRTC_SNAPSHOT_FRAME 0x0b05
++#define mmCRTC2_CRTC_SNAPSHOT_FRAME_BASE_IDX 2
++#define mmCRTC2_CRTC_START_LINE_CONTROL 0x0b06
++#define mmCRTC2_CRTC_START_LINE_CONTROL_BASE_IDX 2
++#define mmCRTC2_CRTC_INTERRUPT_CONTROL 0x0b07
++#define mmCRTC2_CRTC_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmCRTC2_CRTC_UPDATE_LOCK 0x0b08
++#define mmCRTC2_CRTC_UPDATE_LOCK_BASE_IDX 2
++#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL 0x0b09
++#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
++#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x0b0a
++#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2
++#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL 0x0b0b
++#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2
++#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS 0x0b0c
++#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2
++#define mmCRTC2_CRTC_TEST_PATTERN_COLOR 0x0b0d
++#define mmCRTC2_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2
++#define mmCRTC2_CRTC_MASTER_UPDATE_LOCK 0x0b0e
++#define mmCRTC2_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2
++#define mmCRTC2_CRTC_MASTER_UPDATE_MODE 0x0b0f
++#define mmCRTC2_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2
++#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT 0x0b10
++#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2
++#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x0b11
++#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2
++#define mmCRTC2_CRTC_MVP_STATUS 0x0b12
++#define mmCRTC2_CRTC_MVP_STATUS_BASE_IDX 2
++#define mmCRTC2_CRTC_MASTER_EN 0x0b13
++#define mmCRTC2_CRTC_MASTER_EN_BASE_IDX 2
++#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT 0x0b14
++#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2
++#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS 0x0b15
++#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2
++#define mmCRTC2_CRTC_OVERSCAN_COLOR 0x0b17
++#define mmCRTC2_CRTC_OVERSCAN_COLOR_BASE_IDX 2
++#define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT 0x0b18
++#define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2
++#define mmCRTC2_CRTC_BLANK_DATA_COLOR 0x0b19
++#define mmCRTC2_CRTC_BLANK_DATA_COLOR_BASE_IDX 2
++#define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT 0x0b1a
++#define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2
++#define mmCRTC2_CRTC_BLACK_COLOR 0x0b1b
++#define mmCRTC2_CRTC_BLACK_COLOR_BASE_IDX 2
++#define mmCRTC2_CRTC_BLACK_COLOR_EXT 0x0b1c
++#define mmCRTC2_CRTC_BLACK_COLOR_EXT_BASE_IDX 2
++#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION 0x0b1d
++#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
++#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x0b1e
++#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
++#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION 0x0b1f
++#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
++#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x0b20
++#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
++#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION 0x0b21
++#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
++#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x0b22
++#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
++#define mmCRTC2_CRTC_CRC_CNTL 0x0b23
++#define mmCRTC2_CRTC_CRC_CNTL_BASE_IDX 2
++#define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL 0x0b24
++#define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
++#define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL 0x0b25
++#define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
++#define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL 0x0b26
++#define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
++#define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL 0x0b27
++#define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
++#define mmCRTC2_CRTC_CRC0_DATA_RG 0x0b28
++#define mmCRTC2_CRTC_CRC0_DATA_RG_BASE_IDX 2
++#define mmCRTC2_CRTC_CRC0_DATA_B 0x0b29
++#define mmCRTC2_CRTC_CRC0_DATA_B_BASE_IDX 2
++#define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL 0x0b2a
++#define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
++#define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL 0x0b2b
++#define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
++#define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL 0x0b2c
++#define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
++#define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL 0x0b2d
++#define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
++#define mmCRTC2_CRTC_CRC1_DATA_RG 0x0b2e
++#define mmCRTC2_CRTC_CRC1_DATA_RG_BASE_IDX 2
++#define mmCRTC2_CRTC_CRC1_DATA_B 0x0b2f
++#define mmCRTC2_CRTC_CRC1_DATA_B_BASE_IDX 2
++#define mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL 0x0b30
++#define mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2
++#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x0b31
++#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2
++#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x0b32
++#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2
++#define mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x0b33
++#define mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x0b34
++#define mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x0b35
++#define mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL 0x0b36
++#define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2
++#define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL 0x0b37
++#define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2
++#define mmCRTC2_CRTC_GSL_VSYNC_GAP 0x0b38
++#define mmCRTC2_CRTC_GSL_VSYNC_GAP_BASE_IDX 2
++#define mmCRTC2_CRTC_GSL_WINDOW 0x0b39
++#define mmCRTC2_CRTC_GSL_WINDOW_BASE_IDX 2
++#define mmCRTC2_CRTC_GSL_CONTROL 0x0b3a
++#define mmCRTC2_CRTC_GSL_CONTROL_BASE_IDX 2
++#define mmCRTC2_CRTC_RANGE_TIMING_INT_STATUS 0x0b3d
++#define mmCRTC2_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2
++#define mmCRTC2_CRTC_DRR_CONTROL 0x0b3e
++#define mmCRTC2_CRTC_DRR_CONTROL_BASE_IDX 2
++
++
++// addressBlock: dce_dc_fmt2_dispdec
++// base address: 0x1000
++#define mmFMT2_FMT_CLAMP_COMPONENT_R 0x0b42
++#define mmFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
++#define mmFMT2_FMT_CLAMP_COMPONENT_G 0x0b43
++#define mmFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
++#define mmFMT2_FMT_CLAMP_COMPONENT_B 0x0b44
++#define mmFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
++#define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x0b45
++#define mmFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
++#define mmFMT2_FMT_CONTROL 0x0b46
++#define mmFMT2_FMT_CONTROL_BASE_IDX 2
++#define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x0b47
++#define mmFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
++#define mmFMT2_FMT_DITHER_RAND_R_SEED 0x0b48
++#define mmFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
++#define mmFMT2_FMT_DITHER_RAND_G_SEED 0x0b49
++#define mmFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
++#define mmFMT2_FMT_DITHER_RAND_B_SEED 0x0b4a
++#define mmFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
++#define mmFMT2_FMT_CLAMP_CNTL 0x0b4e
++#define mmFMT2_FMT_CLAMP_CNTL_BASE_IDX 2
++#define mmFMT2_FMT_CRC_CNTL 0x0b4f
++#define mmFMT2_FMT_CRC_CNTL_BASE_IDX 2
++#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK 0x0b50
++#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
++#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x0b51
++#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
++#define mmFMT2_FMT_CRC_SIG_RED_GREEN 0x0b52
++#define mmFMT2_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2
++#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL 0x0b53
++#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2
++#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x0b54
++#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
++#define mmFMT2_FMT_420_HBLANK_EARLY_START 0x0b55
++#define mmFMT2_FMT_420_HBLANK_EARLY_START_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dcp3_dispdec
++// base address: 0x1800
++#define mmDCP3_GRPH_ENABLE 0x0b5a
++#define mmDCP3_GRPH_ENABLE_BASE_IDX 2
++#define mmDCP3_GRPH_CONTROL 0x0b5b
++#define mmDCP3_GRPH_CONTROL_BASE_IDX 2
++#define mmDCP3_GRPH_LUT_10BIT_BYPASS 0x0b5c
++#define mmDCP3_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2
++#define mmDCP3_GRPH_SWAP_CNTL 0x0b5d
++#define mmDCP3_GRPH_SWAP_CNTL_BASE_IDX 2
++#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS 0x0b5e
++#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
++#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS 0x0b5f
++#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
++#define mmDCP3_GRPH_PITCH 0x0b60
++#define mmDCP3_GRPH_PITCH_BASE_IDX 2
++#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0b61
++#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
++#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0b62
++#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
++#define mmDCP3_GRPH_SURFACE_OFFSET_X 0x0b63
++#define mmDCP3_GRPH_SURFACE_OFFSET_X_BASE_IDX 2
++#define mmDCP3_GRPH_SURFACE_OFFSET_Y 0x0b64
++#define mmDCP3_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2
++#define mmDCP3_GRPH_X_START 0x0b65
++#define mmDCP3_GRPH_X_START_BASE_IDX 2
++#define mmDCP3_GRPH_Y_START 0x0b66
++#define mmDCP3_GRPH_Y_START_BASE_IDX 2
++#define mmDCP3_GRPH_X_END 0x0b67
++#define mmDCP3_GRPH_X_END_BASE_IDX 2
++#define mmDCP3_GRPH_Y_END 0x0b68
++#define mmDCP3_GRPH_Y_END_BASE_IDX 2
++#define mmDCP3_INPUT_GAMMA_CONTROL 0x0b69
++#define mmDCP3_INPUT_GAMMA_CONTROL_BASE_IDX 2
++#define mmDCP3_GRPH_UPDATE 0x0b6a
++#define mmDCP3_GRPH_UPDATE_BASE_IDX 2
++#define mmDCP3_GRPH_FLIP_CONTROL 0x0b6b
++#define mmDCP3_GRPH_FLIP_CONTROL_BASE_IDX 2
++#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE 0x0b6c
++#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2
++#define mmDCP3_GRPH_DFQ_CONTROL 0x0b6d
++#define mmDCP3_GRPH_DFQ_CONTROL_BASE_IDX 2
++#define mmDCP3_GRPH_DFQ_STATUS 0x0b6e
++#define mmDCP3_GRPH_DFQ_STATUS_BASE_IDX 2
++#define mmDCP3_GRPH_INTERRUPT_STATUS 0x0b6f
++#define mmDCP3_GRPH_INTERRUPT_STATUS_BASE_IDX 2
++#define mmDCP3_GRPH_INTERRUPT_CONTROL 0x0b70
++#define mmDCP3_GRPH_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0b71
++#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2
++#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS 0x0b72
++#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2
++#define mmDCP3_GRPH_COMPRESS_PITCH 0x0b73
++#define mmDCP3_GRPH_COMPRESS_PITCH_BASE_IDX 2
++#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0b74
++#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2
++#define mmDCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0b75
++#define mmDCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2
++#define mmDCP3_PRESCALE_GRPH_CONTROL 0x0b76
++#define mmDCP3_PRESCALE_GRPH_CONTROL_BASE_IDX 2
++#define mmDCP3_PRESCALE_VALUES_GRPH_R 0x0b77
++#define mmDCP3_PRESCALE_VALUES_GRPH_R_BASE_IDX 2
++#define mmDCP3_PRESCALE_VALUES_GRPH_G 0x0b78
++#define mmDCP3_PRESCALE_VALUES_GRPH_G_BASE_IDX 2
++#define mmDCP3_PRESCALE_VALUES_GRPH_B 0x0b79
++#define mmDCP3_PRESCALE_VALUES_GRPH_B_BASE_IDX 2
++#define mmDCP3_INPUT_CSC_CONTROL 0x0b7a
++#define mmDCP3_INPUT_CSC_CONTROL_BASE_IDX 2
++#define mmDCP3_INPUT_CSC_C11_C12 0x0b7b
++#define mmDCP3_INPUT_CSC_C11_C12_BASE_IDX 2
++#define mmDCP3_INPUT_CSC_C13_C14 0x0b7c
++#define mmDCP3_INPUT_CSC_C13_C14_BASE_IDX 2
++#define mmDCP3_INPUT_CSC_C21_C22 0x0b7d
++#define mmDCP3_INPUT_CSC_C21_C22_BASE_IDX 2
++#define mmDCP3_INPUT_CSC_C23_C24 0x0b7e
++#define mmDCP3_INPUT_CSC_C23_C24_BASE_IDX 2
++#define mmDCP3_INPUT_CSC_C31_C32 0x0b7f
++#define mmDCP3_INPUT_CSC_C31_C32_BASE_IDX 2
++#define mmDCP3_INPUT_CSC_C33_C34 0x0b80
++#define mmDCP3_INPUT_CSC_C33_C34_BASE_IDX 2
++#define mmDCP3_OUTPUT_CSC_CONTROL 0x0b81
++#define mmDCP3_OUTPUT_CSC_CONTROL_BASE_IDX 2
++#define mmDCP3_OUTPUT_CSC_C11_C12 0x0b82
++#define mmDCP3_OUTPUT_CSC_C11_C12_BASE_IDX 2
++#define mmDCP3_OUTPUT_CSC_C13_C14 0x0b83
++#define mmDCP3_OUTPUT_CSC_C13_C14_BASE_IDX 2
++#define mmDCP3_OUTPUT_CSC_C21_C22 0x0b84
++#define mmDCP3_OUTPUT_CSC_C21_C22_BASE_IDX 2
++#define mmDCP3_OUTPUT_CSC_C23_C24 0x0b85
++#define mmDCP3_OUTPUT_CSC_C23_C24_BASE_IDX 2
++#define mmDCP3_OUTPUT_CSC_C31_C32 0x0b86
++#define mmDCP3_OUTPUT_CSC_C31_C32_BASE_IDX 2
++#define mmDCP3_OUTPUT_CSC_C33_C34 0x0b87
++#define mmDCP3_OUTPUT_CSC_C33_C34_BASE_IDX 2
++#define mmDCP3_COMM_MATRIXA_TRANS_C11_C12 0x0b88
++#define mmDCP3_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2
++#define mmDCP3_COMM_MATRIXA_TRANS_C13_C14 0x0b89
++#define mmDCP3_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2
++#define mmDCP3_COMM_MATRIXA_TRANS_C21_C22 0x0b8a
++#define mmDCP3_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2
++#define mmDCP3_COMM_MATRIXA_TRANS_C23_C24 0x0b8b
++#define mmDCP3_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2
++#define mmDCP3_COMM_MATRIXA_TRANS_C31_C32 0x0b8c
++#define mmDCP3_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2
++#define mmDCP3_COMM_MATRIXA_TRANS_C33_C34 0x0b8d
++#define mmDCP3_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2
++#define mmDCP3_COMM_MATRIXB_TRANS_C11_C12 0x0b8e
++#define mmDCP3_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2
++#define mmDCP3_COMM_MATRIXB_TRANS_C13_C14 0x0b8f
++#define mmDCP3_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2
++#define mmDCP3_COMM_MATRIXB_TRANS_C21_C22 0x0b90
++#define mmDCP3_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2
++#define mmDCP3_COMM_MATRIXB_TRANS_C23_C24 0x0b91
++#define mmDCP3_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2
++#define mmDCP3_COMM_MATRIXB_TRANS_C31_C32 0x0b92
++#define mmDCP3_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2
++#define mmDCP3_COMM_MATRIXB_TRANS_C33_C34 0x0b93
++#define mmDCP3_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2
++#define mmDCP3_DENORM_CONTROL 0x0b94
++#define mmDCP3_DENORM_CONTROL_BASE_IDX 2
++#define mmDCP3_OUT_ROUND_CONTROL 0x0b95
++#define mmDCP3_OUT_ROUND_CONTROL_BASE_IDX 2
++#define mmDCP3_OUT_CLAMP_CONTROL_R_CR 0x0b96
++#define mmDCP3_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2
++#define mmDCP3_OUT_CLAMP_CONTROL_G_Y 0x0b97
++#define mmDCP3_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2
++#define mmDCP3_OUT_CLAMP_CONTROL_B_CB 0x0b98
++#define mmDCP3_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2
++#define mmDCP3_KEY_CONTROL 0x0b99
++#define mmDCP3_KEY_CONTROL_BASE_IDX 2
++#define mmDCP3_KEY_RANGE_ALPHA 0x0b9a
++#define mmDCP3_KEY_RANGE_ALPHA_BASE_IDX 2
++#define mmDCP3_KEY_RANGE_RED 0x0b9b
++#define mmDCP3_KEY_RANGE_RED_BASE_IDX 2
++#define mmDCP3_KEY_RANGE_GREEN 0x0b9c
++#define mmDCP3_KEY_RANGE_GREEN_BASE_IDX 2
++#define mmDCP3_KEY_RANGE_BLUE 0x0b9d
++#define mmDCP3_KEY_RANGE_BLUE_BASE_IDX 2
++#define mmDCP3_DEGAMMA_CONTROL 0x0b9e
++#define mmDCP3_DEGAMMA_CONTROL_BASE_IDX 2
++#define mmDCP3_GAMUT_REMAP_CONTROL 0x0b9f
++#define mmDCP3_GAMUT_REMAP_CONTROL_BASE_IDX 2
++#define mmDCP3_GAMUT_REMAP_C11_C12 0x0ba0
++#define mmDCP3_GAMUT_REMAP_C11_C12_BASE_IDX 2
++#define mmDCP3_GAMUT_REMAP_C13_C14 0x0ba1
++#define mmDCP3_GAMUT_REMAP_C13_C14_BASE_IDX 2
++#define mmDCP3_GAMUT_REMAP_C21_C22 0x0ba2
++#define mmDCP3_GAMUT_REMAP_C21_C22_BASE_IDX 2
++#define mmDCP3_GAMUT_REMAP_C23_C24 0x0ba3
++#define mmDCP3_GAMUT_REMAP_C23_C24_BASE_IDX 2
++#define mmDCP3_GAMUT_REMAP_C31_C32 0x0ba4
++#define mmDCP3_GAMUT_REMAP_C31_C32_BASE_IDX 2
++#define mmDCP3_GAMUT_REMAP_C33_C34 0x0ba5
++#define mmDCP3_GAMUT_REMAP_C33_C34_BASE_IDX 2
++#define mmDCP3_DCP_SPATIAL_DITHER_CNTL 0x0ba6
++#define mmDCP3_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2
++#define mmDCP3_DCP_RANDOM_SEEDS 0x0ba7
++#define mmDCP3_DCP_RANDOM_SEEDS_BASE_IDX 2
++#define mmDCP3_DCP_FP_CONVERTED_FIELD 0x0ba8
++#define mmDCP3_DCP_FP_CONVERTED_FIELD_BASE_IDX 2
++#define mmDCP3_CUR_CONTROL 0x0ba9
++#define mmDCP3_CUR_CONTROL_BASE_IDX 2
++#define mmDCP3_CUR_SURFACE_ADDRESS 0x0baa
++#define mmDCP3_CUR_SURFACE_ADDRESS_BASE_IDX 2
++#define mmDCP3_CUR_SIZE 0x0bab
++#define mmDCP3_CUR_SIZE_BASE_IDX 2
++#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH 0x0bac
++#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
++#define mmDCP3_CUR_POSITION 0x0bad
++#define mmDCP3_CUR_POSITION_BASE_IDX 2
++#define mmDCP3_CUR_HOT_SPOT 0x0bae
++#define mmDCP3_CUR_HOT_SPOT_BASE_IDX 2
++#define mmDCP3_CUR_COLOR1 0x0baf
++#define mmDCP3_CUR_COLOR1_BASE_IDX 2
++#define mmDCP3_CUR_COLOR2 0x0bb0
++#define mmDCP3_CUR_COLOR2_BASE_IDX 2
++#define mmDCP3_CUR_UPDATE 0x0bb1
++#define mmDCP3_CUR_UPDATE_BASE_IDX 2
++#define mmDCP3_CUR_REQUEST_FILTER_CNTL 0x0bbb
++#define mmDCP3_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2
++#define mmDCP3_CUR_STEREO_CONTROL 0x0bbc
++#define mmDCP3_CUR_STEREO_CONTROL_BASE_IDX 2
++#define mmDCP3_DC_LUT_RW_MODE 0x0bbe
++#define mmDCP3_DC_LUT_RW_MODE_BASE_IDX 2
++#define mmDCP3_DC_LUT_RW_INDEX 0x0bbf
++#define mmDCP3_DC_LUT_RW_INDEX_BASE_IDX 2
++#define mmDCP3_DC_LUT_SEQ_COLOR 0x0bc0
++#define mmDCP3_DC_LUT_SEQ_COLOR_BASE_IDX 2
++#define mmDCP3_DC_LUT_PWL_DATA 0x0bc1
++#define mmDCP3_DC_LUT_PWL_DATA_BASE_IDX 2
++#define mmDCP3_DC_LUT_30_COLOR 0x0bc2
++#define mmDCP3_DC_LUT_30_COLOR_BASE_IDX 2
++#define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE 0x0bc3
++#define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2
++#define mmDCP3_DC_LUT_WRITE_EN_MASK 0x0bc4
++#define mmDCP3_DC_LUT_WRITE_EN_MASK_BASE_IDX 2
++#define mmDCP3_DC_LUT_AUTOFILL 0x0bc5
++#define mmDCP3_DC_LUT_AUTOFILL_BASE_IDX 2
++#define mmDCP3_DC_LUT_CONTROL 0x0bc6
++#define mmDCP3_DC_LUT_CONTROL_BASE_IDX 2
++#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE 0x0bc7
++#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2
++#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN 0x0bc8
++#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2
++#define mmDCP3_DC_LUT_BLACK_OFFSET_RED 0x0bc9
++#define mmDCP3_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2
++#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE 0x0bca
++#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2
++#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN 0x0bcb
++#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2
++#define mmDCP3_DC_LUT_WHITE_OFFSET_RED 0x0bcc
++#define mmDCP3_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2
++#define mmDCP3_DCP_CRC_CONTROL 0x0bcd
++#define mmDCP3_DCP_CRC_CONTROL_BASE_IDX 2
++#define mmDCP3_DCP_CRC_MASK 0x0bce
++#define mmDCP3_DCP_CRC_MASK_BASE_IDX 2
++#define mmDCP3_DCP_CRC_CURRENT 0x0bcf
++#define mmDCP3_DCP_CRC_CURRENT_BASE_IDX 2
++#define mmDCP3_DVMM_PTE_CONTROL 0x0bd0
++#define mmDCP3_DVMM_PTE_CONTROL_BASE_IDX 2
++#define mmDCP3_DCP_CRC_LAST 0x0bd1
++#define mmDCP3_DCP_CRC_LAST_BASE_IDX 2
++#define mmDCP3_DVMM_PTE_ARB_CONTROL 0x0bd2
++#define mmDCP3_DVMM_PTE_ARB_CONTROL_BASE_IDX 2
++#define mmDCP3_GRPH_FLIP_RATE_CNTL 0x0bd4
++#define mmDCP3_GRPH_FLIP_RATE_CNTL_BASE_IDX 2
++#define mmDCP3_DCP_GSL_CONTROL 0x0bd5
++#define mmDCP3_DCP_GSL_CONTROL_BASE_IDX 2
++#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x0bd6
++#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2
++#define mmDCP3_GRPH_STEREOSYNC_FLIP 0x0bdc
++#define mmDCP3_GRPH_STEREOSYNC_FLIP_BASE_IDX 2
++#define mmDCP3_HW_ROTATION 0x0bde
++#define mmDCP3_HW_ROTATION_BASE_IDX 2
++#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x0bdf
++#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2
++#define mmDCP3_REGAMMA_CONTROL 0x0be0
++#define mmDCP3_REGAMMA_CONTROL_BASE_IDX 2
++#define mmDCP3_REGAMMA_LUT_INDEX 0x0be1
++#define mmDCP3_REGAMMA_LUT_INDEX_BASE_IDX 2
++#define mmDCP3_REGAMMA_LUT_DATA 0x0be2
++#define mmDCP3_REGAMMA_LUT_DATA_BASE_IDX 2
++#define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK 0x0be3
++#define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2
++#define mmDCP3_REGAMMA_CNTLA_START_CNTL 0x0be4
++#define mmDCP3_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2
++#define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL 0x0be5
++#define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2
++#define mmDCP3_REGAMMA_CNTLA_END_CNTL1 0x0be6
++#define mmDCP3_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2
++#define mmDCP3_REGAMMA_CNTLA_END_CNTL2 0x0be7
++#define mmDCP3_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2
++#define mmDCP3_REGAMMA_CNTLA_REGION_0_1 0x0be8
++#define mmDCP3_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2
++#define mmDCP3_REGAMMA_CNTLA_REGION_2_3 0x0be9
++#define mmDCP3_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2
++#define mmDCP3_REGAMMA_CNTLA_REGION_4_5 0x0bea
++#define mmDCP3_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2
++#define mmDCP3_REGAMMA_CNTLA_REGION_6_7 0x0beb
++#define mmDCP3_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2
++#define mmDCP3_REGAMMA_CNTLA_REGION_8_9 0x0bec
++#define mmDCP3_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2
++#define mmDCP3_REGAMMA_CNTLA_REGION_10_11 0x0bed
++#define mmDCP3_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2
++#define mmDCP3_REGAMMA_CNTLA_REGION_12_13 0x0bee
++#define mmDCP3_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2
++#define mmDCP3_REGAMMA_CNTLA_REGION_14_15 0x0bef
++#define mmDCP3_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2
++#define mmDCP3_REGAMMA_CNTLB_START_CNTL 0x0bf0
++#define mmDCP3_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2
++#define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL 0x0bf1
++#define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2
++#define mmDCP3_REGAMMA_CNTLB_END_CNTL1 0x0bf2
++#define mmDCP3_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2
++#define mmDCP3_REGAMMA_CNTLB_END_CNTL2 0x0bf3
++#define mmDCP3_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2
++#define mmDCP3_REGAMMA_CNTLB_REGION_0_1 0x0bf4
++#define mmDCP3_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2
++#define mmDCP3_REGAMMA_CNTLB_REGION_2_3 0x0bf5
++#define mmDCP3_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2
++#define mmDCP3_REGAMMA_CNTLB_REGION_4_5 0x0bf6
++#define mmDCP3_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2
++#define mmDCP3_REGAMMA_CNTLB_REGION_6_7 0x0bf7
++#define mmDCP3_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2
++#define mmDCP3_REGAMMA_CNTLB_REGION_8_9 0x0bf8
++#define mmDCP3_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2
++#define mmDCP3_REGAMMA_CNTLB_REGION_10_11 0x0bf9
++#define mmDCP3_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2
++#define mmDCP3_REGAMMA_CNTLB_REGION_12_13 0x0bfa
++#define mmDCP3_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2
++#define mmDCP3_REGAMMA_CNTLB_REGION_14_15 0x0bfb
++#define mmDCP3_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2
++#define mmDCP3_ALPHA_CONTROL 0x0bfc
++#define mmDCP3_ALPHA_CONTROL_BASE_IDX 2
++#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x0bfd
++#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2
++#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x0bfe
++#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
++#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x0bff
++#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2
++#define mmDCP3_GRPH_XDMA_FLIP_TIMEOUT 0x0c00
++#define mmDCP3_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2
++#define mmDCP3_GRPH_XDMA_FLIP_AVG_DELAY 0x0c01
++#define mmDCP3_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2
++#define mmDCP3_GRPH_SURFACE_COUNTER_CONTROL 0x0c02
++#define mmDCP3_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2
++#define mmDCP3_GRPH_SURFACE_COUNTER_OUTPUT 0x0c03
++#define mmDCP3_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2
++
++
++// addressBlock: dce_dc_lb3_dispdec
++// base address: 0x1800
++#define mmLB3_LB_DATA_FORMAT 0x0c1a
++#define mmLB3_LB_DATA_FORMAT_BASE_IDX 2
++#define mmLB3_LB_MEMORY_CTRL 0x0c1b
++#define mmLB3_LB_MEMORY_CTRL_BASE_IDX 2
++#define mmLB3_LB_MEMORY_SIZE_STATUS 0x0c1c
++#define mmLB3_LB_MEMORY_SIZE_STATUS_BASE_IDX 2
++#define mmLB3_LB_DESKTOP_HEIGHT 0x0c1d
++#define mmLB3_LB_DESKTOP_HEIGHT_BASE_IDX 2
++#define mmLB3_LB_VLINE_START_END 0x0c1e
++#define mmLB3_LB_VLINE_START_END_BASE_IDX 2
++#define mmLB3_LB_VLINE2_START_END 0x0c1f
++#define mmLB3_LB_VLINE2_START_END_BASE_IDX 2
++#define mmLB3_LB_V_COUNTER 0x0c20
++#define mmLB3_LB_V_COUNTER_BASE_IDX 2
++#define mmLB3_LB_SNAPSHOT_V_COUNTER 0x0c21
++#define mmLB3_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2
++#define mmLB3_LB_INTERRUPT_MASK 0x0c22
++#define mmLB3_LB_INTERRUPT_MASK_BASE_IDX 2
++#define mmLB3_LB_VLINE_STATUS 0x0c23
++#define mmLB3_LB_VLINE_STATUS_BASE_IDX 2
++#define mmLB3_LB_VLINE2_STATUS 0x0c24
++#define mmLB3_LB_VLINE2_STATUS_BASE_IDX 2
++#define mmLB3_LB_VBLANK_STATUS 0x0c25
++#define mmLB3_LB_VBLANK_STATUS_BASE_IDX 2
++#define mmLB3_LB_SYNC_RESET_SEL 0x0c26
++#define mmLB3_LB_SYNC_RESET_SEL_BASE_IDX 2
++#define mmLB3_LB_BLACK_KEYER_R_CR 0x0c27
++#define mmLB3_LB_BLACK_KEYER_R_CR_BASE_IDX 2
++#define mmLB3_LB_BLACK_KEYER_G_Y 0x0c28
++#define mmLB3_LB_BLACK_KEYER_G_Y_BASE_IDX 2
++#define mmLB3_LB_BLACK_KEYER_B_CB 0x0c29
++#define mmLB3_LB_BLACK_KEYER_B_CB_BASE_IDX 2
++#define mmLB3_LB_KEYER_COLOR_CTRL 0x0c2a
++#define mmLB3_LB_KEYER_COLOR_CTRL_BASE_IDX 2
++#define mmLB3_LB_KEYER_COLOR_R_CR 0x0c2b
++#define mmLB3_LB_KEYER_COLOR_R_CR_BASE_IDX 2
++#define mmLB3_LB_KEYER_COLOR_G_Y 0x0c2c
++#define mmLB3_LB_KEYER_COLOR_G_Y_BASE_IDX 2
++#define mmLB3_LB_KEYER_COLOR_B_CB 0x0c2d
++#define mmLB3_LB_KEYER_COLOR_B_CB_BASE_IDX 2
++#define mmLB3_LB_KEYER_COLOR_REP_R_CR 0x0c2e
++#define mmLB3_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2
++#define mmLB3_LB_KEYER_COLOR_REP_G_Y 0x0c2f
++#define mmLB3_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2
++#define mmLB3_LB_KEYER_COLOR_REP_B_CB 0x0c30
++#define mmLB3_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2
++#define mmLB3_LB_BUFFER_LEVEL_STATUS 0x0c31
++#define mmLB3_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2
++#define mmLB3_LB_BUFFER_URGENCY_CTRL 0x0c32
++#define mmLB3_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2
++#define mmLB3_LB_BUFFER_URGENCY_STATUS 0x0c33
++#define mmLB3_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2
++#define mmLB3_LB_BUFFER_STATUS 0x0c34
++#define mmLB3_LB_BUFFER_STATUS_BASE_IDX 2
++#define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0x0c35
++#define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2
++#define mmLB3_MVP_AFR_FLIP_MODE 0x0c36
++#define mmLB3_MVP_AFR_FLIP_MODE_BASE_IDX 2
++#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0x0c37
++#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2
++#define mmLB3_MVP_FLIP_LINE_NUM_INSERT 0x0c38
++#define mmLB3_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2
++#define mmLB3_DC_MVP_LB_CONTROL 0x0c39
++#define mmLB3_DC_MVP_LB_CONTROL_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dcfe3_dispdec
++// base address: 0x1800
++#define mmDCFE3_DCFE_CLOCK_CONTROL 0x0c5a
++#define mmDCFE3_DCFE_CLOCK_CONTROL_BASE_IDX 2
++#define mmDCFE3_DCFE_SOFT_RESET 0x0c5b
++#define mmDCFE3_DCFE_SOFT_RESET_BASE_IDX 2
++#define mmDCFE3_DCFE_MEM_PWR_CTRL 0x0c5d
++#define mmDCFE3_DCFE_MEM_PWR_CTRL_BASE_IDX 2
++#define mmDCFE3_DCFE_MEM_PWR_CTRL2 0x0c5e
++#define mmDCFE3_DCFE_MEM_PWR_CTRL2_BASE_IDX 2
++#define mmDCFE3_DCFE_MEM_PWR_STATUS 0x0c5f
++#define mmDCFE3_DCFE_MEM_PWR_STATUS_BASE_IDX 2
++#define mmDCFE3_DCFE_MISC 0x0c60
++#define mmDCFE3_DCFE_MISC_BASE_IDX 2
++#define mmDCFE3_DCFE_FLUSH 0x0c61
++#define mmDCFE3_DCFE_FLUSH_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dc_perfmon6_dispdec
++// base address: 0x3138
++#define mmDC_PERFMON6_PERFCOUNTER_CNTL 0x0c6e
++#define mmDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX 2
++#define mmDC_PERFMON6_PERFCOUNTER_CNTL2 0x0c6f
++#define mmDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX 2
++#define mmDC_PERFMON6_PERFCOUNTER_STATE 0x0c70
++#define mmDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX 2
++#define mmDC_PERFMON6_PERFMON_CNTL 0x0c71
++#define mmDC_PERFMON6_PERFMON_CNTL_BASE_IDX 2
++#define mmDC_PERFMON6_PERFMON_CNTL2 0x0c72
++#define mmDC_PERFMON6_PERFMON_CNTL2_BASE_IDX 2
++#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x0c73
++#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
++#define mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x0c74
++#define mmDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX 2
++#define mmDC_PERFMON6_PERFMON_HI 0x0c75
++#define mmDC_PERFMON6_PERFMON_HI_BASE_IDX 2
++#define mmDC_PERFMON6_PERFMON_LOW 0x0c76
++#define mmDC_PERFMON6_PERFMON_LOW_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dmif_pg3_dispdec
++// base address: 0x1800
++#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 0x0c7a
++#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
++#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 0x0c7b
++#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
++#define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 0x0c7c
++#define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2
++#define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL 0x0c7d
++#define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2
++#define mmDMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL 0x0c7e
++#define mmDMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2
++#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL 0x0c7f
++#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2
++#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL2 0x0c80
++#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2
++#define mmDMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL 0x0c81
++#define mmDMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2
++#define mmDMIF_PG3_DPG_REPEATER_PROGRAM 0x0c82
++#define mmDMIF_PG3_DPG_REPEATER_PROGRAM_BASE_IDX 2
++#define mmDMIF_PG3_DPG_CHK_PRE_PROC_CNTL 0x0c86
++#define mmDMIF_PG3_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2
++#define mmDMIF_PG3_DPG_DVMM_STATUS 0x0c87
++#define mmDMIF_PG3_DPG_DVMM_STATUS_BASE_IDX 2
++
++
++// addressBlock: dce_dc_scl3_dispdec
++// base address: 0x1800
++#define mmSCL3_SCL_COEF_RAM_SELECT 0x0c9a
++#define mmSCL3_SCL_COEF_RAM_SELECT_BASE_IDX 2
++#define mmSCL3_SCL_COEF_RAM_TAP_DATA 0x0c9b
++#define mmSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
++#define mmSCL3_SCL_MODE 0x0c9c
++#define mmSCL3_SCL_MODE_BASE_IDX 2
++#define mmSCL3_SCL_TAP_CONTROL 0x0c9d
++#define mmSCL3_SCL_TAP_CONTROL_BASE_IDX 2
++#define mmSCL3_SCL_CONTROL 0x0c9e
++#define mmSCL3_SCL_CONTROL_BASE_IDX 2
++#define mmSCL3_SCL_BYPASS_CONTROL 0x0c9f
++#define mmSCL3_SCL_BYPASS_CONTROL_BASE_IDX 2
++#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x0ca0
++#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
++#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL 0x0ca1
++#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2
++#define mmSCL3_SCL_HORZ_FILTER_CONTROL 0x0ca2
++#define mmSCL3_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2
++#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x0ca3
++#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
++#define mmSCL3_SCL_HORZ_FILTER_INIT 0x0ca4
++#define mmSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2
++#define mmSCL3_SCL_VERT_FILTER_CONTROL 0x0ca5
++#define mmSCL3_SCL_VERT_FILTER_CONTROL_BASE_IDX 2
++#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x0ca6
++#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
++#define mmSCL3_SCL_VERT_FILTER_INIT 0x0ca7
++#define mmSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2
++#define mmSCL3_SCL_VERT_FILTER_INIT_BOT 0x0ca8
++#define mmSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
++#define mmSCL3_SCL_ROUND_OFFSET 0x0ca9
++#define mmSCL3_SCL_ROUND_OFFSET_BASE_IDX 2
++#define mmSCL3_SCL_UPDATE 0x0caa
++#define mmSCL3_SCL_UPDATE_BASE_IDX 2
++#define mmSCL3_SCL_F_SHARP_CONTROL 0x0cab
++#define mmSCL3_SCL_F_SHARP_CONTROL_BASE_IDX 2
++#define mmSCL3_SCL_ALU_CONTROL 0x0cac
++#define mmSCL3_SCL_ALU_CONTROL_BASE_IDX 2
++#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0x0cad
++#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
++#define mmSCL3_VIEWPORT_START_SECONDARY 0x0cae
++#define mmSCL3_VIEWPORT_START_SECONDARY_BASE_IDX 2
++#define mmSCL3_VIEWPORT_START 0x0caf
++#define mmSCL3_VIEWPORT_START_BASE_IDX 2
++#define mmSCL3_VIEWPORT_SIZE 0x0cb0
++#define mmSCL3_VIEWPORT_SIZE_BASE_IDX 2
++#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT 0x0cb1
++#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
++#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM 0x0cb2
++#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
++#define mmSCL3_SCL_MODE_CHANGE_DET1 0x0cb3
++#define mmSCL3_SCL_MODE_CHANGE_DET1_BASE_IDX 2
++#define mmSCL3_SCL_MODE_CHANGE_DET2 0x0cb4
++#define mmSCL3_SCL_MODE_CHANGE_DET2_BASE_IDX 2
++#define mmSCL3_SCL_MODE_CHANGE_DET3 0x0cb5
++#define mmSCL3_SCL_MODE_CHANGE_DET3_BASE_IDX 2
++#define mmSCL3_SCL_MODE_CHANGE_MASK 0x0cb6
++#define mmSCL3_SCL_MODE_CHANGE_MASK_BASE_IDX 2
++
++
++// addressBlock: dce_dc_blnd3_dispdec
++// base address: 0x1800
++#define mmBLND3_BLND_CONTROL 0x0cc7
++#define mmBLND3_BLND_CONTROL_BASE_IDX 2
++#define mmBLND3_BLND_SM_CONTROL2 0x0cc8
++#define mmBLND3_BLND_SM_CONTROL2_BASE_IDX 2
++#define mmBLND3_BLND_CONTROL2 0x0cc9
++#define mmBLND3_BLND_CONTROL2_BASE_IDX 2
++#define mmBLND3_BLND_UPDATE 0x0cca
++#define mmBLND3_BLND_UPDATE_BASE_IDX 2
++#define mmBLND3_BLND_UNDERFLOW_INTERRUPT 0x0ccb
++#define mmBLND3_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2
++#define mmBLND3_BLND_V_UPDATE_LOCK 0x0ccc
++#define mmBLND3_BLND_V_UPDATE_LOCK_BASE_IDX 2
++#define mmBLND3_BLND_REG_UPDATE_STATUS 0x0ccd
++#define mmBLND3_BLND_REG_UPDATE_STATUS_BASE_IDX 2
++
++
++// addressBlock: dce_dc_crtc3_dispdec
++// base address: 0x1800
++#define mmCRTC3_CRTC_H_BLANK_EARLY_NUM 0x0cd2
++#define mmCRTC3_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2
++#define mmCRTC3_CRTC_H_TOTAL 0x0cd3
++#define mmCRTC3_CRTC_H_TOTAL_BASE_IDX 2
++#define mmCRTC3_CRTC_H_BLANK_START_END 0x0cd4
++#define mmCRTC3_CRTC_H_BLANK_START_END_BASE_IDX 2
++#define mmCRTC3_CRTC_H_SYNC_A 0x0cd5
++#define mmCRTC3_CRTC_H_SYNC_A_BASE_IDX 2
++#define mmCRTC3_CRTC_H_SYNC_A_CNTL 0x0cd6
++#define mmCRTC3_CRTC_H_SYNC_A_CNTL_BASE_IDX 2
++#define mmCRTC3_CRTC_H_SYNC_B 0x0cd7
++#define mmCRTC3_CRTC_H_SYNC_B_BASE_IDX 2
++#define mmCRTC3_CRTC_H_SYNC_B_CNTL 0x0cd8
++#define mmCRTC3_CRTC_H_SYNC_B_CNTL_BASE_IDX 2
++#define mmCRTC3_CRTC_VBI_END 0x0cd9
++#define mmCRTC3_CRTC_VBI_END_BASE_IDX 2
++#define mmCRTC3_CRTC_V_TOTAL 0x0cda
++#define mmCRTC3_CRTC_V_TOTAL_BASE_IDX 2
++#define mmCRTC3_CRTC_V_TOTAL_MIN 0x0cdb
++#define mmCRTC3_CRTC_V_TOTAL_MIN_BASE_IDX 2
++#define mmCRTC3_CRTC_V_TOTAL_MAX 0x0cdc
++#define mmCRTC3_CRTC_V_TOTAL_MAX_BASE_IDX 2
++#define mmCRTC3_CRTC_V_TOTAL_CONTROL 0x0cdd
++#define mmCRTC3_CRTC_V_TOTAL_CONTROL_BASE_IDX 2
++#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS 0x0cde
++#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2
++#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS 0x0cdf
++#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2
++#define mmCRTC3_CRTC_V_BLANK_START_END 0x0ce0
++#define mmCRTC3_CRTC_V_BLANK_START_END_BASE_IDX 2
++#define mmCRTC3_CRTC_V_SYNC_A 0x0ce1
++#define mmCRTC3_CRTC_V_SYNC_A_BASE_IDX 2
++#define mmCRTC3_CRTC_V_SYNC_A_CNTL 0x0ce2
++#define mmCRTC3_CRTC_V_SYNC_A_CNTL_BASE_IDX 2
++#define mmCRTC3_CRTC_V_SYNC_B 0x0ce3
++#define mmCRTC3_CRTC_V_SYNC_B_BASE_IDX 2
++#define mmCRTC3_CRTC_V_SYNC_B_CNTL 0x0ce4
++#define mmCRTC3_CRTC_V_SYNC_B_CNTL_BASE_IDX 2
++#define mmCRTC3_CRTC_DTMTEST_CNTL 0x0ce5
++#define mmCRTC3_CRTC_DTMTEST_CNTL_BASE_IDX 2
++#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION 0x0ce6
++#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2
++#define mmCRTC3_CRTC_TRIGA_CNTL 0x0ce7
++#define mmCRTC3_CRTC_TRIGA_CNTL_BASE_IDX 2
++#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG 0x0ce8
++#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2
++#define mmCRTC3_CRTC_TRIGB_CNTL 0x0ce9
++#define mmCRTC3_CRTC_TRIGB_CNTL_BASE_IDX 2
++#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG 0x0cea
++#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2
++#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL 0x0ceb
++#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
++#define mmCRTC3_CRTC_FLOW_CONTROL 0x0cec
++#define mmCRTC3_CRTC_FLOW_CONTROL_BASE_IDX 2
++#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE 0x0ced
++#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
++#define mmCRTC3_CRTC_AVSYNC_COUNTER 0x0cee
++#define mmCRTC3_CRTC_AVSYNC_COUNTER_BASE_IDX 2
++#define mmCRTC3_CRTC_CONTROL 0x0cef
++#define mmCRTC3_CRTC_CONTROL_BASE_IDX 2
++#define mmCRTC3_CRTC_BLANK_CONTROL 0x0cf0
++#define mmCRTC3_CRTC_BLANK_CONTROL_BASE_IDX 2
++#define mmCRTC3_CRTC_INTERLACE_CONTROL 0x0cf1
++#define mmCRTC3_CRTC_INTERLACE_CONTROL_BASE_IDX 2
++#define mmCRTC3_CRTC_INTERLACE_STATUS 0x0cf2
++#define mmCRTC3_CRTC_INTERLACE_STATUS_BASE_IDX 2
++#define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL 0x0cf3
++#define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2
++#define mmCRTC3_CRTC_PIXEL_DATA_READBACK0 0x0cf4
++#define mmCRTC3_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2
++#define mmCRTC3_CRTC_PIXEL_DATA_READBACK1 0x0cf5
++#define mmCRTC3_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2
++#define mmCRTC3_CRTC_STATUS 0x0cf6
++#define mmCRTC3_CRTC_STATUS_BASE_IDX 2
++#define mmCRTC3_CRTC_STATUS_POSITION 0x0cf7
++#define mmCRTC3_CRTC_STATUS_POSITION_BASE_IDX 2
++#define mmCRTC3_CRTC_NOM_VERT_POSITION 0x0cf8
++#define mmCRTC3_CRTC_NOM_VERT_POSITION_BASE_IDX 2
++#define mmCRTC3_CRTC_STATUS_FRAME_COUNT 0x0cf9
++#define mmCRTC3_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2
++#define mmCRTC3_CRTC_STATUS_VF_COUNT 0x0cfa
++#define mmCRTC3_CRTC_STATUS_VF_COUNT_BASE_IDX 2
++#define mmCRTC3_CRTC_STATUS_HV_COUNT 0x0cfb
++#define mmCRTC3_CRTC_STATUS_HV_COUNT_BASE_IDX 2
++#define mmCRTC3_CRTC_COUNT_CONTROL 0x0cfc
++#define mmCRTC3_CRTC_COUNT_CONTROL_BASE_IDX 2
++#define mmCRTC3_CRTC_COUNT_RESET 0x0cfd
++#define mmCRTC3_CRTC_COUNT_RESET_BASE_IDX 2
++#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x0cfe
++#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
++#define mmCRTC3_CRTC_VERT_SYNC_CONTROL 0x0cff
++#define mmCRTC3_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2
++#define mmCRTC3_CRTC_STEREO_STATUS 0x0d00
++#define mmCRTC3_CRTC_STEREO_STATUS_BASE_IDX 2
++#define mmCRTC3_CRTC_STEREO_CONTROL 0x0d01
++#define mmCRTC3_CRTC_STEREO_CONTROL_BASE_IDX 2
++#define mmCRTC3_CRTC_SNAPSHOT_STATUS 0x0d02
++#define mmCRTC3_CRTC_SNAPSHOT_STATUS_BASE_IDX 2
++#define mmCRTC3_CRTC_SNAPSHOT_CONTROL 0x0d03
++#define mmCRTC3_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2
++#define mmCRTC3_CRTC_SNAPSHOT_POSITION 0x0d04
++#define mmCRTC3_CRTC_SNAPSHOT_POSITION_BASE_IDX 2
++#define mmCRTC3_CRTC_SNAPSHOT_FRAME 0x0d05
++#define mmCRTC3_CRTC_SNAPSHOT_FRAME_BASE_IDX 2
++#define mmCRTC3_CRTC_START_LINE_CONTROL 0x0d06
++#define mmCRTC3_CRTC_START_LINE_CONTROL_BASE_IDX 2
++#define mmCRTC3_CRTC_INTERRUPT_CONTROL 0x0d07
++#define mmCRTC3_CRTC_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmCRTC3_CRTC_UPDATE_LOCK 0x0d08
++#define mmCRTC3_CRTC_UPDATE_LOCK_BASE_IDX 2
++#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL 0x0d09
++#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
++#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x0d0a
++#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2
++#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL 0x0d0b
++#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2
++#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS 0x0d0c
++#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2
++#define mmCRTC3_CRTC_TEST_PATTERN_COLOR 0x0d0d
++#define mmCRTC3_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2
++#define mmCRTC3_CRTC_MASTER_UPDATE_LOCK 0x0d0e
++#define mmCRTC3_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2
++#define mmCRTC3_CRTC_MASTER_UPDATE_MODE 0x0d0f
++#define mmCRTC3_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2
++#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT 0x0d10
++#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2
++#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x0d11
++#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2
++#define mmCRTC3_CRTC_MVP_STATUS 0x0d12
++#define mmCRTC3_CRTC_MVP_STATUS_BASE_IDX 2
++#define mmCRTC3_CRTC_MASTER_EN 0x0d13
++#define mmCRTC3_CRTC_MASTER_EN_BASE_IDX 2
++#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT 0x0d14
++#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2
++#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS 0x0d15
++#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2
++#define mmCRTC3_CRTC_OVERSCAN_COLOR 0x0d17
++#define mmCRTC3_CRTC_OVERSCAN_COLOR_BASE_IDX 2
++#define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT 0x0d18
++#define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2
++#define mmCRTC3_CRTC_BLANK_DATA_COLOR 0x0d19
++#define mmCRTC3_CRTC_BLANK_DATA_COLOR_BASE_IDX 2
++#define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT 0x0d1a
++#define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2
++#define mmCRTC3_CRTC_BLACK_COLOR 0x0d1b
++#define mmCRTC3_CRTC_BLACK_COLOR_BASE_IDX 2
++#define mmCRTC3_CRTC_BLACK_COLOR_EXT 0x0d1c
++#define mmCRTC3_CRTC_BLACK_COLOR_EXT_BASE_IDX 2
++#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION 0x0d1d
++#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
++#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x0d1e
++#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
++#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION 0x0d1f
++#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
++#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x0d20
++#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
++#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION 0x0d21
++#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
++#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x0d22
++#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
++#define mmCRTC3_CRTC_CRC_CNTL 0x0d23
++#define mmCRTC3_CRTC_CRC_CNTL_BASE_IDX 2
++#define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL 0x0d24
++#define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
++#define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL 0x0d25
++#define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
++#define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL 0x0d26
++#define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
++#define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL 0x0d27
++#define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
++#define mmCRTC3_CRTC_CRC0_DATA_RG 0x0d28
++#define mmCRTC3_CRTC_CRC0_DATA_RG_BASE_IDX 2
++#define mmCRTC3_CRTC_CRC0_DATA_B 0x0d29
++#define mmCRTC3_CRTC_CRC0_DATA_B_BASE_IDX 2
++#define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL 0x0d2a
++#define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
++#define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL 0x0d2b
++#define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
++#define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL 0x0d2c
++#define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
++#define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL 0x0d2d
++#define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
++#define mmCRTC3_CRTC_CRC1_DATA_RG 0x0d2e
++#define mmCRTC3_CRTC_CRC1_DATA_RG_BASE_IDX 2
++#define mmCRTC3_CRTC_CRC1_DATA_B 0x0d2f
++#define mmCRTC3_CRTC_CRC1_DATA_B_BASE_IDX 2
++#define mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL 0x0d30
++#define mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2
++#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x0d31
++#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2
++#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x0d32
++#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2
++#define mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x0d33
++#define mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x0d34
++#define mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x0d35
++#define mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL 0x0d36
++#define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2
++#define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL 0x0d37
++#define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2
++#define mmCRTC3_CRTC_GSL_VSYNC_GAP 0x0d38
++#define mmCRTC3_CRTC_GSL_VSYNC_GAP_BASE_IDX 2
++#define mmCRTC3_CRTC_GSL_WINDOW 0x0d39
++#define mmCRTC3_CRTC_GSL_WINDOW_BASE_IDX 2
++#define mmCRTC3_CRTC_GSL_CONTROL 0x0d3a
++#define mmCRTC3_CRTC_GSL_CONTROL_BASE_IDX 2
++#define mmCRTC3_CRTC_RANGE_TIMING_INT_STATUS 0x0d3d
++#define mmCRTC3_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2
++#define mmCRTC3_CRTC_DRR_CONTROL 0x0d3e
++#define mmCRTC3_CRTC_DRR_CONTROL_BASE_IDX 2
++
++
++// addressBlock: dce_dc_fmt3_dispdec
++// base address: 0x1800
++#define mmFMT3_FMT_CLAMP_COMPONENT_R 0x0d42
++#define mmFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
++#define mmFMT3_FMT_CLAMP_COMPONENT_G 0x0d43
++#define mmFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
++#define mmFMT3_FMT_CLAMP_COMPONENT_B 0x0d44
++#define mmFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
++#define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x0d45
++#define mmFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
++#define mmFMT3_FMT_CONTROL 0x0d46
++#define mmFMT3_FMT_CONTROL_BASE_IDX 2
++#define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x0d47
++#define mmFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
++#define mmFMT3_FMT_DITHER_RAND_R_SEED 0x0d48
++#define mmFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
++#define mmFMT3_FMT_DITHER_RAND_G_SEED 0x0d49
++#define mmFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
++#define mmFMT3_FMT_DITHER_RAND_B_SEED 0x0d4a
++#define mmFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
++#define mmFMT3_FMT_CLAMP_CNTL 0x0d4e
++#define mmFMT3_FMT_CLAMP_CNTL_BASE_IDX 2
++#define mmFMT3_FMT_CRC_CNTL 0x0d4f
++#define mmFMT3_FMT_CRC_CNTL_BASE_IDX 2
++#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK 0x0d50
++#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
++#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x0d51
++#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
++#define mmFMT3_FMT_CRC_SIG_RED_GREEN 0x0d52
++#define mmFMT3_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2
++#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL 0x0d53
++#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2
++#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x0d54
++#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
++#define mmFMT3_FMT_420_HBLANK_EARLY_START 0x0d55
++#define mmFMT3_FMT_420_HBLANK_EARLY_START_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dcp4_dispdec
++// base address: 0x2000
++#define mmDCP4_GRPH_ENABLE 0x0d5a
++#define mmDCP4_GRPH_ENABLE_BASE_IDX 2
++#define mmDCP4_GRPH_CONTROL 0x0d5b
++#define mmDCP4_GRPH_CONTROL_BASE_IDX 2
++#define mmDCP4_GRPH_LUT_10BIT_BYPASS 0x0d5c
++#define mmDCP4_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2
++#define mmDCP4_GRPH_SWAP_CNTL 0x0d5d
++#define mmDCP4_GRPH_SWAP_CNTL_BASE_IDX 2
++#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS 0x0d5e
++#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
++#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS 0x0d5f
++#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
++#define mmDCP4_GRPH_PITCH 0x0d60
++#define mmDCP4_GRPH_PITCH_BASE_IDX 2
++#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0d61
++#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
++#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0d62
++#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
++#define mmDCP4_GRPH_SURFACE_OFFSET_X 0x0d63
++#define mmDCP4_GRPH_SURFACE_OFFSET_X_BASE_IDX 2
++#define mmDCP4_GRPH_SURFACE_OFFSET_Y 0x0d64
++#define mmDCP4_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2
++#define mmDCP4_GRPH_X_START 0x0d65
++#define mmDCP4_GRPH_X_START_BASE_IDX 2
++#define mmDCP4_GRPH_Y_START 0x0d66
++#define mmDCP4_GRPH_Y_START_BASE_IDX 2
++#define mmDCP4_GRPH_X_END 0x0d67
++#define mmDCP4_GRPH_X_END_BASE_IDX 2
++#define mmDCP4_GRPH_Y_END 0x0d68
++#define mmDCP4_GRPH_Y_END_BASE_IDX 2
++#define mmDCP4_INPUT_GAMMA_CONTROL 0x0d69
++#define mmDCP4_INPUT_GAMMA_CONTROL_BASE_IDX 2
++#define mmDCP4_GRPH_UPDATE 0x0d6a
++#define mmDCP4_GRPH_UPDATE_BASE_IDX 2
++#define mmDCP4_GRPH_FLIP_CONTROL 0x0d6b
++#define mmDCP4_GRPH_FLIP_CONTROL_BASE_IDX 2
++#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE 0x0d6c
++#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2
++#define mmDCP4_GRPH_DFQ_CONTROL 0x0d6d
++#define mmDCP4_GRPH_DFQ_CONTROL_BASE_IDX 2
++#define mmDCP4_GRPH_DFQ_STATUS 0x0d6e
++#define mmDCP4_GRPH_DFQ_STATUS_BASE_IDX 2
++#define mmDCP4_GRPH_INTERRUPT_STATUS 0x0d6f
++#define mmDCP4_GRPH_INTERRUPT_STATUS_BASE_IDX 2
++#define mmDCP4_GRPH_INTERRUPT_CONTROL 0x0d70
++#define mmDCP4_GRPH_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0d71
++#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2
++#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS 0x0d72
++#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2
++#define mmDCP4_GRPH_COMPRESS_PITCH 0x0d73
++#define mmDCP4_GRPH_COMPRESS_PITCH_BASE_IDX 2
++#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0d74
++#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2
++#define mmDCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0d75
++#define mmDCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2
++#define mmDCP4_PRESCALE_GRPH_CONTROL 0x0d76
++#define mmDCP4_PRESCALE_GRPH_CONTROL_BASE_IDX 2
++#define mmDCP4_PRESCALE_VALUES_GRPH_R 0x0d77
++#define mmDCP4_PRESCALE_VALUES_GRPH_R_BASE_IDX 2
++#define mmDCP4_PRESCALE_VALUES_GRPH_G 0x0d78
++#define mmDCP4_PRESCALE_VALUES_GRPH_G_BASE_IDX 2
++#define mmDCP4_PRESCALE_VALUES_GRPH_B 0x0d79
++#define mmDCP4_PRESCALE_VALUES_GRPH_B_BASE_IDX 2
++#define mmDCP4_INPUT_CSC_CONTROL 0x0d7a
++#define mmDCP4_INPUT_CSC_CONTROL_BASE_IDX 2
++#define mmDCP4_INPUT_CSC_C11_C12 0x0d7b
++#define mmDCP4_INPUT_CSC_C11_C12_BASE_IDX 2
++#define mmDCP4_INPUT_CSC_C13_C14 0x0d7c
++#define mmDCP4_INPUT_CSC_C13_C14_BASE_IDX 2
++#define mmDCP4_INPUT_CSC_C21_C22 0x0d7d
++#define mmDCP4_INPUT_CSC_C21_C22_BASE_IDX 2
++#define mmDCP4_INPUT_CSC_C23_C24 0x0d7e
++#define mmDCP4_INPUT_CSC_C23_C24_BASE_IDX 2
++#define mmDCP4_INPUT_CSC_C31_C32 0x0d7f
++#define mmDCP4_INPUT_CSC_C31_C32_BASE_IDX 2
++#define mmDCP4_INPUT_CSC_C33_C34 0x0d80
++#define mmDCP4_INPUT_CSC_C33_C34_BASE_IDX 2
++#define mmDCP4_OUTPUT_CSC_CONTROL 0x0d81
++#define mmDCP4_OUTPUT_CSC_CONTROL_BASE_IDX 2
++#define mmDCP4_OUTPUT_CSC_C11_C12 0x0d82
++#define mmDCP4_OUTPUT_CSC_C11_C12_BASE_IDX 2
++#define mmDCP4_OUTPUT_CSC_C13_C14 0x0d83
++#define mmDCP4_OUTPUT_CSC_C13_C14_BASE_IDX 2
++#define mmDCP4_OUTPUT_CSC_C21_C22 0x0d84
++#define mmDCP4_OUTPUT_CSC_C21_C22_BASE_IDX 2
++#define mmDCP4_OUTPUT_CSC_C23_C24 0x0d85
++#define mmDCP4_OUTPUT_CSC_C23_C24_BASE_IDX 2
++#define mmDCP4_OUTPUT_CSC_C31_C32 0x0d86
++#define mmDCP4_OUTPUT_CSC_C31_C32_BASE_IDX 2
++#define mmDCP4_OUTPUT_CSC_C33_C34 0x0d87
++#define mmDCP4_OUTPUT_CSC_C33_C34_BASE_IDX 2
++#define mmDCP4_COMM_MATRIXA_TRANS_C11_C12 0x0d88
++#define mmDCP4_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2
++#define mmDCP4_COMM_MATRIXA_TRANS_C13_C14 0x0d89
++#define mmDCP4_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2
++#define mmDCP4_COMM_MATRIXA_TRANS_C21_C22 0x0d8a
++#define mmDCP4_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2
++#define mmDCP4_COMM_MATRIXA_TRANS_C23_C24 0x0d8b
++#define mmDCP4_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2
++#define mmDCP4_COMM_MATRIXA_TRANS_C31_C32 0x0d8c
++#define mmDCP4_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2
++#define mmDCP4_COMM_MATRIXA_TRANS_C33_C34 0x0d8d
++#define mmDCP4_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2
++#define mmDCP4_COMM_MATRIXB_TRANS_C11_C12 0x0d8e
++#define mmDCP4_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2
++#define mmDCP4_COMM_MATRIXB_TRANS_C13_C14 0x0d8f
++#define mmDCP4_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2
++#define mmDCP4_COMM_MATRIXB_TRANS_C21_C22 0x0d90
++#define mmDCP4_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2
++#define mmDCP4_COMM_MATRIXB_TRANS_C23_C24 0x0d91
++#define mmDCP4_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2
++#define mmDCP4_COMM_MATRIXB_TRANS_C31_C32 0x0d92
++#define mmDCP4_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2
++#define mmDCP4_COMM_MATRIXB_TRANS_C33_C34 0x0d93
++#define mmDCP4_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2
++#define mmDCP4_DENORM_CONTROL 0x0d94
++#define mmDCP4_DENORM_CONTROL_BASE_IDX 2
++#define mmDCP4_OUT_ROUND_CONTROL 0x0d95
++#define mmDCP4_OUT_ROUND_CONTROL_BASE_IDX 2
++#define mmDCP4_OUT_CLAMP_CONTROL_R_CR 0x0d96
++#define mmDCP4_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2
++#define mmDCP4_OUT_CLAMP_CONTROL_G_Y 0x0d97
++#define mmDCP4_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2
++#define mmDCP4_OUT_CLAMP_CONTROL_B_CB 0x0d98
++#define mmDCP4_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2
++#define mmDCP4_KEY_CONTROL 0x0d99
++#define mmDCP4_KEY_CONTROL_BASE_IDX 2
++#define mmDCP4_KEY_RANGE_ALPHA 0x0d9a
++#define mmDCP4_KEY_RANGE_ALPHA_BASE_IDX 2
++#define mmDCP4_KEY_RANGE_RED 0x0d9b
++#define mmDCP4_KEY_RANGE_RED_BASE_IDX 2
++#define mmDCP4_KEY_RANGE_GREEN 0x0d9c
++#define mmDCP4_KEY_RANGE_GREEN_BASE_IDX 2
++#define mmDCP4_KEY_RANGE_BLUE 0x0d9d
++#define mmDCP4_KEY_RANGE_BLUE_BASE_IDX 2
++#define mmDCP4_DEGAMMA_CONTROL 0x0d9e
++#define mmDCP4_DEGAMMA_CONTROL_BASE_IDX 2
++#define mmDCP4_GAMUT_REMAP_CONTROL 0x0d9f
++#define mmDCP4_GAMUT_REMAP_CONTROL_BASE_IDX 2
++#define mmDCP4_GAMUT_REMAP_C11_C12 0x0da0
++#define mmDCP4_GAMUT_REMAP_C11_C12_BASE_IDX 2
++#define mmDCP4_GAMUT_REMAP_C13_C14 0x0da1
++#define mmDCP4_GAMUT_REMAP_C13_C14_BASE_IDX 2
++#define mmDCP4_GAMUT_REMAP_C21_C22 0x0da2
++#define mmDCP4_GAMUT_REMAP_C21_C22_BASE_IDX 2
++#define mmDCP4_GAMUT_REMAP_C23_C24 0x0da3
++#define mmDCP4_GAMUT_REMAP_C23_C24_BASE_IDX 2
++#define mmDCP4_GAMUT_REMAP_C31_C32 0x0da4
++#define mmDCP4_GAMUT_REMAP_C31_C32_BASE_IDX 2
++#define mmDCP4_GAMUT_REMAP_C33_C34 0x0da5
++#define mmDCP4_GAMUT_REMAP_C33_C34_BASE_IDX 2
++#define mmDCP4_DCP_SPATIAL_DITHER_CNTL 0x0da6
++#define mmDCP4_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2
++#define mmDCP4_DCP_RANDOM_SEEDS 0x0da7
++#define mmDCP4_DCP_RANDOM_SEEDS_BASE_IDX 2
++#define mmDCP4_DCP_FP_CONVERTED_FIELD 0x0da8
++#define mmDCP4_DCP_FP_CONVERTED_FIELD_BASE_IDX 2
++#define mmDCP4_CUR_CONTROL 0x0da9
++#define mmDCP4_CUR_CONTROL_BASE_IDX 2
++#define mmDCP4_CUR_SURFACE_ADDRESS 0x0daa
++#define mmDCP4_CUR_SURFACE_ADDRESS_BASE_IDX 2
++#define mmDCP4_CUR_SIZE 0x0dab
++#define mmDCP4_CUR_SIZE_BASE_IDX 2
++#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH 0x0dac
++#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
++#define mmDCP4_CUR_POSITION 0x0dad
++#define mmDCP4_CUR_POSITION_BASE_IDX 2
++#define mmDCP4_CUR_HOT_SPOT 0x0dae
++#define mmDCP4_CUR_HOT_SPOT_BASE_IDX 2
++#define mmDCP4_CUR_COLOR1 0x0daf
++#define mmDCP4_CUR_COLOR1_BASE_IDX 2
++#define mmDCP4_CUR_COLOR2 0x0db0
++#define mmDCP4_CUR_COLOR2_BASE_IDX 2
++#define mmDCP4_CUR_UPDATE 0x0db1
++#define mmDCP4_CUR_UPDATE_BASE_IDX 2
++#define mmDCP4_CUR_REQUEST_FILTER_CNTL 0x0dbb
++#define mmDCP4_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2
++#define mmDCP4_CUR_STEREO_CONTROL 0x0dbc
++#define mmDCP4_CUR_STEREO_CONTROL_BASE_IDX 2
++#define mmDCP4_DC_LUT_RW_MODE 0x0dbe
++#define mmDCP4_DC_LUT_RW_MODE_BASE_IDX 2
++#define mmDCP4_DC_LUT_RW_INDEX 0x0dbf
++#define mmDCP4_DC_LUT_RW_INDEX_BASE_IDX 2
++#define mmDCP4_DC_LUT_SEQ_COLOR 0x0dc0
++#define mmDCP4_DC_LUT_SEQ_COLOR_BASE_IDX 2
++#define mmDCP4_DC_LUT_PWL_DATA 0x0dc1
++#define mmDCP4_DC_LUT_PWL_DATA_BASE_IDX 2
++#define mmDCP4_DC_LUT_30_COLOR 0x0dc2
++#define mmDCP4_DC_LUT_30_COLOR_BASE_IDX 2
++#define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE 0x0dc3
++#define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2
++#define mmDCP4_DC_LUT_WRITE_EN_MASK 0x0dc4
++#define mmDCP4_DC_LUT_WRITE_EN_MASK_BASE_IDX 2
++#define mmDCP4_DC_LUT_AUTOFILL 0x0dc5
++#define mmDCP4_DC_LUT_AUTOFILL_BASE_IDX 2
++#define mmDCP4_DC_LUT_CONTROL 0x0dc6
++#define mmDCP4_DC_LUT_CONTROL_BASE_IDX 2
++#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE 0x0dc7
++#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2
++#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN 0x0dc8
++#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2
++#define mmDCP4_DC_LUT_BLACK_OFFSET_RED 0x0dc9
++#define mmDCP4_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2
++#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE 0x0dca
++#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2
++#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN 0x0dcb
++#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2
++#define mmDCP4_DC_LUT_WHITE_OFFSET_RED 0x0dcc
++#define mmDCP4_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2
++#define mmDCP4_DCP_CRC_CONTROL 0x0dcd
++#define mmDCP4_DCP_CRC_CONTROL_BASE_IDX 2
++#define mmDCP4_DCP_CRC_MASK 0x0dce
++#define mmDCP4_DCP_CRC_MASK_BASE_IDX 2
++#define mmDCP4_DCP_CRC_CURRENT 0x0dcf
++#define mmDCP4_DCP_CRC_CURRENT_BASE_IDX 2
++#define mmDCP4_DVMM_PTE_CONTROL 0x0dd0
++#define mmDCP4_DVMM_PTE_CONTROL_BASE_IDX 2
++#define mmDCP4_DCP_CRC_LAST 0x0dd1
++#define mmDCP4_DCP_CRC_LAST_BASE_IDX 2
++#define mmDCP4_DVMM_PTE_ARB_CONTROL 0x0dd2
++#define mmDCP4_DVMM_PTE_ARB_CONTROL_BASE_IDX 2
++#define mmDCP4_GRPH_FLIP_RATE_CNTL 0x0dd4
++#define mmDCP4_GRPH_FLIP_RATE_CNTL_BASE_IDX 2
++#define mmDCP4_DCP_GSL_CONTROL 0x0dd5
++#define mmDCP4_DCP_GSL_CONTROL_BASE_IDX 2
++#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x0dd6
++#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2
++#define mmDCP4_GRPH_STEREOSYNC_FLIP 0x0ddc
++#define mmDCP4_GRPH_STEREOSYNC_FLIP_BASE_IDX 2
++#define mmDCP4_HW_ROTATION 0x0dde
++#define mmDCP4_HW_ROTATION_BASE_IDX 2
++#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x0ddf
++#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2
++#define mmDCP4_REGAMMA_CONTROL 0x0de0
++#define mmDCP4_REGAMMA_CONTROL_BASE_IDX 2
++#define mmDCP4_REGAMMA_LUT_INDEX 0x0de1
++#define mmDCP4_REGAMMA_LUT_INDEX_BASE_IDX 2
++#define mmDCP4_REGAMMA_LUT_DATA 0x0de2
++#define mmDCP4_REGAMMA_LUT_DATA_BASE_IDX 2
++#define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK 0x0de3
++#define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2
++#define mmDCP4_REGAMMA_CNTLA_START_CNTL 0x0de4
++#define mmDCP4_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2
++#define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL 0x0de5
++#define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2
++#define mmDCP4_REGAMMA_CNTLA_END_CNTL1 0x0de6
++#define mmDCP4_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2
++#define mmDCP4_REGAMMA_CNTLA_END_CNTL2 0x0de7
++#define mmDCP4_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2
++#define mmDCP4_REGAMMA_CNTLA_REGION_0_1 0x0de8
++#define mmDCP4_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2
++#define mmDCP4_REGAMMA_CNTLA_REGION_2_3 0x0de9
++#define mmDCP4_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2
++#define mmDCP4_REGAMMA_CNTLA_REGION_4_5 0x0dea
++#define mmDCP4_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2
++#define mmDCP4_REGAMMA_CNTLA_REGION_6_7 0x0deb
++#define mmDCP4_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2
++#define mmDCP4_REGAMMA_CNTLA_REGION_8_9 0x0dec
++#define mmDCP4_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2
++#define mmDCP4_REGAMMA_CNTLA_REGION_10_11 0x0ded
++#define mmDCP4_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2
++#define mmDCP4_REGAMMA_CNTLA_REGION_12_13 0x0dee
++#define mmDCP4_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2
++#define mmDCP4_REGAMMA_CNTLA_REGION_14_15 0x0def
++#define mmDCP4_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2
++#define mmDCP4_REGAMMA_CNTLB_START_CNTL 0x0df0
++#define mmDCP4_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2
++#define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL 0x0df1
++#define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2
++#define mmDCP4_REGAMMA_CNTLB_END_CNTL1 0x0df2
++#define mmDCP4_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2
++#define mmDCP4_REGAMMA_CNTLB_END_CNTL2 0x0df3
++#define mmDCP4_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2
++#define mmDCP4_REGAMMA_CNTLB_REGION_0_1 0x0df4
++#define mmDCP4_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2
++#define mmDCP4_REGAMMA_CNTLB_REGION_2_3 0x0df5
++#define mmDCP4_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2
++#define mmDCP4_REGAMMA_CNTLB_REGION_4_5 0x0df6
++#define mmDCP4_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2
++#define mmDCP4_REGAMMA_CNTLB_REGION_6_7 0x0df7
++#define mmDCP4_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2
++#define mmDCP4_REGAMMA_CNTLB_REGION_8_9 0x0df8
++#define mmDCP4_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2
++#define mmDCP4_REGAMMA_CNTLB_REGION_10_11 0x0df9
++#define mmDCP4_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2
++#define mmDCP4_REGAMMA_CNTLB_REGION_12_13 0x0dfa
++#define mmDCP4_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2
++#define mmDCP4_REGAMMA_CNTLB_REGION_14_15 0x0dfb
++#define mmDCP4_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2
++#define mmDCP4_ALPHA_CONTROL 0x0dfc
++#define mmDCP4_ALPHA_CONTROL_BASE_IDX 2
++#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x0dfd
++#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2
++#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x0dfe
++#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
++#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x0dff
++#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2
++#define mmDCP4_GRPH_XDMA_FLIP_TIMEOUT 0x0e00
++#define mmDCP4_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2
++#define mmDCP4_GRPH_XDMA_FLIP_AVG_DELAY 0x0e01
++#define mmDCP4_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2
++#define mmDCP4_GRPH_SURFACE_COUNTER_CONTROL 0x0e02
++#define mmDCP4_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2
++#define mmDCP4_GRPH_SURFACE_COUNTER_OUTPUT 0x0e03
++#define mmDCP4_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2
++
++
++// addressBlock: dce_dc_lb4_dispdec
++// base address: 0x2000
++#define mmLB4_LB_DATA_FORMAT 0x0e1a
++#define mmLB4_LB_DATA_FORMAT_BASE_IDX 2
++#define mmLB4_LB_MEMORY_CTRL 0x0e1b
++#define mmLB4_LB_MEMORY_CTRL_BASE_IDX 2
++#define mmLB4_LB_MEMORY_SIZE_STATUS 0x0e1c
++#define mmLB4_LB_MEMORY_SIZE_STATUS_BASE_IDX 2
++#define mmLB4_LB_DESKTOP_HEIGHT 0x0e1d
++#define mmLB4_LB_DESKTOP_HEIGHT_BASE_IDX 2
++#define mmLB4_LB_VLINE_START_END 0x0e1e
++#define mmLB4_LB_VLINE_START_END_BASE_IDX 2
++#define mmLB4_LB_VLINE2_START_END 0x0e1f
++#define mmLB4_LB_VLINE2_START_END_BASE_IDX 2
++#define mmLB4_LB_V_COUNTER 0x0e20
++#define mmLB4_LB_V_COUNTER_BASE_IDX 2
++#define mmLB4_LB_SNAPSHOT_V_COUNTER 0x0e21
++#define mmLB4_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2
++#define mmLB4_LB_INTERRUPT_MASK 0x0e22
++#define mmLB4_LB_INTERRUPT_MASK_BASE_IDX 2
++#define mmLB4_LB_VLINE_STATUS 0x0e23
++#define mmLB4_LB_VLINE_STATUS_BASE_IDX 2
++#define mmLB4_LB_VLINE2_STATUS 0x0e24
++#define mmLB4_LB_VLINE2_STATUS_BASE_IDX 2
++#define mmLB4_LB_VBLANK_STATUS 0x0e25
++#define mmLB4_LB_VBLANK_STATUS_BASE_IDX 2
++#define mmLB4_LB_SYNC_RESET_SEL 0x0e26
++#define mmLB4_LB_SYNC_RESET_SEL_BASE_IDX 2
++#define mmLB4_LB_BLACK_KEYER_R_CR 0x0e27
++#define mmLB4_LB_BLACK_KEYER_R_CR_BASE_IDX 2
++#define mmLB4_LB_BLACK_KEYER_G_Y 0x0e28
++#define mmLB4_LB_BLACK_KEYER_G_Y_BASE_IDX 2
++#define mmLB4_LB_BLACK_KEYER_B_CB 0x0e29
++#define mmLB4_LB_BLACK_KEYER_B_CB_BASE_IDX 2
++#define mmLB4_LB_KEYER_COLOR_CTRL 0x0e2a
++#define mmLB4_LB_KEYER_COLOR_CTRL_BASE_IDX 2
++#define mmLB4_LB_KEYER_COLOR_R_CR 0x0e2b
++#define mmLB4_LB_KEYER_COLOR_R_CR_BASE_IDX 2
++#define mmLB4_LB_KEYER_COLOR_G_Y 0x0e2c
++#define mmLB4_LB_KEYER_COLOR_G_Y_BASE_IDX 2
++#define mmLB4_LB_KEYER_COLOR_B_CB 0x0e2d
++#define mmLB4_LB_KEYER_COLOR_B_CB_BASE_IDX 2
++#define mmLB4_LB_KEYER_COLOR_REP_R_CR 0x0e2e
++#define mmLB4_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2
++#define mmLB4_LB_KEYER_COLOR_REP_G_Y 0x0e2f
++#define mmLB4_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2
++#define mmLB4_LB_KEYER_COLOR_REP_B_CB 0x0e30
++#define mmLB4_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2
++#define mmLB4_LB_BUFFER_LEVEL_STATUS 0x0e31
++#define mmLB4_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2
++#define mmLB4_LB_BUFFER_URGENCY_CTRL 0x0e32
++#define mmLB4_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2
++#define mmLB4_LB_BUFFER_URGENCY_STATUS 0x0e33
++#define mmLB4_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2
++#define mmLB4_LB_BUFFER_STATUS 0x0e34
++#define mmLB4_LB_BUFFER_STATUS_BASE_IDX 2
++#define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0x0e35
++#define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2
++#define mmLB4_MVP_AFR_FLIP_MODE 0x0e36
++#define mmLB4_MVP_AFR_FLIP_MODE_BASE_IDX 2
++#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0x0e37
++#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2
++#define mmLB4_MVP_FLIP_LINE_NUM_INSERT 0x0e38
++#define mmLB4_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2
++#define mmLB4_DC_MVP_LB_CONTROL 0x0e39
++#define mmLB4_DC_MVP_LB_CONTROL_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dcfe4_dispdec
++// base address: 0x2000
++#define mmDCFE4_DCFE_CLOCK_CONTROL 0x0e5a
++#define mmDCFE4_DCFE_CLOCK_CONTROL_BASE_IDX 2
++#define mmDCFE4_DCFE_SOFT_RESET 0x0e5b
++#define mmDCFE4_DCFE_SOFT_RESET_BASE_IDX 2
++#define mmDCFE4_DCFE_MEM_PWR_CTRL 0x0e5d
++#define mmDCFE4_DCFE_MEM_PWR_CTRL_BASE_IDX 2
++#define mmDCFE4_DCFE_MEM_PWR_CTRL2 0x0e5e
++#define mmDCFE4_DCFE_MEM_PWR_CTRL2_BASE_IDX 2
++#define mmDCFE4_DCFE_MEM_PWR_STATUS 0x0e5f
++#define mmDCFE4_DCFE_MEM_PWR_STATUS_BASE_IDX 2
++#define mmDCFE4_DCFE_MISC 0x0e60
++#define mmDCFE4_DCFE_MISC_BASE_IDX 2
++#define mmDCFE4_DCFE_FLUSH 0x0e61
++#define mmDCFE4_DCFE_FLUSH_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dc_perfmon7_dispdec
++// base address: 0x3938
++#define mmDC_PERFMON7_PERFCOUNTER_CNTL 0x0e6e
++#define mmDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX 2
++#define mmDC_PERFMON7_PERFCOUNTER_CNTL2 0x0e6f
++#define mmDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX 2
++#define mmDC_PERFMON7_PERFCOUNTER_STATE 0x0e70
++#define mmDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX 2
++#define mmDC_PERFMON7_PERFMON_CNTL 0x0e71
++#define mmDC_PERFMON7_PERFMON_CNTL_BASE_IDX 2
++#define mmDC_PERFMON7_PERFMON_CNTL2 0x0e72
++#define mmDC_PERFMON7_PERFMON_CNTL2_BASE_IDX 2
++#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x0e73
++#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
++#define mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x0e74
++#define mmDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX 2
++#define mmDC_PERFMON7_PERFMON_HI 0x0e75
++#define mmDC_PERFMON7_PERFMON_HI_BASE_IDX 2
++#define mmDC_PERFMON7_PERFMON_LOW 0x0e76
++#define mmDC_PERFMON7_PERFMON_LOW_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dmif_pg4_dispdec
++// base address: 0x2000
++#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 0x0e7a
++#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
++#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 0x0e7b
++#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
++#define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 0x0e7c
++#define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2
++#define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL 0x0e7d
++#define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2
++#define mmDMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL 0x0e7e
++#define mmDMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2
++#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL 0x0e7f
++#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2
++#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL2 0x0e80
++#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2
++#define mmDMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL 0x0e81
++#define mmDMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2
++#define mmDMIF_PG4_DPG_REPEATER_PROGRAM 0x0e82
++#define mmDMIF_PG4_DPG_REPEATER_PROGRAM_BASE_IDX 2
++#define mmDMIF_PG4_DPG_CHK_PRE_PROC_CNTL 0x0e86
++#define mmDMIF_PG4_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2
++#define mmDMIF_PG4_DPG_DVMM_STATUS 0x0e87
++#define mmDMIF_PG4_DPG_DVMM_STATUS_BASE_IDX 2
++
++
++// addressBlock: dce_dc_scl4_dispdec
++// base address: 0x2000
++#define mmSCL4_SCL_COEF_RAM_SELECT 0x0e9a
++#define mmSCL4_SCL_COEF_RAM_SELECT_BASE_IDX 2
++#define mmSCL4_SCL_COEF_RAM_TAP_DATA 0x0e9b
++#define mmSCL4_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
++#define mmSCL4_SCL_MODE 0x0e9c
++#define mmSCL4_SCL_MODE_BASE_IDX 2
++#define mmSCL4_SCL_TAP_CONTROL 0x0e9d
++#define mmSCL4_SCL_TAP_CONTROL_BASE_IDX 2
++#define mmSCL4_SCL_CONTROL 0x0e9e
++#define mmSCL4_SCL_CONTROL_BASE_IDX 2
++#define mmSCL4_SCL_BYPASS_CONTROL 0x0e9f
++#define mmSCL4_SCL_BYPASS_CONTROL_BASE_IDX 2
++#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x0ea0
++#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
++#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL 0x0ea1
++#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2
++#define mmSCL4_SCL_HORZ_FILTER_CONTROL 0x0ea2
++#define mmSCL4_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2
++#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x0ea3
++#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
++#define mmSCL4_SCL_HORZ_FILTER_INIT 0x0ea4
++#define mmSCL4_SCL_HORZ_FILTER_INIT_BASE_IDX 2
++#define mmSCL4_SCL_VERT_FILTER_CONTROL 0x0ea5
++#define mmSCL4_SCL_VERT_FILTER_CONTROL_BASE_IDX 2
++#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x0ea6
++#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
++#define mmSCL4_SCL_VERT_FILTER_INIT 0x0ea7
++#define mmSCL4_SCL_VERT_FILTER_INIT_BASE_IDX 2
++#define mmSCL4_SCL_VERT_FILTER_INIT_BOT 0x0ea8
++#define mmSCL4_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
++#define mmSCL4_SCL_ROUND_OFFSET 0x0ea9
++#define mmSCL4_SCL_ROUND_OFFSET_BASE_IDX 2
++#define mmSCL4_SCL_UPDATE 0x0eaa
++#define mmSCL4_SCL_UPDATE_BASE_IDX 2
++#define mmSCL4_SCL_F_SHARP_CONTROL 0x0eab
++#define mmSCL4_SCL_F_SHARP_CONTROL_BASE_IDX 2
++#define mmSCL4_SCL_ALU_CONTROL 0x0eac
++#define mmSCL4_SCL_ALU_CONTROL_BASE_IDX 2
++#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0x0ead
++#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
++#define mmSCL4_VIEWPORT_START_SECONDARY 0x0eae
++#define mmSCL4_VIEWPORT_START_SECONDARY_BASE_IDX 2
++#define mmSCL4_VIEWPORT_START 0x0eaf
++#define mmSCL4_VIEWPORT_START_BASE_IDX 2
++#define mmSCL4_VIEWPORT_SIZE 0x0eb0
++#define mmSCL4_VIEWPORT_SIZE_BASE_IDX 2
++#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT 0x0eb1
++#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
++#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM 0x0eb2
++#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
++#define mmSCL4_SCL_MODE_CHANGE_DET1 0x0eb3
++#define mmSCL4_SCL_MODE_CHANGE_DET1_BASE_IDX 2
++#define mmSCL4_SCL_MODE_CHANGE_DET2 0x0eb4
++#define mmSCL4_SCL_MODE_CHANGE_DET2_BASE_IDX 2
++#define mmSCL4_SCL_MODE_CHANGE_DET3 0x0eb5
++#define mmSCL4_SCL_MODE_CHANGE_DET3_BASE_IDX 2
++#define mmSCL4_SCL_MODE_CHANGE_MASK 0x0eb6
++#define mmSCL4_SCL_MODE_CHANGE_MASK_BASE_IDX 2
++
++
++// addressBlock: dce_dc_blnd4_dispdec
++// base address: 0x2000
++#define mmBLND4_BLND_CONTROL 0x0ec7
++#define mmBLND4_BLND_CONTROL_BASE_IDX 2
++#define mmBLND4_BLND_SM_CONTROL2 0x0ec8
++#define mmBLND4_BLND_SM_CONTROL2_BASE_IDX 2
++#define mmBLND4_BLND_CONTROL2 0x0ec9
++#define mmBLND4_BLND_CONTROL2_BASE_IDX 2
++#define mmBLND4_BLND_UPDATE 0x0eca
++#define mmBLND4_BLND_UPDATE_BASE_IDX 2
++#define mmBLND4_BLND_UNDERFLOW_INTERRUPT 0x0ecb
++#define mmBLND4_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2
++#define mmBLND4_BLND_V_UPDATE_LOCK 0x0ecc
++#define mmBLND4_BLND_V_UPDATE_LOCK_BASE_IDX 2
++#define mmBLND4_BLND_REG_UPDATE_STATUS 0x0ecd
++#define mmBLND4_BLND_REG_UPDATE_STATUS_BASE_IDX 2
++
++
++// addressBlock: dce_dc_crtc4_dispdec
++// base address: 0x2000
++#define mmCRTC4_CRTC_H_BLANK_EARLY_NUM 0x0ed2
++#define mmCRTC4_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2
++#define mmCRTC4_CRTC_H_TOTAL 0x0ed3
++#define mmCRTC4_CRTC_H_TOTAL_BASE_IDX 2
++#define mmCRTC4_CRTC_H_BLANK_START_END 0x0ed4
++#define mmCRTC4_CRTC_H_BLANK_START_END_BASE_IDX 2
++#define mmCRTC4_CRTC_H_SYNC_A 0x0ed5
++#define mmCRTC4_CRTC_H_SYNC_A_BASE_IDX 2
++#define mmCRTC4_CRTC_H_SYNC_A_CNTL 0x0ed6
++#define mmCRTC4_CRTC_H_SYNC_A_CNTL_BASE_IDX 2
++#define mmCRTC4_CRTC_H_SYNC_B 0x0ed7
++#define mmCRTC4_CRTC_H_SYNC_B_BASE_IDX 2
++#define mmCRTC4_CRTC_H_SYNC_B_CNTL 0x0ed8
++#define mmCRTC4_CRTC_H_SYNC_B_CNTL_BASE_IDX 2
++#define mmCRTC4_CRTC_VBI_END 0x0ed9
++#define mmCRTC4_CRTC_VBI_END_BASE_IDX 2
++#define mmCRTC4_CRTC_V_TOTAL 0x0eda
++#define mmCRTC4_CRTC_V_TOTAL_BASE_IDX 2
++#define mmCRTC4_CRTC_V_TOTAL_MIN 0x0edb
++#define mmCRTC4_CRTC_V_TOTAL_MIN_BASE_IDX 2
++#define mmCRTC4_CRTC_V_TOTAL_MAX 0x0edc
++#define mmCRTC4_CRTC_V_TOTAL_MAX_BASE_IDX 2
++#define mmCRTC4_CRTC_V_TOTAL_CONTROL 0x0edd
++#define mmCRTC4_CRTC_V_TOTAL_CONTROL_BASE_IDX 2
++#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS 0x0ede
++#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2
++#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS 0x0edf
++#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2
++#define mmCRTC4_CRTC_V_BLANK_START_END 0x0ee0
++#define mmCRTC4_CRTC_V_BLANK_START_END_BASE_IDX 2
++#define mmCRTC4_CRTC_V_SYNC_A 0x0ee1
++#define mmCRTC4_CRTC_V_SYNC_A_BASE_IDX 2
++#define mmCRTC4_CRTC_V_SYNC_A_CNTL 0x0ee2
++#define mmCRTC4_CRTC_V_SYNC_A_CNTL_BASE_IDX 2
++#define mmCRTC4_CRTC_V_SYNC_B 0x0ee3
++#define mmCRTC4_CRTC_V_SYNC_B_BASE_IDX 2
++#define mmCRTC4_CRTC_V_SYNC_B_CNTL 0x0ee4
++#define mmCRTC4_CRTC_V_SYNC_B_CNTL_BASE_IDX 2
++#define mmCRTC4_CRTC_DTMTEST_CNTL 0x0ee5
++#define mmCRTC4_CRTC_DTMTEST_CNTL_BASE_IDX 2
++#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION 0x0ee6
++#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2
++#define mmCRTC4_CRTC_TRIGA_CNTL 0x0ee7
++#define mmCRTC4_CRTC_TRIGA_CNTL_BASE_IDX 2
++#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG 0x0ee8
++#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2
++#define mmCRTC4_CRTC_TRIGB_CNTL 0x0ee9
++#define mmCRTC4_CRTC_TRIGB_CNTL_BASE_IDX 2
++#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG 0x0eea
++#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2
++#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL 0x0eeb
++#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
++#define mmCRTC4_CRTC_FLOW_CONTROL 0x0eec
++#define mmCRTC4_CRTC_FLOW_CONTROL_BASE_IDX 2
++#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE 0x0eed
++#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
++#define mmCRTC4_CRTC_AVSYNC_COUNTER 0x0eee
++#define mmCRTC4_CRTC_AVSYNC_COUNTER_BASE_IDX 2
++#define mmCRTC4_CRTC_CONTROL 0x0eef
++#define mmCRTC4_CRTC_CONTROL_BASE_IDX 2
++#define mmCRTC4_CRTC_BLANK_CONTROL 0x0ef0
++#define mmCRTC4_CRTC_BLANK_CONTROL_BASE_IDX 2
++#define mmCRTC4_CRTC_INTERLACE_CONTROL 0x0ef1
++#define mmCRTC4_CRTC_INTERLACE_CONTROL_BASE_IDX 2
++#define mmCRTC4_CRTC_INTERLACE_STATUS 0x0ef2
++#define mmCRTC4_CRTC_INTERLACE_STATUS_BASE_IDX 2
++#define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL 0x0ef3
++#define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2
++#define mmCRTC4_CRTC_PIXEL_DATA_READBACK0 0x0ef4
++#define mmCRTC4_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2
++#define mmCRTC4_CRTC_PIXEL_DATA_READBACK1 0x0ef5
++#define mmCRTC4_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2
++#define mmCRTC4_CRTC_STATUS 0x0ef6
++#define mmCRTC4_CRTC_STATUS_BASE_IDX 2
++#define mmCRTC4_CRTC_STATUS_POSITION 0x0ef7
++#define mmCRTC4_CRTC_STATUS_POSITION_BASE_IDX 2
++#define mmCRTC4_CRTC_NOM_VERT_POSITION 0x0ef8
++#define mmCRTC4_CRTC_NOM_VERT_POSITION_BASE_IDX 2
++#define mmCRTC4_CRTC_STATUS_FRAME_COUNT 0x0ef9
++#define mmCRTC4_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2
++#define mmCRTC4_CRTC_STATUS_VF_COUNT 0x0efa
++#define mmCRTC4_CRTC_STATUS_VF_COUNT_BASE_IDX 2
++#define mmCRTC4_CRTC_STATUS_HV_COUNT 0x0efb
++#define mmCRTC4_CRTC_STATUS_HV_COUNT_BASE_IDX 2
++#define mmCRTC4_CRTC_COUNT_CONTROL 0x0efc
++#define mmCRTC4_CRTC_COUNT_CONTROL_BASE_IDX 2
++#define mmCRTC4_CRTC_COUNT_RESET 0x0efd
++#define mmCRTC4_CRTC_COUNT_RESET_BASE_IDX 2
++#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x0efe
++#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
++#define mmCRTC4_CRTC_VERT_SYNC_CONTROL 0x0eff
++#define mmCRTC4_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2
++#define mmCRTC4_CRTC_STEREO_STATUS 0x0f00
++#define mmCRTC4_CRTC_STEREO_STATUS_BASE_IDX 2
++#define mmCRTC4_CRTC_STEREO_CONTROL 0x0f01
++#define mmCRTC4_CRTC_STEREO_CONTROL_BASE_IDX 2
++#define mmCRTC4_CRTC_SNAPSHOT_STATUS 0x0f02
++#define mmCRTC4_CRTC_SNAPSHOT_STATUS_BASE_IDX 2
++#define mmCRTC4_CRTC_SNAPSHOT_CONTROL 0x0f03
++#define mmCRTC4_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2
++#define mmCRTC4_CRTC_SNAPSHOT_POSITION 0x0f04
++#define mmCRTC4_CRTC_SNAPSHOT_POSITION_BASE_IDX 2
++#define mmCRTC4_CRTC_SNAPSHOT_FRAME 0x0f05
++#define mmCRTC4_CRTC_SNAPSHOT_FRAME_BASE_IDX 2
++#define mmCRTC4_CRTC_START_LINE_CONTROL 0x0f06
++#define mmCRTC4_CRTC_START_LINE_CONTROL_BASE_IDX 2
++#define mmCRTC4_CRTC_INTERRUPT_CONTROL 0x0f07
++#define mmCRTC4_CRTC_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmCRTC4_CRTC_UPDATE_LOCK 0x0f08
++#define mmCRTC4_CRTC_UPDATE_LOCK_BASE_IDX 2
++#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL 0x0f09
++#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
++#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x0f0a
++#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2
++#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL 0x0f0b
++#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2
++#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS 0x0f0c
++#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2
++#define mmCRTC4_CRTC_TEST_PATTERN_COLOR 0x0f0d
++#define mmCRTC4_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2
++#define mmCRTC4_CRTC_MASTER_UPDATE_LOCK 0x0f0e
++#define mmCRTC4_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2
++#define mmCRTC4_CRTC_MASTER_UPDATE_MODE 0x0f0f
++#define mmCRTC4_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2
++#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT 0x0f10
++#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2
++#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x0f11
++#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2
++#define mmCRTC4_CRTC_MVP_STATUS 0x0f12
++#define mmCRTC4_CRTC_MVP_STATUS_BASE_IDX 2
++#define mmCRTC4_CRTC_MASTER_EN 0x0f13
++#define mmCRTC4_CRTC_MASTER_EN_BASE_IDX 2
++#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT 0x0f14
++#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2
++#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS 0x0f15
++#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2
++#define mmCRTC4_CRTC_OVERSCAN_COLOR 0x0f17
++#define mmCRTC4_CRTC_OVERSCAN_COLOR_BASE_IDX 2
++#define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT 0x0f18
++#define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2
++#define mmCRTC4_CRTC_BLANK_DATA_COLOR 0x0f19
++#define mmCRTC4_CRTC_BLANK_DATA_COLOR_BASE_IDX 2
++#define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT 0x0f1a
++#define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2
++#define mmCRTC4_CRTC_BLACK_COLOR 0x0f1b
++#define mmCRTC4_CRTC_BLACK_COLOR_BASE_IDX 2
++#define mmCRTC4_CRTC_BLACK_COLOR_EXT 0x0f1c
++#define mmCRTC4_CRTC_BLACK_COLOR_EXT_BASE_IDX 2
++#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION 0x0f1d
++#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
++#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x0f1e
++#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
++#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION 0x0f1f
++#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
++#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x0f20
++#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
++#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION 0x0f21
++#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
++#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x0f22
++#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
++#define mmCRTC4_CRTC_CRC_CNTL 0x0f23
++#define mmCRTC4_CRTC_CRC_CNTL_BASE_IDX 2
++#define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL 0x0f24
++#define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
++#define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL 0x0f25
++#define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
++#define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL 0x0f26
++#define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
++#define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL 0x0f27
++#define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
++#define mmCRTC4_CRTC_CRC0_DATA_RG 0x0f28
++#define mmCRTC4_CRTC_CRC0_DATA_RG_BASE_IDX 2
++#define mmCRTC4_CRTC_CRC0_DATA_B 0x0f29
++#define mmCRTC4_CRTC_CRC0_DATA_B_BASE_IDX 2
++#define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL 0x0f2a
++#define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
++#define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL 0x0f2b
++#define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
++#define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL 0x0f2c
++#define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
++#define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL 0x0f2d
++#define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
++#define mmCRTC4_CRTC_CRC1_DATA_RG 0x0f2e
++#define mmCRTC4_CRTC_CRC1_DATA_RG_BASE_IDX 2
++#define mmCRTC4_CRTC_CRC1_DATA_B 0x0f2f
++#define mmCRTC4_CRTC_CRC1_DATA_B_BASE_IDX 2
++#define mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL 0x0f30
++#define mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2
++#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x0f31
++#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2
++#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x0f32
++#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2
++#define mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x0f33
++#define mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x0f34
++#define mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x0f35
++#define mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL 0x0f36
++#define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2
++#define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL 0x0f37
++#define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2
++#define mmCRTC4_CRTC_GSL_VSYNC_GAP 0x0f38
++#define mmCRTC4_CRTC_GSL_VSYNC_GAP_BASE_IDX 2
++#define mmCRTC4_CRTC_GSL_WINDOW 0x0f39
++#define mmCRTC4_CRTC_GSL_WINDOW_BASE_IDX 2
++#define mmCRTC4_CRTC_GSL_CONTROL 0x0f3a
++#define mmCRTC4_CRTC_GSL_CONTROL_BASE_IDX 2
++#define mmCRTC4_CRTC_RANGE_TIMING_INT_STATUS 0x0f3d
++#define mmCRTC4_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2
++#define mmCRTC4_CRTC_DRR_CONTROL 0x0f3e
++#define mmCRTC4_CRTC_DRR_CONTROL_BASE_IDX 2
++
++
++// addressBlock: dce_dc_fmt4_dispdec
++// base address: 0x2000
++#define mmFMT4_FMT_CLAMP_COMPONENT_R 0x0f42
++#define mmFMT4_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
++#define mmFMT4_FMT_CLAMP_COMPONENT_G 0x0f43
++#define mmFMT4_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
++#define mmFMT4_FMT_CLAMP_COMPONENT_B 0x0f44
++#define mmFMT4_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
++#define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x0f45
++#define mmFMT4_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
++#define mmFMT4_FMT_CONTROL 0x0f46
++#define mmFMT4_FMT_CONTROL_BASE_IDX 2
++#define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x0f47
++#define mmFMT4_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
++#define mmFMT4_FMT_DITHER_RAND_R_SEED 0x0f48
++#define mmFMT4_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
++#define mmFMT4_FMT_DITHER_RAND_G_SEED 0x0f49
++#define mmFMT4_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
++#define mmFMT4_FMT_DITHER_RAND_B_SEED 0x0f4a
++#define mmFMT4_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
++#define mmFMT4_FMT_CLAMP_CNTL 0x0f4e
++#define mmFMT4_FMT_CLAMP_CNTL_BASE_IDX 2
++#define mmFMT4_FMT_CRC_CNTL 0x0f4f
++#define mmFMT4_FMT_CRC_CNTL_BASE_IDX 2
++#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK 0x0f50
++#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
++#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x0f51
++#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
++#define mmFMT4_FMT_CRC_SIG_RED_GREEN 0x0f52
++#define mmFMT4_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2
++#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL 0x0f53
++#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2
++#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x0f54
++#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
++#define mmFMT4_FMT_420_HBLANK_EARLY_START 0x0f55
++#define mmFMT4_FMT_420_HBLANK_EARLY_START_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dcp5_dispdec
++// base address: 0x2800
++#define mmDCP5_GRPH_ENABLE 0x0f5a
++#define mmDCP5_GRPH_ENABLE_BASE_IDX 2
++#define mmDCP5_GRPH_CONTROL 0x0f5b
++#define mmDCP5_GRPH_CONTROL_BASE_IDX 2
++#define mmDCP5_GRPH_LUT_10BIT_BYPASS 0x0f5c
++#define mmDCP5_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2
++#define mmDCP5_GRPH_SWAP_CNTL 0x0f5d
++#define mmDCP5_GRPH_SWAP_CNTL_BASE_IDX 2
++#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS 0x0f5e
++#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
++#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS 0x0f5f
++#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
++#define mmDCP5_GRPH_PITCH 0x0f60
++#define mmDCP5_GRPH_PITCH_BASE_IDX 2
++#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0f61
++#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
++#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0f62
++#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
++#define mmDCP5_GRPH_SURFACE_OFFSET_X 0x0f63
++#define mmDCP5_GRPH_SURFACE_OFFSET_X_BASE_IDX 2
++#define mmDCP5_GRPH_SURFACE_OFFSET_Y 0x0f64
++#define mmDCP5_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2
++#define mmDCP5_GRPH_X_START 0x0f65
++#define mmDCP5_GRPH_X_START_BASE_IDX 2
++#define mmDCP5_GRPH_Y_START 0x0f66
++#define mmDCP5_GRPH_Y_START_BASE_IDX 2
++#define mmDCP5_GRPH_X_END 0x0f67
++#define mmDCP5_GRPH_X_END_BASE_IDX 2
++#define mmDCP5_GRPH_Y_END 0x0f68
++#define mmDCP5_GRPH_Y_END_BASE_IDX 2
++#define mmDCP5_INPUT_GAMMA_CONTROL 0x0f69
++#define mmDCP5_INPUT_GAMMA_CONTROL_BASE_IDX 2
++#define mmDCP5_GRPH_UPDATE 0x0f6a
++#define mmDCP5_GRPH_UPDATE_BASE_IDX 2
++#define mmDCP5_GRPH_FLIP_CONTROL 0x0f6b
++#define mmDCP5_GRPH_FLIP_CONTROL_BASE_IDX 2
++#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE 0x0f6c
++#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2
++#define mmDCP5_GRPH_DFQ_CONTROL 0x0f6d
++#define mmDCP5_GRPH_DFQ_CONTROL_BASE_IDX 2
++#define mmDCP5_GRPH_DFQ_STATUS 0x0f6e
++#define mmDCP5_GRPH_DFQ_STATUS_BASE_IDX 2
++#define mmDCP5_GRPH_INTERRUPT_STATUS 0x0f6f
++#define mmDCP5_GRPH_INTERRUPT_STATUS_BASE_IDX 2
++#define mmDCP5_GRPH_INTERRUPT_CONTROL 0x0f70
++#define mmDCP5_GRPH_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0f71
++#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2
++#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS 0x0f72
++#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2
++#define mmDCP5_GRPH_COMPRESS_PITCH 0x0f73
++#define mmDCP5_GRPH_COMPRESS_PITCH_BASE_IDX 2
++#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0f74
++#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2
++#define mmDCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0f75
++#define mmDCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2
++#define mmDCP5_PRESCALE_GRPH_CONTROL 0x0f76
++#define mmDCP5_PRESCALE_GRPH_CONTROL_BASE_IDX 2
++#define mmDCP5_PRESCALE_VALUES_GRPH_R 0x0f77
++#define mmDCP5_PRESCALE_VALUES_GRPH_R_BASE_IDX 2
++#define mmDCP5_PRESCALE_VALUES_GRPH_G 0x0f78
++#define mmDCP5_PRESCALE_VALUES_GRPH_G_BASE_IDX 2
++#define mmDCP5_PRESCALE_VALUES_GRPH_B 0x0f79
++#define mmDCP5_PRESCALE_VALUES_GRPH_B_BASE_IDX 2
++#define mmDCP5_INPUT_CSC_CONTROL 0x0f7a
++#define mmDCP5_INPUT_CSC_CONTROL_BASE_IDX 2
++#define mmDCP5_INPUT_CSC_C11_C12 0x0f7b
++#define mmDCP5_INPUT_CSC_C11_C12_BASE_IDX 2
++#define mmDCP5_INPUT_CSC_C13_C14 0x0f7c
++#define mmDCP5_INPUT_CSC_C13_C14_BASE_IDX 2
++#define mmDCP5_INPUT_CSC_C21_C22 0x0f7d
++#define mmDCP5_INPUT_CSC_C21_C22_BASE_IDX 2
++#define mmDCP5_INPUT_CSC_C23_C24 0x0f7e
++#define mmDCP5_INPUT_CSC_C23_C24_BASE_IDX 2
++#define mmDCP5_INPUT_CSC_C31_C32 0x0f7f
++#define mmDCP5_INPUT_CSC_C31_C32_BASE_IDX 2
++#define mmDCP5_INPUT_CSC_C33_C34 0x0f80
++#define mmDCP5_INPUT_CSC_C33_C34_BASE_IDX 2
++#define mmDCP5_OUTPUT_CSC_CONTROL 0x0f81
++#define mmDCP5_OUTPUT_CSC_CONTROL_BASE_IDX 2
++#define mmDCP5_OUTPUT_CSC_C11_C12 0x0f82
++#define mmDCP5_OUTPUT_CSC_C11_C12_BASE_IDX 2
++#define mmDCP5_OUTPUT_CSC_C13_C14 0x0f83
++#define mmDCP5_OUTPUT_CSC_C13_C14_BASE_IDX 2
++#define mmDCP5_OUTPUT_CSC_C21_C22 0x0f84
++#define mmDCP5_OUTPUT_CSC_C21_C22_BASE_IDX 2
++#define mmDCP5_OUTPUT_CSC_C23_C24 0x0f85
++#define mmDCP5_OUTPUT_CSC_C23_C24_BASE_IDX 2
++#define mmDCP5_OUTPUT_CSC_C31_C32 0x0f86
++#define mmDCP5_OUTPUT_CSC_C31_C32_BASE_IDX 2
++#define mmDCP5_OUTPUT_CSC_C33_C34 0x0f87
++#define mmDCP5_OUTPUT_CSC_C33_C34_BASE_IDX 2
++#define mmDCP5_COMM_MATRIXA_TRANS_C11_C12 0x0f88
++#define mmDCP5_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2
++#define mmDCP5_COMM_MATRIXA_TRANS_C13_C14 0x0f89
++#define mmDCP5_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2
++#define mmDCP5_COMM_MATRIXA_TRANS_C21_C22 0x0f8a
++#define mmDCP5_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2
++#define mmDCP5_COMM_MATRIXA_TRANS_C23_C24 0x0f8b
++#define mmDCP5_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2
++#define mmDCP5_COMM_MATRIXA_TRANS_C31_C32 0x0f8c
++#define mmDCP5_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2
++#define mmDCP5_COMM_MATRIXA_TRANS_C33_C34 0x0f8d
++#define mmDCP5_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2
++#define mmDCP5_COMM_MATRIXB_TRANS_C11_C12 0x0f8e
++#define mmDCP5_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2
++#define mmDCP5_COMM_MATRIXB_TRANS_C13_C14 0x0f8f
++#define mmDCP5_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2
++#define mmDCP5_COMM_MATRIXB_TRANS_C21_C22 0x0f90
++#define mmDCP5_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2
++#define mmDCP5_COMM_MATRIXB_TRANS_C23_C24 0x0f91
++#define mmDCP5_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2
++#define mmDCP5_COMM_MATRIXB_TRANS_C31_C32 0x0f92
++#define mmDCP5_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2
++#define mmDCP5_COMM_MATRIXB_TRANS_C33_C34 0x0f93
++#define mmDCP5_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2
++#define mmDCP5_DENORM_CONTROL 0x0f94
++#define mmDCP5_DENORM_CONTROL_BASE_IDX 2
++#define mmDCP5_OUT_ROUND_CONTROL 0x0f95
++#define mmDCP5_OUT_ROUND_CONTROL_BASE_IDX 2
++#define mmDCP5_OUT_CLAMP_CONTROL_R_CR 0x0f96
++#define mmDCP5_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2
++#define mmDCP5_OUT_CLAMP_CONTROL_G_Y 0x0f97
++#define mmDCP5_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2
++#define mmDCP5_OUT_CLAMP_CONTROL_B_CB 0x0f98
++#define mmDCP5_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2
++#define mmDCP5_KEY_CONTROL 0x0f99
++#define mmDCP5_KEY_CONTROL_BASE_IDX 2
++#define mmDCP5_KEY_RANGE_ALPHA 0x0f9a
++#define mmDCP5_KEY_RANGE_ALPHA_BASE_IDX 2
++#define mmDCP5_KEY_RANGE_RED 0x0f9b
++#define mmDCP5_KEY_RANGE_RED_BASE_IDX 2
++#define mmDCP5_KEY_RANGE_GREEN 0x0f9c
++#define mmDCP5_KEY_RANGE_GREEN_BASE_IDX 2
++#define mmDCP5_KEY_RANGE_BLUE 0x0f9d
++#define mmDCP5_KEY_RANGE_BLUE_BASE_IDX 2
++#define mmDCP5_DEGAMMA_CONTROL 0x0f9e
++#define mmDCP5_DEGAMMA_CONTROL_BASE_IDX 2
++#define mmDCP5_GAMUT_REMAP_CONTROL 0x0f9f
++#define mmDCP5_GAMUT_REMAP_CONTROL_BASE_IDX 2
++#define mmDCP5_GAMUT_REMAP_C11_C12 0x0fa0
++#define mmDCP5_GAMUT_REMAP_C11_C12_BASE_IDX 2
++#define mmDCP5_GAMUT_REMAP_C13_C14 0x0fa1
++#define mmDCP5_GAMUT_REMAP_C13_C14_BASE_IDX 2
++#define mmDCP5_GAMUT_REMAP_C21_C22 0x0fa2
++#define mmDCP5_GAMUT_REMAP_C21_C22_BASE_IDX 2
++#define mmDCP5_GAMUT_REMAP_C23_C24 0x0fa3
++#define mmDCP5_GAMUT_REMAP_C23_C24_BASE_IDX 2
++#define mmDCP5_GAMUT_REMAP_C31_C32 0x0fa4
++#define mmDCP5_GAMUT_REMAP_C31_C32_BASE_IDX 2
++#define mmDCP5_GAMUT_REMAP_C33_C34 0x0fa5
++#define mmDCP5_GAMUT_REMAP_C33_C34_BASE_IDX 2
++#define mmDCP5_DCP_SPATIAL_DITHER_CNTL 0x0fa6
++#define mmDCP5_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2
++#define mmDCP5_DCP_RANDOM_SEEDS 0x0fa7
++#define mmDCP5_DCP_RANDOM_SEEDS_BASE_IDX 2
++#define mmDCP5_DCP_FP_CONVERTED_FIELD 0x0fa8
++#define mmDCP5_DCP_FP_CONVERTED_FIELD_BASE_IDX 2
++#define mmDCP5_CUR_CONTROL 0x0fa9
++#define mmDCP5_CUR_CONTROL_BASE_IDX 2
++#define mmDCP5_CUR_SURFACE_ADDRESS 0x0faa
++#define mmDCP5_CUR_SURFACE_ADDRESS_BASE_IDX 2
++#define mmDCP5_CUR_SIZE 0x0fab
++#define mmDCP5_CUR_SIZE_BASE_IDX 2
++#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH 0x0fac
++#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
++#define mmDCP5_CUR_POSITION 0x0fad
++#define mmDCP5_CUR_POSITION_BASE_IDX 2
++#define mmDCP5_CUR_HOT_SPOT 0x0fae
++#define mmDCP5_CUR_HOT_SPOT_BASE_IDX 2
++#define mmDCP5_CUR_COLOR1 0x0faf
++#define mmDCP5_CUR_COLOR1_BASE_IDX 2
++#define mmDCP5_CUR_COLOR2 0x0fb0
++#define mmDCP5_CUR_COLOR2_BASE_IDX 2
++#define mmDCP5_CUR_UPDATE 0x0fb1
++#define mmDCP5_CUR_UPDATE_BASE_IDX 2
++#define mmDCP5_CUR_REQUEST_FILTER_CNTL 0x0fbb
++#define mmDCP5_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2
++#define mmDCP5_CUR_STEREO_CONTROL 0x0fbc
++#define mmDCP5_CUR_STEREO_CONTROL_BASE_IDX 2
++#define mmDCP5_DC_LUT_RW_MODE 0x0fbe
++#define mmDCP5_DC_LUT_RW_MODE_BASE_IDX 2
++#define mmDCP5_DC_LUT_RW_INDEX 0x0fbf
++#define mmDCP5_DC_LUT_RW_INDEX_BASE_IDX 2
++#define mmDCP5_DC_LUT_SEQ_COLOR 0x0fc0
++#define mmDCP5_DC_LUT_SEQ_COLOR_BASE_IDX 2
++#define mmDCP5_DC_LUT_PWL_DATA 0x0fc1
++#define mmDCP5_DC_LUT_PWL_DATA_BASE_IDX 2
++#define mmDCP5_DC_LUT_30_COLOR 0x0fc2
++#define mmDCP5_DC_LUT_30_COLOR_BASE_IDX 2
++#define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE 0x0fc3
++#define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2
++#define mmDCP5_DC_LUT_WRITE_EN_MASK 0x0fc4
++#define mmDCP5_DC_LUT_WRITE_EN_MASK_BASE_IDX 2
++#define mmDCP5_DC_LUT_AUTOFILL 0x0fc5
++#define mmDCP5_DC_LUT_AUTOFILL_BASE_IDX 2
++#define mmDCP5_DC_LUT_CONTROL 0x0fc6
++#define mmDCP5_DC_LUT_CONTROL_BASE_IDX 2
++#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE 0x0fc7
++#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2
++#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN 0x0fc8
++#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2
++#define mmDCP5_DC_LUT_BLACK_OFFSET_RED 0x0fc9
++#define mmDCP5_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2
++#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE 0x0fca
++#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2
++#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN 0x0fcb
++#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2
++#define mmDCP5_DC_LUT_WHITE_OFFSET_RED 0x0fcc
++#define mmDCP5_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2
++#define mmDCP5_DCP_CRC_CONTROL 0x0fcd
++#define mmDCP5_DCP_CRC_CONTROL_BASE_IDX 2
++#define mmDCP5_DCP_CRC_MASK 0x0fce
++#define mmDCP5_DCP_CRC_MASK_BASE_IDX 2
++#define mmDCP5_DCP_CRC_CURRENT 0x0fcf
++#define mmDCP5_DCP_CRC_CURRENT_BASE_IDX 2
++#define mmDCP5_DVMM_PTE_CONTROL 0x0fd0
++#define mmDCP5_DVMM_PTE_CONTROL_BASE_IDX 2
++#define mmDCP5_DCP_CRC_LAST 0x0fd1
++#define mmDCP5_DCP_CRC_LAST_BASE_IDX 2
++#define mmDCP5_DVMM_PTE_ARB_CONTROL 0x0fd2
++#define mmDCP5_DVMM_PTE_ARB_CONTROL_BASE_IDX 2
++#define mmDCP5_GRPH_FLIP_RATE_CNTL 0x0fd4
++#define mmDCP5_GRPH_FLIP_RATE_CNTL_BASE_IDX 2
++#define mmDCP5_DCP_GSL_CONTROL 0x0fd5
++#define mmDCP5_DCP_GSL_CONTROL_BASE_IDX 2
++#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x0fd6
++#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2
++#define mmDCP5_GRPH_STEREOSYNC_FLIP 0x0fdc
++#define mmDCP5_GRPH_STEREOSYNC_FLIP_BASE_IDX 2
++#define mmDCP5_HW_ROTATION 0x0fde
++#define mmDCP5_HW_ROTATION_BASE_IDX 2
++#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x0fdf
++#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2
++#define mmDCP5_REGAMMA_CONTROL 0x0fe0
++#define mmDCP5_REGAMMA_CONTROL_BASE_IDX 2
++#define mmDCP5_REGAMMA_LUT_INDEX 0x0fe1
++#define mmDCP5_REGAMMA_LUT_INDEX_BASE_IDX 2
++#define mmDCP5_REGAMMA_LUT_DATA 0x0fe2
++#define mmDCP5_REGAMMA_LUT_DATA_BASE_IDX 2
++#define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK 0x0fe3
++#define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2
++#define mmDCP5_REGAMMA_CNTLA_START_CNTL 0x0fe4
++#define mmDCP5_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2
++#define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL 0x0fe5
++#define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2
++#define mmDCP5_REGAMMA_CNTLA_END_CNTL1 0x0fe6
++#define mmDCP5_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2
++#define mmDCP5_REGAMMA_CNTLA_END_CNTL2 0x0fe7
++#define mmDCP5_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2
++#define mmDCP5_REGAMMA_CNTLA_REGION_0_1 0x0fe8
++#define mmDCP5_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2
++#define mmDCP5_REGAMMA_CNTLA_REGION_2_3 0x0fe9
++#define mmDCP5_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2
++#define mmDCP5_REGAMMA_CNTLA_REGION_4_5 0x0fea
++#define mmDCP5_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2
++#define mmDCP5_REGAMMA_CNTLA_REGION_6_7 0x0feb
++#define mmDCP5_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2
++#define mmDCP5_REGAMMA_CNTLA_REGION_8_9 0x0fec
++#define mmDCP5_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2
++#define mmDCP5_REGAMMA_CNTLA_REGION_10_11 0x0fed
++#define mmDCP5_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2
++#define mmDCP5_REGAMMA_CNTLA_REGION_12_13 0x0fee
++#define mmDCP5_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2
++#define mmDCP5_REGAMMA_CNTLA_REGION_14_15 0x0fef
++#define mmDCP5_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2
++#define mmDCP5_REGAMMA_CNTLB_START_CNTL 0x0ff0
++#define mmDCP5_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2
++#define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL 0x0ff1
++#define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2
++#define mmDCP5_REGAMMA_CNTLB_END_CNTL1 0x0ff2
++#define mmDCP5_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2
++#define mmDCP5_REGAMMA_CNTLB_END_CNTL2 0x0ff3
++#define mmDCP5_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2
++#define mmDCP5_REGAMMA_CNTLB_REGION_0_1 0x0ff4
++#define mmDCP5_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2
++#define mmDCP5_REGAMMA_CNTLB_REGION_2_3 0x0ff5
++#define mmDCP5_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2
++#define mmDCP5_REGAMMA_CNTLB_REGION_4_5 0x0ff6
++#define mmDCP5_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2
++#define mmDCP5_REGAMMA_CNTLB_REGION_6_7 0x0ff7
++#define mmDCP5_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2
++#define mmDCP5_REGAMMA_CNTLB_REGION_8_9 0x0ff8
++#define mmDCP5_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2
++#define mmDCP5_REGAMMA_CNTLB_REGION_10_11 0x0ff9
++#define mmDCP5_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2
++#define mmDCP5_REGAMMA_CNTLB_REGION_12_13 0x0ffa
++#define mmDCP5_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2
++#define mmDCP5_REGAMMA_CNTLB_REGION_14_15 0x0ffb
++#define mmDCP5_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2
++#define mmDCP5_ALPHA_CONTROL 0x0ffc
++#define mmDCP5_ALPHA_CONTROL_BASE_IDX 2
++#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x0ffd
++#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2
++#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x0ffe
++#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
++#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x0fff
++#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2
++#define mmDCP5_GRPH_XDMA_FLIP_TIMEOUT 0x1000
++#define mmDCP5_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2
++#define mmDCP5_GRPH_XDMA_FLIP_AVG_DELAY 0x1001
++#define mmDCP5_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2
++#define mmDCP5_GRPH_SURFACE_COUNTER_CONTROL 0x1002
++#define mmDCP5_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2
++#define mmDCP5_GRPH_SURFACE_COUNTER_OUTPUT 0x1003
++#define mmDCP5_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2
++
++
++// addressBlock: dce_dc_lb5_dispdec
++// base address: 0x2800
++#define mmLB5_LB_DATA_FORMAT 0x101a
++#define mmLB5_LB_DATA_FORMAT_BASE_IDX 2
++#define mmLB5_LB_MEMORY_CTRL 0x101b
++#define mmLB5_LB_MEMORY_CTRL_BASE_IDX 2
++#define mmLB5_LB_MEMORY_SIZE_STATUS 0x101c
++#define mmLB5_LB_MEMORY_SIZE_STATUS_BASE_IDX 2
++#define mmLB5_LB_DESKTOP_HEIGHT 0x101d
++#define mmLB5_LB_DESKTOP_HEIGHT_BASE_IDX 2
++#define mmLB5_LB_VLINE_START_END 0x101e
++#define mmLB5_LB_VLINE_START_END_BASE_IDX 2
++#define mmLB5_LB_VLINE2_START_END 0x101f
++#define mmLB5_LB_VLINE2_START_END_BASE_IDX 2
++#define mmLB5_LB_V_COUNTER 0x1020
++#define mmLB5_LB_V_COUNTER_BASE_IDX 2
++#define mmLB5_LB_SNAPSHOT_V_COUNTER 0x1021
++#define mmLB5_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2
++#define mmLB5_LB_INTERRUPT_MASK 0x1022
++#define mmLB5_LB_INTERRUPT_MASK_BASE_IDX 2
++#define mmLB5_LB_VLINE_STATUS 0x1023
++#define mmLB5_LB_VLINE_STATUS_BASE_IDX 2
++#define mmLB5_LB_VLINE2_STATUS 0x1024
++#define mmLB5_LB_VLINE2_STATUS_BASE_IDX 2
++#define mmLB5_LB_VBLANK_STATUS 0x1025
++#define mmLB5_LB_VBLANK_STATUS_BASE_IDX 2
++#define mmLB5_LB_SYNC_RESET_SEL 0x1026
++#define mmLB5_LB_SYNC_RESET_SEL_BASE_IDX 2
++#define mmLB5_LB_BLACK_KEYER_R_CR 0x1027
++#define mmLB5_LB_BLACK_KEYER_R_CR_BASE_IDX 2
++#define mmLB5_LB_BLACK_KEYER_G_Y 0x1028
++#define mmLB5_LB_BLACK_KEYER_G_Y_BASE_IDX 2
++#define mmLB5_LB_BLACK_KEYER_B_CB 0x1029
++#define mmLB5_LB_BLACK_KEYER_B_CB_BASE_IDX 2
++#define mmLB5_LB_KEYER_COLOR_CTRL 0x102a
++#define mmLB5_LB_KEYER_COLOR_CTRL_BASE_IDX 2
++#define mmLB5_LB_KEYER_COLOR_R_CR 0x102b
++#define mmLB5_LB_KEYER_COLOR_R_CR_BASE_IDX 2
++#define mmLB5_LB_KEYER_COLOR_G_Y 0x102c
++#define mmLB5_LB_KEYER_COLOR_G_Y_BASE_IDX 2
++#define mmLB5_LB_KEYER_COLOR_B_CB 0x102d
++#define mmLB5_LB_KEYER_COLOR_B_CB_BASE_IDX 2
++#define mmLB5_LB_KEYER_COLOR_REP_R_CR 0x102e
++#define mmLB5_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2
++#define mmLB5_LB_KEYER_COLOR_REP_G_Y 0x102f
++#define mmLB5_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2
++#define mmLB5_LB_KEYER_COLOR_REP_B_CB 0x1030
++#define mmLB5_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2
++#define mmLB5_LB_BUFFER_LEVEL_STATUS 0x1031
++#define mmLB5_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2
++#define mmLB5_LB_BUFFER_URGENCY_CTRL 0x1032
++#define mmLB5_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2
++#define mmLB5_LB_BUFFER_URGENCY_STATUS 0x1033
++#define mmLB5_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2
++#define mmLB5_LB_BUFFER_STATUS 0x1034
++#define mmLB5_LB_BUFFER_STATUS_BASE_IDX 2
++#define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0x1035
++#define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2
++#define mmLB5_MVP_AFR_FLIP_MODE 0x1036
++#define mmLB5_MVP_AFR_FLIP_MODE_BASE_IDX 2
++#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0x1037
++#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2
++#define mmLB5_MVP_FLIP_LINE_NUM_INSERT 0x1038
++#define mmLB5_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2
++#define mmLB5_DC_MVP_LB_CONTROL 0x1039
++#define mmLB5_DC_MVP_LB_CONTROL_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dcfe5_dispdec
++// base address: 0x2800
++#define mmDCFE5_DCFE_CLOCK_CONTROL 0x105a
++#define mmDCFE5_DCFE_CLOCK_CONTROL_BASE_IDX 2
++#define mmDCFE5_DCFE_SOFT_RESET 0x105b
++#define mmDCFE5_DCFE_SOFT_RESET_BASE_IDX 2
++#define mmDCFE5_DCFE_MEM_PWR_CTRL 0x105d
++#define mmDCFE5_DCFE_MEM_PWR_CTRL_BASE_IDX 2
++#define mmDCFE5_DCFE_MEM_PWR_CTRL2 0x105e
++#define mmDCFE5_DCFE_MEM_PWR_CTRL2_BASE_IDX 2
++#define mmDCFE5_DCFE_MEM_PWR_STATUS 0x105f
++#define mmDCFE5_DCFE_MEM_PWR_STATUS_BASE_IDX 2
++#define mmDCFE5_DCFE_MISC 0x1060
++#define mmDCFE5_DCFE_MISC_BASE_IDX 2
++#define mmDCFE5_DCFE_FLUSH 0x1061
++#define mmDCFE5_DCFE_FLUSH_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dc_perfmon8_dispdec
++// base address: 0x4138
++#define mmDC_PERFMON8_PERFCOUNTER_CNTL 0x106e
++#define mmDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX 2
++#define mmDC_PERFMON8_PERFCOUNTER_CNTL2 0x106f
++#define mmDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX 2
++#define mmDC_PERFMON8_PERFCOUNTER_STATE 0x1070
++#define mmDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX 2
++#define mmDC_PERFMON8_PERFMON_CNTL 0x1071
++#define mmDC_PERFMON8_PERFMON_CNTL_BASE_IDX 2
++#define mmDC_PERFMON8_PERFMON_CNTL2 0x1072
++#define mmDC_PERFMON8_PERFMON_CNTL2_BASE_IDX 2
++#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x1073
++#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
++#define mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x1074
++#define mmDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX 2
++#define mmDC_PERFMON8_PERFMON_HI 0x1075
++#define mmDC_PERFMON8_PERFMON_HI_BASE_IDX 2
++#define mmDC_PERFMON8_PERFMON_LOW 0x1076
++#define mmDC_PERFMON8_PERFMON_LOW_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dmif_pg5_dispdec
++// base address: 0x2800
++#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 0x107a
++#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
++#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 0x107b
++#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
++#define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 0x107c
++#define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2
++#define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL 0x107d
++#define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2
++#define mmDMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL 0x107e
++#define mmDMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2
++#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL 0x107f
++#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2
++#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL2 0x1080
++#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2
++#define mmDMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL 0x1081
++#define mmDMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2
++#define mmDMIF_PG5_DPG_REPEATER_PROGRAM 0x1082
++#define mmDMIF_PG5_DPG_REPEATER_PROGRAM_BASE_IDX 2
++#define mmDMIF_PG5_DPG_CHK_PRE_PROC_CNTL 0x1086
++#define mmDMIF_PG5_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2
++#define mmDMIF_PG5_DPG_DVMM_STATUS 0x1087
++#define mmDMIF_PG5_DPG_DVMM_STATUS_BASE_IDX 2
++
++
++// addressBlock: dce_dc_scl5_dispdec
++// base address: 0x2800
++#define mmSCL5_SCL_COEF_RAM_SELECT 0x109a
++#define mmSCL5_SCL_COEF_RAM_SELECT_BASE_IDX 2
++#define mmSCL5_SCL_COEF_RAM_TAP_DATA 0x109b
++#define mmSCL5_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
++#define mmSCL5_SCL_MODE 0x109c
++#define mmSCL5_SCL_MODE_BASE_IDX 2
++#define mmSCL5_SCL_TAP_CONTROL 0x109d
++#define mmSCL5_SCL_TAP_CONTROL_BASE_IDX 2
++#define mmSCL5_SCL_CONTROL 0x109e
++#define mmSCL5_SCL_CONTROL_BASE_IDX 2
++#define mmSCL5_SCL_BYPASS_CONTROL 0x109f
++#define mmSCL5_SCL_BYPASS_CONTROL_BASE_IDX 2
++#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x10a0
++#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
++#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL 0x10a1
++#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2
++#define mmSCL5_SCL_HORZ_FILTER_CONTROL 0x10a2
++#define mmSCL5_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2
++#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x10a3
++#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
++#define mmSCL5_SCL_HORZ_FILTER_INIT 0x10a4
++#define mmSCL5_SCL_HORZ_FILTER_INIT_BASE_IDX 2
++#define mmSCL5_SCL_VERT_FILTER_CONTROL 0x10a5
++#define mmSCL5_SCL_VERT_FILTER_CONTROL_BASE_IDX 2
++#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x10a6
++#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
++#define mmSCL5_SCL_VERT_FILTER_INIT 0x10a7
++#define mmSCL5_SCL_VERT_FILTER_INIT_BASE_IDX 2
++#define mmSCL5_SCL_VERT_FILTER_INIT_BOT 0x10a8
++#define mmSCL5_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
++#define mmSCL5_SCL_ROUND_OFFSET 0x10a9
++#define mmSCL5_SCL_ROUND_OFFSET_BASE_IDX 2
++#define mmSCL5_SCL_UPDATE 0x10aa
++#define mmSCL5_SCL_UPDATE_BASE_IDX 2
++#define mmSCL5_SCL_F_SHARP_CONTROL 0x10ab
++#define mmSCL5_SCL_F_SHARP_CONTROL_BASE_IDX 2
++#define mmSCL5_SCL_ALU_CONTROL 0x10ac
++#define mmSCL5_SCL_ALU_CONTROL_BASE_IDX 2
++#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0x10ad
++#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
++#define mmSCL5_VIEWPORT_START_SECONDARY 0x10ae
++#define mmSCL5_VIEWPORT_START_SECONDARY_BASE_IDX 2
++#define mmSCL5_VIEWPORT_START 0x10af
++#define mmSCL5_VIEWPORT_START_BASE_IDX 2
++#define mmSCL5_VIEWPORT_SIZE 0x10b0
++#define mmSCL5_VIEWPORT_SIZE_BASE_IDX 2
++#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT 0x10b1
++#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
++#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM 0x10b2
++#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
++#define mmSCL5_SCL_MODE_CHANGE_DET1 0x10b3
++#define mmSCL5_SCL_MODE_CHANGE_DET1_BASE_IDX 2
++#define mmSCL5_SCL_MODE_CHANGE_DET2 0x10b4
++#define mmSCL5_SCL_MODE_CHANGE_DET2_BASE_IDX 2
++#define mmSCL5_SCL_MODE_CHANGE_DET3 0x10b5
++#define mmSCL5_SCL_MODE_CHANGE_DET3_BASE_IDX 2
++#define mmSCL5_SCL_MODE_CHANGE_MASK 0x10b6
++#define mmSCL5_SCL_MODE_CHANGE_MASK_BASE_IDX 2
++
++
++// addressBlock: dce_dc_blnd5_dispdec
++// base address: 0x2800
++#define mmBLND5_BLND_CONTROL 0x10c7
++#define mmBLND5_BLND_CONTROL_BASE_IDX 2
++#define mmBLND5_BLND_SM_CONTROL2 0x10c8
++#define mmBLND5_BLND_SM_CONTROL2_BASE_IDX 2
++#define mmBLND5_BLND_CONTROL2 0x10c9
++#define mmBLND5_BLND_CONTROL2_BASE_IDX 2
++#define mmBLND5_BLND_UPDATE 0x10ca
++#define mmBLND5_BLND_UPDATE_BASE_IDX 2
++#define mmBLND5_BLND_UNDERFLOW_INTERRUPT 0x10cb
++#define mmBLND5_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2
++#define mmBLND5_BLND_V_UPDATE_LOCK 0x10cc
++#define mmBLND5_BLND_V_UPDATE_LOCK_BASE_IDX 2
++#define mmBLND5_BLND_REG_UPDATE_STATUS 0x10cd
++#define mmBLND5_BLND_REG_UPDATE_STATUS_BASE_IDX 2
++
++
++// addressBlock: dce_dc_crtc5_dispdec
++// base address: 0x2800
++#define mmCRTC5_CRTC_H_BLANK_EARLY_NUM 0x10d2
++#define mmCRTC5_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2
++#define mmCRTC5_CRTC_H_TOTAL 0x10d3
++#define mmCRTC5_CRTC_H_TOTAL_BASE_IDX 2
++#define mmCRTC5_CRTC_H_BLANK_START_END 0x10d4
++#define mmCRTC5_CRTC_H_BLANK_START_END_BASE_IDX 2
++#define mmCRTC5_CRTC_H_SYNC_A 0x10d5
++#define mmCRTC5_CRTC_H_SYNC_A_BASE_IDX 2
++#define mmCRTC5_CRTC_H_SYNC_A_CNTL 0x10d6
++#define mmCRTC5_CRTC_H_SYNC_A_CNTL_BASE_IDX 2
++#define mmCRTC5_CRTC_H_SYNC_B 0x10d7
++#define mmCRTC5_CRTC_H_SYNC_B_BASE_IDX 2
++#define mmCRTC5_CRTC_H_SYNC_B_CNTL 0x10d8
++#define mmCRTC5_CRTC_H_SYNC_B_CNTL_BASE_IDX 2
++#define mmCRTC5_CRTC_VBI_END 0x10d9
++#define mmCRTC5_CRTC_VBI_END_BASE_IDX 2
++#define mmCRTC5_CRTC_V_TOTAL 0x10da
++#define mmCRTC5_CRTC_V_TOTAL_BASE_IDX 2
++#define mmCRTC5_CRTC_V_TOTAL_MIN 0x10db
++#define mmCRTC5_CRTC_V_TOTAL_MIN_BASE_IDX 2
++#define mmCRTC5_CRTC_V_TOTAL_MAX 0x10dc
++#define mmCRTC5_CRTC_V_TOTAL_MAX_BASE_IDX 2
++#define mmCRTC5_CRTC_V_TOTAL_CONTROL 0x10dd
++#define mmCRTC5_CRTC_V_TOTAL_CONTROL_BASE_IDX 2
++#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS 0x10de
++#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2
++#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS 0x10df
++#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2
++#define mmCRTC5_CRTC_V_BLANK_START_END 0x10e0
++#define mmCRTC5_CRTC_V_BLANK_START_END_BASE_IDX 2
++#define mmCRTC5_CRTC_V_SYNC_A 0x10e1
++#define mmCRTC5_CRTC_V_SYNC_A_BASE_IDX 2
++#define mmCRTC5_CRTC_V_SYNC_A_CNTL 0x10e2
++#define mmCRTC5_CRTC_V_SYNC_A_CNTL_BASE_IDX 2
++#define mmCRTC5_CRTC_V_SYNC_B 0x10e3
++#define mmCRTC5_CRTC_V_SYNC_B_BASE_IDX 2
++#define mmCRTC5_CRTC_V_SYNC_B_CNTL 0x10e4
++#define mmCRTC5_CRTC_V_SYNC_B_CNTL_BASE_IDX 2
++#define mmCRTC5_CRTC_DTMTEST_CNTL 0x10e5
++#define mmCRTC5_CRTC_DTMTEST_CNTL_BASE_IDX 2
++#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION 0x10e6
++#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2
++#define mmCRTC5_CRTC_TRIGA_CNTL 0x10e7
++#define mmCRTC5_CRTC_TRIGA_CNTL_BASE_IDX 2
++#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG 0x10e8
++#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2
++#define mmCRTC5_CRTC_TRIGB_CNTL 0x10e9
++#define mmCRTC5_CRTC_TRIGB_CNTL_BASE_IDX 2
++#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG 0x10ea
++#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2
++#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL 0x10eb
++#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
++#define mmCRTC5_CRTC_FLOW_CONTROL 0x10ec
++#define mmCRTC5_CRTC_FLOW_CONTROL_BASE_IDX 2
++#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE 0x10ed
++#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
++#define mmCRTC5_CRTC_AVSYNC_COUNTER 0x10ee
++#define mmCRTC5_CRTC_AVSYNC_COUNTER_BASE_IDX 2
++#define mmCRTC5_CRTC_CONTROL 0x10ef
++#define mmCRTC5_CRTC_CONTROL_BASE_IDX 2
++#define mmCRTC5_CRTC_BLANK_CONTROL 0x10f0
++#define mmCRTC5_CRTC_BLANK_CONTROL_BASE_IDX 2
++#define mmCRTC5_CRTC_INTERLACE_CONTROL 0x10f1
++#define mmCRTC5_CRTC_INTERLACE_CONTROL_BASE_IDX 2
++#define mmCRTC5_CRTC_INTERLACE_STATUS 0x10f2
++#define mmCRTC5_CRTC_INTERLACE_STATUS_BASE_IDX 2
++#define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL 0x10f3
++#define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2
++#define mmCRTC5_CRTC_PIXEL_DATA_READBACK0 0x10f4
++#define mmCRTC5_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2
++#define mmCRTC5_CRTC_PIXEL_DATA_READBACK1 0x10f5
++#define mmCRTC5_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2
++#define mmCRTC5_CRTC_STATUS 0x10f6
++#define mmCRTC5_CRTC_STATUS_BASE_IDX 2
++#define mmCRTC5_CRTC_STATUS_POSITION 0x10f7
++#define mmCRTC5_CRTC_STATUS_POSITION_BASE_IDX 2
++#define mmCRTC5_CRTC_NOM_VERT_POSITION 0x10f8
++#define mmCRTC5_CRTC_NOM_VERT_POSITION_BASE_IDX 2
++#define mmCRTC5_CRTC_STATUS_FRAME_COUNT 0x10f9
++#define mmCRTC5_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2
++#define mmCRTC5_CRTC_STATUS_VF_COUNT 0x10fa
++#define mmCRTC5_CRTC_STATUS_VF_COUNT_BASE_IDX 2
++#define mmCRTC5_CRTC_STATUS_HV_COUNT 0x10fb
++#define mmCRTC5_CRTC_STATUS_HV_COUNT_BASE_IDX 2
++#define mmCRTC5_CRTC_COUNT_CONTROL 0x10fc
++#define mmCRTC5_CRTC_COUNT_CONTROL_BASE_IDX 2
++#define mmCRTC5_CRTC_COUNT_RESET 0x10fd
++#define mmCRTC5_CRTC_COUNT_RESET_BASE_IDX 2
++#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x10fe
++#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
++#define mmCRTC5_CRTC_VERT_SYNC_CONTROL 0x10ff
++#define mmCRTC5_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2
++#define mmCRTC5_CRTC_STEREO_STATUS 0x1100
++#define mmCRTC5_CRTC_STEREO_STATUS_BASE_IDX 2
++#define mmCRTC5_CRTC_STEREO_CONTROL 0x1101
++#define mmCRTC5_CRTC_STEREO_CONTROL_BASE_IDX 2
++#define mmCRTC5_CRTC_SNAPSHOT_STATUS 0x1102
++#define mmCRTC5_CRTC_SNAPSHOT_STATUS_BASE_IDX 2
++#define mmCRTC5_CRTC_SNAPSHOT_CONTROL 0x1103
++#define mmCRTC5_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2
++#define mmCRTC5_CRTC_SNAPSHOT_POSITION 0x1104
++#define mmCRTC5_CRTC_SNAPSHOT_POSITION_BASE_IDX 2
++#define mmCRTC5_CRTC_SNAPSHOT_FRAME 0x1105
++#define mmCRTC5_CRTC_SNAPSHOT_FRAME_BASE_IDX 2
++#define mmCRTC5_CRTC_START_LINE_CONTROL 0x1106
++#define mmCRTC5_CRTC_START_LINE_CONTROL_BASE_IDX 2
++#define mmCRTC5_CRTC_INTERRUPT_CONTROL 0x1107
++#define mmCRTC5_CRTC_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmCRTC5_CRTC_UPDATE_LOCK 0x1108
++#define mmCRTC5_CRTC_UPDATE_LOCK_BASE_IDX 2
++#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL 0x1109
++#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
++#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x110a
++#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2
++#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL 0x110b
++#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2
++#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS 0x110c
++#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2
++#define mmCRTC5_CRTC_TEST_PATTERN_COLOR 0x110d
++#define mmCRTC5_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2
++#define mmCRTC5_CRTC_MASTER_UPDATE_LOCK 0x110e
++#define mmCRTC5_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2
++#define mmCRTC5_CRTC_MASTER_UPDATE_MODE 0x110f
++#define mmCRTC5_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2
++#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT 0x1110
++#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2
++#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1111
++#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2
++#define mmCRTC5_CRTC_MVP_STATUS 0x1112
++#define mmCRTC5_CRTC_MVP_STATUS_BASE_IDX 2
++#define mmCRTC5_CRTC_MASTER_EN 0x1113
++#define mmCRTC5_CRTC_MASTER_EN_BASE_IDX 2
++#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT 0x1114
++#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2
++#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS 0x1115
++#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2
++#define mmCRTC5_CRTC_OVERSCAN_COLOR 0x1117
++#define mmCRTC5_CRTC_OVERSCAN_COLOR_BASE_IDX 2
++#define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT 0x1118
++#define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2
++#define mmCRTC5_CRTC_BLANK_DATA_COLOR 0x1119
++#define mmCRTC5_CRTC_BLANK_DATA_COLOR_BASE_IDX 2
++#define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT 0x111a
++#define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2
++#define mmCRTC5_CRTC_BLACK_COLOR 0x111b
++#define mmCRTC5_CRTC_BLACK_COLOR_BASE_IDX 2
++#define mmCRTC5_CRTC_BLACK_COLOR_EXT 0x111c
++#define mmCRTC5_CRTC_BLACK_COLOR_EXT_BASE_IDX 2
++#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION 0x111d
++#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
++#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x111e
++#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
++#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION 0x111f
++#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
++#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1120
++#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
++#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1121
++#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
++#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1122
++#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
++#define mmCRTC5_CRTC_CRC_CNTL 0x1123
++#define mmCRTC5_CRTC_CRC_CNTL_BASE_IDX 2
++#define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL 0x1124
++#define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
++#define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1125
++#define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
++#define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL 0x1126
++#define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
++#define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1127
++#define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
++#define mmCRTC5_CRTC_CRC0_DATA_RG 0x1128
++#define mmCRTC5_CRTC_CRC0_DATA_RG_BASE_IDX 2
++#define mmCRTC5_CRTC_CRC0_DATA_B 0x1129
++#define mmCRTC5_CRTC_CRC0_DATA_B_BASE_IDX 2
++#define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL 0x112a
++#define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
++#define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL 0x112b
++#define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
++#define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL 0x112c
++#define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
++#define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL 0x112d
++#define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
++#define mmCRTC5_CRTC_CRC1_DATA_RG 0x112e
++#define mmCRTC5_CRTC_CRC1_DATA_RG_BASE_IDX 2
++#define mmCRTC5_CRTC_CRC1_DATA_B 0x112f
++#define mmCRTC5_CRTC_CRC1_DATA_B_BASE_IDX 2
++#define mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL 0x1130
++#define mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2
++#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1131
++#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2
++#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1132
++#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2
++#define mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1133
++#define mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1134
++#define mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1135
++#define mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL 0x1136
++#define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2
++#define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL 0x1137
++#define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2
++#define mmCRTC5_CRTC_GSL_VSYNC_GAP 0x1138
++#define mmCRTC5_CRTC_GSL_VSYNC_GAP_BASE_IDX 2
++#define mmCRTC5_CRTC_GSL_WINDOW 0x1139
++#define mmCRTC5_CRTC_GSL_WINDOW_BASE_IDX 2
++#define mmCRTC5_CRTC_GSL_CONTROL 0x113a
++#define mmCRTC5_CRTC_GSL_CONTROL_BASE_IDX 2
++#define mmCRTC5_CRTC_RANGE_TIMING_INT_STATUS 0x113d
++#define mmCRTC5_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2
++#define mmCRTC5_CRTC_DRR_CONTROL 0x113e
++#define mmCRTC5_CRTC_DRR_CONTROL_BASE_IDX 2
++
++
++// addressBlock: dce_dc_fmt5_dispdec
++// base address: 0x2800
++#define mmFMT5_FMT_CLAMP_COMPONENT_R 0x1142
++#define mmFMT5_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
++#define mmFMT5_FMT_CLAMP_COMPONENT_G 0x1143
++#define mmFMT5_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
++#define mmFMT5_FMT_CLAMP_COMPONENT_B 0x1144
++#define mmFMT5_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
++#define mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x1145
++#define mmFMT5_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
++#define mmFMT5_FMT_CONTROL 0x1146
++#define mmFMT5_FMT_CONTROL_BASE_IDX 2
++#define mmFMT5_FMT_BIT_DEPTH_CONTROL 0x1147
++#define mmFMT5_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
++#define mmFMT5_FMT_DITHER_RAND_R_SEED 0x1148
++#define mmFMT5_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
++#define mmFMT5_FMT_DITHER_RAND_G_SEED 0x1149
++#define mmFMT5_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
++#define mmFMT5_FMT_DITHER_RAND_B_SEED 0x114a
++#define mmFMT5_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
++#define mmFMT5_FMT_CLAMP_CNTL 0x114e
++#define mmFMT5_FMT_CLAMP_CNTL_BASE_IDX 2
++#define mmFMT5_FMT_CRC_CNTL 0x114f
++#define mmFMT5_FMT_CRC_CNTL_BASE_IDX 2
++#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK 0x1150
++#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
++#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1151
++#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
++#define mmFMT5_FMT_CRC_SIG_RED_GREEN 0x1152
++#define mmFMT5_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2
++#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL 0x1153
++#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2
++#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1154
++#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
++#define mmFMT5_FMT_420_HBLANK_EARLY_START 0x1155
++#define mmFMT5_FMT_420_HBLANK_EARLY_START_BASE_IDX 2
++
++
++// addressBlock: dce_dc_unp0_dispdec
++// base address: 0x0
++#define mmUNP0_UNP_GRPH_ENABLE 0x115a
++#define mmUNP0_UNP_GRPH_ENABLE_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_CONTROL 0x115b
++#define mmUNP0_UNP_GRPH_CONTROL_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_CONTROL_C 0x115c
++#define mmUNP0_UNP_GRPH_CONTROL_C_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_CONTROL_EXP 0x115d
++#define mmUNP0_UNP_GRPH_CONTROL_EXP_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_SWAP_CNTL 0x115e
++#define mmUNP0_UNP_GRPH_SWAP_CNTL_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L 0x115f
++#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C 0x1160
++#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L 0x1161
++#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x1162
++#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L 0x1163
++#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C 0x1164
++#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x1165
++#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x1166
++#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L 0x1167
++#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C 0x1168
++#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L 0x1169
++#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x116a
++#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L 0x116b
++#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C 0x116c
++#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x116d
++#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x116e
++#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_PITCH_L 0x116f
++#define mmUNP0_UNP_GRPH_PITCH_L_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_PITCH_C 0x1170
++#define mmUNP0_UNP_GRPH_PITCH_C_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_L 0x1171
++#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_L_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_C 0x1172
++#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_C_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_L 0x1173
++#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_L_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_C 0x1174
++#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_C_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_X_START_L 0x1175
++#define mmUNP0_UNP_GRPH_X_START_L_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_X_START_C 0x1176
++#define mmUNP0_UNP_GRPH_X_START_C_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_Y_START_L 0x1177
++#define mmUNP0_UNP_GRPH_Y_START_L_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_Y_START_C 0x1178
++#define mmUNP0_UNP_GRPH_Y_START_C_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_X_END_L 0x1179
++#define mmUNP0_UNP_GRPH_X_END_L_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_X_END_C 0x117a
++#define mmUNP0_UNP_GRPH_X_END_C_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_Y_END_L 0x117b
++#define mmUNP0_UNP_GRPH_Y_END_L_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_Y_END_C 0x117c
++#define mmUNP0_UNP_GRPH_Y_END_C_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_UPDATE 0x117d
++#define mmUNP0_UNP_GRPH_UPDATE_BASE_IDX 2
++#define mmUNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT 0x117e
++#define mmUNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L 0x117f
++#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C 0x1180
++#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L 0x1181
++#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C 0x1182
++#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_BASE_IDX 2
++#define mmUNP0_UNP_DVMM_PTE_CONTROL 0x1183
++#define mmUNP0_UNP_DVMM_PTE_CONTROL_BASE_IDX 2
++#define mmUNP0_UNP_DVMM_PTE_CONTROL_C 0x1184
++#define mmUNP0_UNP_DVMM_PTE_CONTROL_C_BASE_IDX 2
++#define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL 0x1185
++#define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL_BASE_IDX 2
++#define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL_C 0x1186
++#define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL_C_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_INTERRUPT_STATUS 0x1187
++#define mmUNP0_UNP_GRPH_INTERRUPT_STATUS_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_INTERRUPT_CONTROL 0x1188
++#define mmUNP0_UNP_GRPH_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmUNP0_UNP_GRPH_STEREOSYNC_FLIP 0x1189
++#define mmUNP0_UNP_GRPH_STEREOSYNC_FLIP_BASE_IDX 2
++#define mmUNP0_UNP_FLIP_CONTROL 0x118a
++#define mmUNP0_UNP_FLIP_CONTROL_BASE_IDX 2
++#define mmUNP0_UNP_CRC_CONTROL 0x118b
++#define mmUNP0_UNP_CRC_CONTROL_BASE_IDX 2
++#define mmUNP0_UNP_CRC_MASK 0x118c
++#define mmUNP0_UNP_CRC_MASK_BASE_IDX 2
++#define mmUNP0_UNP_CRC_CURRENT 0x118d
++#define mmUNP0_UNP_CRC_CURRENT_BASE_IDX 2
++#define mmUNP0_UNP_CRC_LAST 0x118e
++#define mmUNP0_UNP_CRC_LAST_BASE_IDX 2
++#define mmUNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK 0x118f
++#define mmUNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2
++#define mmUNP0_UNP_HW_ROTATION 0x1190
++#define mmUNP0_UNP_HW_ROTATION_BASE_IDX 2
++
++
++// addressBlock: dce_dc_lbv0_dispdec
++// base address: 0x0
++#define mmLBV0_LBV_DATA_FORMAT 0x1196
++#define mmLBV0_LBV_DATA_FORMAT_BASE_IDX 2
++#define mmLBV0_LBV_MEMORY_CTRL 0x1197
++#define mmLBV0_LBV_MEMORY_CTRL_BASE_IDX 2
++#define mmLBV0_LBV_MEMORY_SIZE_STATUS 0x1198
++#define mmLBV0_LBV_MEMORY_SIZE_STATUS_BASE_IDX 2
++#define mmLBV0_LBV_DESKTOP_HEIGHT 0x1199
++#define mmLBV0_LBV_DESKTOP_HEIGHT_BASE_IDX 2
++#define mmLBV0_LBV_VLINE_START_END 0x119a
++#define mmLBV0_LBV_VLINE_START_END_BASE_IDX 2
++#define mmLBV0_LBV_VLINE2_START_END 0x119b
++#define mmLBV0_LBV_VLINE2_START_END_BASE_IDX 2
++#define mmLBV0_LBV_V_COUNTER 0x119c
++#define mmLBV0_LBV_V_COUNTER_BASE_IDX 2
++#define mmLBV0_LBV_SNAPSHOT_V_COUNTER 0x119d
++#define mmLBV0_LBV_SNAPSHOT_V_COUNTER_BASE_IDX 2
++#define mmLBV0_LBV_V_COUNTER_CHROMA 0x119e
++#define mmLBV0_LBV_V_COUNTER_CHROMA_BASE_IDX 2
++#define mmLBV0_LBV_SNAPSHOT_V_COUNTER_CHROMA 0x119f
++#define mmLBV0_LBV_SNAPSHOT_V_COUNTER_CHROMA_BASE_IDX 2
++#define mmLBV0_LBV_INTERRUPT_MASK 0x11a0
++#define mmLBV0_LBV_INTERRUPT_MASK_BASE_IDX 2
++#define mmLBV0_LBV_VLINE_STATUS 0x11a1
++#define mmLBV0_LBV_VLINE_STATUS_BASE_IDX 2
++#define mmLBV0_LBV_VLINE2_STATUS 0x11a2
++#define mmLBV0_LBV_VLINE2_STATUS_BASE_IDX 2
++#define mmLBV0_LBV_VBLANK_STATUS 0x11a3
++#define mmLBV0_LBV_VBLANK_STATUS_BASE_IDX 2
++#define mmLBV0_LBV_SYNC_RESET_SEL 0x11a4
++#define mmLBV0_LBV_SYNC_RESET_SEL_BASE_IDX 2
++#define mmLBV0_LBV_BLACK_KEYER_R_CR 0x11a5
++#define mmLBV0_LBV_BLACK_KEYER_R_CR_BASE_IDX 2
++#define mmLBV0_LBV_BLACK_KEYER_G_Y 0x11a6
++#define mmLBV0_LBV_BLACK_KEYER_G_Y_BASE_IDX 2
++#define mmLBV0_LBV_BLACK_KEYER_B_CB 0x11a7
++#define mmLBV0_LBV_BLACK_KEYER_B_CB_BASE_IDX 2
++#define mmLBV0_LBV_KEYER_COLOR_CTRL 0x11a8
++#define mmLBV0_LBV_KEYER_COLOR_CTRL_BASE_IDX 2
++#define mmLBV0_LBV_KEYER_COLOR_R_CR 0x11a9
++#define mmLBV0_LBV_KEYER_COLOR_R_CR_BASE_IDX 2
++#define mmLBV0_LBV_KEYER_COLOR_G_Y 0x11aa
++#define mmLBV0_LBV_KEYER_COLOR_G_Y_BASE_IDX 2
++#define mmLBV0_LBV_KEYER_COLOR_B_CB 0x11ab
++#define mmLBV0_LBV_KEYER_COLOR_B_CB_BASE_IDX 2
++#define mmLBV0_LBV_KEYER_COLOR_REP_R_CR 0x11ac
++#define mmLBV0_LBV_KEYER_COLOR_REP_R_CR_BASE_IDX 2
++#define mmLBV0_LBV_KEYER_COLOR_REP_G_Y 0x11ad
++#define mmLBV0_LBV_KEYER_COLOR_REP_G_Y_BASE_IDX 2
++#define mmLBV0_LBV_KEYER_COLOR_REP_B_CB 0x11ae
++#define mmLBV0_LBV_KEYER_COLOR_REP_B_CB_BASE_IDX 2
++#define mmLBV0_LBV_BUFFER_LEVEL_STATUS 0x11af
++#define mmLBV0_LBV_BUFFER_LEVEL_STATUS_BASE_IDX 2
++#define mmLBV0_LBV_BUFFER_URGENCY_CTRL 0x11b0
++#define mmLBV0_LBV_BUFFER_URGENCY_CTRL_BASE_IDX 2
++#define mmLBV0_LBV_BUFFER_URGENCY_STATUS 0x11b1
++#define mmLBV0_LBV_BUFFER_URGENCY_STATUS_BASE_IDX 2
++#define mmLBV0_LBV_BUFFER_STATUS 0x11b2
++#define mmLBV0_LBV_BUFFER_STATUS_BASE_IDX 2
++#define mmLBV0_LBV_NO_OUTSTANDING_REQ_STATUS 0x11b3
++#define mmLBV0_LBV_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2
++
++
++// addressBlock: dce_dc_sclv0_dispdec
++// base address: 0x0
++#define mmSCLV0_SCLV_COEF_RAM_SELECT 0x11ca
++#define mmSCLV0_SCLV_COEF_RAM_SELECT_BASE_IDX 2
++#define mmSCLV0_SCLV_COEF_RAM_TAP_DATA 0x11cb
++#define mmSCLV0_SCLV_COEF_RAM_TAP_DATA_BASE_IDX 2
++#define mmSCLV0_SCLV_MODE 0x11cc
++#define mmSCLV0_SCLV_MODE_BASE_IDX 2
++#define mmSCLV0_SCLV_TAP_CONTROL 0x11cd
++#define mmSCLV0_SCLV_TAP_CONTROL_BASE_IDX 2
++#define mmSCLV0_SCLV_CONTROL 0x11ce
++#define mmSCLV0_SCLV_CONTROL_BASE_IDX 2
++#define mmSCLV0_SCLV_MANUAL_REPLICATE_CONTROL 0x11cf
++#define mmSCLV0_SCLV_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
++#define mmSCLV0_SCLV_AUTOMATIC_MODE_CONTROL 0x11d0
++#define mmSCLV0_SCLV_AUTOMATIC_MODE_CONTROL_BASE_IDX 2
++#define mmSCLV0_SCLV_HORZ_FILTER_CONTROL 0x11d1
++#define mmSCLV0_SCLV_HORZ_FILTER_CONTROL_BASE_IDX 2
++#define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO 0x11d2
++#define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
++#define mmSCLV0_SCLV_HORZ_FILTER_INIT 0x11d3
++#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BASE_IDX 2
++#define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_C 0x11d4
++#define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
++#define mmSCLV0_SCLV_HORZ_FILTER_INIT_C 0x11d5
++#define mmSCLV0_SCLV_HORZ_FILTER_INIT_C_BASE_IDX 2
++#define mmSCLV0_SCLV_VERT_FILTER_CONTROL 0x11d6
++#define mmSCLV0_SCLV_VERT_FILTER_CONTROL_BASE_IDX 2
++#define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO 0x11d7
++#define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
++#define mmSCLV0_SCLV_VERT_FILTER_INIT 0x11d8
++#define mmSCLV0_SCLV_VERT_FILTER_INIT_BASE_IDX 2
++#define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT 0x11d9
++#define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_BASE_IDX 2
++#define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_C 0x11da
++#define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
++#define mmSCLV0_SCLV_VERT_FILTER_INIT_C 0x11db
++#define mmSCLV0_SCLV_VERT_FILTER_INIT_C_BASE_IDX 2
++#define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_C 0x11dc
++#define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
++#define mmSCLV0_SCLV_ROUND_OFFSET 0x11dd
++#define mmSCLV0_SCLV_ROUND_OFFSET_BASE_IDX 2
++#define mmSCLV0_SCLV_UPDATE 0x11de
++#define mmSCLV0_SCLV_UPDATE_BASE_IDX 2
++#define mmSCLV0_SCLV_ALU_CONTROL 0x11df
++#define mmSCLV0_SCLV_ALU_CONTROL_BASE_IDX 2
++#define mmSCLV0_SCLV_VIEWPORT_START 0x11e0
++#define mmSCLV0_SCLV_VIEWPORT_START_BASE_IDX 2
++#define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY 0x11e1
++#define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_BASE_IDX 2
++#define mmSCLV0_SCLV_VIEWPORT_SIZE 0x11e2
++#define mmSCLV0_SCLV_VIEWPORT_SIZE_BASE_IDX 2
++#define mmSCLV0_SCLV_VIEWPORT_START_C 0x11e3
++#define mmSCLV0_SCLV_VIEWPORT_START_C_BASE_IDX 2
++#define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_C 0x11e4
++#define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_C_BASE_IDX 2
++#define mmSCLV0_SCLV_VIEWPORT_SIZE_C 0x11e5
++#define mmSCLV0_SCLV_VIEWPORT_SIZE_C_BASE_IDX 2
++#define mmSCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT 0x11e6
++#define mmSCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
++#define mmSCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM 0x11e7
++#define mmSCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
++#define mmSCLV0_SCLV_MODE_CHANGE_DET1 0x11e8
++#define mmSCLV0_SCLV_MODE_CHANGE_DET1_BASE_IDX 2
++#define mmSCLV0_SCLV_MODE_CHANGE_DET2 0x11e9
++#define mmSCLV0_SCLV_MODE_CHANGE_DET2_BASE_IDX 2
++#define mmSCLV0_SCLV_MODE_CHANGE_DET3 0x11ea
++#define mmSCLV0_SCLV_MODE_CHANGE_DET3_BASE_IDX 2
++#define mmSCLV0_SCLV_MODE_CHANGE_MASK 0x11eb
++#define mmSCLV0_SCLV_MODE_CHANGE_MASK_BASE_IDX 2
++#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT 0x11ec
++#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_BASE_IDX 2
++#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_C 0x11ed
++#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_C_BASE_IDX 2
++
++
++// addressBlock: dce_dc_col_man0_dispdec
++// base address: 0x0
++#define mmCOL_MAN0_COL_MAN_UPDATE 0x11fe
++#define mmCOL_MAN0_COL_MAN_UPDATE_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_INPUT_CSC_CONTROL 0x11ff
++#define mmCOL_MAN0_COL_MAN_INPUT_CSC_CONTROL_BASE_IDX 2
++#define mmCOL_MAN0_INPUT_CSC_C11_C12_A 0x1200
++#define mmCOL_MAN0_INPUT_CSC_C11_C12_A_BASE_IDX 2
++#define mmCOL_MAN0_INPUT_CSC_C13_C14_A 0x1201
++#define mmCOL_MAN0_INPUT_CSC_C13_C14_A_BASE_IDX 2
++#define mmCOL_MAN0_INPUT_CSC_C21_C22_A 0x1202
++#define mmCOL_MAN0_INPUT_CSC_C21_C22_A_BASE_IDX 2
++#define mmCOL_MAN0_INPUT_CSC_C23_C24_A 0x1203
++#define mmCOL_MAN0_INPUT_CSC_C23_C24_A_BASE_IDX 2
++#define mmCOL_MAN0_INPUT_CSC_C31_C32_A 0x1204
++#define mmCOL_MAN0_INPUT_CSC_C31_C32_A_BASE_IDX 2
++#define mmCOL_MAN0_INPUT_CSC_C33_C34_A 0x1205
++#define mmCOL_MAN0_INPUT_CSC_C33_C34_A_BASE_IDX 2
++#define mmCOL_MAN0_INPUT_CSC_C11_C12_B 0x1206
++#define mmCOL_MAN0_INPUT_CSC_C11_C12_B_BASE_IDX 2
++#define mmCOL_MAN0_INPUT_CSC_C13_C14_B 0x1207
++#define mmCOL_MAN0_INPUT_CSC_C13_C14_B_BASE_IDX 2
++#define mmCOL_MAN0_INPUT_CSC_C21_C22_B 0x1208
++#define mmCOL_MAN0_INPUT_CSC_C21_C22_B_BASE_IDX 2
++#define mmCOL_MAN0_INPUT_CSC_C23_C24_B 0x1209
++#define mmCOL_MAN0_INPUT_CSC_C23_C24_B_BASE_IDX 2
++#define mmCOL_MAN0_INPUT_CSC_C31_C32_B 0x120a
++#define mmCOL_MAN0_INPUT_CSC_C31_C32_B_BASE_IDX 2
++#define mmCOL_MAN0_INPUT_CSC_C33_C34_B 0x120b
++#define mmCOL_MAN0_INPUT_CSC_C33_C34_B_BASE_IDX 2
++#define mmCOL_MAN0_PRESCALE_CONTROL 0x120c
++#define mmCOL_MAN0_PRESCALE_CONTROL_BASE_IDX 2
++#define mmCOL_MAN0_PRESCALE_VALUES_R 0x120d
++#define mmCOL_MAN0_PRESCALE_VALUES_R_BASE_IDX 2
++#define mmCOL_MAN0_PRESCALE_VALUES_G 0x120e
++#define mmCOL_MAN0_PRESCALE_VALUES_G_BASE_IDX 2
++#define mmCOL_MAN0_PRESCALE_VALUES_B 0x120f
++#define mmCOL_MAN0_PRESCALE_VALUES_B_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_OUTPUT_CSC_CONTROL 0x1210
++#define mmCOL_MAN0_COL_MAN_OUTPUT_CSC_CONTROL_BASE_IDX 2
++#define mmCOL_MAN0_OUTPUT_CSC_C11_C12_A 0x1211
++#define mmCOL_MAN0_OUTPUT_CSC_C11_C12_A_BASE_IDX 2
++#define mmCOL_MAN0_OUTPUT_CSC_C13_C14_A 0x1212
++#define mmCOL_MAN0_OUTPUT_CSC_C13_C14_A_BASE_IDX 2
++#define mmCOL_MAN0_OUTPUT_CSC_C21_C22_A 0x1213
++#define mmCOL_MAN0_OUTPUT_CSC_C21_C22_A_BASE_IDX 2
++#define mmCOL_MAN0_OUTPUT_CSC_C23_C24_A 0x1214
++#define mmCOL_MAN0_OUTPUT_CSC_C23_C24_A_BASE_IDX 2
++#define mmCOL_MAN0_OUTPUT_CSC_C31_C32_A 0x1215
++#define mmCOL_MAN0_OUTPUT_CSC_C31_C32_A_BASE_IDX 2
++#define mmCOL_MAN0_OUTPUT_CSC_C33_C34_A 0x1216
++#define mmCOL_MAN0_OUTPUT_CSC_C33_C34_A_BASE_IDX 2
++#define mmCOL_MAN0_OUTPUT_CSC_C11_C12_B 0x1217
++#define mmCOL_MAN0_OUTPUT_CSC_C11_C12_B_BASE_IDX 2
++#define mmCOL_MAN0_OUTPUT_CSC_C13_C14_B 0x1218
++#define mmCOL_MAN0_OUTPUT_CSC_C13_C14_B_BASE_IDX 2
++#define mmCOL_MAN0_OUTPUT_CSC_C21_C22_B 0x1219
++#define mmCOL_MAN0_OUTPUT_CSC_C21_C22_B_BASE_IDX 2
++#define mmCOL_MAN0_OUTPUT_CSC_C23_C24_B 0x121a
++#define mmCOL_MAN0_OUTPUT_CSC_C23_C24_B_BASE_IDX 2
++#define mmCOL_MAN0_OUTPUT_CSC_C31_C32_B 0x121b
++#define mmCOL_MAN0_OUTPUT_CSC_C31_C32_B_BASE_IDX 2
++#define mmCOL_MAN0_OUTPUT_CSC_C33_C34_B 0x121c
++#define mmCOL_MAN0_OUTPUT_CSC_C33_C34_B_BASE_IDX 2
++#define mmCOL_MAN0_DENORM_CLAMP_CONTROL 0x121d
++#define mmCOL_MAN0_DENORM_CLAMP_CONTROL_BASE_IDX 2
++#define mmCOL_MAN0_DENORM_CLAMP_RANGE_R_CR 0x121e
++#define mmCOL_MAN0_DENORM_CLAMP_RANGE_R_CR_BASE_IDX 2
++#define mmCOL_MAN0_DENORM_CLAMP_RANGE_G_Y 0x121f
++#define mmCOL_MAN0_DENORM_CLAMP_RANGE_G_Y_BASE_IDX 2
++#define mmCOL_MAN0_DENORM_CLAMP_RANGE_B_CB 0x1220
++#define mmCOL_MAN0_DENORM_CLAMP_RANGE_B_CB_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_FP_CONVERTED_FIELD 0x1221
++#define mmCOL_MAN0_COL_MAN_FP_CONVERTED_FIELD_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CONTROL 0x1222
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CONTROL_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_INDEX 0x1223
++#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_INDEX_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_DATA 0x1224
++#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_DATA_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK 0x1225
++#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_START_CNTL 0x1226
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL 0x1227
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL1 0x1228
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL2 0x1229
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1 0x122a
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3 0x122b
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5 0x122c
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7 0x122d
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9 0x122e
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11 0x122f
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13 0x1230
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15 0x1231
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_START_CNTL 0x1232
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL 0x1233
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL1 0x1234
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL2 0x1235
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1 0x1236
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3 0x1237
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5 0x1238
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7 0x1239
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9 0x123a
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11 0x123b
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13 0x123c
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15 0x123d
++#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2
++#define mmCOL_MAN0_PACK_FIFO_ERROR 0x123e
++#define mmCOL_MAN0_PACK_FIFO_ERROR_BASE_IDX 2
++#define mmCOL_MAN0_OUTPUT_FIFO_ERROR 0x123f
++#define mmCOL_MAN0_OUTPUT_FIFO_ERROR_BASE_IDX 2
++#define mmCOL_MAN0_INPUT_GAMMA_LUT_AUTOFILL 0x1240
++#define mmCOL_MAN0_INPUT_GAMMA_LUT_AUTOFILL_BASE_IDX 2
++#define mmCOL_MAN0_INPUT_GAMMA_LUT_RW_INDEX 0x1241
++#define mmCOL_MAN0_INPUT_GAMMA_LUT_RW_INDEX_BASE_IDX 2
++#define mmCOL_MAN0_INPUT_GAMMA_LUT_SEQ_COLOR 0x1242
++#define mmCOL_MAN0_INPUT_GAMMA_LUT_SEQ_COLOR_BASE_IDX 2
++#define mmCOL_MAN0_INPUT_GAMMA_LUT_PWL_DATA 0x1243
++#define mmCOL_MAN0_INPUT_GAMMA_LUT_PWL_DATA_BASE_IDX 2
++#define mmCOL_MAN0_INPUT_GAMMA_LUT_30_COLOR 0x1244
++#define mmCOL_MAN0_INPUT_GAMMA_LUT_30_COLOR_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1 0x1245
++#define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2 0x1246
++#define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2_BASE_IDX 2
++#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_B 0x1247
++#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_B_BASE_IDX 2
++#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_G 0x1248
++#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_G_BASE_IDX 2
++#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_R 0x1249
++#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_R_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_DEGAMMA_CONTROL 0x124a
++#define mmCOL_MAN0_COL_MAN_DEGAMMA_CONTROL_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_CONTROL 0x124b
++#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_CONTROL_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C11_C12 0x124c
++#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C11_C12_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C13_C14 0x124d
++#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C13_C14_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C21_C22 0x124e
++#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C21_C22_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C23_C24 0x124f
++#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C23_C24_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C31_C32 0x1250
++#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C31_C32_BASE_IDX 2
++#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C33_C34 0x1251
++#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C33_C34_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dcfev0_dispdec
++// base address: 0x0
++#define mmDCFEV0_DCFEV_CLOCK_CONTROL 0x127e
++#define mmDCFEV0_DCFEV_CLOCK_CONTROL_BASE_IDX 2
++#define mmDCFEV0_DCFEV_SOFT_RESET 0x127f
++#define mmDCFEV0_DCFEV_SOFT_RESET_BASE_IDX 2
++#define mmDCFEV0_DCFEV_DMIFV_CLOCK_CONTROL 0x1280
++#define mmDCFEV0_DCFEV_DMIFV_CLOCK_CONTROL_BASE_IDX 2
++#define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL 0x1282
++#define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL_BASE_IDX 2
++#define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS 0x1283
++#define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS_BASE_IDX 2
++#define mmDCFEV0_DCFEV_MEM_PWR_CTRL 0x1284
++#define mmDCFEV0_DCFEV_MEM_PWR_CTRL_BASE_IDX 2
++#define mmDCFEV0_DCFEV_MEM_PWR_CTRL2 0x1285
++#define mmDCFEV0_DCFEV_MEM_PWR_CTRL2_BASE_IDX 2
++#define mmDCFEV0_DCFEV_MEM_PWR_STATUS 0x1286
++#define mmDCFEV0_DCFEV_MEM_PWR_STATUS_BASE_IDX 2
++#define mmDCFEV0_DCFEV_L_FLUSH 0x1287
++#define mmDCFEV0_DCFEV_L_FLUSH_BASE_IDX 2
++#define mmDCFEV0_DCFEV_C_FLUSH 0x1288
++#define mmDCFEV0_DCFEV_C_FLUSH_BASE_IDX 2
++#define mmDCFEV0_DCFEV_MISC 0x128a
++#define mmDCFEV0_DCFEV_MISC_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dc_perfmon11_dispdec
++// base address: 0x49c8
++#define mmDC_PERFMON11_PERFCOUNTER_CNTL 0x1292
++#define mmDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX 2
++#define mmDC_PERFMON11_PERFCOUNTER_CNTL2 0x1293
++#define mmDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX 2
++#define mmDC_PERFMON11_PERFCOUNTER_STATE 0x1294
++#define mmDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX 2
++#define mmDC_PERFMON11_PERFMON_CNTL 0x1295
++#define mmDC_PERFMON11_PERFMON_CNTL_BASE_IDX 2
++#define mmDC_PERFMON11_PERFMON_CNTL2 0x1296
++#define mmDC_PERFMON11_PERFMON_CNTL2_BASE_IDX 2
++#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x1297
++#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
++#define mmDC_PERFMON11_PERFMON_CVALUE_LOW 0x1298
++#define mmDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX 2
++#define mmDC_PERFMON11_PERFMON_HI 0x1299
++#define mmDC_PERFMON11_PERFMON_HI_BASE_IDX 2
++#define mmDC_PERFMON11_PERFMON_LOW 0x129a
++#define mmDC_PERFMON11_PERFMON_LOW_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dmifv_pg0_dispdec
++// base address: 0x0
++#define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1 0x129e
++#define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
++#define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2 0x129f
++#define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
++#define mmDMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL 0x12a0
++#define mmDMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL_BASE_IDX 2
++#define mmDMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL 0x12a1
++#define mmDMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL_BASE_IDX 2
++#define mmDMIFV_PG0_DPGV0_PIPE_DPM_CONTROL 0x12a2
++#define mmDMIFV_PG0_DPGV0_PIPE_DPM_CONTROL_BASE_IDX 2
++#define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL 0x12a3
++#define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_BASE_IDX 2
++#define mmDMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL 0x12a4
++#define mmDMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL_BASE_IDX 2
++#define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH 0x12a5
++#define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH_BASE_IDX 2
++#define mmDMIFV_PG0_DPGV0_REPEATER_PROGRAM 0x12a6
++#define mmDMIFV_PG0_DPGV0_REPEATER_PROGRAM_BASE_IDX 2
++#define mmDMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL 0x12aa
++#define mmDMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL_BASE_IDX 2
++#define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1 0x12ab
++#define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
++#define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2 0x12ac
++#define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
++#define mmDMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL 0x12ad
++#define mmDMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL_BASE_IDX 2
++#define mmDMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL 0x12ae
++#define mmDMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL_BASE_IDX 2
++#define mmDMIFV_PG0_DPGV1_PIPE_DPM_CONTROL 0x12af
++#define mmDMIFV_PG0_DPGV1_PIPE_DPM_CONTROL_BASE_IDX 2
++#define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL 0x12b0
++#define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_BASE_IDX 2
++#define mmDMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL 0x12b1
++#define mmDMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL_BASE_IDX 2
++#define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH 0x12b2
++#define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH_BASE_IDX 2
++#define mmDMIFV_PG0_DPGV1_REPEATER_PROGRAM 0x12b3
++#define mmDMIFV_PG0_DPGV1_REPEATER_PROGRAM_BASE_IDX 2
++#define mmDMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL 0x12b7
++#define mmDMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL_BASE_IDX 2
++
++
++// addressBlock: dce_dc_blndv0_dispdec
++// base address: 0x0
++#define mmBLNDV0_BLNDV_CONTROL 0x12db
++#define mmBLNDV0_BLNDV_CONTROL_BASE_IDX 2
++#define mmBLNDV0_BLNDV_SM_CONTROL2 0x12dc
++#define mmBLNDV0_BLNDV_SM_CONTROL2_BASE_IDX 2
++#define mmBLNDV0_BLNDV_CONTROL2 0x12dd
++#define mmBLNDV0_BLNDV_CONTROL2_BASE_IDX 2
++#define mmBLNDV0_BLNDV_UPDATE 0x12de
++#define mmBLNDV0_BLNDV_UPDATE_BASE_IDX 2
++#define mmBLNDV0_BLNDV_UNDERFLOW_INTERRUPT 0x12df
++#define mmBLNDV0_BLNDV_UNDERFLOW_INTERRUPT_BASE_IDX 2
++#define mmBLNDV0_BLNDV_V_UPDATE_LOCK 0x12e0
++#define mmBLNDV0_BLNDV_V_UPDATE_LOCK_BASE_IDX 2
++#define mmBLNDV0_BLNDV_REG_UPDATE_STATUS 0x12e1
++#define mmBLNDV0_BLNDV_REG_UPDATE_STATUS_BASE_IDX 2
++
++
++// addressBlock: dce_dc_crtcv0_dispdec
++// base address: 0x0
++#define mmCRTCV0_CRTCV_H_BLANK_EARLY_NUM 0x12e6
++#define mmCRTCV0_CRTCV_H_BLANK_EARLY_NUM_BASE_IDX 2
++#define mmCRTCV0_CRTCV_H_TOTAL 0x12e7
++#define mmCRTCV0_CRTCV_H_TOTAL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_H_BLANK_START_END 0x12e8
++#define mmCRTCV0_CRTCV_H_BLANK_START_END_BASE_IDX 2
++#define mmCRTCV0_CRTCV_H_SYNC_A 0x12e9
++#define mmCRTCV0_CRTCV_H_SYNC_A_BASE_IDX 2
++#define mmCRTCV0_CRTCV_H_SYNC_A_CNTL 0x12ea
++#define mmCRTCV0_CRTCV_H_SYNC_A_CNTL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_H_SYNC_B 0x12eb
++#define mmCRTCV0_CRTCV_H_SYNC_B_BASE_IDX 2
++#define mmCRTCV0_CRTCV_H_SYNC_B_CNTL 0x12ec
++#define mmCRTCV0_CRTCV_H_SYNC_B_CNTL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_VBI_END 0x12ed
++#define mmCRTCV0_CRTCV_VBI_END_BASE_IDX 2
++#define mmCRTCV0_CRTCV_V_TOTAL 0x12ee
++#define mmCRTCV0_CRTCV_V_TOTAL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_V_TOTAL_MIN 0x12ef
++#define mmCRTCV0_CRTCV_V_TOTAL_MIN_BASE_IDX 2
++#define mmCRTCV0_CRTCV_V_TOTAL_MAX 0x12f0
++#define mmCRTCV0_CRTCV_V_TOTAL_MAX_BASE_IDX 2
++#define mmCRTCV0_CRTCV_V_TOTAL_CONTROL 0x12f1
++#define mmCRTCV0_CRTCV_V_TOTAL_CONTROL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_V_TOTAL_INT_STATUS 0x12f2
++#define mmCRTCV0_CRTCV_V_TOTAL_INT_STATUS_BASE_IDX 2
++#define mmCRTCV0_CRTCV_VSYNC_NOM_INT_STATUS 0x12f3
++#define mmCRTCV0_CRTCV_VSYNC_NOM_INT_STATUS_BASE_IDX 2
++#define mmCRTCV0_CRTCV_V_BLANK_START_END 0x12f4
++#define mmCRTCV0_CRTCV_V_BLANK_START_END_BASE_IDX 2
++#define mmCRTCV0_CRTCV_V_SYNC_A 0x12f5
++#define mmCRTCV0_CRTCV_V_SYNC_A_BASE_IDX 2
++#define mmCRTCV0_CRTCV_V_SYNC_A_CNTL 0x12f6
++#define mmCRTCV0_CRTCV_V_SYNC_A_CNTL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_V_SYNC_B 0x12f7
++#define mmCRTCV0_CRTCV_V_SYNC_B_BASE_IDX 2
++#define mmCRTCV0_CRTCV_V_SYNC_B_CNTL 0x12f8
++#define mmCRTCV0_CRTCV_V_SYNC_B_CNTL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_DTMTEST_CNTL 0x12f9
++#define mmCRTCV0_CRTCV_DTMTEST_CNTL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_DTMTEST_STATUS_POSITION 0x12fa
++#define mmCRTCV0_CRTCV_DTMTEST_STATUS_POSITION_BASE_IDX 2
++#define mmCRTCV0_CRTCV_TRIGA_CNTL 0x12fb
++#define mmCRTCV0_CRTCV_TRIGA_CNTL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_TRIGA_MANUAL_TRIG 0x12fc
++#define mmCRTCV0_CRTCV_TRIGA_MANUAL_TRIG_BASE_IDX 2
++#define mmCRTCV0_CRTCV_TRIGB_CNTL 0x12fd
++#define mmCRTCV0_CRTCV_TRIGB_CNTL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_TRIGB_MANUAL_TRIG 0x12fe
++#define mmCRTCV0_CRTCV_TRIGB_MANUAL_TRIG_BASE_IDX 2
++#define mmCRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL 0x12ff
++#define mmCRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_FLOW_CONTROL 0x1300
++#define mmCRTCV0_CRTCV_FLOW_CONTROL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE 0x1301
++#define mmCRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
++#define mmCRTCV0_CRTCV_AVSYNC_COUNTER 0x1302
++#define mmCRTCV0_CRTCV_AVSYNC_COUNTER_BASE_IDX 2
++#define mmCRTCV0_CRTCV_CONTROL 0x1303
++#define mmCRTCV0_CRTCV_CONTROL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_BLANK_CONTROL 0x1304
++#define mmCRTCV0_CRTCV_BLANK_CONTROL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_INTERLACE_CONTROL 0x1305
++#define mmCRTCV0_CRTCV_INTERLACE_CONTROL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_INTERLACE_STATUS 0x1306
++#define mmCRTCV0_CRTCV_INTERLACE_STATUS_BASE_IDX 2
++#define mmCRTCV0_CRTCV_FIELD_INDICATION_CONTROL 0x1307
++#define mmCRTCV0_CRTCV_FIELD_INDICATION_CONTROL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK0 0x1308
++#define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK0_BASE_IDX 2
++#define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK1 0x1309
++#define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK1_BASE_IDX 2
++#define mmCRTCV0_CRTCV_STATUS 0x130a
++#define mmCRTCV0_CRTCV_STATUS_BASE_IDX 2
++#define mmCRTCV0_CRTCV_STATUS_POSITION 0x130b
++#define mmCRTCV0_CRTCV_STATUS_POSITION_BASE_IDX 2
++#define mmCRTCV0_CRTCV_NOM_VERT_POSITION 0x130c
++#define mmCRTCV0_CRTCV_NOM_VERT_POSITION_BASE_IDX 2
++#define mmCRTCV0_CRTCV_STATUS_FRAME_COUNT 0x130d
++#define mmCRTCV0_CRTCV_STATUS_FRAME_COUNT_BASE_IDX 2
++#define mmCRTCV0_CRTCV_STATUS_VF_COUNT 0x130e
++#define mmCRTCV0_CRTCV_STATUS_VF_COUNT_BASE_IDX 2
++#define mmCRTCV0_CRTCV_STATUS_HV_COUNT 0x130f
++#define mmCRTCV0_CRTCV_STATUS_HV_COUNT_BASE_IDX 2
++#define mmCRTCV0_CRTCV_COUNT_CONTROL 0x1310
++#define mmCRTCV0_CRTCV_COUNT_CONTROL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_COUNT_RESET 0x1311
++#define mmCRTCV0_CRTCV_COUNT_RESET_BASE_IDX 2
++#define mmCRTCV0_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1312
++#define mmCRTCV0_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
++#define mmCRTCV0_CRTCV_VERT_SYNC_CONTROL 0x1313
++#define mmCRTCV0_CRTCV_VERT_SYNC_CONTROL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_STEREO_STATUS 0x1314
++#define mmCRTCV0_CRTCV_STEREO_STATUS_BASE_IDX 2
++#define mmCRTCV0_CRTCV_STEREO_CONTROL 0x1315
++#define mmCRTCV0_CRTCV_STEREO_CONTROL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_SNAPSHOT_STATUS 0x1316
++#define mmCRTCV0_CRTCV_SNAPSHOT_STATUS_BASE_IDX 2
++#define mmCRTCV0_CRTCV_SNAPSHOT_CONTROL 0x1317
++#define mmCRTCV0_CRTCV_SNAPSHOT_CONTROL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_SNAPSHOT_POSITION 0x1318
++#define mmCRTCV0_CRTCV_SNAPSHOT_POSITION_BASE_IDX 2
++#define mmCRTCV0_CRTCV_SNAPSHOT_FRAME 0x1319
++#define mmCRTCV0_CRTCV_SNAPSHOT_FRAME_BASE_IDX 2
++#define mmCRTCV0_CRTCV_START_LINE_CONTROL 0x131a
++#define mmCRTCV0_CRTCV_START_LINE_CONTROL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_INTERRUPT_CONTROL 0x131b
++#define mmCRTCV0_CRTCV_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_UPDATE_LOCK 0x131c
++#define mmCRTCV0_CRTCV_UPDATE_LOCK_BASE_IDX 2
++#define mmCRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL 0x131d
++#define mmCRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_VGA_PARAMETER_CAPTURE_MODE 0x131e
++#define mmCRTCV0_CRTCV_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2
++#define mmCRTCV0_CRTCV_TEST_PATTERN_CONTROL 0x131f
++#define mmCRTCV0_CRTCV_TEST_PATTERN_CONTROL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_TEST_PATTERN_PARAMETERS 0x1320
++#define mmCRTCV0_CRTCV_TEST_PATTERN_PARAMETERS_BASE_IDX 2
++#define mmCRTCV0_CRTCV_TEST_PATTERN_COLOR 0x1321
++#define mmCRTCV0_CRTCV_TEST_PATTERN_COLOR_BASE_IDX 2
++#define mmCRTCV0_CRTCV_MASTER_UPDATE_LOCK 0x1322
++#define mmCRTCV0_CRTCV_MASTER_UPDATE_LOCK_BASE_IDX 2
++#define mmCRTCV0_CRTCV_MASTER_UPDATE_MODE 0x1323
++#define mmCRTCV0_CRTCV_MASTER_UPDATE_MODE_BASE_IDX 2
++#define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT 0x1324
++#define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_BASE_IDX 2
++#define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER 0x1325
++#define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2
++#define mmCRTCV0_CRTCV_MVP_STATUS 0x1326
++#define mmCRTCV0_CRTCV_MVP_STATUS_BASE_IDX 2
++#define mmCRTCV0_CRTCV_MASTER_EN 0x1327
++#define mmCRTCV0_CRTCV_MASTER_EN_BASE_IDX 2
++#define mmCRTCV0_CRTCV_ALLOW_STOP_OFF_V_CNT 0x1328
++#define mmCRTCV0_CRTCV_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2
++#define mmCRTCV0_CRTCV_V_UPDATE_INT_STATUS 0x1329
++#define mmCRTCV0_CRTCV_V_UPDATE_INT_STATUS_BASE_IDX 2
++#define mmCRTCV0_CRTCV_OVERSCAN_COLOR 0x132b
++#define mmCRTCV0_CRTCV_OVERSCAN_COLOR_BASE_IDX 2
++#define mmCRTCV0_CRTCV_OVERSCAN_COLOR_EXT 0x132c
++#define mmCRTCV0_CRTCV_OVERSCAN_COLOR_EXT_BASE_IDX 2
++#define mmCRTCV0_CRTCV_BLANK_DATA_COLOR 0x132d
++#define mmCRTCV0_CRTCV_BLANK_DATA_COLOR_BASE_IDX 2
++#define mmCRTCV0_CRTCV_BLANK_DATA_COLOR_EXT 0x132e
++#define mmCRTCV0_CRTCV_BLANK_DATA_COLOR_EXT_BASE_IDX 2
++#define mmCRTCV0_CRTCV_BLACK_COLOR 0x132f
++#define mmCRTCV0_CRTCV_BLACK_COLOR_BASE_IDX 2
++#define mmCRTCV0_CRTCV_BLACK_COLOR_EXT 0x1330
++#define mmCRTCV0_CRTCV_BLACK_COLOR_EXT_BASE_IDX 2
++#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_POSITION 0x1331
++#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
++#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL 0x1332
++#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_POSITION 0x1333
++#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
++#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL 0x1334
++#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_POSITION 0x1335
++#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
++#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL 0x1336
++#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_CRC_CNTL 0x1337
++#define mmCRTCV0_CRTCV_CRC_CNTL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL 0x1338
++#define mmCRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL 0x1339
++#define mmCRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL 0x133a
++#define mmCRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL 0x133b
++#define mmCRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_CRC0_DATA_RG 0x133c
++#define mmCRTCV0_CRTCV_CRC0_DATA_RG_BASE_IDX 2
++#define mmCRTCV0_CRTCV_CRC0_DATA_B 0x133d
++#define mmCRTCV0_CRTCV_CRC0_DATA_B_BASE_IDX 2
++#define mmCRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL 0x133e
++#define mmCRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL 0x133f
++#define mmCRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL 0x1340
++#define mmCRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL 0x1341
++#define mmCRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_CRC1_DATA_RG 0x1342
++#define mmCRTCV0_CRTCV_CRC1_DATA_RG_BASE_IDX 2
++#define mmCRTCV0_CRTCV_CRC1_DATA_B 0x1343
++#define mmCRTCV0_CRTCV_CRC1_DATA_B_BASE_IDX 2
++#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL 0x1344
++#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_START 0x1345
++#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2
++#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_END 0x1346
++#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2
++#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1347
++#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1348
++#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1349
++#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_STATIC_SCREEN_CONTROL 0x134a
++#define mmCRTCV0_CRTCV_STATIC_SCREEN_CONTROL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_3D_STRUCTURE_CONTROL 0x134b
++#define mmCRTCV0_CRTCV_3D_STRUCTURE_CONTROL_BASE_IDX 2
++#define mmCRTCV0_CRTCV_GSL_VSYNC_GAP 0x134c
++#define mmCRTCV0_CRTCV_GSL_VSYNC_GAP_BASE_IDX 2
++#define mmCRTCV0_CRTCV_GSL_WINDOW 0x134d
++#define mmCRTCV0_CRTCV_GSL_WINDOW_BASE_IDX 2
++#define mmCRTCV0_CRTCV_GSL_CONTROL 0x134e
++#define mmCRTCV0_CRTCV_GSL_CONTROL_BASE_IDX 2
++
++
++// addressBlock: dce_dc_unp1_dispdec
++// base address: 0x800
++#define mmUNP1_UNP_GRPH_ENABLE 0x135a
++#define mmUNP1_UNP_GRPH_ENABLE_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_CONTROL 0x135b
++#define mmUNP1_UNP_GRPH_CONTROL_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_CONTROL_C 0x135c
++#define mmUNP1_UNP_GRPH_CONTROL_C_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_CONTROL_EXP 0x135d
++#define mmUNP1_UNP_GRPH_CONTROL_EXP_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_SWAP_CNTL 0x135e
++#define mmUNP1_UNP_GRPH_SWAP_CNTL_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L 0x135f
++#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C 0x1360
++#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L 0x1361
++#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x1362
++#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L 0x1363
++#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C 0x1364
++#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x1365
++#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x1366
++#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L 0x1367
++#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C 0x1368
++#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L 0x1369
++#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x136a
++#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L 0x136b
++#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C 0x136c
++#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x136d
++#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x136e
++#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_PITCH_L 0x136f
++#define mmUNP1_UNP_GRPH_PITCH_L_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_PITCH_C 0x1370
++#define mmUNP1_UNP_GRPH_PITCH_C_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_L 0x1371
++#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_L_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_C 0x1372
++#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_C_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_L 0x1373
++#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_L_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_C 0x1374
++#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_C_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_X_START_L 0x1375
++#define mmUNP1_UNP_GRPH_X_START_L_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_X_START_C 0x1376
++#define mmUNP1_UNP_GRPH_X_START_C_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_Y_START_L 0x1377
++#define mmUNP1_UNP_GRPH_Y_START_L_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_Y_START_C 0x1378
++#define mmUNP1_UNP_GRPH_Y_START_C_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_X_END_L 0x1379
++#define mmUNP1_UNP_GRPH_X_END_L_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_X_END_C 0x137a
++#define mmUNP1_UNP_GRPH_X_END_C_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_Y_END_L 0x137b
++#define mmUNP1_UNP_GRPH_Y_END_L_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_Y_END_C 0x137c
++#define mmUNP1_UNP_GRPH_Y_END_C_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_UPDATE 0x137d
++#define mmUNP1_UNP_GRPH_UPDATE_BASE_IDX 2
++#define mmUNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT 0x137e
++#define mmUNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L 0x137f
++#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C 0x1380
++#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L 0x1381
++#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C 0x1382
++#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_BASE_IDX 2
++#define mmUNP1_UNP_DVMM_PTE_CONTROL 0x1383
++#define mmUNP1_UNP_DVMM_PTE_CONTROL_BASE_IDX 2
++#define mmUNP1_UNP_DVMM_PTE_CONTROL_C 0x1384
++#define mmUNP1_UNP_DVMM_PTE_CONTROL_C_BASE_IDX 2
++#define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL 0x1385
++#define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL_BASE_IDX 2
++#define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL_C 0x1386
++#define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL_C_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_INTERRUPT_STATUS 0x1387
++#define mmUNP1_UNP_GRPH_INTERRUPT_STATUS_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_INTERRUPT_CONTROL 0x1388
++#define mmUNP1_UNP_GRPH_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmUNP1_UNP_GRPH_STEREOSYNC_FLIP 0x1389
++#define mmUNP1_UNP_GRPH_STEREOSYNC_FLIP_BASE_IDX 2
++#define mmUNP1_UNP_FLIP_CONTROL 0x138a
++#define mmUNP1_UNP_FLIP_CONTROL_BASE_IDX 2
++#define mmUNP1_UNP_CRC_CONTROL 0x138b
++#define mmUNP1_UNP_CRC_CONTROL_BASE_IDX 2
++#define mmUNP1_UNP_CRC_MASK 0x138c
++#define mmUNP1_UNP_CRC_MASK_BASE_IDX 2
++#define mmUNP1_UNP_CRC_CURRENT 0x138d
++#define mmUNP1_UNP_CRC_CURRENT_BASE_IDX 2
++#define mmUNP1_UNP_CRC_LAST 0x138e
++#define mmUNP1_UNP_CRC_LAST_BASE_IDX 2
++#define mmUNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK 0x138f
++#define mmUNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2
++#define mmUNP1_UNP_HW_ROTATION 0x1390
++#define mmUNP1_UNP_HW_ROTATION_BASE_IDX 2
++
++
++// addressBlock: dce_dc_lbv1_dispdec
++// base address: 0x800
++#define mmLBV1_LBV_DATA_FORMAT 0x1396
++#define mmLBV1_LBV_DATA_FORMAT_BASE_IDX 2
++#define mmLBV1_LBV_MEMORY_CTRL 0x1397
++#define mmLBV1_LBV_MEMORY_CTRL_BASE_IDX 2
++#define mmLBV1_LBV_MEMORY_SIZE_STATUS 0x1398
++#define mmLBV1_LBV_MEMORY_SIZE_STATUS_BASE_IDX 2
++#define mmLBV1_LBV_DESKTOP_HEIGHT 0x1399
++#define mmLBV1_LBV_DESKTOP_HEIGHT_BASE_IDX 2
++#define mmLBV1_LBV_VLINE_START_END 0x139a
++#define mmLBV1_LBV_VLINE_START_END_BASE_IDX 2
++#define mmLBV1_LBV_VLINE2_START_END 0x139b
++#define mmLBV1_LBV_VLINE2_START_END_BASE_IDX 2
++#define mmLBV1_LBV_V_COUNTER 0x139c
++#define mmLBV1_LBV_V_COUNTER_BASE_IDX 2
++#define mmLBV1_LBV_SNAPSHOT_V_COUNTER 0x139d
++#define mmLBV1_LBV_SNAPSHOT_V_COUNTER_BASE_IDX 2
++#define mmLBV1_LBV_V_COUNTER_CHROMA 0x139e
++#define mmLBV1_LBV_V_COUNTER_CHROMA_BASE_IDX 2
++#define mmLBV1_LBV_SNAPSHOT_V_COUNTER_CHROMA 0x139f
++#define mmLBV1_LBV_SNAPSHOT_V_COUNTER_CHROMA_BASE_IDX 2
++#define mmLBV1_LBV_INTERRUPT_MASK 0x13a0
++#define mmLBV1_LBV_INTERRUPT_MASK_BASE_IDX 2
++#define mmLBV1_LBV_VLINE_STATUS 0x13a1
++#define mmLBV1_LBV_VLINE_STATUS_BASE_IDX 2
++#define mmLBV1_LBV_VLINE2_STATUS 0x13a2
++#define mmLBV1_LBV_VLINE2_STATUS_BASE_IDX 2
++#define mmLBV1_LBV_VBLANK_STATUS 0x13a3
++#define mmLBV1_LBV_VBLANK_STATUS_BASE_IDX 2
++#define mmLBV1_LBV_SYNC_RESET_SEL 0x13a4
++#define mmLBV1_LBV_SYNC_RESET_SEL_BASE_IDX 2
++#define mmLBV1_LBV_BLACK_KEYER_R_CR 0x13a5
++#define mmLBV1_LBV_BLACK_KEYER_R_CR_BASE_IDX 2
++#define mmLBV1_LBV_BLACK_KEYER_G_Y 0x13a6
++#define mmLBV1_LBV_BLACK_KEYER_G_Y_BASE_IDX 2
++#define mmLBV1_LBV_BLACK_KEYER_B_CB 0x13a7
++#define mmLBV1_LBV_BLACK_KEYER_B_CB_BASE_IDX 2
++#define mmLBV1_LBV_KEYER_COLOR_CTRL 0x13a8
++#define mmLBV1_LBV_KEYER_COLOR_CTRL_BASE_IDX 2
++#define mmLBV1_LBV_KEYER_COLOR_R_CR 0x13a9
++#define mmLBV1_LBV_KEYER_COLOR_R_CR_BASE_IDX 2
++#define mmLBV1_LBV_KEYER_COLOR_G_Y 0x13aa
++#define mmLBV1_LBV_KEYER_COLOR_G_Y_BASE_IDX 2
++#define mmLBV1_LBV_KEYER_COLOR_B_CB 0x13ab
++#define mmLBV1_LBV_KEYER_COLOR_B_CB_BASE_IDX 2
++#define mmLBV1_LBV_KEYER_COLOR_REP_R_CR 0x13ac
++#define mmLBV1_LBV_KEYER_COLOR_REP_R_CR_BASE_IDX 2
++#define mmLBV1_LBV_KEYER_COLOR_REP_G_Y 0x13ad
++#define mmLBV1_LBV_KEYER_COLOR_REP_G_Y_BASE_IDX 2
++#define mmLBV1_LBV_KEYER_COLOR_REP_B_CB 0x13ae
++#define mmLBV1_LBV_KEYER_COLOR_REP_B_CB_BASE_IDX 2
++#define mmLBV1_LBV_BUFFER_LEVEL_STATUS 0x13af
++#define mmLBV1_LBV_BUFFER_LEVEL_STATUS_BASE_IDX 2
++#define mmLBV1_LBV_BUFFER_URGENCY_CTRL 0x13b0
++#define mmLBV1_LBV_BUFFER_URGENCY_CTRL_BASE_IDX 2
++#define mmLBV1_LBV_BUFFER_URGENCY_STATUS 0x13b1
++#define mmLBV1_LBV_BUFFER_URGENCY_STATUS_BASE_IDX 2
++#define mmLBV1_LBV_BUFFER_STATUS 0x13b2
++#define mmLBV1_LBV_BUFFER_STATUS_BASE_IDX 2
++#define mmLBV1_LBV_NO_OUTSTANDING_REQ_STATUS 0x13b3
++#define mmLBV1_LBV_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2
++
++
++// addressBlock: dce_dc_sclv1_dispdec
++// base address: 0x800
++#define mmSCLV1_SCLV_COEF_RAM_SELECT 0x13ca
++#define mmSCLV1_SCLV_COEF_RAM_SELECT_BASE_IDX 2
++#define mmSCLV1_SCLV_COEF_RAM_TAP_DATA 0x13cb
++#define mmSCLV1_SCLV_COEF_RAM_TAP_DATA_BASE_IDX 2
++#define mmSCLV1_SCLV_MODE 0x13cc
++#define mmSCLV1_SCLV_MODE_BASE_IDX 2
++#define mmSCLV1_SCLV_TAP_CONTROL 0x13cd
++#define mmSCLV1_SCLV_TAP_CONTROL_BASE_IDX 2
++#define mmSCLV1_SCLV_CONTROL 0x13ce
++#define mmSCLV1_SCLV_CONTROL_BASE_IDX 2
++#define mmSCLV1_SCLV_MANUAL_REPLICATE_CONTROL 0x13cf
++#define mmSCLV1_SCLV_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
++#define mmSCLV1_SCLV_AUTOMATIC_MODE_CONTROL 0x13d0
++#define mmSCLV1_SCLV_AUTOMATIC_MODE_CONTROL_BASE_IDX 2
++#define mmSCLV1_SCLV_HORZ_FILTER_CONTROL 0x13d1
++#define mmSCLV1_SCLV_HORZ_FILTER_CONTROL_BASE_IDX 2
++#define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO 0x13d2
++#define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
++#define mmSCLV1_SCLV_HORZ_FILTER_INIT 0x13d3
++#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BASE_IDX 2
++#define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_C 0x13d4
++#define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
++#define mmSCLV1_SCLV_HORZ_FILTER_INIT_C 0x13d5
++#define mmSCLV1_SCLV_HORZ_FILTER_INIT_C_BASE_IDX 2
++#define mmSCLV1_SCLV_VERT_FILTER_CONTROL 0x13d6
++#define mmSCLV1_SCLV_VERT_FILTER_CONTROL_BASE_IDX 2
++#define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO 0x13d7
++#define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
++#define mmSCLV1_SCLV_VERT_FILTER_INIT 0x13d8
++#define mmSCLV1_SCLV_VERT_FILTER_INIT_BASE_IDX 2
++#define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT 0x13d9
++#define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_BASE_IDX 2
++#define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_C 0x13da
++#define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
++#define mmSCLV1_SCLV_VERT_FILTER_INIT_C 0x13db
++#define mmSCLV1_SCLV_VERT_FILTER_INIT_C_BASE_IDX 2
++#define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_C 0x13dc
++#define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
++#define mmSCLV1_SCLV_ROUND_OFFSET 0x13dd
++#define mmSCLV1_SCLV_ROUND_OFFSET_BASE_IDX 2
++#define mmSCLV1_SCLV_UPDATE 0x13de
++#define mmSCLV1_SCLV_UPDATE_BASE_IDX 2
++#define mmSCLV1_SCLV_ALU_CONTROL 0x13df
++#define mmSCLV1_SCLV_ALU_CONTROL_BASE_IDX 2
++#define mmSCLV1_SCLV_VIEWPORT_START 0x13e0
++#define mmSCLV1_SCLV_VIEWPORT_START_BASE_IDX 2
++#define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY 0x13e1
++#define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_BASE_IDX 2
++#define mmSCLV1_SCLV_VIEWPORT_SIZE 0x13e2
++#define mmSCLV1_SCLV_VIEWPORT_SIZE_BASE_IDX 2
++#define mmSCLV1_SCLV_VIEWPORT_START_C 0x13e3
++#define mmSCLV1_SCLV_VIEWPORT_START_C_BASE_IDX 2
++#define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_C 0x13e4
++#define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_C_BASE_IDX 2
++#define mmSCLV1_SCLV_VIEWPORT_SIZE_C 0x13e5
++#define mmSCLV1_SCLV_VIEWPORT_SIZE_C_BASE_IDX 2
++#define mmSCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT 0x13e6
++#define mmSCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
++#define mmSCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM 0x13e7
++#define mmSCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
++#define mmSCLV1_SCLV_MODE_CHANGE_DET1 0x13e8
++#define mmSCLV1_SCLV_MODE_CHANGE_DET1_BASE_IDX 2
++#define mmSCLV1_SCLV_MODE_CHANGE_DET2 0x13e9
++#define mmSCLV1_SCLV_MODE_CHANGE_DET2_BASE_IDX 2
++#define mmSCLV1_SCLV_MODE_CHANGE_DET3 0x13ea
++#define mmSCLV1_SCLV_MODE_CHANGE_DET3_BASE_IDX 2
++#define mmSCLV1_SCLV_MODE_CHANGE_MASK 0x13eb
++#define mmSCLV1_SCLV_MODE_CHANGE_MASK_BASE_IDX 2
++#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT 0x13ec
++#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_BASE_IDX 2
++#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_C 0x13ed
++#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_C_BASE_IDX 2
++
++
++// addressBlock: dce_dc_col_man1_dispdec
++// base address: 0x800
++#define mmCOL_MAN1_COL_MAN_UPDATE 0x13fe
++#define mmCOL_MAN1_COL_MAN_UPDATE_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_INPUT_CSC_CONTROL 0x13ff
++#define mmCOL_MAN1_COL_MAN_INPUT_CSC_CONTROL_BASE_IDX 2
++#define mmCOL_MAN1_INPUT_CSC_C11_C12_A 0x1400
++#define mmCOL_MAN1_INPUT_CSC_C11_C12_A_BASE_IDX 2
++#define mmCOL_MAN1_INPUT_CSC_C13_C14_A 0x1401
++#define mmCOL_MAN1_INPUT_CSC_C13_C14_A_BASE_IDX 2
++#define mmCOL_MAN1_INPUT_CSC_C21_C22_A 0x1402
++#define mmCOL_MAN1_INPUT_CSC_C21_C22_A_BASE_IDX 2
++#define mmCOL_MAN1_INPUT_CSC_C23_C24_A 0x1403
++#define mmCOL_MAN1_INPUT_CSC_C23_C24_A_BASE_IDX 2
++#define mmCOL_MAN1_INPUT_CSC_C31_C32_A 0x1404
++#define mmCOL_MAN1_INPUT_CSC_C31_C32_A_BASE_IDX 2
++#define mmCOL_MAN1_INPUT_CSC_C33_C34_A 0x1405
++#define mmCOL_MAN1_INPUT_CSC_C33_C34_A_BASE_IDX 2
++#define mmCOL_MAN1_INPUT_CSC_C11_C12_B 0x1406
++#define mmCOL_MAN1_INPUT_CSC_C11_C12_B_BASE_IDX 2
++#define mmCOL_MAN1_INPUT_CSC_C13_C14_B 0x1407
++#define mmCOL_MAN1_INPUT_CSC_C13_C14_B_BASE_IDX 2
++#define mmCOL_MAN1_INPUT_CSC_C21_C22_B 0x1408
++#define mmCOL_MAN1_INPUT_CSC_C21_C22_B_BASE_IDX 2
++#define mmCOL_MAN1_INPUT_CSC_C23_C24_B 0x1409
++#define mmCOL_MAN1_INPUT_CSC_C23_C24_B_BASE_IDX 2
++#define mmCOL_MAN1_INPUT_CSC_C31_C32_B 0x140a
++#define mmCOL_MAN1_INPUT_CSC_C31_C32_B_BASE_IDX 2
++#define mmCOL_MAN1_INPUT_CSC_C33_C34_B 0x140b
++#define mmCOL_MAN1_INPUT_CSC_C33_C34_B_BASE_IDX 2
++#define mmCOL_MAN1_PRESCALE_CONTROL 0x140c
++#define mmCOL_MAN1_PRESCALE_CONTROL_BASE_IDX 2
++#define mmCOL_MAN1_PRESCALE_VALUES_R 0x140d
++#define mmCOL_MAN1_PRESCALE_VALUES_R_BASE_IDX 2
++#define mmCOL_MAN1_PRESCALE_VALUES_G 0x140e
++#define mmCOL_MAN1_PRESCALE_VALUES_G_BASE_IDX 2
++#define mmCOL_MAN1_PRESCALE_VALUES_B 0x140f
++#define mmCOL_MAN1_PRESCALE_VALUES_B_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_OUTPUT_CSC_CONTROL 0x1410
++#define mmCOL_MAN1_COL_MAN_OUTPUT_CSC_CONTROL_BASE_IDX 2
++#define mmCOL_MAN1_OUTPUT_CSC_C11_C12_A 0x1411
++#define mmCOL_MAN1_OUTPUT_CSC_C11_C12_A_BASE_IDX 2
++#define mmCOL_MAN1_OUTPUT_CSC_C13_C14_A 0x1412
++#define mmCOL_MAN1_OUTPUT_CSC_C13_C14_A_BASE_IDX 2
++#define mmCOL_MAN1_OUTPUT_CSC_C21_C22_A 0x1413
++#define mmCOL_MAN1_OUTPUT_CSC_C21_C22_A_BASE_IDX 2
++#define mmCOL_MAN1_OUTPUT_CSC_C23_C24_A 0x1414
++#define mmCOL_MAN1_OUTPUT_CSC_C23_C24_A_BASE_IDX 2
++#define mmCOL_MAN1_OUTPUT_CSC_C31_C32_A 0x1415
++#define mmCOL_MAN1_OUTPUT_CSC_C31_C32_A_BASE_IDX 2
++#define mmCOL_MAN1_OUTPUT_CSC_C33_C34_A 0x1416
++#define mmCOL_MAN1_OUTPUT_CSC_C33_C34_A_BASE_IDX 2
++#define mmCOL_MAN1_OUTPUT_CSC_C11_C12_B 0x1417
++#define mmCOL_MAN1_OUTPUT_CSC_C11_C12_B_BASE_IDX 2
++#define mmCOL_MAN1_OUTPUT_CSC_C13_C14_B 0x1418
++#define mmCOL_MAN1_OUTPUT_CSC_C13_C14_B_BASE_IDX 2
++#define mmCOL_MAN1_OUTPUT_CSC_C21_C22_B 0x1419
++#define mmCOL_MAN1_OUTPUT_CSC_C21_C22_B_BASE_IDX 2
++#define mmCOL_MAN1_OUTPUT_CSC_C23_C24_B 0x141a
++#define mmCOL_MAN1_OUTPUT_CSC_C23_C24_B_BASE_IDX 2
++#define mmCOL_MAN1_OUTPUT_CSC_C31_C32_B 0x141b
++#define mmCOL_MAN1_OUTPUT_CSC_C31_C32_B_BASE_IDX 2
++#define mmCOL_MAN1_OUTPUT_CSC_C33_C34_B 0x141c
++#define mmCOL_MAN1_OUTPUT_CSC_C33_C34_B_BASE_IDX 2
++#define mmCOL_MAN1_DENORM_CLAMP_CONTROL 0x141d
++#define mmCOL_MAN1_DENORM_CLAMP_CONTROL_BASE_IDX 2
++#define mmCOL_MAN1_DENORM_CLAMP_RANGE_R_CR 0x141e
++#define mmCOL_MAN1_DENORM_CLAMP_RANGE_R_CR_BASE_IDX 2
++#define mmCOL_MAN1_DENORM_CLAMP_RANGE_G_Y 0x141f
++#define mmCOL_MAN1_DENORM_CLAMP_RANGE_G_Y_BASE_IDX 2
++#define mmCOL_MAN1_DENORM_CLAMP_RANGE_B_CB 0x1420
++#define mmCOL_MAN1_DENORM_CLAMP_RANGE_B_CB_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_FP_CONVERTED_FIELD 0x1421
++#define mmCOL_MAN1_COL_MAN_FP_CONVERTED_FIELD_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CONTROL 0x1422
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CONTROL_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_INDEX 0x1423
++#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_INDEX_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_DATA 0x1424
++#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_DATA_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK 0x1425
++#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_START_CNTL 0x1426
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL 0x1427
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL1 0x1428
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL2 0x1429
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1 0x142a
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3 0x142b
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5 0x142c
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7 0x142d
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9 0x142e
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11 0x142f
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13 0x1430
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15 0x1431
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_START_CNTL 0x1432
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL 0x1433
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL1 0x1434
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL2 0x1435
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1 0x1436
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3 0x1437
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5 0x1438
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7 0x1439
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9 0x143a
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11 0x143b
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13 0x143c
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15 0x143d
++#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2
++#define mmCOL_MAN1_PACK_FIFO_ERROR 0x143e
++#define mmCOL_MAN1_PACK_FIFO_ERROR_BASE_IDX 2
++#define mmCOL_MAN1_OUTPUT_FIFO_ERROR 0x143f
++#define mmCOL_MAN1_OUTPUT_FIFO_ERROR_BASE_IDX 2
++#define mmCOL_MAN1_INPUT_GAMMA_LUT_AUTOFILL 0x1440
++#define mmCOL_MAN1_INPUT_GAMMA_LUT_AUTOFILL_BASE_IDX 2
++#define mmCOL_MAN1_INPUT_GAMMA_LUT_RW_INDEX 0x1441
++#define mmCOL_MAN1_INPUT_GAMMA_LUT_RW_INDEX_BASE_IDX 2
++#define mmCOL_MAN1_INPUT_GAMMA_LUT_SEQ_COLOR 0x1442
++#define mmCOL_MAN1_INPUT_GAMMA_LUT_SEQ_COLOR_BASE_IDX 2
++#define mmCOL_MAN1_INPUT_GAMMA_LUT_PWL_DATA 0x1443
++#define mmCOL_MAN1_INPUT_GAMMA_LUT_PWL_DATA_BASE_IDX 2
++#define mmCOL_MAN1_INPUT_GAMMA_LUT_30_COLOR 0x1444
++#define mmCOL_MAN1_INPUT_GAMMA_LUT_30_COLOR_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1 0x1445
++#define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2 0x1446
++#define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2_BASE_IDX 2
++#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_B 0x1447
++#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_B_BASE_IDX 2
++#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_G 0x1448
++#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_G_BASE_IDX 2
++#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_R 0x1449
++#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_R_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_DEGAMMA_CONTROL 0x144a
++#define mmCOL_MAN1_COL_MAN_DEGAMMA_CONTROL_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_CONTROL 0x144b
++#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_CONTROL_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C11_C12 0x144c
++#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C11_C12_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C13_C14 0x144d
++#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C13_C14_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C21_C22 0x144e
++#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C21_C22_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C23_C24 0x144f
++#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C23_C24_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C31_C32 0x1450
++#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C31_C32_BASE_IDX 2
++#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C33_C34 0x1451
++#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C33_C34_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dcfev1_dispdec
++// base address: 0x800
++#define mmDCFEV1_DCFEV_CLOCK_CONTROL 0x147e
++#define mmDCFEV1_DCFEV_CLOCK_CONTROL_BASE_IDX 2
++#define mmDCFEV1_DCFEV_SOFT_RESET 0x147f
++#define mmDCFEV1_DCFEV_SOFT_RESET_BASE_IDX 2
++#define mmDCFEV1_DCFEV_DMIFV_CLOCK_CONTROL 0x1480
++#define mmDCFEV1_DCFEV_DMIFV_CLOCK_CONTROL_BASE_IDX 2
++#define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL 0x1482
++#define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL_BASE_IDX 2
++#define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS 0x1483
++#define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS_BASE_IDX 2
++#define mmDCFEV1_DCFEV_MEM_PWR_CTRL 0x1484
++#define mmDCFEV1_DCFEV_MEM_PWR_CTRL_BASE_IDX 2
++#define mmDCFEV1_DCFEV_MEM_PWR_CTRL2 0x1485
++#define mmDCFEV1_DCFEV_MEM_PWR_CTRL2_BASE_IDX 2
++#define mmDCFEV1_DCFEV_MEM_PWR_STATUS 0x1486
++#define mmDCFEV1_DCFEV_MEM_PWR_STATUS_BASE_IDX 2
++#define mmDCFEV1_DCFEV_L_FLUSH 0x1487
++#define mmDCFEV1_DCFEV_L_FLUSH_BASE_IDX 2
++#define mmDCFEV1_DCFEV_C_FLUSH 0x1488
++#define mmDCFEV1_DCFEV_C_FLUSH_BASE_IDX 2
++#define mmDCFEV1_DCFEV_MISC 0x148a
++#define mmDCFEV1_DCFEV_MISC_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dc_perfmon12_dispdec
++// base address: 0x51c8
++#define mmDC_PERFMON12_PERFCOUNTER_CNTL 0x1492
++#define mmDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX 2
++#define mmDC_PERFMON12_PERFCOUNTER_CNTL2 0x1493
++#define mmDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX 2
++#define mmDC_PERFMON12_PERFCOUNTER_STATE 0x1494
++#define mmDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX 2
++#define mmDC_PERFMON12_PERFMON_CNTL 0x1495
++#define mmDC_PERFMON12_PERFMON_CNTL_BASE_IDX 2
++#define mmDC_PERFMON12_PERFMON_CNTL2 0x1496
++#define mmDC_PERFMON12_PERFMON_CNTL2_BASE_IDX 2
++#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0x1497
++#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
++#define mmDC_PERFMON12_PERFMON_CVALUE_LOW 0x1498
++#define mmDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX 2
++#define mmDC_PERFMON12_PERFMON_HI 0x1499
++#define mmDC_PERFMON12_PERFMON_HI_BASE_IDX 2
++#define mmDC_PERFMON12_PERFMON_LOW 0x149a
++#define mmDC_PERFMON12_PERFMON_LOW_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dmifv_pg1_dispdec
++// base address: 0x800
++#define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1 0x149e
++#define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
++#define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2 0x149f
++#define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
++#define mmDMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL 0x14a0
++#define mmDMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL_BASE_IDX 2
++#define mmDMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL 0x14a1
++#define mmDMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL_BASE_IDX 2
++#define mmDMIFV_PG1_DPGV0_PIPE_DPM_CONTROL 0x14a2
++#define mmDMIFV_PG1_DPGV0_PIPE_DPM_CONTROL_BASE_IDX 2
++#define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL 0x14a3
++#define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_BASE_IDX 2
++#define mmDMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL 0x14a4
++#define mmDMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL_BASE_IDX 2
++#define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH 0x14a5
++#define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH_BASE_IDX 2
++#define mmDMIFV_PG1_DPGV0_REPEATER_PROGRAM 0x14a6
++#define mmDMIFV_PG1_DPGV0_REPEATER_PROGRAM_BASE_IDX 2
++#define mmDMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL 0x14aa
++#define mmDMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL_BASE_IDX 2
++#define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1 0x14ab
++#define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
++#define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2 0x14ac
++#define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
++#define mmDMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL 0x14ad
++#define mmDMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL_BASE_IDX 2
++#define mmDMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL 0x14ae
++#define mmDMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL_BASE_IDX 2
++#define mmDMIFV_PG1_DPGV1_PIPE_DPM_CONTROL 0x14af
++#define mmDMIFV_PG1_DPGV1_PIPE_DPM_CONTROL_BASE_IDX 2
++#define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL 0x14b0
++#define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_BASE_IDX 2
++#define mmDMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL 0x14b1
++#define mmDMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL_BASE_IDX 2
++#define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH 0x14b2
++#define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH_BASE_IDX 2
++#define mmDMIFV_PG1_DPGV1_REPEATER_PROGRAM 0x14b3
++#define mmDMIFV_PG1_DPGV1_REPEATER_PROGRAM_BASE_IDX 2
++#define mmDMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL 0x14b7
++#define mmDMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL_BASE_IDX 2
++
++
++// addressBlock: dce_dc_blndv1_dispdec
++// base address: 0x800
++#define mmBLNDV1_BLNDV_CONTROL 0x14db
++#define mmBLNDV1_BLNDV_CONTROL_BASE_IDX 2
++#define mmBLNDV1_BLNDV_SM_CONTROL2 0x14dc
++#define mmBLNDV1_BLNDV_SM_CONTROL2_BASE_IDX 2
++#define mmBLNDV1_BLNDV_CONTROL2 0x14dd
++#define mmBLNDV1_BLNDV_CONTROL2_BASE_IDX 2
++#define mmBLNDV1_BLNDV_UPDATE 0x14de
++#define mmBLNDV1_BLNDV_UPDATE_BASE_IDX 2
++#define mmBLNDV1_BLNDV_UNDERFLOW_INTERRUPT 0x14df
++#define mmBLNDV1_BLNDV_UNDERFLOW_INTERRUPT_BASE_IDX 2
++#define mmBLNDV1_BLNDV_V_UPDATE_LOCK 0x14e0
++#define mmBLNDV1_BLNDV_V_UPDATE_LOCK_BASE_IDX 2
++#define mmBLNDV1_BLNDV_REG_UPDATE_STATUS 0x14e1
++#define mmBLNDV1_BLNDV_REG_UPDATE_STATUS_BASE_IDX 2
++
++
++// addressBlock: dce_dc_crtcv1_dispdec
++// base address: 0x800
++#define mmCRTCV1_CRTCV_H_BLANK_EARLY_NUM 0x14e6
++#define mmCRTCV1_CRTCV_H_BLANK_EARLY_NUM_BASE_IDX 2
++#define mmCRTCV1_CRTCV_H_TOTAL 0x14e7
++#define mmCRTCV1_CRTCV_H_TOTAL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_H_BLANK_START_END 0x14e8
++#define mmCRTCV1_CRTCV_H_BLANK_START_END_BASE_IDX 2
++#define mmCRTCV1_CRTCV_H_SYNC_A 0x14e9
++#define mmCRTCV1_CRTCV_H_SYNC_A_BASE_IDX 2
++#define mmCRTCV1_CRTCV_H_SYNC_A_CNTL 0x14ea
++#define mmCRTCV1_CRTCV_H_SYNC_A_CNTL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_H_SYNC_B 0x14eb
++#define mmCRTCV1_CRTCV_H_SYNC_B_BASE_IDX 2
++#define mmCRTCV1_CRTCV_H_SYNC_B_CNTL 0x14ec
++#define mmCRTCV1_CRTCV_H_SYNC_B_CNTL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_VBI_END 0x14ed
++#define mmCRTCV1_CRTCV_VBI_END_BASE_IDX 2
++#define mmCRTCV1_CRTCV_V_TOTAL 0x14ee
++#define mmCRTCV1_CRTCV_V_TOTAL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_V_TOTAL_MIN 0x14ef
++#define mmCRTCV1_CRTCV_V_TOTAL_MIN_BASE_IDX 2
++#define mmCRTCV1_CRTCV_V_TOTAL_MAX 0x14f0
++#define mmCRTCV1_CRTCV_V_TOTAL_MAX_BASE_IDX 2
++#define mmCRTCV1_CRTCV_V_TOTAL_CONTROL 0x14f1
++#define mmCRTCV1_CRTCV_V_TOTAL_CONTROL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_V_TOTAL_INT_STATUS 0x14f2
++#define mmCRTCV1_CRTCV_V_TOTAL_INT_STATUS_BASE_IDX 2
++#define mmCRTCV1_CRTCV_VSYNC_NOM_INT_STATUS 0x14f3
++#define mmCRTCV1_CRTCV_VSYNC_NOM_INT_STATUS_BASE_IDX 2
++#define mmCRTCV1_CRTCV_V_BLANK_START_END 0x14f4
++#define mmCRTCV1_CRTCV_V_BLANK_START_END_BASE_IDX 2
++#define mmCRTCV1_CRTCV_V_SYNC_A 0x14f5
++#define mmCRTCV1_CRTCV_V_SYNC_A_BASE_IDX 2
++#define mmCRTCV1_CRTCV_V_SYNC_A_CNTL 0x14f6
++#define mmCRTCV1_CRTCV_V_SYNC_A_CNTL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_V_SYNC_B 0x14f7
++#define mmCRTCV1_CRTCV_V_SYNC_B_BASE_IDX 2
++#define mmCRTCV1_CRTCV_V_SYNC_B_CNTL 0x14f8
++#define mmCRTCV1_CRTCV_V_SYNC_B_CNTL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_DTMTEST_CNTL 0x14f9
++#define mmCRTCV1_CRTCV_DTMTEST_CNTL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_DTMTEST_STATUS_POSITION 0x14fa
++#define mmCRTCV1_CRTCV_DTMTEST_STATUS_POSITION_BASE_IDX 2
++#define mmCRTCV1_CRTCV_TRIGA_CNTL 0x14fb
++#define mmCRTCV1_CRTCV_TRIGA_CNTL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_TRIGA_MANUAL_TRIG 0x14fc
++#define mmCRTCV1_CRTCV_TRIGA_MANUAL_TRIG_BASE_IDX 2
++#define mmCRTCV1_CRTCV_TRIGB_CNTL 0x14fd
++#define mmCRTCV1_CRTCV_TRIGB_CNTL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_TRIGB_MANUAL_TRIG 0x14fe
++#define mmCRTCV1_CRTCV_TRIGB_MANUAL_TRIG_BASE_IDX 2
++#define mmCRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL 0x14ff
++#define mmCRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_FLOW_CONTROL 0x1500
++#define mmCRTCV1_CRTCV_FLOW_CONTROL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE 0x1501
++#define mmCRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
++#define mmCRTCV1_CRTCV_AVSYNC_COUNTER 0x1502
++#define mmCRTCV1_CRTCV_AVSYNC_COUNTER_BASE_IDX 2
++#define mmCRTCV1_CRTCV_CONTROL 0x1503
++#define mmCRTCV1_CRTCV_CONTROL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_BLANK_CONTROL 0x1504
++#define mmCRTCV1_CRTCV_BLANK_CONTROL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_INTERLACE_CONTROL 0x1505
++#define mmCRTCV1_CRTCV_INTERLACE_CONTROL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_INTERLACE_STATUS 0x1506
++#define mmCRTCV1_CRTCV_INTERLACE_STATUS_BASE_IDX 2
++#define mmCRTCV1_CRTCV_FIELD_INDICATION_CONTROL 0x1507
++#define mmCRTCV1_CRTCV_FIELD_INDICATION_CONTROL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK0 0x1508
++#define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK0_BASE_IDX 2
++#define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK1 0x1509
++#define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK1_BASE_IDX 2
++#define mmCRTCV1_CRTCV_STATUS 0x150a
++#define mmCRTCV1_CRTCV_STATUS_BASE_IDX 2
++#define mmCRTCV1_CRTCV_STATUS_POSITION 0x150b
++#define mmCRTCV1_CRTCV_STATUS_POSITION_BASE_IDX 2
++#define mmCRTCV1_CRTCV_NOM_VERT_POSITION 0x150c
++#define mmCRTCV1_CRTCV_NOM_VERT_POSITION_BASE_IDX 2
++#define mmCRTCV1_CRTCV_STATUS_FRAME_COUNT 0x150d
++#define mmCRTCV1_CRTCV_STATUS_FRAME_COUNT_BASE_IDX 2
++#define mmCRTCV1_CRTCV_STATUS_VF_COUNT 0x150e
++#define mmCRTCV1_CRTCV_STATUS_VF_COUNT_BASE_IDX 2
++#define mmCRTCV1_CRTCV_STATUS_HV_COUNT 0x150f
++#define mmCRTCV1_CRTCV_STATUS_HV_COUNT_BASE_IDX 2
++#define mmCRTCV1_CRTCV_COUNT_CONTROL 0x1510
++#define mmCRTCV1_CRTCV_COUNT_CONTROL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_COUNT_RESET 0x1511
++#define mmCRTCV1_CRTCV_COUNT_RESET_BASE_IDX 2
++#define mmCRTCV1_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1512
++#define mmCRTCV1_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
++#define mmCRTCV1_CRTCV_VERT_SYNC_CONTROL 0x1513
++#define mmCRTCV1_CRTCV_VERT_SYNC_CONTROL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_STEREO_STATUS 0x1514
++#define mmCRTCV1_CRTCV_STEREO_STATUS_BASE_IDX 2
++#define mmCRTCV1_CRTCV_STEREO_CONTROL 0x1515
++#define mmCRTCV1_CRTCV_STEREO_CONTROL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_SNAPSHOT_STATUS 0x1516
++#define mmCRTCV1_CRTCV_SNAPSHOT_STATUS_BASE_IDX 2
++#define mmCRTCV1_CRTCV_SNAPSHOT_CONTROL 0x1517
++#define mmCRTCV1_CRTCV_SNAPSHOT_CONTROL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_SNAPSHOT_POSITION 0x1518
++#define mmCRTCV1_CRTCV_SNAPSHOT_POSITION_BASE_IDX 2
++#define mmCRTCV1_CRTCV_SNAPSHOT_FRAME 0x1519
++#define mmCRTCV1_CRTCV_SNAPSHOT_FRAME_BASE_IDX 2
++#define mmCRTCV1_CRTCV_START_LINE_CONTROL 0x151a
++#define mmCRTCV1_CRTCV_START_LINE_CONTROL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_INTERRUPT_CONTROL 0x151b
++#define mmCRTCV1_CRTCV_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_UPDATE_LOCK 0x151c
++#define mmCRTCV1_CRTCV_UPDATE_LOCK_BASE_IDX 2
++#define mmCRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL 0x151d
++#define mmCRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_VGA_PARAMETER_CAPTURE_MODE 0x151e
++#define mmCRTCV1_CRTCV_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2
++#define mmCRTCV1_CRTCV_TEST_PATTERN_CONTROL 0x151f
++#define mmCRTCV1_CRTCV_TEST_PATTERN_CONTROL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_TEST_PATTERN_PARAMETERS 0x1520
++#define mmCRTCV1_CRTCV_TEST_PATTERN_PARAMETERS_BASE_IDX 2
++#define mmCRTCV1_CRTCV_TEST_PATTERN_COLOR 0x1521
++#define mmCRTCV1_CRTCV_TEST_PATTERN_COLOR_BASE_IDX 2
++#define mmCRTCV1_CRTCV_MASTER_UPDATE_LOCK 0x1522
++#define mmCRTCV1_CRTCV_MASTER_UPDATE_LOCK_BASE_IDX 2
++#define mmCRTCV1_CRTCV_MASTER_UPDATE_MODE 0x1523
++#define mmCRTCV1_CRTCV_MASTER_UPDATE_MODE_BASE_IDX 2
++#define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT 0x1524
++#define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_BASE_IDX 2
++#define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER 0x1525
++#define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2
++#define mmCRTCV1_CRTCV_MVP_STATUS 0x1526
++#define mmCRTCV1_CRTCV_MVP_STATUS_BASE_IDX 2
++#define mmCRTCV1_CRTCV_MASTER_EN 0x1527
++#define mmCRTCV1_CRTCV_MASTER_EN_BASE_IDX 2
++#define mmCRTCV1_CRTCV_ALLOW_STOP_OFF_V_CNT 0x1528
++#define mmCRTCV1_CRTCV_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2
++#define mmCRTCV1_CRTCV_V_UPDATE_INT_STATUS 0x1529
++#define mmCRTCV1_CRTCV_V_UPDATE_INT_STATUS_BASE_IDX 2
++#define mmCRTCV1_CRTCV_OVERSCAN_COLOR 0x152b
++#define mmCRTCV1_CRTCV_OVERSCAN_COLOR_BASE_IDX 2
++#define mmCRTCV1_CRTCV_OVERSCAN_COLOR_EXT 0x152c
++#define mmCRTCV1_CRTCV_OVERSCAN_COLOR_EXT_BASE_IDX 2
++#define mmCRTCV1_CRTCV_BLANK_DATA_COLOR 0x152d
++#define mmCRTCV1_CRTCV_BLANK_DATA_COLOR_BASE_IDX 2
++#define mmCRTCV1_CRTCV_BLANK_DATA_COLOR_EXT 0x152e
++#define mmCRTCV1_CRTCV_BLANK_DATA_COLOR_EXT_BASE_IDX 2
++#define mmCRTCV1_CRTCV_BLACK_COLOR 0x152f
++#define mmCRTCV1_CRTCV_BLACK_COLOR_BASE_IDX 2
++#define mmCRTCV1_CRTCV_BLACK_COLOR_EXT 0x1530
++#define mmCRTCV1_CRTCV_BLACK_COLOR_EXT_BASE_IDX 2
++#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_POSITION 0x1531
++#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
++#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL 0x1532
++#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_POSITION 0x1533
++#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
++#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL 0x1534
++#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_POSITION 0x1535
++#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
++#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL 0x1536
++#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_CRC_CNTL 0x1537
++#define mmCRTCV1_CRTCV_CRC_CNTL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL 0x1538
++#define mmCRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL 0x1539
++#define mmCRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL 0x153a
++#define mmCRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL 0x153b
++#define mmCRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_CRC0_DATA_RG 0x153c
++#define mmCRTCV1_CRTCV_CRC0_DATA_RG_BASE_IDX 2
++#define mmCRTCV1_CRTCV_CRC0_DATA_B 0x153d
++#define mmCRTCV1_CRTCV_CRC0_DATA_B_BASE_IDX 2
++#define mmCRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL 0x153e
++#define mmCRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL 0x153f
++#define mmCRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL 0x1540
++#define mmCRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL 0x1541
++#define mmCRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_CRC1_DATA_RG 0x1542
++#define mmCRTCV1_CRTCV_CRC1_DATA_RG_BASE_IDX 2
++#define mmCRTCV1_CRTCV_CRC1_DATA_B 0x1543
++#define mmCRTCV1_CRTCV_CRC1_DATA_B_BASE_IDX 2
++#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL 0x1544
++#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_START 0x1545
++#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2
++#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_END 0x1546
++#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2
++#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1547
++#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1548
++#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1549
++#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_STATIC_SCREEN_CONTROL 0x154a
++#define mmCRTCV1_CRTCV_STATIC_SCREEN_CONTROL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_3D_STRUCTURE_CONTROL 0x154b
++#define mmCRTCV1_CRTCV_3D_STRUCTURE_CONTROL_BASE_IDX 2
++#define mmCRTCV1_CRTCV_GSL_VSYNC_GAP 0x154c
++#define mmCRTCV1_CRTCV_GSL_VSYNC_GAP_BASE_IDX 2
++#define mmCRTCV1_CRTCV_GSL_WINDOW 0x154d
++#define mmCRTCV1_CRTCV_GSL_WINDOW_BASE_IDX 2
++#define mmCRTCV1_CRTCV_GSL_CONTROL 0x154e
++#define mmCRTCV1_CRTCV_GSL_CONTROL_BASE_IDX 2
++
++
++// addressBlock: dce_dc_hpd0_dispdec
++// base address: 0x0
++#define mmHPD0_DC_HPD_INT_STATUS 0x1600
++#define mmHPD0_DC_HPD_INT_STATUS_BASE_IDX 2
++#define mmHPD0_DC_HPD_INT_CONTROL 0x1601
++#define mmHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2
++#define mmHPD0_DC_HPD_CONTROL 0x1602
++#define mmHPD0_DC_HPD_CONTROL_BASE_IDX 2
++#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0x1603
++#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
++#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x1604
++#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
++
++
++// addressBlock: dce_dc_hpd1_dispdec
++// base address: 0x20
++#define mmHPD1_DC_HPD_INT_STATUS 0x1608
++#define mmHPD1_DC_HPD_INT_STATUS_BASE_IDX 2
++#define mmHPD1_DC_HPD_INT_CONTROL 0x1609
++#define mmHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2
++#define mmHPD1_DC_HPD_CONTROL 0x160a
++#define mmHPD1_DC_HPD_CONTROL_BASE_IDX 2
++#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0x160b
++#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
++#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x160c
++#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
++
++
++// addressBlock: dce_dc_hpd2_dispdec
++// base address: 0x40
++#define mmHPD2_DC_HPD_INT_STATUS 0x1610
++#define mmHPD2_DC_HPD_INT_STATUS_BASE_IDX 2
++#define mmHPD2_DC_HPD_INT_CONTROL 0x1611
++#define mmHPD2_DC_HPD_INT_CONTROL_BASE_IDX 2
++#define mmHPD2_DC_HPD_CONTROL 0x1612
++#define mmHPD2_DC_HPD_CONTROL_BASE_IDX 2
++#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL 0x1613
++#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
++#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x1614
++#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
++
++
++// addressBlock: dce_dc_hpd3_dispdec
++// base address: 0x60
++#define mmHPD3_DC_HPD_INT_STATUS 0x1618
++#define mmHPD3_DC_HPD_INT_STATUS_BASE_IDX 2
++#define mmHPD3_DC_HPD_INT_CONTROL 0x1619
++#define mmHPD3_DC_HPD_INT_CONTROL_BASE_IDX 2
++#define mmHPD3_DC_HPD_CONTROL 0x161a
++#define mmHPD3_DC_HPD_CONTROL_BASE_IDX 2
++#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL 0x161b
++#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
++#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x161c
++#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
++
++
++// addressBlock: dce_dc_hpd4_dispdec
++// base address: 0x80
++#define mmHPD4_DC_HPD_INT_STATUS 0x1620
++#define mmHPD4_DC_HPD_INT_STATUS_BASE_IDX 2
++#define mmHPD4_DC_HPD_INT_CONTROL 0x1621
++#define mmHPD4_DC_HPD_INT_CONTROL_BASE_IDX 2
++#define mmHPD4_DC_HPD_CONTROL 0x1622
++#define mmHPD4_DC_HPD_CONTROL_BASE_IDX 2
++#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL 0x1623
++#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
++#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x1624
++#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
++
++
++// addressBlock: dce_dc_hpd5_dispdec
++// base address: 0xa0
++#define mmHPD5_DC_HPD_INT_STATUS 0x1628
++#define mmHPD5_DC_HPD_INT_STATUS_BASE_IDX 2
++#define mmHPD5_DC_HPD_INT_CONTROL 0x1629
++#define mmHPD5_DC_HPD_INT_CONTROL_BASE_IDX 2
++#define mmHPD5_DC_HPD_CONTROL 0x162a
++#define mmHPD5_DC_HPD_CONTROL_BASE_IDX 2
++#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL 0x162b
++#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
++#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL 0x162c
++#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dc_perfmon2_dispdec
++// base address: 0x5840
++#define mmDC_PERFMON2_PERFCOUNTER_CNTL 0x1630
++#define mmDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX 2
++#define mmDC_PERFMON2_PERFCOUNTER_CNTL2 0x1631
++#define mmDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX 2
++#define mmDC_PERFMON2_PERFCOUNTER_STATE 0x1632
++#define mmDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX 2
++#define mmDC_PERFMON2_PERFMON_CNTL 0x1633
++#define mmDC_PERFMON2_PERFMON_CNTL_BASE_IDX 2
++#define mmDC_PERFMON2_PERFMON_CNTL2 0x1634
++#define mmDC_PERFMON2_PERFMON_CNTL2_BASE_IDX 2
++#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x1635
++#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
++#define mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x1636
++#define mmDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX 2
++#define mmDC_PERFMON2_PERFMON_HI 0x1637
++#define mmDC_PERFMON2_PERFMON_HI_BASE_IDX 2
++#define mmDC_PERFMON2_PERFMON_LOW 0x1638
++#define mmDC_PERFMON2_PERFMON_LOW_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dp_aux0_dispdec
++// base address: 0x0
++#define mmDP_AUX0_AUX_CONTROL 0x1766
++#define mmDP_AUX0_AUX_CONTROL_BASE_IDX 2
++#define mmDP_AUX0_AUX_SW_CONTROL 0x1767
++#define mmDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2
++#define mmDP_AUX0_AUX_ARB_CONTROL 0x1768
++#define mmDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2
++#define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x1769
++#define mmDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmDP_AUX0_AUX_SW_STATUS 0x176a
++#define mmDP_AUX0_AUX_SW_STATUS_BASE_IDX 2
++#define mmDP_AUX0_AUX_LS_STATUS 0x176b
++#define mmDP_AUX0_AUX_LS_STATUS_BASE_IDX 2
++#define mmDP_AUX0_AUX_SW_DATA 0x176c
++#define mmDP_AUX0_AUX_SW_DATA_BASE_IDX 2
++#define mmDP_AUX0_AUX_LS_DATA 0x176d
++#define mmDP_AUX0_AUX_LS_DATA_BASE_IDX 2
++#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x176e
++#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
++#define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x176f
++#define mmDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2
++#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x1770
++#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
++#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x1771
++#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
++#define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x1772
++#define mmDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2
++#define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x1773
++#define mmDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2
++#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x1775
++#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
++#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1776
++#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
++#define mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x1777
++#define mmDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dp_aux1_dispdec
++// base address: 0x70
++#define mmDP_AUX1_AUX_CONTROL 0x1782
++#define mmDP_AUX1_AUX_CONTROL_BASE_IDX 2
++#define mmDP_AUX1_AUX_SW_CONTROL 0x1783
++#define mmDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2
++#define mmDP_AUX1_AUX_ARB_CONTROL 0x1784
++#define mmDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2
++#define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x1785
++#define mmDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmDP_AUX1_AUX_SW_STATUS 0x1786
++#define mmDP_AUX1_AUX_SW_STATUS_BASE_IDX 2
++#define mmDP_AUX1_AUX_LS_STATUS 0x1787
++#define mmDP_AUX1_AUX_LS_STATUS_BASE_IDX 2
++#define mmDP_AUX1_AUX_SW_DATA 0x1788
++#define mmDP_AUX1_AUX_SW_DATA_BASE_IDX 2
++#define mmDP_AUX1_AUX_LS_DATA 0x1789
++#define mmDP_AUX1_AUX_LS_DATA_BASE_IDX 2
++#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x178a
++#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
++#define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x178b
++#define mmDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2
++#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x178c
++#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
++#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x178d
++#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
++#define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x178e
++#define mmDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2
++#define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x178f
++#define mmDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2
++#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x1791
++#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
++#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1792
++#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
++#define mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x1793
++#define mmDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dp_aux2_dispdec
++// base address: 0xe0
++#define mmDP_AUX2_AUX_CONTROL 0x179e
++#define mmDP_AUX2_AUX_CONTROL_BASE_IDX 2
++#define mmDP_AUX2_AUX_SW_CONTROL 0x179f
++#define mmDP_AUX2_AUX_SW_CONTROL_BASE_IDX 2
++#define mmDP_AUX2_AUX_ARB_CONTROL 0x17a0
++#define mmDP_AUX2_AUX_ARB_CONTROL_BASE_IDX 2
++#define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x17a1
++#define mmDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmDP_AUX2_AUX_SW_STATUS 0x17a2
++#define mmDP_AUX2_AUX_SW_STATUS_BASE_IDX 2
++#define mmDP_AUX2_AUX_LS_STATUS 0x17a3
++#define mmDP_AUX2_AUX_LS_STATUS_BASE_IDX 2
++#define mmDP_AUX2_AUX_SW_DATA 0x17a4
++#define mmDP_AUX2_AUX_SW_DATA_BASE_IDX 2
++#define mmDP_AUX2_AUX_LS_DATA 0x17a5
++#define mmDP_AUX2_AUX_LS_DATA_BASE_IDX 2
++#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x17a6
++#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
++#define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x17a7
++#define mmDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX 2
++#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x17a8
++#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
++#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x17a9
++#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
++#define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x17aa
++#define mmDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX 2
++#define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x17ab
++#define mmDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX 2
++#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x17ad
++#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
++#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x17ae
++#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
++#define mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x17af
++#define mmDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dp_aux3_dispdec
++// base address: 0x150
++#define mmDP_AUX3_AUX_CONTROL 0x17ba
++#define mmDP_AUX3_AUX_CONTROL_BASE_IDX 2
++#define mmDP_AUX3_AUX_SW_CONTROL 0x17bb
++#define mmDP_AUX3_AUX_SW_CONTROL_BASE_IDX 2
++#define mmDP_AUX3_AUX_ARB_CONTROL 0x17bc
++#define mmDP_AUX3_AUX_ARB_CONTROL_BASE_IDX 2
++#define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x17bd
++#define mmDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmDP_AUX3_AUX_SW_STATUS 0x17be
++#define mmDP_AUX3_AUX_SW_STATUS_BASE_IDX 2
++#define mmDP_AUX3_AUX_LS_STATUS 0x17bf
++#define mmDP_AUX3_AUX_LS_STATUS_BASE_IDX 2
++#define mmDP_AUX3_AUX_SW_DATA 0x17c0
++#define mmDP_AUX3_AUX_SW_DATA_BASE_IDX 2
++#define mmDP_AUX3_AUX_LS_DATA 0x17c1
++#define mmDP_AUX3_AUX_LS_DATA_BASE_IDX 2
++#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x17c2
++#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
++#define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x17c3
++#define mmDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX 2
++#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x17c4
++#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
++#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x17c5
++#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
++#define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x17c6
++#define mmDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX 2
++#define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x17c7
++#define mmDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX 2
++#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x17c9
++#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
++#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x17ca
++#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
++#define mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x17cb
++#define mmDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dp_aux4_dispdec
++// base address: 0x1c0
++#define mmDP_AUX4_AUX_CONTROL 0x17d6
++#define mmDP_AUX4_AUX_CONTROL_BASE_IDX 2
++#define mmDP_AUX4_AUX_SW_CONTROL 0x17d7
++#define mmDP_AUX4_AUX_SW_CONTROL_BASE_IDX 2
++#define mmDP_AUX4_AUX_ARB_CONTROL 0x17d8
++#define mmDP_AUX4_AUX_ARB_CONTROL_BASE_IDX 2
++#define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x17d9
++#define mmDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmDP_AUX4_AUX_SW_STATUS 0x17da
++#define mmDP_AUX4_AUX_SW_STATUS_BASE_IDX 2
++#define mmDP_AUX4_AUX_LS_STATUS 0x17db
++#define mmDP_AUX4_AUX_LS_STATUS_BASE_IDX 2
++#define mmDP_AUX4_AUX_SW_DATA 0x17dc
++#define mmDP_AUX4_AUX_SW_DATA_BASE_IDX 2
++#define mmDP_AUX4_AUX_LS_DATA 0x17dd
++#define mmDP_AUX4_AUX_LS_DATA_BASE_IDX 2
++#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x17de
++#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
++#define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x17df
++#define mmDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX 2
++#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x17e0
++#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
++#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x17e1
++#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
++#define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x17e2
++#define mmDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX 2
++#define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x17e3
++#define mmDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX 2
++#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x17e5
++#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
++#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x17e6
++#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
++#define mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x17e7
++#define mmDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dp_aux5_dispdec
++// base address: 0x230
++#define mmDP_AUX5_AUX_CONTROL 0x17f2
++#define mmDP_AUX5_AUX_CONTROL_BASE_IDX 2
++#define mmDP_AUX5_AUX_SW_CONTROL 0x17f3
++#define mmDP_AUX5_AUX_SW_CONTROL_BASE_IDX 2
++#define mmDP_AUX5_AUX_ARB_CONTROL 0x17f4
++#define mmDP_AUX5_AUX_ARB_CONTROL_BASE_IDX 2
++#define mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x17f5
++#define mmDP_AUX5_AUX_INTERRUPT_CONTROL_BASE_IDX 2
++#define mmDP_AUX5_AUX_SW_STATUS 0x17f6
++#define mmDP_AUX5_AUX_SW_STATUS_BASE_IDX 2
++#define mmDP_AUX5_AUX_LS_STATUS 0x17f7
++#define mmDP_AUX5_AUX_LS_STATUS_BASE_IDX 2
++#define mmDP_AUX5_AUX_SW_DATA 0x17f8
++#define mmDP_AUX5_AUX_SW_DATA_BASE_IDX 2
++#define mmDP_AUX5_AUX_LS_DATA 0x17f9
++#define mmDP_AUX5_AUX_LS_DATA_BASE_IDX 2
++#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x17fa
++#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
++#define mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x17fb
++#define mmDP_AUX5_AUX_DPHY_TX_CONTROL_BASE_IDX 2
++#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x17fc
++#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
++#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x17fd
++#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
++#define mmDP_AUX5_AUX_DPHY_TX_STATUS 0x17fe
++#define mmDP_AUX5_AUX_DPHY_TX_STATUS_BASE_IDX 2
++#define mmDP_AUX5_AUX_DPHY_RX_STATUS 0x17ff
++#define mmDP_AUX5_AUX_DPHY_RX_STATUS_BASE_IDX 2
++#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0x1801
++#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
++#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1802
++#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
++#define mmDP_AUX5_AUX_GTC_SYNC_STATUS 0x1803
++#define mmDP_AUX5_AUX_GTC_SYNC_STATUS_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dig0_dispdec
++// base address: 0x0
++#define mmDIG0_DIG_FE_CNTL 0x187e
++#define mmDIG0_DIG_FE_CNTL_BASE_IDX 2
++#define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x187f
++#define mmDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
++#define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x1880
++#define mmDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
++#define mmDIG0_DIG_CLOCK_PATTERN 0x1881
++#define mmDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2
++#define mmDIG0_DIG_TEST_PATTERN 0x1882
++#define mmDIG0_DIG_TEST_PATTERN_BASE_IDX 2
++#define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x1883
++#define mmDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
++#define mmDIG0_DIG_FIFO_STATUS 0x1884
++#define mmDIG0_DIG_FIFO_STATUS_BASE_IDX 2
++#define mmDIG0_HDMI_CONTROL 0x1887
++#define mmDIG0_HDMI_CONTROL_BASE_IDX 2
++#define mmDIG0_HDMI_STATUS 0x1888
++#define mmDIG0_HDMI_STATUS_BASE_IDX 2
++#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x1889
++#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
++#define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x188a
++#define mmDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
++#define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x188b
++#define mmDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
++#define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x188c
++#define mmDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
++#define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x188d
++#define mmDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
++#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x188e
++#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
++#define mmDIG0_AFMT_INTERRUPT_STATUS 0x188f
++#define mmDIG0_AFMT_INTERRUPT_STATUS_BASE_IDX 2
++#define mmDIG0_HDMI_GC 0x1891
++#define mmDIG0_HDMI_GC_BASE_IDX 2
++#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x1892
++#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
++#define mmDIG0_AFMT_ISRC1_0 0x1893
++#define mmDIG0_AFMT_ISRC1_0_BASE_IDX 2
++#define mmDIG0_AFMT_ISRC1_1 0x1894
++#define mmDIG0_AFMT_ISRC1_1_BASE_IDX 2
++#define mmDIG0_AFMT_ISRC1_2 0x1895
++#define mmDIG0_AFMT_ISRC1_2_BASE_IDX 2
++#define mmDIG0_AFMT_ISRC1_3 0x1896
++#define mmDIG0_AFMT_ISRC1_3_BASE_IDX 2
++#define mmDIG0_AFMT_ISRC1_4 0x1897
++#define mmDIG0_AFMT_ISRC1_4_BASE_IDX 2
++#define mmDIG0_AFMT_ISRC2_0 0x1898
++#define mmDIG0_AFMT_ISRC2_0_BASE_IDX 2
++#define mmDIG0_AFMT_ISRC2_1 0x1899
++#define mmDIG0_AFMT_ISRC2_1_BASE_IDX 2
++#define mmDIG0_AFMT_ISRC2_2 0x189a
++#define mmDIG0_AFMT_ISRC2_2_BASE_IDX 2
++#define mmDIG0_AFMT_ISRC2_3 0x189b
++#define mmDIG0_AFMT_ISRC2_3_BASE_IDX 2
++#define mmDIG0_AFMT_AVI_INFO0 0x189c
++#define mmDIG0_AFMT_AVI_INFO0_BASE_IDX 2
++#define mmDIG0_AFMT_AVI_INFO1 0x189d
++#define mmDIG0_AFMT_AVI_INFO1_BASE_IDX 2
++#define mmDIG0_AFMT_AVI_INFO2 0x189e
++#define mmDIG0_AFMT_AVI_INFO2_BASE_IDX 2
++#define mmDIG0_AFMT_AVI_INFO3 0x189f
++#define mmDIG0_AFMT_AVI_INFO3_BASE_IDX 2
++#define mmDIG0_AFMT_MPEG_INFO0 0x18a0
++#define mmDIG0_AFMT_MPEG_INFO0_BASE_IDX 2
++#define mmDIG0_AFMT_MPEG_INFO1 0x18a1
++#define mmDIG0_AFMT_MPEG_INFO1_BASE_IDX 2
++#define mmDIG0_AFMT_GENERIC_HDR 0x18a2
++#define mmDIG0_AFMT_GENERIC_HDR_BASE_IDX 2
++#define mmDIG0_AFMT_GENERIC_0 0x18a3
++#define mmDIG0_AFMT_GENERIC_0_BASE_IDX 2
++#define mmDIG0_AFMT_GENERIC_1 0x18a4
++#define mmDIG0_AFMT_GENERIC_1_BASE_IDX 2
++#define mmDIG0_AFMT_GENERIC_2 0x18a5
++#define mmDIG0_AFMT_GENERIC_2_BASE_IDX 2
++#define mmDIG0_AFMT_GENERIC_3 0x18a6
++#define mmDIG0_AFMT_GENERIC_3_BASE_IDX 2
++#define mmDIG0_AFMT_GENERIC_4 0x18a7
++#define mmDIG0_AFMT_GENERIC_4_BASE_IDX 2
++#define mmDIG0_AFMT_GENERIC_5 0x18a8
++#define mmDIG0_AFMT_GENERIC_5_BASE_IDX 2
++#define mmDIG0_AFMT_GENERIC_6 0x18a9
++#define mmDIG0_AFMT_GENERIC_6_BASE_IDX 2
++#define mmDIG0_AFMT_GENERIC_7 0x18aa
++#define mmDIG0_AFMT_GENERIC_7_BASE_IDX 2
++#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x18ab
++#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
++#define mmDIG0_HDMI_ACR_32_0 0x18ac
++#define mmDIG0_HDMI_ACR_32_0_BASE_IDX 2
++#define mmDIG0_HDMI_ACR_32_1 0x18ad
++#define mmDIG0_HDMI_ACR_32_1_BASE_IDX 2
++#define mmDIG0_HDMI_ACR_44_0 0x18ae
++#define mmDIG0_HDMI_ACR_44_0_BASE_IDX 2
++#define mmDIG0_HDMI_ACR_44_1 0x18af
++#define mmDIG0_HDMI_ACR_44_1_BASE_IDX 2
++#define mmDIG0_HDMI_ACR_48_0 0x18b0
++#define mmDIG0_HDMI_ACR_48_0_BASE_IDX 2
++#define mmDIG0_HDMI_ACR_48_1 0x18b1
++#define mmDIG0_HDMI_ACR_48_1_BASE_IDX 2
++#define mmDIG0_HDMI_ACR_STATUS_0 0x18b2
++#define mmDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2
++#define mmDIG0_HDMI_ACR_STATUS_1 0x18b3
++#define mmDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2
++#define mmDIG0_AFMT_AUDIO_INFO0 0x18b4
++#define mmDIG0_AFMT_AUDIO_INFO0_BASE_IDX 2
++#define mmDIG0_AFMT_AUDIO_INFO1 0x18b5
++#define mmDIG0_AFMT_AUDIO_INFO1_BASE_IDX 2
++#define mmDIG0_AFMT_60958_0 0x18b6
++#define mmDIG0_AFMT_60958_0_BASE_IDX 2
++#define mmDIG0_AFMT_60958_1 0x18b7
++#define mmDIG0_AFMT_60958_1_BASE_IDX 2
++#define mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x18b8
++#define mmDIG0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
++#define mmDIG0_AFMT_RAMP_CONTROL0 0x18b9
++#define mmDIG0_AFMT_RAMP_CONTROL0_BASE_IDX 2
++#define mmDIG0_AFMT_RAMP_CONTROL1 0x18ba
++#define mmDIG0_AFMT_RAMP_CONTROL1_BASE_IDX 2
++#define mmDIG0_AFMT_RAMP_CONTROL2 0x18bb
++#define mmDIG0_AFMT_RAMP_CONTROL2_BASE_IDX 2
++#define mmDIG0_AFMT_RAMP_CONTROL3 0x18bc
++#define mmDIG0_AFMT_RAMP_CONTROL3_BASE_IDX 2
++#define mmDIG0_AFMT_60958_2 0x18bd
++#define mmDIG0_AFMT_60958_2_BASE_IDX 2
++#define mmDIG0_AFMT_AUDIO_CRC_RESULT 0x18be
++#define mmDIG0_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
++#define mmDIG0_AFMT_STATUS 0x18bf
++#define mmDIG0_AFMT_STATUS_BASE_IDX 2
++#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x18c0
++#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
++#define mmDIG0_AFMT_VBI_PACKET_CONTROL 0x18c1
++#define mmDIG0_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
++#define mmDIG0_AFMT_INFOFRAME_CONTROL0 0x18c2
++#define mmDIG0_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
++#define mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x18c3
++#define mmDIG0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
++#define mmDIG0_DIG_BE_CNTL 0x18c5
++#define mmDIG0_DIG_BE_CNTL_BASE_IDX 2
++#define mmDIG0_DIG_BE_EN_CNTL 0x18c6
++#define mmDIG0_DIG_BE_EN_CNTL_BASE_IDX 2
++#define mmDIG0_TMDS_CNTL 0x18e9
++#define mmDIG0_TMDS_CNTL_BASE_IDX 2
++#define mmDIG0_TMDS_CONTROL_CHAR 0x18ea
++#define mmDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2
++#define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x18eb
++#define mmDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
++#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x18ec
++#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
++#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x18ed
++#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
++#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x18ee
++#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
++#define mmDIG0_TMDS_CTL_BITS 0x18f0
++#define mmDIG0_TMDS_CTL_BITS_BASE_IDX 2
++#define mmDIG0_TMDS_DCBALANCER_CONTROL 0x18f1
++#define mmDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
++#define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x18f3
++#define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
++#define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x18f4
++#define mmDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
++#define mmDIG0_DIG_VERSION 0x18f6
++#define mmDIG0_DIG_VERSION_BASE_IDX 2
++#define mmDIG0_DIG_LANE_ENABLE 0x18f7
++#define mmDIG0_DIG_LANE_ENABLE_BASE_IDX 2
++#define mmDIG0_AFMT_CNTL 0x18fc
++#define mmDIG0_AFMT_CNTL_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dp0_dispdec
++// base address: 0x0
++#define mmDP0_DP_LINK_CNTL 0x191e
++#define mmDP0_DP_LINK_CNTL_BASE_IDX 2
++#define mmDP0_DP_PIXEL_FORMAT 0x191f
++#define mmDP0_DP_PIXEL_FORMAT_BASE_IDX 2
++#define mmDP0_DP_MSA_COLORIMETRY 0x1920
++#define mmDP0_DP_MSA_COLORIMETRY_BASE_IDX 2
++#define mmDP0_DP_CONFIG 0x1921
++#define mmDP0_DP_CONFIG_BASE_IDX 2
++#define mmDP0_DP_VID_STREAM_CNTL 0x1922
++#define mmDP0_DP_VID_STREAM_CNTL_BASE_IDX 2
++#define mmDP0_DP_STEER_FIFO 0x1923
++#define mmDP0_DP_STEER_FIFO_BASE_IDX 2
++#define mmDP0_DP_MSA_MISC 0x1924
++#define mmDP0_DP_MSA_MISC_BASE_IDX 2
++#define mmDP0_DP_VID_TIMING 0x1926
++#define mmDP0_DP_VID_TIMING_BASE_IDX 2
++#define mmDP0_DP_VID_N 0x1927
++#define mmDP0_DP_VID_N_BASE_IDX 2
++#define mmDP0_DP_VID_M 0x1928
++#define mmDP0_DP_VID_M_BASE_IDX 2
++#define mmDP0_DP_LINK_FRAMING_CNTL 0x1929
++#define mmDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2
++#define mmDP0_DP_HBR2_EYE_PATTERN 0x192a
++#define mmDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2
++#define mmDP0_DP_VID_MSA_VBID 0x192b
++#define mmDP0_DP_VID_MSA_VBID_BASE_IDX 2
++#define mmDP0_DP_VID_INTERRUPT_CNTL 0x192c
++#define mmDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
++#define mmDP0_DP_DPHY_CNTL 0x192d
++#define mmDP0_DP_DPHY_CNTL_BASE_IDX 2
++#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x192e
++#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
++#define mmDP0_DP_DPHY_SYM0 0x192f
++#define mmDP0_DP_DPHY_SYM0_BASE_IDX 2
++#define mmDP0_DP_DPHY_SYM1 0x1930
++#define mmDP0_DP_DPHY_SYM1_BASE_IDX 2
++#define mmDP0_DP_DPHY_SYM2 0x1931
++#define mmDP0_DP_DPHY_SYM2_BASE_IDX 2
++#define mmDP0_DP_DPHY_8B10B_CNTL 0x1932
++#define mmDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2
++#define mmDP0_DP_DPHY_PRBS_CNTL 0x1933
++#define mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2
++#define mmDP0_DP_DPHY_SCRAM_CNTL 0x1934
++#define mmDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
++#define mmDP0_DP_DPHY_CRC_EN 0x1935
++#define mmDP0_DP_DPHY_CRC_EN_BASE_IDX 2
++#define mmDP0_DP_DPHY_CRC_CNTL 0x1936
++#define mmDP0_DP_DPHY_CRC_CNTL_BASE_IDX 2
++#define mmDP0_DP_DPHY_CRC_RESULT 0x1937
++#define mmDP0_DP_DPHY_CRC_RESULT_BASE_IDX 2
++#define mmDP0_DP_DPHY_CRC_MST_CNTL 0x1938
++#define mmDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
++#define mmDP0_DP_DPHY_CRC_MST_STATUS 0x1939
++#define mmDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
++#define mmDP0_DP_DPHY_FAST_TRAINING 0x193a
++#define mmDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2
++#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x193b
++#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
++#define mmDP0_DP_MSA_V_TIMING_OVERRIDE1 0x193c
++#define mmDP0_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2
++#define mmDP0_DP_MSA_V_TIMING_OVERRIDE2 0x193d
++#define mmDP0_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2
++#define mmDP0_DP_SEC_CNTL 0x1941
++#define mmDP0_DP_SEC_CNTL_BASE_IDX 2
++#define mmDP0_DP_SEC_CNTL1 0x1942
++#define mmDP0_DP_SEC_CNTL1_BASE_IDX 2
++#define mmDP0_DP_SEC_FRAMING1 0x1943
++#define mmDP0_DP_SEC_FRAMING1_BASE_IDX 2
++#define mmDP0_DP_SEC_FRAMING2 0x1944
++#define mmDP0_DP_SEC_FRAMING2_BASE_IDX 2
++#define mmDP0_DP_SEC_FRAMING3 0x1945
++#define mmDP0_DP_SEC_FRAMING3_BASE_IDX 2
++#define mmDP0_DP_SEC_FRAMING4 0x1946
++#define mmDP0_DP_SEC_FRAMING4_BASE_IDX 2
++#define mmDP0_DP_SEC_AUD_N 0x1947
++#define mmDP0_DP_SEC_AUD_N_BASE_IDX 2
++#define mmDP0_DP_SEC_AUD_N_READBACK 0x1948
++#define mmDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2
++#define mmDP0_DP_SEC_AUD_M 0x1949
++#define mmDP0_DP_SEC_AUD_M_BASE_IDX 2
++#define mmDP0_DP_SEC_AUD_M_READBACK 0x194a
++#define mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2
++#define mmDP0_DP_SEC_TIMESTAMP 0x194b
++#define mmDP0_DP_SEC_TIMESTAMP_BASE_IDX 2
++#define mmDP0_DP_SEC_PACKET_CNTL 0x194c
++#define mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2
++#define mmDP0_DP_MSE_RATE_CNTL 0x194d
++#define mmDP0_DP_MSE_RATE_CNTL_BASE_IDX 2
++#define mmDP0_DP_MSE_RATE_UPDATE 0x194f
++#define mmDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2
++#define mmDP0_DP_MSE_SAT0 0x1950
++#define mmDP0_DP_MSE_SAT0_BASE_IDX 2
++#define mmDP0_DP_MSE_SAT1 0x1951
++#define mmDP0_DP_MSE_SAT1_BASE_IDX 2
++#define mmDP0_DP_MSE_SAT2 0x1952
++#define mmDP0_DP_MSE_SAT2_BASE_IDX 2
++#define mmDP0_DP_MSE_SAT_UPDATE 0x1953
++#define mmDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2
++#define mmDP0_DP_MSE_LINK_TIMING 0x1954
++#define mmDP0_DP_MSE_LINK_TIMING_BASE_IDX 2
++#define mmDP0_DP_MSE_MISC_CNTL 0x1955
++#define mmDP0_DP_MSE_MISC_CNTL_BASE_IDX 2
++#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x195a
++#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
++#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x195b
++#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
++#define mmDP0_DP_MSE_SAT0_STATUS 0x195d
++#define mmDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2
++#define mmDP0_DP_MSE_SAT1_STATUS 0x195e
++#define mmDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2
++#define mmDP0_DP_MSE_SAT2_STATUS 0x195f
++#define mmDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dig1_dispdec
++// base address: 0x400
++#define mmDIG1_DIG_FE_CNTL 0x197e
++#define mmDIG1_DIG_FE_CNTL_BASE_IDX 2
++#define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x197f
++#define mmDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
++#define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x1980
++#define mmDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
++#define mmDIG1_DIG_CLOCK_PATTERN 0x1981
++#define mmDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2
++#define mmDIG1_DIG_TEST_PATTERN 0x1982
++#define mmDIG1_DIG_TEST_PATTERN_BASE_IDX 2
++#define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x1983
++#define mmDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
++#define mmDIG1_DIG_FIFO_STATUS 0x1984
++#define mmDIG1_DIG_FIFO_STATUS_BASE_IDX 2
++#define mmDIG1_HDMI_CONTROL 0x1987
++#define mmDIG1_HDMI_CONTROL_BASE_IDX 2
++#define mmDIG1_HDMI_STATUS 0x1988
++#define mmDIG1_HDMI_STATUS_BASE_IDX 2
++#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x1989
++#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
++#define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x198a
++#define mmDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
++#define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x198b
++#define mmDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
++#define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x198c
++#define mmDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
++#define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x198d
++#define mmDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
++#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x198e
++#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
++#define mmDIG1_AFMT_INTERRUPT_STATUS 0x198f
++#define mmDIG1_AFMT_INTERRUPT_STATUS_BASE_IDX 2
++#define mmDIG1_HDMI_GC 0x1991
++#define mmDIG1_HDMI_GC_BASE_IDX 2
++#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x1992
++#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
++#define mmDIG1_AFMT_ISRC1_0 0x1993
++#define mmDIG1_AFMT_ISRC1_0_BASE_IDX 2
++#define mmDIG1_AFMT_ISRC1_1 0x1994
++#define mmDIG1_AFMT_ISRC1_1_BASE_IDX 2
++#define mmDIG1_AFMT_ISRC1_2 0x1995
++#define mmDIG1_AFMT_ISRC1_2_BASE_IDX 2
++#define mmDIG1_AFMT_ISRC1_3 0x1996
++#define mmDIG1_AFMT_ISRC1_3_BASE_IDX 2
++#define mmDIG1_AFMT_ISRC1_4 0x1997
++#define mmDIG1_AFMT_ISRC1_4_BASE_IDX 2
++#define mmDIG1_AFMT_ISRC2_0 0x1998
++#define mmDIG1_AFMT_ISRC2_0_BASE_IDX 2
++#define mmDIG1_AFMT_ISRC2_1 0x1999
++#define mmDIG1_AFMT_ISRC2_1_BASE_IDX 2
++#define mmDIG1_AFMT_ISRC2_2 0x199a
++#define mmDIG1_AFMT_ISRC2_2_BASE_IDX 2
++#define mmDIG1_AFMT_ISRC2_3 0x199b
++#define mmDIG1_AFMT_ISRC2_3_BASE_IDX 2
++#define mmDIG1_AFMT_AVI_INFO0 0x199c
++#define mmDIG1_AFMT_AVI_INFO0_BASE_IDX 2
++#define mmDIG1_AFMT_AVI_INFO1 0x199d
++#define mmDIG1_AFMT_AVI_INFO1_BASE_IDX 2
++#define mmDIG1_AFMT_AVI_INFO2 0x199e
++#define mmDIG1_AFMT_AVI_INFO2_BASE_IDX 2
++#define mmDIG1_AFMT_AVI_INFO3 0x199f
++#define mmDIG1_AFMT_AVI_INFO3_BASE_IDX 2
++#define mmDIG1_AFMT_MPEG_INFO0 0x19a0
++#define mmDIG1_AFMT_MPEG_INFO0_BASE_IDX 2
++#define mmDIG1_AFMT_MPEG_INFO1 0x19a1
++#define mmDIG1_AFMT_MPEG_INFO1_BASE_IDX 2
++#define mmDIG1_AFMT_GENERIC_HDR 0x19a2
++#define mmDIG1_AFMT_GENERIC_HDR_BASE_IDX 2
++#define mmDIG1_AFMT_GENERIC_0 0x19a3
++#define mmDIG1_AFMT_GENERIC_0_BASE_IDX 2
++#define mmDIG1_AFMT_GENERIC_1 0x19a4
++#define mmDIG1_AFMT_GENERIC_1_BASE_IDX 2
++#define mmDIG1_AFMT_GENERIC_2 0x19a5
++#define mmDIG1_AFMT_GENERIC_2_BASE_IDX 2
++#define mmDIG1_AFMT_GENERIC_3 0x19a6
++#define mmDIG1_AFMT_GENERIC_3_BASE_IDX 2
++#define mmDIG1_AFMT_GENERIC_4 0x19a7
++#define mmDIG1_AFMT_GENERIC_4_BASE_IDX 2
++#define mmDIG1_AFMT_GENERIC_5 0x19a8
++#define mmDIG1_AFMT_GENERIC_5_BASE_IDX 2
++#define mmDIG1_AFMT_GENERIC_6 0x19a9
++#define mmDIG1_AFMT_GENERIC_6_BASE_IDX 2
++#define mmDIG1_AFMT_GENERIC_7 0x19aa
++#define mmDIG1_AFMT_GENERIC_7_BASE_IDX 2
++#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x19ab
++#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
++#define mmDIG1_HDMI_ACR_32_0 0x19ac
++#define mmDIG1_HDMI_ACR_32_0_BASE_IDX 2
++#define mmDIG1_HDMI_ACR_32_1 0x19ad
++#define mmDIG1_HDMI_ACR_32_1_BASE_IDX 2
++#define mmDIG1_HDMI_ACR_44_0 0x19ae
++#define mmDIG1_HDMI_ACR_44_0_BASE_IDX 2
++#define mmDIG1_HDMI_ACR_44_1 0x19af
++#define mmDIG1_HDMI_ACR_44_1_BASE_IDX 2
++#define mmDIG1_HDMI_ACR_48_0 0x19b0
++#define mmDIG1_HDMI_ACR_48_0_BASE_IDX 2
++#define mmDIG1_HDMI_ACR_48_1 0x19b1
++#define mmDIG1_HDMI_ACR_48_1_BASE_IDX 2
++#define mmDIG1_HDMI_ACR_STATUS_0 0x19b2
++#define mmDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2
++#define mmDIG1_HDMI_ACR_STATUS_1 0x19b3
++#define mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2
++#define mmDIG1_AFMT_AUDIO_INFO0 0x19b4
++#define mmDIG1_AFMT_AUDIO_INFO0_BASE_IDX 2
++#define mmDIG1_AFMT_AUDIO_INFO1 0x19b5
++#define mmDIG1_AFMT_AUDIO_INFO1_BASE_IDX 2
++#define mmDIG1_AFMT_60958_0 0x19b6
++#define mmDIG1_AFMT_60958_0_BASE_IDX 2
++#define mmDIG1_AFMT_60958_1 0x19b7
++#define mmDIG1_AFMT_60958_1_BASE_IDX 2
++#define mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x19b8
++#define mmDIG1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
++#define mmDIG1_AFMT_RAMP_CONTROL0 0x19b9
++#define mmDIG1_AFMT_RAMP_CONTROL0_BASE_IDX 2
++#define mmDIG1_AFMT_RAMP_CONTROL1 0x19ba
++#define mmDIG1_AFMT_RAMP_CONTROL1_BASE_IDX 2
++#define mmDIG1_AFMT_RAMP_CONTROL2 0x19bb
++#define mmDIG1_AFMT_RAMP_CONTROL2_BASE_IDX 2
++#define mmDIG1_AFMT_RAMP_CONTROL3 0x19bc
++#define mmDIG1_AFMT_RAMP_CONTROL3_BASE_IDX 2
++#define mmDIG1_AFMT_60958_2 0x19bd
++#define mmDIG1_AFMT_60958_2_BASE_IDX 2
++#define mmDIG1_AFMT_AUDIO_CRC_RESULT 0x19be
++#define mmDIG1_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
++#define mmDIG1_AFMT_STATUS 0x19bf
++#define mmDIG1_AFMT_STATUS_BASE_IDX 2
++#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x19c0
++#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
++#define mmDIG1_AFMT_VBI_PACKET_CONTROL 0x19c1
++#define mmDIG1_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
++#define mmDIG1_AFMT_INFOFRAME_CONTROL0 0x19c2
++#define mmDIG1_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
++#define mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x19c3
++#define mmDIG1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
++#define mmDIG1_DIG_BE_CNTL 0x19c5
++#define mmDIG1_DIG_BE_CNTL_BASE_IDX 2
++#define mmDIG1_DIG_BE_EN_CNTL 0x19c6
++#define mmDIG1_DIG_BE_EN_CNTL_BASE_IDX 2
++#define mmDIG1_TMDS_CNTL 0x19e9
++#define mmDIG1_TMDS_CNTL_BASE_IDX 2
++#define mmDIG1_TMDS_CONTROL_CHAR 0x19ea
++#define mmDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2
++#define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x19eb
++#define mmDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
++#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x19ec
++#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
++#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x19ed
++#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
++#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x19ee
++#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
++#define mmDIG1_TMDS_CTL_BITS 0x19f0
++#define mmDIG1_TMDS_CTL_BITS_BASE_IDX 2
++#define mmDIG1_TMDS_DCBALANCER_CONTROL 0x19f1
++#define mmDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
++#define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x19f3
++#define mmDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
++#define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x19f4
++#define mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
++#define mmDIG1_DIG_VERSION 0x19f6
++#define mmDIG1_DIG_VERSION_BASE_IDX 2
++#define mmDIG1_DIG_LANE_ENABLE 0x19f7
++#define mmDIG1_DIG_LANE_ENABLE_BASE_IDX 2
++#define mmDIG1_AFMT_CNTL 0x19fc
++#define mmDIG1_AFMT_CNTL_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dp1_dispdec
++// base address: 0x400
++#define mmDP1_DP_LINK_CNTL 0x1a1e
++#define mmDP1_DP_LINK_CNTL_BASE_IDX 2
++#define mmDP1_DP_PIXEL_FORMAT 0x1a1f
++#define mmDP1_DP_PIXEL_FORMAT_BASE_IDX 2
++#define mmDP1_DP_MSA_COLORIMETRY 0x1a20
++#define mmDP1_DP_MSA_COLORIMETRY_BASE_IDX 2
++#define mmDP1_DP_CONFIG 0x1a21
++#define mmDP1_DP_CONFIG_BASE_IDX 2
++#define mmDP1_DP_VID_STREAM_CNTL 0x1a22
++#define mmDP1_DP_VID_STREAM_CNTL_BASE_IDX 2
++#define mmDP1_DP_STEER_FIFO 0x1a23
++#define mmDP1_DP_STEER_FIFO_BASE_IDX 2
++#define mmDP1_DP_MSA_MISC 0x1a24
++#define mmDP1_DP_MSA_MISC_BASE_IDX 2
++#define mmDP1_DP_VID_TIMING 0x1a26
++#define mmDP1_DP_VID_TIMING_BASE_IDX 2
++#define mmDP1_DP_VID_N 0x1a27
++#define mmDP1_DP_VID_N_BASE_IDX 2
++#define mmDP1_DP_VID_M 0x1a28
++#define mmDP1_DP_VID_M_BASE_IDX 2
++#define mmDP1_DP_LINK_FRAMING_CNTL 0x1a29
++#define mmDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2
++#define mmDP1_DP_HBR2_EYE_PATTERN 0x1a2a
++#define mmDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2
++#define mmDP1_DP_VID_MSA_VBID 0x1a2b
++#define mmDP1_DP_VID_MSA_VBID_BASE_IDX 2
++#define mmDP1_DP_VID_INTERRUPT_CNTL 0x1a2c
++#define mmDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
++#define mmDP1_DP_DPHY_CNTL 0x1a2d
++#define mmDP1_DP_DPHY_CNTL_BASE_IDX 2
++#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x1a2e
++#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
++#define mmDP1_DP_DPHY_SYM0 0x1a2f
++#define mmDP1_DP_DPHY_SYM0_BASE_IDX 2
++#define mmDP1_DP_DPHY_SYM1 0x1a30
++#define mmDP1_DP_DPHY_SYM1_BASE_IDX 2
++#define mmDP1_DP_DPHY_SYM2 0x1a31
++#define mmDP1_DP_DPHY_SYM2_BASE_IDX 2
++#define mmDP1_DP_DPHY_8B10B_CNTL 0x1a32
++#define mmDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2
++#define mmDP1_DP_DPHY_PRBS_CNTL 0x1a33
++#define mmDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2
++#define mmDP1_DP_DPHY_SCRAM_CNTL 0x1a34
++#define mmDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
++#define mmDP1_DP_DPHY_CRC_EN 0x1a35
++#define mmDP1_DP_DPHY_CRC_EN_BASE_IDX 2
++#define mmDP1_DP_DPHY_CRC_CNTL 0x1a36
++#define mmDP1_DP_DPHY_CRC_CNTL_BASE_IDX 2
++#define mmDP1_DP_DPHY_CRC_RESULT 0x1a37
++#define mmDP1_DP_DPHY_CRC_RESULT_BASE_IDX 2
++#define mmDP1_DP_DPHY_CRC_MST_CNTL 0x1a38
++#define mmDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
++#define mmDP1_DP_DPHY_CRC_MST_STATUS 0x1a39
++#define mmDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
++#define mmDP1_DP_DPHY_FAST_TRAINING 0x1a3a
++#define mmDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2
++#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x1a3b
++#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
++#define mmDP1_DP_MSA_V_TIMING_OVERRIDE1 0x1a3c
++#define mmDP1_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2
++#define mmDP1_DP_MSA_V_TIMING_OVERRIDE2 0x1a3d
++#define mmDP1_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2
++#define mmDP1_DP_SEC_CNTL 0x1a41
++#define mmDP1_DP_SEC_CNTL_BASE_IDX 2
++#define mmDP1_DP_SEC_CNTL1 0x1a42
++#define mmDP1_DP_SEC_CNTL1_BASE_IDX 2
++#define mmDP1_DP_SEC_FRAMING1 0x1a43
++#define mmDP1_DP_SEC_FRAMING1_BASE_IDX 2
++#define mmDP1_DP_SEC_FRAMING2 0x1a44
++#define mmDP1_DP_SEC_FRAMING2_BASE_IDX 2
++#define mmDP1_DP_SEC_FRAMING3 0x1a45
++#define mmDP1_DP_SEC_FRAMING3_BASE_IDX 2
++#define mmDP1_DP_SEC_FRAMING4 0x1a46
++#define mmDP1_DP_SEC_FRAMING4_BASE_IDX 2
++#define mmDP1_DP_SEC_AUD_N 0x1a47
++#define mmDP1_DP_SEC_AUD_N_BASE_IDX 2
++#define mmDP1_DP_SEC_AUD_N_READBACK 0x1a48
++#define mmDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2
++#define mmDP1_DP_SEC_AUD_M 0x1a49
++#define mmDP1_DP_SEC_AUD_M_BASE_IDX 2
++#define mmDP1_DP_SEC_AUD_M_READBACK 0x1a4a
++#define mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2
++#define mmDP1_DP_SEC_TIMESTAMP 0x1a4b
++#define mmDP1_DP_SEC_TIMESTAMP_BASE_IDX 2
++#define mmDP1_DP_SEC_PACKET_CNTL 0x1a4c
++#define mmDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2
++#define mmDP1_DP_MSE_RATE_CNTL 0x1a4d
++#define mmDP1_DP_MSE_RATE_CNTL_BASE_IDX 2
++#define mmDP1_DP_MSE_RATE_UPDATE 0x1a4f
++#define mmDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2
++#define mmDP1_DP_MSE_SAT0 0x1a50
++#define mmDP1_DP_MSE_SAT0_BASE_IDX 2
++#define mmDP1_DP_MSE_SAT1 0x1a51
++#define mmDP1_DP_MSE_SAT1_BASE_IDX 2
++#define mmDP1_DP_MSE_SAT2 0x1a52
++#define mmDP1_DP_MSE_SAT2_BASE_IDX 2
++#define mmDP1_DP_MSE_SAT_UPDATE 0x1a53
++#define mmDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2
++#define mmDP1_DP_MSE_LINK_TIMING 0x1a54
++#define mmDP1_DP_MSE_LINK_TIMING_BASE_IDX 2
++#define mmDP1_DP_MSE_MISC_CNTL 0x1a55
++#define mmDP1_DP_MSE_MISC_CNTL_BASE_IDX 2
++#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x1a5a
++#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
++#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x1a5b
++#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
++#define mmDP1_DP_MSE_SAT0_STATUS 0x1a5d
++#define mmDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2
++#define mmDP1_DP_MSE_SAT1_STATUS 0x1a5e
++#define mmDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2
++#define mmDP1_DP_MSE_SAT2_STATUS 0x1a5f
++#define mmDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dig2_dispdec
++// base address: 0x800
++#define mmDIG2_DIG_FE_CNTL 0x1a7e
++#define mmDIG2_DIG_FE_CNTL_BASE_IDX 2
++#define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x1a7f
++#define mmDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
++#define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x1a80
++#define mmDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
++#define mmDIG2_DIG_CLOCK_PATTERN 0x1a81
++#define mmDIG2_DIG_CLOCK_PATTERN_BASE_IDX 2
++#define mmDIG2_DIG_TEST_PATTERN 0x1a82
++#define mmDIG2_DIG_TEST_PATTERN_BASE_IDX 2
++#define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x1a83
++#define mmDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
++#define mmDIG2_DIG_FIFO_STATUS 0x1a84
++#define mmDIG2_DIG_FIFO_STATUS_BASE_IDX 2
++#define mmDIG2_HDMI_CONTROL 0x1a87
++#define mmDIG2_HDMI_CONTROL_BASE_IDX 2
++#define mmDIG2_HDMI_STATUS 0x1a88
++#define mmDIG2_HDMI_STATUS_BASE_IDX 2
++#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x1a89
++#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
++#define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x1a8a
++#define mmDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
++#define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x1a8b
++#define mmDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
++#define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x1a8c
++#define mmDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
++#define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x1a8d
++#define mmDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
++#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x1a8e
++#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
++#define mmDIG2_AFMT_INTERRUPT_STATUS 0x1a8f
++#define mmDIG2_AFMT_INTERRUPT_STATUS_BASE_IDX 2
++#define mmDIG2_HDMI_GC 0x1a91
++#define mmDIG2_HDMI_GC_BASE_IDX 2
++#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x1a92
++#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
++#define mmDIG2_AFMT_ISRC1_0 0x1a93
++#define mmDIG2_AFMT_ISRC1_0_BASE_IDX 2
++#define mmDIG2_AFMT_ISRC1_1 0x1a94
++#define mmDIG2_AFMT_ISRC1_1_BASE_IDX 2
++#define mmDIG2_AFMT_ISRC1_2 0x1a95
++#define mmDIG2_AFMT_ISRC1_2_BASE_IDX 2
++#define mmDIG2_AFMT_ISRC1_3 0x1a96
++#define mmDIG2_AFMT_ISRC1_3_BASE_IDX 2
++#define mmDIG2_AFMT_ISRC1_4 0x1a97
++#define mmDIG2_AFMT_ISRC1_4_BASE_IDX 2
++#define mmDIG2_AFMT_ISRC2_0 0x1a98
++#define mmDIG2_AFMT_ISRC2_0_BASE_IDX 2
++#define mmDIG2_AFMT_ISRC2_1 0x1a99
++#define mmDIG2_AFMT_ISRC2_1_BASE_IDX 2
++#define mmDIG2_AFMT_ISRC2_2 0x1a9a
++#define mmDIG2_AFMT_ISRC2_2_BASE_IDX 2
++#define mmDIG2_AFMT_ISRC2_3 0x1a9b
++#define mmDIG2_AFMT_ISRC2_3_BASE_IDX 2
++#define mmDIG2_AFMT_AVI_INFO0 0x1a9c
++#define mmDIG2_AFMT_AVI_INFO0_BASE_IDX 2
++#define mmDIG2_AFMT_AVI_INFO1 0x1a9d
++#define mmDIG2_AFMT_AVI_INFO1_BASE_IDX 2
++#define mmDIG2_AFMT_AVI_INFO2 0x1a9e
++#define mmDIG2_AFMT_AVI_INFO2_BASE_IDX 2
++#define mmDIG2_AFMT_AVI_INFO3 0x1a9f
++#define mmDIG2_AFMT_AVI_INFO3_BASE_IDX 2
++#define mmDIG2_AFMT_MPEG_INFO0 0x1aa0
++#define mmDIG2_AFMT_MPEG_INFO0_BASE_IDX 2
++#define mmDIG2_AFMT_MPEG_INFO1 0x1aa1
++#define mmDIG2_AFMT_MPEG_INFO1_BASE_IDX 2
++#define mmDIG2_AFMT_GENERIC_HDR 0x1aa2
++#define mmDIG2_AFMT_GENERIC_HDR_BASE_IDX 2
++#define mmDIG2_AFMT_GENERIC_0 0x1aa3
++#define mmDIG2_AFMT_GENERIC_0_BASE_IDX 2
++#define mmDIG2_AFMT_GENERIC_1 0x1aa4
++#define mmDIG2_AFMT_GENERIC_1_BASE_IDX 2
++#define mmDIG2_AFMT_GENERIC_2 0x1aa5
++#define mmDIG2_AFMT_GENERIC_2_BASE_IDX 2
++#define mmDIG2_AFMT_GENERIC_3 0x1aa6
++#define mmDIG2_AFMT_GENERIC_3_BASE_IDX 2
++#define mmDIG2_AFMT_GENERIC_4 0x1aa7
++#define mmDIG2_AFMT_GENERIC_4_BASE_IDX 2
++#define mmDIG2_AFMT_GENERIC_5 0x1aa8
++#define mmDIG2_AFMT_GENERIC_5_BASE_IDX 2
++#define mmDIG2_AFMT_GENERIC_6 0x1aa9
++#define mmDIG2_AFMT_GENERIC_6_BASE_IDX 2
++#define mmDIG2_AFMT_GENERIC_7 0x1aaa
++#define mmDIG2_AFMT_GENERIC_7_BASE_IDX 2
++#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x1aab
++#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
++#define mmDIG2_HDMI_ACR_32_0 0x1aac
++#define mmDIG2_HDMI_ACR_32_0_BASE_IDX 2
++#define mmDIG2_HDMI_ACR_32_1 0x1aad
++#define mmDIG2_HDMI_ACR_32_1_BASE_IDX 2
++#define mmDIG2_HDMI_ACR_44_0 0x1aae
++#define mmDIG2_HDMI_ACR_44_0_BASE_IDX 2
++#define mmDIG2_HDMI_ACR_44_1 0x1aaf
++#define mmDIG2_HDMI_ACR_44_1_BASE_IDX 2
++#define mmDIG2_HDMI_ACR_48_0 0x1ab0
++#define mmDIG2_HDMI_ACR_48_0_BASE_IDX 2
++#define mmDIG2_HDMI_ACR_48_1 0x1ab1
++#define mmDIG2_HDMI_ACR_48_1_BASE_IDX 2
++#define mmDIG2_HDMI_ACR_STATUS_0 0x1ab2
++#define mmDIG2_HDMI_ACR_STATUS_0_BASE_IDX 2
++#define mmDIG2_HDMI_ACR_STATUS_1 0x1ab3
++#define mmDIG2_HDMI_ACR_STATUS_1_BASE_IDX 2
++#define mmDIG2_AFMT_AUDIO_INFO0 0x1ab4
++#define mmDIG2_AFMT_AUDIO_INFO0_BASE_IDX 2
++#define mmDIG2_AFMT_AUDIO_INFO1 0x1ab5
++#define mmDIG2_AFMT_AUDIO_INFO1_BASE_IDX 2
++#define mmDIG2_AFMT_60958_0 0x1ab6
++#define mmDIG2_AFMT_60958_0_BASE_IDX 2
++#define mmDIG2_AFMT_60958_1 0x1ab7
++#define mmDIG2_AFMT_60958_1_BASE_IDX 2
++#define mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x1ab8
++#define mmDIG2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
++#define mmDIG2_AFMT_RAMP_CONTROL0 0x1ab9
++#define mmDIG2_AFMT_RAMP_CONTROL0_BASE_IDX 2
++#define mmDIG2_AFMT_RAMP_CONTROL1 0x1aba
++#define mmDIG2_AFMT_RAMP_CONTROL1_BASE_IDX 2
++#define mmDIG2_AFMT_RAMP_CONTROL2 0x1abb
++#define mmDIG2_AFMT_RAMP_CONTROL2_BASE_IDX 2
++#define mmDIG2_AFMT_RAMP_CONTROL3 0x1abc
++#define mmDIG2_AFMT_RAMP_CONTROL3_BASE_IDX 2
++#define mmDIG2_AFMT_60958_2 0x1abd
++#define mmDIG2_AFMT_60958_2_BASE_IDX 2
++#define mmDIG2_AFMT_AUDIO_CRC_RESULT 0x1abe
++#define mmDIG2_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
++#define mmDIG2_AFMT_STATUS 0x1abf
++#define mmDIG2_AFMT_STATUS_BASE_IDX 2
++#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x1ac0
++#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
++#define mmDIG2_AFMT_VBI_PACKET_CONTROL 0x1ac1
++#define mmDIG2_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
++#define mmDIG2_AFMT_INFOFRAME_CONTROL0 0x1ac2
++#define mmDIG2_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
++#define mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x1ac3
++#define mmDIG2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
++#define mmDIG2_DIG_BE_CNTL 0x1ac5
++#define mmDIG2_DIG_BE_CNTL_BASE_IDX 2
++#define mmDIG2_DIG_BE_EN_CNTL 0x1ac6
++#define mmDIG2_DIG_BE_EN_CNTL_BASE_IDX 2
++#define mmDIG2_TMDS_CNTL 0x1ae9
++#define mmDIG2_TMDS_CNTL_BASE_IDX 2
++#define mmDIG2_TMDS_CONTROL_CHAR 0x1aea
++#define mmDIG2_TMDS_CONTROL_CHAR_BASE_IDX 2
++#define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x1aeb
++#define mmDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
++#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x1aec
++#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
++#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x1aed
++#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
++#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x1aee
++#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
++#define mmDIG2_TMDS_CTL_BITS 0x1af0
++#define mmDIG2_TMDS_CTL_BITS_BASE_IDX 2
++#define mmDIG2_TMDS_DCBALANCER_CONTROL 0x1af1
++#define mmDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
++#define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x1af3
++#define mmDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
++#define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x1af4
++#define mmDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
++#define mmDIG2_DIG_VERSION 0x1af6
++#define mmDIG2_DIG_VERSION_BASE_IDX 2
++#define mmDIG2_DIG_LANE_ENABLE 0x1af7
++#define mmDIG2_DIG_LANE_ENABLE_BASE_IDX 2
++#define mmDIG2_AFMT_CNTL 0x1afc
++#define mmDIG2_AFMT_CNTL_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dp2_dispdec
++// base address: 0x800
++#define mmDP2_DP_LINK_CNTL 0x1b1e
++#define mmDP2_DP_LINK_CNTL_BASE_IDX 2
++#define mmDP2_DP_PIXEL_FORMAT 0x1b1f
++#define mmDP2_DP_PIXEL_FORMAT_BASE_IDX 2
++#define mmDP2_DP_MSA_COLORIMETRY 0x1b20
++#define mmDP2_DP_MSA_COLORIMETRY_BASE_IDX 2
++#define mmDP2_DP_CONFIG 0x1b21
++#define mmDP2_DP_CONFIG_BASE_IDX 2
++#define mmDP2_DP_VID_STREAM_CNTL 0x1b22
++#define mmDP2_DP_VID_STREAM_CNTL_BASE_IDX 2
++#define mmDP2_DP_STEER_FIFO 0x1b23
++#define mmDP2_DP_STEER_FIFO_BASE_IDX 2
++#define mmDP2_DP_MSA_MISC 0x1b24
++#define mmDP2_DP_MSA_MISC_BASE_IDX 2
++#define mmDP2_DP_VID_TIMING 0x1b26
++#define mmDP2_DP_VID_TIMING_BASE_IDX 2
++#define mmDP2_DP_VID_N 0x1b27
++#define mmDP2_DP_VID_N_BASE_IDX 2
++#define mmDP2_DP_VID_M 0x1b28
++#define mmDP2_DP_VID_M_BASE_IDX 2
++#define mmDP2_DP_LINK_FRAMING_CNTL 0x1b29
++#define mmDP2_DP_LINK_FRAMING_CNTL_BASE_IDX 2
++#define mmDP2_DP_HBR2_EYE_PATTERN 0x1b2a
++#define mmDP2_DP_HBR2_EYE_PATTERN_BASE_IDX 2
++#define mmDP2_DP_VID_MSA_VBID 0x1b2b
++#define mmDP2_DP_VID_MSA_VBID_BASE_IDX 2
++#define mmDP2_DP_VID_INTERRUPT_CNTL 0x1b2c
++#define mmDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
++#define mmDP2_DP_DPHY_CNTL 0x1b2d
++#define mmDP2_DP_DPHY_CNTL_BASE_IDX 2
++#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x1b2e
++#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
++#define mmDP2_DP_DPHY_SYM0 0x1b2f
++#define mmDP2_DP_DPHY_SYM0_BASE_IDX 2
++#define mmDP2_DP_DPHY_SYM1 0x1b30
++#define mmDP2_DP_DPHY_SYM1_BASE_IDX 2
++#define mmDP2_DP_DPHY_SYM2 0x1b31
++#define mmDP2_DP_DPHY_SYM2_BASE_IDX 2
++#define mmDP2_DP_DPHY_8B10B_CNTL 0x1b32
++#define mmDP2_DP_DPHY_8B10B_CNTL_BASE_IDX 2
++#define mmDP2_DP_DPHY_PRBS_CNTL 0x1b33
++#define mmDP2_DP_DPHY_PRBS_CNTL_BASE_IDX 2
++#define mmDP2_DP_DPHY_SCRAM_CNTL 0x1b34
++#define mmDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
++#define mmDP2_DP_DPHY_CRC_EN 0x1b35
++#define mmDP2_DP_DPHY_CRC_EN_BASE_IDX 2
++#define mmDP2_DP_DPHY_CRC_CNTL 0x1b36
++#define mmDP2_DP_DPHY_CRC_CNTL_BASE_IDX 2
++#define mmDP2_DP_DPHY_CRC_RESULT 0x1b37
++#define mmDP2_DP_DPHY_CRC_RESULT_BASE_IDX 2
++#define mmDP2_DP_DPHY_CRC_MST_CNTL 0x1b38
++#define mmDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
++#define mmDP2_DP_DPHY_CRC_MST_STATUS 0x1b39
++#define mmDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
++#define mmDP2_DP_DPHY_FAST_TRAINING 0x1b3a
++#define mmDP2_DP_DPHY_FAST_TRAINING_BASE_IDX 2
++#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x1b3b
++#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
++#define mmDP2_DP_MSA_V_TIMING_OVERRIDE1 0x1b3c
++#define mmDP2_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2
++#define mmDP2_DP_MSA_V_TIMING_OVERRIDE2 0x1b3d
++#define mmDP2_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2
++#define mmDP2_DP_SEC_CNTL 0x1b41
++#define mmDP2_DP_SEC_CNTL_BASE_IDX 2
++#define mmDP2_DP_SEC_CNTL1 0x1b42
++#define mmDP2_DP_SEC_CNTL1_BASE_IDX 2
++#define mmDP2_DP_SEC_FRAMING1 0x1b43
++#define mmDP2_DP_SEC_FRAMING1_BASE_IDX 2
++#define mmDP2_DP_SEC_FRAMING2 0x1b44
++#define mmDP2_DP_SEC_FRAMING2_BASE_IDX 2
++#define mmDP2_DP_SEC_FRAMING3 0x1b45
++#define mmDP2_DP_SEC_FRAMING3_BASE_IDX 2
++#define mmDP2_DP_SEC_FRAMING4 0x1b46
++#define mmDP2_DP_SEC_FRAMING4_BASE_IDX 2
++#define mmDP2_DP_SEC_AUD_N 0x1b47
++#define mmDP2_DP_SEC_AUD_N_BASE_IDX 2
++#define mmDP2_DP_SEC_AUD_N_READBACK 0x1b48
++#define mmDP2_DP_SEC_AUD_N_READBACK_BASE_IDX 2
++#define mmDP2_DP_SEC_AUD_M 0x1b49
++#define mmDP2_DP_SEC_AUD_M_BASE_IDX 2
++#define mmDP2_DP_SEC_AUD_M_READBACK 0x1b4a
++#define mmDP2_DP_SEC_AUD_M_READBACK_BASE_IDX 2
++#define mmDP2_DP_SEC_TIMESTAMP 0x1b4b
++#define mmDP2_DP_SEC_TIMESTAMP_BASE_IDX 2
++#define mmDP2_DP_SEC_PACKET_CNTL 0x1b4c
++#define mmDP2_DP_SEC_PACKET_CNTL_BASE_IDX 2
++#define mmDP2_DP_MSE_RATE_CNTL 0x1b4d
++#define mmDP2_DP_MSE_RATE_CNTL_BASE_IDX 2
++#define mmDP2_DP_MSE_RATE_UPDATE 0x1b4f
++#define mmDP2_DP_MSE_RATE_UPDATE_BASE_IDX 2
++#define mmDP2_DP_MSE_SAT0 0x1b50
++#define mmDP2_DP_MSE_SAT0_BASE_IDX 2
++#define mmDP2_DP_MSE_SAT1 0x1b51
++#define mmDP2_DP_MSE_SAT1_BASE_IDX 2
++#define mmDP2_DP_MSE_SAT2 0x1b52
++#define mmDP2_DP_MSE_SAT2_BASE_IDX 2
++#define mmDP2_DP_MSE_SAT_UPDATE 0x1b53
++#define mmDP2_DP_MSE_SAT_UPDATE_BASE_IDX 2
++#define mmDP2_DP_MSE_LINK_TIMING 0x1b54
++#define mmDP2_DP_MSE_LINK_TIMING_BASE_IDX 2
++#define mmDP2_DP_MSE_MISC_CNTL 0x1b55
++#define mmDP2_DP_MSE_MISC_CNTL_BASE_IDX 2
++#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x1b5a
++#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
++#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x1b5b
++#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
++#define mmDP2_DP_MSE_SAT0_STATUS 0x1b5d
++#define mmDP2_DP_MSE_SAT0_STATUS_BASE_IDX 2
++#define mmDP2_DP_MSE_SAT1_STATUS 0x1b5e
++#define mmDP2_DP_MSE_SAT1_STATUS_BASE_IDX 2
++#define mmDP2_DP_MSE_SAT2_STATUS 0x1b5f
++#define mmDP2_DP_MSE_SAT2_STATUS_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dig3_dispdec
++// base address: 0xc00
++#define mmDIG3_DIG_FE_CNTL 0x1b7e
++#define mmDIG3_DIG_FE_CNTL_BASE_IDX 2
++#define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x1b7f
++#define mmDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
++#define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x1b80
++#define mmDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
++#define mmDIG3_DIG_CLOCK_PATTERN 0x1b81
++#define mmDIG3_DIG_CLOCK_PATTERN_BASE_IDX 2
++#define mmDIG3_DIG_TEST_PATTERN 0x1b82
++#define mmDIG3_DIG_TEST_PATTERN_BASE_IDX 2
++#define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x1b83
++#define mmDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
++#define mmDIG3_DIG_FIFO_STATUS 0x1b84
++#define mmDIG3_DIG_FIFO_STATUS_BASE_IDX 2
++#define mmDIG3_HDMI_CONTROL 0x1b87
++#define mmDIG3_HDMI_CONTROL_BASE_IDX 2
++#define mmDIG3_HDMI_STATUS 0x1b88
++#define mmDIG3_HDMI_STATUS_BASE_IDX 2
++#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x1b89
++#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
++#define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x1b8a
++#define mmDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
++#define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x1b8b
++#define mmDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
++#define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x1b8c
++#define mmDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
++#define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x1b8d
++#define mmDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
++#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x1b8e
++#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
++#define mmDIG3_AFMT_INTERRUPT_STATUS 0x1b8f
++#define mmDIG3_AFMT_INTERRUPT_STATUS_BASE_IDX 2
++#define mmDIG3_HDMI_GC 0x1b91
++#define mmDIG3_HDMI_GC_BASE_IDX 2
++#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x1b92
++#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
++#define mmDIG3_AFMT_ISRC1_0 0x1b93
++#define mmDIG3_AFMT_ISRC1_0_BASE_IDX 2
++#define mmDIG3_AFMT_ISRC1_1 0x1b94
++#define mmDIG3_AFMT_ISRC1_1_BASE_IDX 2
++#define mmDIG3_AFMT_ISRC1_2 0x1b95
++#define mmDIG3_AFMT_ISRC1_2_BASE_IDX 2
++#define mmDIG3_AFMT_ISRC1_3 0x1b96
++#define mmDIG3_AFMT_ISRC1_3_BASE_IDX 2
++#define mmDIG3_AFMT_ISRC1_4 0x1b97
++#define mmDIG3_AFMT_ISRC1_4_BASE_IDX 2
++#define mmDIG3_AFMT_ISRC2_0 0x1b98
++#define mmDIG3_AFMT_ISRC2_0_BASE_IDX 2
++#define mmDIG3_AFMT_ISRC2_1 0x1b99
++#define mmDIG3_AFMT_ISRC2_1_BASE_IDX 2
++#define mmDIG3_AFMT_ISRC2_2 0x1b9a
++#define mmDIG3_AFMT_ISRC2_2_BASE_IDX 2
++#define mmDIG3_AFMT_ISRC2_3 0x1b9b
++#define mmDIG3_AFMT_ISRC2_3_BASE_IDX 2
++#define mmDIG3_AFMT_AVI_INFO0 0x1b9c
++#define mmDIG3_AFMT_AVI_INFO0_BASE_IDX 2
++#define mmDIG3_AFMT_AVI_INFO1 0x1b9d
++#define mmDIG3_AFMT_AVI_INFO1_BASE_IDX 2
++#define mmDIG3_AFMT_AVI_INFO2 0x1b9e
++#define mmDIG3_AFMT_AVI_INFO2_BASE_IDX 2
++#define mmDIG3_AFMT_AVI_INFO3 0x1b9f
++#define mmDIG3_AFMT_AVI_INFO3_BASE_IDX 2
++#define mmDIG3_AFMT_MPEG_INFO0 0x1ba0
++#define mmDIG3_AFMT_MPEG_INFO0_BASE_IDX 2
++#define mmDIG3_AFMT_MPEG_INFO1 0x1ba1
++#define mmDIG3_AFMT_MPEG_INFO1_BASE_IDX 2
++#define mmDIG3_AFMT_GENERIC_HDR 0x1ba2
++#define mmDIG3_AFMT_GENERIC_HDR_BASE_IDX 2
++#define mmDIG3_AFMT_GENERIC_0 0x1ba3
++#define mmDIG3_AFMT_GENERIC_0_BASE_IDX 2
++#define mmDIG3_AFMT_GENERIC_1 0x1ba4
++#define mmDIG3_AFMT_GENERIC_1_BASE_IDX 2
++#define mmDIG3_AFMT_GENERIC_2 0x1ba5
++#define mmDIG3_AFMT_GENERIC_2_BASE_IDX 2
++#define mmDIG3_AFMT_GENERIC_3 0x1ba6
++#define mmDIG3_AFMT_GENERIC_3_BASE_IDX 2
++#define mmDIG3_AFMT_GENERIC_4 0x1ba7
++#define mmDIG3_AFMT_GENERIC_4_BASE_IDX 2
++#define mmDIG3_AFMT_GENERIC_5 0x1ba8
++#define mmDIG3_AFMT_GENERIC_5_BASE_IDX 2
++#define mmDIG3_AFMT_GENERIC_6 0x1ba9
++#define mmDIG3_AFMT_GENERIC_6_BASE_IDX 2
++#define mmDIG3_AFMT_GENERIC_7 0x1baa
++#define mmDIG3_AFMT_GENERIC_7_BASE_IDX 2
++#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x1bab
++#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
++#define mmDIG3_HDMI_ACR_32_0 0x1bac
++#define mmDIG3_HDMI_ACR_32_0_BASE_IDX 2
++#define mmDIG3_HDMI_ACR_32_1 0x1bad
++#define mmDIG3_HDMI_ACR_32_1_BASE_IDX 2
++#define mmDIG3_HDMI_ACR_44_0 0x1bae
++#define mmDIG3_HDMI_ACR_44_0_BASE_IDX 2
++#define mmDIG3_HDMI_ACR_44_1 0x1baf
++#define mmDIG3_HDMI_ACR_44_1_BASE_IDX 2
++#define mmDIG3_HDMI_ACR_48_0 0x1bb0
++#define mmDIG3_HDMI_ACR_48_0_BASE_IDX 2
++#define mmDIG3_HDMI_ACR_48_1 0x1bb1
++#define mmDIG3_HDMI_ACR_48_1_BASE_IDX 2
++#define mmDIG3_HDMI_ACR_STATUS_0 0x1bb2
++#define mmDIG3_HDMI_ACR_STATUS_0_BASE_IDX 2
++#define mmDIG3_HDMI_ACR_STATUS_1 0x1bb3
++#define mmDIG3_HDMI_ACR_STATUS_1_BASE_IDX 2
++#define mmDIG3_AFMT_AUDIO_INFO0 0x1bb4
++#define mmDIG3_AFMT_AUDIO_INFO0_BASE_IDX 2
++#define mmDIG3_AFMT_AUDIO_INFO1 0x1bb5
++#define mmDIG3_AFMT_AUDIO_INFO1_BASE_IDX 2
++#define mmDIG3_AFMT_60958_0 0x1bb6
++#define mmDIG3_AFMT_60958_0_BASE_IDX 2
++#define mmDIG3_AFMT_60958_1 0x1bb7
++#define mmDIG3_AFMT_60958_1_BASE_IDX 2
++#define mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x1bb8
++#define mmDIG3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
++#define mmDIG3_AFMT_RAMP_CONTROL0 0x1bb9
++#define mmDIG3_AFMT_RAMP_CONTROL0_BASE_IDX 2
++#define mmDIG3_AFMT_RAMP_CONTROL1 0x1bba
++#define mmDIG3_AFMT_RAMP_CONTROL1_BASE_IDX 2
++#define mmDIG3_AFMT_RAMP_CONTROL2 0x1bbb
++#define mmDIG3_AFMT_RAMP_CONTROL2_BASE_IDX 2
++#define mmDIG3_AFMT_RAMP_CONTROL3 0x1bbc
++#define mmDIG3_AFMT_RAMP_CONTROL3_BASE_IDX 2
++#define mmDIG3_AFMT_60958_2 0x1bbd
++#define mmDIG3_AFMT_60958_2_BASE_IDX 2
++#define mmDIG3_AFMT_AUDIO_CRC_RESULT 0x1bbe
++#define mmDIG3_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
++#define mmDIG3_AFMT_STATUS 0x1bbf
++#define mmDIG3_AFMT_STATUS_BASE_IDX 2
++#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x1bc0
++#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
++#define mmDIG3_AFMT_VBI_PACKET_CONTROL 0x1bc1
++#define mmDIG3_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
++#define mmDIG3_AFMT_INFOFRAME_CONTROL0 0x1bc2
++#define mmDIG3_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
++#define mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x1bc3
++#define mmDIG3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
++#define mmDIG3_DIG_BE_CNTL 0x1bc5
++#define mmDIG3_DIG_BE_CNTL_BASE_IDX 2
++#define mmDIG3_DIG_BE_EN_CNTL 0x1bc6
++#define mmDIG3_DIG_BE_EN_CNTL_BASE_IDX 2
++#define mmDIG3_TMDS_CNTL 0x1be9
++#define mmDIG3_TMDS_CNTL_BASE_IDX 2
++#define mmDIG3_TMDS_CONTROL_CHAR 0x1bea
++#define mmDIG3_TMDS_CONTROL_CHAR_BASE_IDX 2
++#define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x1beb
++#define mmDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
++#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x1bec
++#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
++#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x1bed
++#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
++#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x1bee
++#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
++#define mmDIG3_TMDS_CTL_BITS 0x1bf0
++#define mmDIG3_TMDS_CTL_BITS_BASE_IDX 2
++#define mmDIG3_TMDS_DCBALANCER_CONTROL 0x1bf1
++#define mmDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
++#define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x1bf3
++#define mmDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
++#define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x1bf4
++#define mmDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
++#define mmDIG3_DIG_VERSION 0x1bf6
++#define mmDIG3_DIG_VERSION_BASE_IDX 2
++#define mmDIG3_DIG_LANE_ENABLE 0x1bf7
++#define mmDIG3_DIG_LANE_ENABLE_BASE_IDX 2
++#define mmDIG3_AFMT_CNTL 0x1bfc
++#define mmDIG3_AFMT_CNTL_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dp3_dispdec
++// base address: 0xc00
++#define mmDP3_DP_LINK_CNTL 0x1c1e
++#define mmDP3_DP_LINK_CNTL_BASE_IDX 2
++#define mmDP3_DP_PIXEL_FORMAT 0x1c1f
++#define mmDP3_DP_PIXEL_FORMAT_BASE_IDX 2
++#define mmDP3_DP_MSA_COLORIMETRY 0x1c20
++#define mmDP3_DP_MSA_COLORIMETRY_BASE_IDX 2
++#define mmDP3_DP_CONFIG 0x1c21
++#define mmDP3_DP_CONFIG_BASE_IDX 2
++#define mmDP3_DP_VID_STREAM_CNTL 0x1c22
++#define mmDP3_DP_VID_STREAM_CNTL_BASE_IDX 2
++#define mmDP3_DP_STEER_FIFO 0x1c23
++#define mmDP3_DP_STEER_FIFO_BASE_IDX 2
++#define mmDP3_DP_MSA_MISC 0x1c24
++#define mmDP3_DP_MSA_MISC_BASE_IDX 2
++#define mmDP3_DP_VID_TIMING 0x1c26
++#define mmDP3_DP_VID_TIMING_BASE_IDX 2
++#define mmDP3_DP_VID_N 0x1c27
++#define mmDP3_DP_VID_N_BASE_IDX 2
++#define mmDP3_DP_VID_M 0x1c28
++#define mmDP3_DP_VID_M_BASE_IDX 2
++#define mmDP3_DP_LINK_FRAMING_CNTL 0x1c29
++#define mmDP3_DP_LINK_FRAMING_CNTL_BASE_IDX 2
++#define mmDP3_DP_HBR2_EYE_PATTERN 0x1c2a
++#define mmDP3_DP_HBR2_EYE_PATTERN_BASE_IDX 2
++#define mmDP3_DP_VID_MSA_VBID 0x1c2b
++#define mmDP3_DP_VID_MSA_VBID_BASE_IDX 2
++#define mmDP3_DP_VID_INTERRUPT_CNTL 0x1c2c
++#define mmDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
++#define mmDP3_DP_DPHY_CNTL 0x1c2d
++#define mmDP3_DP_DPHY_CNTL_BASE_IDX 2
++#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x1c2e
++#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
++#define mmDP3_DP_DPHY_SYM0 0x1c2f
++#define mmDP3_DP_DPHY_SYM0_BASE_IDX 2
++#define mmDP3_DP_DPHY_SYM1 0x1c30
++#define mmDP3_DP_DPHY_SYM1_BASE_IDX 2
++#define mmDP3_DP_DPHY_SYM2 0x1c31
++#define mmDP3_DP_DPHY_SYM2_BASE_IDX 2
++#define mmDP3_DP_DPHY_8B10B_CNTL 0x1c32
++#define mmDP3_DP_DPHY_8B10B_CNTL_BASE_IDX 2
++#define mmDP3_DP_DPHY_PRBS_CNTL 0x1c33
++#define mmDP3_DP_DPHY_PRBS_CNTL_BASE_IDX 2
++#define mmDP3_DP_DPHY_SCRAM_CNTL 0x1c34
++#define mmDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
++#define mmDP3_DP_DPHY_CRC_EN 0x1c35
++#define mmDP3_DP_DPHY_CRC_EN_BASE_IDX 2
++#define mmDP3_DP_DPHY_CRC_CNTL 0x1c36
++#define mmDP3_DP_DPHY_CRC_CNTL_BASE_IDX 2
++#define mmDP3_DP_DPHY_CRC_RESULT 0x1c37
++#define mmDP3_DP_DPHY_CRC_RESULT_BASE_IDX 2
++#define mmDP3_DP_DPHY_CRC_MST_CNTL 0x1c38
++#define mmDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
++#define mmDP3_DP_DPHY_CRC_MST_STATUS 0x1c39
++#define mmDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
++#define mmDP3_DP_DPHY_FAST_TRAINING 0x1c3a
++#define mmDP3_DP_DPHY_FAST_TRAINING_BASE_IDX 2
++#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x1c3b
++#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
++#define mmDP3_DP_MSA_V_TIMING_OVERRIDE1 0x1c3c
++#define mmDP3_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2
++#define mmDP3_DP_MSA_V_TIMING_OVERRIDE2 0x1c3d
++#define mmDP3_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2
++#define mmDP3_DP_SEC_CNTL 0x1c41
++#define mmDP3_DP_SEC_CNTL_BASE_IDX 2
++#define mmDP3_DP_SEC_CNTL1 0x1c42
++#define mmDP3_DP_SEC_CNTL1_BASE_IDX 2
++#define mmDP3_DP_SEC_FRAMING1 0x1c43
++#define mmDP3_DP_SEC_FRAMING1_BASE_IDX 2
++#define mmDP3_DP_SEC_FRAMING2 0x1c44
++#define mmDP3_DP_SEC_FRAMING2_BASE_IDX 2
++#define mmDP3_DP_SEC_FRAMING3 0x1c45
++#define mmDP3_DP_SEC_FRAMING3_BASE_IDX 2
++#define mmDP3_DP_SEC_FRAMING4 0x1c46
++#define mmDP3_DP_SEC_FRAMING4_BASE_IDX 2
++#define mmDP3_DP_SEC_AUD_N 0x1c47
++#define mmDP3_DP_SEC_AUD_N_BASE_IDX 2
++#define mmDP3_DP_SEC_AUD_N_READBACK 0x1c48
++#define mmDP3_DP_SEC_AUD_N_READBACK_BASE_IDX 2
++#define mmDP3_DP_SEC_AUD_M 0x1c49
++#define mmDP3_DP_SEC_AUD_M_BASE_IDX 2
++#define mmDP3_DP_SEC_AUD_M_READBACK 0x1c4a
++#define mmDP3_DP_SEC_AUD_M_READBACK_BASE_IDX 2
++#define mmDP3_DP_SEC_TIMESTAMP 0x1c4b
++#define mmDP3_DP_SEC_TIMESTAMP_BASE_IDX 2
++#define mmDP3_DP_SEC_PACKET_CNTL 0x1c4c
++#define mmDP3_DP_SEC_PACKET_CNTL_BASE_IDX 2
++#define mmDP3_DP_MSE_RATE_CNTL 0x1c4d
++#define mmDP3_DP_MSE_RATE_CNTL_BASE_IDX 2
++#define mmDP3_DP_MSE_RATE_UPDATE 0x1c4f
++#define mmDP3_DP_MSE_RATE_UPDATE_BASE_IDX 2
++#define mmDP3_DP_MSE_SAT0 0x1c50
++#define mmDP3_DP_MSE_SAT0_BASE_IDX 2
++#define mmDP3_DP_MSE_SAT1 0x1c51
++#define mmDP3_DP_MSE_SAT1_BASE_IDX 2
++#define mmDP3_DP_MSE_SAT2 0x1c52
++#define mmDP3_DP_MSE_SAT2_BASE_IDX 2
++#define mmDP3_DP_MSE_SAT_UPDATE 0x1c53
++#define mmDP3_DP_MSE_SAT_UPDATE_BASE_IDX 2
++#define mmDP3_DP_MSE_LINK_TIMING 0x1c54
++#define mmDP3_DP_MSE_LINK_TIMING_BASE_IDX 2
++#define mmDP3_DP_MSE_MISC_CNTL 0x1c55
++#define mmDP3_DP_MSE_MISC_CNTL_BASE_IDX 2
++#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x1c5a
++#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
++#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x1c5b
++#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
++#define mmDP3_DP_MSE_SAT0_STATUS 0x1c5d
++#define mmDP3_DP_MSE_SAT0_STATUS_BASE_IDX 2
++#define mmDP3_DP_MSE_SAT1_STATUS 0x1c5e
++#define mmDP3_DP_MSE_SAT1_STATUS_BASE_IDX 2
++#define mmDP3_DP_MSE_SAT2_STATUS 0x1c5f
++#define mmDP3_DP_MSE_SAT2_STATUS_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dig4_dispdec
++// base address: 0x1000
++#define mmDIG4_DIG_FE_CNTL 0x1c7e
++#define mmDIG4_DIG_FE_CNTL_BASE_IDX 2
++#define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x1c7f
++#define mmDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
++#define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x1c80
++#define mmDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
++#define mmDIG4_DIG_CLOCK_PATTERN 0x1c81
++#define mmDIG4_DIG_CLOCK_PATTERN_BASE_IDX 2
++#define mmDIG4_DIG_TEST_PATTERN 0x1c82
++#define mmDIG4_DIG_TEST_PATTERN_BASE_IDX 2
++#define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x1c83
++#define mmDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
++#define mmDIG4_DIG_FIFO_STATUS 0x1c84
++#define mmDIG4_DIG_FIFO_STATUS_BASE_IDX 2
++#define mmDIG4_HDMI_CONTROL 0x1c87
++#define mmDIG4_HDMI_CONTROL_BASE_IDX 2
++#define mmDIG4_HDMI_STATUS 0x1c88
++#define mmDIG4_HDMI_STATUS_BASE_IDX 2
++#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x1c89
++#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
++#define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x1c8a
++#define mmDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
++#define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x1c8b
++#define mmDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
++#define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x1c8c
++#define mmDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
++#define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x1c8d
++#define mmDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
++#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x1c8e
++#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
++#define mmDIG4_AFMT_INTERRUPT_STATUS 0x1c8f
++#define mmDIG4_AFMT_INTERRUPT_STATUS_BASE_IDX 2
++#define mmDIG4_HDMI_GC 0x1c91
++#define mmDIG4_HDMI_GC_BASE_IDX 2
++#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x1c92
++#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
++#define mmDIG4_AFMT_ISRC1_0 0x1c93
++#define mmDIG4_AFMT_ISRC1_0_BASE_IDX 2
++#define mmDIG4_AFMT_ISRC1_1 0x1c94
++#define mmDIG4_AFMT_ISRC1_1_BASE_IDX 2
++#define mmDIG4_AFMT_ISRC1_2 0x1c95
++#define mmDIG4_AFMT_ISRC1_2_BASE_IDX 2
++#define mmDIG4_AFMT_ISRC1_3 0x1c96
++#define mmDIG4_AFMT_ISRC1_3_BASE_IDX 2
++#define mmDIG4_AFMT_ISRC1_4 0x1c97
++#define mmDIG4_AFMT_ISRC1_4_BASE_IDX 2
++#define mmDIG4_AFMT_ISRC2_0 0x1c98
++#define mmDIG4_AFMT_ISRC2_0_BASE_IDX 2
++#define mmDIG4_AFMT_ISRC2_1 0x1c99
++#define mmDIG4_AFMT_ISRC2_1_BASE_IDX 2
++#define mmDIG4_AFMT_ISRC2_2 0x1c9a
++#define mmDIG4_AFMT_ISRC2_2_BASE_IDX 2
++#define mmDIG4_AFMT_ISRC2_3 0x1c9b
++#define mmDIG4_AFMT_ISRC2_3_BASE_IDX 2
++#define mmDIG4_AFMT_AVI_INFO0 0x1c9c
++#define mmDIG4_AFMT_AVI_INFO0_BASE_IDX 2
++#define mmDIG4_AFMT_AVI_INFO1 0x1c9d
++#define mmDIG4_AFMT_AVI_INFO1_BASE_IDX 2
++#define mmDIG4_AFMT_AVI_INFO2 0x1c9e
++#define mmDIG4_AFMT_AVI_INFO2_BASE_IDX 2
++#define mmDIG4_AFMT_AVI_INFO3 0x1c9f
++#define mmDIG4_AFMT_AVI_INFO3_BASE_IDX 2
++#define mmDIG4_AFMT_MPEG_INFO0 0x1ca0
++#define mmDIG4_AFMT_MPEG_INFO0_BASE_IDX 2
++#define mmDIG4_AFMT_MPEG_INFO1 0x1ca1
++#define mmDIG4_AFMT_MPEG_INFO1_BASE_IDX 2
++#define mmDIG4_AFMT_GENERIC_HDR 0x1ca2
++#define mmDIG4_AFMT_GENERIC_HDR_BASE_IDX 2
++#define mmDIG4_AFMT_GENERIC_0 0x1ca3
++#define mmDIG4_AFMT_GENERIC_0_BASE_IDX 2
++#define mmDIG4_AFMT_GENERIC_1 0x1ca4
++#define mmDIG4_AFMT_GENERIC_1_BASE_IDX 2
++#define mmDIG4_AFMT_GENERIC_2 0x1ca5
++#define mmDIG4_AFMT_GENERIC_2_BASE_IDX 2
++#define mmDIG4_AFMT_GENERIC_3 0x1ca6
++#define mmDIG4_AFMT_GENERIC_3_BASE_IDX 2
++#define mmDIG4_AFMT_GENERIC_4 0x1ca7
++#define mmDIG4_AFMT_GENERIC_4_BASE_IDX 2
++#define mmDIG4_AFMT_GENERIC_5 0x1ca8
++#define mmDIG4_AFMT_GENERIC_5_BASE_IDX 2
++#define mmDIG4_AFMT_GENERIC_6 0x1ca9
++#define mmDIG4_AFMT_GENERIC_6_BASE_IDX 2
++#define mmDIG4_AFMT_GENERIC_7 0x1caa
++#define mmDIG4_AFMT_GENERIC_7_BASE_IDX 2
++#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x1cab
++#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
++#define mmDIG4_HDMI_ACR_32_0 0x1cac
++#define mmDIG4_HDMI_ACR_32_0_BASE_IDX 2
++#define mmDIG4_HDMI_ACR_32_1 0x1cad
++#define mmDIG4_HDMI_ACR_32_1_BASE_IDX 2
++#define mmDIG4_HDMI_ACR_44_0 0x1cae
++#define mmDIG4_HDMI_ACR_44_0_BASE_IDX 2
++#define mmDIG4_HDMI_ACR_44_1 0x1caf
++#define mmDIG4_HDMI_ACR_44_1_BASE_IDX 2
++#define mmDIG4_HDMI_ACR_48_0 0x1cb0
++#define mmDIG4_HDMI_ACR_48_0_BASE_IDX 2
++#define mmDIG4_HDMI_ACR_48_1 0x1cb1
++#define mmDIG4_HDMI_ACR_48_1_BASE_IDX 2
++#define mmDIG4_HDMI_ACR_STATUS_0 0x1cb2
++#define mmDIG4_HDMI_ACR_STATUS_0_BASE_IDX 2
++#define mmDIG4_HDMI_ACR_STATUS_1 0x1cb3
++#define mmDIG4_HDMI_ACR_STATUS_1_BASE_IDX 2
++#define mmDIG4_AFMT_AUDIO_INFO0 0x1cb4
++#define mmDIG4_AFMT_AUDIO_INFO0_BASE_IDX 2
++#define mmDIG4_AFMT_AUDIO_INFO1 0x1cb5
++#define mmDIG4_AFMT_AUDIO_INFO1_BASE_IDX 2
++#define mmDIG4_AFMT_60958_0 0x1cb6
++#define mmDIG4_AFMT_60958_0_BASE_IDX 2
++#define mmDIG4_AFMT_60958_1 0x1cb7
++#define mmDIG4_AFMT_60958_1_BASE_IDX 2
++#define mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x1cb8
++#define mmDIG4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
++#define mmDIG4_AFMT_RAMP_CONTROL0 0x1cb9
++#define mmDIG4_AFMT_RAMP_CONTROL0_BASE_IDX 2
++#define mmDIG4_AFMT_RAMP_CONTROL1 0x1cba
++#define mmDIG4_AFMT_RAMP_CONTROL1_BASE_IDX 2
++#define mmDIG4_AFMT_RAMP_CONTROL2 0x1cbb
++#define mmDIG4_AFMT_RAMP_CONTROL2_BASE_IDX 2
++#define mmDIG4_AFMT_RAMP_CONTROL3 0x1cbc
++#define mmDIG4_AFMT_RAMP_CONTROL3_BASE_IDX 2
++#define mmDIG4_AFMT_60958_2 0x1cbd
++#define mmDIG4_AFMT_60958_2_BASE_IDX 2
++#define mmDIG4_AFMT_AUDIO_CRC_RESULT 0x1cbe
++#define mmDIG4_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
++#define mmDIG4_AFMT_STATUS 0x1cbf
++#define mmDIG4_AFMT_STATUS_BASE_IDX 2
++#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x1cc0
++#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
++#define mmDIG4_AFMT_VBI_PACKET_CONTROL 0x1cc1
++#define mmDIG4_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
++#define mmDIG4_AFMT_INFOFRAME_CONTROL0 0x1cc2
++#define mmDIG4_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
++#define mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x1cc3
++#define mmDIG4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
++#define mmDIG4_DIG_BE_CNTL 0x1cc5
++#define mmDIG4_DIG_BE_CNTL_BASE_IDX 2
++#define mmDIG4_DIG_BE_EN_CNTL 0x1cc6
++#define mmDIG4_DIG_BE_EN_CNTL_BASE_IDX 2
++#define mmDIG4_TMDS_CNTL 0x1ce9
++#define mmDIG4_TMDS_CNTL_BASE_IDX 2
++#define mmDIG4_TMDS_CONTROL_CHAR 0x1cea
++#define mmDIG4_TMDS_CONTROL_CHAR_BASE_IDX 2
++#define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x1ceb
++#define mmDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
++#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x1cec
++#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
++#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x1ced
++#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
++#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x1cee
++#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
++#define mmDIG4_TMDS_CTL_BITS 0x1cf0
++#define mmDIG4_TMDS_CTL_BITS_BASE_IDX 2
++#define mmDIG4_TMDS_DCBALANCER_CONTROL 0x1cf1
++#define mmDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
++#define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x1cf3
++#define mmDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
++#define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x1cf4
++#define mmDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
++#define mmDIG4_DIG_VERSION 0x1cf6
++#define mmDIG4_DIG_VERSION_BASE_IDX 2
++#define mmDIG4_DIG_LANE_ENABLE 0x1cf7
++#define mmDIG4_DIG_LANE_ENABLE_BASE_IDX 2
++#define mmDIG4_AFMT_CNTL 0x1cfc
++#define mmDIG4_AFMT_CNTL_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dp4_dispdec
++// base address: 0x1000
++#define mmDP4_DP_LINK_CNTL 0x1d1e
++#define mmDP4_DP_LINK_CNTL_BASE_IDX 2
++#define mmDP4_DP_PIXEL_FORMAT 0x1d1f
++#define mmDP4_DP_PIXEL_FORMAT_BASE_IDX 2
++#define mmDP4_DP_MSA_COLORIMETRY 0x1d20
++#define mmDP4_DP_MSA_COLORIMETRY_BASE_IDX 2
++#define mmDP4_DP_CONFIG 0x1d21
++#define mmDP4_DP_CONFIG_BASE_IDX 2
++#define mmDP4_DP_VID_STREAM_CNTL 0x1d22
++#define mmDP4_DP_VID_STREAM_CNTL_BASE_IDX 2
++#define mmDP4_DP_STEER_FIFO 0x1d23
++#define mmDP4_DP_STEER_FIFO_BASE_IDX 2
++#define mmDP4_DP_MSA_MISC 0x1d24
++#define mmDP4_DP_MSA_MISC_BASE_IDX 2
++#define mmDP4_DP_VID_TIMING 0x1d26
++#define mmDP4_DP_VID_TIMING_BASE_IDX 2
++#define mmDP4_DP_VID_N 0x1d27
++#define mmDP4_DP_VID_N_BASE_IDX 2
++#define mmDP4_DP_VID_M 0x1d28
++#define mmDP4_DP_VID_M_BASE_IDX 2
++#define mmDP4_DP_LINK_FRAMING_CNTL 0x1d29
++#define mmDP4_DP_LINK_FRAMING_CNTL_BASE_IDX 2
++#define mmDP4_DP_HBR2_EYE_PATTERN 0x1d2a
++#define mmDP4_DP_HBR2_EYE_PATTERN_BASE_IDX 2
++#define mmDP4_DP_VID_MSA_VBID 0x1d2b
++#define mmDP4_DP_VID_MSA_VBID_BASE_IDX 2
++#define mmDP4_DP_VID_INTERRUPT_CNTL 0x1d2c
++#define mmDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
++#define mmDP4_DP_DPHY_CNTL 0x1d2d
++#define mmDP4_DP_DPHY_CNTL_BASE_IDX 2
++#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x1d2e
++#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
++#define mmDP4_DP_DPHY_SYM0 0x1d2f
++#define mmDP4_DP_DPHY_SYM0_BASE_IDX 2
++#define mmDP4_DP_DPHY_SYM1 0x1d30
++#define mmDP4_DP_DPHY_SYM1_BASE_IDX 2
++#define mmDP4_DP_DPHY_SYM2 0x1d31
++#define mmDP4_DP_DPHY_SYM2_BASE_IDX 2
++#define mmDP4_DP_DPHY_8B10B_CNTL 0x1d32
++#define mmDP4_DP_DPHY_8B10B_CNTL_BASE_IDX 2
++#define mmDP4_DP_DPHY_PRBS_CNTL 0x1d33
++#define mmDP4_DP_DPHY_PRBS_CNTL_BASE_IDX 2
++#define mmDP4_DP_DPHY_SCRAM_CNTL 0x1d34
++#define mmDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
++#define mmDP4_DP_DPHY_CRC_EN 0x1d35
++#define mmDP4_DP_DPHY_CRC_EN_BASE_IDX 2
++#define mmDP4_DP_DPHY_CRC_CNTL 0x1d36
++#define mmDP4_DP_DPHY_CRC_CNTL_BASE_IDX 2
++#define mmDP4_DP_DPHY_CRC_RESULT 0x1d37
++#define mmDP4_DP_DPHY_CRC_RESULT_BASE_IDX 2
++#define mmDP4_DP_DPHY_CRC_MST_CNTL 0x1d38
++#define mmDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
++#define mmDP4_DP_DPHY_CRC_MST_STATUS 0x1d39
++#define mmDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
++#define mmDP4_DP_DPHY_FAST_TRAINING 0x1d3a
++#define mmDP4_DP_DPHY_FAST_TRAINING_BASE_IDX 2
++#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x1d3b
++#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
++#define mmDP4_DP_MSA_V_TIMING_OVERRIDE1 0x1d3c
++#define mmDP4_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2
++#define mmDP4_DP_MSA_V_TIMING_OVERRIDE2 0x1d3d
++#define mmDP4_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2
++#define mmDP4_DP_SEC_CNTL 0x1d41
++#define mmDP4_DP_SEC_CNTL_BASE_IDX 2
++#define mmDP4_DP_SEC_CNTL1 0x1d42
++#define mmDP4_DP_SEC_CNTL1_BASE_IDX 2
++#define mmDP4_DP_SEC_FRAMING1 0x1d43
++#define mmDP4_DP_SEC_FRAMING1_BASE_IDX 2
++#define mmDP4_DP_SEC_FRAMING2 0x1d44
++#define mmDP4_DP_SEC_FRAMING2_BASE_IDX 2
++#define mmDP4_DP_SEC_FRAMING3 0x1d45
++#define mmDP4_DP_SEC_FRAMING3_BASE_IDX 2
++#define mmDP4_DP_SEC_FRAMING4 0x1d46
++#define mmDP4_DP_SEC_FRAMING4_BASE_IDX 2
++#define mmDP4_DP_SEC_AUD_N 0x1d47
++#define mmDP4_DP_SEC_AUD_N_BASE_IDX 2
++#define mmDP4_DP_SEC_AUD_N_READBACK 0x1d48
++#define mmDP4_DP_SEC_AUD_N_READBACK_BASE_IDX 2
++#define mmDP4_DP_SEC_AUD_M 0x1d49
++#define mmDP4_DP_SEC_AUD_M_BASE_IDX 2
++#define mmDP4_DP_SEC_AUD_M_READBACK 0x1d4a
++#define mmDP4_DP_SEC_AUD_M_READBACK_BASE_IDX 2
++#define mmDP4_DP_SEC_TIMESTAMP 0x1d4b
++#define mmDP4_DP_SEC_TIMESTAMP_BASE_IDX 2
++#define mmDP4_DP_SEC_PACKET_CNTL 0x1d4c
++#define mmDP4_DP_SEC_PACKET_CNTL_BASE_IDX 2
++#define mmDP4_DP_MSE_RATE_CNTL 0x1d4d
++#define mmDP4_DP_MSE_RATE_CNTL_BASE_IDX 2
++#define mmDP4_DP_MSE_RATE_UPDATE 0x1d4f
++#define mmDP4_DP_MSE_RATE_UPDATE_BASE_IDX 2
++#define mmDP4_DP_MSE_SAT0 0x1d50
++#define mmDP4_DP_MSE_SAT0_BASE_IDX 2
++#define mmDP4_DP_MSE_SAT1 0x1d51
++#define mmDP4_DP_MSE_SAT1_BASE_IDX 2
++#define mmDP4_DP_MSE_SAT2 0x1d52
++#define mmDP4_DP_MSE_SAT2_BASE_IDX 2
++#define mmDP4_DP_MSE_SAT_UPDATE 0x1d53
++#define mmDP4_DP_MSE_SAT_UPDATE_BASE_IDX 2
++#define mmDP4_DP_MSE_LINK_TIMING 0x1d54
++#define mmDP4_DP_MSE_LINK_TIMING_BASE_IDX 2
++#define mmDP4_DP_MSE_MISC_CNTL 0x1d55
++#define mmDP4_DP_MSE_MISC_CNTL_BASE_IDX 2
++#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x1d5a
++#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
++#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x1d5b
++#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
++#define mmDP4_DP_MSE_SAT0_STATUS 0x1d5d
++#define mmDP4_DP_MSE_SAT0_STATUS_BASE_IDX 2
++#define mmDP4_DP_MSE_SAT1_STATUS 0x1d5e
++#define mmDP4_DP_MSE_SAT1_STATUS_BASE_IDX 2
++#define mmDP4_DP_MSE_SAT2_STATUS 0x1d5f
++#define mmDP4_DP_MSE_SAT2_STATUS_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dig5_dispdec
++// base address: 0x1400
++#define mmDIG5_DIG_FE_CNTL 0x1d7e
++#define mmDIG5_DIG_FE_CNTL_BASE_IDX 2
++#define mmDIG5_DIG_OUTPUT_CRC_CNTL 0x1d7f
++#define mmDIG5_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
++#define mmDIG5_DIG_OUTPUT_CRC_RESULT 0x1d80
++#define mmDIG5_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
++#define mmDIG5_DIG_CLOCK_PATTERN 0x1d81
++#define mmDIG5_DIG_CLOCK_PATTERN_BASE_IDX 2
++#define mmDIG5_DIG_TEST_PATTERN 0x1d82
++#define mmDIG5_DIG_TEST_PATTERN_BASE_IDX 2
++#define mmDIG5_DIG_RANDOM_PATTERN_SEED 0x1d83
++#define mmDIG5_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
++#define mmDIG5_DIG_FIFO_STATUS 0x1d84
++#define mmDIG5_DIG_FIFO_STATUS_BASE_IDX 2
++#define mmDIG5_HDMI_CONTROL 0x1d87
++#define mmDIG5_HDMI_CONTROL_BASE_IDX 2
++#define mmDIG5_HDMI_STATUS 0x1d88
++#define mmDIG5_HDMI_STATUS_BASE_IDX 2
++#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x1d89
++#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
++#define mmDIG5_HDMI_ACR_PACKET_CONTROL 0x1d8a
++#define mmDIG5_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
++#define mmDIG5_HDMI_VBI_PACKET_CONTROL 0x1d8b
++#define mmDIG5_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
++#define mmDIG5_HDMI_INFOFRAME_CONTROL0 0x1d8c
++#define mmDIG5_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
++#define mmDIG5_HDMI_INFOFRAME_CONTROL1 0x1d8d
++#define mmDIG5_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
++#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x1d8e
++#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
++#define mmDIG5_AFMT_INTERRUPT_STATUS 0x1d8f
++#define mmDIG5_AFMT_INTERRUPT_STATUS_BASE_IDX 2
++#define mmDIG5_HDMI_GC 0x1d91
++#define mmDIG5_HDMI_GC_BASE_IDX 2
++#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x1d92
++#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
++#define mmDIG5_AFMT_ISRC1_0 0x1d93
++#define mmDIG5_AFMT_ISRC1_0_BASE_IDX 2
++#define mmDIG5_AFMT_ISRC1_1 0x1d94
++#define mmDIG5_AFMT_ISRC1_1_BASE_IDX 2
++#define mmDIG5_AFMT_ISRC1_2 0x1d95
++#define mmDIG5_AFMT_ISRC1_2_BASE_IDX 2
++#define mmDIG5_AFMT_ISRC1_3 0x1d96
++#define mmDIG5_AFMT_ISRC1_3_BASE_IDX 2
++#define mmDIG5_AFMT_ISRC1_4 0x1d97
++#define mmDIG5_AFMT_ISRC1_4_BASE_IDX 2
++#define mmDIG5_AFMT_ISRC2_0 0x1d98
++#define mmDIG5_AFMT_ISRC2_0_BASE_IDX 2
++#define mmDIG5_AFMT_ISRC2_1 0x1d99
++#define mmDIG5_AFMT_ISRC2_1_BASE_IDX 2
++#define mmDIG5_AFMT_ISRC2_2 0x1d9a
++#define mmDIG5_AFMT_ISRC2_2_BASE_IDX 2
++#define mmDIG5_AFMT_ISRC2_3 0x1d9b
++#define mmDIG5_AFMT_ISRC2_3_BASE_IDX 2
++#define mmDIG5_AFMT_AVI_INFO0 0x1d9c
++#define mmDIG5_AFMT_AVI_INFO0_BASE_IDX 2
++#define mmDIG5_AFMT_AVI_INFO1 0x1d9d
++#define mmDIG5_AFMT_AVI_INFO1_BASE_IDX 2
++#define mmDIG5_AFMT_AVI_INFO2 0x1d9e
++#define mmDIG5_AFMT_AVI_INFO2_BASE_IDX 2
++#define mmDIG5_AFMT_AVI_INFO3 0x1d9f
++#define mmDIG5_AFMT_AVI_INFO3_BASE_IDX 2
++#define mmDIG5_AFMT_MPEG_INFO0 0x1da0
++#define mmDIG5_AFMT_MPEG_INFO0_BASE_IDX 2
++#define mmDIG5_AFMT_MPEG_INFO1 0x1da1
++#define mmDIG5_AFMT_MPEG_INFO1_BASE_IDX 2
++#define mmDIG5_AFMT_GENERIC_HDR 0x1da2
++#define mmDIG5_AFMT_GENERIC_HDR_BASE_IDX 2
++#define mmDIG5_AFMT_GENERIC_0 0x1da3
++#define mmDIG5_AFMT_GENERIC_0_BASE_IDX 2
++#define mmDIG5_AFMT_GENERIC_1 0x1da4
++#define mmDIG5_AFMT_GENERIC_1_BASE_IDX 2
++#define mmDIG5_AFMT_GENERIC_2 0x1da5
++#define mmDIG5_AFMT_GENERIC_2_BASE_IDX 2
++#define mmDIG5_AFMT_GENERIC_3 0x1da6
++#define mmDIG5_AFMT_GENERIC_3_BASE_IDX 2
++#define mmDIG5_AFMT_GENERIC_4 0x1da7
++#define mmDIG5_AFMT_GENERIC_4_BASE_IDX 2
++#define mmDIG5_AFMT_GENERIC_5 0x1da8
++#define mmDIG5_AFMT_GENERIC_5_BASE_IDX 2
++#define mmDIG5_AFMT_GENERIC_6 0x1da9
++#define mmDIG5_AFMT_GENERIC_6_BASE_IDX 2
++#define mmDIG5_AFMT_GENERIC_7 0x1daa
++#define mmDIG5_AFMT_GENERIC_7_BASE_IDX 2
++#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x1dab
++#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
++#define mmDIG5_HDMI_ACR_32_0 0x1dac
++#define mmDIG5_HDMI_ACR_32_0_BASE_IDX 2
++#define mmDIG5_HDMI_ACR_32_1 0x1dad
++#define mmDIG5_HDMI_ACR_32_1_BASE_IDX 2
++#define mmDIG5_HDMI_ACR_44_0 0x1dae
++#define mmDIG5_HDMI_ACR_44_0_BASE_IDX 2
++#define mmDIG5_HDMI_ACR_44_1 0x1daf
++#define mmDIG5_HDMI_ACR_44_1_BASE_IDX 2
++#define mmDIG5_HDMI_ACR_48_0 0x1db0
++#define mmDIG5_HDMI_ACR_48_0_BASE_IDX 2
++#define mmDIG5_HDMI_ACR_48_1 0x1db1
++#define mmDIG5_HDMI_ACR_48_1_BASE_IDX 2
++#define mmDIG5_HDMI_ACR_STATUS_0 0x1db2
++#define mmDIG5_HDMI_ACR_STATUS_0_BASE_IDX 2
++#define mmDIG5_HDMI_ACR_STATUS_1 0x1db3
++#define mmDIG5_HDMI_ACR_STATUS_1_BASE_IDX 2
++#define mmDIG5_AFMT_AUDIO_INFO0 0x1db4
++#define mmDIG5_AFMT_AUDIO_INFO0_BASE_IDX 2
++#define mmDIG5_AFMT_AUDIO_INFO1 0x1db5
++#define mmDIG5_AFMT_AUDIO_INFO1_BASE_IDX 2
++#define mmDIG5_AFMT_60958_0 0x1db6
++#define mmDIG5_AFMT_60958_0_BASE_IDX 2
++#define mmDIG5_AFMT_60958_1 0x1db7
++#define mmDIG5_AFMT_60958_1_BASE_IDX 2
++#define mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x1db8
++#define mmDIG5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
++#define mmDIG5_AFMT_RAMP_CONTROL0 0x1db9
++#define mmDIG5_AFMT_RAMP_CONTROL0_BASE_IDX 2
++#define mmDIG5_AFMT_RAMP_CONTROL1 0x1dba
++#define mmDIG5_AFMT_RAMP_CONTROL1_BASE_IDX 2
++#define mmDIG5_AFMT_RAMP_CONTROL2 0x1dbb
++#define mmDIG5_AFMT_RAMP_CONTROL2_BASE_IDX 2
++#define mmDIG5_AFMT_RAMP_CONTROL3 0x1dbc
++#define mmDIG5_AFMT_RAMP_CONTROL3_BASE_IDX 2
++#define mmDIG5_AFMT_60958_2 0x1dbd
++#define mmDIG5_AFMT_60958_2_BASE_IDX 2
++#define mmDIG5_AFMT_AUDIO_CRC_RESULT 0x1dbe
++#define mmDIG5_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
++#define mmDIG5_AFMT_STATUS 0x1dbf
++#define mmDIG5_AFMT_STATUS_BASE_IDX 2
++#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x1dc0
++#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
++#define mmDIG5_AFMT_VBI_PACKET_CONTROL 0x1dc1
++#define mmDIG5_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
++#define mmDIG5_AFMT_INFOFRAME_CONTROL0 0x1dc2
++#define mmDIG5_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
++#define mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x1dc3
++#define mmDIG5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
++#define mmDIG5_DIG_BE_CNTL 0x1dc5
++#define mmDIG5_DIG_BE_CNTL_BASE_IDX 2
++#define mmDIG5_DIG_BE_EN_CNTL 0x1dc6
++#define mmDIG5_DIG_BE_EN_CNTL_BASE_IDX 2
++#define mmDIG5_TMDS_CNTL 0x1de9
++#define mmDIG5_TMDS_CNTL_BASE_IDX 2
++#define mmDIG5_TMDS_CONTROL_CHAR 0x1dea
++#define mmDIG5_TMDS_CONTROL_CHAR_BASE_IDX 2
++#define mmDIG5_TMDS_CONTROL0_FEEDBACK 0x1deb
++#define mmDIG5_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
++#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x1dec
++#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
++#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x1ded
++#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
++#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x1dee
++#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
++#define mmDIG5_TMDS_CTL_BITS 0x1df0
++#define mmDIG5_TMDS_CTL_BITS_BASE_IDX 2
++#define mmDIG5_TMDS_DCBALANCER_CONTROL 0x1df1
++#define mmDIG5_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
++#define mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x1df3
++#define mmDIG5_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
++#define mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x1df4
++#define mmDIG5_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
++#define mmDIG5_DIG_VERSION 0x1df6
++#define mmDIG5_DIG_VERSION_BASE_IDX 2
++#define mmDIG5_DIG_LANE_ENABLE 0x1df7
++#define mmDIG5_DIG_LANE_ENABLE_BASE_IDX 2
++#define mmDIG5_AFMT_CNTL 0x1dfc
++#define mmDIG5_AFMT_CNTL_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dp5_dispdec
++// base address: 0x1400
++#define mmDP5_DP_LINK_CNTL 0x1e1e
++#define mmDP5_DP_LINK_CNTL_BASE_IDX 2
++#define mmDP5_DP_PIXEL_FORMAT 0x1e1f
++#define mmDP5_DP_PIXEL_FORMAT_BASE_IDX 2
++#define mmDP5_DP_MSA_COLORIMETRY 0x1e20
++#define mmDP5_DP_MSA_COLORIMETRY_BASE_IDX 2
++#define mmDP5_DP_CONFIG 0x1e21
++#define mmDP5_DP_CONFIG_BASE_IDX 2
++#define mmDP5_DP_VID_STREAM_CNTL 0x1e22
++#define mmDP5_DP_VID_STREAM_CNTL_BASE_IDX 2
++#define mmDP5_DP_STEER_FIFO 0x1e23
++#define mmDP5_DP_STEER_FIFO_BASE_IDX 2
++#define mmDP5_DP_MSA_MISC 0x1e24
++#define mmDP5_DP_MSA_MISC_BASE_IDX 2
++#define mmDP5_DP_VID_TIMING 0x1e26
++#define mmDP5_DP_VID_TIMING_BASE_IDX 2
++#define mmDP5_DP_VID_N 0x1e27
++#define mmDP5_DP_VID_N_BASE_IDX 2
++#define mmDP5_DP_VID_M 0x1e28
++#define mmDP5_DP_VID_M_BASE_IDX 2
++#define mmDP5_DP_LINK_FRAMING_CNTL 0x1e29
++#define mmDP5_DP_LINK_FRAMING_CNTL_BASE_IDX 2
++#define mmDP5_DP_HBR2_EYE_PATTERN 0x1e2a
++#define mmDP5_DP_HBR2_EYE_PATTERN_BASE_IDX 2
++#define mmDP5_DP_VID_MSA_VBID 0x1e2b
++#define mmDP5_DP_VID_MSA_VBID_BASE_IDX 2
++#define mmDP5_DP_VID_INTERRUPT_CNTL 0x1e2c
++#define mmDP5_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
++#define mmDP5_DP_DPHY_CNTL 0x1e2d
++#define mmDP5_DP_DPHY_CNTL_BASE_IDX 2
++#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x1e2e
++#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
++#define mmDP5_DP_DPHY_SYM0 0x1e2f
++#define mmDP5_DP_DPHY_SYM0_BASE_IDX 2
++#define mmDP5_DP_DPHY_SYM1 0x1e30
++#define mmDP5_DP_DPHY_SYM1_BASE_IDX 2
++#define mmDP5_DP_DPHY_SYM2 0x1e31
++#define mmDP5_DP_DPHY_SYM2_BASE_IDX 2
++#define mmDP5_DP_DPHY_8B10B_CNTL 0x1e32
++#define mmDP5_DP_DPHY_8B10B_CNTL_BASE_IDX 2
++#define mmDP5_DP_DPHY_PRBS_CNTL 0x1e33
++#define mmDP5_DP_DPHY_PRBS_CNTL_BASE_IDX 2
++#define mmDP5_DP_DPHY_SCRAM_CNTL 0x1e34
++#define mmDP5_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
++#define mmDP5_DP_DPHY_CRC_EN 0x1e35
++#define mmDP5_DP_DPHY_CRC_EN_BASE_IDX 2
++#define mmDP5_DP_DPHY_CRC_CNTL 0x1e36
++#define mmDP5_DP_DPHY_CRC_CNTL_BASE_IDX 2
++#define mmDP5_DP_DPHY_CRC_RESULT 0x1e37
++#define mmDP5_DP_DPHY_CRC_RESULT_BASE_IDX 2
++#define mmDP5_DP_DPHY_CRC_MST_CNTL 0x1e38
++#define mmDP5_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
++#define mmDP5_DP_DPHY_CRC_MST_STATUS 0x1e39
++#define mmDP5_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
++#define mmDP5_DP_DPHY_FAST_TRAINING 0x1e3a
++#define mmDP5_DP_DPHY_FAST_TRAINING_BASE_IDX 2
++#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x1e3b
++#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
++#define mmDP5_DP_MSA_V_TIMING_OVERRIDE1 0x1e3c
++#define mmDP5_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2
++#define mmDP5_DP_MSA_V_TIMING_OVERRIDE2 0x1e3d
++#define mmDP5_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2
++#define mmDP5_DP_SEC_CNTL 0x1e41
++#define mmDP5_DP_SEC_CNTL_BASE_IDX 2
++#define mmDP5_DP_SEC_CNTL1 0x1e42
++#define mmDP5_DP_SEC_CNTL1_BASE_IDX 2
++#define mmDP5_DP_SEC_FRAMING1 0x1e43
++#define mmDP5_DP_SEC_FRAMING1_BASE_IDX 2
++#define mmDP5_DP_SEC_FRAMING2 0x1e44
++#define mmDP5_DP_SEC_FRAMING2_BASE_IDX 2
++#define mmDP5_DP_SEC_FRAMING3 0x1e45
++#define mmDP5_DP_SEC_FRAMING3_BASE_IDX 2
++#define mmDP5_DP_SEC_FRAMING4 0x1e46
++#define mmDP5_DP_SEC_FRAMING4_BASE_IDX 2
++#define mmDP5_DP_SEC_AUD_N 0x1e47
++#define mmDP5_DP_SEC_AUD_N_BASE_IDX 2
++#define mmDP5_DP_SEC_AUD_N_READBACK 0x1e48
++#define mmDP5_DP_SEC_AUD_N_READBACK_BASE_IDX 2
++#define mmDP5_DP_SEC_AUD_M 0x1e49
++#define mmDP5_DP_SEC_AUD_M_BASE_IDX 2
++#define mmDP5_DP_SEC_AUD_M_READBACK 0x1e4a
++#define mmDP5_DP_SEC_AUD_M_READBACK_BASE_IDX 2
++#define mmDP5_DP_SEC_TIMESTAMP 0x1e4b
++#define mmDP5_DP_SEC_TIMESTAMP_BASE_IDX 2
++#define mmDP5_DP_SEC_PACKET_CNTL 0x1e4c
++#define mmDP5_DP_SEC_PACKET_CNTL_BASE_IDX 2
++#define mmDP5_DP_MSE_RATE_CNTL 0x1e4d
++#define mmDP5_DP_MSE_RATE_CNTL_BASE_IDX 2
++#define mmDP5_DP_MSE_RATE_UPDATE 0x1e4f
++#define mmDP5_DP_MSE_RATE_UPDATE_BASE_IDX 2
++#define mmDP5_DP_MSE_SAT0 0x1e50
++#define mmDP5_DP_MSE_SAT0_BASE_IDX 2
++#define mmDP5_DP_MSE_SAT1 0x1e51
++#define mmDP5_DP_MSE_SAT1_BASE_IDX 2
++#define mmDP5_DP_MSE_SAT2 0x1e52
++#define mmDP5_DP_MSE_SAT2_BASE_IDX 2
++#define mmDP5_DP_MSE_SAT_UPDATE 0x1e53
++#define mmDP5_DP_MSE_SAT_UPDATE_BASE_IDX 2
++#define mmDP5_DP_MSE_LINK_TIMING 0x1e54
++#define mmDP5_DP_MSE_LINK_TIMING_BASE_IDX 2
++#define mmDP5_DP_MSE_MISC_CNTL 0x1e55
++#define mmDP5_DP_MSE_MISC_CNTL_BASE_IDX 2
++#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x1e5a
++#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
++#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL 0x1e5b
++#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
++#define mmDP5_DP_MSE_SAT0_STATUS 0x1e5d
++#define mmDP5_DP_MSE_SAT0_STATUS_BASE_IDX 2
++#define mmDP5_DP_MSE_SAT1_STATUS 0x1e5e
++#define mmDP5_DP_MSE_SAT1_STATUS_BASE_IDX 2
++#define mmDP5_DP_MSE_SAT2_STATUS 0x1e5f
++#define mmDP5_DP_MSE_SAT2_STATUS_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dig6_dispdec
++// base address: 0x1800
++#define mmDIG6_DIG_FE_CNTL 0x1e7e
++#define mmDIG6_DIG_FE_CNTL_BASE_IDX 2
++#define mmDIG6_DIG_OUTPUT_CRC_CNTL 0x1e7f
++#define mmDIG6_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
++#define mmDIG6_DIG_OUTPUT_CRC_RESULT 0x1e80
++#define mmDIG6_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
++#define mmDIG6_DIG_CLOCK_PATTERN 0x1e81
++#define mmDIG6_DIG_CLOCK_PATTERN_BASE_IDX 2
++#define mmDIG6_DIG_TEST_PATTERN 0x1e82
++#define mmDIG6_DIG_TEST_PATTERN_BASE_IDX 2
++#define mmDIG6_DIG_RANDOM_PATTERN_SEED 0x1e83
++#define mmDIG6_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
++#define mmDIG6_DIG_FIFO_STATUS 0x1e84
++#define mmDIG6_DIG_FIFO_STATUS_BASE_IDX 2
++#define mmDIG6_HDMI_CONTROL 0x1e87
++#define mmDIG6_HDMI_CONTROL_BASE_IDX 2
++#define mmDIG6_HDMI_STATUS 0x1e88
++#define mmDIG6_HDMI_STATUS_BASE_IDX 2
++#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL 0x1e89
++#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
++#define mmDIG6_HDMI_ACR_PACKET_CONTROL 0x1e8a
++#define mmDIG6_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
++#define mmDIG6_HDMI_VBI_PACKET_CONTROL 0x1e8b
++#define mmDIG6_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
++#define mmDIG6_HDMI_INFOFRAME_CONTROL0 0x1e8c
++#define mmDIG6_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
++#define mmDIG6_HDMI_INFOFRAME_CONTROL1 0x1e8d
++#define mmDIG6_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
++#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 0x1e8e
++#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
++#define mmDIG6_AFMT_INTERRUPT_STATUS 0x1e8f
++#define mmDIG6_AFMT_INTERRUPT_STATUS_BASE_IDX 2
++#define mmDIG6_HDMI_GC 0x1e91
++#define mmDIG6_HDMI_GC_BASE_IDX 2
++#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 0x1e92
++#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
++#define mmDIG6_AFMT_ISRC1_0 0x1e93
++#define mmDIG6_AFMT_ISRC1_0_BASE_IDX 2
++#define mmDIG6_AFMT_ISRC1_1 0x1e94
++#define mmDIG6_AFMT_ISRC1_1_BASE_IDX 2
++#define mmDIG6_AFMT_ISRC1_2 0x1e95
++#define mmDIG6_AFMT_ISRC1_2_BASE_IDX 2
++#define mmDIG6_AFMT_ISRC1_3 0x1e96
++#define mmDIG6_AFMT_ISRC1_3_BASE_IDX 2
++#define mmDIG6_AFMT_ISRC1_4 0x1e97
++#define mmDIG6_AFMT_ISRC1_4_BASE_IDX 2
++#define mmDIG6_AFMT_ISRC2_0 0x1e98
++#define mmDIG6_AFMT_ISRC2_0_BASE_IDX 2
++#define mmDIG6_AFMT_ISRC2_1 0x1e99
++#define mmDIG6_AFMT_ISRC2_1_BASE_IDX 2
++#define mmDIG6_AFMT_ISRC2_2 0x1e9a
++#define mmDIG6_AFMT_ISRC2_2_BASE_IDX 2
++#define mmDIG6_AFMT_ISRC2_3 0x1e9b
++#define mmDIG6_AFMT_ISRC2_3_BASE_IDX 2
++#define mmDIG6_AFMT_AVI_INFO0 0x1e9c
++#define mmDIG6_AFMT_AVI_INFO0_BASE_IDX 2
++#define mmDIG6_AFMT_AVI_INFO1 0x1e9d
++#define mmDIG6_AFMT_AVI_INFO1_BASE_IDX 2
++#define mmDIG6_AFMT_AVI_INFO2 0x1e9e
++#define mmDIG6_AFMT_AVI_INFO2_BASE_IDX 2
++#define mmDIG6_AFMT_AVI_INFO3 0x1e9f
++#define mmDIG6_AFMT_AVI_INFO3_BASE_IDX 2
++#define mmDIG6_AFMT_MPEG_INFO0 0x1ea0
++#define mmDIG6_AFMT_MPEG_INFO0_BASE_IDX 2
++#define mmDIG6_AFMT_MPEG_INFO1 0x1ea1
++#define mmDIG6_AFMT_MPEG_INFO1_BASE_IDX 2
++#define mmDIG6_AFMT_GENERIC_HDR 0x1ea2
++#define mmDIG6_AFMT_GENERIC_HDR_BASE_IDX 2
++#define mmDIG6_AFMT_GENERIC_0 0x1ea3
++#define mmDIG6_AFMT_GENERIC_0_BASE_IDX 2
++#define mmDIG6_AFMT_GENERIC_1 0x1ea4
++#define mmDIG6_AFMT_GENERIC_1_BASE_IDX 2
++#define mmDIG6_AFMT_GENERIC_2 0x1ea5
++#define mmDIG6_AFMT_GENERIC_2_BASE_IDX 2
++#define mmDIG6_AFMT_GENERIC_3 0x1ea6
++#define mmDIG6_AFMT_GENERIC_3_BASE_IDX 2
++#define mmDIG6_AFMT_GENERIC_4 0x1ea7
++#define mmDIG6_AFMT_GENERIC_4_BASE_IDX 2
++#define mmDIG6_AFMT_GENERIC_5 0x1ea8
++#define mmDIG6_AFMT_GENERIC_5_BASE_IDX 2
++#define mmDIG6_AFMT_GENERIC_6 0x1ea9
++#define mmDIG6_AFMT_GENERIC_6_BASE_IDX 2
++#define mmDIG6_AFMT_GENERIC_7 0x1eaa
++#define mmDIG6_AFMT_GENERIC_7_BASE_IDX 2
++#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 0x1eab
++#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
++#define mmDIG6_HDMI_ACR_32_0 0x1eac
++#define mmDIG6_HDMI_ACR_32_0_BASE_IDX 2
++#define mmDIG6_HDMI_ACR_32_1 0x1ead
++#define mmDIG6_HDMI_ACR_32_1_BASE_IDX 2
++#define mmDIG6_HDMI_ACR_44_0 0x1eae
++#define mmDIG6_HDMI_ACR_44_0_BASE_IDX 2
++#define mmDIG6_HDMI_ACR_44_1 0x1eaf
++#define mmDIG6_HDMI_ACR_44_1_BASE_IDX 2
++#define mmDIG6_HDMI_ACR_48_0 0x1eb0
++#define mmDIG6_HDMI_ACR_48_0_BASE_IDX 2
++#define mmDIG6_HDMI_ACR_48_1 0x1eb1
++#define mmDIG6_HDMI_ACR_48_1_BASE_IDX 2
++#define mmDIG6_HDMI_ACR_STATUS_0 0x1eb2
++#define mmDIG6_HDMI_ACR_STATUS_0_BASE_IDX 2
++#define mmDIG6_HDMI_ACR_STATUS_1 0x1eb3
++#define mmDIG6_HDMI_ACR_STATUS_1_BASE_IDX 2
++#define mmDIG6_AFMT_AUDIO_INFO0 0x1eb4
++#define mmDIG6_AFMT_AUDIO_INFO0_BASE_IDX 2
++#define mmDIG6_AFMT_AUDIO_INFO1 0x1eb5
++#define mmDIG6_AFMT_AUDIO_INFO1_BASE_IDX 2
++#define mmDIG6_AFMT_60958_0 0x1eb6
++#define mmDIG6_AFMT_60958_0_BASE_IDX 2
++#define mmDIG6_AFMT_60958_1 0x1eb7
++#define mmDIG6_AFMT_60958_1_BASE_IDX 2
++#define mmDIG6_AFMT_AUDIO_CRC_CONTROL 0x1eb8
++#define mmDIG6_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
++#define mmDIG6_AFMT_RAMP_CONTROL0 0x1eb9
++#define mmDIG6_AFMT_RAMP_CONTROL0_BASE_IDX 2
++#define mmDIG6_AFMT_RAMP_CONTROL1 0x1eba
++#define mmDIG6_AFMT_RAMP_CONTROL1_BASE_IDX 2
++#define mmDIG6_AFMT_RAMP_CONTROL2 0x1ebb
++#define mmDIG6_AFMT_RAMP_CONTROL2_BASE_IDX 2
++#define mmDIG6_AFMT_RAMP_CONTROL3 0x1ebc
++#define mmDIG6_AFMT_RAMP_CONTROL3_BASE_IDX 2
++#define mmDIG6_AFMT_60958_2 0x1ebd
++#define mmDIG6_AFMT_60958_2_BASE_IDX 2
++#define mmDIG6_AFMT_AUDIO_CRC_RESULT 0x1ebe
++#define mmDIG6_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
++#define mmDIG6_AFMT_STATUS 0x1ebf
++#define mmDIG6_AFMT_STATUS_BASE_IDX 2
++#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL 0x1ec0
++#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
++#define mmDIG6_AFMT_VBI_PACKET_CONTROL 0x1ec1
++#define mmDIG6_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
++#define mmDIG6_AFMT_INFOFRAME_CONTROL0 0x1ec2
++#define mmDIG6_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
++#define mmDIG6_AFMT_AUDIO_SRC_CONTROL 0x1ec3
++#define mmDIG6_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
++#define mmDIG6_DIG_BE_CNTL 0x1ec5
++#define mmDIG6_DIG_BE_CNTL_BASE_IDX 2
++#define mmDIG6_DIG_BE_EN_CNTL 0x1ec6
++#define mmDIG6_DIG_BE_EN_CNTL_BASE_IDX 2
++#define mmDIG6_TMDS_CNTL 0x1ee9
++#define mmDIG6_TMDS_CNTL_BASE_IDX 2
++#define mmDIG6_TMDS_CONTROL_CHAR 0x1eea
++#define mmDIG6_TMDS_CONTROL_CHAR_BASE_IDX 2
++#define mmDIG6_TMDS_CONTROL0_FEEDBACK 0x1eeb
++#define mmDIG6_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
++#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL 0x1eec
++#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
++#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 0x1eed
++#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
++#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 0x1eee
++#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
++#define mmDIG6_TMDS_CTL_BITS 0x1ef0
++#define mmDIG6_TMDS_CTL_BITS_BASE_IDX 2
++#define mmDIG6_TMDS_DCBALANCER_CONTROL 0x1ef1
++#define mmDIG6_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
++#define mmDIG6_TMDS_CTL0_1_GEN_CNTL 0x1ef3
++#define mmDIG6_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
++#define mmDIG6_TMDS_CTL2_3_GEN_CNTL 0x1ef4
++#define mmDIG6_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
++#define mmDIG6_DIG_VERSION 0x1ef6
++#define mmDIG6_DIG_VERSION_BASE_IDX 2
++#define mmDIG6_DIG_LANE_ENABLE 0x1ef7
++#define mmDIG6_DIG_LANE_ENABLE_BASE_IDX 2
++#define mmDIG6_AFMT_CNTL 0x1efc
++#define mmDIG6_AFMT_CNTL_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dp6_dispdec
++// base address: 0x1800
++#define mmDP6_DP_LINK_CNTL 0x1f1e
++#define mmDP6_DP_LINK_CNTL_BASE_IDX 2
++#define mmDP6_DP_PIXEL_FORMAT 0x1f1f
++#define mmDP6_DP_PIXEL_FORMAT_BASE_IDX 2
++#define mmDP6_DP_MSA_COLORIMETRY 0x1f20
++#define mmDP6_DP_MSA_COLORIMETRY_BASE_IDX 2
++#define mmDP6_DP_CONFIG 0x1f21
++#define mmDP6_DP_CONFIG_BASE_IDX 2
++#define mmDP6_DP_VID_STREAM_CNTL 0x1f22
++#define mmDP6_DP_VID_STREAM_CNTL_BASE_IDX 2
++#define mmDP6_DP_STEER_FIFO 0x1f23
++#define mmDP6_DP_STEER_FIFO_BASE_IDX 2
++#define mmDP6_DP_MSA_MISC 0x1f24
++#define mmDP6_DP_MSA_MISC_BASE_IDX 2
++#define mmDP6_DP_VID_TIMING 0x1f26
++#define mmDP6_DP_VID_TIMING_BASE_IDX 2
++#define mmDP6_DP_VID_N 0x1f27
++#define mmDP6_DP_VID_N_BASE_IDX 2
++#define mmDP6_DP_VID_M 0x1f28
++#define mmDP6_DP_VID_M_BASE_IDX 2
++#define mmDP6_DP_LINK_FRAMING_CNTL 0x1f29
++#define mmDP6_DP_LINK_FRAMING_CNTL_BASE_IDX 2
++#define mmDP6_DP_HBR2_EYE_PATTERN 0x1f2a
++#define mmDP6_DP_HBR2_EYE_PATTERN_BASE_IDX 2
++#define mmDP6_DP_VID_MSA_VBID 0x1f2b
++#define mmDP6_DP_VID_MSA_VBID_BASE_IDX 2
++#define mmDP6_DP_VID_INTERRUPT_CNTL 0x1f2c
++#define mmDP6_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
++#define mmDP6_DP_DPHY_CNTL 0x1f2d
++#define mmDP6_DP_DPHY_CNTL_BASE_IDX 2
++#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL 0x1f2e
++#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
++#define mmDP6_DP_DPHY_SYM0 0x1f2f
++#define mmDP6_DP_DPHY_SYM0_BASE_IDX 2
++#define mmDP6_DP_DPHY_SYM1 0x1f30
++#define mmDP6_DP_DPHY_SYM1_BASE_IDX 2
++#define mmDP6_DP_DPHY_SYM2 0x1f31
++#define mmDP6_DP_DPHY_SYM2_BASE_IDX 2
++#define mmDP6_DP_DPHY_8B10B_CNTL 0x1f32
++#define mmDP6_DP_DPHY_8B10B_CNTL_BASE_IDX 2
++#define mmDP6_DP_DPHY_PRBS_CNTL 0x1f33
++#define mmDP6_DP_DPHY_PRBS_CNTL_BASE_IDX 2
++#define mmDP6_DP_DPHY_SCRAM_CNTL 0x1f34
++#define mmDP6_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
++#define mmDP6_DP_DPHY_CRC_EN 0x1f35
++#define mmDP6_DP_DPHY_CRC_EN_BASE_IDX 2
++#define mmDP6_DP_DPHY_CRC_CNTL 0x1f36
++#define mmDP6_DP_DPHY_CRC_CNTL_BASE_IDX 2
++#define mmDP6_DP_DPHY_CRC_RESULT 0x1f37
++#define mmDP6_DP_DPHY_CRC_RESULT_BASE_IDX 2
++#define mmDP6_DP_DPHY_CRC_MST_CNTL 0x1f38
++#define mmDP6_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
++#define mmDP6_DP_DPHY_CRC_MST_STATUS 0x1f39
++#define mmDP6_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
++#define mmDP6_DP_DPHY_FAST_TRAINING 0x1f3a
++#define mmDP6_DP_DPHY_FAST_TRAINING_BASE_IDX 2
++#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS 0x1f3b
++#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
++#define mmDP6_DP_MSA_V_TIMING_OVERRIDE1 0x1f3c
++#define mmDP6_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2
++#define mmDP6_DP_MSA_V_TIMING_OVERRIDE2 0x1f3d
++#define mmDP6_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2
++#define mmDP6_DP_SEC_CNTL 0x1f41
++#define mmDP6_DP_SEC_CNTL_BASE_IDX 2
++#define mmDP6_DP_SEC_CNTL1 0x1f42
++#define mmDP6_DP_SEC_CNTL1_BASE_IDX 2
++#define mmDP6_DP_SEC_FRAMING1 0x1f43
++#define mmDP6_DP_SEC_FRAMING1_BASE_IDX 2
++#define mmDP6_DP_SEC_FRAMING2 0x1f44
++#define mmDP6_DP_SEC_FRAMING2_BASE_IDX 2
++#define mmDP6_DP_SEC_FRAMING3 0x1f45
++#define mmDP6_DP_SEC_FRAMING3_BASE_IDX 2
++#define mmDP6_DP_SEC_FRAMING4 0x1f46
++#define mmDP6_DP_SEC_FRAMING4_BASE_IDX 2
++#define mmDP6_DP_SEC_AUD_N 0x1f47
++#define mmDP6_DP_SEC_AUD_N_BASE_IDX 2
++#define mmDP6_DP_SEC_AUD_N_READBACK 0x1f48
++#define mmDP6_DP_SEC_AUD_N_READBACK_BASE_IDX 2
++#define mmDP6_DP_SEC_AUD_M 0x1f49
++#define mmDP6_DP_SEC_AUD_M_BASE_IDX 2
++#define mmDP6_DP_SEC_AUD_M_READBACK 0x1f4a
++#define mmDP6_DP_SEC_AUD_M_READBACK_BASE_IDX 2
++#define mmDP6_DP_SEC_TIMESTAMP 0x1f4b
++#define mmDP6_DP_SEC_TIMESTAMP_BASE_IDX 2
++#define mmDP6_DP_SEC_PACKET_CNTL 0x1f4c
++#define mmDP6_DP_SEC_PACKET_CNTL_BASE_IDX 2
++#define mmDP6_DP_MSE_RATE_CNTL 0x1f4d
++#define mmDP6_DP_MSE_RATE_CNTL_BASE_IDX 2
++#define mmDP6_DP_MSE_RATE_UPDATE 0x1f4f
++#define mmDP6_DP_MSE_RATE_UPDATE_BASE_IDX 2
++#define mmDP6_DP_MSE_SAT0 0x1f50
++#define mmDP6_DP_MSE_SAT0_BASE_IDX 2
++#define mmDP6_DP_MSE_SAT1 0x1f51
++#define mmDP6_DP_MSE_SAT1_BASE_IDX 2
++#define mmDP6_DP_MSE_SAT2 0x1f52
++#define mmDP6_DP_MSE_SAT2_BASE_IDX 2
++#define mmDP6_DP_MSE_SAT_UPDATE 0x1f53
++#define mmDP6_DP_MSE_SAT_UPDATE_BASE_IDX 2
++#define mmDP6_DP_MSE_LINK_TIMING 0x1f54
++#define mmDP6_DP_MSE_LINK_TIMING_BASE_IDX 2
++#define mmDP6_DP_MSE_MISC_CNTL 0x1f55
++#define mmDP6_DP_MSE_MISC_CNTL_BASE_IDX 2
++#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x1f5a
++#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
++#define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL 0x1f5b
++#define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
++#define mmDP6_DP_MSE_SAT0_STATUS 0x1f5d
++#define mmDP6_DP_MSE_SAT0_STATUS_BASE_IDX 2
++#define mmDP6_DP_MSE_SAT1_STATUS 0x1f5e
++#define mmDP6_DP_MSE_SAT1_STATUS_BASE_IDX 2
++#define mmDP6_DP_MSE_SAT2_STATUS 0x1f5f
++#define mmDP6_DP_MSE_SAT2_STATUS_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dcio_uniphy0_dispdec
++// base address: 0x0
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 0x213e
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 0x213f
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 0x2140
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 0x2141
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 0x2142
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 0x2143
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 0x2144
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 0x2145
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 0x2146
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 0x2147
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 0x2148
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 0x2149
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 0x214a
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 0x214b
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 0x214c
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 0x214d
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 0x214e
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 0x214f
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 0x2150
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 0x2151
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 0x2152
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 0x2153
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 0x2154
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 0x2155
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 0x2156
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 0x2157
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 0x2158
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 0x2159
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 0x215a
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 0x215b
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 0x215c
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 0x215d
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32 0x215e
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33 0x215f
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34 0x2160
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35 0x2161
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36 0x2162
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37 0x2163
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38 0x2164
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39 0x2165
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40 0x2166
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41 0x2167
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42 0x2168
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43 0x2169
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44 0x216a
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45 0x216b
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46 0x216c
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47 0x216d
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48 0x216e
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49 0x216f
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50 0x2170
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51 0x2171
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52 0x2172
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53 0x2173
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54 0x2174
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55 0x2175
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56 0x2176
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57 0x2177
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58 0x2178
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59 0x2179
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60 0x217a
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61 0x217b
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62 0x217c
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63 0x217d
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64 0x217e
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65 0x217f
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66 0x2180
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67 0x2181
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68 0x2182
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69 0x2183
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70 0x2184
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71 0x2185
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72 0x2186
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73 0x2187
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74 0x2188
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75 0x2189
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76 0x218a
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77 0x218b
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78 0x218c
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79 0x218d
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80 0x218e
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81 0x218f
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82 0x2190
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83 0x2191
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84 0x2192
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85 0x2193
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86 0x2194
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87 0x2195
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88 0x2196
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89 0x2197
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90 0x2198
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91 0x2199
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92 0x219a
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93 0x219b
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94 0x219c
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95 0x219d
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96 0x219e
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97 0x219f
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98 0x21a0
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99 0x21a1
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100 0x21a2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101 0x21a3
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102 0x21a4
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103 0x21a5
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104 0x21a6
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105 0x21a7
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106 0x21a8
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107 0x21a9
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108 0x21aa
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109 0x21ab
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110 0x21ac
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111 0x21ad
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112 0x21ae
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113 0x21af
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114 0x21b0
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115 0x21b1
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116 0x21b2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117 0x21b3
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118 0x21b4
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119 0x21b5
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120 0x21b6
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121 0x21b7
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122 0x21b8
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123 0x21b9
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124 0x21ba
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125 0x21bb
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126 0x21bc
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127 0x21bd
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128 0x21be
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129 0x21bf
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130 0x21c0
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131 0x21c1
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132 0x21c2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133 0x21c3
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134 0x21c4
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135 0x21c5
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136 0x21c6
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137 0x21c7
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138 0x21c8
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139 0x21c9
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140 0x21ca
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141 0x21cb
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142 0x21cc
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143 0x21cd
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144 0x21ce
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145 0x21cf
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146 0x21d0
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147 0x21d1
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148 0x21d2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149 0x21d3
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150 0x21d4
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151 0x21d5
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152 0x21d6
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153 0x21d7
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154 0x21d8
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155 0x21d9
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156 0x21da
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157 0x21db
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158 0x21dc
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159 0x21dd
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dc_combophycmregs0_dispdec
++// base address: 0x0
++#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE1 0x213e
++#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE1_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE2 0x213f
++#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE2_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE3 0x2140
++#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE3_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM 0x2141
++#define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT 0x2142
++#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL 0x2143
++#define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS0_COMMON_TMDP 0x2144
++#define mmDC_COMBOPHYCMREGS0_COMMON_TMDP_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS 0x2145
++#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL 0x2146
++#define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1 0x2147
++#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2 0x2148
++#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3 0x2149
++#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4 0x214a
++#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5 0x214b
++#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6 0x214c
++#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7 0x214d
++#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dc_combophytxregs0_dispdec
++// base address: 0x0
++#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0 0x215e
++#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0 0x215f
++#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2160
++#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0 0x2161
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0 0x2162
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0 0x2163
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0 0x2164
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0 0x2165
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0 0x2166
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0 0x2167
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0 0x2168
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0 0x2169
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0 0x216a
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0 0x216b
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0 0x216c
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0 0x216d
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1 0x216e
++#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1 0x216f
++#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2170
++#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1 0x2171
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1 0x2172
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1 0x2173
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1 0x2174
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1 0x2175
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1 0x2176
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1 0x2177
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1 0x2178
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1 0x2179
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1 0x217a
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1 0x217b
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1 0x217c
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1 0x217d
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2 0x217e
++#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2 0x217f
++#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2180
++#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2 0x2181
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2 0x2182
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2 0x2183
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2 0x2184
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2 0x2185
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2 0x2186
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2 0x2187
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2 0x2188
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2 0x2189
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2 0x218a
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2 0x218b
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2 0x218c
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2 0x218d
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3 0x218e
++#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3 0x218f
++#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2190
++#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3 0x2191
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3 0x2192
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3 0x2193
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3 0x2194
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3 0x2195
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3 0x2196
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3 0x2197
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3 0x2198
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3 0x2199
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3 0x219a
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3 0x219b
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3 0x219c
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3 0x219d
++#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dc_combophypllregs0_dispdec
++// base address: 0x0
++#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0 0x219e
++#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1 0x219f
++#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2 0x21a0
++#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3 0x21a1
++#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE 0x21a2
++#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE 0x21a3
++#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS0_CAL_CTRL 0x21a4
++#define mmDC_COMBOPHYPLLREGS0_CAL_CTRL_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL 0x21a5
++#define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS0_VREG_CFG 0x21a7
++#define mmDC_COMBOPHYPLLREGS0_VREG_CFG_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS0_OBSERVE0 0x21a8
++#define mmDC_COMBOPHYPLLREGS0_OBSERVE0_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS0_OBSERVE1 0x21a9
++#define mmDC_COMBOPHYPLLREGS0_OBSERVE1_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS0_DFT_OUT 0x21aa
++#define mmDC_COMBOPHYPLLREGS0_DFT_OUT_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dcio_uniphy1_dispdec
++// base address: 0x320
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x2206
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x2207
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x2208
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x2209
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x220a
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x220b
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x220c
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x220d
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x220e
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x220f
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x2210
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x2211
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x2212
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x2213
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x2214
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x2215
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x2216
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x2217
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x2218
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x2219
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x221a
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x221b
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x221c
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x221d
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x221e
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x221f
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x2220
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x2221
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x2222
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x2223
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x2224
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x2225
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 0x2226
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 0x2227
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 0x2228
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 0x2229
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 0x222a
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 0x222b
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 0x222c
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 0x222d
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 0x222e
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 0x222f
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 0x2230
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 0x2231
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 0x2232
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 0x2233
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 0x2234
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 0x2235
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 0x2236
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 0x2237
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 0x2238
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 0x2239
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 0x223a
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 0x223b
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 0x223c
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 0x223d
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 0x223e
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 0x223f
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58 0x2240
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59 0x2241
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60 0x2242
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61 0x2243
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62 0x2244
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63 0x2245
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64 0x2246
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65 0x2247
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66 0x2248
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67 0x2249
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68 0x224a
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69 0x224b
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70 0x224c
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71 0x224d
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72 0x224e
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73 0x224f
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74 0x2250
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75 0x2251
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76 0x2252
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77 0x2253
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78 0x2254
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79 0x2255
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80 0x2256
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81 0x2257
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82 0x2258
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83 0x2259
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84 0x225a
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85 0x225b
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86 0x225c
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87 0x225d
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88 0x225e
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89 0x225f
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90 0x2260
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91 0x2261
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92 0x2262
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93 0x2263
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94 0x2264
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95 0x2265
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96 0x2266
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97 0x2267
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98 0x2268
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99 0x2269
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100 0x226a
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101 0x226b
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102 0x226c
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103 0x226d
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104 0x226e
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105 0x226f
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106 0x2270
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107 0x2271
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108 0x2272
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109 0x2273
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110 0x2274
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111 0x2275
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112 0x2276
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113 0x2277
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114 0x2278
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115 0x2279
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116 0x227a
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117 0x227b
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118 0x227c
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119 0x227d
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120 0x227e
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121 0x227f
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122 0x2280
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123 0x2281
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124 0x2282
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125 0x2283
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126 0x2284
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127 0x2285
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128 0x2286
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129 0x2287
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130 0x2288
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131 0x2289
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132 0x228a
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133 0x228b
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134 0x228c
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135 0x228d
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136 0x228e
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137 0x228f
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138 0x2290
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139 0x2291
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140 0x2292
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141 0x2293
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142 0x2294
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143 0x2295
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144 0x2296
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145 0x2297
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146 0x2298
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147 0x2299
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148 0x229a
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149 0x229b
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150 0x229c
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151 0x229d
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152 0x229e
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153 0x229f
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154 0x22a0
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155 0x22a1
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156 0x22a2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157 0x22a3
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158 0x22a4
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159 0x22a5
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dc_combophycmregs1_dispdec
++// base address: 0x320
++#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE1 0x2206
++#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE1_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE2 0x2207
++#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE2_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE3 0x2208
++#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE3_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM 0x2209
++#define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT 0x220a
++#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL 0x220b
++#define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS1_COMMON_TMDP 0x220c
++#define mmDC_COMBOPHYCMREGS1_COMMON_TMDP_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS 0x220d
++#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL 0x220e
++#define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1 0x220f
++#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2 0x2210
++#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3 0x2211
++#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4 0x2212
++#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5 0x2213
++#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6 0x2214
++#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7 0x2215
++#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dc_combophytxregs1_dispdec
++// base address: 0x320
++#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0 0x2226
++#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0 0x2227
++#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2228
++#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0 0x2229
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0 0x222a
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0 0x222b
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0 0x222c
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0 0x222d
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0 0x222e
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0 0x222f
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0 0x2230
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0 0x2231
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0 0x2232
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0 0x2233
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0 0x2234
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0 0x2235
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1 0x2236
++#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1 0x2237
++#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2238
++#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1 0x2239
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1 0x223a
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1 0x223b
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1 0x223c
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1 0x223d
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1 0x223e
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1 0x223f
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1 0x2240
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1 0x2241
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1 0x2242
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1 0x2243
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1 0x2244
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1 0x2245
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2 0x2246
++#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2 0x2247
++#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2248
++#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2 0x2249
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2 0x224a
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2 0x224b
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2 0x224c
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2 0x224d
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2 0x224e
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2 0x224f
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2 0x2250
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2 0x2251
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2 0x2252
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2 0x2253
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2 0x2254
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2 0x2255
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3 0x2256
++#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3 0x2257
++#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2258
++#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3 0x2259
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3 0x225a
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3 0x225b
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3 0x225c
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3 0x225d
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3 0x225e
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3 0x225f
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3 0x2260
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3 0x2261
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3 0x2262
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3 0x2263
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3 0x2264
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3 0x2265
++#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dc_combophypllregs1_dispdec
++// base address: 0x320
++#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0 0x2266
++#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1 0x2267
++#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2 0x2268
++#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3 0x2269
++#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE 0x226a
++#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE 0x226b
++#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS1_CAL_CTRL 0x226c
++#define mmDC_COMBOPHYPLLREGS1_CAL_CTRL_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL 0x226d
++#define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS1_VREG_CFG 0x226f
++#define mmDC_COMBOPHYPLLREGS1_VREG_CFG_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS1_OBSERVE0 0x2270
++#define mmDC_COMBOPHYPLLREGS1_OBSERVE0_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS1_OBSERVE1 0x2271
++#define mmDC_COMBOPHYPLLREGS1_OBSERVE1_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS1_DFT_OUT 0x2272
++#define mmDC_COMBOPHYPLLREGS1_DFT_OUT_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dcio_uniphy2_dispdec
++// base address: 0x640
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x22ce
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x22cf
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x22d0
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x22d1
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x22d2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x22d3
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x22d4
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x22d5
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x22d6
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x22d7
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x22d8
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x22d9
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x22da
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x22db
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x22dc
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x22dd
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x22de
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x22df
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x22e0
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x22e1
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x22e2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x22e3
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x22e4
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x22e5
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x22e6
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x22e7
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x22e8
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x22e9
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x22ea
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x22eb
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x22ec
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x22ed
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 0x22ee
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 0x22ef
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 0x22f0
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 0x22f1
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 0x22f2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 0x22f3
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 0x22f4
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 0x22f5
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 0x22f6
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 0x22f7
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 0x22f8
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 0x22f9
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 0x22fa
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 0x22fb
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 0x22fc
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 0x22fd
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 0x22fe
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 0x22ff
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 0x2300
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 0x2301
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 0x2302
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 0x2303
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 0x2304
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 0x2305
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 0x2306
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 0x2307
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58 0x2308
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59 0x2309
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60 0x230a
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61 0x230b
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62 0x230c
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63 0x230d
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64 0x230e
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65 0x230f
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66 0x2310
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67 0x2311
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68 0x2312
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69 0x2313
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70 0x2314
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71 0x2315
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72 0x2316
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73 0x2317
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74 0x2318
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75 0x2319
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76 0x231a
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77 0x231b
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78 0x231c
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79 0x231d
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80 0x231e
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81 0x231f
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82 0x2320
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83 0x2321
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84 0x2322
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85 0x2323
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86 0x2324
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87 0x2325
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88 0x2326
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89 0x2327
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90 0x2328
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91 0x2329
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92 0x232a
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93 0x232b
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94 0x232c
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95 0x232d
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96 0x232e
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97 0x232f
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98 0x2330
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99 0x2331
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100 0x2332
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101 0x2333
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102 0x2334
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103 0x2335
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104 0x2336
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105 0x2337
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106 0x2338
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107 0x2339
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108 0x233a
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109 0x233b
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110 0x233c
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111 0x233d
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112 0x233e
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113 0x233f
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114 0x2340
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115 0x2341
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116 0x2342
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117 0x2343
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118 0x2344
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119 0x2345
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120 0x2346
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121 0x2347
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122 0x2348
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123 0x2349
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124 0x234a
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125 0x234b
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126 0x234c
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127 0x234d
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128 0x234e
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129 0x234f
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130 0x2350
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131 0x2351
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132 0x2352
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133 0x2353
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134 0x2354
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135 0x2355
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136 0x2356
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137 0x2357
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138 0x2358
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139 0x2359
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140 0x235a
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141 0x235b
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142 0x235c
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143 0x235d
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144 0x235e
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145 0x235f
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146 0x2360
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147 0x2361
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148 0x2362
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149 0x2363
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150 0x2364
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151 0x2365
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152 0x2366
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153 0x2367
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154 0x2368
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155 0x2369
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156 0x236a
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157 0x236b
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158 0x236c
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159 0x236d
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dc_combophycmregs2_dispdec
++// base address: 0x640
++#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE1 0x22ce
++#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE1_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE2 0x22cf
++#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE2_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE3 0x22d0
++#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE3_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM 0x22d1
++#define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT 0x22d2
++#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL 0x22d3
++#define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS2_COMMON_TMDP 0x22d4
++#define mmDC_COMBOPHYCMREGS2_COMMON_TMDP_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS 0x22d5
++#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL 0x22d6
++#define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1 0x22d7
++#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2 0x22d8
++#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3 0x22d9
++#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4 0x22da
++#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5 0x22db
++#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6 0x22dc
++#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7 0x22dd
++#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dc_combophytxregs2_dispdec
++// base address: 0x640
++#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0 0x22ee
++#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0 0x22ef
++#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x22f0
++#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0 0x22f1
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0 0x22f2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0 0x22f3
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0 0x22f4
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0 0x22f5
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0 0x22f6
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0 0x22f7
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0 0x22f8
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0 0x22f9
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0 0x22fa
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0 0x22fb
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0 0x22fc
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0 0x22fd
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1 0x22fe
++#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1 0x22ff
++#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2300
++#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1 0x2301
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1 0x2302
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1 0x2303
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1 0x2304
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1 0x2305
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1 0x2306
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1 0x2307
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1 0x2308
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1 0x2309
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1 0x230a
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1 0x230b
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1 0x230c
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1 0x230d
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2 0x230e
++#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2 0x230f
++#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2310
++#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2 0x2311
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2 0x2312
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2 0x2313
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2 0x2314
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2 0x2315
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2 0x2316
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2 0x2317
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2 0x2318
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2 0x2319
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2 0x231a
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2 0x231b
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2 0x231c
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2 0x231d
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3 0x231e
++#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3 0x231f
++#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2320
++#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3 0x2321
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3 0x2322
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3 0x2323
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3 0x2324
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3 0x2325
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3 0x2326
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3 0x2327
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3 0x2328
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3 0x2329
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3 0x232a
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3 0x232b
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3 0x232c
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3 0x232d
++#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dc_combophypllregs2_dispdec
++// base address: 0x640
++#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0 0x232e
++#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1 0x232f
++#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2 0x2330
++#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3 0x2331
++#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE 0x2332
++#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE 0x2333
++#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS2_CAL_CTRL 0x2334
++#define mmDC_COMBOPHYPLLREGS2_CAL_CTRL_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL 0x2335
++#define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS2_VREG_CFG 0x2337
++#define mmDC_COMBOPHYPLLREGS2_VREG_CFG_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS2_OBSERVE0 0x2338
++#define mmDC_COMBOPHYPLLREGS2_OBSERVE0_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS2_OBSERVE1 0x2339
++#define mmDC_COMBOPHYPLLREGS2_OBSERVE1_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS2_DFT_OUT 0x233a
++#define mmDC_COMBOPHYPLLREGS2_DFT_OUT_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dcio_uniphy3_dispdec
++// base address: 0x960
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x2396
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x2397
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x2398
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x2399
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x239a
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x239b
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x239c
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x239d
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x239e
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x239f
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x23a0
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x23a1
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x23a2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x23a3
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x23a4
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x23a5
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x23a6
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x23a7
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x23a8
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x23a9
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x23aa
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x23ab
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x23ac
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x23ad
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x23ae
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x23af
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x23b0
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x23b1
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x23b2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x23b3
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x23b4
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x23b5
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 0x23b6
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 0x23b7
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 0x23b8
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 0x23b9
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 0x23ba
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 0x23bb
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 0x23bc
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 0x23bd
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 0x23be
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 0x23bf
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 0x23c0
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 0x23c1
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 0x23c2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 0x23c3
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 0x23c4
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 0x23c5
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 0x23c6
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 0x23c7
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 0x23c8
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 0x23c9
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 0x23ca
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 0x23cb
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 0x23cc
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 0x23cd
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 0x23ce
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 0x23cf
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58 0x23d0
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59 0x23d1
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60 0x23d2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61 0x23d3
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62 0x23d4
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63 0x23d5
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64 0x23d6
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65 0x23d7
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66 0x23d8
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67 0x23d9
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68 0x23da
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69 0x23db
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70 0x23dc
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71 0x23dd
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72 0x23de
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73 0x23df
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74 0x23e0
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75 0x23e1
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76 0x23e2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77 0x23e3
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78 0x23e4
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79 0x23e5
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80 0x23e6
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81 0x23e7
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82 0x23e8
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83 0x23e9
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84 0x23ea
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85 0x23eb
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86 0x23ec
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87 0x23ed
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88 0x23ee
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89 0x23ef
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90 0x23f0
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91 0x23f1
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92 0x23f2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93 0x23f3
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94 0x23f4
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95 0x23f5
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96 0x23f6
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97 0x23f7
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98 0x23f8
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99 0x23f9
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100 0x23fa
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101 0x23fb
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102 0x23fc
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103 0x23fd
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104 0x23fe
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105 0x23ff
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106 0x2400
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107 0x2401
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108 0x2402
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109 0x2403
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110 0x2404
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111 0x2405
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112 0x2406
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113 0x2407
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114 0x2408
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115 0x2409
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116 0x240a
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117 0x240b
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118 0x240c
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119 0x240d
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120 0x240e
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121 0x240f
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122 0x2410
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123 0x2411
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124 0x2412
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125 0x2413
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126 0x2414
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127 0x2415
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128 0x2416
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129 0x2417
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130 0x2418
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131 0x2419
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132 0x241a
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133 0x241b
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134 0x241c
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135 0x241d
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136 0x241e
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137 0x241f
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138 0x2420
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139 0x2421
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140 0x2422
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141 0x2423
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142 0x2424
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143 0x2425
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144 0x2426
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145 0x2427
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146 0x2428
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147 0x2429
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148 0x242a
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149 0x242b
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150 0x242c
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151 0x242d
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152 0x242e
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153 0x242f
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154 0x2430
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155 0x2431
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156 0x2432
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157 0x2433
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158 0x2434
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159 0x2435
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dc_combophycmregs3_dispdec
++// base address: 0x960
++#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE1 0x2396
++#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE1_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE2 0x2397
++#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE2_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE3 0x2398
++#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE3_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM 0x2399
++#define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT 0x239a
++#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL 0x239b
++#define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS3_COMMON_TMDP 0x239c
++#define mmDC_COMBOPHYCMREGS3_COMMON_TMDP_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS 0x239d
++#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL 0x239e
++#define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1 0x239f
++#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2 0x23a0
++#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3 0x23a1
++#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4 0x23a2
++#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5 0x23a3
++#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6 0x23a4
++#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7 0x23a5
++#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dc_combophytxregs3_dispdec
++// base address: 0x960
++#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0 0x23b6
++#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0 0x23b7
++#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x23b8
++#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0 0x23b9
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0 0x23ba
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0 0x23bb
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0 0x23bc
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0 0x23bd
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0 0x23be
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0 0x23bf
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0 0x23c0
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0 0x23c1
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0 0x23c2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0 0x23c3
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0 0x23c4
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0 0x23c5
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1 0x23c6
++#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1 0x23c7
++#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x23c8
++#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1 0x23c9
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1 0x23ca
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1 0x23cb
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1 0x23cc
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1 0x23cd
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1 0x23ce
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1 0x23cf
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1 0x23d0
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1 0x23d1
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1 0x23d2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1 0x23d3
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1 0x23d4
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1 0x23d5
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2 0x23d6
++#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2 0x23d7
++#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x23d8
++#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2 0x23d9
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2 0x23da
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2 0x23db
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2 0x23dc
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2 0x23dd
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2 0x23de
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2 0x23df
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2 0x23e0
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2 0x23e1
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2 0x23e2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2 0x23e3
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2 0x23e4
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2 0x23e5
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3 0x23e6
++#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3 0x23e7
++#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x23e8
++#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3 0x23e9
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3 0x23ea
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3 0x23eb
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3 0x23ec
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3 0x23ed
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3 0x23ee
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3 0x23ef
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3 0x23f0
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3 0x23f1
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3 0x23f2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3 0x23f3
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3 0x23f4
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3 0x23f5
++#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dc_combophypllregs3_dispdec
++// base address: 0x960
++#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0 0x23f6
++#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1 0x23f7
++#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2 0x23f8
++#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3 0x23f9
++#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE 0x23fa
++#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE 0x23fb
++#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS3_CAL_CTRL 0x23fc
++#define mmDC_COMBOPHYPLLREGS3_CAL_CTRL_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL 0x23fd
++#define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS3_VREG_CFG 0x23ff
++#define mmDC_COMBOPHYPLLREGS3_VREG_CFG_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS3_OBSERVE0 0x2400
++#define mmDC_COMBOPHYPLLREGS3_OBSERVE0_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS3_OBSERVE1 0x2401
++#define mmDC_COMBOPHYPLLREGS3_OBSERVE1_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS3_DFT_OUT 0x2402
++#define mmDC_COMBOPHYPLLREGS3_DFT_OUT_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dcio_uniphy4_dispdec
++// base address: 0xc80
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0x245e
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0x245f
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0x2460
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0x2461
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0x2462
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0x2463
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0x2464
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0x2465
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0x2466
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0x2467
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0x2468
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0x2469
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0x246a
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0x246b
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0x246c
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0x246d
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0x246e
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0x246f
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0x2470
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0x2471
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0x2472
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0x2473
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0x2474
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0x2475
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0x2476
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0x2477
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0x2478
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0x2479
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0x247a
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0x247b
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0x247c
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0x247d
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32 0x247e
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33 0x247f
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34 0x2480
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35 0x2481
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36 0x2482
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37 0x2483
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38 0x2484
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39 0x2485
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40 0x2486
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41 0x2487
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42 0x2488
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43 0x2489
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44 0x248a
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45 0x248b
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46 0x248c
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47 0x248d
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48 0x248e
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49 0x248f
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50 0x2490
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51 0x2491
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52 0x2492
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53 0x2493
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54 0x2494
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55 0x2495
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56 0x2496
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57 0x2497
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58 0x2498
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59 0x2499
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60 0x249a
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61 0x249b
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62 0x249c
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63 0x249d
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64 0x249e
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65 0x249f
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66 0x24a0
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67 0x24a1
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68 0x24a2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69 0x24a3
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70 0x24a4
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71 0x24a5
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72 0x24a6
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73 0x24a7
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74 0x24a8
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75 0x24a9
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76 0x24aa
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77 0x24ab
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78 0x24ac
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79 0x24ad
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80 0x24ae
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81 0x24af
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82 0x24b0
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83 0x24b1
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84 0x24b2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85 0x24b3
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86 0x24b4
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87 0x24b5
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88 0x24b6
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89 0x24b7
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90 0x24b8
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91 0x24b9
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92 0x24ba
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93 0x24bb
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94 0x24bc
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95 0x24bd
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96 0x24be
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97 0x24bf
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98 0x24c0
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99 0x24c1
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100 0x24c2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101 0x24c3
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102 0x24c4
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103 0x24c5
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104 0x24c6
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105 0x24c7
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106 0x24c8
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107 0x24c9
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108 0x24ca
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109 0x24cb
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110 0x24cc
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111 0x24cd
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112 0x24ce
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113 0x24cf
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114 0x24d0
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115 0x24d1
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116 0x24d2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117 0x24d3
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118 0x24d4
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119 0x24d5
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120 0x24d6
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121 0x24d7
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122 0x24d8
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123 0x24d9
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124 0x24da
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125 0x24db
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126 0x24dc
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127 0x24dd
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128 0x24de
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129 0x24df
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130 0x24e0
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131 0x24e1
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132 0x24e2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133 0x24e3
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134 0x24e4
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135 0x24e5
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136 0x24e6
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137 0x24e7
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138 0x24e8
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139 0x24e9
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140 0x24ea
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141 0x24eb
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142 0x24ec
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143 0x24ed
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144 0x24ee
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145 0x24ef
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146 0x24f0
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147 0x24f1
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148 0x24f2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149 0x24f3
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150 0x24f4
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151 0x24f5
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152 0x24f6
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153 0x24f7
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154 0x24f8
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155 0x24f9
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156 0x24fa
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157 0x24fb
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158 0x24fc
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159 0x24fd
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dc_combophycmregs4_dispdec
++// base address: 0xc80
++#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE1 0x245e
++#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE1_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE2 0x245f
++#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE2_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE3 0x2460
++#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE3_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM 0x2461
++#define mmDC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT 0x2462
++#define mmDC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS4_COMMON_TXCNTRL 0x2463
++#define mmDC_COMBOPHYCMREGS4_COMMON_TXCNTRL_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS4_COMMON_TMDP 0x2464
++#define mmDC_COMBOPHYCMREGS4_COMMON_TMDP_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS4_COMMON_LANE_RESETS 0x2465
++#define mmDC_COMBOPHYCMREGS4_COMMON_LANE_RESETS_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL 0x2466
++#define mmDC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU1 0x2467
++#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU1_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU2 0x2468
++#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU2_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU3 0x2469
++#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU3_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU4 0x246a
++#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU4_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU5 0x246b
++#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU5_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU6 0x246c
++#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU6_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU7 0x246d
++#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU7_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dc_combophytxregs4_dispdec
++// base address: 0xc80
++#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0 0x247e
++#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0 0x247f
++#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2480
++#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0 0x2481
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0 0x2482
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0 0x2483
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0 0x2484
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0 0x2485
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0 0x2486
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0 0x2487
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0 0x2488
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0 0x2489
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0 0x248a
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0 0x248b
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0 0x248c
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0 0x248d
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1 0x248e
++#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1 0x248f
++#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2490
++#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1 0x2491
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1 0x2492
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1 0x2493
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1 0x2494
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1 0x2495
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1 0x2496
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1 0x2497
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1 0x2498
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1 0x2499
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1 0x249a
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1 0x249b
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1 0x249c
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1 0x249d
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2 0x249e
++#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2 0x249f
++#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x24a0
++#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2 0x24a1
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2 0x24a2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2 0x24a3
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2 0x24a4
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2 0x24a5
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2 0x24a6
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2 0x24a7
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2 0x24a8
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2 0x24a9
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2 0x24aa
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2 0x24ab
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2 0x24ac
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2 0x24ad
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3 0x24ae
++#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3 0x24af
++#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x24b0
++#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3 0x24b1
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3 0x24b2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3 0x24b3
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3 0x24b4
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3 0x24b5
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3 0x24b6
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3 0x24b7
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3 0x24b8
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3 0x24b9
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3 0x24ba
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3 0x24bb
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3 0x24bc
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3 0x24bd
++#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dc_combophypllregs4_dispdec
++// base address: 0xc80
++#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL0 0x24be
++#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL0_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL1 0x24bf
++#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL1_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL2 0x24c0
++#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL2_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL3 0x24c1
++#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL3_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS4_BW_CTRL_COARSE 0x24c2
++#define mmDC_COMBOPHYPLLREGS4_BW_CTRL_COARSE_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS4_BW_CTRL_FINE 0x24c3
++#define mmDC_COMBOPHYPLLREGS4_BW_CTRL_FINE_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS4_CAL_CTRL 0x24c4
++#define mmDC_COMBOPHYPLLREGS4_CAL_CTRL_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS4_LOOP_CTRL 0x24c5
++#define mmDC_COMBOPHYPLLREGS4_LOOP_CTRL_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS4_VREG_CFG 0x24c7
++#define mmDC_COMBOPHYPLLREGS4_VREG_CFG_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS4_OBSERVE0 0x24c8
++#define mmDC_COMBOPHYPLLREGS4_OBSERVE0_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS4_OBSERVE1 0x24c9
++#define mmDC_COMBOPHYPLLREGS4_OBSERVE1_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS4_DFT_OUT 0x24ca
++#define mmDC_COMBOPHYPLLREGS4_DFT_OUT_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dcio_uniphy5_dispdec
++// base address: 0xfa0
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0 0x2526
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1 0x2527
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2 0x2528
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3 0x2529
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4 0x252a
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5 0x252b
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6 0x252c
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7 0x252d
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8 0x252e
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9 0x252f
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10 0x2530
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11 0x2531
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12 0x2532
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13 0x2533
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14 0x2534
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15 0x2535
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16 0x2536
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17 0x2537
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18 0x2538
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19 0x2539
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20 0x253a
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21 0x253b
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22 0x253c
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23 0x253d
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24 0x253e
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25 0x253f
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26 0x2540
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27 0x2541
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28 0x2542
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29 0x2543
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30 0x2544
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31 0x2545
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32 0x2546
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33 0x2547
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34 0x2548
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35 0x2549
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36 0x254a
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37 0x254b
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38 0x254c
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39 0x254d
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40 0x254e
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41 0x254f
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42 0x2550
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43 0x2551
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44 0x2552
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45 0x2553
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46 0x2554
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47 0x2555
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48 0x2556
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49 0x2557
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50 0x2558
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51 0x2559
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52 0x255a
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53 0x255b
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54 0x255c
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55 0x255d
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56 0x255e
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57 0x255f
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58 0x2560
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59 0x2561
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60 0x2562
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61 0x2563
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62 0x2564
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63 0x2565
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64 0x2566
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65 0x2567
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66 0x2568
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67 0x2569
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68 0x256a
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69 0x256b
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70 0x256c
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71 0x256d
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72 0x256e
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73 0x256f
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74 0x2570
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75 0x2571
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76 0x2572
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77 0x2573
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78 0x2574
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79 0x2575
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80 0x2576
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81 0x2577
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82 0x2578
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83 0x2579
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84 0x257a
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85 0x257b
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86 0x257c
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87 0x257d
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88 0x257e
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89 0x257f
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90 0x2580
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91 0x2581
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92 0x2582
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93 0x2583
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94 0x2584
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95 0x2585
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96 0x2586
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97 0x2587
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98 0x2588
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99 0x2589
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100 0x258a
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101 0x258b
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102 0x258c
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103 0x258d
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104 0x258e
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105 0x258f
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106 0x2590
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107 0x2591
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108 0x2592
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109 0x2593
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110 0x2594
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111 0x2595
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112 0x2596
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113 0x2597
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114 0x2598
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115 0x2599
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116 0x259a
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117 0x259b
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118 0x259c
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119 0x259d
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120 0x259e
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121 0x259f
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122 0x25a0
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123 0x25a1
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124 0x25a2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125 0x25a3
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126 0x25a4
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127 0x25a5
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128 0x25a6
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129 0x25a7
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130 0x25a8
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131 0x25a9
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132 0x25aa
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133 0x25ab
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134 0x25ac
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135 0x25ad
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136 0x25ae
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137 0x25af
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138 0x25b0
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139 0x25b1
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140 0x25b2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141 0x25b3
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142 0x25b4
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143 0x25b5
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144 0x25b6
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145 0x25b7
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146 0x25b8
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147 0x25b9
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148 0x25ba
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149 0x25bb
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150 0x25bc
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151 0x25bd
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152 0x25be
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153 0x25bf
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154 0x25c0
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155 0x25c1
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156 0x25c2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157 0x25c3
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158 0x25c4
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159 0x25c5
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dc_combophycmregs5_dispdec
++// base address: 0xfa0
++#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE1 0x2526
++#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE1_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE2 0x2527
++#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE2_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE3 0x2528
++#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE3_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM 0x2529
++#define mmDC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT 0x252a
++#define mmDC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS5_COMMON_TXCNTRL 0x252b
++#define mmDC_COMBOPHYCMREGS5_COMMON_TXCNTRL_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS5_COMMON_TMDP 0x252c
++#define mmDC_COMBOPHYCMREGS5_COMMON_TMDP_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS5_COMMON_LANE_RESETS 0x252d
++#define mmDC_COMBOPHYCMREGS5_COMMON_LANE_RESETS_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL 0x252e
++#define mmDC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU1 0x252f
++#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU1_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU2 0x2530
++#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU2_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU3 0x2531
++#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU3_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU4 0x2532
++#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU4_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU5 0x2533
++#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU5_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU6 0x2534
++#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU6_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU7 0x2535
++#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU7_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dc_combophytxregs5_dispdec
++// base address: 0xfa0
++#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0 0x2546
++#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0 0x2547
++#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2548
++#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0 0x2549
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0 0x254a
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0 0x254b
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0 0x254c
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0 0x254d
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0 0x254e
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0 0x254f
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0 0x2550
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0 0x2551
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0 0x2552
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0 0x2553
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0 0x2554
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0 0x2555
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1 0x2556
++#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1 0x2557
++#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2558
++#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1 0x2559
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1 0x255a
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1 0x255b
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1 0x255c
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1 0x255d
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1 0x255e
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1 0x255f
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1 0x2560
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1 0x2561
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1 0x2562
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1 0x2563
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1 0x2564
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1 0x2565
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2 0x2566
++#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2 0x2567
++#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2568
++#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2 0x2569
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2 0x256a
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2 0x256b
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2 0x256c
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2 0x256d
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2 0x256e
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2 0x256f
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2 0x2570
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2 0x2571
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2 0x2572
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2 0x2573
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2 0x2574
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2 0x2575
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3 0x2576
++#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3 0x2577
++#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2578
++#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3 0x2579
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3 0x257a
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3 0x257b
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3 0x257c
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3 0x257d
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3 0x257e
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3 0x257f
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3 0x2580
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3 0x2581
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3 0x2582
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3 0x2583
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3 0x2584
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3 0x2585
++#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dc_combophypllregs5_dispdec
++// base address: 0xfa0
++#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL0 0x2586
++#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL0_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL1 0x2587
++#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL1_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL2 0x2588
++#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL2_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL3 0x2589
++#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL3_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS5_BW_CTRL_COARSE 0x258a
++#define mmDC_COMBOPHYPLLREGS5_BW_CTRL_COARSE_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS5_BW_CTRL_FINE 0x258b
++#define mmDC_COMBOPHYPLLREGS5_BW_CTRL_FINE_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS5_CAL_CTRL 0x258c
++#define mmDC_COMBOPHYPLLREGS5_CAL_CTRL_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS5_LOOP_CTRL 0x258d
++#define mmDC_COMBOPHYPLLREGS5_LOOP_CTRL_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS5_VREG_CFG 0x258f
++#define mmDC_COMBOPHYPLLREGS5_VREG_CFG_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS5_OBSERVE0 0x2590
++#define mmDC_COMBOPHYPLLREGS5_OBSERVE0_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS5_OBSERVE1 0x2591
++#define mmDC_COMBOPHYPLLREGS5_OBSERVE1_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS5_DFT_OUT 0x2592
++#define mmDC_COMBOPHYPLLREGS5_DFT_OUT_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dcio_uniphy6_dispdec
++// base address: 0x12c0
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0 0x25ee
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1 0x25ef
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2 0x25f0
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3 0x25f1
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4 0x25f2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5 0x25f3
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6 0x25f4
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7 0x25f5
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8 0x25f6
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9 0x25f7
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10 0x25f8
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11 0x25f9
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12 0x25fa
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13 0x25fb
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14 0x25fc
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15 0x25fd
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16 0x25fe
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17 0x25ff
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18 0x2600
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19 0x2601
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20 0x2602
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21 0x2603
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22 0x2604
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23 0x2605
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24 0x2606
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25 0x2607
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26 0x2608
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27 0x2609
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28 0x260a
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29 0x260b
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30 0x260c
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31 0x260d
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32 0x260e
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33 0x260f
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34 0x2610
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35 0x2611
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36 0x2612
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37 0x2613
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38 0x2614
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39 0x2615
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40 0x2616
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41 0x2617
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42 0x2618
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43 0x2619
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44 0x261a
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45 0x261b
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46 0x261c
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47 0x261d
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48 0x261e
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49 0x261f
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50 0x2620
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51 0x2621
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52 0x2622
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53 0x2623
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54 0x2624
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55 0x2625
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56 0x2626
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57 0x2627
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED58 0x2628
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED59 0x2629
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED60 0x262a
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED61 0x262b
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED62 0x262c
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED63 0x262d
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED64 0x262e
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED65 0x262f
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED66 0x2630
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED67 0x2631
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED68 0x2632
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED69 0x2633
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED70 0x2634
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED71 0x2635
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED72 0x2636
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED73 0x2637
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED74 0x2638
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED75 0x2639
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED76 0x263a
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED77 0x263b
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED78 0x263c
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED79 0x263d
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED80 0x263e
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED81 0x263f
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED82 0x2640
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED83 0x2641
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED84 0x2642
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED85 0x2643
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED86 0x2644
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED87 0x2645
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED88 0x2646
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED89 0x2647
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED90 0x2648
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED91 0x2649
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED92 0x264a
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED93 0x264b
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED94 0x264c
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED95 0x264d
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED96 0x264e
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED97 0x264f
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED98 0x2650
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED99 0x2651
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED100 0x2652
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED101 0x2653
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED102 0x2654
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED103 0x2655
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED104 0x2656
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED105 0x2657
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED106 0x2658
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED107 0x2659
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED108 0x265a
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED109 0x265b
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED110 0x265c
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED111 0x265d
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED112 0x265e
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED113 0x265f
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED114 0x2660
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED115 0x2661
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED116 0x2662
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED117 0x2663
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED118 0x2664
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED119 0x2665
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED120 0x2666
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED121 0x2667
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED122 0x2668
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED123 0x2669
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED124 0x266a
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED125 0x266b
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED126 0x266c
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED127 0x266d
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED128 0x266e
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED129 0x266f
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED130 0x2670
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED131 0x2671
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED132 0x2672
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED133 0x2673
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED134 0x2674
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED135 0x2675
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED136 0x2676
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED137 0x2677
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED138 0x2678
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED139 0x2679
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED140 0x267a
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED141 0x267b
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED142 0x267c
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED143 0x267d
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED144 0x267e
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED145 0x267f
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED146 0x2680
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED147 0x2681
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED148 0x2682
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED149 0x2683
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED150 0x2684
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED151 0x2685
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED152 0x2686
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED153 0x2687
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED154 0x2688
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED155 0x2689
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED156 0x268a
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED157 0x268b
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED158 0x268c
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED159 0x268d
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dc_combophycmregs6_dispdec
++// base address: 0x12c0
++#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE1 0x25ee
++#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE1_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE2 0x25ef
++#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE2_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE3 0x25f0
++#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE3_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM 0x25f1
++#define mmDC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT 0x25f2
++#define mmDC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS6_COMMON_TXCNTRL 0x25f3
++#define mmDC_COMBOPHYCMREGS6_COMMON_TXCNTRL_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS6_COMMON_TMDP 0x25f4
++#define mmDC_COMBOPHYCMREGS6_COMMON_TMDP_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS6_COMMON_LANE_RESETS 0x25f5
++#define mmDC_COMBOPHYCMREGS6_COMMON_LANE_RESETS_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL 0x25f6
++#define mmDC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU1 0x25f7
++#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU1_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU2 0x25f8
++#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU2_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU3 0x25f9
++#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU3_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU4 0x25fa
++#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU4_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU5 0x25fb
++#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU5_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU6 0x25fc
++#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU6_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU7 0x25fd
++#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU7_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dc_combophytxregs6_dispdec
++// base address: 0x12c0
++#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0 0x260e
++#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0 0x260f
++#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2610
++#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE0 0x2611
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE0 0x2612
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE0 0x2613
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE0 0x2614
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE0 0x2615
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE0 0x2616
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE0 0x2617
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE0 0x2618
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE0 0x2619
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE0 0x261a
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE0 0x261b
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE0 0x261c
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE0 0x261d
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1 0x261e
++#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1 0x261f
++#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2620
++#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE1 0x2621
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE1 0x2622
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE1 0x2623
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE1 0x2624
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE1 0x2625
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE1 0x2626
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE1 0x2627
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE1 0x2628
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE1 0x2629
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE1 0x262a
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE1 0x262b
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE1 0x262c
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE1 0x262d
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2 0x262e
++#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2 0x262f
++#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2630
++#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE2 0x2631
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE2 0x2632
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE2 0x2633
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE2 0x2634
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE2 0x2635
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE2 0x2636
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE2 0x2637
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE2 0x2638
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE2 0x2639
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE2 0x263a
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE2 0x263b
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE2 0x263c
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE2 0x263d
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3 0x263e
++#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3 0x263f
++#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2640
++#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE3 0x2641
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE3 0x2642
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE3 0x2643
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE3 0x2644
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE3 0x2645
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE3 0x2646
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE3 0x2647
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE3 0x2648
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE3 0x2649
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE3 0x264a
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE3 0x264b
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE3 0x264c
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE3 0x264d
++#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE3_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dc_combophypllregs6_dispdec
++// base address: 0x12c0
++#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL0 0x264e
++#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL0_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL1 0x264f
++#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL1_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL2 0x2650
++#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL2_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL3 0x2651
++#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL3_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS6_BW_CTRL_COARSE 0x2652
++#define mmDC_COMBOPHYPLLREGS6_BW_CTRL_COARSE_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS6_BW_CTRL_FINE 0x2653
++#define mmDC_COMBOPHYPLLREGS6_BW_CTRL_FINE_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS6_CAL_CTRL 0x2654
++#define mmDC_COMBOPHYPLLREGS6_CAL_CTRL_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS6_LOOP_CTRL 0x2655
++#define mmDC_COMBOPHYPLLREGS6_LOOP_CTRL_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS6_VREG_CFG 0x2657
++#define mmDC_COMBOPHYPLLREGS6_VREG_CFG_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS6_OBSERVE0 0x2658
++#define mmDC_COMBOPHYPLLREGS6_OBSERVE0_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS6_OBSERVE1 0x2659
++#define mmDC_COMBOPHYPLLREGS6_OBSERVE1_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS6_DFT_OUT 0x265a
++#define mmDC_COMBOPHYPLLREGS6_DFT_OUT_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dcio_uniphy8_dispdec
++// base address: 0x15e0
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0 0x26b6
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1 0x26b7
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2 0x26b8
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3 0x26b9
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4 0x26ba
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5 0x26bb
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6 0x26bc
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7 0x26bd
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8 0x26be
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9 0x26bf
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10 0x26c0
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11 0x26c1
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12 0x26c2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13 0x26c3
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14 0x26c4
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15 0x26c5
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16 0x26c6
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17 0x26c7
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18 0x26c8
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19 0x26c9
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20 0x26ca
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21 0x26cb
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22 0x26cc
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23 0x26cd
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24 0x26ce
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25 0x26cf
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26 0x26d0
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27 0x26d1
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28 0x26d2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29 0x26d3
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30 0x26d4
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31 0x26d5
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED32 0x26d6
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED33 0x26d7
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED34 0x26d8
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED35 0x26d9
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED36 0x26da
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED37 0x26db
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED38 0x26dc
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED39 0x26dd
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED40 0x26de
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED41 0x26df
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED42 0x26e0
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED43 0x26e1
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED44 0x26e2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED45 0x26e3
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED46 0x26e4
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED47 0x26e5
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED48 0x26e6
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED49 0x26e7
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED50 0x26e8
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED51 0x26e9
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED52 0x26ea
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED53 0x26eb
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED54 0x26ec
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED55 0x26ed
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED56 0x26ee
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED57 0x26ef
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED58 0x26f0
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED59 0x26f1
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED60 0x26f2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED61 0x26f3
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED62 0x26f4
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED63 0x26f5
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED64 0x26f6
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED65 0x26f7
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED66 0x26f8
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED67 0x26f9
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED68 0x26fa
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED69 0x26fb
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED70 0x26fc
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED71 0x26fd
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED72 0x26fe
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED73 0x26ff
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED74 0x2700
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED75 0x2701
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED76 0x2702
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED77 0x2703
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED78 0x2704
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED79 0x2705
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED80 0x2706
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED81 0x2707
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED82 0x2708
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED83 0x2709
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED84 0x270a
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED85 0x270b
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED86 0x270c
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED87 0x270d
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED88 0x270e
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED89 0x270f
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED90 0x2710
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED91 0x2711
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED92 0x2712
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED93 0x2713
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED94 0x2714
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED95 0x2715
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED96 0x2716
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED97 0x2717
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED98 0x2718
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED99 0x2719
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED100 0x271a
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED101 0x271b
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED102 0x271c
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED103 0x271d
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED104 0x271e
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED105 0x271f
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED106 0x2720
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED107 0x2721
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED108 0x2722
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED109 0x2723
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED110 0x2724
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED111 0x2725
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED112 0x2726
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED113 0x2727
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED114 0x2728
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED115 0x2729
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED116 0x272a
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED117 0x272b
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED118 0x272c
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED119 0x272d
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED120 0x272e
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED121 0x272f
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED122 0x2730
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED123 0x2731
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED124 0x2732
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED125 0x2733
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED126 0x2734
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED127 0x2735
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED128 0x2736
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED129 0x2737
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED130 0x2738
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED131 0x2739
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED132 0x273a
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED133 0x273b
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED134 0x273c
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED135 0x273d
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED136 0x273e
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED137 0x273f
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED138 0x2740
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED139 0x2741
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED140 0x2742
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED141 0x2743
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED142 0x2744
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED143 0x2745
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED144 0x2746
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED145 0x2747
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED146 0x2748
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED147 0x2749
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED148 0x274a
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED149 0x274b
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED150 0x274c
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED151 0x274d
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED152 0x274e
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED153 0x274f
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED154 0x2750
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED155 0x2751
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED156 0x2752
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED157 0x2753
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED158 0x2754
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED159 0x2755
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dc_combophycmregs8_dispdec
++// base address: 0x15e0
++#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE1 0x26b6
++#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE1_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE2 0x26b7
++#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE2_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE3 0x26b8
++#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE3_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM 0x26b9
++#define mmDC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT 0x26ba
++#define mmDC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS8_COMMON_TXCNTRL 0x26bb
++#define mmDC_COMBOPHYCMREGS8_COMMON_TXCNTRL_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS8_COMMON_TMDP 0x26bc
++#define mmDC_COMBOPHYCMREGS8_COMMON_TMDP_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS8_COMMON_LANE_RESETS 0x26bd
++#define mmDC_COMBOPHYCMREGS8_COMMON_LANE_RESETS_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL 0x26be
++#define mmDC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU1 0x26bf
++#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU1_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU2 0x26c0
++#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU2_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU3 0x26c1
++#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU3_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU4 0x26c2
++#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU4_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU5 0x26c3
++#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU5_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU6 0x26c4
++#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU6_BASE_IDX 2
++#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU7 0x26c5
++#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU7_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dc_combophytxregs8_dispdec
++// base address: 0x15e0
++#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0 0x26d6
++#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0 0x26d7
++#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x26d8
++#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE0 0x26d9
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE0 0x26da
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE0 0x26db
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE0 0x26dc
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE0 0x26dd
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE0 0x26de
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE0 0x26df
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE0 0x26e0
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE0 0x26e1
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE0 0x26e2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE0 0x26e3
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE0 0x26e4
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE0 0x26e5
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE0_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1 0x26e6
++#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1 0x26e7
++#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x26e8
++#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE1 0x26e9
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE1 0x26ea
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE1 0x26eb
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE1 0x26ec
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE1 0x26ed
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE1 0x26ee
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE1 0x26ef
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE1 0x26f0
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE1 0x26f1
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE1 0x26f2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE1 0x26f3
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE1 0x26f4
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE1 0x26f5
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE1_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2 0x26f6
++#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2 0x26f7
++#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x26f8
++#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE2 0x26f9
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE2 0x26fa
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE2 0x26fb
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE2 0x26fc
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE2 0x26fd
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE2 0x26fe
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE2 0x26ff
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE2 0x2700
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE2 0x2701
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE2 0x2702
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE2 0x2703
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE2 0x2704
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE2 0x2705
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE2_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3 0x2706
++#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3 0x2707
++#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2708
++#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE3 0x2709
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE3 0x270a
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE3 0x270b
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE3 0x270c
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE3 0x270d
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE3 0x270e
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE3 0x270f
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE3 0x2710
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE3 0x2711
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE3 0x2712
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE3 0x2713
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE3 0x2714
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE3_BASE_IDX 2
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE3 0x2715
++#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE3_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dc_combophypllregs8_dispdec
++// base address: 0x15e0
++#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL0 0x2716
++#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL0_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL1 0x2717
++#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL1_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL2 0x2718
++#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL2_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL3 0x2719
++#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL3_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS8_BW_CTRL_COARSE 0x271a
++#define mmDC_COMBOPHYPLLREGS8_BW_CTRL_COARSE_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS8_BW_CTRL_FINE 0x271b
++#define mmDC_COMBOPHYPLLREGS8_BW_CTRL_FINE_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS8_CAL_CTRL 0x271c
++#define mmDC_COMBOPHYPLLREGS8_CAL_CTRL_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS8_LOOP_CTRL 0x271d
++#define mmDC_COMBOPHYPLLREGS8_LOOP_CTRL_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS8_VREG_CFG 0x271f
++#define mmDC_COMBOPHYPLLREGS8_VREG_CFG_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS8_OBSERVE0 0x2720
++#define mmDC_COMBOPHYPLLREGS8_OBSERVE0_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS8_OBSERVE1 0x2721
++#define mmDC_COMBOPHYPLLREGS8_OBSERVE1_BASE_IDX 2
++#define mmDC_COMBOPHYPLLREGS8_DFT_OUT 0x2722
++#define mmDC_COMBOPHYPLLREGS8_DFT_OUT_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dsi0_dispdec
++// base address: 0x0
++#define mmDSI0_DISP_DSI_CTRL 0x27be
++#define mmDSI0_DISP_DSI_CTRL_BASE_IDX 2
++#define mmDSI0_DISP_DSI_STATUS 0x27bf
++#define mmDSI0_DISP_DSI_STATUS_BASE_IDX 2
++#define mmDSI0_DISP_DSI_VIDEO_MODE_CTRL 0x27c0
++#define mmDSI0_DISP_DSI_VIDEO_MODE_CTRL_BASE_IDX 2
++#define mmDSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE 0x27c1
++#define mmDSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE_BASE_IDX 2
++#define mmDSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD 0x27c2
++#define mmDSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD_BASE_IDX 2
++#define mmDSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD 0x27c3
++#define mmDSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD_BASE_IDX 2
++#define mmDSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE 0x27c4
++#define mmDSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE_BASE_IDX 2
++#define mmDSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE 0x27c5
++#define mmDSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE_BASE_IDX 2
++#define mmDSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL 0x27c6
++#define mmDSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL_BASE_IDX 2
++#define mmDSI0_DISP_DSI_COMMAND_MODE_CTRL 0x27c7
++#define mmDSI0_DISP_DSI_COMMAND_MODE_CTRL_BASE_IDX 2
++#define mmDSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL 0x27c8
++#define mmDSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL_BASE_IDX 2
++#define mmDSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL 0x27c9
++#define mmDSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL_BASE_IDX 2
++#define mmDSI0_DISP_DSI_DMA_CMD_OFFSET 0x27ca
++#define mmDSI0_DISP_DSI_DMA_CMD_OFFSET_BASE_IDX 2
++#define mmDSI0_DISP_DSI_DMA_CMD_LENGTH 0x27cb
++#define mmDSI0_DISP_DSI_DMA_CMD_LENGTH_BASE_IDX 2
++#define mmDSI0_DISP_DSI_DMA_DATA_OFFSET_0 0x27cc
++#define mmDSI0_DISP_DSI_DMA_DATA_OFFSET_0_BASE_IDX 2
++#define mmDSI0_DISP_DSI_DMA_DATA_OFFSET_1 0x27cd
++#define mmDSI0_DISP_DSI_DMA_DATA_OFFSET_1_BASE_IDX 2
++#define mmDSI0_DISP_DSI_DMA_DATA_PITCH 0x27ce
++#define mmDSI0_DISP_DSI_DMA_DATA_PITCH_BASE_IDX 2
++#define mmDSI0_DISP_DSI_DMA_DATA_WIDTH 0x27cf
++#define mmDSI0_DISP_DSI_DMA_DATA_WIDTH_BASE_IDX 2
++#define mmDSI0_DISP_DSI_DMA_DATA_HEIGHT 0x27d0
++#define mmDSI0_DISP_DSI_DMA_DATA_HEIGHT_BASE_IDX 2
++#define mmDSI0_DISP_DSI_DMA_FIFO_CTRL 0x27d1
++#define mmDSI0_DISP_DSI_DMA_FIFO_CTRL_BASE_IDX 2
++#define mmDSI0_DISP_DSI_DMA_NULL_PACKET_DATA 0x27d2
++#define mmDSI0_DISP_DSI_DMA_NULL_PACKET_DATA_BASE_IDX 2
++#define mmDSI0_DISP_DSI_DENG_DATA_LENGTH 0x27d3
++#define mmDSI0_DISP_DSI_DENG_DATA_LENGTH_BASE_IDX 2
++#define mmDSI0_DISP_DSI_ACK_ERROR_REPORT 0x27d4
++#define mmDSI0_DISP_DSI_ACK_ERROR_REPORT_BASE_IDX 2
++#define mmDSI0_DISP_DSI_RDBK_DATA0 0x27d5
++#define mmDSI0_DISP_DSI_RDBK_DATA0_BASE_IDX 2
++#define mmDSI0_DISP_DSI_RDBK_DATA1 0x27d6
++#define mmDSI0_DISP_DSI_RDBK_DATA1_BASE_IDX 2
++#define mmDSI0_DISP_DSI_RDBK_DATA2 0x27d7
++#define mmDSI0_DISP_DSI_RDBK_DATA2_BASE_IDX 2
++#define mmDSI0_DISP_DSI_RDBK_DATA3 0x27d8
++#define mmDSI0_DISP_DSI_RDBK_DATA3_BASE_IDX 2
++#define mmDSI0_DISP_DSI_RDBK_DATATYPE0 0x27d9
++#define mmDSI0_DISP_DSI_RDBK_DATATYPE0_BASE_IDX 2
++#define mmDSI0_DISP_DSI_RDBK_DATATYPE1 0x27da
++#define mmDSI0_DISP_DSI_RDBK_DATATYPE1_BASE_IDX 2
++#define mmDSI0_DISP_DSI_TRIG_CTRL 0x27db
++#define mmDSI0_DISP_DSI_TRIG_CTRL_BASE_IDX 2
++#define mmDSI0_DISP_DSI_EXT_MUX 0x27dc
++#define mmDSI0_DISP_DSI_EXT_MUX_BASE_IDX 2
++#define mmDSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL 0x27dd
++#define mmDSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL_BASE_IDX 2
++#define mmDSI0_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER 0x27de
++#define mmDSI0_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER_BASE_IDX 2
++#define mmDSI0_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER 0x27df
++#define mmDSI0_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER_BASE_IDX 2
++#define mmDSI0_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER 0x27e0
++#define mmDSI0_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER_BASE_IDX 2
++#define mmDSI0_DISP_DSI_RESET_SW_TRIGGER 0x27e1
++#define mmDSI0_DISP_DSI_RESET_SW_TRIGGER_BASE_IDX 2
++#define mmDSI0_DISP_DSI_EXT_RESET 0x27e2
++#define mmDSI0_DISP_DSI_EXT_RESET_BASE_IDX 2
++#define mmDSI0_DISP_DSI_LANE_CRC_HS_MODE 0x27e3
++#define mmDSI0_DISP_DSI_LANE_CRC_HS_MODE_BASE_IDX 2
++#define mmDSI0_DISP_DSI_LANE_CRC_LP_MODE 0x27e4
++#define mmDSI0_DISP_DSI_LANE_CRC_LP_MODE_BASE_IDX 2
++#define mmDSI0_DISP_DSI_LANE_CRC_CTRL 0x27e5
++#define mmDSI0_DISP_DSI_LANE_CRC_CTRL_BASE_IDX 2
++#define mmDSI0_DISP_DSI_PIXEL_CRC_CTRL 0x27e6
++#define mmDSI0_DISP_DSI_PIXEL_CRC_CTRL_BASE_IDX 2
++#define mmDSI0_DISP_DSI_LANE_CTRL 0x27e7
++#define mmDSI0_DISP_DSI_LANE_CTRL_BASE_IDX 2
++#define mmDSI0_DISP_DSI_DLN0_PHY_ERROR 0x27e8
++#define mmDSI0_DISP_DSI_DLN0_PHY_ERROR_BASE_IDX 2
++#define mmDSI0_DISP_DSI_LP_TIMER_CTRL 0x27e9
++#define mmDSI0_DISP_DSI_LP_TIMER_CTRL_BASE_IDX 2
++#define mmDSI0_DISP_DSI_HS_TIMER_CTRL 0x27ea
++#define mmDSI0_DISP_DSI_HS_TIMER_CTRL_BASE_IDX 2
++#define mmDSI0_DISP_DSI_TIMEOUT_STATUS 0x27eb
++#define mmDSI0_DISP_DSI_TIMEOUT_STATUS_BASE_IDX 2
++#define mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL 0x27ec
++#define mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL_BASE_IDX 2
++#define mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2 0x27ed
++#define mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2_BASE_IDX 2
++#define mmDSI0_DISP_DSI_EOT_PACKET 0x27ee
++#define mmDSI0_DISP_DSI_EOT_PACKET_BASE_IDX 2
++#define mmDSI0_DISP_DSI_EOT_PACKET_CTRL 0x27ef
++#define mmDSI0_DISP_DSI_EOT_PACKET_CTRL_BASE_IDX 2
++#define mmDSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER 0x27f0
++#define mmDSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER_BASE_IDX 2
++#define mmDSI0_DISP_DSI_MIPI_BIST_CTRL 0x27f1
++#define mmDSI0_DISP_DSI_MIPI_BIST_CTRL_BASE_IDX 2
++#define mmDSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE 0x27f2
++#define mmDSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE_BASE_IDX 2
++#define mmDSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE 0x27f3
++#define mmDSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE_BASE_IDX 2
++#define mmDSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG 0x27f4
++#define mmDSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG_BASE_IDX 2
++#define mmDSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL 0x27f5
++#define mmDSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL_BASE_IDX 2
++#define mmDSI0_DISP_DSI_MIPI_BIST_LSFR_INIT 0x27f6
++#define mmDSI0_DISP_DSI_MIPI_BIST_LSFR_INIT_BASE_IDX 2
++#define mmDSI0_DISP_DSI_MIPI_BIST_START 0x27f7
++#define mmDSI0_DISP_DSI_MIPI_BIST_START_BASE_IDX 2
++#define mmDSI0_DISP_DSI_MIPI_BIST_STATUS 0x27f8
++#define mmDSI0_DISP_DSI_MIPI_BIST_STATUS_BASE_IDX 2
++#define mmDSI0_DISP_DSI_ERROR_INTERRUPT_MASK 0x27f9
++#define mmDSI0_DISP_DSI_ERROR_INTERRUPT_MASK_BASE_IDX 2
++#define mmDSI0_DISP_DSI_INTERRUPT_CTRL 0x27fa
++#define mmDSI0_DISP_DSI_INTERRUPT_CTRL_BASE_IDX 2
++#define mmDSI0_DISP_DSI_CLK_CTRL 0x27fb
++#define mmDSI0_DISP_DSI_CLK_CTRL_BASE_IDX 2
++#define mmDSI0_DISP_DSI_CLK_STATUS 0x27fc
++#define mmDSI0_DISP_DSI_CLK_STATUS_BASE_IDX 2
++#define mmDSI0_DISP_DSI_DENG_FIFO_STATUS 0x27fd
++#define mmDSI0_DISP_DSI_DENG_FIFO_STATUS_BASE_IDX 2
++#define mmDSI0_DISP_DSI_DENG_FIFO_CTRL 0x27fe
++#define mmDSI0_DISP_DSI_DENG_FIFO_CTRL_BASE_IDX 2
++#define mmDSI0_DISP_DSI_CMD_FIFO_DATA 0x27ff
++#define mmDSI0_DISP_DSI_CMD_FIFO_DATA_BASE_IDX 2
++#define mmDSI0_DISP_DSI_CMD_FIFO_CTRL 0x2800
++#define mmDSI0_DISP_DSI_CMD_FIFO_CTRL_BASE_IDX 2
++#define mmDSI0_DISP_DSI_TE_CTRL 0x2801
++#define mmDSI0_DISP_DSI_TE_CTRL_BASE_IDX 2
++#define mmDSI0_DISP_DSI_LANE_STATUS 0x2805
++#define mmDSI0_DISP_DSI_LANE_STATUS_BASE_IDX 2
++#define mmDSI0_DISP_DSI_PERF_CTRL 0x2806
++#define mmDSI0_DISP_DSI_PERF_CTRL_BASE_IDX 2
++#define mmDSI0_DISP_DSI_HSYNC_LENGTH 0x2807
++#define mmDSI0_DISP_DSI_HSYNC_LENGTH_BASE_IDX 2
++#define mmDSI0_DISP_DSI_RDBK_NUM 0x2808
++#define mmDSI0_DISP_DSI_RDBK_NUM_BASE_IDX 2
++#define mmDSI0_DISP_DSI_CMD_MEM_PWR_CTRL 0x2809
++#define mmDSI0_DISP_DSI_CMD_MEM_PWR_CTRL_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dsi1_dispdec
++// base address: 0x400
++#define mmDSI1_DISP_DSI_CTRL 0x28be
++#define mmDSI1_DISP_DSI_CTRL_BASE_IDX 2
++#define mmDSI1_DISP_DSI_STATUS 0x28bf
++#define mmDSI1_DISP_DSI_STATUS_BASE_IDX 2
++#define mmDSI1_DISP_DSI_VIDEO_MODE_CTRL 0x28c0
++#define mmDSI1_DISP_DSI_VIDEO_MODE_CTRL_BASE_IDX 2
++#define mmDSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE 0x28c1
++#define mmDSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE_BASE_IDX 2
++#define mmDSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD 0x28c2
++#define mmDSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD_BASE_IDX 2
++#define mmDSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD 0x28c3
++#define mmDSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD_BASE_IDX 2
++#define mmDSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE 0x28c4
++#define mmDSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE_BASE_IDX 2
++#define mmDSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE 0x28c5
++#define mmDSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE_BASE_IDX 2
++#define mmDSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL 0x28c6
++#define mmDSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL_BASE_IDX 2
++#define mmDSI1_DISP_DSI_COMMAND_MODE_CTRL 0x28c7
++#define mmDSI1_DISP_DSI_COMMAND_MODE_CTRL_BASE_IDX 2
++#define mmDSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL 0x28c8
++#define mmDSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL_BASE_IDX 2
++#define mmDSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL 0x28c9
++#define mmDSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL_BASE_IDX 2
++#define mmDSI1_DISP_DSI_DMA_CMD_OFFSET 0x28ca
++#define mmDSI1_DISP_DSI_DMA_CMD_OFFSET_BASE_IDX 2
++#define mmDSI1_DISP_DSI_DMA_CMD_LENGTH 0x28cb
++#define mmDSI1_DISP_DSI_DMA_CMD_LENGTH_BASE_IDX 2
++#define mmDSI1_DISP_DSI_DMA_DATA_OFFSET_0 0x28cc
++#define mmDSI1_DISP_DSI_DMA_DATA_OFFSET_0_BASE_IDX 2
++#define mmDSI1_DISP_DSI_DMA_DATA_OFFSET_1 0x28cd
++#define mmDSI1_DISP_DSI_DMA_DATA_OFFSET_1_BASE_IDX 2
++#define mmDSI1_DISP_DSI_DMA_DATA_PITCH 0x28ce
++#define mmDSI1_DISP_DSI_DMA_DATA_PITCH_BASE_IDX 2
++#define mmDSI1_DISP_DSI_DMA_DATA_WIDTH 0x28cf
++#define mmDSI1_DISP_DSI_DMA_DATA_WIDTH_BASE_IDX 2
++#define mmDSI1_DISP_DSI_DMA_DATA_HEIGHT 0x28d0
++#define mmDSI1_DISP_DSI_DMA_DATA_HEIGHT_BASE_IDX 2
++#define mmDSI1_DISP_DSI_DMA_FIFO_CTRL 0x28d1
++#define mmDSI1_DISP_DSI_DMA_FIFO_CTRL_BASE_IDX 2
++#define mmDSI1_DISP_DSI_DMA_NULL_PACKET_DATA 0x28d2
++#define mmDSI1_DISP_DSI_DMA_NULL_PACKET_DATA_BASE_IDX 2
++#define mmDSI1_DISP_DSI_DENG_DATA_LENGTH 0x28d3
++#define mmDSI1_DISP_DSI_DENG_DATA_LENGTH_BASE_IDX 2
++#define mmDSI1_DISP_DSI_ACK_ERROR_REPORT 0x28d4
++#define mmDSI1_DISP_DSI_ACK_ERROR_REPORT_BASE_IDX 2
++#define mmDSI1_DISP_DSI_RDBK_DATA0 0x28d5
++#define mmDSI1_DISP_DSI_RDBK_DATA0_BASE_IDX 2
++#define mmDSI1_DISP_DSI_RDBK_DATA1 0x28d6
++#define mmDSI1_DISP_DSI_RDBK_DATA1_BASE_IDX 2
++#define mmDSI1_DISP_DSI_RDBK_DATA2 0x28d7
++#define mmDSI1_DISP_DSI_RDBK_DATA2_BASE_IDX 2
++#define mmDSI1_DISP_DSI_RDBK_DATA3 0x28d8
++#define mmDSI1_DISP_DSI_RDBK_DATA3_BASE_IDX 2
++#define mmDSI1_DISP_DSI_RDBK_DATATYPE0 0x28d9
++#define mmDSI1_DISP_DSI_RDBK_DATATYPE0_BASE_IDX 2
++#define mmDSI1_DISP_DSI_RDBK_DATATYPE1 0x28da
++#define mmDSI1_DISP_DSI_RDBK_DATATYPE1_BASE_IDX 2
++#define mmDSI1_DISP_DSI_TRIG_CTRL 0x28db
++#define mmDSI1_DISP_DSI_TRIG_CTRL_BASE_IDX 2
++#define mmDSI1_DISP_DSI_EXT_MUX 0x28dc
++#define mmDSI1_DISP_DSI_EXT_MUX_BASE_IDX 2
++#define mmDSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL 0x28dd
++#define mmDSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL_BASE_IDX 2
++#define mmDSI1_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER 0x28de
++#define mmDSI1_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER_BASE_IDX 2
++#define mmDSI1_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER 0x28df
++#define mmDSI1_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER_BASE_IDX 2
++#define mmDSI1_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER 0x28e0
++#define mmDSI1_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER_BASE_IDX 2
++#define mmDSI1_DISP_DSI_RESET_SW_TRIGGER 0x28e1
++#define mmDSI1_DISP_DSI_RESET_SW_TRIGGER_BASE_IDX 2
++#define mmDSI1_DISP_DSI_EXT_RESET 0x28e2
++#define mmDSI1_DISP_DSI_EXT_RESET_BASE_IDX 2
++#define mmDSI1_DISP_DSI_LANE_CRC_HS_MODE 0x28e3
++#define mmDSI1_DISP_DSI_LANE_CRC_HS_MODE_BASE_IDX 2
++#define mmDSI1_DISP_DSI_LANE_CRC_LP_MODE 0x28e4
++#define mmDSI1_DISP_DSI_LANE_CRC_LP_MODE_BASE_IDX 2
++#define mmDSI1_DISP_DSI_LANE_CRC_CTRL 0x28e5
++#define mmDSI1_DISP_DSI_LANE_CRC_CTRL_BASE_IDX 2
++#define mmDSI1_DISP_DSI_PIXEL_CRC_CTRL 0x28e6
++#define mmDSI1_DISP_DSI_PIXEL_CRC_CTRL_BASE_IDX 2
++#define mmDSI1_DISP_DSI_LANE_CTRL 0x28e7
++#define mmDSI1_DISP_DSI_LANE_CTRL_BASE_IDX 2
++#define mmDSI1_DISP_DSI_DLN0_PHY_ERROR 0x28e8
++#define mmDSI1_DISP_DSI_DLN0_PHY_ERROR_BASE_IDX 2
++#define mmDSI1_DISP_DSI_LP_TIMER_CTRL 0x28e9
++#define mmDSI1_DISP_DSI_LP_TIMER_CTRL_BASE_IDX 2
++#define mmDSI1_DISP_DSI_HS_TIMER_CTRL 0x28ea
++#define mmDSI1_DISP_DSI_HS_TIMER_CTRL_BASE_IDX 2
++#define mmDSI1_DISP_DSI_TIMEOUT_STATUS 0x28eb
++#define mmDSI1_DISP_DSI_TIMEOUT_STATUS_BASE_IDX 2
++#define mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL 0x28ec
++#define mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL_BASE_IDX 2
++#define mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2 0x28ed
++#define mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2_BASE_IDX 2
++#define mmDSI1_DISP_DSI_EOT_PACKET 0x28ee
++#define mmDSI1_DISP_DSI_EOT_PACKET_BASE_IDX 2
++#define mmDSI1_DISP_DSI_EOT_PACKET_CTRL 0x28ef
++#define mmDSI1_DISP_DSI_EOT_PACKET_CTRL_BASE_IDX 2
++#define mmDSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER 0x28f0
++#define mmDSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER_BASE_IDX 2
++#define mmDSI1_DISP_DSI_MIPI_BIST_CTRL 0x28f1
++#define mmDSI1_DISP_DSI_MIPI_BIST_CTRL_BASE_IDX 2
++#define mmDSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE 0x28f2
++#define mmDSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE_BASE_IDX 2
++#define mmDSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE 0x28f3
++#define mmDSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE_BASE_IDX 2
++#define mmDSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG 0x28f4
++#define mmDSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG_BASE_IDX 2
++#define mmDSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL 0x28f5
++#define mmDSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL_BASE_IDX 2
++#define mmDSI1_DISP_DSI_MIPI_BIST_LSFR_INIT 0x28f6
++#define mmDSI1_DISP_DSI_MIPI_BIST_LSFR_INIT_BASE_IDX 2
++#define mmDSI1_DISP_DSI_MIPI_BIST_START 0x28f7
++#define mmDSI1_DISP_DSI_MIPI_BIST_START_BASE_IDX 2
++#define mmDSI1_DISP_DSI_MIPI_BIST_STATUS 0x28f8
++#define mmDSI1_DISP_DSI_MIPI_BIST_STATUS_BASE_IDX 2
++#define mmDSI1_DISP_DSI_ERROR_INTERRUPT_MASK 0x28f9
++#define mmDSI1_DISP_DSI_ERROR_INTERRUPT_MASK_BASE_IDX 2
++#define mmDSI1_DISP_DSI_INTERRUPT_CTRL 0x28fa
++#define mmDSI1_DISP_DSI_INTERRUPT_CTRL_BASE_IDX 2
++#define mmDSI1_DISP_DSI_CLK_CTRL 0x28fb
++#define mmDSI1_DISP_DSI_CLK_CTRL_BASE_IDX 2
++#define mmDSI1_DISP_DSI_CLK_STATUS 0x28fc
++#define mmDSI1_DISP_DSI_CLK_STATUS_BASE_IDX 2
++#define mmDSI1_DISP_DSI_DENG_FIFO_STATUS 0x28fd
++#define mmDSI1_DISP_DSI_DENG_FIFO_STATUS_BASE_IDX 2
++#define mmDSI1_DISP_DSI_DENG_FIFO_CTRL 0x28fe
++#define mmDSI1_DISP_DSI_DENG_FIFO_CTRL_BASE_IDX 2
++#define mmDSI1_DISP_DSI_CMD_FIFO_DATA 0x28ff
++#define mmDSI1_DISP_DSI_CMD_FIFO_DATA_BASE_IDX 2
++#define mmDSI1_DISP_DSI_CMD_FIFO_CTRL 0x2900
++#define mmDSI1_DISP_DSI_CMD_FIFO_CTRL_BASE_IDX 2
++#define mmDSI1_DISP_DSI_TE_CTRL 0x2901
++#define mmDSI1_DISP_DSI_TE_CTRL_BASE_IDX 2
++#define mmDSI1_DISP_DSI_LANE_STATUS 0x2905
++#define mmDSI1_DISP_DSI_LANE_STATUS_BASE_IDX 2
++#define mmDSI1_DISP_DSI_PERF_CTRL 0x2906
++#define mmDSI1_DISP_DSI_PERF_CTRL_BASE_IDX 2
++#define mmDSI1_DISP_DSI_HSYNC_LENGTH 0x2907
++#define mmDSI1_DISP_DSI_HSYNC_LENGTH_BASE_IDX 2
++#define mmDSI1_DISP_DSI_RDBK_NUM 0x2908
++#define mmDSI1_DISP_DSI_RDBK_NUM_BASE_IDX 2
++#define mmDSI1_DISP_DSI_CMD_MEM_PWR_CTRL 0x2909
++#define mmDSI1_DISP_DSI_CMD_MEM_PWR_CTRL_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dprx_sd0_dispdec
++// base address: 0x0
++#define mmDPRX_SD0_DPRX_SD_CONTROL 0x29be
++#define mmDPRX_SD0_DPRX_SD_CONTROL_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_STREAM_ENABLE 0x29bf
++#define mmDPRX_SD0_DPRX_SD_STREAM_ENABLE_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_MSA0 0x29c0
++#define mmDPRX_SD0_DPRX_SD_MSA0_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_MSA1 0x29c1
++#define mmDPRX_SD0_DPRX_SD_MSA1_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_MSA2 0x29c2
++#define mmDPRX_SD0_DPRX_SD_MSA2_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_MSA3 0x29c3
++#define mmDPRX_SD0_DPRX_SD_MSA3_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_MSA4 0x29c4
++#define mmDPRX_SD0_DPRX_SD_MSA4_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_MSA5 0x29c5
++#define mmDPRX_SD0_DPRX_SD_MSA5_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_MSA6 0x29c6
++#define mmDPRX_SD0_DPRX_SD_MSA6_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_MSA7 0x29c7
++#define mmDPRX_SD0_DPRX_SD_MSA7_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_MSA8 0x29c8
++#define mmDPRX_SD0_DPRX_SD_MSA8_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_VBID 0x29c9
++#define mmDPRX_SD0_DPRX_SD_VBID_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_CURRENT_LINE 0x29ca
++#define mmDPRX_SD0_DPRX_SD_CURRENT_LINE_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_SNAPSHOT 0x29cb
++#define mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_SNAPSHOT_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE 0x29cc
++#define mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_MSE_SAT 0x29ce
++#define mmDPRX_SD0_DPRX_SD_MSE_SAT_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_MSE_FORCE_UPDATE 0x29cf
++#define mmDPRX_SD0_DPRX_SD_MSE_FORCE_UPDATE_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE 0x29d0
++#define mmDPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_V_PARAMETER 0x29d1
++#define mmDPRX_SD0_DPRX_SD_V_PARAMETER_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_PIXEL_FORMAT 0x29d2
++#define mmDPRX_SD0_DPRX_SD_PIXEL_FORMAT_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS 0x29d3
++#define mmDPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED 0x29d4
++#define mmDPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS 0x29d5
++#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_CONTROL 0x29d6
++#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_CONTROL_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS 0x29d7
++#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_CONTROL 0x29d8
++#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_CONTROL_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR 0x29d9
++#define mmDPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE 0x29da
++#define mmDPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR 0x29db
++#define mmDPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_VCPF_PHASE_LOCKED 0x29dc
++#define mmDPRX_SD0_DPRX_SD_VCPF_PHASE_LOCKED_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR 0x29dd
++#define mmDPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR 0x29de
++#define mmDPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_PIXEL_FIFO_ERROR 0x29df
++#define mmDPRX_SD0_DPRX_SD_PIXEL_FIFO_ERROR_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH 0x29e1
++#define mmDPRX_SD0_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_SDP_STEER 0x29e3
++#define mmDPRX_SD0_DPRX_SD_SDP_STEER_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS 0x29e4
++#define mmDPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_SDP_LEVEL 0x29e5
++#define mmDPRX_SD0_DPRX_SD_SDP_LEVEL_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_SDP_DATA 0x29e6
++#define mmDPRX_SD0_DPRX_SD_SDP_DATA_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_SDP_ERROR 0x29e7
++#define mmDPRX_SD0_DPRX_SD_SDP_ERROR_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_AUDIO_HEADER 0x29e8
++#define mmDPRX_SD0_DPRX_SD_AUDIO_HEADER_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_AUDIO_FIFO_ERROR 0x29e9
++#define mmDPRX_SD0_DPRX_SD_AUDIO_FIFO_ERROR_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_SDP_CONTROL 0x29ea
++#define mmDPRX_SD0_DPRX_SD_SDP_CONTROL_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_V_TOTAL_MEASURED 0x29eb
++#define mmDPRX_SD0_DPRX_SD_V_TOTAL_MEASURED_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_H_TOTAL_MEASURED 0x29ec
++#define mmDPRX_SD0_DPRX_SD_H_TOTAL_MEASURED_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_BS_COUNTER 0x29ed
++#define mmDPRX_SD0_DPRX_SD_BS_COUNTER_BASE_IDX 2
++#define mmDPRX_SD0_DPRX_SD_MSE_ACT_HANDLED 0x29ee
++#define mmDPRX_SD0_DPRX_SD_MSE_ACT_HANDLED_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dprx_sd1_dispdec
++// base address: 0x180
++#define mmDPRX_SD1_DPRX_SD_CONTROL 0x2a1e
++#define mmDPRX_SD1_DPRX_SD_CONTROL_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_STREAM_ENABLE 0x2a1f
++#define mmDPRX_SD1_DPRX_SD_STREAM_ENABLE_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_MSA0 0x2a20
++#define mmDPRX_SD1_DPRX_SD_MSA0_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_MSA1 0x2a21
++#define mmDPRX_SD1_DPRX_SD_MSA1_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_MSA2 0x2a22
++#define mmDPRX_SD1_DPRX_SD_MSA2_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_MSA3 0x2a23
++#define mmDPRX_SD1_DPRX_SD_MSA3_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_MSA4 0x2a24
++#define mmDPRX_SD1_DPRX_SD_MSA4_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_MSA5 0x2a25
++#define mmDPRX_SD1_DPRX_SD_MSA5_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_MSA6 0x2a26
++#define mmDPRX_SD1_DPRX_SD_MSA6_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_MSA7 0x2a27
++#define mmDPRX_SD1_DPRX_SD_MSA7_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_MSA8 0x2a28
++#define mmDPRX_SD1_DPRX_SD_MSA8_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_VBID 0x2a29
++#define mmDPRX_SD1_DPRX_SD_VBID_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_CURRENT_LINE 0x2a2a
++#define mmDPRX_SD1_DPRX_SD_CURRENT_LINE_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_SNAPSHOT 0x2a2b
++#define mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_SNAPSHOT_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE 0x2a2c
++#define mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_MSE_SAT 0x2a2e
++#define mmDPRX_SD1_DPRX_SD_MSE_SAT_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_MSE_FORCE_UPDATE 0x2a2f
++#define mmDPRX_SD1_DPRX_SD_MSE_FORCE_UPDATE_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE 0x2a30
++#define mmDPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_V_PARAMETER 0x2a31
++#define mmDPRX_SD1_DPRX_SD_V_PARAMETER_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_PIXEL_FORMAT 0x2a32
++#define mmDPRX_SD1_DPRX_SD_PIXEL_FORMAT_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS 0x2a33
++#define mmDPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED 0x2a34
++#define mmDPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS 0x2a35
++#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_CONTROL 0x2a36
++#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_CONTROL_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS 0x2a37
++#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_CONTROL 0x2a38
++#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_CONTROL_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR 0x2a39
++#define mmDPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE 0x2a3a
++#define mmDPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR 0x2a3b
++#define mmDPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_VCPF_PHASE_LOCKED 0x2a3c
++#define mmDPRX_SD1_DPRX_SD_VCPF_PHASE_LOCKED_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR 0x2a3d
++#define mmDPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR 0x2a3e
++#define mmDPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_PIXEL_FIFO_ERROR 0x2a3f
++#define mmDPRX_SD1_DPRX_SD_PIXEL_FIFO_ERROR_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH 0x2a41
++#define mmDPRX_SD1_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_SDP_STEER 0x2a43
++#define mmDPRX_SD1_DPRX_SD_SDP_STEER_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS 0x2a44
++#define mmDPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_SDP_LEVEL 0x2a45
++#define mmDPRX_SD1_DPRX_SD_SDP_LEVEL_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_SDP_DATA 0x2a46
++#define mmDPRX_SD1_DPRX_SD_SDP_DATA_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_SDP_ERROR 0x2a47
++#define mmDPRX_SD1_DPRX_SD_SDP_ERROR_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_AUDIO_HEADER 0x2a48
++#define mmDPRX_SD1_DPRX_SD_AUDIO_HEADER_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_AUDIO_FIFO_ERROR 0x2a49
++#define mmDPRX_SD1_DPRX_SD_AUDIO_FIFO_ERROR_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_SDP_CONTROL 0x2a4a
++#define mmDPRX_SD1_DPRX_SD_SDP_CONTROL_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_V_TOTAL_MEASURED 0x2a4b
++#define mmDPRX_SD1_DPRX_SD_V_TOTAL_MEASURED_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_H_TOTAL_MEASURED 0x2a4c
++#define mmDPRX_SD1_DPRX_SD_H_TOTAL_MEASURED_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_BS_COUNTER 0x2a4d
++#define mmDPRX_SD1_DPRX_SD_BS_COUNTER_BASE_IDX 2
++#define mmDPRX_SD1_DPRX_SD_MSE_ACT_HANDLED 0x2a4e
++#define mmDPRX_SD1_DPRX_SD_MSE_ACT_HANDLED_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dc_perfmon10_dispdec
++// base address: 0xacf8
++#define mmDC_PERFMON10_PERFCOUNTER_CNTL 0x2b5e
++#define mmDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX 2
++#define mmDC_PERFMON10_PERFCOUNTER_CNTL2 0x2b5f
++#define mmDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX 2
++#define mmDC_PERFMON10_PERFCOUNTER_STATE 0x2b60
++#define mmDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX 2
++#define mmDC_PERFMON10_PERFMON_CNTL 0x2b61
++#define mmDC_PERFMON10_PERFMON_CNTL_BASE_IDX 2
++#define mmDC_PERFMON10_PERFMON_CNTL2 0x2b62
++#define mmDC_PERFMON10_PERFMON_CNTL2_BASE_IDX 2
++#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x2b63
++#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
++#define mmDC_PERFMON10_PERFMON_CVALUE_LOW 0x2b64
++#define mmDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX 2
++#define mmDC_PERFMON10_PERFMON_HI 0x2b65
++#define mmDC_PERFMON10_PERFMON_HI_BASE_IDX 2
++#define mmDC_PERFMON10_PERFMON_LOW 0x2b66
++#define mmDC_PERFMON10_PERFMON_LOW_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dc_zcalregs_dispdec
++// base address: 0x0
++#define mmCOMP_EN_CTL 0x2d96
++#define mmCOMP_EN_CTL_BASE_IDX 2
++#define mmCOMP_EN_DFX 0x2d97
++#define mmCOMP_EN_DFX_BASE_IDX 2
++#define mmZCAL_FUSES 0x2d98
++#define mmZCAL_FUSES_BASE_IDX 2
++
++
++// addressBlock: dce_dc_dispdec_VGA_MEM_WRITE_PAGE_ADDR
++// base address: 0x48
++//#define mmVGA_dispdec_VGA_MEM_WRITE_PAGE_ADDR 0x0012
++
++
++// addressBlock: dce_dc_dispdec_VGA_MEM_READ_PAGE_ADDR
++// base address: 0x4c
++//#define mmVGA_dispdec_VGA_MEM_READ_PAGE_ADDR 0x0014
++
++
++// addressBlock: dce_dc_dispdec[948..986]
++// base address: 0x3b4
++//#define mmVGA_CRTC8_IDX 0x002d
++//#define mmVGA_CRTC8_DATA 0x002d
++//#define mmVGA_GENFC_WT 0x002e
++//#define mmVGA_GENS1 0x002e
++//#define mmVGA_ATTRDW 0x0030
++//#define mmVGA_ATTRX 0x0030
++//#define mmVGA_ATTRDR 0x0030
++//#define mmVGA_GENMO_WT 0x0030
++//#define mmVGA_GENS0 0x0030
++//#define mmVGA_GENENB 0x0030
++//#define mmVGA_SEQ8_IDX 0x0031
++//#define mmVGA_SEQ8_DATA 0x0031
++//#define mmVGA_DAC_MASK 0x0031
++//#define mmVGA_DAC_R_INDEX 0x0031
++//#define mmVGA_DAC_W_INDEX 0x0032
++//#define mmVGA_DAC_DATA 0x0032
++//#define mmVGA_GENFC_RD 0x0032
++//#define mmVGA_GENMO_RD 0x0033
++//#define mmVGA_GRPH8_IDX 0x0033
++//#define mmVGA_GRPH8_DATA 0x0033
++//#define mmVGA_CRTC8_IDX_1 0x0035
++//#define mmVGA_CRTC8_DATA_1 0x0035
++//#define mmVGA_GENFC_WT_1 0x0036
++//#define mmVGA_GENS1_1 0x0036
++
++
++// addressBlock: dce_dc_azdec
++// base address: 0x0
++#define mmCORB_WRITE_POINTER 0x0000
++#define mmCORB_WRITE_POINTER_BASE_IDX 0
++#define mmCORB_READ_POINTER 0x0000
++#define mmCORB_READ_POINTER_BASE_IDX 0
++#define mmCORB_CONTROL 0x0001
++#define mmCORB_CONTROL_BASE_IDX 0
++#define mmCORB_STATUS 0x0001
++#define mmCORB_STATUS_BASE_IDX 0
++#define mmCORB_SIZE 0x0001
++#define mmCORB_SIZE_BASE_IDX 0
++#define mmRIRB_LOWER_BASE_ADDRESS 0x0002
++#define mmRIRB_LOWER_BASE_ADDRESS_BASE_IDX 0
++#define mmRIRB_UPPER_BASE_ADDRESS 0x0003
++#define mmRIRB_UPPER_BASE_ADDRESS_BASE_IDX 0
++#define mmRIRB_WRITE_POINTER 0x0004
++#define mmRIRB_WRITE_POINTER_BASE_IDX 0
++#define mmRESPONSE_INTERRUPT_COUNT 0x0004
++#define mmRESPONSE_INTERRUPT_COUNT_BASE_IDX 0
++#define mmRIRB_CONTROL 0x0005
++#define mmRIRB_CONTROL_BASE_IDX 0
++#define mmRIRB_STATUS 0x0005
++#define mmRIRB_STATUS_BASE_IDX 0
++#define mmRIRB_SIZE 0x0005
++#define mmRIRB_SIZE_BASE_IDX 0
++#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x0006
++#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 0
++#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x0006
++#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 0
++#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
++#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
++#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
++#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
++#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
++#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
++#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
++#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
++#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006
++#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0
++#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
++#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
++#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
++#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
++#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007
++#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0
++#define mmIMMEDIATE_COMMAND_STATUS 0x0008
++#define mmIMMEDIATE_COMMAND_STATUS_BASE_IDX 0
++#define mmDMA_POSITION_LOWER_BASE_ADDRESS 0x000a
++#define mmDMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0
++#define mmDMA_POSITION_UPPER_BASE_ADDRESS 0x000b
++#define mmDMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0
++#define mmWALL_CLOCK_COUNTER_ALIAS 0x074c
++#define mmWALL_CLOCK_COUNTER_ALIAS_BASE_IDX 1
++
++
++// addressBlock: dce_dc_azstream0_azdec
++// base address: 0x0
++#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x000e
++#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
++#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x000f
++#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
++#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0010
++#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
++#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0011
++#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
++#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0012
++#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
++#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0012
++#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
++#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0014
++#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
++#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0015
++#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
++#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0761
++#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
++
++
++// addressBlock: dce_dc_azstream1_azdec
++// base address: 0x20
++#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0016
++#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
++#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0017
++#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
++#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0018
++#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
++#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0019
++#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
++#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x001a
++#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
++#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x001a
++#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
++#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x001c
++#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
++#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x001d
++#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
++#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0769
++#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
++
++
++// addressBlock: dce_dc_azstream2_azdec
++// base address: 0x40
++#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x001e
++#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
++#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x001f
++#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
++#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0020
++#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
++#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0021
++#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
++#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0022
++#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
++#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0022
++#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
++#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0024
++#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
++#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0025
++#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
++#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0771
++#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
++
++
++// addressBlock: dce_dc_azstream3_azdec
++// base address: 0x60
++#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0026
++#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
++#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0027
++#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
++#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0028
++#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
++#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0029
++#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
++#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x002a
++#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
++#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x002a
++#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
++#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x002c
++#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
++#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x002d
++#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
++#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0779
++#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
++
++
++// addressBlock: dce_dc_azstream4_azdec
++// base address: 0x80
++#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x002e
++#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
++#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x002f
++#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
++#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0030
++#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
++#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0031
++#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
++#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0032
++#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
++#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0032
++#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
++#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0034
++#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
++#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0035
++#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
++#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0781
++#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
++
++
++// addressBlock: dce_dc_azstream5_azdec
++// base address: 0xa0
++#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0036
++#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
++#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0037
++#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
++#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0038
++#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
++#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0039
++#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
++#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x003a
++#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
++#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x003a
++#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
++#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x003c
++#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
++#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x003d
++#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
++#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0789
++#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
++
++
++// addressBlock: dce_dc_azstream6_azdec
++// base address: 0xc0
++#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x003e
++#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
++#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x003f
++#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
++#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0040
++#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
++#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0041
++#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
++#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0042
++#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
++#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0042
++#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
++#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0044
++#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
++#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0045
++#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
++#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0791
++#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
++
++
++// addressBlock: dce_dc_azstream7_azdec
++// base address: 0xe0
++#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0046
++#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
++#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0047
++#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
++#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0048
++#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
++#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0049
++#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
++#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x004a
++#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
++#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x004a
++#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
++#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x004c
++#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
++#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x004d
++#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
++#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0799
++#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
++
++
++// addressBlock: azf0stream0_streamind
++// base address: 0x0
++#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 0x0000
++#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
++#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
++#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
++#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
++
++
++// addressBlock: azf0stream1_streamind
++// base address: 0x0
++#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 0x0000
++#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
++#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
++#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
++#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
++
++
++// addressBlock: azf0stream2_streamind
++// base address: 0x0
++#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 0x0000
++#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
++#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
++#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
++#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
++
++
++// addressBlock: azf0stream3_streamind
++// base address: 0x0
++#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 0x0000
++#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
++#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
++#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
++#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
++
++
++// addressBlock: azf0stream4_streamind
++// base address: 0x0
++#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 0x0000
++#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
++#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
++#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
++#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
++
++
++// addressBlock: azf0stream5_streamind
++// base address: 0x0
++#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 0x0000
++#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
++#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
++#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
++#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
++
++
++// addressBlock: azf0stream6_streamind
++// base address: 0x0
++#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 0x0000
++#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
++#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
++#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
++#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
++
++
++// addressBlock: azf0stream7_streamind
++// base address: 0x0
++#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 0x0000
++#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
++#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
++#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
++#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
++
++
++// addressBlock: azf0stream8_streamind
++// base address: 0x0
++#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 0x0000
++#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
++#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
++#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
++#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
++
++
++// addressBlock: azf0stream9_streamind
++// base address: 0x0
++#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 0x0000
++#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
++#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
++#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
++#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
++
++
++// addressBlock: azf0stream10_streamind
++// base address: 0x0
++#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 0x0000
++#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
++#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
++#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
++#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
++
++
++// addressBlock: azf0stream11_streamind
++// base address: 0x0
++#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 0x0000
++#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
++#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
++#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
++#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
++
++
++// addressBlock: azf0stream12_streamind
++// base address: 0x0
++#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 0x0000
++#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
++#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
++#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
++#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
++
++
++// addressBlock: azf0stream13_streamind
++// base address: 0x0
++#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 0x0000
++#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
++#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
++#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
++#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
++
++
++// addressBlock: azf0stream14_streamind
++// base address: 0x0
++#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 0x0000
++#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
++#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
++#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
++#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
++
++
++// addressBlock: azf0stream15_streamind
++// base address: 0x0
++#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 0x0000
++#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
++#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
++#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
++#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
++
++
++// addressBlock: azf0endpoint0_endpointind
++// base address: 0x0
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
++#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
++#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
++#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
++#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
++#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
++#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
++#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
++#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
++#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
++#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
++#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
++#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
++#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
++
++
++// addressBlock: azf0endpoint1_endpointind
++// base address: 0x0
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
++#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
++#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
++#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
++#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
++#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
++#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
++#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
++#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
++#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
++#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
++#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
++#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
++#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
++
++
++// addressBlock: azf0endpoint2_endpointind
++// base address: 0x0
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
++#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
++#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
++#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
++#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
++#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
++#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
++#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
++#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
++#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
++#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
++#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
++#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
++#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
++
++
++// addressBlock: azf0endpoint3_endpointind
++// base address: 0x0
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
++#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
++#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
++#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
++#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
++#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
++#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
++#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
++#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
++#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
++#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
++#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
++#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
++#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
++
++
++// addressBlock: azf0endpoint4_endpointind
++// base address: 0x0
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
++#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
++#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
++#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
++#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
++#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
++#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
++#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
++#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
++#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
++#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
++#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
++#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
++#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
++
++
++// addressBlock: azf0endpoint5_endpointind
++// base address: 0x0
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
++#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
++#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
++#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
++#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
++#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
++#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
++#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
++#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
++#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
++#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
++#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
++#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
++#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
++
++
++// addressBlock: azf0endpoint6_endpointind
++// base address: 0x0
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
++#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
++#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
++#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
++#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
++#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
++#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
++#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
++#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
++#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
++#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
++#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
++#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
++#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
++
++
++// addressBlock: azf0endpoint7_endpointind
++// base address: 0x0
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
++#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
++#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
++#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
++#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
++#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
++#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
++#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
++#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
++#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
++#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
++#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
++#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
++#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
++
++
++// addressBlock: azf0inputendpoint0_inputendpointind
++// base address: 0x0
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
++
++
++// addressBlock: azf0inputendpoint1_inputendpointind
++// base address: 0x0
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
++
++
++// addressBlock: azf0inputendpoint2_inputendpointind
++// base address: 0x0
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
++
++
++// addressBlock: azf0inputendpoint3_inputendpointind
++// base address: 0x0
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
++
++
++// addressBlock: azf0inputendpoint4_inputendpointind
++// base address: 0x0
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
++
++
++// addressBlock: azf0inputendpoint5_inputendpointind
++// base address: 0x0
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
++
++
++// addressBlock: azf0inputendpoint6_inputendpointind
++// base address: 0x0
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
++
++
++// addressBlock: azf0inputendpoint7_inputendpointind
++// base address: 0x0
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
++
++
++// addressBlock: f2codecind
++// base address: 0x0
++#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0f00
++#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0f02
++#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0f04
++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705
++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720
++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721
++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722
++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723
++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770
++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff
++#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04
++#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05
++#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a
++#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b
++#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f
++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200
++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706
++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d
++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e
++#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724
++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e
++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770
++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771
++#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09
++#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a
++#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792
++#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e
++#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09
++#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c
++#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e
++#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200
++#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706
++#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d
++#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09
++#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a
++#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e
++#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09
++#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c
++
++
++// addressBlock: descriptorind
++// base address: 0x0
++#define ixAUDIO_DESCRIPTOR0 0x0001
++#define ixAUDIO_DESCRIPTOR1 0x0002
++#define ixAUDIO_DESCRIPTOR2 0x0003
++#define ixAUDIO_DESCRIPTOR3 0x0004
++#define ixAUDIO_DESCRIPTOR4 0x0005
++#define ixAUDIO_DESCRIPTOR5 0x0006
++#define ixAUDIO_DESCRIPTOR6 0x0007
++#define ixAUDIO_DESCRIPTOR7 0x0008
++#define ixAUDIO_DESCRIPTOR8 0x0009
++#define ixAUDIO_DESCRIPTOR9 0x000a
++#define ixAUDIO_DESCRIPTOR10 0x000b
++#define ixAUDIO_DESCRIPTOR11 0x000c
++#define ixAUDIO_DESCRIPTOR12 0x000d
++#define ixAUDIO_DESCRIPTOR13 0x000e
++
++
++// addressBlock: sinkinfoind
++// base address: 0x0
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004
++#define ixSINK_DESCRIPTION0 0x0005
++#define ixSINK_DESCRIPTION1 0x0006
++#define ixSINK_DESCRIPTION2 0x0007
++#define ixSINK_DESCRIPTION3 0x0008
++#define ixSINK_DESCRIPTION4 0x0009
++#define ixSINK_DESCRIPTION5 0x000a
++#define ixSINK_DESCRIPTION6 0x000b
++#define ixSINK_DESCRIPTION7 0x000c
++#define ixSINK_DESCRIPTION8 0x000d
++#define ixSINK_DESCRIPTION9 0x000e
++#define ixSINK_DESCRIPTION10 0x000f
++#define ixSINK_DESCRIPTION11 0x0010
++#define ixSINK_DESCRIPTION12 0x0011
++#define ixSINK_DESCRIPTION13 0x0012
++#define ixSINK_DESCRIPTION14 0x0013
++#define ixSINK_DESCRIPTION15 0x0014
++#define ixSINK_DESCRIPTION16 0x0015
++#define ixSINK_DESCRIPTION17 0x0016
++
++
++// addressBlock: azinputcrc0resultind
++// base address: 0x0
++#define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0000
++#define ixAZALIA_INPUT_CRC0_CHANNEL1 0x0001
++#define ixAZALIA_INPUT_CRC0_CHANNEL2 0x0002
++#define ixAZALIA_INPUT_CRC0_CHANNEL3 0x0003
++#define ixAZALIA_INPUT_CRC0_CHANNEL4 0x0004
++#define ixAZALIA_INPUT_CRC0_CHANNEL5 0x0005
++#define ixAZALIA_INPUT_CRC0_CHANNEL6 0x0006
++#define ixAZALIA_INPUT_CRC0_CHANNEL7 0x0007
++
++
++// addressBlock: azinputcrc1resultind
++// base address: 0x0
++#define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0000
++#define ixAZALIA_INPUT_CRC1_CHANNEL1 0x0001
++#define ixAZALIA_INPUT_CRC1_CHANNEL2 0x0002
++#define ixAZALIA_INPUT_CRC1_CHANNEL3 0x0003
++#define ixAZALIA_INPUT_CRC1_CHANNEL4 0x0004
++#define ixAZALIA_INPUT_CRC1_CHANNEL5 0x0005
++#define ixAZALIA_INPUT_CRC1_CHANNEL6 0x0006
++#define ixAZALIA_INPUT_CRC1_CHANNEL7 0x0007
++
++
++// addressBlock: azcrc0resultind
++// base address: 0x0
++#define ixAZALIA_CRC0_CHANNEL0 0x0000
++#define ixAZALIA_CRC0_CHANNEL1 0x0001
++#define ixAZALIA_CRC0_CHANNEL2 0x0002
++#define ixAZALIA_CRC0_CHANNEL3 0x0003
++#define ixAZALIA_CRC0_CHANNEL4 0x0004
++#define ixAZALIA_CRC0_CHANNEL5 0x0005
++#define ixAZALIA_CRC0_CHANNEL6 0x0006
++#define ixAZALIA_CRC0_CHANNEL7 0x0007
++
++
++// addressBlock: azcrc1resultind
++// base address: 0x0
++#define ixAZALIA_CRC1_CHANNEL0 0x0000
++#define ixAZALIA_CRC1_CHANNEL1 0x0001
++#define ixAZALIA_CRC1_CHANNEL2 0x0002
++#define ixAZALIA_CRC1_CHANNEL3 0x0003
++#define ixAZALIA_CRC1_CHANNEL4 0x0004
++#define ixAZALIA_CRC1_CHANNEL5 0x0005
++#define ixAZALIA_CRC1_CHANNEL6 0x0006
++#define ixAZALIA_CRC1_CHANNEL7 0x0007
++
++
++// addressBlock: vgaseqind
++// base address: 0x0
++#define ixSEQ00 0x0000
++#define ixSEQ01 0x0001
++#define ixSEQ02 0x0002
++#define ixSEQ03 0x0003
++#define ixSEQ04 0x0004
++
++
++// addressBlock: vgacrtind
++// base address: 0x0
++#define ixCRT00 0x0000
++#define ixCRT01 0x0001
++#define ixCRT02 0x0002
++#define ixCRT03 0x0003
++#define ixCRT04 0x0004
++#define ixCRT05 0x0005
++#define ixCRT06 0x0006
++#define ixCRT07 0x0007
++#define ixCRT08 0x0008
++#define ixCRT09 0x0009
++#define ixCRT0A 0x000a
++#define ixCRT0B 0x000b
++#define ixCRT0C 0x000c
++#define ixCRT0D 0x000d
++#define ixCRT0E 0x000e
++#define ixCRT0F 0x000f
++#define ixCRT10 0x0010
++#define ixCRT11 0x0011
++#define ixCRT12 0x0012
++#define ixCRT13 0x0013
++#define ixCRT14 0x0014
++#define ixCRT15 0x0015
++#define ixCRT16 0x0016
++#define ixCRT17 0x0017
++#define ixCRT18 0x0018
++#define ixCRT1E 0x001e
++#define ixCRT1F 0x001f
++#define ixCRT22 0x0022
++
++
++// addressBlock: vgagrphind
++// base address: 0x0
++#define ixGRA00 0x0000
++#define ixGRA01 0x0001
++#define ixGRA02 0x0002
++#define ixGRA03 0x0003
++#define ixGRA04 0x0004
++#define ixGRA05 0x0005
++#define ixGRA06 0x0006
++#define ixGRA07 0x0007
++#define ixGRA08 0x0008
++
++
++// addressBlock: vgaattrind
++// base address: 0x0
++#define ixATTR00 0x0000
++#define ixATTR01 0x0001
++#define ixATTR02 0x0002
++#define ixATTR03 0x0003
++#define ixATTR04 0x0004
++#define ixATTR05 0x0005
++#define ixATTR06 0x0006
++#define ixATTR07 0x0007
++#define ixATTR08 0x0008
++#define ixATTR09 0x0009
++#define ixATTR0A 0x000a
++#define ixATTR0B 0x000b
++#define ixATTR0C 0x000c
++#define ixATTR0D 0x000d
++#define ixATTR0E 0x000e
++#define ixATTR0F 0x000f
++#define ixATTR10 0x0010
++#define ixATTR11 0x0011
++#define ixATTR12 0x0012
++#define ixATTR13 0x0013
++#define ixATTR14 0x0014
++
++
++#endif
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h
+new file mode 100644
+index 0000000..d8ad862
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h
+@@ -0,0 +1,64636 @@
++/*
++ * Copyright (C) 2017 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++#ifndef _dce_12_0_SH_MASK_HEADER
++#define _dce_12_0_SH_MASK_HEADER
++
++
++// addressBlock: dce_dc_dispdec_VGA_MEM_WRITE_PAGE_ADDR
++//dispdec_VGA_MEM_WRITE_PAGE_ADDR
++#define dispdec_VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0
++#define dispdec_VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10
++#define dispdec_VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x000003FFL
++#define dispdec_VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x03FF0000L
++
++
++// addressBlock: dce_dc_dispdec_VGA_MEM_READ_PAGE_ADDR
++//dispdec_VGA_MEM_READ_PAGE_ADDR
++#define dispdec_VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0
++#define dispdec_VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10
++#define dispdec_VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x000003FFL
++#define dispdec_VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x03FF0000L
++
++
++// addressBlock: dce_dc_dc_perfmon0_dispdec
++//DC_PERFMON0_PERFCOUNTER_CNTL
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
++//DC_PERFMON0_PERFCOUNTER_CNTL2
++#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
++#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
++#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
++#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
++#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
++#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
++#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
++#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
++//DC_PERFMON0_PERFCOUNTER_STATE
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
++//DC_PERFMON0_PERFMON_CNTL
++#define DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
++#define DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
++#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
++#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
++#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
++#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
++#define DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
++#define DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
++#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
++#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
++#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
++#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
++//DC_PERFMON0_PERFMON_CNTL2
++#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
++#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
++#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
++#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
++#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
++#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
++#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
++#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
++//DC_PERFMON0_PERFMON_CVALUE_INT_MISC
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
++//DC_PERFMON0_PERFMON_CVALUE_LOW
++#define DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
++#define DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
++//DC_PERFMON0_PERFMON_HI
++#define DC_PERFMON0_PERFMON_HI__PERFMON_HI__SHIFT 0x0
++#define DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
++#define DC_PERFMON0_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
++#define DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
++//DC_PERFMON0_PERFMON_LOW
++#define DC_PERFMON0_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
++#define DC_PERFMON0_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dc_perfmon13_dispdec
++//DC_PERFMON13_PERFCOUNTER_CNTL
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
++//DC_PERFMON13_PERFCOUNTER_CNTL2
++#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
++#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
++#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
++#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
++#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
++#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
++#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
++#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
++//DC_PERFMON13_PERFCOUNTER_STATE
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
++//DC_PERFMON13_PERFMON_CNTL
++#define DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
++#define DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
++#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
++#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
++#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
++#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
++#define DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
++#define DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
++#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
++#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
++#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
++#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
++//DC_PERFMON13_PERFMON_CNTL2
++#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
++#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
++#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
++#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
++#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
++#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
++#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
++#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
++//DC_PERFMON13_PERFMON_CVALUE_INT_MISC
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
++//DC_PERFMON13_PERFMON_CVALUE_LOW
++#define DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
++#define DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
++//DC_PERFMON13_PERFMON_HI
++#define DC_PERFMON13_PERFMON_HI__PERFMON_HI__SHIFT 0x0
++#define DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
++#define DC_PERFMON13_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
++#define DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
++//DC_PERFMON13_PERFMON_LOW
++#define DC_PERFMON13_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
++#define DC_PERFMON13_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dc_displaypllregs_dispdec
++//PPLL_VREG_CFG
++#define PPLL_VREG_CFG__pw_pc_bleeder_ac__SHIFT 0x0
++#define PPLL_VREG_CFG__pw_pc_bleeder_en__SHIFT 0x1
++#define PPLL_VREG_CFG__pw_pc_is_1p2__SHIFT 0x2
++#define PPLL_VREG_CFG__pw_pc_reg_obs_sel__SHIFT 0x3
++#define PPLL_VREG_CFG__pw_pc_reg_on_mode__SHIFT 0x5
++#define PPLL_VREG_CFG__pw_pc_rlad_tap_sel__SHIFT 0x7
++#define PPLL_VREG_CFG__pw_pc_reg_off_hi__SHIFT 0xb
++#define PPLL_VREG_CFG__pw_pc_reg_off_lo__SHIFT 0xc
++#define PPLL_VREG_CFG__pw_pc_scale_driver__SHIFT 0xd
++#define PPLL_VREG_CFG__pw_pc_sel_bump__SHIFT 0xf
++#define PPLL_VREG_CFG__pw_pc_sel_rladder_x__SHIFT 0x10
++#define PPLL_VREG_CFG__pw_pc_short_rc_filt_x__SHIFT 0x11
++#define PPLL_VREG_CFG__pw_pc_vref_pwr_on__SHIFT 0x12
++#define PPLL_VREG_CFG__pw_pc_dpll_cfg_2__SHIFT 0x14
++#define PPLL_VREG_CFG__pw_pc_bleeder_ac_MASK 0x00000001L
++#define PPLL_VREG_CFG__pw_pc_bleeder_en_MASK 0x00000002L
++#define PPLL_VREG_CFG__pw_pc_is_1p2_MASK 0x00000004L
++#define PPLL_VREG_CFG__pw_pc_reg_obs_sel_MASK 0x00000018L
++#define PPLL_VREG_CFG__pw_pc_reg_on_mode_MASK 0x00000060L
++#define PPLL_VREG_CFG__pw_pc_rlad_tap_sel_MASK 0x00000780L
++#define PPLL_VREG_CFG__pw_pc_reg_off_hi_MASK 0x00000800L
++#define PPLL_VREG_CFG__pw_pc_reg_off_lo_MASK 0x00001000L
++#define PPLL_VREG_CFG__pw_pc_scale_driver_MASK 0x00006000L
++#define PPLL_VREG_CFG__pw_pc_sel_bump_MASK 0x00008000L
++#define PPLL_VREG_CFG__pw_pc_sel_rladder_x_MASK 0x00010000L
++#define PPLL_VREG_CFG__pw_pc_short_rc_filt_x_MASK 0x00020000L
++#define PPLL_VREG_CFG__pw_pc_vref_pwr_on_MASK 0x00040000L
++#define PPLL_VREG_CFG__pw_pc_dpll_cfg_2_MASK 0x0FF00000L
++//PPLL_MODE_CNTL
++#define PPLL_MODE_CNTL__pw_pc_refclk_gate_dis__SHIFT 0x0
++#define PPLL_MODE_CNTL__pw_pc_multi_phase_en__SHIFT 0x8
++#define PPLL_MODE_CNTL__reg_tmg_pwr_state__SHIFT 0x10
++#define PPLL_MODE_CNTL__pw_pc_refclk_gate_dis_MASK 0x00000001L
++#define PPLL_MODE_CNTL__pw_pc_multi_phase_en_MASK 0x00000F00L
++#define PPLL_MODE_CNTL__reg_tmg_pwr_state_MASK 0x00030000L
++//PPLL_FREQ_CTRL0
++#define PPLL_FREQ_CTRL0__reg_tmg_fcw0_frac__SHIFT 0x0
++#define PPLL_FREQ_CTRL0__reg_tmg_fcw0_int__SHIFT 0x10
++#define PPLL_FREQ_CTRL0__reg_tmg_fcw0_frac_MASK 0x0000FFFFL
++#define PPLL_FREQ_CTRL0__reg_tmg_fcw0_int_MASK 0x01FF0000L
++//PPLL_FREQ_CTRL1
++#define PPLL_FREQ_CTRL1__reg_tmg_fcw1_frac__SHIFT 0x0
++#define PPLL_FREQ_CTRL1__reg_tmg_fcw1_int__SHIFT 0x10
++#define PPLL_FREQ_CTRL1__reg_tmg_fcw1_frac_MASK 0x0000FFFFL
++#define PPLL_FREQ_CTRL1__reg_tmg_fcw1_int_MASK 0x01FF0000L
++//PPLL_FREQ_CTRL2
++#define PPLL_FREQ_CTRL2__reg_tmg_fcw_denom__SHIFT 0x0
++#define PPLL_FREQ_CTRL2__reg_tmg_fcw_slew_frac__SHIFT 0x10
++#define PPLL_FREQ_CTRL2__reg_tmg_fcw_denom_MASK 0x0000FFFFL
++#define PPLL_FREQ_CTRL2__reg_tmg_fcw_slew_frac_MASK 0xFFFF0000L
++//PPLL_FREQ_CTRL3
++#define PPLL_FREQ_CTRL3__reg_tmg_refclk_div__SHIFT 0x0
++#define PPLL_FREQ_CTRL3__reg_tmg_vco_pre_div__SHIFT 0x3
++#define PPLL_FREQ_CTRL3__reg_tmg_fracn_en__SHIFT 0x6
++#define PPLL_FREQ_CTRL3__reg_tmg_ssc_en__SHIFT 0x8
++#define PPLL_FREQ_CTRL3__reg_tmg_fcw_sel__SHIFT 0xa
++#define PPLL_FREQ_CTRL3__reg_tmg_freq_jump_en__SHIFT 0xc
++#define PPLL_FREQ_CTRL3__reg_tmg_tdc_resol__SHIFT 0x10
++#define PPLL_FREQ_CTRL3__pw_pc_dpll_cfg_1__SHIFT 0x18
++#define PPLL_FREQ_CTRL3__reg_tmg_refclk_div_MASK 0x00000003L
++#define PPLL_FREQ_CTRL3__reg_tmg_vco_pre_div_MASK 0x00000018L
++#define PPLL_FREQ_CTRL3__reg_tmg_fracn_en_MASK 0x00000040L
++#define PPLL_FREQ_CTRL3__reg_tmg_ssc_en_MASK 0x00000100L
++#define PPLL_FREQ_CTRL3__reg_tmg_fcw_sel_MASK 0x00000400L
++#define PPLL_FREQ_CTRL3__reg_tmg_freq_jump_en_MASK 0x00001000L
++#define PPLL_FREQ_CTRL3__reg_tmg_tdc_resol_MASK 0x00FF0000L
++#define PPLL_FREQ_CTRL3__pw_pc_dpll_cfg_1_MASK 0xFF000000L
++//PPLL_BW_CTRL_COARSE
++#define PPLL_BW_CTRL_COARSE__reg_tmg_gi_crse_mant__SHIFT 0x0
++#define PPLL_BW_CTRL_COARSE__reg_tmg_gi_crse_exp__SHIFT 0x2
++#define PPLL_BW_CTRL_COARSE__reg_tmg_gp_crse_mant__SHIFT 0x7
++#define PPLL_BW_CTRL_COARSE__reg_tmg_gp_crse_exp__SHIFT 0xc
++#define PPLL_BW_CTRL_COARSE__reg_tmg_nctl_crse_res__SHIFT 0x11
++#define PPLL_BW_CTRL_COARSE__reg_tmg_nctl_crse_frac_res__SHIFT 0x18
++#define PPLL_BW_CTRL_COARSE__reg_tmg_gi_crse_mant_MASK 0x00000003L
++#define PPLL_BW_CTRL_COARSE__reg_tmg_gi_crse_exp_MASK 0x0000003CL
++#define PPLL_BW_CTRL_COARSE__reg_tmg_gp_crse_mant_MASK 0x00000780L
++#define PPLL_BW_CTRL_COARSE__reg_tmg_gp_crse_exp_MASK 0x0000F000L
++#define PPLL_BW_CTRL_COARSE__reg_tmg_nctl_crse_res_MASK 0x007E0000L
++#define PPLL_BW_CTRL_COARSE__reg_tmg_nctl_crse_frac_res_MASK 0x03000000L
++//PPLL_BW_CTRL_FINE
++#define PPLL_BW_CTRL_FINE__pw_pc_dpll_cfg_3__SHIFT 0x0
++#define PPLL_BW_CTRL_FINE__pw_pc_dpll_cfg_3_MASK 0x000003FFL
++//PPLL_CAL_CTRL
++#define PPLL_CAL_CTRL__pw_pc_bypass_freq_lock__SHIFT 0x0
++#define PPLL_CAL_CTRL__pw_pc_tdc_cal_en__SHIFT 0x1
++#define PPLL_CAL_CTRL__pw_pc_tdc_cal_ctrl__SHIFT 0x3
++#define PPLL_CAL_CTRL__pw_pc_meas_win_sel__SHIFT 0x9
++#define PPLL_CAL_CTRL__pw_pc_kdco_cal_dis__SHIFT 0xb
++#define PPLL_CAL_CTRL__pw_pc_kdco_ratio__SHIFT 0xd
++#define PPLL_CAL_CTRL__pw_pc_kdco_incr_cal_dis__SHIFT 0x16
++#define PPLL_CAL_CTRL__pw_pc_nctl_adj_dis__SHIFT 0x17
++#define PPLL_CAL_CTRL__pw_pc_refclk_rate__SHIFT 0x18
++#define PPLL_CAL_CTRL__pw_pc_bypass_freq_lock_MASK 0x00000001L
++#define PPLL_CAL_CTRL__pw_pc_tdc_cal_en_MASK 0x00000002L
++#define PPLL_CAL_CTRL__pw_pc_tdc_cal_ctrl_MASK 0x000001F8L
++#define PPLL_CAL_CTRL__pw_pc_meas_win_sel_MASK 0x00000600L
++#define PPLL_CAL_CTRL__pw_pc_kdco_cal_dis_MASK 0x00000800L
++#define PPLL_CAL_CTRL__pw_pc_kdco_ratio_MASK 0x001FE000L
++#define PPLL_CAL_CTRL__pw_pc_kdco_incr_cal_dis_MASK 0x00400000L
++#define PPLL_CAL_CTRL__pw_pc_nctl_adj_dis_MASK 0x00800000L
++#define PPLL_CAL_CTRL__pw_pc_refclk_rate_MASK 0xFF000000L
++//PPLL_LOOP_CTRL
++#define PPLL_LOOP_CTRL__pw_pc_fbdiv_mask_en__SHIFT 0x0
++#define PPLL_LOOP_CTRL__pw_pc_fb_slip_dis__SHIFT 0x2
++#define PPLL_LOOP_CTRL__pw_pc_clk_tdc_sel__SHIFT 0x4
++#define PPLL_LOOP_CTRL__pw_pc_clk_nctl_sel__SHIFT 0x7
++#define PPLL_LOOP_CTRL__pw_pc_sig_del_patt_sel__SHIFT 0xa
++#define PPLL_LOOP_CTRL__pw_pc_nctl_sig_del_dis__SHIFT 0xc
++#define PPLL_LOOP_CTRL__pw_pc_fbclk_track_refclk__SHIFT 0xe
++#define PPLL_LOOP_CTRL__pw_pc_prbs_en__SHIFT 0x10
++#define PPLL_LOOP_CTRL__pw_pc_tdc_clk_gate_en__SHIFT 0x12
++#define PPLL_LOOP_CTRL__pw_pc_phase_offset__SHIFT 0x14
++#define PPLL_LOOP_CTRL__pw_pc_fbdiv_mask_en_MASK 0x00000001L
++#define PPLL_LOOP_CTRL__pw_pc_fb_slip_dis_MASK 0x00000004L
++#define PPLL_LOOP_CTRL__pw_pc_clk_tdc_sel_MASK 0x00000030L
++#define PPLL_LOOP_CTRL__pw_pc_clk_nctl_sel_MASK 0x00000180L
++#define PPLL_LOOP_CTRL__pw_pc_sig_del_patt_sel_MASK 0x00000400L
++#define PPLL_LOOP_CTRL__pw_pc_nctl_sig_del_dis_MASK 0x00001000L
++#define PPLL_LOOP_CTRL__pw_pc_fbclk_track_refclk_MASK 0x00004000L
++#define PPLL_LOOP_CTRL__pw_pc_prbs_en_MASK 0x00010000L
++#define PPLL_LOOP_CTRL__pw_pc_tdc_clk_gate_en_MASK 0x00040000L
++#define PPLL_LOOP_CTRL__pw_pc_phase_offset_MASK 0x07F00000L
++//PPLL_REFCLK_CNTL
++#define PPLL_REFCLK_CNTL__regs_pw_refclk0_recv_en__SHIFT 0x0
++#define PPLL_REFCLK_CNTL__regs_pw_refclk1_recv_en__SHIFT 0x1
++#define PPLL_REFCLK_CNTL__regs_pw_refclk2_recv_en__SHIFT 0x2
++#define PPLL_REFCLK_CNTL__regs_pw_refclk3_recv_en__SHIFT 0x3
++#define PPLL_REFCLK_CNTL__regs_pw_refclk0_recv_sel__SHIFT 0x8
++#define PPLL_REFCLK_CNTL__regs_pw_refclk1_recv_sel__SHIFT 0x9
++#define PPLL_REFCLK_CNTL__regs_pw_refclk2_recv_sel__SHIFT 0xa
++#define PPLL_REFCLK_CNTL__regs_pw_refclk3_recv_sel__SHIFT 0xb
++#define PPLL_REFCLK_CNTL__regs_pw_refdivsrc__SHIFT 0xe
++#define PPLL_REFCLK_CNTL__regs_pw_ref2core_sel__SHIFT 0x10
++#define PPLL_REFCLK_CNTL__regs_pw_refclk0_recv_en_MASK 0x00000001L
++#define PPLL_REFCLK_CNTL__regs_pw_refclk1_recv_en_MASK 0x00000002L
++#define PPLL_REFCLK_CNTL__regs_pw_refclk2_recv_en_MASK 0x00000004L
++#define PPLL_REFCLK_CNTL__regs_pw_refclk3_recv_en_MASK 0x00000008L
++#define PPLL_REFCLK_CNTL__regs_pw_refclk0_recv_sel_MASK 0x00000100L
++#define PPLL_REFCLK_CNTL__regs_pw_refclk1_recv_sel_MASK 0x00000200L
++#define PPLL_REFCLK_CNTL__regs_pw_refclk2_recv_sel_MASK 0x00000400L
++#define PPLL_REFCLK_CNTL__regs_pw_refclk3_recv_sel_MASK 0x00000800L
++#define PPLL_REFCLK_CNTL__regs_pw_refdivsrc_MASK 0x0000C000L
++#define PPLL_REFCLK_CNTL__regs_pw_ref2core_sel_MASK 0x00010000L
++//PPLL_CLKOUT_CNTL
++#define PPLL_CLKOUT_CNTL__regs_pw_pixclk_pre_pdivsel__SHIFT 0x8
++#define PPLL_CLKOUT_CNTL__regs_pw_pixclk_pdivsel__SHIFT 0x9
++#define PPLL_CLKOUT_CNTL__regs_pw_dvoclk_pre_pdivsel__SHIFT 0xa
++#define PPLL_CLKOUT_CNTL__regs_pw_dvoclk_pdivsel__SHIFT 0xb
++#define PPLL_CLKOUT_CNTL__regs_pw_idclk_en__SHIFT 0xc
++#define PPLL_CLKOUT_CNTL__regs_pw_idclk_pre_pdivsel__SHIFT 0xd
++#define PPLL_CLKOUT_CNTL__regs_pw_idclk_pdivsel__SHIFT 0xe
++#define PPLL_CLKOUT_CNTL__regs_pw_idclk_obs_sel__SHIFT 0xf
++#define PPLL_CLKOUT_CNTL__regs_pw_refclk_sel__SHIFT 0x10
++#define PPLL_CLKOUT_CNTL__regs_cc_resetb__SHIFT 0x14
++#define PPLL_CLKOUT_CNTL__regs_pw_pixclk_pre_pdivsel_MASK 0x00000100L
++#define PPLL_CLKOUT_CNTL__regs_pw_pixclk_pdivsel_MASK 0x00000200L
++#define PPLL_CLKOUT_CNTL__regs_pw_dvoclk_pre_pdivsel_MASK 0x00000400L
++#define PPLL_CLKOUT_CNTL__regs_pw_dvoclk_pdivsel_MASK 0x00000800L
++#define PPLL_CLKOUT_CNTL__regs_pw_idclk_en_MASK 0x00001000L
++#define PPLL_CLKOUT_CNTL__regs_pw_idclk_pre_pdivsel_MASK 0x00002000L
++#define PPLL_CLKOUT_CNTL__regs_pw_idclk_pdivsel_MASK 0x00004000L
++#define PPLL_CLKOUT_CNTL__regs_pw_idclk_obs_sel_MASK 0x00008000L
++#define PPLL_CLKOUT_CNTL__regs_pw_refclk_sel_MASK 0x00030000L
++#define PPLL_CLKOUT_CNTL__regs_cc_resetb_MASK 0x00100000L
++//PPLL_DFT_CNTL
++#define PPLL_DFT_CNTL__regs_pw_obs_en__SHIFT 0x0
++#define PPLL_DFT_CNTL__regs_pw_obs_div_sel_1__SHIFT 0x1
++#define PPLL_DFT_CNTL__regs_pw_obs_clk_sel_1__SHIFT 0x4
++#define PPLL_DFT_CNTL__regs_pw_obs_clk_sel_2__SHIFT 0x8
++#define PPLL_DFT_CNTL__regs_pw_obs_sel__SHIFT 0xc
++#define PPLL_DFT_CNTL__regs_pw_obs_en_MASK 0x00000001L
++#define PPLL_DFT_CNTL__regs_pw_obs_div_sel_1_MASK 0x00000006L
++#define PPLL_DFT_CNTL__regs_pw_obs_clk_sel_1_MASK 0x000000F0L
++#define PPLL_DFT_CNTL__regs_pw_obs_clk_sel_2_MASK 0x00000F00L
++#define PPLL_DFT_CNTL__regs_pw_obs_sel_MASK 0x00003000L
++//PPLL_ANALOG_CNTL
++#define PPLL_ANALOG_CNTL__regs_pw_spare__SHIFT 0x0
++#define PPLL_ANALOG_CNTL__regs_pw_spare_MASK 0x000000FFL
++//PPLL_POSTDIV
++#define PPLL_POSTDIV__reg_tmg_postdiv__SHIFT 0x8
++#define PPLL_POSTDIV__reg_tmg_pixclk_pdiv2__SHIFT 0xc
++#define PPLL_POSTDIV__reg_tmg_postdiv_MASK 0x00000F00L
++#define PPLL_POSTDIV__reg_tmg_pixclk_pdiv2_MASK 0x00001000L
++//PPLL_OBSERVE0
++#define PPLL_OBSERVE0__pw_pc_lock_det_tdc_steps__SHIFT 0x0
++#define PPLL_OBSERVE0__pw_pc_clear_sticky_lock__SHIFT 0x6
++#define PPLL_OBSERVE0__pw_pc_lock_det_dis__SHIFT 0x8
++#define PPLL_OBSERVE0__pw_pc_dco_cfg__SHIFT 0xa
++#define PPLL_OBSERVE0__pw_pc_anaobs_sel__SHIFT 0x15
++#define PPLL_OBSERVE0__pw_pc_lock_det_tdc_steps_MASK 0x0000001FL
++#define PPLL_OBSERVE0__pw_pc_clear_sticky_lock_MASK 0x00000040L
++#define PPLL_OBSERVE0__pw_pc_lock_det_dis_MASK 0x00000100L
++#define PPLL_OBSERVE0__pw_pc_dco_cfg_MASK 0x0003FC00L
++#define PPLL_OBSERVE0__pw_pc_anaobs_sel_MASK 0x00E00000L
++//PPLL_OBSERVE1
++#define PPLL_OBSERVE1__pw_pc_digobs_sel__SHIFT 0x0
++#define PPLL_OBSERVE1__pw_pc_digobs_trig_sel__SHIFT 0x5
++#define PPLL_OBSERVE1__pw_pc_digobs_div__SHIFT 0xa
++#define PPLL_OBSERVE1__pw_pc_digobs_trig_div__SHIFT 0xc
++#define PPLL_OBSERVE1__reg_tmg_lock_timer__SHIFT 0x10
++#define PPLL_OBSERVE1__pw_pc_digobs_sel_MASK 0x0000000FL
++#define PPLL_OBSERVE1__pw_pc_digobs_trig_sel_MASK 0x000001E0L
++#define PPLL_OBSERVE1__pw_pc_digobs_div_MASK 0x00000C00L
++#define PPLL_OBSERVE1__pw_pc_digobs_trig_div_MASK 0x00003000L
++#define PPLL_OBSERVE1__reg_tmg_lock_timer_MASK 0x3FFF0000L
++//PPLL_UPDATE_CNTL
++#define PPLL_UPDATE_CNTL__reg_tmg_PLL_UPDATE_LOCK__SHIFT 0x2
++#define PPLL_UPDATE_CNTL__reg_tmg_PLL_UPDATE_POINT__SHIFT 0x3
++#define PPLL_UPDATE_CNTL__tmg_reg_UPDATE_PENDING__SHIFT 0x8
++#define PPLL_UPDATE_CNTL__pc_pw_pll_rdy__SHIFT 0x9
++#define PPLL_UPDATE_CNTL__TieLow1__SHIFT 0x10
++#define PPLL_UPDATE_CNTL__reg_tmg_PLL_UPDATE_LOCK_MASK 0x00000004L
++#define PPLL_UPDATE_CNTL__reg_tmg_PLL_UPDATE_POINT_MASK 0x00000008L
++#define PPLL_UPDATE_CNTL__tmg_reg_UPDATE_PENDING_MASK 0x00000100L
++#define PPLL_UPDATE_CNTL__pc_pw_pll_rdy_MASK 0x00000200L
++#define PPLL_UPDATE_CNTL__TieLow1_MASK 0x00010000L
++//PPLL_OBSERVE0_OUT
++#define PPLL_OBSERVE0_OUT__disppll_core_obsout__SHIFT 0x0
++#define PPLL_OBSERVE0_OUT__disppll_core_obsout_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dccg_pll0_dispdec
++//PLL_MACRO_CNTL_RESERVED0
++#define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED1
++#define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED2
++#define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED3
++#define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED4
++#define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED5
++#define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED6
++#define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED7
++#define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED8
++#define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED9
++#define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED10
++#define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED11
++#define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED12
++#define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED13
++#define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED14
++#define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED15
++#define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED16
++#define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED17
++#define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED18
++#define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED19
++#define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED20
++#define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED21
++#define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED22
++#define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED23
++#define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED24
++#define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED25
++#define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED26
++#define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED27
++#define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED28
++#define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED29
++#define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED30
++#define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED31
++#define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED32
++#define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED33
++#define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED34
++#define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED35
++#define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED36
++#define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED37
++#define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED38
++#define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED39
++#define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED40
++#define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED41
++#define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dc_perfmon1_dispdec
++//DC_PERFMON1_PERFCOUNTER_CNTL
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
++//DC_PERFMON1_PERFCOUNTER_CNTL2
++#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
++#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
++#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
++#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
++#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
++#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
++#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
++#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
++//DC_PERFMON1_PERFCOUNTER_STATE
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
++//DC_PERFMON1_PERFMON_CNTL
++#define DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
++#define DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
++#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
++#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
++#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
++#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
++#define DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
++#define DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
++#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
++#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
++#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
++#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
++//DC_PERFMON1_PERFMON_CNTL2
++#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
++#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
++#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
++#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
++#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
++#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
++#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
++#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
++//DC_PERFMON1_PERFMON_CVALUE_INT_MISC
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
++//DC_PERFMON1_PERFMON_CVALUE_LOW
++#define DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
++#define DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
++//DC_PERFMON1_PERFMON_HI
++#define DC_PERFMON1_PERFMON_HI__PERFMON_HI__SHIFT 0x0
++#define DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
++#define DC_PERFMON1_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
++#define DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
++//DC_PERFMON1_PERFMON_LOW
++#define DC_PERFMON1_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
++#define DC_PERFMON1_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_mcif_wb0_dispdec
++//MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL
++#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT 0x0
++#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ__SHIFT 0x1
++#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT 0x4
++#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT 0x5
++#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6
++#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT 0x7
++#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT 0x8
++#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID__SHIFT 0x10
++#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT 0x18
++#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK 0x00000001L
++#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ_MASK 0x00000002L
++#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK 0x00000010L
++#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK 0x00000020L
++#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK 0x00000040L
++#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK 0x00000080L
++#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK 0x00000F00L
++#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID_MASK 0x000F0000L
++#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK 0x01000000L
++//MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R
++#define MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R__SHIFT 0x0
++#define MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R_MASK 0x00001FFFL
++//MCIF_WB0_MCIF_WB_BUFMGR_STATUS
++#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT 0x0
++#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT 0x1
++#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT 0x2
++#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT 0x4
++#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT 0x7
++#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT 0x8
++#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT 0xc
++#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT 0x1c
++#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK 0x00000001L
++#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK 0x00000002L
++#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK 0x00000004L
++#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK 0x00000070L
++#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK 0x00000080L
++#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK 0x00000F00L
++#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK 0x01FFF000L
++#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK 0x70000000L
++//MCIF_WB0_MCIF_WB_BUF_PITCH
++#define MCIF_WB0_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT 0x8
++#define MCIF_WB0_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT 0x18
++#define MCIF_WB0_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK 0x0000FF00L
++#define MCIF_WB0_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK 0xFF000000L
++//MCIF_WB0_MCIF_WB_BUF_1_STATUS
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT 0x0
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT 0x1
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT 0x2
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT 0x3
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT 0x4
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT 0x5
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT 0x8
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT 0xc
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD__SHIFT 0xf
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT 0x10
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR__SHIFT 0x1d
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR__SHIFT 0x1e
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR__SHIFT 0x1f
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK 0x00000001L
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK 0x00000002L
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK 0x00000004L
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK 0x00000008L
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK 0x00000010L
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK 0x000000E0L
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK 0x00000F00L
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK 0x00007000L
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD_MASK 0x00008000L
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK 0x1FFF0000L
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR_MASK 0x20000000L
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR_MASK 0x40000000L
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR_MASK 0x80000000L
++//MCIF_WB0_MCIF_WB_BUF_1_STATUS2
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R__SHIFT 0x0
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT 0xd
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT 0xe
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT 0x11
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT 0x12
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R_MASK 0x00001FFFL
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK 0x00002000L
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK 0x00004000L
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK 0x00020000L
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK 0x00040000L
++//MCIF_WB0_MCIF_WB_BUF_2_STATUS
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT 0x0
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT 0x1
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT 0x2
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT 0x3
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT 0x4
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT 0x5
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT 0x8
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT 0xc
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD__SHIFT 0xf
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT 0x10
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR__SHIFT 0x1d
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR__SHIFT 0x1e
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR__SHIFT 0x1f
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK 0x00000001L
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK 0x00000002L
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK 0x00000004L
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK 0x00000008L
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK 0x00000010L
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK 0x000000E0L
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK 0x00000F00L
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK 0x00007000L
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD_MASK 0x00008000L
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK 0x1FFF0000L
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR_MASK 0x20000000L
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR_MASK 0x40000000L
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR_MASK 0x80000000L
++//MCIF_WB0_MCIF_WB_BUF_2_STATUS2
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R__SHIFT 0x0
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT 0xd
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT 0xe
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT 0x11
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT 0x12
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R_MASK 0x00001FFFL
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK 0x00002000L
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK 0x00004000L
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK 0x00020000L
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK 0x00040000L
++//MCIF_WB0_MCIF_WB_BUF_3_STATUS
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT 0x0
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT 0x1
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT 0x2
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT 0x3
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT 0x4
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT 0x5
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT 0x8
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT 0xc
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD__SHIFT 0xf
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT 0x10
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR__SHIFT 0x1d
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR__SHIFT 0x1e
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR__SHIFT 0x1f
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK 0x00000001L
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK 0x00000002L
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK 0x00000004L
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK 0x00000008L
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK 0x00000010L
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK 0x000000E0L
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK 0x00000F00L
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK 0x00007000L
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD_MASK 0x00008000L
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK 0x1FFF0000L
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR_MASK 0x20000000L
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR_MASK 0x40000000L
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR_MASK 0x80000000L
++//MCIF_WB0_MCIF_WB_BUF_3_STATUS2
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R__SHIFT 0x0
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT 0xd
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT 0xe
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT 0x11
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT 0x12
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R_MASK 0x00001FFFL
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK 0x00002000L
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK 0x00004000L
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK 0x00020000L
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK 0x00040000L
++//MCIF_WB0_MCIF_WB_BUF_4_STATUS
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT 0x0
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT 0x1
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT 0x2
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT 0x3
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT 0x4
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT 0x5
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT 0x8
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT 0xc
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD__SHIFT 0xf
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT 0x10
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR__SHIFT 0x1d
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR__SHIFT 0x1e
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR__SHIFT 0x1f
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK 0x00000001L
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK 0x00000002L
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK 0x00000004L
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK 0x00000008L
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK 0x00000010L
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK 0x000000E0L
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK 0x00000F00L
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK 0x00007000L
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD_MASK 0x00008000L
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK 0x1FFF0000L
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR_MASK 0x20000000L
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR_MASK 0x40000000L
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR_MASK 0x80000000L
++//MCIF_WB0_MCIF_WB_BUF_4_STATUS2
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R__SHIFT 0x0
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT 0xd
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT 0xe
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT 0x11
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT 0x12
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R_MASK 0x00001FFFL
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK 0x00002000L
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK 0x00004000L
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK 0x00020000L
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK 0x00040000L
++//MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL
++#define MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT 0x0
++#define MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT 0x16
++#define MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK 0x00000003L
++#define MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK 0xFFC00000L
++//MCIF_WB0_MCIF_WB_SCLK_CHANGE
++#define MCIF_WB0_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT 0x0
++#define MCIF_WB0_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK__SHIFT 0x1
++#define MCIF_WB0_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK 0x00000001L
++#define MCIF_WB0_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK_MASK 0x0000000EL
++//MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y
++#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT 0x0
++#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK 0xFFFFFFFFL
++//MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET
++#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET__SHIFT 0x0
++#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET_MASK 0x0003FFFFL
++//MCIF_WB0_MCIF_WB_BUF_1_ADDR_C
++#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT 0x0
++#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK 0xFFFFFFFFL
++//MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET
++#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET__SHIFT 0x0
++#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET_MASK 0x0003FFFFL
++//MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y
++#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT 0x0
++#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK 0xFFFFFFFFL
++//MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET
++#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET__SHIFT 0x0
++#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET_MASK 0x0003FFFFL
++//MCIF_WB0_MCIF_WB_BUF_2_ADDR_C
++#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT 0x0
++#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK 0xFFFFFFFFL
++//MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET
++#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET__SHIFT 0x0
++#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET_MASK 0x0003FFFFL
++//MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y
++#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT 0x0
++#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK 0xFFFFFFFFL
++//MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET
++#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET__SHIFT 0x0
++#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET_MASK 0x0003FFFFL
++//MCIF_WB0_MCIF_WB_BUF_3_ADDR_C
++#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT 0x0
++#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK 0xFFFFFFFFL
++//MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET
++#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET__SHIFT 0x0
++#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET_MASK 0x0003FFFFL
++//MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y
++#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT 0x0
++#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK 0xFFFFFFFFL
++//MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET
++#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET__SHIFT 0x0
++#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET_MASK 0x0003FFFFL
++//MCIF_WB0_MCIF_WB_BUF_4_ADDR_C
++#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT 0x0
++#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK 0xFFFFFFFFL
++//MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET
++#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET__SHIFT 0x0
++#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET_MASK 0x0003FFFFL
++//MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL
++#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT 0x0
++#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT 0x4
++#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT 0x5
++#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT 0x6
++#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT 0x8
++#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT 0x10
++#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK 0x00000001L
++#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK 0x00000010L
++#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK 0x00000020L
++#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK 0x00000040L
++#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK 0x00000F00L
++#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK 0x1FFF0000L
++//MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK
++#define MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT 0x0
++#define MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK 0x0001FFFFL
++//MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL
++#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x0
++#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x1
++#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0x2
++#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x4
++#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000001L
++#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000002L
++#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000004L
++#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00000070L
++//MCIF_WB0_MCIF_WB_WATERMARK
++#define MCIF_WB0_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT 0x0
++#define MCIF_WB0_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK 0x0000FFFFL
++//MCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL
++#define MCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT 0x0
++#define MCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK 0x00000001L
++//MCIF_WB0_MCIF_WB_WARM_UP_CNTL
++#define MCIF_WB0_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP__SHIFT 0x8
++#define MCIF_WB0_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP_MASK 0x0000FF00L
++//MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL
++#define MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ__SHIFT 0x0
++#define MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT 0x1
++#define MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ_MASK 0x00000001L
++#define MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK 0x00000002L
++//MCIF_WB0_MULTI_LEVEL_QOS_CTRL
++#define MCIF_WB0_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT 0x0
++#define MCIF_WB0_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK 0x003FFFFFL
++//MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE
++#define MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT 0x0
++#define MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK 0x000FFFFFL
++//MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE
++#define MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT 0x0
++#define MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK 0x000FFFFFL
++
++
++// addressBlock: dce_dc_mcif_wb1_dispdec
++//MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL
++#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT 0x0
++#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ__SHIFT 0x1
++#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT 0x4
++#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT 0x5
++#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6
++#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT 0x7
++#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT 0x8
++#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID__SHIFT 0x10
++#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT 0x18
++#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK 0x00000001L
++#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ_MASK 0x00000002L
++#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK 0x00000010L
++#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK 0x00000020L
++#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK 0x00000040L
++#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK 0x00000080L
++#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK 0x00000F00L
++#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID_MASK 0x000F0000L
++#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK 0x01000000L
++//MCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R
++#define MCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R__SHIFT 0x0
++#define MCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R_MASK 0x00001FFFL
++//MCIF_WB1_MCIF_WB_BUFMGR_STATUS
++#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT 0x0
++#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT 0x1
++#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT 0x2
++#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT 0x4
++#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT 0x7
++#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT 0x8
++#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT 0xc
++#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT 0x1c
++#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK 0x00000001L
++#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK 0x00000002L
++#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK 0x00000004L
++#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK 0x00000070L
++#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK 0x00000080L
++#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK 0x00000F00L
++#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK 0x01FFF000L
++#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK 0x70000000L
++//MCIF_WB1_MCIF_WB_BUF_PITCH
++#define MCIF_WB1_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT 0x8
++#define MCIF_WB1_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT 0x18
++#define MCIF_WB1_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK 0x0000FF00L
++#define MCIF_WB1_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK 0xFF000000L
++//MCIF_WB1_MCIF_WB_BUF_1_STATUS
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT 0x0
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT 0x1
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT 0x2
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT 0x3
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT 0x4
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT 0x5
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT 0x8
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT 0xc
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD__SHIFT 0xf
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT 0x10
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR__SHIFT 0x1d
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR__SHIFT 0x1e
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR__SHIFT 0x1f
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK 0x00000001L
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK 0x00000002L
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK 0x00000004L
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK 0x00000008L
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK 0x00000010L
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK 0x000000E0L
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK 0x00000F00L
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK 0x00007000L
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD_MASK 0x00008000L
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK 0x1FFF0000L
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR_MASK 0x20000000L
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR_MASK 0x40000000L
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR_MASK 0x80000000L
++//MCIF_WB1_MCIF_WB_BUF_1_STATUS2
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R__SHIFT 0x0
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT 0xd
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT 0xe
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT 0x11
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT 0x12
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R_MASK 0x00001FFFL
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK 0x00002000L
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK 0x00004000L
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK 0x00020000L
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK 0x00040000L
++//MCIF_WB1_MCIF_WB_BUF_2_STATUS
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT 0x0
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT 0x1
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT 0x2
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT 0x3
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT 0x4
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT 0x5
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT 0x8
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT 0xc
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD__SHIFT 0xf
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT 0x10
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR__SHIFT 0x1d
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR__SHIFT 0x1e
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR__SHIFT 0x1f
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK 0x00000001L
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK 0x00000002L
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK 0x00000004L
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK 0x00000008L
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK 0x00000010L
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK 0x000000E0L
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK 0x00000F00L
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK 0x00007000L
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD_MASK 0x00008000L
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK 0x1FFF0000L
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR_MASK 0x20000000L
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR_MASK 0x40000000L
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR_MASK 0x80000000L
++//MCIF_WB1_MCIF_WB_BUF_2_STATUS2
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R__SHIFT 0x0
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT 0xd
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT 0xe
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT 0x11
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT 0x12
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R_MASK 0x00001FFFL
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK 0x00002000L
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK 0x00004000L
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK 0x00020000L
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK 0x00040000L
++//MCIF_WB1_MCIF_WB_BUF_3_STATUS
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT 0x0
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT 0x1
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT 0x2
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT 0x3
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT 0x4
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT 0x5
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT 0x8
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT 0xc
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD__SHIFT 0xf
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT 0x10
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR__SHIFT 0x1d
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR__SHIFT 0x1e
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR__SHIFT 0x1f
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK 0x00000001L
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK 0x00000002L
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK 0x00000004L
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK 0x00000008L
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK 0x00000010L
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK 0x000000E0L
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK 0x00000F00L
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK 0x00007000L
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD_MASK 0x00008000L
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK 0x1FFF0000L
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR_MASK 0x20000000L
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR_MASK 0x40000000L
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR_MASK 0x80000000L
++//MCIF_WB1_MCIF_WB_BUF_3_STATUS2
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R__SHIFT 0x0
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT 0xd
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT 0xe
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT 0x11
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT 0x12
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R_MASK 0x00001FFFL
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK 0x00002000L
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK 0x00004000L
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK 0x00020000L
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK 0x00040000L
++//MCIF_WB1_MCIF_WB_BUF_4_STATUS
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT 0x0
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT 0x1
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT 0x2
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT 0x3
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT 0x4
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT 0x5
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT 0x8
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT 0xc
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD__SHIFT 0xf
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT 0x10
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR__SHIFT 0x1d
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR__SHIFT 0x1e
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR__SHIFT 0x1f
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK 0x00000001L
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK 0x00000002L
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK 0x00000004L
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK 0x00000008L
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK 0x00000010L
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK 0x000000E0L
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK 0x00000F00L
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK 0x00007000L
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD_MASK 0x00008000L
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK 0x1FFF0000L
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR_MASK 0x20000000L
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR_MASK 0x40000000L
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR_MASK 0x80000000L
++//MCIF_WB1_MCIF_WB_BUF_4_STATUS2
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R__SHIFT 0x0
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT 0xd
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT 0xe
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT 0x11
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT 0x12
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R_MASK 0x00001FFFL
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK 0x00002000L
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK 0x00004000L
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK 0x00020000L
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK 0x00040000L
++//MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL
++#define MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT 0x0
++#define MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT 0x16
++#define MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK 0x00000003L
++#define MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK 0xFFC00000L
++//MCIF_WB1_MCIF_WB_SCLK_CHANGE
++#define MCIF_WB1_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT 0x0
++#define MCIF_WB1_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK__SHIFT 0x1
++#define MCIF_WB1_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK 0x00000001L
++#define MCIF_WB1_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK_MASK 0x0000000EL
++//MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y
++#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT 0x0
++#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK 0xFFFFFFFFL
++//MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET
++#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET__SHIFT 0x0
++#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET_MASK 0x0003FFFFL
++//MCIF_WB1_MCIF_WB_BUF_1_ADDR_C
++#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT 0x0
++#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK 0xFFFFFFFFL
++//MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET
++#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET__SHIFT 0x0
++#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET_MASK 0x0003FFFFL
++//MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y
++#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT 0x0
++#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK 0xFFFFFFFFL
++//MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET
++#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET__SHIFT 0x0
++#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET_MASK 0x0003FFFFL
++//MCIF_WB1_MCIF_WB_BUF_2_ADDR_C
++#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT 0x0
++#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK 0xFFFFFFFFL
++//MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET
++#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET__SHIFT 0x0
++#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET_MASK 0x0003FFFFL
++//MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y
++#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT 0x0
++#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK 0xFFFFFFFFL
++//MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET
++#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET__SHIFT 0x0
++#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET_MASK 0x0003FFFFL
++//MCIF_WB1_MCIF_WB_BUF_3_ADDR_C
++#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT 0x0
++#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK 0xFFFFFFFFL
++//MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET
++#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET__SHIFT 0x0
++#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET_MASK 0x0003FFFFL
++//MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y
++#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT 0x0
++#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK 0xFFFFFFFFL
++//MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET
++#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET__SHIFT 0x0
++#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET_MASK 0x0003FFFFL
++//MCIF_WB1_MCIF_WB_BUF_4_ADDR_C
++#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT 0x0
++#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK 0xFFFFFFFFL
++//MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET
++#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET__SHIFT 0x0
++#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET_MASK 0x0003FFFFL
++//MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL
++#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT 0x0
++#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT 0x4
++#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT 0x5
++#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT 0x6
++#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT 0x8
++#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT 0x10
++#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK 0x00000001L
++#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK 0x00000010L
++#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK 0x00000020L
++#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK 0x00000040L
++#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK 0x00000F00L
++#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK 0x1FFF0000L
++//MCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK
++#define MCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT 0x0
++#define MCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK 0x0001FFFFL
++//MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL
++#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x0
++#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x1
++#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0x2
++#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x4
++#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000001L
++#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000002L
++#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000004L
++#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00000070L
++//MCIF_WB1_MCIF_WB_WATERMARK
++#define MCIF_WB1_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT 0x0
++#define MCIF_WB1_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK 0x0000FFFFL
++//MCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL
++#define MCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT 0x0
++#define MCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK 0x00000001L
++//MCIF_WB1_MCIF_WB_WARM_UP_CNTL
++#define MCIF_WB1_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP__SHIFT 0x8
++#define MCIF_WB1_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP_MASK 0x0000FF00L
++//MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL
++#define MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ__SHIFT 0x0
++#define MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT 0x1
++#define MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ_MASK 0x00000001L
++#define MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK 0x00000002L
++//MCIF_WB1_MULTI_LEVEL_QOS_CTRL
++#define MCIF_WB1_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT 0x0
++#define MCIF_WB1_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK 0x003FFFFFL
++//MCIF_WB1_MCIF_WB_BUF_LUMA_SIZE
++#define MCIF_WB1_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT 0x0
++#define MCIF_WB1_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK 0x000FFFFFL
++//MCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE
++#define MCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT 0x0
++#define MCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK 0x000FFFFFL
++
++
++// addressBlock: dce_dc_mcif_wb2_dispdec
++//MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL
++#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT 0x0
++#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ__SHIFT 0x1
++#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT 0x4
++#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT 0x5
++#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6
++#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT 0x7
++#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT 0x8
++#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID__SHIFT 0x10
++#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT 0x18
++#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK 0x00000001L
++#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ_MASK 0x00000002L
++#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK 0x00000010L
++#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK 0x00000020L
++#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK 0x00000040L
++#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK 0x00000080L
++#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK 0x00000F00L
++#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID_MASK 0x000F0000L
++#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK 0x01000000L
++//MCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R
++#define MCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R__SHIFT 0x0
++#define MCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R_MASK 0x00001FFFL
++//MCIF_WB2_MCIF_WB_BUFMGR_STATUS
++#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT 0x0
++#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT 0x1
++#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT 0x2
++#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT 0x4
++#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT 0x7
++#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT 0x8
++#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT 0xc
++#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT 0x1c
++#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK 0x00000001L
++#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK 0x00000002L
++#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK 0x00000004L
++#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK 0x00000070L
++#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK 0x00000080L
++#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK 0x00000F00L
++#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK 0x01FFF000L
++#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK 0x70000000L
++//MCIF_WB2_MCIF_WB_BUF_PITCH
++#define MCIF_WB2_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT 0x8
++#define MCIF_WB2_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT 0x18
++#define MCIF_WB2_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK 0x0000FF00L
++#define MCIF_WB2_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK 0xFF000000L
++//MCIF_WB2_MCIF_WB_BUF_1_STATUS
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT 0x0
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT 0x1
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT 0x2
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT 0x3
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT 0x4
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT 0x5
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT 0x8
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT 0xc
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD__SHIFT 0xf
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT 0x10
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR__SHIFT 0x1d
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR__SHIFT 0x1e
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR__SHIFT 0x1f
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK 0x00000001L
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK 0x00000002L
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK 0x00000004L
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK 0x00000008L
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK 0x00000010L
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK 0x000000E0L
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK 0x00000F00L
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK 0x00007000L
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD_MASK 0x00008000L
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK 0x1FFF0000L
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR_MASK 0x20000000L
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR_MASK 0x40000000L
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR_MASK 0x80000000L
++//MCIF_WB2_MCIF_WB_BUF_1_STATUS2
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R__SHIFT 0x0
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT 0xd
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT 0xe
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT 0x11
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT 0x12
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R_MASK 0x00001FFFL
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK 0x00002000L
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK 0x00004000L
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK 0x00020000L
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK 0x00040000L
++//MCIF_WB2_MCIF_WB_BUF_2_STATUS
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT 0x0
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT 0x1
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT 0x2
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT 0x3
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT 0x4
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT 0x5
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT 0x8
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT 0xc
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD__SHIFT 0xf
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT 0x10
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR__SHIFT 0x1d
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR__SHIFT 0x1e
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR__SHIFT 0x1f
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK 0x00000001L
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK 0x00000002L
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK 0x00000004L
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK 0x00000008L
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK 0x00000010L
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK 0x000000E0L
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK 0x00000F00L
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK 0x00007000L
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD_MASK 0x00008000L
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK 0x1FFF0000L
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR_MASK 0x20000000L
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR_MASK 0x40000000L
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR_MASK 0x80000000L
++//MCIF_WB2_MCIF_WB_BUF_2_STATUS2
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R__SHIFT 0x0
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT 0xd
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT 0xe
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT 0x11
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT 0x12
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R_MASK 0x00001FFFL
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK 0x00002000L
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK 0x00004000L
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK 0x00020000L
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK 0x00040000L
++//MCIF_WB2_MCIF_WB_BUF_3_STATUS
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT 0x0
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT 0x1
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT 0x2
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT 0x3
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT 0x4
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT 0x5
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT 0x8
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT 0xc
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD__SHIFT 0xf
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT 0x10
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR__SHIFT 0x1d
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR__SHIFT 0x1e
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR__SHIFT 0x1f
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK 0x00000001L
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK 0x00000002L
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK 0x00000004L
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK 0x00000008L
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK 0x00000010L
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK 0x000000E0L
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK 0x00000F00L
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK 0x00007000L
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD_MASK 0x00008000L
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK 0x1FFF0000L
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR_MASK 0x20000000L
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR_MASK 0x40000000L
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR_MASK 0x80000000L
++//MCIF_WB2_MCIF_WB_BUF_3_STATUS2
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R__SHIFT 0x0
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT 0xd
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT 0xe
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT 0x11
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT 0x12
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R_MASK 0x00001FFFL
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK 0x00002000L
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK 0x00004000L
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK 0x00020000L
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK 0x00040000L
++//MCIF_WB2_MCIF_WB_BUF_4_STATUS
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT 0x0
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT 0x1
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT 0x2
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT 0x3
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT 0x4
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT 0x5
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT 0x8
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT 0xc
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD__SHIFT 0xf
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT 0x10
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR__SHIFT 0x1d
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR__SHIFT 0x1e
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR__SHIFT 0x1f
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK 0x00000001L
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK 0x00000002L
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK 0x00000004L
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK 0x00000008L
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK 0x00000010L
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK 0x000000E0L
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK 0x00000F00L
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK 0x00007000L
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD_MASK 0x00008000L
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK 0x1FFF0000L
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR_MASK 0x20000000L
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR_MASK 0x40000000L
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR_MASK 0x80000000L
++//MCIF_WB2_MCIF_WB_BUF_4_STATUS2
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R__SHIFT 0x0
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT 0xd
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT 0xe
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT 0x11
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT 0x12
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R_MASK 0x00001FFFL
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK 0x00002000L
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK 0x00004000L
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK 0x00020000L
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK 0x00040000L
++//MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL
++#define MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT 0x0
++#define MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT 0x16
++#define MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK 0x00000003L
++#define MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK 0xFFC00000L
++//MCIF_WB2_MCIF_WB_SCLK_CHANGE
++#define MCIF_WB2_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT 0x0
++#define MCIF_WB2_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK__SHIFT 0x1
++#define MCIF_WB2_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK 0x00000001L
++#define MCIF_WB2_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK_MASK 0x0000000EL
++//MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y
++#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT 0x0
++#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK 0xFFFFFFFFL
++//MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET
++#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET__SHIFT 0x0
++#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET_MASK 0x0003FFFFL
++//MCIF_WB2_MCIF_WB_BUF_1_ADDR_C
++#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT 0x0
++#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK 0xFFFFFFFFL
++//MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET
++#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET__SHIFT 0x0
++#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET_MASK 0x0003FFFFL
++//MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y
++#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT 0x0
++#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK 0xFFFFFFFFL
++//MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET
++#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET__SHIFT 0x0
++#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET_MASK 0x0003FFFFL
++//MCIF_WB2_MCIF_WB_BUF_2_ADDR_C
++#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT 0x0
++#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK 0xFFFFFFFFL
++//MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET
++#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET__SHIFT 0x0
++#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET_MASK 0x0003FFFFL
++//MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y
++#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT 0x0
++#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK 0xFFFFFFFFL
++//MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET
++#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET__SHIFT 0x0
++#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET_MASK 0x0003FFFFL
++//MCIF_WB2_MCIF_WB_BUF_3_ADDR_C
++#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT 0x0
++#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK 0xFFFFFFFFL
++//MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET
++#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET__SHIFT 0x0
++#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET_MASK 0x0003FFFFL
++//MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y
++#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT 0x0
++#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK 0xFFFFFFFFL
++//MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET
++#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET__SHIFT 0x0
++#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET_MASK 0x0003FFFFL
++//MCIF_WB2_MCIF_WB_BUF_4_ADDR_C
++#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT 0x0
++#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK 0xFFFFFFFFL
++//MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET
++#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET__SHIFT 0x0
++#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET_MASK 0x0003FFFFL
++//MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL
++#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT 0x0
++#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT 0x4
++#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT 0x5
++#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT 0x6
++#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT 0x8
++#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT 0x10
++#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK 0x00000001L
++#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK 0x00000010L
++#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK 0x00000020L
++#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK 0x00000040L
++#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK 0x00000F00L
++#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK 0x1FFF0000L
++//MCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK
++#define MCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT 0x0
++#define MCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK 0x0001FFFFL
++//MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL
++#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x0
++#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x1
++#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0x2
++#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x4
++#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000001L
++#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000002L
++#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000004L
++#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00000070L
++//MCIF_WB2_MCIF_WB_WATERMARK
++#define MCIF_WB2_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT 0x0
++#define MCIF_WB2_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK 0x0000FFFFL
++//MCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL
++#define MCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT 0x0
++#define MCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK 0x00000001L
++//MCIF_WB2_MCIF_WB_WARM_UP_CNTL
++#define MCIF_WB2_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP__SHIFT 0x8
++#define MCIF_WB2_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP_MASK 0x0000FF00L
++//MCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL
++#define MCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ__SHIFT 0x0
++#define MCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT 0x1
++#define MCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ_MASK 0x00000001L
++#define MCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK 0x00000002L
++//MCIF_WB2_MULTI_LEVEL_QOS_CTRL
++#define MCIF_WB2_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT 0x0
++#define MCIF_WB2_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK 0x003FFFFFL
++//MCIF_WB2_MCIF_WB_BUF_LUMA_SIZE
++#define MCIF_WB2_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT 0x0
++#define MCIF_WB2_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK 0x000FFFFFL
++//MCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE
++#define MCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT 0x0
++#define MCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK 0x000FFFFFL
++
++
++// addressBlock: dce_dc_cwb0_dispdec
++//CWB0_CWB_CTRL
++#define CWB0_CWB_CTRL__CWB_EN__SHIFT 0x0
++#define CWB0_CWB_CTRL__CWB_OUTPUT_COLOR_DEPTH__SHIFT 0x2
++#define CWB0_CWB_CTRL__CWB_ZERO_PADDING_MODE__SHIFT 0x4
++#define CWB0_CWB_CTRL__CWB_CB_CR_SWAP__SHIFT 0x6
++#define CWB0_CWB_CTRL__CWB_422MODE_LUMA_CHROMA_SWAP__SHIFT 0x7
++#define CWB0_CWB_CTRL__CWB_444MODE_ROUNDING_EN__SHIFT 0x8
++#define CWB0_CWB_CTRL__CWB_PACK_FMT_SEL__SHIFT 0xa
++#define CWB0_CWB_CTRL__CWB_EN_MASK 0x00000001L
++#define CWB0_CWB_CTRL__CWB_OUTPUT_COLOR_DEPTH_MASK 0x0000000CL
++#define CWB0_CWB_CTRL__CWB_ZERO_PADDING_MODE_MASK 0x00000010L
++#define CWB0_CWB_CTRL__CWB_CB_CR_SWAP_MASK 0x00000040L
++#define CWB0_CWB_CTRL__CWB_422MODE_LUMA_CHROMA_SWAP_MASK 0x00000080L
++#define CWB0_CWB_CTRL__CWB_444MODE_ROUNDING_EN_MASK 0x00000100L
++#define CWB0_CWB_CTRL__CWB_PACK_FMT_SEL_MASK 0x00000400L
++//CWB0_CWB_FENCE_PAR0
++#define CWB0_CWB_FENCE_PAR0__CWB_OUTPUT_LINE_WIDTH__SHIFT 0x0
++#define CWB0_CWB_FENCE_PAR0__CWB_ERROR_LINE_WIDTH__SHIFT 0x10
++#define CWB0_CWB_FENCE_PAR0__CWB_OUTPUT_LINE_WIDTH_MASK 0x00001FFFL
++#define CWB0_CWB_FENCE_PAR0__CWB_ERROR_LINE_WIDTH_MASK 0x1FFF0000L
++//CWB0_CWB_FENCE_PAR1
++#define CWB0_CWB_FENCE_PAR1__CWB_OUTPUT_LINES_PER_FRAME__SHIFT 0x0
++#define CWB0_CWB_FENCE_PAR1__CWB_EOF_TO_SOF_SPACING__SHIFT 0x10
++#define CWB0_CWB_FENCE_PAR1__CWB_OUTPUT_LINES_PER_FRAME_MASK 0x00001FFFL
++#define CWB0_CWB_FENCE_PAR1__CWB_EOF_TO_SOF_SPACING_MASK 0x003F0000L
++//CWB0_CWB_CRC_CTRL
++#define CWB0_CWB_CRC_CTRL__CWB_CRC_EN__SHIFT 0x0
++#define CWB0_CWB_CRC_CTRL__CWB_CRC_CONT_EN__SHIFT 0x2
++#define CWB0_CWB_CRC_CTRL__CWB_CRC_SRC_SEL__SHIFT 0x6
++#define CWB0_CWB_CRC_CTRL__CWB_CRC_EN_MASK 0x00000001L
++#define CWB0_CWB_CRC_CTRL__CWB_CRC_CONT_EN_MASK 0x00000004L
++#define CWB0_CWB_CRC_CTRL__CWB_CRC_SRC_SEL_MASK 0x00000040L
++//CWB0_CWB_CRC_RED_GREEN_MASK
++#define CWB0_CWB_CRC_RED_GREEN_MASK__CWB_CRC_RED_MASK__SHIFT 0x0
++#define CWB0_CWB_CRC_RED_GREEN_MASK__CWB_CRC_GREEN_MASK__SHIFT 0x10
++#define CWB0_CWB_CRC_RED_GREEN_MASK__CWB_CRC_RED_MASK_MASK 0x0000FFFFL
++#define CWB0_CWB_CRC_RED_GREEN_MASK__CWB_CRC_GREEN_MASK_MASK 0xFFFF0000L
++//CWB0_CWB_CRC_BLUE_MASK
++#define CWB0_CWB_CRC_BLUE_MASK__CWB_CRC_BLUE_MASK__SHIFT 0x0
++#define CWB0_CWB_CRC_BLUE_MASK__CWB_CRC_BLUE_MASK_MASK 0x0000FFFFL
++//CWB0_CWB_CRC_RED_GREEN_RESULT
++#define CWB0_CWB_CRC_RED_GREEN_RESULT__CWB_CRC_RED_RESULT__SHIFT 0x0
++#define CWB0_CWB_CRC_RED_GREEN_RESULT__CWB_CRC_GREEN_RESULT__SHIFT 0x10
++#define CWB0_CWB_CRC_RED_GREEN_RESULT__CWB_CRC_RED_RESULT_MASK 0x0000FFFFL
++#define CWB0_CWB_CRC_RED_GREEN_RESULT__CWB_CRC_GREEN_RESULT_MASK 0xFFFF0000L
++//CWB0_CWB_CRC_BLUE_RESULT
++#define CWB0_CWB_CRC_BLUE_RESULT__CWB_CRC_BLUE_RESULT__SHIFT 0x0
++#define CWB0_CWB_CRC_BLUE_RESULT__CWB_CRC_COUNT__SHIFT 0x10
++#define CWB0_CWB_CRC_BLUE_RESULT__CWB_CRC_BLUE_RESULT_MASK 0x0000FFFFL
++#define CWB0_CWB_CRC_BLUE_RESULT__CWB_CRC_COUNT_MASK 0x000F0000L
++
++
++// addressBlock: dce_dc_cwb1_dispdec
++//CWB1_CWB_CTRL
++#define CWB1_CWB_CTRL__CWB_EN__SHIFT 0x0
++#define CWB1_CWB_CTRL__CWB_OUTPUT_COLOR_DEPTH__SHIFT 0x2
++#define CWB1_CWB_CTRL__CWB_ZERO_PADDING_MODE__SHIFT 0x4
++#define CWB1_CWB_CTRL__CWB_CB_CR_SWAP__SHIFT 0x6
++#define CWB1_CWB_CTRL__CWB_422MODE_LUMA_CHROMA_SWAP__SHIFT 0x7
++#define CWB1_CWB_CTRL__CWB_444MODE_ROUNDING_EN__SHIFT 0x8
++#define CWB1_CWB_CTRL__CWB_PACK_FMT_SEL__SHIFT 0xa
++#define CWB1_CWB_CTRL__CWB_EN_MASK 0x00000001L
++#define CWB1_CWB_CTRL__CWB_OUTPUT_COLOR_DEPTH_MASK 0x0000000CL
++#define CWB1_CWB_CTRL__CWB_ZERO_PADDING_MODE_MASK 0x00000010L
++#define CWB1_CWB_CTRL__CWB_CB_CR_SWAP_MASK 0x00000040L
++#define CWB1_CWB_CTRL__CWB_422MODE_LUMA_CHROMA_SWAP_MASK 0x00000080L
++#define CWB1_CWB_CTRL__CWB_444MODE_ROUNDING_EN_MASK 0x00000100L
++#define CWB1_CWB_CTRL__CWB_PACK_FMT_SEL_MASK 0x00000400L
++//CWB1_CWB_FENCE_PAR0
++#define CWB1_CWB_FENCE_PAR0__CWB_OUTPUT_LINE_WIDTH__SHIFT 0x0
++#define CWB1_CWB_FENCE_PAR0__CWB_ERROR_LINE_WIDTH__SHIFT 0x10
++#define CWB1_CWB_FENCE_PAR0__CWB_OUTPUT_LINE_WIDTH_MASK 0x00001FFFL
++#define CWB1_CWB_FENCE_PAR0__CWB_ERROR_LINE_WIDTH_MASK 0x1FFF0000L
++//CWB1_CWB_FENCE_PAR1
++#define CWB1_CWB_FENCE_PAR1__CWB_OUTPUT_LINES_PER_FRAME__SHIFT 0x0
++#define CWB1_CWB_FENCE_PAR1__CWB_EOF_TO_SOF_SPACING__SHIFT 0x10
++#define CWB1_CWB_FENCE_PAR1__CWB_OUTPUT_LINES_PER_FRAME_MASK 0x00001FFFL
++#define CWB1_CWB_FENCE_PAR1__CWB_EOF_TO_SOF_SPACING_MASK 0x003F0000L
++//CWB1_CWB_CRC_CTRL
++#define CWB1_CWB_CRC_CTRL__CWB_CRC_EN__SHIFT 0x0
++#define CWB1_CWB_CRC_CTRL__CWB_CRC_CONT_EN__SHIFT 0x2
++#define CWB1_CWB_CRC_CTRL__CWB_CRC_SRC_SEL__SHIFT 0x6
++#define CWB1_CWB_CRC_CTRL__CWB_CRC_EN_MASK 0x00000001L
++#define CWB1_CWB_CRC_CTRL__CWB_CRC_CONT_EN_MASK 0x00000004L
++#define CWB1_CWB_CRC_CTRL__CWB_CRC_SRC_SEL_MASK 0x00000040L
++//CWB1_CWB_CRC_RED_GREEN_MASK
++#define CWB1_CWB_CRC_RED_GREEN_MASK__CWB_CRC_RED_MASK__SHIFT 0x0
++#define CWB1_CWB_CRC_RED_GREEN_MASK__CWB_CRC_GREEN_MASK__SHIFT 0x10
++#define CWB1_CWB_CRC_RED_GREEN_MASK__CWB_CRC_RED_MASK_MASK 0x0000FFFFL
++#define CWB1_CWB_CRC_RED_GREEN_MASK__CWB_CRC_GREEN_MASK_MASK 0xFFFF0000L
++//CWB1_CWB_CRC_BLUE_MASK
++#define CWB1_CWB_CRC_BLUE_MASK__CWB_CRC_BLUE_MASK__SHIFT 0x0
++#define CWB1_CWB_CRC_BLUE_MASK__CWB_CRC_BLUE_MASK_MASK 0x0000FFFFL
++//CWB1_CWB_CRC_RED_GREEN_RESULT
++#define CWB1_CWB_CRC_RED_GREEN_RESULT__CWB_CRC_RED_RESULT__SHIFT 0x0
++#define CWB1_CWB_CRC_RED_GREEN_RESULT__CWB_CRC_GREEN_RESULT__SHIFT 0x10
++#define CWB1_CWB_CRC_RED_GREEN_RESULT__CWB_CRC_RED_RESULT_MASK 0x0000FFFFL
++#define CWB1_CWB_CRC_RED_GREEN_RESULT__CWB_CRC_GREEN_RESULT_MASK 0xFFFF0000L
++//CWB1_CWB_CRC_BLUE_RESULT
++#define CWB1_CWB_CRC_BLUE_RESULT__CWB_CRC_BLUE_RESULT__SHIFT 0x0
++#define CWB1_CWB_CRC_BLUE_RESULT__CWB_CRC_COUNT__SHIFT 0x10
++#define CWB1_CWB_CRC_BLUE_RESULT__CWB_CRC_BLUE_RESULT_MASK 0x0000FFFFL
++#define CWB1_CWB_CRC_BLUE_RESULT__CWB_CRC_COUNT_MASK 0x000F0000L
++
++
++// addressBlock: dce_dc_dc_perfmon9_dispdec
++//DC_PERFMON9_PERFCOUNTER_CNTL
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
++//DC_PERFMON9_PERFCOUNTER_CNTL2
++#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
++#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
++#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
++#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
++#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
++#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
++#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
++#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
++//DC_PERFMON9_PERFCOUNTER_STATE
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
++//DC_PERFMON9_PERFMON_CNTL
++#define DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
++#define DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
++#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
++#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
++#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
++#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
++#define DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
++#define DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
++#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
++#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
++#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
++#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
++//DC_PERFMON9_PERFMON_CNTL2
++#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
++#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
++#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
++#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
++#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
++#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
++#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
++#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
++//DC_PERFMON9_PERFMON_CVALUE_INT_MISC
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
++//DC_PERFMON9_PERFMON_CVALUE_LOW
++#define DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
++#define DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
++//DC_PERFMON9_PERFMON_HI
++#define DC_PERFMON9_PERFMON_HI__PERFMON_HI__SHIFT 0x0
++#define DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
++#define DC_PERFMON9_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
++#define DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
++//DC_PERFMON9_PERFMON_LOW
++#define DC_PERFMON9_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
++#define DC_PERFMON9_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dispdec
++//VGA_MEM_WRITE_PAGE_ADDR
++#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0
++#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10
++#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x000003FFL
++#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x03FF0000L
++//VGA_MEM_READ_PAGE_ADDR
++#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0
++#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10
++#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x000003FFL
++#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x03FF0000L
++//VGA_RENDER_CONTROL
++#define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0
++#define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5
++#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT 0x7
++#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT 0x8
++#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT 0x10
++#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT 0x18
++#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT 0x19
++#define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK 0x0000001FL
++#define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK 0x00000060L
++#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK 0x00000080L
++#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK 0x00000100L
++#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK 0x00030000L
++#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK 0x01000000L
++#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK 0x02000000L
++//VGA_SEQUENCER_RESET_CONTROL
++#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x0
++#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x1
++#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x2
++#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x3
++#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x4
++#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x5
++#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x8
++#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x9
++#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xa
++#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xb
++#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xc
++#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xd
++#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT 0x10
++#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT 0x11
++#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT 0x12
++#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000001L
++#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000002L
++#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000004L
++#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000008L
++#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000010L
++#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000020L
++#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000100L
++#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000200L
++#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000400L
++#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000800L
++#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00001000L
++#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00002000L
++#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK 0x00010000L
++#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK 0x00020000L
++#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK 0x00FC0000L
++//VGA_MODE_CONTROL
++#define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT 0x0
++#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT 0x4
++#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT 0x8
++#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT 0x10
++#define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT__SHIFT 0x18
++#define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK 0x00000001L
++#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK 0x00000030L
++#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK 0x00000100L
++#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK 0x00010000L
++#define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT_MASK 0x01000000L
++//VGA_SURFACE_PITCH_SELECT
++#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT 0x0
++#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT 0x8
++#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK 0x00000003L
++#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK 0x00000300L
++//VGA_MEMORY_BASE_ADDRESS
++#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT 0x0
++#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK 0xFFFFFFFFL
++//VGA_DISPBUF1_SURFACE_ADDR
++#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT 0x0
++#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK 0x01FFFFFFL
++//VGA_DISPBUF2_SURFACE_ADDR
++#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT 0x0
++#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK 0x01FFFFFFL
++//VGA_MEMORY_BASE_ADDRESS_HIGH
++#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT 0x0
++#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK 0x000000FFL
++//VGA_HDP_CONTROL
++#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT 0x0
++#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT 0x4
++#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT 0x8
++#define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT 0x10
++#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 0x18
++#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK 0x00000001L
++#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK 0x00000010L
++#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK 0x00000100L
++#define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK 0x00010000L
++#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK 0x01000000L
++//VGA_CACHE_CONTROL
++#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT 0x0
++#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT 0x8
++#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT 0x10
++#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT 0x14
++#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT 0x18
++#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK 0x00000001L
++#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK 0x00000100L
++#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK 0x00010000L
++#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK 0x00100000L
++#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK 0x3F000000L
++//D1VGA_CONTROL
++#define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT 0x0
++#define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT 0x8
++#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
++#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
++#define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT 0x18
++#define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK 0x00000001L
++#define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK 0x00000100L
++#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L
++#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L
++#define D1VGA_CONTROL__D1VGA_ROTATE_MASK 0x03000000L
++//D2VGA_CONTROL
++#define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT 0x0
++#define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT 0x8
++#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
++#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
++#define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT 0x18
++#define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK 0x00000001L
++#define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x00000100L
++#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L
++#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L
++#define D2VGA_CONTROL__D2VGA_ROTATE_MASK 0x03000000L
++//VGA_STATUS
++#define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT 0x0
++#define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT 0x1
++#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT 0x2
++#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT 0x3
++#define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK 0x00000001L
++#define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK 0x00000002L
++#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK 0x00000004L
++#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK 0x00000008L
++//VGA_INTERRUPT_CONTROL
++#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT 0x0
++#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT 0x8
++#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT 0x10
++#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT 0x18
++#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK 0x00000001L
++#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK 0x00000100L
++#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK 0x00010000L
++#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK 0x01000000L
++//VGA_STATUS_CLEAR
++#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT 0x0
++#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT 0x8
++#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT 0x10
++#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT 0x18
++#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK 0x00000001L
++#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK 0x00000100L
++#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK 0x00010000L
++#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK 0x01000000L
++//VGA_INTERRUPT_STATUS
++#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT 0x0
++#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT 0x1
++#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT 0x2
++#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT 0x3
++#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK 0x00000001L
++#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK 0x00000002L
++#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK 0x00000004L
++#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK 0x00000008L
++//VGA_MAIN_CONTROL
++#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT 0x0
++#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT 0x3
++#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT 0x5
++#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT 0x8
++#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY__SHIFT 0xc
++#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT 0x10
++#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT 0x18
++#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT 0x1a
++#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT 0x1d
++#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT 0x1f
++#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK 0x00000003L
++#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK 0x00000018L
++#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK 0x000000E0L
++#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK 0x00000300L
++#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY_MASK 0x0000F000L
++#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK 0x00030000L
++#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK 0x03000000L
++#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK 0x04000000L
++#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK 0x20000000L
++#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK 0x80000000L
++//VGA_TEST_CONTROL
++#define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT 0x0
++#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT 0x8
++#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT 0x10
++#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT 0x18
++#define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK 0x00000001L
++#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK 0x00000100L
++#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK 0x00010000L
++#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK 0x01000000L
++//VGA_QOS_CTRL
++#define VGA_QOS_CTRL__VGA_READ_QOS__SHIFT 0x0
++#define VGA_QOS_CTRL__VGA_WRITE_QOS__SHIFT 0x4
++#define VGA_QOS_CTRL__VGA_READ_QOS_MASK 0x0000000FL
++#define VGA_QOS_CTRL__VGA_WRITE_QOS_MASK 0x000000F0L
++//CRTC8_IDX
++#define CRTC8_IDX__VCRTC_IDX__SHIFT 0x0
++#define CRTC8_IDX__VCRTC_IDX_MASK 0x3FL
++//CRTC8_DATA
++#define CRTC8_DATA__VCRTC_DATA__SHIFT 0x0
++#define CRTC8_DATA__VCRTC_DATA_MASK 0xFFL
++//GENFC_WT
++#define GENFC_WT__VSYNC_SEL_W__SHIFT 0x3
++#define GENFC_WT__VSYNC_SEL_W_MASK 0x08L
++//GENS1
++#define GENS1__NO_DISPLAY__SHIFT 0x0
++#define GENS1__VGA_VSTATUS__SHIFT 0x3
++#define GENS1__PIXEL_READ_BACK__SHIFT 0x4
++#define GENS1__NO_DISPLAY_MASK 0x01L
++#define GENS1__VGA_VSTATUS_MASK 0x08L
++#define GENS1__PIXEL_READ_BACK_MASK 0x30L
++//ATTRDW
++#define ATTRDW__ATTR_DATA__SHIFT 0x0
++#define ATTRDW__ATTR_DATA_MASK 0xFFL
++//ATTRX
++#define ATTRX__ATTR_IDX__SHIFT 0x0
++#define ATTRX__ATTR_PAL_RW_ENB__SHIFT 0x5
++#define ATTRX__ATTR_IDX_MASK 0x1FL
++#define ATTRX__ATTR_PAL_RW_ENB_MASK 0x20L
++//ATTRDR
++#define ATTRDR__ATTR_DATA__SHIFT 0x0
++#define ATTRDR__ATTR_DATA_MASK 0xFFL
++//GENMO_WT
++#define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT 0x0
++#define GENMO_WT__VGA_RAM_EN__SHIFT 0x1
++#define GENMO_WT__VGA_CKSEL__SHIFT 0x2
++#define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT 0x5
++#define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x6
++#define GENMO_WT__VGA_VSYNC_POL__SHIFT 0x7
++#define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK 0x01L
++#define GENMO_WT__VGA_RAM_EN_MASK 0x02L
++#define GENMO_WT__VGA_CKSEL_MASK 0x0CL
++#define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK 0x20L
++#define GENMO_WT__VGA_HSYNC_POL_MASK 0x40L
++#define GENMO_WT__VGA_VSYNC_POL_MASK 0x80L
++//GENS0
++#define GENS0__SENSE_SWITCH__SHIFT 0x4
++#define GENS0__CRT_INTR__SHIFT 0x7
++#define GENS0__SENSE_SWITCH_MASK 0x10L
++#define GENS0__CRT_INTR_MASK 0x80L
++//GENENB
++#define GENENB__BLK_IO_BASE__SHIFT 0x0
++#define GENENB__BLK_IO_BASE_MASK 0xFFL
++//SEQ8_IDX
++#define SEQ8_IDX__SEQ_IDX__SHIFT 0x0
++#define SEQ8_IDX__SEQ_IDX_MASK 0x07L
++//SEQ8_DATA
++#define SEQ8_DATA__SEQ_DATA__SHIFT 0x0
++#define SEQ8_DATA__SEQ_DATA_MASK 0xFFL
++//DAC_MASK
++#define DAC_MASK__DAC_MASK__SHIFT 0x0
++#define DAC_MASK__DAC_MASK_MASK 0xFFL
++//DAC_R_INDEX
++#define DAC_R_INDEX__DAC_R_INDEX__SHIFT 0x0
++#define DAC_R_INDEX__DAC_R_INDEX_MASK 0xFFL
++//DAC_W_INDEX
++#define DAC_W_INDEX__DAC_W_INDEX__SHIFT 0x0
++#define DAC_W_INDEX__DAC_W_INDEX_MASK 0xFFL
++//DAC_DATA
++#define DAC_DATA__DAC_DATA__SHIFT 0x0
++#define DAC_DATA__DAC_DATA_MASK 0x3FL
++//GENFC_RD
++#define GENFC_RD__VSYNC_SEL_R__SHIFT 0x3
++#define GENFC_RD__VSYNC_SEL_R_MASK 0x08L
++//GENMO_RD
++#define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT 0x0
++#define GENMO_RD__VGA_RAM_EN__SHIFT 0x1
++#define GENMO_RD__VGA_CKSEL__SHIFT 0x2
++#define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT 0x5
++#define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x6
++#define GENMO_RD__VGA_VSYNC_POL__SHIFT 0x7
++#define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK 0x01L
++#define GENMO_RD__VGA_RAM_EN_MASK 0x02L
++#define GENMO_RD__VGA_CKSEL_MASK 0x0CL
++#define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK 0x20L
++#define GENMO_RD__VGA_HSYNC_POL_MASK 0x40L
++#define GENMO_RD__VGA_VSYNC_POL_MASK 0x80L
++//GRPH8_IDX
++#define GRPH8_IDX__GRPH_IDX__SHIFT 0x0
++#define GRPH8_IDX__GRPH_IDX_MASK 0x0FL
++//GRPH8_DATA
++#define GRPH8_DATA__GRPH_DATA__SHIFT 0x0
++#define GRPH8_DATA__GRPH_DATA_MASK 0xFFL
++//CRTC8_IDX_1
++#define CRTC8_IDX_1__VCRTC_IDX__SHIFT 0x0
++#define CRTC8_IDX_1__VCRTC_IDX_MASK 0x3FL
++//CRTC8_DATA_1
++#define CRTC8_DATA_1__VCRTC_DATA__SHIFT 0x0
++#define CRTC8_DATA_1__VCRTC_DATA_MASK 0xFFL
++//GENFC_WT_1
++#define GENFC_WT_1__VSYNC_SEL_W__SHIFT 0x3
++#define GENFC_WT_1__VSYNC_SEL_W_MASK 0x08L
++//GENS1_1
++#define GENS1_1__NO_DISPLAY__SHIFT 0x0
++#define GENS1_1__VGA_VSTATUS__SHIFT 0x3
++#define GENS1_1__PIXEL_READ_BACK__SHIFT 0x4
++#define GENS1_1__NO_DISPLAY_MASK 0x01L
++#define GENS1_1__VGA_VSTATUS_MASK 0x08L
++#define GENS1_1__PIXEL_READ_BACK_MASK 0x30L
++//D3VGA_CONTROL
++#define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT 0x0
++#define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT 0x8
++#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
++#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
++#define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT 0x18
++#define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK 0x00000001L
++#define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK 0x00000100L
++#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L
++#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L
++#define D3VGA_CONTROL__D3VGA_ROTATE_MASK 0x03000000L
++//D4VGA_CONTROL
++#define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT 0x0
++#define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT 0x8
++#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
++#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
++#define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT 0x18
++#define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK 0x00000001L
++#define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK 0x00000100L
++#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L
++#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L
++#define D4VGA_CONTROL__D4VGA_ROTATE_MASK 0x03000000L
++//D5VGA_CONTROL
++#define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT 0x0
++#define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT 0x8
++#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
++#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
++#define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT 0x18
++#define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK 0x00000001L
++#define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK 0x00000100L
++#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L
++#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L
++#define D5VGA_CONTROL__D5VGA_ROTATE_MASK 0x03000000L
++//D6VGA_CONTROL
++#define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT 0x0
++#define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT 0x8
++#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
++#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
++#define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT 0x18
++#define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK 0x00000001L
++#define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK 0x00000100L
++#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L
++#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L
++#define D6VGA_CONTROL__D6VGA_ROTATE_MASK 0x03000000L
++//VGA_SOURCE_SELECT
++#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT 0x0
++#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT 0x8
++#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK 0x00000007L
++#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK 0x00000700L
++//PHYPLLA_PIXCLK_RESYNC_CNTL
++#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
++#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
++#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE__SHIFT 0x8
++#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
++#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
++#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
++#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE_MASK 0x00000100L
++#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
++//PHYPLLB_PIXCLK_RESYNC_CNTL
++#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
++#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
++#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE__SHIFT 0x8
++#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
++#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
++#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
++#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK 0x00000100L
++#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
++//PHYPLLC_PIXCLK_RESYNC_CNTL
++#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
++#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
++#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE__SHIFT 0x8
++#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
++#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
++#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
++#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE_MASK 0x00000100L
++#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
++//PHYPLLD_PIXCLK_RESYNC_CNTL
++#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
++#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
++#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE__SHIFT 0x8
++#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
++#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
++#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
++#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE_MASK 0x00000100L
++#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
++//DCFEV0_CRTC_PIXEL_RATE_CNTL
++#define DCFEV0_CRTC_PIXEL_RATE_CNTL__DCFEV0_CRTC_PIXEL_RATE_SOURCE__SHIFT 0x0
++#define DCFEV0_CRTC_PIXEL_RATE_CNTL__DCFEV0_CRTC_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x8
++#define DCFEV0_CRTC_PIXEL_RATE_CNTL__DCFEV0_CRTC_PIXEL_RATE_PLL_SOURCE__SHIFT 0xf
++#define DCFEV0_CRTC_PIXEL_RATE_CNTL__DCFEV0_CRTC_PIXEL_RATE_SOURCE_MASK 0x00000003L
++#define DCFEV0_CRTC_PIXEL_RATE_CNTL__DCFEV0_CRTC_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000700L
++#define DCFEV0_CRTC_PIXEL_RATE_CNTL__DCFEV0_CRTC_PIXEL_RATE_PLL_SOURCE_MASK 0x00008000L
++//DCFEV1_CRTC_PIXEL_RATE_CNTL
++#define DCFEV1_CRTC_PIXEL_RATE_CNTL__DCFEV1_CRTC_PIXEL_RATE_SOURCE__SHIFT 0x0
++#define DCFEV1_CRTC_PIXEL_RATE_CNTL__DCFEV1_CRTC_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x8
++#define DCFEV1_CRTC_PIXEL_RATE_CNTL__DCFEV1_CRTC_PIXEL_RATE_PLL_SOURCE__SHIFT 0xf
++#define DCFEV1_CRTC_PIXEL_RATE_CNTL__DCFEV1_CRTC_PIXEL_RATE_SOURCE_MASK 0x00000003L
++#define DCFEV1_CRTC_PIXEL_RATE_CNTL__DCFEV1_CRTC_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000700L
++#define DCFEV1_CRTC_PIXEL_RATE_CNTL__DCFEV1_CRTC_PIXEL_RATE_PLL_SOURCE_MASK 0x00008000L
++//SYMCLKLPA_CLOCK_ENABLE
++#define SYMCLKLPA_CLOCK_ENABLE__SYMCLKLPA_CLOCK_ENABLE__SHIFT 0x0
++#define SYMCLKLPA_CLOCK_ENABLE__SYMCLKLPA_FE_FORCE_EN__SHIFT 0x4
++#define SYMCLKLPA_CLOCK_ENABLE__SYMCLKLPA_FE_FORCE_SRC__SHIFT 0x8
++#define SYMCLKLPA_CLOCK_ENABLE__SYMCLKLPA_CLOCK_ENABLE_MASK 0x00000001L
++#define SYMCLKLPA_CLOCK_ENABLE__SYMCLKLPA_FE_FORCE_EN_MASK 0x00000010L
++#define SYMCLKLPA_CLOCK_ENABLE__SYMCLKLPA_FE_FORCE_SRC_MASK 0x00000700L
++//SYMCLKLPB_CLOCK_ENABLE
++#define SYMCLKLPB_CLOCK_ENABLE__SYMCLKLPB_CLOCK_ENABLE__SHIFT 0x0
++#define SYMCLKLPB_CLOCK_ENABLE__SYMCLKLPB_FE_FORCE_EN__SHIFT 0x4
++#define SYMCLKLPB_CLOCK_ENABLE__SYMCLKLPB_FE_FORCE_SRC__SHIFT 0x8
++#define SYMCLKLPB_CLOCK_ENABLE__SYMCLKLPB_CLOCK_ENABLE_MASK 0x00000001L
++#define SYMCLKLPB_CLOCK_ENABLE__SYMCLKLPB_FE_FORCE_EN_MASK 0x00000010L
++#define SYMCLKLPB_CLOCK_ENABLE__SYMCLKLPB_FE_FORCE_SRC_MASK 0x00000700L
++//DPREFCLK_CGTT_BLK_CTRL_REG
++#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY__SHIFT 0x0
++#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY__SHIFT 0x4
++#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY_MASK 0x0000000FL
++#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY_MASK 0x00000FF0L
++//REFCLK_CNTL
++#define REFCLK_CNTL__REFCLK_CLOCK_EN__SHIFT 0x0
++#define REFCLK_CNTL__REFCLK_SRC_SEL__SHIFT 0x1
++#define REFCLK_CNTL__REFCLK_CLOCK_EN_MASK 0x00000001L
++#define REFCLK_CNTL__REFCLK_SRC_SEL_MASK 0x00000002L
++//MIPI_CLK_CNTL
++#define MIPI_CLK_CNTL__DSICLK_CLOCK_ENABLE__SHIFT 0x0
++#define MIPI_CLK_CNTL__BYTECLK_CLOCK_ENABLE__SHIFT 0x1
++#define MIPI_CLK_CNTL__ESCCLK_CLOCK_ENABLE__SHIFT 0x2
++#define MIPI_CLK_CNTL__DSICLK_CLOCK_ENABLE_MASK 0x00000001L
++#define MIPI_CLK_CNTL__BYTECLK_CLOCK_ENABLE_MASK 0x00000002L
++#define MIPI_CLK_CNTL__ESCCLK_CLOCK_ENABLE_MASK 0x00000004L
++//REFCLK_CGTT_BLK_CTRL_REG
++#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY__SHIFT 0x0
++#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY__SHIFT 0x4
++#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY_MASK 0x0000000FL
++#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY_MASK 0x00000FF0L
++//PHYPLLE_PIXCLK_RESYNC_CNTL
++#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
++#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
++#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE__SHIFT 0x8
++#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
++#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
++#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
++#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE_MASK 0x00000100L
++#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
++//DCCG_PERFMON_CNTL2
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE__SHIFT 0x0
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE__SHIFT 0x1
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE__SHIFT 0x2
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE__SHIFT 0x3
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE__SHIFT 0x4
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE__SHIFT 0x5
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE__SHIFT 0x6
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE__SHIFT 0x7
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE__SHIFT 0x8
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE_MASK 0x00000001L
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE_MASK 0x00000002L
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE_MASK 0x00000004L
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE_MASK 0x00000008L
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE_MASK 0x00000010L
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE_MASK 0x00000020L
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE_MASK 0x00000040L
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE_MASK 0x00000080L
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE_MASK 0x00000100L
++//DSICLK_CGTT_BLK_CTRL_REG
++#define DSICLK_CGTT_BLK_CTRL_REG__DSICLK_TURN_ON_DELAY__SHIFT 0x0
++#define DSICLK_CGTT_BLK_CTRL_REG__DSICLK_TURN_OFF_DELAY__SHIFT 0x4
++#define DSICLK_CGTT_BLK_CTRL_REG__DSICLK_TURN_ON_DELAY_MASK 0x0000000FL
++#define DSICLK_CGTT_BLK_CTRL_REG__DSICLK_TURN_OFF_DELAY_MASK 0x00000FF0L
++//DCCG_CBUS_WRCMD_DELAY
++#define DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY__SHIFT 0x0
++#define DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY_MASK 0x0000000FL
++//DCCG_DS_DTO_INCR
++#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT 0x0
++#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK 0xFFFFFFFFL
++//DCCG_DS_DTO_MODULO
++#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT 0x0
++#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK 0xFFFFFFFFL
++//DCCG_DS_CNTL
++#define DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT 0x0
++#define DCCG_DS_CNTL__DCCG_DS_REF_SRC__SHIFT 0x4
++#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT 0x8
++#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT 0x9
++#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT 0x10
++#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT 0x18
++#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT 0x19
++#define DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK 0x00000001L
++#define DCCG_DS_CNTL__DCCG_DS_REF_SRC_MASK 0x00000030L
++#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK 0x00000100L
++#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK 0x00000200L
++#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK 0x00030000L
++#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK 0x01000000L
++#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK 0x02000000L
++//DCCG_DS_HW_CAL_INTERVAL
++#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT 0x0
++#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK 0xFFFFFFFFL
++//SYMCLKG_CLOCK_ENABLE
++#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_CLOCK_ENABLE__SHIFT 0x0
++#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_EN__SHIFT 0x4
++#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_SRC__SHIFT 0x8
++#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_CLOCK_ENABLE_MASK 0x00000001L
++#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_EN_MASK 0x00000010L
++#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_SRC_MASK 0x00000700L
++//DPREFCLK_CNTL
++#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT 0x0
++#define DPREFCLK_CNTL__UNB_DB_CLK_ENABLE__SHIFT 0x8
++#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK 0x00000007L
++#define DPREFCLK_CNTL__UNB_DB_CLK_ENABLE_MASK 0x00000100L
++//AOMCLK0_CNTL
++#define AOMCLK0_CNTL__AOMCLK0_CLOCK_EN__SHIFT 0x0
++#define AOMCLK0_CNTL__AOMCLK0_CLOCK_EN_MASK 0x00000001L
++//AOMCLK1_CNTL
++#define AOMCLK1_CNTL__AOMCLK1_CLOCK_EN__SHIFT 0x0
++#define AOMCLK1_CNTL__AOMCLK1_CLOCK_EN_MASK 0x00000001L
++//AOMCLK2_CNTL
++#define AOMCLK2_CNTL__AOMCLK2_CLOCK_EN__SHIFT 0x0
++#define AOMCLK2_CNTL__AOMCLK2_CLOCK_EN_MASK 0x00000001L
++//DCCG_AUDIO_DTO2_PHASE
++#define DCCG_AUDIO_DTO2_PHASE__DCCG_AUDIO_DTO2_PHASE__SHIFT 0x0
++#define DCCG_AUDIO_DTO2_PHASE__DCCG_AUDIO_DTO2_PHASE_MASK 0xFFFFFFFFL
++//DCCG_AUDIO_DTO2_MODULO
++#define DCCG_AUDIO_DTO2_MODULO__DCCG_AUDIO_DTO2_MODULO__SHIFT 0x0
++#define DCCG_AUDIO_DTO2_MODULO__DCCG_AUDIO_DTO2_MODULO_MASK 0xFFFFFFFFL
++//DCE_VERSION
++#define DCE_VERSION__MAJOR_VERSION__SHIFT 0x0
++#define DCE_VERSION__MINOR_VERSION__SHIFT 0x8
++#define DCE_VERSION__MAJOR_VERSION_MASK 0x000000FFL
++#define DCE_VERSION__MINOR_VERSION_MASK 0x0000FF00L
++//PHYPLLG_PIXCLK_RESYNC_CNTL
++#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
++#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
++#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_ENABLE__SHIFT 0x8
++#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
++#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
++#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
++#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_ENABLE_MASK 0x00000100L
++#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
++//DCCG_GTC_CNTL
++#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT 0x0
++#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK 0x00000001L
++//DCCG_GTC_DTO_INCR
++#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT 0x0
++#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK 0xFFFFFFFFL
++//DCCG_GTC_DTO_MODULO
++#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT 0x0
++#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK 0xFFFFFFFFL
++//DCCG_GTC_CURRENT
++#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT 0x0
++#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK 0xFFFFFFFFL
++//DENTIST_DISPCLK_CNTL
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0xf
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x11
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x12
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13
++#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE__SHIFT 0x14
++#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG__SHIFT 0x15
++#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG__SHIFT 0x16
++#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER__SHIFT 0x18
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x0000007FL
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x00007F00L
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK 0x00018000L
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK 0x00020000L
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK 0x00040000L
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x00080000L
++#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE_MASK 0x00100000L
++#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG_MASK 0x00200000L
++#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG_MASK 0x00400000L
++#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER_MASK 0x7F000000L
++//MIPI_DTO_CNTL
++#define MIPI_DTO_CNTL__MIPI_DTO_ENABLE__SHIFT 0x0
++#define MIPI_DTO_CNTL__MIPI_DTO_ENABLE_MASK 0x00000001L
++//MIPI_DTO_PHASE
++#define MIPI_DTO_PHASE__MIPI_DTO_PHASE__SHIFT 0x0
++#define MIPI_DTO_PHASE__MIPI_DTO_PHASE_MASK 0xFFFFFFFFL
++//MIPI_DTO_MODULO
++#define MIPI_DTO_MODULO__MIPI_DTO_MODULO__SHIFT 0x0
++#define MIPI_DTO_MODULO__MIPI_DTO_MODULO_MASK 0xFFFFFFFFL
++//DAC_CLK_ENABLE
++#define DAC_CLK_ENABLE__DACA_CLK_ENABLE__SHIFT 0x0
++#define DAC_CLK_ENABLE__DACB_CLK_ENABLE__SHIFT 0x4
++#define DAC_CLK_ENABLE__DACA_CLK_ENABLE_MASK 0x00000001L
++#define DAC_CLK_ENABLE__DACB_CLK_ENABLE_MASK 0x00000010L
++//DVO_CLK_ENABLE
++#define DVO_CLK_ENABLE__DVO_CLK_ENABLE__SHIFT 0x0
++#define DVO_CLK_ENABLE__DVO_CLK_ENABLE_MASK 0x00000001L
++//AVSYNC_COUNTER_WRITE
++#define AVSYNC_COUNTER_WRITE__AVSYNC_COUNTER_WRVALUE__SHIFT 0x0
++#define AVSYNC_COUNTER_WRITE__AVSYNC_COUNTER_WRVALUE_MASK 0xFFFFFFFFL
++//AVSYNC_COUNTER_CONTROL
++#define AVSYNC_COUNTER_CONTROL__AVSYNC_COUNTER_ENABLE__SHIFT 0x0
++#define AVSYNC_COUNTER_CONTROL__AVSYNC_COUNTER_ENABLE_MASK 0x00000001L
++//DMCU_SMU_INTERRUPT_CNTL
++#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT__SHIFT 0x0
++#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS__SHIFT 0x10
++#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT_MASK 0x00000001L
++#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS_MASK 0xFFFF0000L
++//SMU_CONTROL
++#define SMU_CONTROL__DISPLAY0_FORCE_VBI__SHIFT 0x0
++#define SMU_CONTROL__DISPLAY1_FORCE_VBI__SHIFT 0x1
++#define SMU_CONTROL__DISPLAY2_FORCE_VBI__SHIFT 0x2
++#define SMU_CONTROL__DISPLAY3_FORCE_VBI__SHIFT 0x3
++#define SMU_CONTROL__DISPLAY4_FORCE_VBI__SHIFT 0x4
++#define SMU_CONTROL__DISPLAY5_FORCE_VBI__SHIFT 0x5
++#define SMU_CONTROL__DISPLAY_V0_FORCE_VBI__SHIFT 0x6
++#define SMU_CONTROL__DISPLAY_V1_FORCE_VBI__SHIFT 0x7
++#define SMU_CONTROL__MCIF_WB_FORCE_VBI__SHIFT 0x8
++#define SMU_CONTROL__DISPLAY0_FORCE_VBI_MASK 0x00000001L
++#define SMU_CONTROL__DISPLAY1_FORCE_VBI_MASK 0x00000002L
++#define SMU_CONTROL__DISPLAY2_FORCE_VBI_MASK 0x00000004L
++#define SMU_CONTROL__DISPLAY3_FORCE_VBI_MASK 0x00000008L
++#define SMU_CONTROL__DISPLAY4_FORCE_VBI_MASK 0x00000010L
++#define SMU_CONTROL__DISPLAY5_FORCE_VBI_MASK 0x00000020L
++#define SMU_CONTROL__DISPLAY_V0_FORCE_VBI_MASK 0x00000040L
++#define SMU_CONTROL__DISPLAY_V1_FORCE_VBI_MASK 0x00000080L
++#define SMU_CONTROL__MCIF_WB_FORCE_VBI_MASK 0x00000100L
++//SMU_INTERRUPT_CONTROL
++#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT 0x0
++#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT 0x4
++#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT 0x10
++#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK 0x00000001L
++#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK 0x00000010L
++#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK 0xFFFF0000L
++//AVSYNC_COUNTER_READ
++#define AVSYNC_COUNTER_READ__AVSYNC_COUNTER_RDVALUE__SHIFT 0x0
++#define AVSYNC_COUNTER_READ__AVSYNC_COUNTER_RDVALUE_MASK 0xFFFFFFFFL
++//MILLISECOND_TIME_BASE_DIV
++#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT 0x0
++#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14
++#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK 0x0001FFFFL
++#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L
++//DISPCLK_FREQ_CHANGE_CNTL
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT 0x0
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT 0x10
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT 0x14
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT 0x19
++#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT 0x1c
++#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT 0x1d
++#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT 0x1e
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT 0x1f
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK 0x00003FFFL
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK 0x000F0000L
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK 0x00100000L
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK 0x0E000000L
++#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK 0x10000000L
++#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK 0x20000000L
++#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK 0x40000000L
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK 0x80000000L
++//DC_MEM_GLOBAL_PWR_REQ_CNTL
++#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS__SHIFT 0x0
++#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS_MASK 0x00000001L
++//DCCG_PERFMON_CNTL
++#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT 0x0
++#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT 0x1
++#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE__SHIFT 0x2
++#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE__SHIFT 0x3
++#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT 0x4
++#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT 0x5
++#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT 0x6
++#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT 0x7
++#define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL__SHIFT 0x8
++#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV__SHIFT 0xb
++#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK 0x00000001L
++#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK 0x00000002L
++#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE_MASK 0x00000004L
++#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE_MASK 0x00000008L
++#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK 0x00000010L
++#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK 0x00000020L
++#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK 0x00000040L
++#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK 0x00000080L
++#define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL_MASK 0x00000700L
++#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV_MASK 0xFFFFF800L
++//DCCG_GATE_DISABLE_CNTL
++#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT 0x0
++#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT 0x1
++#define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE__SHIFT 0x2
++#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT 0x3
++#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT 0x4
++#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE__SHIFT 0x5
++#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT 0x6
++#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE__SHIFT 0x8
++#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT 0x11
++#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT 0x12
++#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT 0x13
++#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE__SHIFT 0x15
++#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT 0x16
++#define DCCG_GATE_DISABLE_CNTL__UNB_DB_CLK_GATE_DISABLE__SHIFT 0x17
++#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE__SHIFT 0x1a
++#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE__SHIFT 0x1b
++#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE__SHIFT 0x1c
++#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE__SHIFT 0x1d
++#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE__SHIFT 0x1e
++#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK 0x00000001L
++#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK 0x00000002L
++#define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE_MASK 0x00000004L
++#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK 0x00000008L
++#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK 0x00000010L
++#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE_MASK 0x00000020L
++#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK 0x00000040L
++#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE_MASK 0x00000100L
++#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK 0x00020000L
++#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK 0x00040000L
++#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK 0x00080000L
++#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE_MASK 0x00200000L
++#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK 0x00400000L
++#define DCCG_GATE_DISABLE_CNTL__UNB_DB_CLK_GATE_DISABLE_MASK 0x00800000L
++#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE_MASK 0x04000000L
++#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE_MASK 0x08000000L
++#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE_MASK 0x10000000L
++#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE_MASK 0x20000000L
++#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE_MASK 0x40000000L
++//DISPCLK_CGTT_BLK_CTRL_REG
++#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT 0x0
++#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT 0x4
++#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK 0x0000000FL
++#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK 0x00000FF0L
++//SCLK_CGTT_BLK_CTRL_REG
++#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY__SHIFT 0x0
++#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY__SHIFT 0x4
++#define SCLK_CGTT_BLK_CTRL_REG__CGTT_SCLK_OVERRIDE__SHIFT 0xc
++#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY_MASK 0x0000000FL
++#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY_MASK 0x00000FF0L
++#define SCLK_CGTT_BLK_CTRL_REG__CGTT_SCLK_OVERRIDE_MASK 0x00001000L
++//DCCG_CAC_STATUS
++#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT 0x0
++#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK 0xFFFFFFFFL
++//PIXCLK1_RESYNC_CNTL
++#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE__SHIFT 0x0
++#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1__SHIFT 0x4
++#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE_MASK 0x00000001L
++#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1_MASK 0x00000030L
++//PIXCLK2_RESYNC_CNTL
++#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE__SHIFT 0x0
++#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2__SHIFT 0x4
++#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE_MASK 0x00000001L
++#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2_MASK 0x00000030L
++//PIXCLK0_RESYNC_CNTL
++#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE__SHIFT 0x0
++#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0__SHIFT 0x4
++#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE_MASK 0x00000001L
++#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0_MASK 0x00000030L
++//MICROSECOND_TIME_BASE_DIV
++#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT 0x0
++#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x8
++#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT 0x10
++#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT 0x11
++#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14
++#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK 0x0000007FL
++#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK 0x00007F00L
++#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK 0x00010000L
++#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK 0x00020000L
++#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L
++//DCCG_GATE_DISABLE_CNTL2
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE__SHIFT 0x0
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE__SHIFT 0x1
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE__SHIFT 0x2
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE__SHIFT 0x3
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE__SHIFT 0x4
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE__SHIFT 0x5
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE__SHIFT 0x6
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPA_FE_GATE_DISABLE__SHIFT 0x8
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_FE_GATE_DISABLE__SHIFT 0x9
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE__SHIFT 0x10
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE__SHIFT 0x11
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE__SHIFT 0x12
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE__SHIFT 0x13
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE__SHIFT 0x14
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE__SHIFT 0x15
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE__SHIFT 0x16
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPA_GATE_DISABLE__SHIFT 0x18
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_GATE_DISABLE__SHIFT 0x19
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE_MASK 0x00000001L
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE_MASK 0x00000002L
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE_MASK 0x00000004L
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE_MASK 0x00000008L
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE_MASK 0x00000010L
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE_MASK 0x00000020L
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE_MASK 0x00000040L
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPA_FE_GATE_DISABLE_MASK 0x00000100L
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_FE_GATE_DISABLE_MASK 0x00000200L
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE_MASK 0x00010000L
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE_MASK 0x00020000L
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE_MASK 0x00040000L
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE_MASK 0x00080000L
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE_MASK 0x00100000L
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE_MASK 0x00200000L
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE_MASK 0x00400000L
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPA_GATE_DISABLE_MASK 0x01000000L
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_GATE_DISABLE_MASK 0x02000000L
++//SYMCLK_CGTT_BLK_CTRL_REG
++#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY__SHIFT 0x0
++#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY__SHIFT 0x4
++#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY_MASK 0x0000000FL
++#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY_MASK 0x00000FF0L
++//PHYPLLF_PIXCLK_RESYNC_CNTL
++#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
++#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
++#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE__SHIFT 0x8
++#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
++#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
++#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
++#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE_MASK 0x00000100L
++#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
++//DCCG_DISP_CNTL_REG
++#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT 0x8
++#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK 0x00000100L
++//CRTC0_PIXEL_RATE_CNTL
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE__SHIFT 0x0
++#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT 0x4
++#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT 0x5
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL__SHIFT 0x8
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL__SHIFT 0x9
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_HALF_RATE_EN__SHIFT 0xb
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR__SHIFT 0xe
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT__SHIFT 0x10
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE_MASK 0x00000003L
++#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK 0x00000010L
++#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK 0x00000020L
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL_MASK 0x00000100L
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL_MASK 0x00000200L
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_HALF_RATE_EN_MASK 0x00000800L
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR_MASK 0x0000C000L
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT_MASK 0x0FFF0000L
++//DP_DTO0_PHASE
++#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT 0x0
++#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK 0xFFFFFFFFL
++//DP_DTO0_MODULO
++#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT 0x0
++#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK 0xFFFFFFFFL
++//CRTC0_PHYPLL_PIXEL_RATE_CNTL
++#define CRTC0_PHYPLL_PIXEL_RATE_CNTL__CRTC0_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0
++#define CRTC0_PHYPLL_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4
++#define CRTC0_PHYPLL_PIXEL_RATE_CNTL__CRTC0_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L
++#define CRTC0_PHYPLL_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L
++//CRTC1_PIXEL_RATE_CNTL
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE__SHIFT 0x0
++#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT 0x4
++#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT 0x5
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL__SHIFT 0x8
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL__SHIFT 0x9
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_HALF_RATE_EN__SHIFT 0xb
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR__SHIFT 0xe
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT__SHIFT 0x10
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE_MASK 0x00000003L
++#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK 0x00000010L
++#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK 0x00000020L
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL_MASK 0x00000100L
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL_MASK 0x00000200L
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_HALF_RATE_EN_MASK 0x00000800L
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR_MASK 0x0000C000L
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT_MASK 0x0FFF0000L
++//DP_DTO1_PHASE
++#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT 0x0
++#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK 0xFFFFFFFFL
++//DP_DTO1_MODULO
++#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT 0x0
++#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK 0xFFFFFFFFL
++//CRTC1_PHYPLL_PIXEL_RATE_CNTL
++#define CRTC1_PHYPLL_PIXEL_RATE_CNTL__CRTC1_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0
++#define CRTC1_PHYPLL_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4
++#define CRTC1_PHYPLL_PIXEL_RATE_CNTL__CRTC1_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L
++#define CRTC1_PHYPLL_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L
++//CRTC2_PIXEL_RATE_CNTL
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE__SHIFT 0x0
++#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT 0x4
++#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT 0x5
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL__SHIFT 0x8
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL__SHIFT 0x9
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_HALF_RATE_EN__SHIFT 0xb
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR__SHIFT 0xe
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT__SHIFT 0x10
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE_MASK 0x00000003L
++#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK 0x00000010L
++#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK 0x00000020L
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL_MASK 0x00000100L
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL_MASK 0x00000200L
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_HALF_RATE_EN_MASK 0x00000800L
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR_MASK 0x0000C000L
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT_MASK 0x0FFF0000L
++//DP_DTO2_PHASE
++#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT 0x0
++#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK 0xFFFFFFFFL
++//DP_DTO2_MODULO
++#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT 0x0
++#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK 0xFFFFFFFFL
++//CRTC2_PHYPLL_PIXEL_RATE_CNTL
++#define CRTC2_PHYPLL_PIXEL_RATE_CNTL__CRTC2_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0
++#define CRTC2_PHYPLL_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4
++#define CRTC2_PHYPLL_PIXEL_RATE_CNTL__CRTC2_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L
++#define CRTC2_PHYPLL_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L
++//CRTC3_PIXEL_RATE_CNTL
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE__SHIFT 0x0
++#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT 0x4
++#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT 0x5
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL__SHIFT 0x8
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL__SHIFT 0x9
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_HALF_RATE_EN__SHIFT 0xb
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR__SHIFT 0xe
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT__SHIFT 0x10
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE_MASK 0x00000003L
++#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK 0x00000010L
++#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK 0x00000020L
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL_MASK 0x00000100L
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL_MASK 0x00000200L
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_HALF_RATE_EN_MASK 0x00000800L
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR_MASK 0x0000C000L
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT_MASK 0x0FFF0000L
++//DP_DTO3_PHASE
++#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT 0x0
++#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK 0xFFFFFFFFL
++//DP_DTO3_MODULO
++#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT 0x0
++#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK 0xFFFFFFFFL
++//CRTC3_PHYPLL_PIXEL_RATE_CNTL
++#define CRTC3_PHYPLL_PIXEL_RATE_CNTL__CRTC3_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0
++#define CRTC3_PHYPLL_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4
++#define CRTC3_PHYPLL_PIXEL_RATE_CNTL__CRTC3_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L
++#define CRTC3_PHYPLL_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L
++//CRTC4_PIXEL_RATE_CNTL
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE__SHIFT 0x0
++#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE__SHIFT 0x4
++#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE__SHIFT 0x5
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL__SHIFT 0x8
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL__SHIFT 0x9
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_HALF_RATE_EN__SHIFT 0xb
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR__SHIFT 0xe
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT__SHIFT 0x10
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE_MASK 0x00000003L
++#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE_MASK 0x00000010L
++#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE_MASK 0x00000020L
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL_MASK 0x00000100L
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL_MASK 0x00000200L
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_HALF_RATE_EN_MASK 0x00000800L
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR_MASK 0x0000C000L
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT_MASK 0x0FFF0000L
++//DP_DTO4_PHASE
++#define DP_DTO4_PHASE__DP_DTO4_PHASE__SHIFT 0x0
++#define DP_DTO4_PHASE__DP_DTO4_PHASE_MASK 0xFFFFFFFFL
++//DP_DTO4_MODULO
++#define DP_DTO4_MODULO__DP_DTO4_MODULO__SHIFT 0x0
++#define DP_DTO4_MODULO__DP_DTO4_MODULO_MASK 0xFFFFFFFFL
++//CRTC4_PHYPLL_PIXEL_RATE_CNTL
++#define CRTC4_PHYPLL_PIXEL_RATE_CNTL__CRTC4_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0
++#define CRTC4_PHYPLL_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4
++#define CRTC4_PHYPLL_PIXEL_RATE_CNTL__CRTC4_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L
++#define CRTC4_PHYPLL_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L
++//CRTC5_PIXEL_RATE_CNTL
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE__SHIFT 0x0
++#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE__SHIFT 0x4
++#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE__SHIFT 0x5
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL__SHIFT 0x8
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL__SHIFT 0x9
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_HALF_RATE_EN__SHIFT 0xb
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR__SHIFT 0xe
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT__SHIFT 0x10
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE_MASK 0x00000003L
++#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE_MASK 0x00000010L
++#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE_MASK 0x00000020L
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL_MASK 0x00000100L
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL_MASK 0x00000200L
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_HALF_RATE_EN_MASK 0x00000800L
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR_MASK 0x0000C000L
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT_MASK 0x0FFF0000L
++//DP_DTO5_PHASE
++#define DP_DTO5_PHASE__DP_DTO5_PHASE__SHIFT 0x0
++#define DP_DTO5_PHASE__DP_DTO5_PHASE_MASK 0xFFFFFFFFL
++//DP_DTO5_MODULO
++#define DP_DTO5_MODULO__DP_DTO5_MODULO__SHIFT 0x0
++#define DP_DTO5_MODULO__DP_DTO5_MODULO_MASK 0xFFFFFFFFL
++//CRTC5_PHYPLL_PIXEL_RATE_CNTL
++#define CRTC5_PHYPLL_PIXEL_RATE_CNTL__CRTC5_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0
++#define CRTC5_PHYPLL_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4
++#define CRTC5_PHYPLL_PIXEL_RATE_CNTL__CRTC5_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L
++#define CRTC5_PHYPLL_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L
++//DCCG_SOFT_RESET
++#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT 0x0
++#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET__SHIFT 0x1
++#define DCCG_SOFT_RESET__SOFT_RESET_DVO__SHIFT 0x2
++#define DCCG_SOFT_RESET__DVO_ENABLE_RST__SHIFT 0x3
++#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT 0x4
++#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT 0x8
++#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT 0xc
++#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT 0xd
++#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET__SHIFT 0xe
++#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET__SHIFT 0xf
++#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET__SHIFT 0x10
++#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET__SHIFT 0x11
++#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET__SHIFT 0x12
++#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET__SHIFT 0x13
++#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET__SHIFT 0x14
++#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET__SHIFT 0x15
++#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK 0x00000001L
++#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET_MASK 0x00000002L
++#define DCCG_SOFT_RESET__SOFT_RESET_DVO_MASK 0x00000004L
++#define DCCG_SOFT_RESET__DVO_ENABLE_RST_MASK 0x00000008L
++#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK 0x00000010L
++#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK 0x00000100L
++#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK 0x00001000L
++#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK 0x00002000L
++#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET_MASK 0x00004000L
++#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET_MASK 0x00008000L
++#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET_MASK 0x00010000L
++#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET_MASK 0x00020000L
++#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET_MASK 0x00040000L
++#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET_MASK 0x00080000L
++#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET_MASK 0x00100000L
++#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET_MASK 0x00200000L
++//SYMCLKA_CLOCK_ENABLE
++#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT 0x0
++#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT 0x4
++#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT 0x8
++#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK 0x00000001L
++#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK 0x00000010L
++#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK 0x00000700L
++//SYMCLKB_CLOCK_ENABLE
++#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT 0x0
++#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT 0x4
++#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT 0x8
++#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK 0x00000001L
++#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK 0x00000010L
++#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK 0x00000700L
++//SYMCLKC_CLOCK_ENABLE
++#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT 0x0
++#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT 0x4
++#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT 0x8
++#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK 0x00000001L
++#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK 0x00000010L
++#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK 0x00000700L
++//SYMCLKD_CLOCK_ENABLE
++#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT 0x0
++#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT 0x4
++#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT 0x8
++#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK 0x00000001L
++#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK 0x00000010L
++#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK 0x00000700L
++//SYMCLKE_CLOCK_ENABLE
++#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT 0x0
++#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT 0x4
++#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT 0x8
++#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK 0x00000001L
++#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK 0x00000010L
++#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK 0x00000700L
++//SYMCLKF_CLOCK_ENABLE
++#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE__SHIFT 0x0
++#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN__SHIFT 0x4
++#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC__SHIFT 0x8
++#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE_MASK 0x00000001L
++#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN_MASK 0x00000010L
++#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC_MASK 0x00000700L
++//DVOACLKD_CNTL
++#define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL__SHIFT 0x0
++#define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL__SHIFT 0x8
++#define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN__SHIFT 0x10
++#define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN__SHIFT 0x11
++#define DVOACLKD_CNTL__DVOACLKD_IN_PHASE__SHIFT 0x12
++#define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL_MASK 0x00000007L
++#define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL_MASK 0x00001F00L
++#define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN_MASK 0x00010000L
++#define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN_MASK 0x00020000L
++#define DVOACLKD_CNTL__DVOACLKD_IN_PHASE_MASK 0x00040000L
++//DVOACLKC_MVP_CNTL
++#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL__SHIFT 0x0
++#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL__SHIFT 0x8
++#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN__SHIFT 0x10
++#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN__SHIFT 0x11
++#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE__SHIFT 0x12
++#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE__SHIFT 0x14
++#define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL__SHIFT 0x18
++#define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL__SHIFT 0x1c
++#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL_MASK 0x00000007L
++#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL_MASK 0x00001F00L
++#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN_MASK 0x00010000L
++#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN_MASK 0x00020000L
++#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE_MASK 0x00040000L
++#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_MASK 0x00100000L
++#define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL_MASK 0x03000000L
++#define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL_MASK 0x30000000L
++//DVOACLKC_CNTL
++#define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL__SHIFT 0x0
++#define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL__SHIFT 0x8
++#define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN__SHIFT 0x10
++#define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN__SHIFT 0x11
++#define DVOACLKC_CNTL__DVOACLKC_IN_PHASE__SHIFT 0x12
++#define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL_MASK 0x00000007L
++#define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL_MASK 0x00001F00L
++#define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN_MASK 0x00010000L
++#define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN_MASK 0x00020000L
++#define DVOACLKC_CNTL__DVOACLKC_IN_PHASE_MASK 0x00040000L
++//DCCG_AUDIO_DTO_SOURCE
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT 0x0
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT 0x4
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL__SHIFT 0xc
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN__SHIFT 0x10
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT 0x14
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT 0x18
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT 0x1c
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK 0x00000007L
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK 0x00000030L
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL_MASK 0x00003000L
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN_MASK 0x00010000L
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK 0x00100000L
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK 0x01000000L
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK 0x10000000L
++//DCCG_AUDIO_DTO0_PHASE
++#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT 0x0
++#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK 0xFFFFFFFFL
++//DCCG_AUDIO_DTO0_MODULE
++#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT 0x0
++#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK 0xFFFFFFFFL
++//DCCG_AUDIO_DTO1_PHASE
++#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT 0x0
++#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK 0xFFFFFFFFL
++//DCCG_AUDIO_DTO1_MODULE
++#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT 0x0
++#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK 0xFFFFFFFFL
++//DCCG_TEST_CLK_SEL
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT 0x0
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT 0xc
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT 0x10
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT 0x1c
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK 0x000001FFL
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK 0x00001000L
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK 0x01FF0000L
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK 0x10000000L
++//FBC_CNTL
++#define FBC_CNTL__FBC_GRPH_COMP_EN__SHIFT 0x0
++#define FBC_CNTL__FBC_SRC_SEL__SHIFT 0x1
++#define FBC_CNTL__FBC_COMP_CLK_GATE_EN__SHIFT 0x8
++#define FBC_CNTL__FBC_DECOMP_CLK_GATE_EN__SHIFT 0xa
++#define FBC_CNTL__FBC_COHERENCY_MODE__SHIFT 0x10
++#define FBC_CNTL__FBC_DS_ALLOW_DIS__SHIFT 0x18
++#define FBC_CNTL__FBC_SOFT_COMPRESS_EN__SHIFT 0x19
++#define FBC_CNTL__FBC_QOS_LEVEL__SHIFT 0x1a
++#define FBC_CNTL__FBC_EN__SHIFT 0x1f
++#define FBC_CNTL__FBC_GRPH_COMP_EN_MASK 0x00000001L
++#define FBC_CNTL__FBC_SRC_SEL_MASK 0x0000000EL
++#define FBC_CNTL__FBC_COMP_CLK_GATE_EN_MASK 0x00000100L
++#define FBC_CNTL__FBC_DECOMP_CLK_GATE_EN_MASK 0x00000400L
++#define FBC_CNTL__FBC_COHERENCY_MODE_MASK 0x00030000L
++#define FBC_CNTL__FBC_DS_ALLOW_DIS_MASK 0x01000000L
++#define FBC_CNTL__FBC_SOFT_COMPRESS_EN_MASK 0x02000000L
++#define FBC_CNTL__FBC_QOS_LEVEL_MASK 0x3C000000L
++#define FBC_CNTL__FBC_EN_MASK 0x80000000L
++//FBC_IDLE_FORCE_CLEAR_MASK
++#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK__SHIFT 0x0
++#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK_MASK 0xFFFFFFFFL
++//FBC_START_STOP_DELAY
++#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY__SHIFT 0x0
++#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY__SHIFT 0x7
++#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY__SHIFT 0x8
++#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY_MASK 0x0000001FL
++#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY_MASK 0x00000080L
++#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY_MASK 0x00001F00L
++//FBC_COMP_CNTL
++#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION__SHIFT 0x0
++#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN__SHIFT 0x10
++#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN__SHIFT 0x11
++#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN__SHIFT 0x12
++#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN__SHIFT 0x13
++#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN__SHIFT 0x14
++#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION_MASK 0x0000000FL
++#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN_MASK 0x00010000L
++#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN_MASK 0x00020000L
++#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN_MASK 0x00040000L
++#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN_MASK 0x00080000L
++#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN_MASK 0x00100000L
++//FBC_COMP_MODE
++#define FBC_COMP_MODE__FBC_RLE_EN__SHIFT 0x0
++#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN__SHIFT 0x8
++#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN__SHIFT 0x9
++#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN__SHIFT 0xa
++#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN__SHIFT 0xb
++#define FBC_COMP_MODE__FBC_IND_EN__SHIFT 0x10
++#define FBC_COMP_MODE__FBC_RLE_EN_MASK 0x00000001L
++#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN_MASK 0x00000100L
++#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN_MASK 0x00000200L
++#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN_MASK 0x00000400L
++#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN_MASK 0x00000800L
++#define FBC_COMP_MODE__FBC_IND_EN_MASK 0x00010000L
++//FBC_IND_LUT0
++#define FBC_IND_LUT0__FBC_IND_LUT0__SHIFT 0x0
++#define FBC_IND_LUT0__FBC_IND_LUT0_MASK 0xFFFFFFFFL
++//FBC_IND_LUT1
++#define FBC_IND_LUT1__FBC_IND_LUT1__SHIFT 0x0
++#define FBC_IND_LUT1__FBC_IND_LUT1_MASK 0xFFFFFFFFL
++//FBC_IND_LUT2
++#define FBC_IND_LUT2__FBC_IND_LUT2__SHIFT 0x0
++#define FBC_IND_LUT2__FBC_IND_LUT2_MASK 0xFFFFFFFFL
++//FBC_IND_LUT3
++#define FBC_IND_LUT3__FBC_IND_LUT3__SHIFT 0x0
++#define FBC_IND_LUT3__FBC_IND_LUT3_MASK 0xFFFFFFFFL
++//FBC_IND_LUT4
++#define FBC_IND_LUT4__FBC_IND_LUT4__SHIFT 0x0
++#define FBC_IND_LUT4__FBC_IND_LUT4_MASK 0xFFFFFFFFL
++//FBC_IND_LUT5
++#define FBC_IND_LUT5__FBC_IND_LUT5__SHIFT 0x0
++#define FBC_IND_LUT5__FBC_IND_LUT5_MASK 0xFFFFFFFFL
++//FBC_IND_LUT6
++#define FBC_IND_LUT6__FBC_IND_LUT6__SHIFT 0x0
++#define FBC_IND_LUT6__FBC_IND_LUT6_MASK 0xFFFFFFFFL
++//FBC_IND_LUT7
++#define FBC_IND_LUT7__FBC_IND_LUT7__SHIFT 0x0
++#define FBC_IND_LUT7__FBC_IND_LUT7_MASK 0xFFFFFFFFL
++//FBC_IND_LUT8
++#define FBC_IND_LUT8__FBC_IND_LUT8__SHIFT 0x0
++#define FBC_IND_LUT8__FBC_IND_LUT8_MASK 0xFFFFFFFFL
++//FBC_IND_LUT9
++#define FBC_IND_LUT9__FBC_IND_LUT9__SHIFT 0x0
++#define FBC_IND_LUT9__FBC_IND_LUT9_MASK 0xFFFFFFFFL
++//FBC_IND_LUT10
++#define FBC_IND_LUT10__FBC_IND_LUT10__SHIFT 0x0
++#define FBC_IND_LUT10__FBC_IND_LUT10_MASK 0xFFFFFFFFL
++//FBC_IND_LUT11
++#define FBC_IND_LUT11__FBC_IND_LUT11__SHIFT 0x0
++#define FBC_IND_LUT11__FBC_IND_LUT11_MASK 0xFFFFFFFFL
++//FBC_IND_LUT12
++#define FBC_IND_LUT12__FBC_IND_LUT12__SHIFT 0x0
++#define FBC_IND_LUT12__FBC_IND_LUT12_MASK 0xFFFFFFFFL
++//FBC_IND_LUT13
++#define FBC_IND_LUT13__FBC_IND_LUT13__SHIFT 0x0
++#define FBC_IND_LUT13__FBC_IND_LUT13_MASK 0xFFFFFFFFL
++//FBC_IND_LUT14
++#define FBC_IND_LUT14__FBC_IND_LUT14__SHIFT 0x0
++#define FBC_IND_LUT14__FBC_IND_LUT14_MASK 0xFFFFFFFFL
++//FBC_IND_LUT15
++#define FBC_IND_LUT15__FBC_IND_LUT15__SHIFT 0x0
++#define FBC_IND_LUT15__FBC_IND_LUT15_MASK 0xFFFFFFFFL
++//FBC_CSM_REGION_OFFSET_01
++#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0__SHIFT 0x0
++#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1__SHIFT 0x10
++#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0_MASK 0x00000FFFL
++#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1_MASK 0x0FFF0000L
++//FBC_CSM_REGION_OFFSET_23
++#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2__SHIFT 0x0
++#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3__SHIFT 0x10
++#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2_MASK 0x00000FFFL
++#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3_MASK 0x0FFF0000L
++//FBC_CLIENT_REGION_MASK
++#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK__SHIFT 0x10
++#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK_MASK 0x000F0000L
++//FBC_DEBUG_COMP
++#define FBC_DEBUG_COMP__FBC_COMP_SWAP__SHIFT 0x0
++#define FBC_DEBUG_COMP__FBC_COMP_RSIZE__SHIFT 0x3
++#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS__SHIFT 0x4
++#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL__SHIFT 0x8
++#define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE__SHIFT 0xa
++#define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE__SHIFT 0xb
++#define FBC_DEBUG_COMP__FBC_COMP_SWAP_MASK 0x00000003L
++#define FBC_DEBUG_COMP__FBC_COMP_RSIZE_MASK 0x00000008L
++#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS_MASK 0x000000F0L
++#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL_MASK 0x00000300L
++#define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE_MASK 0x00000400L
++#define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE_MASK 0x00000800L
++//FBC_MISC
++#define FBC_MISC__FBC_DECOMPRESS_ERROR__SHIFT 0x0
++#define FBC_MISC__FBC_STOP_ON_ERROR__SHIFT 0x2
++#define FBC_MISC__FBC_INVALIDATE_ON_ERROR__SHIFT 0x3
++#define FBC_MISC__FBC_ERROR_PIXEL__SHIFT 0x4
++#define FBC_MISC__FBC_DIVIDE_X__SHIFT 0x8
++#define FBC_MISC__FBC_DIVIDE_Y__SHIFT 0xa
++#define FBC_MISC__FBC_RSM_WRITE_VALUE__SHIFT 0xb
++#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY__SHIFT 0xc
++#define FBC_MISC__FBC_STOP_ON_HFLIP_EVENT__SHIFT 0xd
++#define FBC_MISC__FBC_STOP_COMP_ON_INVALIDATE__SHIFT 0xe
++#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR__SHIFT 0x10
++#define FBC_MISC__FBC_RESET_AT_ENABLE__SHIFT 0x14
++#define FBC_MISC__FBC_RESET_AT_DISABLE__SHIFT 0x15
++#define FBC_MISC__FBC_SLOW_REQ_INTERVAL__SHIFT 0x18
++#define FBC_MISC__FBC_FORCE_DECOMPRESSOR_EN__SHIFT 0x1f
++#define FBC_MISC__FBC_DECOMPRESS_ERROR_MASK 0x00000003L
++#define FBC_MISC__FBC_STOP_ON_ERROR_MASK 0x00000004L
++#define FBC_MISC__FBC_INVALIDATE_ON_ERROR_MASK 0x00000008L
++#define FBC_MISC__FBC_ERROR_PIXEL_MASK 0x000000F0L
++#define FBC_MISC__FBC_DIVIDE_X_MASK 0x00000300L
++#define FBC_MISC__FBC_DIVIDE_Y_MASK 0x00000400L
++#define FBC_MISC__FBC_RSM_WRITE_VALUE_MASK 0x00000800L
++#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY_MASK 0x00001000L
++#define FBC_MISC__FBC_STOP_ON_HFLIP_EVENT_MASK 0x00002000L
++#define FBC_MISC__FBC_STOP_COMP_ON_INVALIDATE_MASK 0x00004000L
++#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR_MASK 0x00010000L
++#define FBC_MISC__FBC_RESET_AT_ENABLE_MASK 0x00100000L
++#define FBC_MISC__FBC_RESET_AT_DISABLE_MASK 0x00200000L
++#define FBC_MISC__FBC_SLOW_REQ_INTERVAL_MASK 0x1F000000L
++#define FBC_MISC__FBC_FORCE_DECOMPRESSOR_EN_MASK 0x80000000L
++//FBC_STATUS
++#define FBC_STATUS__FBC_ENABLE_STATUS__SHIFT 0x0
++#define FBC_STATUS__FBC_ENABLE_STATUS_SW__SHIFT 0x4
++#define FBC_STATUS__FBC_COMPRESSION_ENABLE_STATUS__SHIFT 0x8
++#define FBC_STATUS__FBC_DECOMPRESSION_ENABLE_STATUS__SHIFT 0xc
++#define FBC_STATUS__FBC_ENABLE_STATUS_MASK 0x00000001L
++#define FBC_STATUS__FBC_ENABLE_STATUS_SW_MASK 0x00000010L
++#define FBC_STATUS__FBC_COMPRESSION_ENABLE_STATUS_MASK 0x00000100L
++#define FBC_STATUS__FBC_DECOMPRESSION_ENABLE_STATUS_MASK 0x00001000L
++//FBC_ALPHA_CNTL
++#define FBC_ALPHA_CNTL__FBC_ALPHA_COMP_EN__SHIFT 0x0
++#define FBC_ALPHA_CNTL__FBC_FORCE_COPY_TO_COMP_BUF__SHIFT 0x4
++#define FBC_ALPHA_CNTL__FBC_ZERO_ALPHA_CHUNK_SKIP_EN__SHIFT 0x8
++#define FBC_ALPHA_CNTL__FBC_ALPHA_COMP_EN_MASK 0x00000001L
++#define FBC_ALPHA_CNTL__FBC_FORCE_COPY_TO_COMP_BUF_MASK 0x00000010L
++#define FBC_ALPHA_CNTL__FBC_ZERO_ALPHA_CHUNK_SKIP_EN_MASK 0x00000100L
++//FBC_ALPHA_RGB_OVERRIDE
++#define FBC_ALPHA_RGB_OVERRIDE__FBC_ZERO_ALPHA_R_VAL__SHIFT 0x0
++#define FBC_ALPHA_RGB_OVERRIDE__FBC_ZERO_ALPHA_G_VAL__SHIFT 0xc
++#define FBC_ALPHA_RGB_OVERRIDE__FBC_ZERO_ALPHA_B_VAL__SHIFT 0x18
++#define FBC_ALPHA_RGB_OVERRIDE__FBC_ZERO_ALPHA_R_VAL_MASK 0x000000FFL
++#define FBC_ALPHA_RGB_OVERRIDE__FBC_ZERO_ALPHA_G_VAL_MASK 0x000FF000L
++#define FBC_ALPHA_RGB_OVERRIDE__FBC_ZERO_ALPHA_B_VAL_MASK 0xFF000000L
++//PIPE0_PG_CONFIG
++#define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0
++#define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x00000001L
++//PIPE0_PG_ENABLE
++#define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0
++#define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x00000001L
++//PIPE0_PG_STATUS
++#define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
++#define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS__SHIFT 0x1e
++#define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000L
++#define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS_MASK 0xC0000000L
++//PIPE1_PG_CONFIG
++#define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON__SHIFT 0x0
++#define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON_MASK 0x00000001L
++//PIPE1_PG_ENABLE
++#define PIPE1_PG_ENABLE__PIPE1_POWER_GATE__SHIFT 0x0
++#define PIPE1_PG_ENABLE__PIPE1_POWER_GATE_MASK 0x00000001L
++//PIPE1_PG_STATUS
++#define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE__SHIFT 0x1c
++#define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS__SHIFT 0x1e
++#define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE_MASK 0x10000000L
++#define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS_MASK 0xC0000000L
++//PIPE2_PG_CONFIG
++#define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON__SHIFT 0x0
++#define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON_MASK 0x00000001L
++//PIPE2_PG_ENABLE
++#define PIPE2_PG_ENABLE__PIPE2_POWER_GATE__SHIFT 0x0
++#define PIPE2_PG_ENABLE__PIPE2_POWER_GATE_MASK 0x00000001L
++//PIPE2_PG_STATUS
++#define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE__SHIFT 0x1c
++#define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS__SHIFT 0x1e
++#define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE_MASK 0x10000000L
++#define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS_MASK 0xC0000000L
++//PIPE3_PG_CONFIG
++#define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON__SHIFT 0x0
++#define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON_MASK 0x00000001L
++//PIPE3_PG_ENABLE
++#define PIPE3_PG_ENABLE__PIPE3_POWER_GATE__SHIFT 0x0
++#define PIPE3_PG_ENABLE__PIPE3_POWER_GATE_MASK 0x00000001L
++//PIPE3_PG_STATUS
++#define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE__SHIFT 0x1c
++#define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS__SHIFT 0x1e
++#define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE_MASK 0x10000000L
++#define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS_MASK 0xC0000000L
++//PIPE4_PG_CONFIG
++#define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON__SHIFT 0x0
++#define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON_MASK 0x00000001L
++//PIPE4_PG_ENABLE
++#define PIPE4_PG_ENABLE__PIPE4_POWER_GATE__SHIFT 0x0
++#define PIPE4_PG_ENABLE__PIPE4_POWER_GATE_MASK 0x00000001L
++//PIPE4_PG_STATUS
++#define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE__SHIFT 0x1c
++#define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS__SHIFT 0x1e
++#define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE_MASK 0x10000000L
++#define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS_MASK 0xC0000000L
++//PIPE5_PG_CONFIG
++#define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON__SHIFT 0x0
++#define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON_MASK 0x00000001L
++//PIPE5_PG_ENABLE
++#define PIPE5_PG_ENABLE__PIPE5_POWER_GATE__SHIFT 0x0
++#define PIPE5_PG_ENABLE__PIPE5_POWER_GATE_MASK 0x00000001L
++//PIPE5_PG_STATUS
++#define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE__SHIFT 0x1c
++#define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS__SHIFT 0x1e
++#define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE_MASK 0x10000000L
++#define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS_MASK 0xC0000000L
++//DSI_PG_CONFIG
++#define DSI_PG_CONFIG__DSI_POWER_FORCEON__SHIFT 0x0
++#define DSI_PG_CONFIG__DSI_POWER_FORCEON_MASK 0x00000001L
++//DSI_PG_ENABLE
++#define DSI_PG_ENABLE__DSI_POWER_GATE__SHIFT 0x0
++#define DSI_PG_ENABLE__DSI_POWER_GATE_MASK 0x00000001L
++//DSI_PG_STATUS
++#define DSI_PG_STATUS__DSI_DESIRED_PWR_STATE__SHIFT 0x1c
++#define DSI_PG_STATUS__DSI_PGFSM_PWR_STATUS__SHIFT 0x1e
++#define DSI_PG_STATUS__DSI_DESIRED_PWR_STATE_MASK 0x10000000L
++#define DSI_PG_STATUS__DSI_PGFSM_PWR_STATUS_MASK 0xC0000000L
++//DCFEV0_PG_CONFIG
++#define DCFEV0_PG_CONFIG__DCFEV0_POWER_FORCEON__SHIFT 0x0
++#define DCFEV0_PG_CONFIG__DCFEV0_POWER_FORCEON_MASK 0x00000001L
++//DCFEV0_PG_ENABLE
++#define DCFEV0_PG_ENABLE__DCFEV0_POWER_GATE__SHIFT 0x0
++#define DCFEV0_PG_ENABLE__DCFEV0_POWER_GATE_MASK 0x00000001L
++//DCFEV0_PG_STATUS
++#define DCFEV0_PG_STATUS__DCFEV0_DESIRED_PWR_STATE__SHIFT 0x1c
++#define DCFEV0_PG_STATUS__DCFEV0_PGFSM_PWR_STATUS__SHIFT 0x1e
++#define DCFEV0_PG_STATUS__DCFEV0_DESIRED_PWR_STATE_MASK 0x10000000L
++#define DCFEV0_PG_STATUS__DCFEV0_PGFSM_PWR_STATUS_MASK 0xC0000000L
++//DCPG_INTERRUPT_STATUS
++#define DCPG_INTERRUPT_STATUS__DCFE0_POWER_UP_INT_OCCURRED__SHIFT 0x0
++#define DCPG_INTERRUPT_STATUS__DCFE0_POWER_DOWN_INT_OCCURRED__SHIFT 0x1
++#define DCPG_INTERRUPT_STATUS__DCFE1_POWER_UP_INT_OCCURRED__SHIFT 0x2
++#define DCPG_INTERRUPT_STATUS__DCFE1_POWER_DOWN_INT_OCCURRED__SHIFT 0x3
++#define DCPG_INTERRUPT_STATUS__DCFE2_POWER_UP_INT_OCCURRED__SHIFT 0x4
++#define DCPG_INTERRUPT_STATUS__DCFE2_POWER_DOWN_INT_OCCURRED__SHIFT 0x5
++#define DCPG_INTERRUPT_STATUS__DCFE3_POWER_UP_INT_OCCURRED__SHIFT 0x6
++#define DCPG_INTERRUPT_STATUS__DCFE3_POWER_DOWN_INT_OCCURRED__SHIFT 0x7
++#define DCPG_INTERRUPT_STATUS__DCFE4_POWER_UP_INT_OCCURRED__SHIFT 0x8
++#define DCPG_INTERRUPT_STATUS__DCFE4_POWER_DOWN_INT_OCCURRED__SHIFT 0x9
++#define DCPG_INTERRUPT_STATUS__DCFE5_POWER_UP_INT_OCCURRED__SHIFT 0xa
++#define DCPG_INTERRUPT_STATUS__DCFE5_POWER_DOWN_INT_OCCURRED__SHIFT 0xb
++#define DCPG_INTERRUPT_STATUS__DCFEV0_POWER_UP_INT_OCCURRED__SHIFT 0xc
++#define DCPG_INTERRUPT_STATUS__DCFEV0_POWER_DOWN_INT_OCCURRED__SHIFT 0xd
++#define DCPG_INTERRUPT_STATUS__DSI_POWER_UP_INT_OCCURRED__SHIFT 0xe
++#define DCPG_INTERRUPT_STATUS__DSI_POWER_DOWN_INT_OCCURRED__SHIFT 0xf
++#define DCPG_INTERRUPT_STATUS__DCFEV1_POWER_UP_INT_OCCURRED__SHIFT 0x10
++#define DCPG_INTERRUPT_STATUS__DCFEV1_POWER_DOWN_INT_OCCURRED__SHIFT 0x11
++#define DCPG_INTERRUPT_STATUS__DCFE0_POWER_UP_INT_OCCURRED_MASK 0x00000001L
++#define DCPG_INTERRUPT_STATUS__DCFE0_POWER_DOWN_INT_OCCURRED_MASK 0x00000002L
++#define DCPG_INTERRUPT_STATUS__DCFE1_POWER_UP_INT_OCCURRED_MASK 0x00000004L
++#define DCPG_INTERRUPT_STATUS__DCFE1_POWER_DOWN_INT_OCCURRED_MASK 0x00000008L
++#define DCPG_INTERRUPT_STATUS__DCFE2_POWER_UP_INT_OCCURRED_MASK 0x00000010L
++#define DCPG_INTERRUPT_STATUS__DCFE2_POWER_DOWN_INT_OCCURRED_MASK 0x00000020L
++#define DCPG_INTERRUPT_STATUS__DCFE3_POWER_UP_INT_OCCURRED_MASK 0x00000040L
++#define DCPG_INTERRUPT_STATUS__DCFE3_POWER_DOWN_INT_OCCURRED_MASK 0x00000080L
++#define DCPG_INTERRUPT_STATUS__DCFE4_POWER_UP_INT_OCCURRED_MASK 0x00000100L
++#define DCPG_INTERRUPT_STATUS__DCFE4_POWER_DOWN_INT_OCCURRED_MASK 0x00000200L
++#define DCPG_INTERRUPT_STATUS__DCFE5_POWER_UP_INT_OCCURRED_MASK 0x00000400L
++#define DCPG_INTERRUPT_STATUS__DCFE5_POWER_DOWN_INT_OCCURRED_MASK 0x00000800L
++#define DCPG_INTERRUPT_STATUS__DCFEV0_POWER_UP_INT_OCCURRED_MASK 0x00001000L
++#define DCPG_INTERRUPT_STATUS__DCFEV0_POWER_DOWN_INT_OCCURRED_MASK 0x00002000L
++#define DCPG_INTERRUPT_STATUS__DSI_POWER_UP_INT_OCCURRED_MASK 0x00004000L
++#define DCPG_INTERRUPT_STATUS__DSI_POWER_DOWN_INT_OCCURRED_MASK 0x00008000L
++#define DCPG_INTERRUPT_STATUS__DCFEV1_POWER_UP_INT_OCCURRED_MASK 0x00010000L
++#define DCPG_INTERRUPT_STATUS__DCFEV1_POWER_DOWN_INT_OCCURRED_MASK 0x00020000L
++//DCPG_INTERRUPT_CONTROL
++#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_UP_INT_MASK__SHIFT 0x0
++#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_UP_INT_CLEAR__SHIFT 0x1
++#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_MASK__SHIFT 0x2
++#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_CLEAR__SHIFT 0x3
++#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_MASK__SHIFT 0x4
++#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_CLEAR__SHIFT 0x5
++#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_DOWN_INT_MASK__SHIFT 0x6
++#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_DOWN_INT_CLEAR__SHIFT 0x7
++#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_MASK__SHIFT 0x8
++#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_CLEAR__SHIFT 0x9
++#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_MASK__SHIFT 0xa
++#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_CLEAR__SHIFT 0xb
++#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_UP_INT_MASK__SHIFT 0xc
++#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_UP_INT_CLEAR__SHIFT 0xd
++#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_DOWN_INT_MASK__SHIFT 0xe
++#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_DOWN_INT_CLEAR__SHIFT 0xf
++#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_MASK__SHIFT 0x10
++#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_CLEAR__SHIFT 0x11
++#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_DOWN_INT_MASK__SHIFT 0x12
++#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_DOWN_INT_CLEAR__SHIFT 0x13
++#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_UP_INT_MASK__SHIFT 0x14
++#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_UP_INT_CLEAR__SHIFT 0x15
++#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_DOWN_INT_MASK__SHIFT 0x16
++#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_DOWN_INT_CLEAR__SHIFT 0x17
++#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_UP_INT_MASK__SHIFT 0x18
++#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_UP_INT_CLEAR__SHIFT 0x19
++#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_DOWN_INT_MASK__SHIFT 0x1a
++#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_DOWN_INT_CLEAR__SHIFT 0x1b
++#define DCPG_INTERRUPT_CONTROL__DSI_POWER_UP_INT_MASK__SHIFT 0x1c
++#define DCPG_INTERRUPT_CONTROL__DSI_POWER_UP_INT_CLEAR__SHIFT 0x1d
++#define DCPG_INTERRUPT_CONTROL__DSI_POWER_DOWN_INT_MASK__SHIFT 0x1e
++#define DCPG_INTERRUPT_CONTROL__DSI_POWER_DOWN_INT_CLEAR__SHIFT 0x1f
++#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_UP_INT_MASK_MASK 0x00000001L
++#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_UP_INT_CLEAR_MASK 0x00000002L
++#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_MASK_MASK 0x00000004L
++#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_CLEAR_MASK 0x00000008L
++#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_MASK_MASK 0x00000010L
++#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_CLEAR_MASK 0x00000020L
++#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_DOWN_INT_MASK_MASK 0x00000040L
++#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_DOWN_INT_CLEAR_MASK 0x00000080L
++#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_MASK_MASK 0x00000100L
++#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_CLEAR_MASK 0x00000200L
++#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_MASK_MASK 0x00000400L
++#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_CLEAR_MASK 0x00000800L
++#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_UP_INT_MASK_MASK 0x00001000L
++#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_UP_INT_CLEAR_MASK 0x00002000L
++#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_DOWN_INT_MASK_MASK 0x00004000L
++#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_DOWN_INT_CLEAR_MASK 0x00008000L
++#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_MASK_MASK 0x00010000L
++#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_CLEAR_MASK 0x00020000L
++#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_DOWN_INT_MASK_MASK 0x00040000L
++#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_DOWN_INT_CLEAR_MASK 0x00080000L
++#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_UP_INT_MASK_MASK 0x00100000L
++#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_UP_INT_CLEAR_MASK 0x00200000L
++#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_DOWN_INT_MASK_MASK 0x00400000L
++#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_DOWN_INT_CLEAR_MASK 0x00800000L
++#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_UP_INT_MASK_MASK 0x01000000L
++#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_UP_INT_CLEAR_MASK 0x02000000L
++#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_DOWN_INT_MASK_MASK 0x04000000L
++#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_DOWN_INT_CLEAR_MASK 0x08000000L
++#define DCPG_INTERRUPT_CONTROL__DSI_POWER_UP_INT_MASK_MASK 0x10000000L
++#define DCPG_INTERRUPT_CONTROL__DSI_POWER_UP_INT_CLEAR_MASK 0x20000000L
++#define DCPG_INTERRUPT_CONTROL__DSI_POWER_DOWN_INT_MASK_MASK 0x40000000L
++#define DCPG_INTERRUPT_CONTROL__DSI_POWER_DOWN_INT_CLEAR_MASK 0x80000000L
++//DCPG_INTERRUPT_CONTROL2
++#define DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_UP_INT_MASK__SHIFT 0x18
++#define DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_UP_INT_CLEAR__SHIFT 0x19
++#define DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_DOWN_INT_MASK__SHIFT 0x1a
++#define DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_DOWN_INT_CLEAR__SHIFT 0x1b
++#define DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_UP_INT_MASK_MASK 0x01000000L
++#define DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_UP_INT_CLEAR_MASK 0x02000000L
++#define DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_DOWN_INT_MASK_MASK 0x04000000L
++#define DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_DOWN_INT_CLEAR_MASK 0x08000000L
++//DCFEV1_PG_CONFIG
++#define DCFEV1_PG_CONFIG__DCFEV1_POWER_FORCEON__SHIFT 0x0
++#define DCFEV1_PG_CONFIG__DCFEV1_POWER_FORCEON_MASK 0x00000001L
++//DCFEV1_PG_ENABLE
++#define DCFEV1_PG_ENABLE__DCFEV1_POWER_GATE__SHIFT 0x0
++#define DCFEV1_PG_ENABLE__DCFEV1_POWER_GATE_MASK 0x00000001L
++//DCFEV1_PG_STATUS
++#define DCFEV1_PG_STATUS__DCFEV1_DESIRED_PWR_STATE__SHIFT 0x1c
++#define DCFEV1_PG_STATUS__DCFEV1_PGFSM_PWR_STATUS__SHIFT 0x1e
++#define DCFEV1_PG_STATUS__DCFEV1_DESIRED_PWR_STATE_MASK 0x10000000L
++#define DCFEV1_PG_STATUS__DCFEV1_PGFSM_PWR_STATUS_MASK 0xC0000000L
++//DC_IP_REQUEST_CNTL
++#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT 0x0
++#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK 0x00000001L
++//DC_PGCNTL_STATUS_REG
++//DMIFV_STATUS
++#define DMIFV_STATUS__DMIFV_MC_SEND_ON_IDLE__SHIFT 0x0
++#define DMIFV_STATUS__DMIFV_CLEAR_MC_SEND_ON_IDLE__SHIFT 0x8
++#define DMIFV_STATUS__DMIFV_MC_SEND_ON_IDLE_MASK 0x0000000FL
++#define DMIFV_STATUS__DMIFV_CLEAR_MC_SEND_ON_IDLE_MASK 0x00000F00L
++//DMIF_CONTROL
++#define DMIF_CONTROL__DMIF_BUFF_SIZE__SHIFT 0x0
++#define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK__SHIFT 0x2
++#define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT__SHIFT 0x4
++#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE__SHIFT 0x8
++#define DMIF_CONTROL__DMIF_UNDERFLOW_RECOVERY_EN__SHIFT 0xb
++#define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE__SHIFT 0xc
++#define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS__SHIFT 0x11
++#define DMIF_CONTROL__DMIF_DELAY_ARBITRATION__SHIFT 0x18
++#define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN__SHIFT 0x1d
++#define DMIF_CONTROL__DMIF_PSTATE_URGENT_DISABLE__SHIFT 0x1f
++#define DMIF_CONTROL__DMIF_BUFF_SIZE_MASK 0x00000003L
++#define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK_MASK 0x00000004L
++#define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT_MASK 0x00000010L
++#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE_MASK 0x00000700L
++#define DMIF_CONTROL__DMIF_UNDERFLOW_RECOVERY_EN_MASK 0x00000800L
++#define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE_MASK 0x0001F000L
++#define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS_MASK 0x007E0000L
++#define DMIF_CONTROL__DMIF_DELAY_ARBITRATION_MASK 0x1F000000L
++#define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN_MASK 0x60000000L
++#define DMIF_CONTROL__DMIF_PSTATE_URGENT_DISABLE_MASK 0x80000000L
++//DMIF_STATUS
++#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE__SHIFT 0x0
++#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE__SHIFT 0x8
++#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0xf
++#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x10
++#define DMIF_STATUS__DMIF_PIPE_EN_FBC_CHUNK_TRACKER__SHIFT 0x11
++#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT__SHIFT 0x14
++#define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT__SHIFT 0x18
++#define DMIF_STATUS__DMIF_UNDERFLOW__SHIFT 0x1c
++#define DMIF_STATUS__DMIF_MC_LATENCY_TAP_POINT__SHIFT 0x1d
++#define DMIF_STATUS__DMIF_MC_LATENCY_REQ_TYPE__SHIFT 0x1f
++#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE_MASK 0x0000003FL
++#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE_MASK 0x00003F00L
++#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x00008000L
++#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x00010000L
++#define DMIF_STATUS__DMIF_PIPE_EN_FBC_CHUNK_TRACKER_MASK 0x000E0000L
++#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT_MASK 0x00F00000L
++#define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT_MASK 0x0F000000L
++#define DMIF_STATUS__DMIF_UNDERFLOW_MASK 0x10000000L
++#define DMIF_STATUS__DMIF_MC_LATENCY_TAP_POINT_MASK 0x60000000L
++#define DMIF_STATUS__DMIF_MC_LATENCY_REQ_TYPE_MASK 0x80000000L
++//DMIF_ARBITRATION_CONTROL
++#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD__SHIFT 0x0
++#define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT__SHIFT 0x10
++#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD_MASK 0x0000FFFFL
++#define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT_MASK 0xFFFF0000L
++//PIPE0_ARBITRATION_CONTROL3
++#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
++#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000FFFFL
++//PIPE1_ARBITRATION_CONTROL3
++#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
++#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000FFFFL
++//PIPE2_ARBITRATION_CONTROL3
++#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
++#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000FFFFL
++//PIPE3_ARBITRATION_CONTROL3
++#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
++#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000FFFFL
++//PIPE4_ARBITRATION_CONTROL3
++#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
++#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000FFFFL
++//PIPE5_ARBITRATION_CONTROL3
++#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
++#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000FFFFL
++//DMIF_P_VMID
++#define DMIF_P_VMID__P_VMID_PIPE0__SHIFT 0x0
++#define DMIF_P_VMID__P_VMID_PIPE1__SHIFT 0x4
++#define DMIF_P_VMID__P_VMID_PIPE2__SHIFT 0x8
++#define DMIF_P_VMID__P_VMID_PIPE3__SHIFT 0xc
++#define DMIF_P_VMID__P_VMID_PIPE4__SHIFT 0x10
++#define DMIF_P_VMID__P_VMID_PIPE5__SHIFT 0x14
++#define DMIF_P_VMID__P_VMID_PIPE6__SHIFT 0x18
++#define DMIF_P_VMID__P_VMID_PIPE7__SHIFT 0x1c
++#define DMIF_P_VMID__P_VMID_PIPE0_MASK 0x0000000FL
++#define DMIF_P_VMID__P_VMID_PIPE1_MASK 0x000000F0L
++#define DMIF_P_VMID__P_VMID_PIPE2_MASK 0x00000F00L
++#define DMIF_P_VMID__P_VMID_PIPE3_MASK 0x0000F000L
++#define DMIF_P_VMID__P_VMID_PIPE4_MASK 0x000F0000L
++#define DMIF_P_VMID__P_VMID_PIPE5_MASK 0x00F00000L
++#define DMIF_P_VMID__P_VMID_PIPE6_MASK 0x0F000000L
++#define DMIF_P_VMID__P_VMID_PIPE7_MASK 0xF0000000L
++//DMIF_ADDR_CALC
++#define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE__SHIFT 0x3
++#define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE__SHIFT 0x1c
++#define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
++#define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE_MASK 0x30000000L
++//DMIF_STATUS2
++#define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS__SHIFT 0x0
++#define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS__SHIFT 0x1
++#define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS__SHIFT 0x2
++#define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS__SHIFT 0x3
++#define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS__SHIFT 0x4
++#define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS__SHIFT 0x5
++#define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS__SHIFT 0x8
++#define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS__SHIFT 0x9
++#define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS_MASK 0x00000001L
++#define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS_MASK 0x00000002L
++#define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS_MASK 0x00000004L
++#define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS_MASK 0x00000008L
++#define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS_MASK 0x00000010L
++#define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS_MASK 0x00000020L
++#define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS_MASK 0x00000100L
++#define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS_MASK 0x00000200L
++//PIPE0_MAX_REQUESTS
++#define PIPE0_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
++#define PIPE0_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003FFL
++//PIPE1_MAX_REQUESTS
++#define PIPE1_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
++#define PIPE1_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003FFL
++//PIPE2_MAX_REQUESTS
++#define PIPE2_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
++#define PIPE2_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003FFL
++//PIPE3_MAX_REQUESTS
++#define PIPE3_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
++#define PIPE3_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003FFL
++//PIPE4_MAX_REQUESTS
++#define PIPE4_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
++#define PIPE4_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003FFL
++//PIPE5_MAX_REQUESTS
++#define PIPE5_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
++#define PIPE5_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003FFL
++//LOW_POWER_TILING_CONTROL
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE__SHIFT 0x0
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE__SHIFT 0x3
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES__SHIFT 0x5
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS__SHIFT 0x8
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE__SHIFT 0xb
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE__SHIFT 0xc
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN__SHIFT 0x10
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE_MASK 0x00000001L
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE_MASK 0x00000018L
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES_MASK 0x000000E0L
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS_MASK 0x00000700L
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE_MASK 0x00000800L
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE_MASK 0x00007000L
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN_MASK 0x0FFF0000L
++//MCIF_CONTROL
++#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x1e
++#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x1f
++#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x40000000L
++#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x80000000L
++//MCIF_WRITE_COMBINE_CONTROL
++#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT 0x0
++#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK 0x000003FFL
++//MCIF_PHASE0_OUTSTANDING_COUNTER
++#define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER__SHIFT 0x0
++#define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL
++//CC_DC_PIPE_DIS
++#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT 0x1
++#define CC_DC_PIPE_DIS__DC_UNDERLAY_PIPE_DIS__SHIFT 0x10
++#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK 0x0000007EL
++#define CC_DC_PIPE_DIS__DC_UNDERLAY_PIPE_DIS_MASK 0x003F0000L
++//SMU_WM_CONTROL
++#define SMU_WM_CONTROL__DMIF_WM_CHG_SEL__SHIFT 0x0
++#define SMU_WM_CONTROL__DMIF_WM_CHG_REQ__SHIFT 0x2
++#define SMU_WM_CONTROL__DMIF_WM_CHG_ACK_INT_DIS__SHIFT 0x10
++#define SMU_WM_CONTROL__DMIF_WM_CHG_ACK_INT_STATUS__SHIFT 0x11
++#define SMU_WM_CONTROL__MCIF_WB_WM_CHG_SEL__SHIFT 0x14
++#define SMU_WM_CONTROL__MCIF_WB_WM_CHG_REQ__SHIFT 0x16
++#define SMU_WM_CONTROL__MCIF_WB_WM_CHG_ACK_INT_DIS__SHIFT 0x18
++#define SMU_WM_CONTROL__MCIF_WB_WM_CHG_ACK_INT_STATUS__SHIFT 0x19
++#define SMU_WM_CONTROL__DMIF_WM_CHG_SEL_MASK 0x00000003L
++#define SMU_WM_CONTROL__DMIF_WM_CHG_REQ_MASK 0x00000004L
++#define SMU_WM_CONTROL__DMIF_WM_CHG_ACK_INT_DIS_MASK 0x00010000L
++#define SMU_WM_CONTROL__DMIF_WM_CHG_ACK_INT_STATUS_MASK 0x00020000L
++#define SMU_WM_CONTROL__MCIF_WB_WM_CHG_SEL_MASK 0x00300000L
++#define SMU_WM_CONTROL__MCIF_WB_WM_CHG_REQ_MASK 0x00400000L
++#define SMU_WM_CONTROL__MCIF_WB_WM_CHG_ACK_INT_DIS_MASK 0x01000000L
++#define SMU_WM_CONTROL__MCIF_WB_WM_CHG_ACK_INT_STATUS_MASK 0x02000000L
++//RBBMIF_TIMEOUT
++#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT 0x0
++#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD__SHIFT 0x14
++#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK 0x000FFFFFL
++#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD_MASK 0xFFF00000L
++//RBBMIF_STATUS
++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT 0x0
++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_OP__SHIFT 0x1c
++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT 0x1d
++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT 0x1e
++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT 0x1f
++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK 0x0000FFFFL
++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_OP_MASK 0x10000000L
++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK 0x20000000L
++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK_MASK 0x40000000L
++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK_MASK 0x80000000L
++//RBBMIF_TIMEOUT_DIS
++#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT 0x0
++#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT 0x1
++#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT 0x2
++#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT 0x3
++#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS__SHIFT 0x4
++#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS__SHIFT 0x5
++#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS__SHIFT 0x6
++#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS__SHIFT 0x7
++#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS__SHIFT 0x8
++#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS__SHIFT 0x9
++#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS__SHIFT 0xa
++#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS__SHIFT 0xb
++#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS__SHIFT 0xc
++#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS__SHIFT 0xd
++#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS__SHIFT 0xe
++#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS__SHIFT 0xf
++#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK 0x00000001L
++#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK 0x00000002L
++#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK 0x00000004L
++#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK 0x00000008L
++#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS_MASK 0x00000010L
++#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS_MASK 0x00000020L
++#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS_MASK 0x00000040L
++#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS_MASK 0x00000080L
++#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS_MASK 0x00000100L
++#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS_MASK 0x00000200L
++#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS_MASK 0x00000400L
++#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK 0x00000800L
++#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS_MASK 0x00001000L
++#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS_MASK 0x00002000L
++#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS_MASK 0x00004000L
++#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS_MASK 0x00008000L
++//DCI_MEM_PWR_STATUS
++#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM1_PWR_STATE__SHIFT 0x0
++#define DCI_MEM_PWR_STATUS__VGA_MEM_PWR_STATE__SHIFT 0x8
++#define DCI_MEM_PWR_STATUS__DMCU_ERAM_MEM_PWR_STATE__SHIFT 0x9
++#define DCI_MEM_PWR_STATUS__DMCU_IRAM_MEM_PWR_STATE__SHIFT 0xb
++#define DCI_MEM_PWR_STATUS__FBC_MEM_PWR_STATE__SHIFT 0xc
++#define DCI_MEM_PWR_STATUS__DMIF_CURSOR_MEM_PWR_STATE__SHIFT 0x10
++#define DCI_MEM_PWR_STATUS__DMIF_CURSOR_RD_REQ_MEM_PWR_STATE__SHIFT 0x12
++#define DCI_MEM_PWR_STATUS__VIP_MEM_PWR_STATE__SHIFT 0x16
++#define DCI_MEM_PWR_STATUS__DMIF0_ASYNC_MEM_PWR_STATE__SHIFT 0x18
++#define DCI_MEM_PWR_STATUS__DMIF0_DATA_MEM_PWR_STATE__SHIFT 0x1a
++#define DCI_MEM_PWR_STATUS__DMIF0_CHUNK_MEM_PWR_STATE__SHIFT 0x1c
++#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM1_PWR_STATE_MASK 0x00000003L
++#define DCI_MEM_PWR_STATUS__VGA_MEM_PWR_STATE_MASK 0x00000100L
++#define DCI_MEM_PWR_STATUS__DMCU_ERAM_MEM_PWR_STATE_MASK 0x00000600L
++#define DCI_MEM_PWR_STATUS__DMCU_IRAM_MEM_PWR_STATE_MASK 0x00000800L
++#define DCI_MEM_PWR_STATUS__FBC_MEM_PWR_STATE_MASK 0x00003000L
++#define DCI_MEM_PWR_STATUS__DMIF_CURSOR_MEM_PWR_STATE_MASK 0x00030000L
++#define DCI_MEM_PWR_STATUS__DMIF_CURSOR_RD_REQ_MEM_PWR_STATE_MASK 0x000C0000L
++#define DCI_MEM_PWR_STATUS__VIP_MEM_PWR_STATE_MASK 0x00400000L
++#define DCI_MEM_PWR_STATUS__DMIF0_ASYNC_MEM_PWR_STATE_MASK 0x03000000L
++#define DCI_MEM_PWR_STATUS__DMIF0_DATA_MEM_PWR_STATE_MASK 0x0C000000L
++#define DCI_MEM_PWR_STATUS__DMIF0_CHUNK_MEM_PWR_STATE_MASK 0x10000000L
++//DCI_MEM_PWR_STATUS2
++#define DCI_MEM_PWR_STATUS2__DMIF1_ASYNC_MEM_PWR_STATE__SHIFT 0x0
++#define DCI_MEM_PWR_STATUS2__DMIF1_DATA_MEM_PWR_STATE__SHIFT 0x2
++#define DCI_MEM_PWR_STATUS2__DMIF1_CHUNK_MEM_PWR_STATE__SHIFT 0x4
++#define DCI_MEM_PWR_STATUS2__DMIF2_ASYNC_MEM_PWR_STATE__SHIFT 0x5
++#define DCI_MEM_PWR_STATUS2__DMIF2_DATA_MEM_PWR_STATE__SHIFT 0x7
++#define DCI_MEM_PWR_STATUS2__DMIF2_CHUNK_MEM_PWR_STATE__SHIFT 0x9
++#define DCI_MEM_PWR_STATUS2__DMIF3_ASYNC_MEM_PWR_STATE__SHIFT 0xa
++#define DCI_MEM_PWR_STATUS2__DMIF3_DATA_MEM_PWR_STATE__SHIFT 0xc
++#define DCI_MEM_PWR_STATUS2__DMIF3_CHUNK_MEM_PWR_STATE__SHIFT 0xe
++#define DCI_MEM_PWR_STATUS2__DMIF4_ASYNC_MEM_PWR_STATE__SHIFT 0xf
++#define DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE__SHIFT 0x11
++#define DCI_MEM_PWR_STATUS2__DMIF4_CHUNK_MEM_PWR_STATE__SHIFT 0x13
++#define DCI_MEM_PWR_STATUS2__DMIF5_ASYNC_MEM_PWR_STATE__SHIFT 0x14
++#define DCI_MEM_PWR_STATUS2__DMIF5_DATA_MEM_PWR_STATE__SHIFT 0x16
++#define DCI_MEM_PWR_STATUS2__DMIF5_CHUNK_MEM_PWR_STATE__SHIFT 0x18
++#define DCI_MEM_PWR_STATUS2__DMIF1_ASYNC_MEM_PWR_STATE_MASK 0x00000003L
++#define DCI_MEM_PWR_STATUS2__DMIF1_DATA_MEM_PWR_STATE_MASK 0x0000000CL
++#define DCI_MEM_PWR_STATUS2__DMIF1_CHUNK_MEM_PWR_STATE_MASK 0x00000010L
++#define DCI_MEM_PWR_STATUS2__DMIF2_ASYNC_MEM_PWR_STATE_MASK 0x00000060L
++#define DCI_MEM_PWR_STATUS2__DMIF2_DATA_MEM_PWR_STATE_MASK 0x00000180L
++#define DCI_MEM_PWR_STATUS2__DMIF2_CHUNK_MEM_PWR_STATE_MASK 0x00000200L
++#define DCI_MEM_PWR_STATUS2__DMIF3_ASYNC_MEM_PWR_STATE_MASK 0x00000C00L
++#define DCI_MEM_PWR_STATUS2__DMIF3_DATA_MEM_PWR_STATE_MASK 0x00003000L
++#define DCI_MEM_PWR_STATUS2__DMIF3_CHUNK_MEM_PWR_STATE_MASK 0x00004000L
++#define DCI_MEM_PWR_STATUS2__DMIF4_ASYNC_MEM_PWR_STATE_MASK 0x00018000L
++#define DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE_MASK 0x00060000L
++#define DCI_MEM_PWR_STATUS2__DMIF4_CHUNK_MEM_PWR_STATE_MASK 0x00080000L
++#define DCI_MEM_PWR_STATUS2__DMIF5_ASYNC_MEM_PWR_STATE_MASK 0x00300000L
++#define DCI_MEM_PWR_STATUS2__DMIF5_DATA_MEM_PWR_STATE_MASK 0x00C00000L
++#define DCI_MEM_PWR_STATUS2__DMIF5_CHUNK_MEM_PWR_STATE_MASK 0x01000000L
++//DCI_CLK_CNTL
++#define DCI_CLK_CNTL__DCI_TEST_CLK_SEL__SHIFT 0x0
++#define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS__SHIFT 0x5
++#define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS__SHIFT 0x6
++#define DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT 0x7
++#define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT 0x8
++#define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS__SHIFT 0x9
++#define DCI_CLK_CNTL__DISPCLK_G_DMIFV1_L_GATE_DIS__SHIFT 0xa
++#define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT 0xb
++#define DCI_CLK_CNTL__DISPCLK_G_DMIFV1_C_GATE_DIS__SHIFT 0xc
++#define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS__SHIFT 0xd
++#define DCI_CLK_CNTL__VPCLK_POL__SHIFT 0xe
++#define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT 0xf
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS__SHIFT 0x10
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS__SHIFT 0x11
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS__SHIFT 0x12
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS__SHIFT 0x13
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS__SHIFT 0x14
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS__SHIFT 0x15
++#define DCI_CLK_CNTL__DCEFCLK_G_DMIF_FBCTRK_GATE_DIS__SHIFT 0x16
++#define DCI_CLK_CNTL__DCEFCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x17
++#define DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT 0x18
++#define DCI_CLK_CNTL__DISPCLK_G_DMIFV0_L_GATE_DIS__SHIFT 0x19
++#define DCI_CLK_CNTL__DISPCLK_G_DMIFV0_C_GATE_DIS__SHIFT 0x1a
++#define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL__SHIFT 0x1b
++#define DCI_CLK_CNTL__DCI_TEST_CLK_SEL_MASK 0x0000001FL
++#define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS_MASK 0x00000020L
++#define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS_MASK 0x00000040L
++#define DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK 0x00000080L
++#define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS_MASK 0x00000100L
++#define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS_MASK 0x00000200L
++#define DCI_CLK_CNTL__DISPCLK_G_DMIFV1_L_GATE_DIS_MASK 0x00000400L
++#define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x00000800L
++#define DCI_CLK_CNTL__DISPCLK_G_DMIFV1_C_GATE_DIS_MASK 0x00001000L
++#define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS_MASK 0x00002000L
++#define DCI_CLK_CNTL__VPCLK_POL_MASK 0x00004000L
++#define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK 0x00008000L
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS_MASK 0x00010000L
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS_MASK 0x00020000L
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS_MASK 0x00040000L
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS_MASK 0x00080000L
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS_MASK 0x00100000L
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS_MASK 0x00200000L
++#define DCI_CLK_CNTL__DCEFCLK_G_DMIF_FBCTRK_GATE_DIS_MASK 0x00400000L
++#define DCI_CLK_CNTL__DCEFCLK_G_DMIFTRK_GATE_DIS_MASK 0x00800000L
++#define DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK 0x01000000L
++#define DCI_CLK_CNTL__DISPCLK_G_DMIFV0_L_GATE_DIS_MASK 0x02000000L
++#define DCI_CLK_CNTL__DISPCLK_G_DMIFV0_C_GATE_DIS_MASK 0x04000000L
++#define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL_MASK 0xF8000000L
++//DCI_CLK_CNTL2
++#define DCI_CLK_CNTL2__DISPCLK_G_MCIF_DWB_GATE_DIS__SHIFT 0x0
++#define DCI_CLK_CNTL2__SCLK_G_MCIF_DWB_GATE_DIS__SHIFT 0x1
++#define DCI_CLK_CNTL2__DISPCLK_G_MCIF_CWB0_GATE_DIS__SHIFT 0x2
++#define DCI_CLK_CNTL2__SCLK_G_MCIF_CWB0_GATE_DIS__SHIFT 0x3
++#define DCI_CLK_CNTL2__DISPCLK_G_MCIF_CWB1_GATE_DIS__SHIFT 0x4
++#define DCI_CLK_CNTL2__DCEFCLK_GATE_DIS__SHIFT 0x5
++#define DCI_CLK_CNTL2__DCEFCLK_TURN_ON_DELAY__SHIFT 0x8
++#define DCI_CLK_CNTL2__DCEFCLK_TURN_OFF_DELAY__SHIFT 0xc
++#define DCI_CLK_CNTL2__CGTT_DCEFCLK_OVERRIDE__SHIFT 0x14
++#define DCI_CLK_CNTL2__SCLK_G_MCIF_CWB1_GATE_DIS__SHIFT 0x1f
++#define DCI_CLK_CNTL2__DISPCLK_G_MCIF_DWB_GATE_DIS_MASK 0x00000001L
++#define DCI_CLK_CNTL2__SCLK_G_MCIF_DWB_GATE_DIS_MASK 0x00000002L
++#define DCI_CLK_CNTL2__DISPCLK_G_MCIF_CWB0_GATE_DIS_MASK 0x00000004L
++#define DCI_CLK_CNTL2__SCLK_G_MCIF_CWB0_GATE_DIS_MASK 0x00000008L
++#define DCI_CLK_CNTL2__DISPCLK_G_MCIF_CWB1_GATE_DIS_MASK 0x00000010L
++#define DCI_CLK_CNTL2__DCEFCLK_GATE_DIS_MASK 0x00000020L
++#define DCI_CLK_CNTL2__DCEFCLK_TURN_ON_DELAY_MASK 0x00000F00L
++#define DCI_CLK_CNTL2__DCEFCLK_TURN_OFF_DELAY_MASK 0x000FF000L
++#define DCI_CLK_CNTL2__CGTT_DCEFCLK_OVERRIDE_MASK 0x00100000L
++#define DCI_CLK_CNTL2__SCLK_G_MCIF_CWB1_GATE_DIS_MASK 0x80000000L
++//DCI_MEM_PWR_CNTL
++#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_FORCE__SHIFT 0x0
++#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_DIS__SHIFT 0x2
++#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE__SHIFT 0x7
++#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_DIS__SHIFT 0x8
++#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE__SHIFT 0x9
++#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS__SHIFT 0xb
++#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE__SHIFT 0xc
++#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS__SHIFT 0xd
++#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_FORCE__SHIFT 0xe
++#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_DIS__SHIFT 0x10
++#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_FORCE__SHIFT 0x14
++#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_DIS__SHIFT 0x16
++#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_FORCE__SHIFT 0x17
++#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_DIS__SHIFT 0x19
++#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_FORCE__SHIFT 0x1a
++#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_DIS__SHIFT 0x1c
++#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_FORCE__SHIFT 0x1d
++#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_DIS__SHIFT 0x1e
++#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_FORCE_MASK 0x00000003L
++#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_DIS_MASK 0x00000004L
++#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE_MASK 0x00000080L
++#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_DIS_MASK 0x00000100L
++#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE_MASK 0x00000600L
++#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS_MASK 0x00000800L
++#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE_MASK 0x00001000L
++#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS_MASK 0x00002000L
++#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_FORCE_MASK 0x0000C000L
++#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_DIS_MASK 0x00010000L
++#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_FORCE_MASK 0x00300000L
++#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_DIS_MASK 0x00400000L
++#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_FORCE_MASK 0x01800000L
++#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_DIS_MASK 0x02000000L
++#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_FORCE_MASK 0x0C000000L
++#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_DIS_MASK 0x10000000L
++#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_FORCE_MASK 0x20000000L
++#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_DIS_MASK 0x40000000L
++//DCI_MEM_PWR_CNTL2
++#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_FORCE__SHIFT 0x0
++#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_DIS__SHIFT 0x2
++#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_FORCE__SHIFT 0x3
++#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_DIS__SHIFT 0x5
++#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_FORCE__SHIFT 0x6
++#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_DIS__SHIFT 0x7
++#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_FORCE__SHIFT 0x8
++#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_DIS__SHIFT 0xa
++#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_FORCE__SHIFT 0xb
++#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_DIS__SHIFT 0xd
++#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_FORCE__SHIFT 0xe
++#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_DIS__SHIFT 0xf
++#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_FORCE__SHIFT 0x10
++#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_DIS__SHIFT 0x12
++#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_FORCE__SHIFT 0x13
++#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_DIS__SHIFT 0x15
++#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_FORCE__SHIFT 0x16
++#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_DIS__SHIFT 0x17
++#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_FORCE__SHIFT 0x18
++#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_DIS__SHIFT 0x1a
++#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_FORCE__SHIFT 0x1b
++#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_DIS__SHIFT 0x1d
++#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_FORCE__SHIFT 0x1e
++#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_DIS__SHIFT 0x1f
++#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_FORCE_MASK 0x00000003L
++#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_DIS_MASK 0x00000004L
++#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_FORCE_MASK 0x00000018L
++#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_DIS_MASK 0x00000020L
++#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_FORCE_MASK 0x00000040L
++#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_DIS_MASK 0x00000080L
++#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_FORCE_MASK 0x00000300L
++#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_DIS_MASK 0x00000400L
++#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_FORCE_MASK 0x00001800L
++#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_DIS_MASK 0x00002000L
++#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_FORCE_MASK 0x00004000L
++#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_DIS_MASK 0x00008000L
++#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_FORCE_MASK 0x00030000L
++#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_DIS_MASK 0x00040000L
++#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_FORCE_MASK 0x00180000L
++#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_DIS_MASK 0x00200000L
++#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_FORCE_MASK 0x00400000L
++#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_DIS_MASK 0x00800000L
++#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_FORCE_MASK 0x03000000L
++#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_DIS_MASK 0x04000000L
++#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_FORCE_MASK 0x18000000L
++#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_DIS_MASK 0x20000000L
++#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_FORCE_MASK 0x40000000L
++#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_DIS_MASK 0x80000000L
++//DCI_MEM_PWR_CNTL3
++#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_FORCE__SHIFT 0x0
++#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_DIS__SHIFT 0x2
++#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_FORCE__SHIFT 0x3
++#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_DIS__SHIFT 0x5
++#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_FORCE__SHIFT 0x6
++#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_DIS__SHIFT 0x7
++#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_FORCE__SHIFT 0x8
++#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_DIS__SHIFT 0xa
++#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_FORCE__SHIFT 0xb
++#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_DIS__SHIFT 0xd
++#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_FORCE__SHIFT 0xe
++#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_DIS__SHIFT 0xf
++#define DCI_MEM_PWR_CNTL3__DMIF_RDREQ_MEM_PWR_MODE_SEL__SHIFT 0x10
++#define DCI_MEM_PWR_CNTL3__DMIF_ASYNC_MEM_PWR_MODE_SEL__SHIFT 0x12
++#define DCI_MEM_PWR_CNTL3__DMIF_DATA_MEM_PWR_MODE_SEL__SHIFT 0x14
++#define DCI_MEM_PWR_CNTL3__DMCU_ERAM_MEM_PWR_MODE_SEL__SHIFT 0x16
++#define DCI_MEM_PWR_CNTL3__FBC_MEM_PWR_MODE_SEL__SHIFT 0x17
++#define DCI_MEM_PWR_CNTL3__MCIF_CWB0_MEM_PWR_MODE_SEL__SHIFT 0x19
++#define DCI_MEM_PWR_CNTL3__MCIF_CWB1_MEM_PWR_MODE_SEL__SHIFT 0x1b
++#define DCI_MEM_PWR_CNTL3__MCIF_DWB_MEM_PWR_MODE_SEL__SHIFT 0x1d
++#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_FORCE_MASK 0x00000003L
++#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_DIS_MASK 0x00000004L
++#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_FORCE_MASK 0x00000018L
++#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_DIS_MASK 0x00000020L
++#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_FORCE_MASK 0x00000040L
++#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_DIS_MASK 0x00000080L
++#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_FORCE_MASK 0x00000300L
++#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_DIS_MASK 0x00000400L
++#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_FORCE_MASK 0x00001800L
++#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_DIS_MASK 0x00002000L
++#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_FORCE_MASK 0x00004000L
++#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_DIS_MASK 0x00008000L
++#define DCI_MEM_PWR_CNTL3__DMIF_RDREQ_MEM_PWR_MODE_SEL_MASK 0x00030000L
++#define DCI_MEM_PWR_CNTL3__DMIF_ASYNC_MEM_PWR_MODE_SEL_MASK 0x000C0000L
++#define DCI_MEM_PWR_CNTL3__DMIF_DATA_MEM_PWR_MODE_SEL_MASK 0x00300000L
++#define DCI_MEM_PWR_CNTL3__DMCU_ERAM_MEM_PWR_MODE_SEL_MASK 0x00400000L
++#define DCI_MEM_PWR_CNTL3__FBC_MEM_PWR_MODE_SEL_MASK 0x01800000L
++#define DCI_MEM_PWR_CNTL3__MCIF_CWB0_MEM_PWR_MODE_SEL_MASK 0x06000000L
++#define DCI_MEM_PWR_CNTL3__MCIF_CWB1_MEM_PWR_MODE_SEL_MASK 0x18000000L
++#define DCI_MEM_PWR_CNTL3__MCIF_DWB_MEM_PWR_MODE_SEL_MASK 0x60000000L
++//PIPE0_DMIF_BUFFER_CONTROL
++#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
++#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
++#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L
++#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L
++//PIPE1_DMIF_BUFFER_CONTROL
++#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
++#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
++#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L
++#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L
++//PIPE2_DMIF_BUFFER_CONTROL
++#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
++#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
++#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L
++#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L
++//PIPE3_DMIF_BUFFER_CONTROL
++#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
++#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
++#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L
++#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L
++//PIPE4_DMIF_BUFFER_CONTROL
++#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
++#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
++#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L
++#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L
++//PIPE5_DMIF_BUFFER_CONTROL
++#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
++#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
++#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L
++#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L
++//RBBMIF_STATUS_FLAG
++#define RBBMIF_STATUS_FLAG__RBBMIF_STATE__SHIFT 0x0
++#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT__SHIFT 0x4
++#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY__SHIFT 0x5
++#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL__SHIFT 0x6
++#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG__SHIFT 0x8
++#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE__SHIFT 0x9
++#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR__SHIFT 0x10
++#define RBBMIF_STATUS_FLAG__RBBMIF_STATE_MASK 0x00000003L
++#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT_MASK 0x00000010L
++#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY_MASK 0x00000020L
++#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL_MASK 0x00000040L
++#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG_MASK 0x00000100L
++#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE_MASK 0x00000E00L
++#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR_MASK 0xFFFF0000L
++//DCI_SOFT_RESET
++#define DCI_SOFT_RESET__VGA_SOFT_RESET__SHIFT 0x0
++#define DCI_SOFT_RESET__VIP_SOFT_RESET__SHIFT 0x1
++#define DCI_SOFT_RESET__MCIF_SOFT_RESET__SHIFT 0x2
++#define DCI_SOFT_RESET__FBC_SOFT_RESET__SHIFT 0x3
++#define DCI_SOFT_RESET__DMIF0_SOFT_RESET__SHIFT 0x4
++#define DCI_SOFT_RESET__DMIF1_SOFT_RESET__SHIFT 0x5
++#define DCI_SOFT_RESET__DMIF2_SOFT_RESET__SHIFT 0x6
++#define DCI_SOFT_RESET__DMIF3_SOFT_RESET__SHIFT 0x7
++#define DCI_SOFT_RESET__DMIF4_SOFT_RESET__SHIFT 0x8
++#define DCI_SOFT_RESET__DMIF5_SOFT_RESET__SHIFT 0x9
++#define DCI_SOFT_RESET__DCFEV0_L_SOFT_RESET__SHIFT 0xa
++#define DCI_SOFT_RESET__DCFEV0_C_SOFT_RESET__SHIFT 0xb
++#define DCI_SOFT_RESET__DCFEV1_L_SOFT_RESET__SHIFT 0xc
++#define DCI_SOFT_RESET__DCFEV1_C_SOFT_RESET__SHIFT 0xd
++#define DCI_SOFT_RESET__DMIFARB_SOFT_RESET__SHIFT 0xe
++#define DCI_SOFT_RESET__DCHUB_SOFT_RESET__SHIFT 0xf
++#define DCI_SOFT_RESET__MCIF_DWB_SOFT_RESET__SHIFT 0x10
++#define DCI_SOFT_RESET__MCIF_CWB0_SOFT_RESET__SHIFT 0x11
++#define DCI_SOFT_RESET__MCIF_CWB1_SOFT_RESET__SHIFT 0x12
++#define DCI_SOFT_RESET__MCIF_WB_SOFT_RESET__SHIFT 0x13
++#define DCI_SOFT_RESET__VGA_SOFT_RESET_MASK 0x00000001L
++#define DCI_SOFT_RESET__VIP_SOFT_RESET_MASK 0x00000002L
++#define DCI_SOFT_RESET__MCIF_SOFT_RESET_MASK 0x00000004L
++#define DCI_SOFT_RESET__FBC_SOFT_RESET_MASK 0x00000008L
++#define DCI_SOFT_RESET__DMIF0_SOFT_RESET_MASK 0x00000010L
++#define DCI_SOFT_RESET__DMIF1_SOFT_RESET_MASK 0x00000020L
++#define DCI_SOFT_RESET__DMIF2_SOFT_RESET_MASK 0x00000040L
++#define DCI_SOFT_RESET__DMIF3_SOFT_RESET_MASK 0x00000080L
++#define DCI_SOFT_RESET__DMIF4_SOFT_RESET_MASK 0x00000100L
++#define DCI_SOFT_RESET__DMIF5_SOFT_RESET_MASK 0x00000200L
++#define DCI_SOFT_RESET__DCFEV0_L_SOFT_RESET_MASK 0x00000400L
++#define DCI_SOFT_RESET__DCFEV0_C_SOFT_RESET_MASK 0x00000800L
++#define DCI_SOFT_RESET__DCFEV1_L_SOFT_RESET_MASK 0x00001000L
++#define DCI_SOFT_RESET__DCFEV1_C_SOFT_RESET_MASK 0x00002000L
++#define DCI_SOFT_RESET__DMIFARB_SOFT_RESET_MASK 0x00004000L
++#define DCI_SOFT_RESET__DCHUB_SOFT_RESET_MASK 0x00008000L
++#define DCI_SOFT_RESET__MCIF_DWB_SOFT_RESET_MASK 0x00010000L
++#define DCI_SOFT_RESET__MCIF_CWB0_SOFT_RESET_MASK 0x00020000L
++#define DCI_SOFT_RESET__MCIF_CWB1_SOFT_RESET_MASK 0x00040000L
++#define DCI_SOFT_RESET__MCIF_WB_SOFT_RESET_MASK 0x00080000L
++//DMIF_URG_OVERRIDE
++#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_EN__SHIFT 0x0
++#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_LEVEL__SHIFT 0x4
++#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_EN_MASK 0x00000001L
++#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_LEVEL_MASK 0x000000F0L
++//PIPE6_ARBITRATION_CONTROL3
++#define PIPE6_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
++#define PIPE6_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000FFFFL
++//PIPE7_ARBITRATION_CONTROL3
++#define PIPE7_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
++#define PIPE7_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000FFFFL
++//PIPE6_MAX_REQUESTS
++#define PIPE6_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
++#define PIPE6_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003FFL
++//PIPE7_MAX_REQUESTS
++#define PIPE7_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
++#define PIPE7_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003FFL
++//DVMM_REG_RD_STATUS
++#define DVMM_REG_RD_STATUS__DVMM_REG_RD_STATUS__SHIFT 0x0
++#define DVMM_REG_RD_STATUS__DVMM_REG_RD_STATUS_MASK 0x00000001L
++//DVMM_REG_RD_DATA
++#define DVMM_REG_RD_DATA__DVMM_REG_RD_DATA__SHIFT 0x0
++#define DVMM_REG_RD_DATA__DVMM_REG_RD_DATA_MASK 0xFFFFFFFFL
++//DVMM_PTE_REQ
++#define DVMM_PTE_REQ__MAX_PTEREQ_TO_ISSUE__SHIFT 0x0
++#define DVMM_PTE_REQ__HFLIP_PTEREQ_PER_CHUNK_INT__SHIFT 0x8
++#define DVMM_PTE_REQ__HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER__SHIFT 0x10
++#define DVMM_PTE_REQ__MAX_PTEREQ_TO_ISSUE_MASK 0x000000FFL
++#define DVMM_PTE_REQ__HFLIP_PTEREQ_PER_CHUNK_INT_MASK 0x0000FF00L
++#define DVMM_PTE_REQ__HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER_MASK 0x003F0000L
++//DVMM_CNTL
++#define DVMM_CNTL__PDE_CACHE_INVALIDATE_CNTL__SHIFT 0x0
++#define DVMM_CNTL__FORCE_SYSTEM_ACCESS_MODE__SHIFT 0x7
++#define DVMM_CNTL__OVERRIDE_SNOOP__SHIFT 0x11
++#define DVMM_CNTL__ENABLE_PDE_INVALIDATE__SHIFT 0x12
++#define DVMM_CNTL__PDE_CACHE_INVALIDATE_CNTL_MASK 0x00000003L
++#define DVMM_CNTL__FORCE_SYSTEM_ACCESS_MODE_MASK 0x00000080L
++#define DVMM_CNTL__OVERRIDE_SNOOP_MASK 0x00020000L
++#define DVMM_CNTL__ENABLE_PDE_INVALIDATE_MASK 0x00040000L
++//DVMM_FAULT_STATUS
++#define DVMM_FAULT_STATUS__DVMM_FAULT_STATUS__SHIFT 0x0
++#define DVMM_FAULT_STATUS__DVMM_FAULT_STATUS_MASK 0xFFFFFFFFL
++//DVMM_FAULT_ADDR
++#define DVMM_FAULT_ADDR__DVMM_FAULT_ADDR__SHIFT 0x0
++#define DVMM_FAULT_ADDR__DVMM_FAULT_ADDR_MASK 0xFFFFFFFFL
++//FMON_CTRL
++#define FMON_CTRL__FMON_START__SHIFT 0x0
++#define FMON_CTRL__FMON_MODE__SHIFT 0x1
++#define FMON_CTRL__FMON_PSTATE_IGNORE__SHIFT 0x4
++#define FMON_CTRL__FMON_STATUS_IGNORE__SHIFT 0x5
++#define FMON_CTRL__FMON_URG_MODE_GREATER__SHIFT 0x6
++#define FMON_CTRL__FMON_FILTER_UID_EN__SHIFT 0x7
++#define FMON_CTRL__FMON_STATE__SHIFT 0x8
++#define FMON_CTRL__FMON_URG_THRESHOLD__SHIFT 0xc
++#define FMON_CTRL__FMON_FILTER_UID__SHIFT 0x10
++#define FMON_CTRL__FMON_SOF_SEL__SHIFT 0x18
++#define FMON_CTRL__FMON_START_MASK 0x00000001L
++#define FMON_CTRL__FMON_MODE_MASK 0x00000006L
++#define FMON_CTRL__FMON_PSTATE_IGNORE_MASK 0x00000010L
++#define FMON_CTRL__FMON_STATUS_IGNORE_MASK 0x00000020L
++#define FMON_CTRL__FMON_URG_MODE_GREATER_MASK 0x00000040L
++#define FMON_CTRL__FMON_FILTER_UID_EN_MASK 0x00000080L
++#define FMON_CTRL__FMON_STATE_MASK 0x00000300L
++#define FMON_CTRL__FMON_URG_THRESHOLD_MASK 0x0000F000L
++#define FMON_CTRL__FMON_FILTER_UID_MASK 0x001F0000L
++#define FMON_CTRL__FMON_SOF_SEL_MASK 0x07000000L
++//DVMM_PTE_PGMEM_CONTROL
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE0_MEM_PWR_FORCE__SHIFT 0x0
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE0_MEM_PWR_DIS__SHIFT 0x2
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE1_MEM_PWR_FORCE__SHIFT 0x3
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE1_MEM_PWR_DIS__SHIFT 0x5
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE2_MEM_PWR_FORCE__SHIFT 0x6
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE2_MEM_PWR_DIS__SHIFT 0x8
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE3_MEM_PWR_FORCE__SHIFT 0x9
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE3_MEM_PWR_DIS__SHIFT 0xb
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE4_MEM_PWR_FORCE__SHIFT 0xc
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE4_MEM_PWR_DIS__SHIFT 0xe
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE5_MEM_PWR_FORCE__SHIFT 0xf
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE5_MEM_PWR_DIS__SHIFT 0x11
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE6_MEM_PWR_FORCE__SHIFT 0x12
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE6_MEM_PWR_DIS__SHIFT 0x14
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE7_MEM_PWR_FORCE__SHIFT 0x15
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE7_MEM_PWR_DIS__SHIFT 0x17
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE_MEM_PWR_MODE_SEL__SHIFT 0x18
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE0_MEM_PWR_FORCE_MASK 0x00000003L
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE0_MEM_PWR_DIS_MASK 0x00000004L
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE1_MEM_PWR_FORCE_MASK 0x00000018L
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE1_MEM_PWR_DIS_MASK 0x00000020L
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE2_MEM_PWR_FORCE_MASK 0x000000C0L
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE2_MEM_PWR_DIS_MASK 0x00000100L
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE3_MEM_PWR_FORCE_MASK 0x00000600L
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE3_MEM_PWR_DIS_MASK 0x00000800L
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE4_MEM_PWR_FORCE_MASK 0x00003000L
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE4_MEM_PWR_DIS_MASK 0x00004000L
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE5_MEM_PWR_FORCE_MASK 0x00018000L
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE5_MEM_PWR_DIS_MASK 0x00020000L
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE6_MEM_PWR_FORCE_MASK 0x000C0000L
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE6_MEM_PWR_DIS_MASK 0x00100000L
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE7_MEM_PWR_FORCE_MASK 0x00600000L
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE7_MEM_PWR_DIS_MASK 0x00800000L
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE_MEM_PWR_MODE_SEL_MASK 0x03000000L
++//DVMM_PTE_PGMEM_STATE
++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE0_PTE_PGMEM_STATE__SHIFT 0x0
++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE1_PTE_PGMEM_STATE__SHIFT 0x2
++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE2_PTE_PGMEM_STATE__SHIFT 0x4
++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE3_PTE_PGMEM_STATE__SHIFT 0x6
++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE4_PTE_PGMEM_STATE__SHIFT 0x8
++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE5_PTE_PGMEM_STATE__SHIFT 0xa
++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE6_PTE_PGMEM_STATE__SHIFT 0xc
++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE7_PTE_PGMEM_STATE__SHIFT 0xe
++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE0_PTE_PGMEM_STATE_MASK 0x00000003L
++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE1_PTE_PGMEM_STATE_MASK 0x0000000CL
++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE2_PTE_PGMEM_STATE_MASK 0x00000030L
++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE3_PTE_PGMEM_STATE_MASK 0x000000C0L
++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE4_PTE_PGMEM_STATE_MASK 0x00000300L
++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE5_PTE_PGMEM_STATE_MASK 0x00000C00L
++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE6_PTE_PGMEM_STATE_MASK 0x00003000L
++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE7_PTE_PGMEM_STATE_MASK 0x0000C000L
++//MCIF_PHASE1_OUTSTANDING_COUNTER
++#define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER__SHIFT 0x0
++#define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL
++//MCIF_PHASE2_OUTSTANDING_COUNTER
++#define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER__SHIFT 0x0
++#define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL
++//MCIF_WB_PHASE0_OUTSTANDING_COUNTER
++#define MCIF_WB_PHASE0_OUTSTANDING_COUNTER__MCIF_WB_PHASE0_OUTSTANDING_COUNTER__SHIFT 0x0
++#define MCIF_WB_PHASE0_OUTSTANDING_COUNTER__MCIF_WB_PHASE0_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL
++//MCIF_WB_PHASE1_OUTSTANDING_COUNTER
++#define MCIF_WB_PHASE1_OUTSTANDING_COUNTER__MCIF_WB_PHASE1_OUTSTANDING_COUNTER__SHIFT 0x0
++#define MCIF_WB_PHASE1_OUTSTANDING_COUNTER__MCIF_WB_PHASE1_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL
++//DCI_MEM_PWR_CNTL4
++#define DCI_MEM_PWR_CNTL4__MCIF_DWB_LUMA_MEM_EN_NUM__SHIFT 0x0
++#define DCI_MEM_PWR_CNTL4__MCIF_DWB_CHROMA_MEM_EN_NUM__SHIFT 0x1
++#define DCI_MEM_PWR_CNTL4__MCIF_CWB0_LUMA_MEM_EN_NUM__SHIFT 0x2
++#define DCI_MEM_PWR_CNTL4__MCIF_CWB0_CHROMA_MEM_EN_NUM__SHIFT 0x3
++#define DCI_MEM_PWR_CNTL4__MCIF_CWB1_LUMA_MEM_EN_NUM__SHIFT 0x4
++#define DCI_MEM_PWR_CNTL4__MCIF_CWB1_CHROMA_MEM_EN_NUM__SHIFT 0x5
++#define DCI_MEM_PWR_CNTL4__DMIF_CURSOR_MEM_PWR_FORCE__SHIFT 0x6
++#define DCI_MEM_PWR_CNTL4__DMIF_CURSOR_MEM_PWR_DIS__SHIFT 0x8
++#define DCI_MEM_PWR_CNTL4__DMIF_CURSOR_RD_REQ_MEM_PWR_FORCE__SHIFT 0x9
++#define DCI_MEM_PWR_CNTL4__DMIF_CURSOR_RD_REQ_MEM_PWR_DIS__SHIFT 0xb
++#define DCI_MEM_PWR_CNTL4__DMIF_CURSOR_RD_REQ_MEM_PWR_MODE_SEL__SHIFT 0xc
++#define DCI_MEM_PWR_CNTL4__MCIF_DWB_LUMA_MEM_EN_NUM_MASK 0x00000001L
++#define DCI_MEM_PWR_CNTL4__MCIF_DWB_CHROMA_MEM_EN_NUM_MASK 0x00000002L
++#define DCI_MEM_PWR_CNTL4__MCIF_CWB0_LUMA_MEM_EN_NUM_MASK 0x00000004L
++#define DCI_MEM_PWR_CNTL4__MCIF_CWB0_CHROMA_MEM_EN_NUM_MASK 0x00000008L
++#define DCI_MEM_PWR_CNTL4__MCIF_CWB1_LUMA_MEM_EN_NUM_MASK 0x00000010L
++#define DCI_MEM_PWR_CNTL4__MCIF_CWB1_CHROMA_MEM_EN_NUM_MASK 0x00000020L
++#define DCI_MEM_PWR_CNTL4__DMIF_CURSOR_MEM_PWR_FORCE_MASK 0x000000C0L
++#define DCI_MEM_PWR_CNTL4__DMIF_CURSOR_MEM_PWR_DIS_MASK 0x00000100L
++#define DCI_MEM_PWR_CNTL4__DMIF_CURSOR_RD_REQ_MEM_PWR_FORCE_MASK 0x00000600L
++#define DCI_MEM_PWR_CNTL4__DMIF_CURSOR_RD_REQ_MEM_PWR_DIS_MASK 0x00000800L
++#define DCI_MEM_PWR_CNTL4__DMIF_CURSOR_RD_REQ_MEM_PWR_MODE_SEL_MASK 0x00003000L
++//MCIF_WB_MISC_CTRL
++#define MCIF_WB_MISC_CTRL__MCIFWB_WR_COMBINE_TIMEOUT_THRESH__SHIFT 0x0
++#define MCIF_WB_MISC_CTRL__MCIF_WB_SOCCLK_DS_ENABLE__SHIFT 0x10
++#define MCIF_WB_MISC_CTRL__MCIFWB_WR_COMBINE_TIMEOUT_THRESH_MASK 0x000003FFL
++#define MCIF_WB_MISC_CTRL__MCIF_WB_SOCCLK_DS_ENABLE_MASK 0x00010000L
++//DCI_MEM_PWR_STATUS3
++#define DCI_MEM_PWR_STATUS3__MCIF_DWB_LUMA_MEM0_PWR_STATE__SHIFT 0x0
++#define DCI_MEM_PWR_STATUS3__MCIF_DWB_LUMA_MEM1_PWR_STATE__SHIFT 0x2
++#define DCI_MEM_PWR_STATUS3__MCIF_DWB_CHROMA_MEM0_PWR_STATE__SHIFT 0x4
++#define DCI_MEM_PWR_STATUS3__MCIF_DWB_CHROMA_MEM1_PWR_STATE__SHIFT 0x6
++#define DCI_MEM_PWR_STATUS3__MCIF_CWB0_LUMA_MEM0_PWR_STATE__SHIFT 0x8
++#define DCI_MEM_PWR_STATUS3__MCIF_CWB0_LUMA_MEM1_PWR_STATE__SHIFT 0xa
++#define DCI_MEM_PWR_STATUS3__MCIF_CWB0_CHROMA_MEM0_PWR_STATE__SHIFT 0xc
++#define DCI_MEM_PWR_STATUS3__MCIF_CWB0_CHROMA_MEM1_PWR_STATE__SHIFT 0xe
++#define DCI_MEM_PWR_STATUS3__MCIF_CWB1_LUMA_MEM0_PWR_STATE__SHIFT 0x10
++#define DCI_MEM_PWR_STATUS3__MCIF_CWB1_LUMA_MEM1_PWR_STATE__SHIFT 0x12
++#define DCI_MEM_PWR_STATUS3__MCIF_CWB1_CHROMA_MEM0_PWR_STATE__SHIFT 0x14
++#define DCI_MEM_PWR_STATUS3__MCIF_CWB1_CHROMA_MEM1_PWR_STATE__SHIFT 0x16
++#define DCI_MEM_PWR_STATUS3__MCIF_DWB_LUMA_MEM0_PWR_STATE_MASK 0x00000003L
++#define DCI_MEM_PWR_STATUS3__MCIF_DWB_LUMA_MEM1_PWR_STATE_MASK 0x0000000CL
++#define DCI_MEM_PWR_STATUS3__MCIF_DWB_CHROMA_MEM0_PWR_STATE_MASK 0x00000030L
++#define DCI_MEM_PWR_STATUS3__MCIF_DWB_CHROMA_MEM1_PWR_STATE_MASK 0x000000C0L
++#define DCI_MEM_PWR_STATUS3__MCIF_CWB0_LUMA_MEM0_PWR_STATE_MASK 0x00000300L
++#define DCI_MEM_PWR_STATUS3__MCIF_CWB0_LUMA_MEM1_PWR_STATE_MASK 0x00000C00L
++#define DCI_MEM_PWR_STATUS3__MCIF_CWB0_CHROMA_MEM0_PWR_STATE_MASK 0x00003000L
++#define DCI_MEM_PWR_STATUS3__MCIF_CWB0_CHROMA_MEM1_PWR_STATE_MASK 0x0000C000L
++#define DCI_MEM_PWR_STATUS3__MCIF_CWB1_LUMA_MEM0_PWR_STATE_MASK 0x00030000L
++#define DCI_MEM_PWR_STATUS3__MCIF_CWB1_LUMA_MEM1_PWR_STATE_MASK 0x000C0000L
++#define DCI_MEM_PWR_STATUS3__MCIF_CWB1_CHROMA_MEM0_PWR_STATE_MASK 0x00300000L
++#define DCI_MEM_PWR_STATUS3__MCIF_CWB1_CHROMA_MEM1_PWR_STATE_MASK 0x00C00000L
++//DMIF_CURSOR_CONTROL
++#define DMIF_CURSOR_CONTROL__ADDRESS_TRANSLATION_ENABLE__SHIFT 0x4
++#define DMIF_CURSOR_CONTROL__PRIVILEGED_ACCESS_ENABLE__SHIFT 0x8
++#define DMIF_CURSOR_CONTROL__LOW_READ_URG_LEVEL__SHIFT 0x10
++#define DMIF_CURSOR_CONTROL__DMIF_CURSOR_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x1e
++#define DMIF_CURSOR_CONTROL__DMIF_CURSOR_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x1f
++#define DMIF_CURSOR_CONTROL__ADDRESS_TRANSLATION_ENABLE_MASK 0x00000010L
++#define DMIF_CURSOR_CONTROL__PRIVILEGED_ACCESS_ENABLE_MASK 0x00000100L
++#define DMIF_CURSOR_CONTROL__LOW_READ_URG_LEVEL_MASK 0x00FF0000L
++#define DMIF_CURSOR_CONTROL__DMIF_CURSOR_MC_LATENCY_COUNTER_ENABLE_MASK 0x40000000L
++#define DMIF_CURSOR_CONTROL__DMIF_CURSOR_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x80000000L
++//DMIF_CURSOR_MEM_CONTROL
++#define DMIF_CURSOR_MEM_CONTROL__DMIF_CURSOR_MEM_CACHE_MODE_DIS__SHIFT 0x0
++#define DMIF_CURSOR_MEM_CONTROL__DMIF_CURSOR_MEM_CACHE_MODE__SHIFT 0x4
++#define DMIF_CURSOR_MEM_CONTROL__DMIF_CURSOR_MEM_CACHE_SIZE__SHIFT 0x8
++#define DMIF_CURSOR_MEM_CONTROL__DMIF_CURSOR_MEM_CACHE_PIPE__SHIFT 0x10
++#define DMIF_CURSOR_MEM_CONTROL__DMIF_CURSOR_MEM_CACHE_TYPE__SHIFT 0x13
++#define DMIF_CURSOR_MEM_CONTROL__DMIF_CURSOR_MEM_CACHE_MODE_DIS_MASK 0x00000001L
++#define DMIF_CURSOR_MEM_CONTROL__DMIF_CURSOR_MEM_CACHE_MODE_MASK 0x00000030L
++#define DMIF_CURSOR_MEM_CONTROL__DMIF_CURSOR_MEM_CACHE_SIZE_MASK 0x0000FF00L
++#define DMIF_CURSOR_MEM_CONTROL__DMIF_CURSOR_MEM_CACHE_PIPE_MASK 0x00070000L
++#define DMIF_CURSOR_MEM_CONTROL__DMIF_CURSOR_MEM_CACHE_TYPE_MASK 0x00180000L
++//DCHUB_FB_LOCATION
++#define DCHUB_FB_LOCATION__FB_BASE__SHIFT 0x0
++#define DCHUB_FB_LOCATION__FB_TOP__SHIFT 0x10
++#define DCHUB_FB_LOCATION__FB_BASE_MASK 0x0000FFFFL
++#define DCHUB_FB_LOCATION__FB_TOP_MASK 0xFFFF0000L
++//DCHUB_FB_OFFSET
++#define DCHUB_FB_OFFSET__FB_OFFSET__SHIFT 0x0
++#define DCHUB_FB_OFFSET__FB_OFFSET_MASK 0x003FFFFFL
++//DCHUB_AGP_BASE
++#define DCHUB_AGP_BASE__AGP_BASE__SHIFT 0x0
++#define DCHUB_AGP_BASE__AGP_BASE_MASK 0x003FFFFFL
++//DCHUB_AGP_BOT
++#define DCHUB_AGP_BOT__AGP_BOT__SHIFT 0x0
++#define DCHUB_AGP_BOT__AGP_BOT_MASK 0x0003FFFFL
++//DCHUB_AGP_TOP
++#define DCHUB_AGP_TOP__AGP_TOP__SHIFT 0x0
++#define DCHUB_AGP_TOP__AGP_TOP_MASK 0x0003FFFFL
++//DCHUB_DRAM_APER_BASE
++#define DCHUB_DRAM_APER_BASE__BASE__SHIFT 0x0
++#define DCHUB_DRAM_APER_BASE__LOCK_DCHUB_DRAM_REGS__SHIFT 0x1c
++#define DCHUB_DRAM_APER_BASE__BASE_MASK 0x00FFFFFFL
++#define DCHUB_DRAM_APER_BASE__LOCK_DCHUB_DRAM_REGS_MASK 0x10000000L
++//DCHUB_DRAM_APER_DEF
++#define DCHUB_DRAM_APER_DEF__DEF__SHIFT 0x0
++#define DCHUB_DRAM_APER_DEF__DEF_MASK 0xFFFFFFFFL
++//DCHUB_DRAM_APER_TOP
++#define DCHUB_DRAM_APER_TOP__TOP__SHIFT 0x0
++#define DCHUB_DRAM_APER_TOP__TOP_MASK 0x00FFFFFFL
++//DCHUB_CONTROL_STATUS
++#define DCHUB_CONTROL_STATUS__NO_OUTSTANDING_REQ__SHIFT 0x0
++#define DCHUB_CONTROL_STATUS__SDP_PORT_STATUS__SHIFT 0x4
++#define DCHUB_CONTROL_STATUS__SDP_DATA_RESPONSE_STATUS__SHIFT 0x6
++#define DCHUB_CONTROL_STATUS__SDP_REQ_CREDIT_ERROR__SHIFT 0x9
++#define DCHUB_CONTROL_STATUS__SDP_DATA_RESPONSE_STATUS_CLEAR__SHIFT 0xc
++#define DCHUB_CONTROL_STATUS__SDP_REQ_CREDIT_ERROR_CLEAR__SHIFT 0xd
++#define DCHUB_CONTROL_STATUS__FLUSH_REQ_CREDIT_EN__SHIFT 0x10
++#define DCHUB_CONTROL_STATUS__REQ_CREDIT_EN__SHIFT 0x11
++#define DCHUB_CONTROL_STATUS__DCE_PORT_CONTROL__SHIFT 0x12
++#define DCHUB_CONTROL_STATUS__SDP_CREDIT_DISCONNECT_DELAY__SHIFT 0x14
++#define DCHUB_CONTROL_STATUS__NO_OUTSTANDING_REQ_MASK 0x00000001L
++#define DCHUB_CONTROL_STATUS__SDP_PORT_STATUS_MASK 0x00000030L
++#define DCHUB_CONTROL_STATUS__SDP_DATA_RESPONSE_STATUS_MASK 0x000001C0L
++#define DCHUB_CONTROL_STATUS__SDP_REQ_CREDIT_ERROR_MASK 0x00000200L
++#define DCHUB_CONTROL_STATUS__SDP_DATA_RESPONSE_STATUS_CLEAR_MASK 0x00001000L
++#define DCHUB_CONTROL_STATUS__SDP_REQ_CREDIT_ERROR_CLEAR_MASK 0x00002000L
++#define DCHUB_CONTROL_STATUS__FLUSH_REQ_CREDIT_EN_MASK 0x00010000L
++#define DCHUB_CONTROL_STATUS__REQ_CREDIT_EN_MASK 0x00020000L
++#define DCHUB_CONTROL_STATUS__DCE_PORT_CONTROL_MASK 0x00040000L
++#define DCHUB_CONTROL_STATUS__SDP_CREDIT_DISCONNECT_DELAY_MASK 0x03F00000L
++//WB_ENABLE
++#define WB_ENABLE__WB_ENABLE__SHIFT 0x0
++#define WB_ENABLE__WB_ENABLE_MASK 0x00000001L
++//WB_EC_CONFIG
++#define WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS__SHIFT 0x0
++#define WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS__SHIFT 0x1
++#define WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS__SHIFT 0x2
++#define WB_EC_CONFIG__WB_TEST_CLK_SEL__SHIFT 0x3
++#define WB_EC_CONFIG__WB_LB_LS_DIS__SHIFT 0x7
++#define WB_EC_CONFIG__WB_LB_SD_DIS__SHIFT 0x8
++#define WB_EC_CONFIG__WB_LUT_LS_DIS__SHIFT 0x9
++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL__SHIFT 0xc
++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS__SHIFT 0xe
++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE__SHIFT 0xf
++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_SM__SHIFT 0x11
++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_BG__SHIFT 0x13
++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE__SHIFT 0x15
++#define WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE__SHIFT 0x17
++#define WB_EC_CONFIG__LB_MEM_PWR_STATE_SM__SHIFT 0x18
++#define WB_EC_CONFIG__LB_MEM_PWR_STATE_BG__SHIFT 0x1a
++#define WB_EC_CONFIG__LB_MEM_PWR_STATE__SHIFT 0x1c
++#define WB_EC_CONFIG__LUT_MEM_PWR_STATE__SHIFT 0x1e
++#define WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS_MASK 0x00000001L
++#define WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS_MASK 0x00000002L
++#define WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS_MASK 0x00000004L
++#define WB_EC_CONFIG__WB_TEST_CLK_SEL_MASK 0x00000078L
++#define WB_EC_CONFIG__WB_LB_LS_DIS_MASK 0x00000080L
++#define WB_EC_CONFIG__WB_LB_SD_DIS_MASK 0x00000100L
++#define WB_EC_CONFIG__WB_LUT_LS_DIS_MASK 0x00000200L
++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL_MASK 0x00003000L
++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS_MASK 0x00004000L
++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE_MASK 0x00018000L
++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_SM_MASK 0x00060000L
++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_BG_MASK 0x00180000L
++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_MASK 0x00600000L
++#define WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE_MASK 0x00800000L
++#define WB_EC_CONFIG__LB_MEM_PWR_STATE_SM_MASK 0x03000000L
++#define WB_EC_CONFIG__LB_MEM_PWR_STATE_BG_MASK 0x0C000000L
++#define WB_EC_CONFIG__LB_MEM_PWR_STATE_MASK 0x30000000L
++#define WB_EC_CONFIG__LUT_MEM_PWR_STATE_MASK 0xC0000000L
++//CNV_MODE
++#define CNV_MODE__CNV_FRAME_CAPTURE_RATE__SHIFT 0x8
++#define CNV_MODE__CNV_WINDOW_CROP_EN__SHIFT 0xc
++#define CNV_MODE__CNV_STEREO_TYPE__SHIFT 0xd
++#define CNV_MODE__CNV_INTERLACED_MODE__SHIFT 0xf
++#define CNV_MODE__CNV_EYE_SELECTION__SHIFT 0x10
++#define CNV_MODE__CNV_STEREO_POLARITY__SHIFT 0x12
++#define CNV_MODE__CNV_INTERLACED_FIELD_ORDER__SHIFT 0x13
++#define CNV_MODE__CNV_STEREO_SPLIT__SHIFT 0x14
++#define CNV_MODE__CNV_NEW_CONTENT__SHIFT 0x18
++#define CNV_MODE__CNV_FRAME_CAPTURE_EN__SHIFT 0x1f
++#define CNV_MODE__CNV_FRAME_CAPTURE_RATE_MASK 0x00000300L
++#define CNV_MODE__CNV_WINDOW_CROP_EN_MASK 0x00001000L
++#define CNV_MODE__CNV_STEREO_TYPE_MASK 0x00006000L
++#define CNV_MODE__CNV_INTERLACED_MODE_MASK 0x00008000L
++#define CNV_MODE__CNV_EYE_SELECTION_MASK 0x00030000L
++#define CNV_MODE__CNV_STEREO_POLARITY_MASK 0x00040000L
++#define CNV_MODE__CNV_INTERLACED_FIELD_ORDER_MASK 0x00080000L
++#define CNV_MODE__CNV_STEREO_SPLIT_MASK 0x00100000L
++#define CNV_MODE__CNV_NEW_CONTENT_MASK 0x01000000L
++#define CNV_MODE__CNV_FRAME_CAPTURE_EN_MASK 0x80000000L
++//CNV_WINDOW_START
++#define CNV_WINDOW_START__CNV_WINDOW_START_X__SHIFT 0x0
++#define CNV_WINDOW_START__CNV_WINDOW_START_Y__SHIFT 0x10
++#define CNV_WINDOW_START__CNV_WINDOW_START_X_MASK 0x00000FFFL
++#define CNV_WINDOW_START__CNV_WINDOW_START_Y_MASK 0x0FFF0000L
++//CNV_WINDOW_SIZE
++#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH__SHIFT 0x0
++#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT__SHIFT 0x10
++#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH_MASK 0x00000FFFL
++#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT_MASK 0x0FFF0000L
++//CNV_UPDATE
++#define CNV_UPDATE__CNV_UPDATE_PENDING__SHIFT 0x0
++#define CNV_UPDATE__CNV_UPDATE_TAKEN__SHIFT 0x8
++#define CNV_UPDATE__CNV_UPDATE_LOCK__SHIFT 0x10
++#define CNV_UPDATE__CNV_UPDATE_PENDING_MASK 0x00000001L
++#define CNV_UPDATE__CNV_UPDATE_TAKEN_MASK 0x00000100L
++#define CNV_UPDATE__CNV_UPDATE_LOCK_MASK 0x00010000L
++//CNV_SOURCE_SIZE
++#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH__SHIFT 0x0
++#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT__SHIFT 0x10
++#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH_MASK 0x00007FFFL
++#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT_MASK 0x7FFF0000L
++//CNV_CSC_CONTROL
++#define CNV_CSC_CONTROL__CNV_CSC_BYPASS__SHIFT 0x0
++#define CNV_CSC_CONTROL__CNV_CSC_BYPASS_MASK 0x00000001L
++//CNV_CSC_C11_C12
++#define CNV_CSC_C11_C12__CNV_CSC_C11__SHIFT 0x0
++#define CNV_CSC_C11_C12__CNV_CSC_C12__SHIFT 0x10
++#define CNV_CSC_C11_C12__CNV_CSC_C11_MASK 0x00001FFFL
++#define CNV_CSC_C11_C12__CNV_CSC_C12_MASK 0x1FFF0000L
++//CNV_CSC_C13_C14
++#define CNV_CSC_C13_C14__CNV_CSC_C13__SHIFT 0x0
++#define CNV_CSC_C13_C14__CNV_CSC_C14__SHIFT 0x10
++#define CNV_CSC_C13_C14__CNV_CSC_C13_MASK 0x00001FFFL
++#define CNV_CSC_C13_C14__CNV_CSC_C14_MASK 0x7FFF0000L
++//CNV_CSC_C21_C22
++#define CNV_CSC_C21_C22__CNV_CSC_C21__SHIFT 0x0
++#define CNV_CSC_C21_C22__CNV_CSC_C22__SHIFT 0x10
++#define CNV_CSC_C21_C22__CNV_CSC_C21_MASK 0x00001FFFL
++#define CNV_CSC_C21_C22__CNV_CSC_C22_MASK 0x1FFF0000L
++//CNV_CSC_C23_C24
++#define CNV_CSC_C23_C24__CNV_CSC_C23__SHIFT 0x0
++#define CNV_CSC_C23_C24__CNV_CSC_C24__SHIFT 0x10
++#define CNV_CSC_C23_C24__CNV_CSC_C23_MASK 0x00001FFFL
++#define CNV_CSC_C23_C24__CNV_CSC_C24_MASK 0x7FFF0000L
++//CNV_CSC_C31_C32
++#define CNV_CSC_C31_C32__CNV_CSC_C31__SHIFT 0x0
++#define CNV_CSC_C31_C32__CNV_CSC_C32__SHIFT 0x10
++#define CNV_CSC_C31_C32__CNV_CSC_C31_MASK 0x00001FFFL
++#define CNV_CSC_C31_C32__CNV_CSC_C32_MASK 0x1FFF0000L
++//CNV_CSC_C33_C34
++#define CNV_CSC_C33_C34__CNV_CSC_C33__SHIFT 0x0
++#define CNV_CSC_C33_C34__CNV_CSC_C34__SHIFT 0x10
++#define CNV_CSC_C33_C34__CNV_CSC_C33_MASK 0x00001FFFL
++#define CNV_CSC_C33_C34__CNV_CSC_C34_MASK 0x7FFF0000L
++//CNV_CSC_ROUND_OFFSET_R
++#define CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R__SHIFT 0x0
++#define CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R_MASK 0x0000FFFFL
++//CNV_CSC_ROUND_OFFSET_G
++#define CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G__SHIFT 0x0
++#define CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G_MASK 0x0000FFFFL
++//CNV_CSC_ROUND_OFFSET_B
++#define CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B__SHIFT 0x0
++#define CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B_MASK 0x0000FFFFL
++//CNV_CSC_CLAMP_R
++#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R__SHIFT 0x0
++#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R__SHIFT 0x10
++#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R_MASK 0x0000FFFFL
++#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R_MASK 0xFFFF0000L
++//CNV_CSC_CLAMP_G
++#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G__SHIFT 0x0
++#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G__SHIFT 0x10
++#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G_MASK 0x0000FFFFL
++#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G_MASK 0xFFFF0000L
++//CNV_CSC_CLAMP_B
++#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B__SHIFT 0x0
++#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B__SHIFT 0x10
++#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B_MASK 0x0000FFFFL
++#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B_MASK 0xFFFF0000L
++//CNV_TEST_CNTL
++#define CNV_TEST_CNTL__CNV_TEST_CRC_EN__SHIFT 0x4
++#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN__SHIFT 0x8
++#define CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY__SHIFT 0x10
++#define CNV_TEST_CNTL__CNV_TEST_CRC_EN_MASK 0x00000010L
++#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN_MASK 0x00000100L
++#define CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY_MASK 0x00010000L
++//CNV_TEST_CRC_RED
++#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK__SHIFT 0x4
++#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED__SHIFT 0x10
++#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK_MASK 0x0000FFF0L
++#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED_MASK 0xFFFF0000L
++//CNV_TEST_CRC_GREEN
++#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK__SHIFT 0x4
++#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN__SHIFT 0x10
++#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK_MASK 0x0000FFF0L
++#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN_MASK 0xFFFF0000L
++//CNV_TEST_CRC_BLUE
++#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK__SHIFT 0x4
++#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE__SHIFT 0x10
++#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK_MASK 0x0000FFF0L
++#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE_MASK 0xFFFF0000L
++//CNV_INPUT_SELECT
++#define CNV_INPUT_SELECT__CNV_INPUT_SRC_SELECT__SHIFT 0x0
++#define CNV_INPUT_SELECT__CNV_INPUT_PIPE_SELECT__SHIFT 0x2
++#define CNV_INPUT_SELECT__CNV_INPUT_SRC_SELECT_MASK 0x00000003L
++#define CNV_INPUT_SELECT__CNV_INPUT_PIPE_SELECT_MASK 0x0000001CL
++//WB_SOFT_RESET
++#define WB_SOFT_RESET__WB_SOFT_RESET__SHIFT 0x0
++#define WB_SOFT_RESET__WB_SOFT_RESET_MASK 0x00000001L
++//WB_WARM_UP_MODE_CTL1
++#define WB_WARM_UP_MODE_CTL1__WIDTH_WARMUP__SHIFT 0x0
++#define WB_WARM_UP_MODE_CTL1__HEIGHT_WARMUP__SHIFT 0x10
++#define WB_WARM_UP_MODE_CTL1__GMC_WARM_UP_ENABLE__SHIFT 0x1f
++#define WB_WARM_UP_MODE_CTL1__WIDTH_WARMUP_MASK 0x00007FFFL
++#define WB_WARM_UP_MODE_CTL1__HEIGHT_WARMUP_MASK 0x7FFF0000L
++#define WB_WARM_UP_MODE_CTL1__GMC_WARM_UP_ENABLE_MASK 0x80000000L
++//WB_WARM_UP_MODE_CTL2
++#define WB_WARM_UP_MODE_CTL2__DATA_VALUE_WARMUP__SHIFT 0x0
++#define WB_WARM_UP_MODE_CTL2__MODE_WARMUP__SHIFT 0x8
++#define WB_WARM_UP_MODE_CTL2__DATA_VALUE_WARMUP_MASK 0x000000FFL
++#define WB_WARM_UP_MODE_CTL2__MODE_WARMUP_MASK 0x00000100L
++//WBSCL_COEF_RAM_SELECT
++#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0
++#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_PHASE__SHIFT 0x8
++#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10
++#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000007L
++#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_PHASE_MASK 0x00000F00L
++#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_FILTER_TYPE_MASK 0x00030000L
++//WBSCL_COEF_RAM_TAP_DATA
++#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0
++#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
++#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10
++#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
++#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL
++#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L
++#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L
++#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L
++//WBSCL_MODE
++#define WBSCL_MODE__WBSCL_MODE__SHIFT 0x0
++#define WBSCL_MODE__WBSCL_MODE_MASK 0x00000003L
++//WBSCL_TAP_CONTROL
++#define WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_Y_RGB__SHIFT 0x0
++#define WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_CBCR__SHIFT 0x4
++#define WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_Y_RGB__SHIFT 0x8
++#define WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_CBCR__SHIFT 0xc
++#define WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_Y_RGB_MASK 0x0000000FL
++#define WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_CBCR_MASK 0x000000F0L
++#define WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_Y_RGB_MASK 0x00000F00L
++#define WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_CBCR_MASK 0x0000F000L
++//WBSCL_DEST_SIZE
++#define WBSCL_DEST_SIZE__WBSCL_DEST_HEIGHT__SHIFT 0x0
++#define WBSCL_DEST_SIZE__WBSCL_DEST_WIDTH__SHIFT 0x10
++#define WBSCL_DEST_SIZE__WBSCL_DEST_HEIGHT_MASK 0x00007FFFL
++#define WBSCL_DEST_SIZE__WBSCL_DEST_WIDTH_MASK 0x7FFF0000L
++//WBSCL_HORZ_FILTER_SCALE_RATIO
++#define WBSCL_HORZ_FILTER_SCALE_RATIO__WBSCL_H_SCALE_RATIO__SHIFT 0x0
++#define WBSCL_HORZ_FILTER_SCALE_RATIO__WBSCL_H_SCALE_RATIO_MASK 0x07FFFFFFL
++//WBSCL_HORZ_FILTER_INIT_Y_RGB
++#define WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_FRAC_Y_RGB__SHIFT 0x0
++#define WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_INT_Y_RGB__SHIFT 0x18
++#define WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_FRAC_Y_RGB_MASK 0x00FFFFFFL
++#define WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_INT_Y_RGB_MASK 0x1F000000L
++//WBSCL_HORZ_FILTER_INIT_CBCR
++#define WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_FRAC_CBCR__SHIFT 0x0
++#define WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_INT_CBCR__SHIFT 0x18
++#define WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_FRAC_CBCR_MASK 0x00FFFFFFL
++#define WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_INT_CBCR_MASK 0x1F000000L
++//WBSCL_VERT_FILTER_SCALE_RATIO
++#define WBSCL_VERT_FILTER_SCALE_RATIO__WBSCL_V_SCALE_RATIO__SHIFT 0x0
++#define WBSCL_VERT_FILTER_SCALE_RATIO__WBSCL_V_SCALE_RATIO_MASK 0x07FFFFFFL
++//WBSCL_VERT_FILTER_INIT_Y_RGB
++#define WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_FRAC_Y_RGB__SHIFT 0x0
++#define WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_INT_Y_RGB__SHIFT 0x18
++#define WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_FRAC_Y_RGB_MASK 0x00FFFFFFL
++#define WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_INT_Y_RGB_MASK 0x1F000000L
++//WBSCL_VERT_FILTER_INIT_CBCR
++#define WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_FRAC_CBCR__SHIFT 0x0
++#define WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_INT_CBCR__SHIFT 0x18
++#define WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_FRAC_CBCR_MASK 0x00FFFFFFL
++#define WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_INT_CBCR_MASK 0x1F000000L
++//WBSCL_ROUND_OFFSET
++#define WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_Y_RGB__SHIFT 0x0
++#define WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_CBCR__SHIFT 0x10
++#define WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_Y_RGB_MASK 0x0000FFFFL
++#define WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_CBCR_MASK 0xFFFF0000L
++//WBSCL_CLAMP
++#define WBSCL_CLAMP__WBSCL_CLAMP_UPPER_Y_RGB__SHIFT 0x0
++#define WBSCL_CLAMP__WBSCL_CLAMP_LOWER_Y_RGB__SHIFT 0x8
++#define WBSCL_CLAMP__WBSCL_CLAMP_UPPER_CBCR__SHIFT 0x10
++#define WBSCL_CLAMP__WBSCL_CLAMP_LOWER_CBCR__SHIFT 0x18
++#define WBSCL_CLAMP__WBSCL_CLAMP_UPPER_Y_RGB_MASK 0x000000FFL
++#define WBSCL_CLAMP__WBSCL_CLAMP_LOWER_Y_RGB_MASK 0x0000FF00L
++#define WBSCL_CLAMP__WBSCL_CLAMP_UPPER_CBCR_MASK 0x00FF0000L
++#define WBSCL_CLAMP__WBSCL_CLAMP_LOWER_CBCR_MASK 0xFF000000L
++//WBSCL_OVERFLOW_STATUS
++#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_FLAG__SHIFT 0x0
++#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_ACK__SHIFT 0x8
++#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_MASK__SHIFT 0xc
++#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_STATUS__SHIFT 0x10
++#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_TYPE__SHIFT 0x14
++#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_FLAG_MASK 0x00000001L
++#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_ACK_MASK 0x00000100L
++#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_MASK_MASK 0x00001000L
++#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_STATUS_MASK 0x00010000L
++#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_TYPE_MASK 0x00100000L
++//WBSCL_COEF_RAM_CONFLICT_STATUS
++#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_FLAG__SHIFT 0x0
++#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_ACK__SHIFT 0x8
++#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_MASK__SHIFT 0xc
++#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10
++#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_TYPE__SHIFT 0x14
++#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_FLAG_MASK 0x00000001L
++#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_ACK_MASK 0x00000100L
++#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_MASK_MASK 0x00001000L
++#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_STATUS_MASK 0x00010000L
++#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_TYPE_MASK 0x00100000L
++//WBSCL_OUTSIDE_PIX_STRATEGY
++#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_OUTSIDE_PIX_STRATEGY__SHIFT 0x0
++#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_B_CB__SHIFT 0x8
++#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_G_Y__SHIFT 0x10
++#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_R_CR__SHIFT 0x18
++#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_OUTSIDE_PIX_STRATEGY_MASK 0x00000001L
++#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_B_CB_MASK 0x0000FF00L
++#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_G_Y_MASK 0x00FF0000L
++#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_R_CR_MASK 0xFF000000L
++//WBSCL_TEST_CNTL
++#define WBSCL_TEST_CNTL__WBSCL_TEST_CRC_EN__SHIFT 0x4
++#define WBSCL_TEST_CNTL__WBSCL_TEST_CRC_CONT_EN__SHIFT 0x8
++#define WBSCL_TEST_CNTL__WBSCL_TEST_CRC_DE_ONLY__SHIFT 0x10
++#define WBSCL_TEST_CNTL__WBSCL_TEST_CRC_EN_MASK 0x00000010L
++#define WBSCL_TEST_CNTL__WBSCL_TEST_CRC_CONT_EN_MASK 0x00000100L
++#define WBSCL_TEST_CNTL__WBSCL_TEST_CRC_DE_ONLY_MASK 0x00010000L
++//WBSCL_TEST_CRC_RED
++#define WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_RED_MASK__SHIFT 0x8
++#define WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_SIG_RED__SHIFT 0x10
++#define WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_RED_MASK_MASK 0x0000FF00L
++#define WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_SIG_RED_MASK 0xFFFF0000L
++//WBSCL_TEST_CRC_GREEN
++#define WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_GREEN_MASK__SHIFT 0x0
++#define WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_SIG_GREEN__SHIFT 0x10
++#define WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_GREEN_MASK_MASK 0x0000FFFFL
++#define WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_SIG_GREEN_MASK 0xFFFF0000L
++//WBSCL_TEST_CRC_BLUE
++#define WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_BLUE_MASK__SHIFT 0x8
++#define WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_SIG_BLUE__SHIFT 0x10
++#define WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_BLUE_MASK_MASK 0x0000FF00L
++#define WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_SIG_BLUE_MASK 0xFFFF0000L
++//WBSCL_BACKPRESSURE_CNT_EN
++#define WBSCL_BACKPRESSURE_CNT_EN__WBSCL_BACKPRESSURE_CNT_EN__SHIFT 0x0
++#define WBSCL_BACKPRESSURE_CNT_EN__WBSCL_BACKPRESSURE_CNT_EN_MASK 0x00000001L
++//WB_MCIF_BACKPRESSURE_CNT
++#define WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_Y_MAX_BACKPRESSURE__SHIFT 0x0
++#define WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_C_MAX_BACKPRESSURE__SHIFT 0x10
++#define WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_Y_MAX_BACKPRESSURE_MASK 0x0000FFFFL
++#define WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_C_MAX_BACKPRESSURE_MASK 0xFFFF0000L
++//WBSCL_RAM_SHUTDOWN
++#define WBSCL_RAM_SHUTDOWN__WBSCL_RAM_SHUTDOWN_SEL__SHIFT 0x0
++#define WBSCL_RAM_SHUTDOWN__WBSCL_RAM_SHUTDOWN_SEL_MASK 0x00000003L
++//DMCU_CTRL
++#define DMCU_CTRL__RESET_UC__SHIFT 0x0
++#define DMCU_CTRL__IGNORE_PWRMGT__SHIFT 0x1
++#define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT 0x2
++#define DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT 0x3
++#define DMCU_CTRL__DMCU_ENABLE__SHIFT 0x4
++#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN__SHIFT 0x8
++#define DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT 0x10
++#define DMCU_CTRL__RESET_UC_MASK 0x00000001L
++#define DMCU_CTRL__IGNORE_PWRMGT_MASK 0x00000002L
++#define DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK 0x00000004L
++#define DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK 0x00000008L
++#define DMCU_CTRL__DMCU_ENABLE_MASK 0x00000010L
++#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN_MASK 0x00000100L
++#define DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK 0xFFFF0000L
++//DMCU_STATUS
++#define DMCU_STATUS__UC_IN_RESET__SHIFT 0x0
++#define DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT 0x1
++#define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT 0x2
++#define DMCU_STATUS__UC_IN_RESET_MASK 0x00000001L
++#define DMCU_STATUS__UC_IN_WAIT_MODE_MASK 0x00000002L
++#define DMCU_STATUS__UC_IN_STOP_MODE_MASK 0x00000004L
++//DMCU_PC_START_ADDR
++#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT 0x0
++#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT 0x8
++#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK 0x000000FFL
++#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK 0x0000FF00L
++//DMCU_FW_START_ADDR
++#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT 0x0
++#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT 0x8
++#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK 0x000000FFL
++#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK 0x0000FF00L
++//DMCU_FW_END_ADDR
++#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT 0x0
++#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT 0x8
++#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK 0x000000FFL
++#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK 0x0000FF00L
++//DMCU_FW_ISR_START_ADDR
++#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT 0x0
++#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT 0x8
++#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK 0x000000FFL
++#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK 0x0000FF00L
++//DMCU_FW_CS_HI
++#define DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT 0x0
++#define DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK 0xFFFFFFFFL
++//DMCU_FW_CS_LO
++#define DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT 0x0
++#define DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK 0xFFFFFFFFL
++//DMCU_RAM_ACCESS_CTRL
++#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT 0x0
++#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT 0x1
++#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT 0x2
++#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT 0x3
++#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN__SHIFT 0x4
++#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT 0x5
++#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK 0x00000001L
++#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK 0x00000002L
++#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK 0x00000004L
++#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK 0x00000008L
++#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN_MASK 0x00000010L
++#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK 0x00000020L
++//DMCU_ERAM_WR_CTRL
++#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT 0x0
++#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT 0x10
++#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT 0x14
++#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK 0x0000FFFFL
++#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK 0x000F0000L
++#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK 0x00100000L
++//DMCU_ERAM_WR_DATA
++#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT 0x0
++#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK 0xFFFFFFFFL
++//DMCU_ERAM_RD_CTRL
++#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT 0x0
++#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT 0x10
++#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT 0x14
++#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK 0x0000FFFFL
++#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK 0x000F0000L
++#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK 0x00100000L
++//DMCU_ERAM_RD_DATA
++#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT 0x0
++#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK 0xFFFFFFFFL
++//DMCU_IRAM_WR_CTRL
++#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT 0x0
++#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK 0x000003FFL
++//DMCU_IRAM_WR_DATA
++#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT 0x0
++#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK 0x000000FFL
++//DMCU_IRAM_RD_CTRL
++#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT 0x0
++#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK 0x000003FFL
++//DMCU_IRAM_RD_DATA
++#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT 0x0
++#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK 0x000000FFL
++//DMCU_EVENT_TRIGGER
++#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC__SHIFT 0x0
++#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT 0x10
++#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST__SHIFT 0x17
++#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC_MASK 0x00000001L
++#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK 0x007F0000L
++#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST_MASK 0x00800000L
++//DMCU_UC_INTERNAL_INT_STATUS
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT 0x0
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT 0x1
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT 0x2
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT 0x3
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT 0x4
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT 0x5
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT 0x6
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT 0x7
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT 0x8
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT 0x9
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT 0xa
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT 0xb
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT 0xc
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT 0xd
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT 0xe
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT 0xf
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK 0x00000001L
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK 0x00000002L
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK 0x00000004L
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK 0x00000008L
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK 0x00000010L
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK 0x00000020L
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK 0x00000040L
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK 0x00000080L
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK 0x00000100L
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK 0x00000200L
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK 0x00000400L
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK 0x00000800L
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK 0x00001000L
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK 0x00002000L
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK 0x00004000L
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK 0x00008000L
++//DMCU_SS_INTERRUPT_CNTL_STATUS
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS__SHIFT 0xd
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED__SHIFT 0xe
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR__SHIFT 0xe
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS__SHIFT 0xf
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED__SHIFT 0x10
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR__SHIFT 0x10
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS__SHIFT 0x11
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED__SHIFT 0x12
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR__SHIFT 0x12
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS__SHIFT 0x13
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED__SHIFT 0x14
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR__SHIFT 0x14
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS__SHIFT 0x15
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED__SHIFT 0x16
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR__SHIFT 0x16
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS__SHIFT 0x17
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED__SHIFT 0x18
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR__SHIFT 0x18
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS_MASK 0x00002000L
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED_MASK 0x00004000L
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR_MASK 0x00004000L
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS_MASK 0x00008000L
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED_MASK 0x00010000L
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR_MASK 0x00010000L
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS_MASK 0x00020000L
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED_MASK 0x00040000L
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR_MASK 0x00040000L
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS_MASK 0x00080000L
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED_MASK 0x00100000L
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR_MASK 0x00100000L
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS_MASK 0x00200000L
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED_MASK 0x00400000L
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR_MASK 0x00400000L
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS_MASK 0x00800000L
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED_MASK 0x01000000L
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR_MASK 0x01000000L
++//DMCU_INTERRUPT_STATUS
++#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT 0x0
++#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT 0x0
++#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT 0x1
++#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT 0x1
++#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT 0x2
++#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT 0x2
++#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT 0x3
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_OCCURRED__SHIFT 0x4
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_CLEAR__SHIFT 0x4
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_OCCURRED__SHIFT 0x5
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_CLEAR__SHIFT 0x5
++#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT 0x8
++#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT 0x8
++#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT 0x9
++#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT 0xa
++#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT 0xa
++#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT 0xb
++#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT 0xb
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED__SHIFT 0xc
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR__SHIFT 0xc
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED__SHIFT 0xd
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR__SHIFT 0xd
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED__SHIFT 0xe
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR__SHIFT 0xe
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED__SHIFT 0xf
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR__SHIFT 0xf
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED__SHIFT 0x10
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR__SHIFT 0x10
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED__SHIFT 0x11
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR__SHIFT 0x11
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED__SHIFT 0x12
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR__SHIFT 0x12
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED__SHIFT 0x13
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR__SHIFT 0x13
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED__SHIFT 0x14
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR__SHIFT 0x14
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED__SHIFT 0x15
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR__SHIFT 0x15
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED__SHIFT 0x16
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR__SHIFT 0x16
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED__SHIFT 0x17
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR__SHIFT 0x17
++#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT 0x18
++#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT 0x18
++#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT 0x19
++#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT 0x19
++#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED__SHIFT 0x1a
++#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR__SHIFT 0x1a
++#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED__SHIFT 0x1b
++#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT 0x1b
++#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED__SHIFT 0x1c
++#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR__SHIFT 0x1c
++#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED__SHIFT 0x1d
++#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR__SHIFT 0x1d
++#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK 0x00000001L
++#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK 0x00000001L
++#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK 0x00000002L
++#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK 0x00000002L
++#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK 0x00000004L
++#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK 0x00000004L
++#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK 0x00000008L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_OCCURRED_MASK 0x00000010L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_CLEAR_MASK 0x00000010L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_OCCURRED_MASK 0x00000020L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_CLEAR_MASK 0x00000020L
++#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK 0x00000100L
++#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK 0x00000100L
++#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK 0x00000200L
++#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK 0x00000400L
++#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK 0x00000400L
++#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK 0x00000800L
++#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK 0x00000800L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED_MASK 0x00001000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR_MASK 0x00001000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED_MASK 0x00002000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR_MASK 0x00002000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED_MASK 0x00004000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR_MASK 0x00004000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED_MASK 0x00008000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR_MASK 0x00008000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED_MASK 0x00010000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR_MASK 0x00010000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED_MASK 0x00020000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR_MASK 0x00020000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED_MASK 0x00040000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR_MASK 0x00040000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED_MASK 0x00080000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR_MASK 0x00080000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED_MASK 0x00100000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR_MASK 0x00100000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED_MASK 0x00200000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR_MASK 0x00200000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED_MASK 0x00400000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR_MASK 0x00400000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED_MASK 0x00800000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR_MASK 0x00800000L
++#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x01000000L
++#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK 0x01000000L
++#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK 0x02000000L
++#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK 0x02000000L
++#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK 0x04000000L
++#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x04000000L
++#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED_MASK 0x08000000L
++#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR_MASK 0x08000000L
++#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK 0x10000000L
++#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR_MASK 0x10000000L
++#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED_MASK 0x20000000L
++#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR_MASK 0x20000000L
++//DMCU_INTERRUPT_TO_HOST_EN_MASK
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT 0x0
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT 0x1
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT 0x2
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT 0x9
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT 0xa
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT 0xb
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK 0x00000001L
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK 0x00000002L
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK 0x00000004L
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK 0x00000200L
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK 0x00000400L
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK 0x00000800L
++//DMCU_INTERRUPT_TO_UC_EN_MASK
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT 0x0
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT 0x1
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x2
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT 0x3
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_TO_UC_EN__SHIFT 0x4
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x5
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN__SHIFT 0x6
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN__SHIFT 0x7
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT 0x8
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN__SHIFT 0x9
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN__SHIFT 0xa
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN__SHIFT 0xb
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN__SHIFT 0xc
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN__SHIFT 0xd
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN__SHIFT 0xe
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN__SHIFT 0xf
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN__SHIFT 0x10
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN__SHIFT 0x11
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x12
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x13
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x14
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x15
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x16
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x17
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT 0x18
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT 0x19
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN__SHIFT 0x1a
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN__SHIFT 0x1b
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN__SHIFT 0x1c
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN__SHIFT 0x1d
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN__SHIFT 0x1e
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK 0x00000001L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK 0x00000002L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK 0x00000004L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK 0x00000008L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_TO_UC_EN_MASK 0x00000010L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000020L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN_MASK 0x00000040L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN_MASK 0x00000080L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK 0x00000100L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN_MASK 0x00000200L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN_MASK 0x00000400L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN_MASK 0x00000800L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN_MASK 0x00001000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN_MASK 0x00002000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN_MASK 0x00004000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN_MASK 0x00008000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN_MASK 0x00010000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN_MASK 0x00020000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN_MASK 0x00040000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN_MASK 0x00080000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN_MASK 0x00100000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN_MASK 0x00200000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN_MASK 0x00400000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN_MASK 0x00800000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK 0x01000000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK 0x02000000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN_MASK 0x04000000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN_MASK 0x08000000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN_MASK 0x10000000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN_MASK 0x20000000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN_MASK 0x40000000L
++//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x0
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x1
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x2
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT 0x3
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x4
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x5
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL__SHIFT 0x6
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL__SHIFT 0x7
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT 0x8
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL__SHIFT 0x9
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL__SHIFT 0xa
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL__SHIFT 0xb
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xc
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xd
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xe
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xf
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x10
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x11
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x12
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x13
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x14
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x15
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x16
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x17
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT 0x18
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT 0x19
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL__SHIFT 0x1b
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL__SHIFT 0x1c
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL__SHIFT 0x1d
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL__SHIFT 0x1e
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x00000001L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x00000002L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000004L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK 0x00000008L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000010L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000020L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL_MASK 0x00000040L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL_MASK 0x00000080L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x00000100L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL_MASK 0x00000200L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL_MASK 0x00000400L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL_MASK 0x00000800L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00001000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00002000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00004000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00008000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00010000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00020000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00040000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00080000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00100000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00200000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00400000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00800000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK 0x01000000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK 0x02000000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL_MASK 0x04000000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL_MASK 0x08000000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL_MASK 0x10000000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL_MASK 0x20000000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL_MASK 0x40000000L
++//DC_DMCU_SCRATCH
++#define DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT 0x0
++#define DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK 0xFFFFFFFFL
++//DMCU_INT_CNT
++#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT 0x0
++#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT 0x8
++#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT 0x10
++#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK 0x000000FFL
++#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK 0x0000FF00L
++#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK 0x00FF0000L
++//DMCU_FW_CHECKSUM_SMPL_BYTE_POS
++#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT 0x0
++#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT 0x2
++#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK 0x00000003L
++#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK 0x0000000CL
++//DMCU_UC_CLK_GATING_CNTL
++#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY__SHIFT 0x0
++#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY__SHIFT 0x8
++#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN__SHIFT 0x10
++#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY_MASK 0x00000007L
++#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY_MASK 0x00000700L
++#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN_MASK 0x00010000L
++//MASTER_COMM_DATA_REG1
++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0__SHIFT 0x0
++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1__SHIFT 0x8
++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2__SHIFT 0x10
++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3__SHIFT 0x18
++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0_MASK 0x000000FFL
++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1_MASK 0x0000FF00L
++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2_MASK 0x00FF0000L
++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3_MASK 0xFF000000L
++//MASTER_COMM_DATA_REG2
++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0__SHIFT 0x0
++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1__SHIFT 0x8
++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2__SHIFT 0x10
++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3__SHIFT 0x18
++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0_MASK 0x000000FFL
++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1_MASK 0x0000FF00L
++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2_MASK 0x00FF0000L
++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3_MASK 0xFF000000L
++//MASTER_COMM_DATA_REG3
++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0__SHIFT 0x0
++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1__SHIFT 0x8
++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2__SHIFT 0x10
++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3__SHIFT 0x18
++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0_MASK 0x000000FFL
++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1_MASK 0x0000FF00L
++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2_MASK 0x00FF0000L
++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3_MASK 0xFF000000L
++//MASTER_COMM_CMD_REG
++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0__SHIFT 0x0
++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1__SHIFT 0x8
++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT 0x10
++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT 0x18
++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0_MASK 0x000000FFL
++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1_MASK 0x0000FF00L
++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2_MASK 0x00FF0000L
++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3_MASK 0xFF000000L
++//MASTER_COMM_CNTL_REG
++#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT 0x0
++#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L
++//SLAVE_COMM_DATA_REG1
++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0__SHIFT 0x0
++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1__SHIFT 0x8
++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2__SHIFT 0x10
++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3__SHIFT 0x18
++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0_MASK 0x000000FFL
++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1_MASK 0x0000FF00L
++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2_MASK 0x00FF0000L
++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3_MASK 0xFF000000L
++//SLAVE_COMM_DATA_REG2
++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0__SHIFT 0x0
++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1__SHIFT 0x8
++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2__SHIFT 0x10
++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3__SHIFT 0x18
++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0_MASK 0x000000FFL
++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1_MASK 0x0000FF00L
++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2_MASK 0x00FF0000L
++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3_MASK 0xFF000000L
++//SLAVE_COMM_DATA_REG3
++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0__SHIFT 0x0
++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1__SHIFT 0x8
++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2__SHIFT 0x10
++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3__SHIFT 0x18
++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0_MASK 0x000000FFL
++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1_MASK 0x0000FF00L
++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2_MASK 0x00FF0000L
++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3_MASK 0xFF000000L
++//SLAVE_COMM_CMD_REG
++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0__SHIFT 0x0
++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1__SHIFT 0x8
++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2__SHIFT 0x10
++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3__SHIFT 0x18
++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0_MASK 0x000000FFL
++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1_MASK 0x0000FF00L
++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2_MASK 0x00FF0000L
++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3_MASK 0xFF000000L
++//SLAVE_COMM_CNTL_REG
++#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT__SHIFT 0x0
++#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS__SHIFT 0x8
++#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT_MASK 0x00000001L
++#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS_MASK 0x00000100L
++//BL1_PWM_AMBIENT_LIGHT_LEVEL
++#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0
++#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x0001FFFFL
++//BL1_PWM_USER_LEVEL
++#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0
++#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x0001FFFFL
++//BL1_PWM_TARGET_ABM_LEVEL
++#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0
++#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x0001FFFFL
++//BL1_PWM_CURRENT_ABM_LEVEL
++#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0
++#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x0001FFFFL
++//BL1_PWM_FINAL_DUTY_CYCLE
++#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0
++#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x0001FFFFL
++//BL1_PWM_MINIMUM_DUTY_CYCLE
++#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0
++#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x0001FFFFL
++//BL1_PWM_ABM_CNTL
++#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0
++#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1
++#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2
++#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3
++#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10
++#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x00000001L
++#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x00000002L
++#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x00000004L
++#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x00000008L
++#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xFFFF0000L
++//BL1_PWM_BL_UPDATE_SAMPLE_RATE
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L
++//BL1_PWM_GRP2_REG_LOCK
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x0
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x11
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x18
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x00000001L
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x00000100L
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x00010000L
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0x000E0000L
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L
++//DMCU_INTERRUPT_TO_UC_EN_MASK_1
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV0_POWER_UP_INT_TO_UC_EN__SHIFT 0x0
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x1
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCFEV0_VBLANK_INT_TO_UC_EN__SHIFT 0x2
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV1_POWER_UP_INT_TO_UC_EN__SHIFT 0x3
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x4
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCFEV1_VBLANK_INT_TO_UC_EN__SHIFT 0x5
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC0_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0x6
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC1_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0x7
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC2_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0x8
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC3_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0x9
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC4_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0xa
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC5_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0xb
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DMCU_GENERIC_INT_TO_UC_EN__SHIFT 0xd
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV0_POWER_UP_INT_TO_UC_EN_MASK 0x00000001L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000002L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCFEV0_VBLANK_INT_TO_UC_EN_MASK 0x00000004L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV1_POWER_UP_INT_TO_UC_EN_MASK 0x00000008L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000010L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCFEV1_VBLANK_INT_TO_UC_EN_MASK 0x00000020L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC0_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000040L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC1_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000080L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC2_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000100L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC3_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000200L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC4_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000400L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC5_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000800L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DMCU_GENERIC_INT_TO_UC_EN_MASK 0x00002000L
++//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x1
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCFEV0_VBLANK_INT_XIRQ_IRQ_SEL__SHIFT 0x2
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x3
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x4
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCFEV1_VBLANK_INT_XIRQ_IRQ_SEL__SHIFT 0x5
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x6
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x7
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x8
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x9
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0xa
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0xb
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DMCU_GENERIC_INT_XIRQ_IRQ_SEL__SHIFT 0xd
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000001L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000002L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCFEV0_VBLANK_INT_XIRQ_IRQ_SEL_MASK 0x00000004L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000008L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000010L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCFEV1_VBLANK_INT_XIRQ_IRQ_SEL_MASK 0x00000020L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000040L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000080L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000100L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000200L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000400L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000800L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DMCU_GENERIC_INT_XIRQ_IRQ_SEL_MASK 0x00002000L
++//DMCU_INTERRUPT_STATUS_1
++#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_UP_INT_OCCURRED__SHIFT 0x0
++#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_UP_INT_CLEAR__SHIFT 0x0
++#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_UP_INT_OCCURRED__SHIFT 0x1
++#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_UP_INT_CLEAR__SHIFT 0x1
++#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_OCCURRED__SHIFT 0x2
++#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_CLEAR__SHIFT 0x2
++#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_OCCURRED__SHIFT 0x3
++#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_CLEAR__SHIFT 0x3
++#define DMCU_INTERRUPT_STATUS_1__DCFEV0_VBLANK_INT_OCCURRED__SHIFT 0x4
++#define DMCU_INTERRUPT_STATUS_1__DCFEV0_VBLANK_INT_CLEAR__SHIFT 0x4
++#define DMCU_INTERRUPT_STATUS_1__DCFEV1_VBLANK_INT_OCCURRED__SHIFT 0x5
++#define DMCU_INTERRUPT_STATUS_1__DCFEV1_VBLANK_INT_CLEAR__SHIFT 0x5
++#define DMCU_INTERRUPT_STATUS_1__CRTC0_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x6
++#define DMCU_INTERRUPT_STATUS_1__CRTC0_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0x6
++#define DMCU_INTERRUPT_STATUS_1__CRTC1_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x7
++#define DMCU_INTERRUPT_STATUS_1__CRTC1_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0x7
++#define DMCU_INTERRUPT_STATUS_1__CRTC2_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x8
++#define DMCU_INTERRUPT_STATUS_1__CRTC2_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0x8
++#define DMCU_INTERRUPT_STATUS_1__CRTC3_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x9
++#define DMCU_INTERRUPT_STATUS_1__CRTC3_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0x9
++#define DMCU_INTERRUPT_STATUS_1__CRTC4_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0xa
++#define DMCU_INTERRUPT_STATUS_1__CRTC4_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0xa
++#define DMCU_INTERRUPT_STATUS_1__CRTC5_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0xb
++#define DMCU_INTERRUPT_STATUS_1__CRTC5_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0xb
++#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_OCCURRED__SHIFT 0xd
++#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_CLEAR__SHIFT 0xd
++#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_UP_INT_OCCURRED_MASK 0x00000001L
++#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_UP_INT_CLEAR_MASK 0x00000001L
++#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_UP_INT_OCCURRED_MASK 0x00000002L
++#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_UP_INT_CLEAR_MASK 0x00000002L
++#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_OCCURRED_MASK 0x00000004L
++#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_CLEAR_MASK 0x00000004L
++#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_OCCURRED_MASK 0x00000008L
++#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_CLEAR_MASK 0x00000008L
++#define DMCU_INTERRUPT_STATUS_1__DCFEV0_VBLANK_INT_OCCURRED_MASK 0x00000010L
++#define DMCU_INTERRUPT_STATUS_1__DCFEV0_VBLANK_INT_CLEAR_MASK 0x00000010L
++#define DMCU_INTERRUPT_STATUS_1__DCFEV1_VBLANK_INT_OCCURRED_MASK 0x00000020L
++#define DMCU_INTERRUPT_STATUS_1__DCFEV1_VBLANK_INT_CLEAR_MASK 0x00000020L
++#define DMCU_INTERRUPT_STATUS_1__CRTC0_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000040L
++#define DMCU_INTERRUPT_STATUS_1__CRTC0_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000040L
++#define DMCU_INTERRUPT_STATUS_1__CRTC1_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000080L
++#define DMCU_INTERRUPT_STATUS_1__CRTC1_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000080L
++#define DMCU_INTERRUPT_STATUS_1__CRTC2_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000100L
++#define DMCU_INTERRUPT_STATUS_1__CRTC2_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000100L
++#define DMCU_INTERRUPT_STATUS_1__CRTC3_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000200L
++#define DMCU_INTERRUPT_STATUS_1__CRTC3_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000200L
++#define DMCU_INTERRUPT_STATUS_1__CRTC4_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000400L
++#define DMCU_INTERRUPT_STATUS_1__CRTC4_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000400L
++#define DMCU_INTERRUPT_STATUS_1__CRTC5_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000800L
++#define DMCU_INTERRUPT_STATUS_1__CRTC5_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000800L
++#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_OCCURRED_MASK 0x00002000L
++#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_CLEAR_MASK 0x00002000L
++//DMCU_DPRX_INTERRUPT_STATUS1
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED__SHIFT 0x0
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR__SHIFT 0x0
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT 0x1
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT 0x1
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED__SHIFT 0x2
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR__SHIFT 0x2
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED__SHIFT 0x3
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR__SHIFT 0x3
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED__SHIFT 0x4
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR__SHIFT 0x4
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED__SHIFT 0x5
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR__SHIFT 0x5
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT 0x6
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT 0x6
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED__SHIFT 0x7
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR__SHIFT 0x7
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED__SHIFT 0x8
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR__SHIFT 0x8
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED__SHIFT 0x9
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR__SHIFT 0x9
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xa
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xa
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xb
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xb
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xc
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xc
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xd
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xd
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xe
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xe
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xf
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xf
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0x10
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0x10
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED__SHIFT 0x11
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR__SHIFT 0x11
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED__SHIFT 0x12
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR__SHIFT 0x12
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED__SHIFT 0x13
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR__SHIFT 0x13
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED__SHIFT 0x14
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR__SHIFT 0x14
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED__SHIFT 0x15
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR__SHIFT 0x15
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED__SHIFT 0x16
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR__SHIFT 0x16
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED__SHIFT 0x17
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR__SHIFT 0x17
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED__SHIFT 0x18
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR__SHIFT 0x18
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED__SHIFT 0x19
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR__SHIFT 0x19
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED__SHIFT 0x1a
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR__SHIFT 0x1a
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED__SHIFT 0x1b
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR__SHIFT 0x1b
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED__SHIFT 0x1c
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR__SHIFT 0x1c
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED_MASK 0x00000001L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR_MASK 0x00000001L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK 0x00000002L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK 0x00000002L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED_MASK 0x00000004L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR_MASK 0x00000004L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED_MASK 0x00000008L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR_MASK 0x00000008L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED_MASK 0x00000010L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR_MASK 0x00000010L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED_MASK 0x00000020L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR_MASK 0x00000020L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK 0x00000040L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK 0x00000040L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED_MASK 0x00000080L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR_MASK 0x00000080L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED_MASK 0x00000100L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR_MASK 0x00000100L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED_MASK 0x00000200L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR_MASK 0x00000200L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00000400L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00000400L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00000800L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00000800L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00001000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00001000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00002000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00002000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00004000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00004000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00008000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00008000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00010000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00010000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED_MASK 0x00020000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR_MASK 0x00020000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED_MASK 0x00040000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR_MASK 0x00040000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED_MASK 0x00080000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR_MASK 0x00080000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED_MASK 0x00100000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR_MASK 0x00100000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED_MASK 0x00200000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR_MASK 0x00200000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED_MASK 0x00400000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR_MASK 0x00400000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED_MASK 0x00800000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR_MASK 0x00800000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED_MASK 0x01000000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR_MASK 0x01000000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED_MASK 0x02000000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR_MASK 0x02000000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED_MASK 0x04000000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR_MASK 0x04000000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED_MASK 0x08000000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR_MASK 0x08000000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED_MASK 0x10000000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR_MASK 0x10000000L
++//DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT 0x0
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT 0x1
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN__SHIFT 0x2
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN__SHIFT 0x3
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT 0x4
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT 0x5
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT 0x6
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN__SHIFT 0x7
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN__SHIFT 0x8
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT 0x9
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xa
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xb
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xc
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xd
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xe
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xf
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0x10
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN__SHIFT 0x11
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN__SHIFT 0x12
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN__SHIFT 0x13
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN__SHIFT 0x14
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN__SHIFT 0x15
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN__SHIFT 0x16
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN__SHIFT 0x17
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN__SHIFT 0x18
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN__SHIFT 0x19
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1a
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1b
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1c
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN_MASK 0x00000001L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK 0x00000002L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN_MASK 0x00000004L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN_MASK 0x00000008L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN_MASK 0x00000010L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN_MASK 0x00000020L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK 0x00000040L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN_MASK 0x00000080L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN_MASK 0x00000100L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN_MASK 0x00000200L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00000400L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00000800L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00001000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00002000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00004000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00008000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00010000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN_MASK 0x00020000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN_MASK 0x00040000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN_MASK 0x00080000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN_MASK 0x00100000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN_MASK 0x00200000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN_MASK 0x00400000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN_MASK 0x00800000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN_MASK 0x01000000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN_MASK 0x02000000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN_MASK 0x04000000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN_MASK 0x08000000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN_MASK 0x10000000L
++//DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x0
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT 0x1
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT 0x2
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT 0x3
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x4
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x5
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT 0x6
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT 0x7
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT 0x8
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x9
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xa
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xb
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xc
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xd
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xe
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xf
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0x10
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL__SHIFT 0x11
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL__SHIFT 0x12
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL__SHIFT 0x13
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL__SHIFT 0x14
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL__SHIFT 0x15
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL__SHIFT 0x16
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL__SHIFT 0x17
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL__SHIFT 0x18
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x19
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1b
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1c
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x00000001L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK 0x00000002L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK 0x00000004L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK 0x00000008L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x00000010L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x00000020L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK 0x00000040L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK 0x00000080L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK 0x00000100L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x00000200L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00000400L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00000800L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00001000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00002000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00004000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00008000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00010000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL_MASK 0x00020000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL_MASK 0x00040000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL_MASK 0x00080000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL_MASK 0x00100000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL_MASK 0x00200000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL_MASK 0x00400000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL_MASK 0x00800000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL_MASK 0x01000000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x02000000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x04000000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x08000000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x10000000L
++//DC_ABM1_CNTL
++#define DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0
++#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT 0x8
++#define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE__SHIFT 0x1f
++#define DC_ABM1_CNTL__ABM1_EN_MASK 0x00000001L
++#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT_MASK 0x00000700L
++#define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE_MASK 0x80000000L
++//DC_ABM1_IPCSC_COEFF_SEL
++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0
++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8
++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10
++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0x0000000FL
++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0x00000F00L
++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0x000F0000L
++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L
++//DC_ABM1_ACE_OFFSET_SLOPE_0
++#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x0
++#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10
++#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x1f
++#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x00007FFFL
++#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x07FF0000L
++#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000L
++//DC_ABM1_ACE_OFFSET_SLOPE_1
++#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x0
++#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10
++#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x1f
++#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x00007FFFL
++#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x07FF0000L
++#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000L
++//DC_ABM1_ACE_OFFSET_SLOPE_2
++#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x0
++#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10
++#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x1f
++#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x00007FFFL
++#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x07FF0000L
++#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000L
++//DC_ABM1_ACE_OFFSET_SLOPE_3
++#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x0
++#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10
++#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x1f
++#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x00007FFFL
++#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x07FF0000L
++#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000L
++//DC_ABM1_ACE_OFFSET_SLOPE_4
++#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x0
++#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10
++#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x1f
++#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x00007FFFL
++#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x07FF0000L
++#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000L
++//DC_ABM1_ACE_THRES_12
++#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x0
++#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x10
++#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x1f
++#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x000003FFL
++#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x03FF0000L
++#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000L
++//DC_ABM1_ACE_THRES_34
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x0
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x10
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x1f
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x000003FFL
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x03FF0000L
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000L
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000L
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000L
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000L
++//DC_ABM1_ACE_CNTL_MISC
++#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0
++#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8
++#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x00000001L
++#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x00000100L
++//DMCU_PERFMON_INTERRUPT_STATUS5
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x00000001L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER0_INT_CLEAR_MASK 0x00000001L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x00000002L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER1_INT_CLEAR_MASK 0x00000002L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x00000004L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER2_INT_CLEAR_MASK 0x00000004L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x00000008L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER3_INT_CLEAR_MASK 0x00000008L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x00000010L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER4_INT_CLEAR_MASK 0x00000010L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x00000020L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER5_INT_CLEAR_MASK 0x00000020L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x00000040L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER6_INT_CLEAR_MASK 0x00000040L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x00000080L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER7_INT_CLEAR_MASK 0x00000080L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x00000100L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER0_INT_CLEAR_MASK 0x00000100L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x00000200L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER1_INT_CLEAR_MASK 0x00000200L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x00000400L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER2_INT_CLEAR_MASK 0x00000400L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x00000800L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER3_INT_CLEAR_MASK 0x00000800L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x00001000L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER4_INT_CLEAR_MASK 0x00001000L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x00002000L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER5_INT_CLEAR_MASK 0x00002000L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x00004000L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER6_INT_CLEAR_MASK 0x00004000L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x00008000L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER7_INT_CLEAR_MASK 0x00008000L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x00010000L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x00010000L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x00020000L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x00020000L
++//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x00000001L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x00000002L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x00000004L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x00000008L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x00000010L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x00000020L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x00000040L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x00000080L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x00000100L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x00000200L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x00000400L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x00000800L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x00001000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x00002000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x00004000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x00008000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x00010000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x00020000L
++//DMCU_PERFMON_INTERRUPT_STATUS1
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x00000001L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_CLEAR_MASK 0x00000001L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x00000002L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR_MASK 0x00000002L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x00000004L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR_MASK 0x00000004L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x00000008L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_CLEAR_MASK 0x00000008L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x00000010L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_CLEAR_MASK 0x00000010L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x00000020L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_CLEAR_MASK 0x00000020L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x00000040L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_CLEAR_MASK 0x00000040L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x00000080L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_CLEAR_MASK 0x00000080L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x00000100L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_CLEAR_MASK 0x00000100L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x00000200L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_CLEAR_MASK 0x00000200L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x00000400L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_CLEAR_MASK 0x00000400L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x00000800L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_CLEAR_MASK 0x00000800L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x00001000L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_CLEAR_MASK 0x00001000L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x00002000L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_CLEAR_MASK 0x00002000L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x00004000L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_CLEAR_MASK 0x00004000L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x00008000L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_CLEAR_MASK 0x00008000L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x00010000L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_CLEAR_MASK 0x00010000L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x00020000L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_CLEAR_MASK 0x00020000L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x00040000L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_CLEAR_MASK 0x00040000L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x00080000L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_CLEAR_MASK 0x00080000L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x00100000L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_CLEAR_MASK 0x00100000L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x00200000L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_CLEAR_MASK 0x00200000L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x00400000L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_CLEAR_MASK 0x00400000L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x00800000L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_CLEAR_MASK 0x00800000L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x01000000L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x01000000L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x02000000L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x02000000L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x04000000L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x04000000L
++//DMCU_PERFMON_INTERRUPT_STATUS2
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x00000001L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_CLEAR_MASK 0x00000001L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x00000002L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR_MASK 0x00000002L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x00000004L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR_MASK 0x00000004L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x00000008L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_CLEAR_MASK 0x00000008L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x00000010L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_CLEAR_MASK 0x00000010L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x00000020L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_CLEAR_MASK 0x00000020L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x00000040L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_CLEAR_MASK 0x00000040L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x00000080L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_CLEAR_MASK 0x00000080L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x00000100L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_CLEAR_MASK 0x00000100L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x00000200L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_CLEAR_MASK 0x00000200L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x00000400L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_CLEAR_MASK 0x00000400L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x00000800L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_CLEAR_MASK 0x00000800L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x00001000L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_CLEAR_MASK 0x00001000L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x00002000L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_CLEAR_MASK 0x00002000L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x00004000L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_CLEAR_MASK 0x00004000L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x00008000L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_CLEAR_MASK 0x00008000L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x00010000L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_CLEAR_MASK 0x00010000L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x00020000L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_CLEAR_MASK 0x00020000L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x00040000L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_CLEAR_MASK 0x00040000L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x00080000L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_CLEAR_MASK 0x00080000L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x00100000L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_CLEAR_MASK 0x00100000L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x00200000L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_CLEAR_MASK 0x00200000L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x00400000L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_CLEAR_MASK 0x00400000L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x00800000L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_CLEAR_MASK 0x00800000L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x01000000L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x01000000L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x02000000L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x02000000L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x04000000L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x04000000L
++//DMCU_PERFMON_INTERRUPT_STATUS3
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x00000001L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_CLEAR_MASK 0x00000001L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x00000002L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR_MASK 0x00000002L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x00000004L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR_MASK 0x00000004L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x00000008L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_CLEAR_MASK 0x00000008L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x00000010L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_CLEAR_MASK 0x00000010L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x00000020L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_CLEAR_MASK 0x00000020L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x00000040L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_CLEAR_MASK 0x00000040L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x00000080L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_CLEAR_MASK 0x00000080L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x00000100L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_CLEAR_MASK 0x00000100L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x00000200L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_CLEAR_MASK 0x00000200L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x00000400L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_CLEAR_MASK 0x00000400L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x00000800L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_CLEAR_MASK 0x00000800L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x00001000L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_CLEAR_MASK 0x00001000L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x00002000L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_CLEAR_MASK 0x00002000L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x00004000L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_CLEAR_MASK 0x00004000L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x00008000L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_CLEAR_MASK 0x00008000L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x00010000L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_CLEAR_MASK 0x00010000L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x00020000L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_CLEAR_MASK 0x00020000L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x00040000L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_CLEAR_MASK 0x00040000L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x00080000L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_CLEAR_MASK 0x00080000L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x00100000L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_CLEAR_MASK 0x00100000L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x00200000L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_CLEAR_MASK 0x00200000L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x00400000L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_CLEAR_MASK 0x00400000L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x00800000L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_CLEAR_MASK 0x00800000L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x01000000L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x01000000L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x02000000L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x02000000L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x04000000L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x04000000L
++//DMCU_PERFMON_INTERRUPT_STATUS4
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER0_INT_OCCURRED__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER0_INT_CLEAR__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER1_INT_OCCURRED__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER1_INT_CLEAR__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER2_INT_OCCURRED__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER2_INT_CLEAR__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER3_INT_OCCURRED__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER3_INT_CLEAR__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER4_INT_OCCURRED__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER4_INT_CLEAR__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER5_INT_OCCURRED__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER5_INT_CLEAR__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER6_INT_OCCURRED__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER6_INT_CLEAR__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER7_INT_OCCURRED__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER7_INT_CLEAR__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x00000001L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_CLEAR_MASK 0x00000001L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x00000002L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_CLEAR_MASK 0x00000002L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x00000004L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_CLEAR_MASK 0x00000004L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x00000008L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_CLEAR_MASK 0x00000008L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x00000010L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_CLEAR_MASK 0x00000010L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x00000020L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_CLEAR_MASK 0x00000020L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x00000040L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_CLEAR_MASK 0x00000040L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x00000080L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_CLEAR_MASK 0x00000080L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x00000100L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_CLEAR_MASK 0x00000100L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x00000200L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_CLEAR_MASK 0x00000200L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x00000400L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_CLEAR_MASK 0x00000400L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x00000800L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_CLEAR_MASK 0x00000800L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x00001000L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_CLEAR_MASK 0x00001000L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x00002000L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_CLEAR_MASK 0x00002000L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x00004000L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_CLEAR_MASK 0x00004000L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x00008000L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_CLEAR_MASK 0x00008000L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER0_INT_OCCURRED_MASK 0x00010000L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER0_INT_CLEAR_MASK 0x00010000L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER1_INT_OCCURRED_MASK 0x00020000L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER1_INT_CLEAR_MASK 0x00020000L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER2_INT_OCCURRED_MASK 0x00040000L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER2_INT_CLEAR_MASK 0x00040000L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER3_INT_OCCURRED_MASK 0x00080000L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER3_INT_CLEAR_MASK 0x00080000L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER4_INT_OCCURRED_MASK 0x00100000L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER4_INT_CLEAR_MASK 0x00100000L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER5_INT_OCCURRED_MASK 0x00200000L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER5_INT_CLEAR_MASK 0x00200000L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER6_INT_OCCURRED_MASK 0x00400000L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER6_INT_CLEAR_MASK 0x00400000L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER7_INT_OCCURRED_MASK 0x00800000L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER7_INT_CLEAR_MASK 0x00800000L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x01000000L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x01000000L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x02000000L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x02000000L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_OFF_INT_OCCURRED_MASK 0x04000000L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_OFF_INT_CLEAR_MASK 0x04000000L
++//DC_ABM1_HGLS_REG_READ_PROGRESS
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x00000001L
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x00000002L
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x00000004L
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x00000100L
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x00000200L
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x00000400L
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x00010000L
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x01000000L
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000L
++//DC_ABM1_HG_MISC_CTRL
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0xc
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10
++#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14
++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x17
++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x18
++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x1c
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x1d
++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x1e
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x00000003L
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x00000100L
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x00001000L
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x00030000L
++#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x00100000L
++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x00800000L
++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x07000000L
++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000L
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000L
++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000L
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L
++//DC_ABM1_LS_SUM_OF_LUMA
++#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0
++#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xFFFFFFFFL
++//DC_ABM1_LS_MIN_MAX_LUMA
++#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0
++#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10
++#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x000003FFL
++#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x03FF0000L
++//DC_ABM1_LS_FILTERED_MIN_MAX_LUMA
++#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0
++#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10
++#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x000003FFL
++#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x03FF0000L
++//DC_ABM1_LS_PIXEL_COUNT
++#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0
++#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0x00FFFFFFL
++//DC_ABM1_LS_OVR_SCAN_BIN
++#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN__SHIFT 0x0
++#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN_MASK 0x00FFFFFFL
++//DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
++#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0
++#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10
++#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
++#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x000003FFL
++#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x03FF0000L
++#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000L
++//DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT
++#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0
++#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL
++//DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT
++#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0
++#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL
++//DC_ABM1_HG_SAMPLE_RATE
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L
++//DC_ABM1_LS_SAMPLE_RATE
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L
++//DC_ABM1_HG_BIN_1_32_SHIFT_FLAG
++#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0
++#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xFFFFFFFFL
++//DC_ABM1_HG_BIN_1_8_SHIFT_INDEX
++#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0
++#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xFFFFFFFFL
++//DC_ABM1_HG_BIN_9_16_SHIFT_INDEX
++#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0
++#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xFFFFFFFFL
++//DC_ABM1_HG_BIN_17_24_SHIFT_INDEX
++#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0
++#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xFFFFFFFFL
++//DC_ABM1_HG_BIN_25_32_SHIFT_INDEX
++#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0
++#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_1
++#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_2
++#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_3
++#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_4
++#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_5
++#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_6
++#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_7
++#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_8
++#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_9
++#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_10
++#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_11
++#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_12
++#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_13
++#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_14
++#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_15
++#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_16
++#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_17
++#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_18
++#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_19
++#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_20
++#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_21
++#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_22
++#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_23
++#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_24
++#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xFFFFFFFFL
++//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00000001L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00000002L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00000004L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00000008L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00000010L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00000020L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00000040L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00000080L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x00000100L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00000200L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00000400L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00000800L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00001000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00002000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00004000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00008000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00010000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x00020000L
++//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x00000001L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x00000002L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x00000004L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x00000008L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x00000010L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x00000020L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x00000040L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x00000080L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x00000100L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x00000200L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x00000400L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x00000800L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x00001000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x00002000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x00004000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x00008000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x00010000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x00020000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x00040000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x00080000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x00100000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x00200000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x00400000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x00800000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x01000000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x02000000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x04000000L
++//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x00000001L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x00000002L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x00000004L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x00000008L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x00000010L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x00000020L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x00000040L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x00000080L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x00000100L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x00000200L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x00000400L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x00000800L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x00001000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x00002000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x00004000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x00008000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x00010000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x00020000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x00040000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x00080000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x00100000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x00200000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x00400000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x00800000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x01000000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x02000000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x04000000L
++//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x00000001L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x00000002L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x00000004L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x00000008L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x00000010L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x00000020L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x00000040L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x00000080L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x00000100L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x00000200L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x00000400L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x00000800L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x00001000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x00002000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x00004000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x00008000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x00010000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x00020000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x00040000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x00080000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x00100000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x00200000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x00400000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x00800000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x01000000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x02000000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x04000000L
++//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER0_INT_TO_UC_EN__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER1_INT_TO_UC_EN__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER2_INT_TO_UC_EN__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER3_INT_TO_UC_EN__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER4_INT_TO_UC_EN__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER5_INT_TO_UC_EN__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER6_INT_TO_UC_EN__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER7_INT_TO_UC_EN__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x00000001L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x00000002L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x00000004L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x00000008L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x00000010L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x00000020L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x00000040L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x00000080L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x00000100L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x00000200L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x00000400L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x00000800L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x00001000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x00002000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x00004000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x00008000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER0_INT_TO_UC_EN_MASK 0x00010000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER1_INT_TO_UC_EN_MASK 0x00020000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER2_INT_TO_UC_EN_MASK 0x00040000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER3_INT_TO_UC_EN_MASK 0x00080000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER4_INT_TO_UC_EN_MASK 0x00100000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER5_INT_TO_UC_EN_MASK 0x00200000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER6_INT_TO_UC_EN_MASK 0x00400000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER7_INT_TO_UC_EN_MASK 0x00800000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x01000000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x02000000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER_OFF_INT_TO_UC_EN_MASK 0x04000000L
++//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00000001L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00000002L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00000004L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00000008L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00000010L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00000020L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00000040L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00000080L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00000100L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00000200L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00000400L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00000800L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00001000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00002000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00004000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00008000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00010000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00020000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00040000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00080000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00100000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00200000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00400000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00800000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x01000000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x02000000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x04000000L
++//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00000001L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00000002L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00000004L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00000008L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00000010L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00000020L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00000040L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00000080L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00000100L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00000200L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00000400L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00000800L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00001000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00002000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00004000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00008000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00010000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00020000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00040000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00080000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00100000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00200000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00400000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00800000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x01000000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x02000000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x04000000L
++//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00000001L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00000002L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00000004L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00000008L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00000010L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00000020L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00000040L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00000080L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00000100L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00000200L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00000400L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00000800L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00001000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00002000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00004000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00008000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00010000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00020000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00040000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00080000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00100000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00200000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00400000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00800000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x01000000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x02000000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x04000000L
++//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00000001L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00000002L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00000004L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00000008L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00000010L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00000020L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00000040L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00000080L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00000100L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00000200L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00000400L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00000800L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00001000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00002000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00004000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00008000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00010000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00020000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00040000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00080000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00100000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00200000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00400000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00800000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x01000000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x02000000L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x04000000L
++//DC_ABM1_OVERSCAN_PIXEL_VALUE
++#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE__SHIFT 0x0
++#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE__SHIFT 0xa
++#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE__SHIFT 0x14
++#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE_MASK 0x000003FFL
++#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE_MASK 0x000FFC00L
++#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE_MASK 0x3FF00000L
++//DC_ABM1_BL_MASTER_LOCK
++#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f
++#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L
++//AZALIA_CONTROLLER_CLOCK_GATING
++#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT 0x0
++#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT 0x4
++#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK 0x00000001L
++#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK 0x00000010L
++//AZALIA_AUDIO_DTO
++#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT 0x0
++#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT 0x10
++#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK 0x0000FFFFL
++#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK 0xFFFF0000L
++//AZALIA_AUDIO_DTO_CONTROL
++#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT 0x8
++#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK 0x00000300L
++//AZALIA_SOCCLK_CONTROL
++#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN__SHIFT 0x1
++#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN_MASK 0x00000002L
++//AZALIA_UNDERFLOW_FILLER_SAMPLE
++#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT 0x0
++#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK 0xFFFFFFFFL
++//AZALIA_DATA_DMA_CONTROL
++#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT 0x0
++#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP__SHIFT 0x2
++#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT 0x4
++#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS__SHIFT 0x6
++#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT 0x10
++#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT 0x11
++#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK 0x00000003L
++#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP_MASK 0x0000000CL
++#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK 0x00000030L
++#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS_MASK 0x000000C0L
++#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK 0x00010000L
++#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK 0x00020000L
++//AZALIA_BDL_DMA_CONTROL
++#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT 0x0
++#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP__SHIFT 0x2
++#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT 0x4
++#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS__SHIFT 0x6
++#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK 0x00000003L
++#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP_MASK 0x0000000CL
++#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK 0x00000030L
++#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS_MASK 0x000000C0L
++//AZALIA_RIRB_AND_DP_CONTROL
++#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT 0x0
++#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT 0x4
++#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER__SHIFT 0x5
++#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK 0x00000001L
++#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK 0x00000010L
++#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER_MASK 0x000001E0L
++//AZALIA_CORB_DMA_CONTROL
++#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT 0x0
++#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT 0x4
++#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK 0x00000001L
++#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK 0x00000010L
++//AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER
++#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT 0x0
++#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK 0xFFFFFFFFL
++//AZALIA_CYCLIC_BUFFER_SYNC
++#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT 0x0
++#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK 0x00000001L
++//AZALIA_GLOBAL_CAPABILITIES
++#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1
++#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x00000006L
++//AZALIA_OUTPUT_PAYLOAD_CAPABILITY
++#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0
++#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x10
++#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0x0000FFFFL
++#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xFFFF0000L
++//AZALIA_OUTPUT_STREAM_ARBITER_CONTROL
++#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT 0x0
++#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT 0x8
++#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL__SHIFT 0x10
++#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK 0x000000FFL
++#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK 0x00000100L
++#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL_MASK 0x00FF0000L
++//AZALIA_INPUT_PAYLOAD_CAPABILITY
++#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0
++#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT 0x10
++#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0x0000FFFFL
++#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY_MASK 0xFFFF0000L
++//AZALIA_INPUT_CRC0_CONTROL0
++#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN__SHIFT 0x0
++#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4
++#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8
++#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN_MASK 0x00000001L
++#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x00000010L
++#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x00000700L
++//AZALIA_INPUT_CRC0_CONTROL1
++#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0
++#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL
++//AZALIA_INPUT_CRC0_CONTROL2
++#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0
++#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0x0000FFFFL
++//AZALIA_INPUT_CRC0_CONTROL3
++#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0
++#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4
++#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8
++#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x00000001L
++#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L
++#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L
++//AZALIA_INPUT_CRC0_RESULT
++#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT__SHIFT 0x0
++#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT_MASK 0xFFFFFFFFL
++//AZALIA_INPUT_CRC1_CONTROL0
++#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN__SHIFT 0x0
++#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4
++#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8
++#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN_MASK 0x00000001L
++#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x00000010L
++#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x00000700L
++//AZALIA_INPUT_CRC1_CONTROL1
++#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0
++#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL
++//AZALIA_INPUT_CRC1_CONTROL2
++#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0
++#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0x0000FFFFL
++//AZALIA_INPUT_CRC1_CONTROL3
++#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0
++#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4
++#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8
++#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x00000001L
++#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L
++#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L
++//AZALIA_INPUT_CRC1_RESULT
++#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT__SHIFT 0x0
++#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT_MASK 0xFFFFFFFFL
++//AZALIA_CRC0_CONTROL0
++#define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT 0x0
++#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4
++#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8
++#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc
++#define AZALIA_CRC0_CONTROL0__CRC_EN_MASK 0x00000001L
++#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK 0x00000010L
++#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK 0x00000700L
++#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK 0x00001000L
++//AZALIA_CRC0_CONTROL1
++#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0
++#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL
++//AZALIA_CRC0_CONTROL2
++#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0
++#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK 0x0000FFFFL
++//AZALIA_CRC0_CONTROL3
++#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT 0x0
++#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4
++#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8
++#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK 0x00000001L
++#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L
++#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L
++//AZALIA_CRC0_RESULT
++#define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT 0x0
++#define AZALIA_CRC0_RESULT__CRC_RESULT_MASK 0xFFFFFFFFL
++//AZALIA_CRC1_CONTROL0
++#define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT 0x0
++#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4
++#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8
++#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc
++#define AZALIA_CRC1_CONTROL0__CRC_EN_MASK 0x00000001L
++#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK 0x00000010L
++#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK 0x00000700L
++#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK 0x00001000L
++//AZALIA_CRC1_CONTROL1
++#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0
++#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL
++//AZALIA_CRC1_CONTROL2
++#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0
++#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK 0x0000FFFFL
++//AZALIA_CRC1_CONTROL3
++#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT 0x0
++#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4
++#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8
++#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK 0x00000001L
++#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L
++#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L
++//AZALIA_CRC1_RESULT
++#define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT 0x0
++#define AZALIA_CRC1_RESULT__CRC_RESULT_MASK 0xFFFFFFFFL
++//AZALIA_MEM_PWR_CTRL
++#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE__SHIFT 0x0
++#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS__SHIFT 0x2
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE__SHIFT 0x3
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS__SHIFT 0x5
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE__SHIFT 0x6
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS__SHIFT 0x8
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE__SHIFT 0x9
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS__SHIFT 0xb
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE__SHIFT 0xc
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS__SHIFT 0xe
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE__SHIFT 0xf
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS__SHIFT 0x11
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE__SHIFT 0x12
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS__SHIFT 0x14
++#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL__SHIFT 0x1c
++#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE_MASK 0x00000003L
++#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS_MASK 0x00000004L
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE_MASK 0x00000018L
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS_MASK 0x00000020L
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE_MASK 0x000000C0L
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS_MASK 0x00000100L
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE_MASK 0x00000600L
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS_MASK 0x00000800L
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE_MASK 0x00003000L
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS_MASK 0x00004000L
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE_MASK 0x00018000L
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS_MASK 0x00020000L
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE_MASK 0x000C0000L
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS_MASK 0x00100000L
++#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL_MASK 0x30000000L
++//AZALIA_MEM_PWR_STATUS
++#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE__SHIFT 0x0
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE__SHIFT 0x2
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE__SHIFT 0x4
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE__SHIFT 0x6
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE__SHIFT 0x8
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE__SHIFT 0xa
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE__SHIFT 0xc
++#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE_MASK 0x00000003L
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE_MASK 0x0000000CL
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE_MASK 0x00000030L
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE_MASK 0x000000C0L
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE_MASK 0x00000300L
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE_MASK 0x00000C00L
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE_MASK 0x00003000L
++//AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID
++#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0
++#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xFFFFFFFFL
++//AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID
++#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0
++#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xFFFFFFFFL
++//AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL
++#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT 0x0
++#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT 0x4
++#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK 0x00000007L
++#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK 0x00000070L
++//AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL
++#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT 0x0
++#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK 0x0000003FL
++//AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xFFFFFFFFL
++//AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
++//AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xFFFFFFFFL
++//AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3FFFFFFFL
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L
++//AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000FL
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000F0L
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L
++//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L
++//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000FFL
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000FF00L
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00FF0000L
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xFF000000L
++//AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x000000FFL
++//CC_RCU_DC_AUDIO_PORT_CONNECTIVITY
++#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT 0x0
++#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4
++#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK 0x00000007L
++#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L
++//CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY
++#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY__SHIFT 0x0
++#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4
++#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_MASK 0x00000007L
++#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L
++//AZALIA_F0_GTC_GROUP_OFFSET0
++#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0__SHIFT 0x0
++#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0_MASK 0xFFFFFFFFL
++//AZALIA_F0_GTC_GROUP_OFFSET1
++#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1__SHIFT 0x0
++#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1_MASK 0xFFFFFFFFL
++//AZALIA_F0_GTC_GROUP_OFFSET2
++#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2__SHIFT 0x0
++#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2_MASK 0xFFFFFFFFL
++//AZALIA_F0_GTC_GROUP_OFFSET3
++#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3__SHIFT 0x0
++#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3_MASK 0xFFFFFFFFL
++//AZALIA_F0_GTC_GROUP_OFFSET4
++#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4__SHIFT 0x0
++#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4_MASK 0xFFFFFFFFL
++//AZALIA_F0_GTC_GROUP_OFFSET5
++#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5__SHIFT 0x0
++#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5_MASK 0xFFFFFFFFL
++//AZALIA_F0_GTC_GROUP_OFFSET6
++#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6__SHIFT 0x0
++#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6_MASK 0xFFFFFFFFL
++//REG_DC_AUDIO_PORT_CONNECTIVITY
++#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY__SHIFT 0x0
++#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4
++#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_MASK 0x00000007L
++#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L
++//REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY
++#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY__SHIFT 0x0
++#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4
++#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_MASK 0x00000007L
++#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L
++//DAC_ENABLE
++#define DAC_ENABLE__DAC_ENABLE__SHIFT 0x0
++#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE__SHIFT 0x1
++#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW__SHIFT 0x2
++#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR__SHIFT 0x4
++#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK__SHIFT 0x5
++#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM__SHIFT 0x8
++#define DAC_ENABLE__DAC_ENABLE_MASK 0x00000001L
++#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE_MASK 0x00000002L
++#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW_MASK 0x0000000CL
++#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_MASK 0x00000010L
++#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK_MASK 0x00000020L
++#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM_MASK 0x00000100L
++//DAC_SOURCE_SELECT
++#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT__SHIFT 0x0
++#define DAC_SOURCE_SELECT__DAC_TV_SELECT__SHIFT 0x3
++#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT_MASK 0x00000007L
++#define DAC_SOURCE_SELECT__DAC_TV_SELECT_MASK 0x00000008L
++//DAC_CRC_EN
++#define DAC_CRC_EN__DAC_CRC_EN__SHIFT 0x0
++#define DAC_CRC_EN__DAC_CRC_CONT_EN__SHIFT 0x10
++#define DAC_CRC_EN__DAC_CRC_EN_MASK 0x00000001L
++#define DAC_CRC_EN__DAC_CRC_CONT_EN_MASK 0x00010000L
++//DAC_CRC_CONTROL
++#define DAC_CRC_CONTROL__DAC_CRC_FIELD__SHIFT 0x0
++#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKB__SHIFT 0x8
++#define DAC_CRC_CONTROL__DAC_CRC_FIELD_MASK 0x00000001L
++#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKB_MASK 0x00000100L
++//DAC_CRC_SIG_RGB_MASK
++#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK__SHIFT 0x0
++#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK__SHIFT 0xa
++#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK__SHIFT 0x14
++#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK_MASK 0x000003FFL
++#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK_MASK 0x000FFC00L
++#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK_MASK 0x3FF00000L
++//DAC_CRC_SIG_CONTROL_MASK
++#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK__SHIFT 0x0
++#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK_MASK 0x0000003FL
++//DAC_CRC_SIG_RGB
++#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE__SHIFT 0x0
++#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN__SHIFT 0xa
++#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED__SHIFT 0x14
++#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE_MASK 0x000003FFL
++#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN_MASK 0x000FFC00L
++#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED_MASK 0x3FF00000L
++//DAC_CRC_SIG_CONTROL
++#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL__SHIFT 0x0
++#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL_MASK 0x0000003FL
++//DAC_SYNC_TRISTATE_CONTROL
++#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE__SHIFT 0x0
++#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE__SHIFT 0x8
++#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE__SHIFT 0x10
++#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE_MASK 0x00000001L
++#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE_MASK 0x00000100L
++#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE_MASK 0x00010000L
++//DAC_STEREOSYNC_SELECT
++#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT__SHIFT 0x0
++#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT_MASK 0x00000007L
++//DAC_AUTODETECT_CONTROL
++#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE__SHIFT 0x0
++#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER__SHIFT 0x8
++#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK__SHIFT 0x10
++#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE_MASK 0x00000003L
++#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER_MASK 0x0000FF00L
++#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK_MASK 0x00070000L
++//DAC_AUTODETECT_CONTROL2
++#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER__SHIFT 0x0
++#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE__SHIFT 0x8
++#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER_MASK 0x000000FFL
++#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE_MASK 0x00000100L
++//DAC_AUTODETECT_CONTROL3
++#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY__SHIFT 0x0
++#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY__SHIFT 0x8
++#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY_MASK 0x000000FFL
++#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY_MASK 0x0000FF00L
++//DAC_AUTODETECT_STATUS
++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS__SHIFT 0x0
++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT__SHIFT 0x4
++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE__SHIFT 0x8
++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE__SHIFT 0x10
++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE__SHIFT 0x18
++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS_MASK 0x00000001L
++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT_MASK 0x00000010L
++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE_MASK 0x00000300L
++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE_MASK 0x00030000L
++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE_MASK 0x03000000L
++//DAC_AUTODETECT_INT_CONTROL
++#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK__SHIFT 0x0
++#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE__SHIFT 0x10
++#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK_MASK 0x00000001L
++#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE_MASK 0x00010000L
++//DAC_FORCE_OUTPUT_CNTL
++#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN__SHIFT 0x0
++#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL__SHIFT 0x8
++#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKB_ONLY__SHIFT 0x18
++#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN_MASK 0x00000001L
++#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL_MASK 0x00000700L
++#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKB_ONLY_MASK 0x01000000L
++//DAC_FORCE_DATA
++#define DAC_FORCE_DATA__DAC_FORCE_DATA__SHIFT 0x0
++#define DAC_FORCE_DATA__DAC_FORCE_DATA_MASK 0x000003FFL
++//DAC_POWERDOWN
++#define DAC_POWERDOWN__DAC_POWERDOWN__SHIFT 0x0
++#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE__SHIFT 0x8
++#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN__SHIFT 0x10
++#define DAC_POWERDOWN__DAC_POWERDOWN_RED__SHIFT 0x18
++#define DAC_POWERDOWN__DAC_POWERDOWN_MASK 0x00000001L
++#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE_MASK 0x00000100L
++#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN_MASK 0x00010000L
++#define DAC_POWERDOWN__DAC_POWERDOWN_RED_MASK 0x01000000L
++//DAC_CONTROL
++#define DAC_CONTROL__DAC_DFORCE_EN__SHIFT 0x0
++#define DAC_CONTROL__DAC_TV_ENABLE__SHIFT 0x8
++#define DAC_CONTROL__DAC_ZSCALE_SHIFT__SHIFT 0x10
++#define DAC_CONTROL__DAC_DFORCE_EN_MASK 0x00000001L
++#define DAC_CONTROL__DAC_TV_ENABLE_MASK 0x00000100L
++#define DAC_CONTROL__DAC_ZSCALE_SHIFT_MASK 0x00010000L
++//DAC_COMPARATOR_ENABLE
++#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN__SHIFT 0x0
++#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN__SHIFT 0x8
++#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE__SHIFT 0x10
++#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE__SHIFT 0x11
++#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE__SHIFT 0x12
++#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN_MASK 0x00000001L
++#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN_MASK 0x00000100L
++#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE_MASK 0x00010000L
++#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE_MASK 0x00020000L
++#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE_MASK 0x00040000L
++//DAC_COMPARATOR_OUTPUT
++#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT__SHIFT 0x0
++#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE__SHIFT 0x1
++#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN__SHIFT 0x2
++#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED__SHIFT 0x3
++#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_MASK 0x00000001L
++#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE_MASK 0x00000002L
++#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN_MASK 0x00000004L
++#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED_MASK 0x00000008L
++//DAC_PWR_CNTL
++#define DAC_PWR_CNTL__DAC_BG_MODE__SHIFT 0x0
++#define DAC_PWR_CNTL__DAC_PWRCNTL__SHIFT 0x10
++#define DAC_PWR_CNTL__DAC_BG_MODE_MASK 0x00000003L
++#define DAC_PWR_CNTL__DAC_PWRCNTL_MASK 0x00030000L
++//DAC_DFT_CONFIG
++#define DAC_DFT_CONFIG__DAC_DFT_CONFIG__SHIFT 0x0
++#define DAC_DFT_CONFIG__DAC_DFT_CONFIG_MASK 0xFFFFFFFFL
++//DAC_FIFO_STATUS
++#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
++#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
++#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
++#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
++#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL__SHIFT 0x16
++#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED__SHIFT 0x1d
++#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
++#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
++#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L
++#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL
++#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L
++#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL_MASK 0x000F0000L
++#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L
++#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED_MASK 0x20000000L
++#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L
++#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L
++//DC_I2C_CONTROL
++#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT 0x0
++#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT 0x1
++#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT 0x2
++#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT 0x3
++#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT 0x8
++#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT 0x14
++#define DC_I2C_CONTROL__DC_I2C_GO_MASK 0x00000001L
++#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK 0x00000002L
++#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK 0x00000004L
++#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK 0x00000008L
++#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK 0x00000700L
++#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK 0x00300000L
++//DC_I2C_ARBITRATION
++#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT 0x0
++#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT 0x2
++#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT 0x4
++#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT 0x8
++#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT 0xc
++#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT 0x14
++#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT 0x15
++#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT 0x18
++#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT 0x19
++#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK 0x00000003L
++#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK 0x0000000CL
++#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK 0x00000010L
++#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK 0x00000100L
++#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK 0x00001000L
++#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK 0x00100000L
++#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK 0x00200000L
++#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK 0x01000000L
++#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK 0x02000000L
++//DC_I2C_INTERRUPT_CONTROL
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT 0x0
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT 0x1
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT 0x2
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT 0x4
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT 0x5
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT 0x6
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT 0x8
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT 0x9
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT 0xa
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT 0xc
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT 0xd
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT 0xe
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT 0x10
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT 0x11
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT 0x12
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT 0x14
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT 0x15
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT 0x16
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT 0x18
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT 0x19
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT 0x1a
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT 0x1b
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT 0x1c
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT 0x1d
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK 0x00000001L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK 0x00000002L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK 0x00000004L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK 0x00000010L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK 0x00000020L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK 0x00000040L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK 0x00000100L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK 0x00000200L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK 0x00000400L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK 0x00001000L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK 0x00002000L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK 0x00004000L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK 0x00010000L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK 0x00020000L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK 0x00040000L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK 0x00100000L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK 0x00200000L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK 0x00400000L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK 0x01000000L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK 0x02000000L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK 0x04000000L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK 0x08000000L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK 0x10000000L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK 0x20000000L
++//DC_I2C_SW_STATUS
++#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT 0x0
++#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT 0x2
++#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT 0x4
++#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT 0x5
++#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT 0x6
++#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT 0x7
++#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT 0x8
++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT 0xc
++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT 0xd
++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT 0xe
++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT 0xf
++#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT 0x12
++#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK 0x00000003L
++#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK 0x00000004L
++#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK 0x00000010L
++#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK 0x00000020L
++#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK 0x00000040L
++#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK 0x00000080L
++#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK 0x00000100L
++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK 0x00001000L
++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK 0x00002000L
++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK 0x00004000L
++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK 0x00008000L
++#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK 0x00040000L
++//DC_I2C_DDC1_HW_STATUS
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT 0x0
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT 0x3
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT 0x10
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT 0x11
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT 0x14
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT 0x1c
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK 0x00000003L
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK 0x00000008L
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK 0x00010000L
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK 0x00020000L
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK 0x00100000L
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK 0x70000000L
++//DC_I2C_DDC2_HW_STATUS
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT 0x0
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT 0x3
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT 0x10
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT 0x11
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT 0x14
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT 0x1c
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK 0x00000003L
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK 0x00000008L
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK 0x00010000L
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK 0x00020000L
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK 0x00100000L
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK 0x70000000L
++//DC_I2C_DDC3_HW_STATUS
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT 0x0
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT 0x3
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT 0x10
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT 0x11
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT 0x14
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT 0x1c
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK 0x00000003L
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK 0x00000008L
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK 0x00010000L
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK 0x00020000L
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK 0x00100000L
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK 0x70000000L
++//DC_I2C_DDC4_HW_STATUS
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT 0x0
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT 0x3
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT 0x10
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT 0x11
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT 0x14
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT 0x1c
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK 0x00000003L
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK 0x00000008L
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK 0x00010000L
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK 0x00020000L
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK 0x00100000L
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK 0x70000000L
++//DC_I2C_DDC5_HW_STATUS
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT 0x0
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT 0x3
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT 0x10
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT 0x11
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT 0x14
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT 0x1c
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK 0x00000003L
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK 0x00000008L
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK 0x00010000L
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK 0x00020000L
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK 0x00100000L
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK 0x70000000L
++//DC_I2C_DDC6_HW_STATUS
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS__SHIFT 0x0
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE__SHIFT 0x3
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ__SHIFT 0x10
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG__SHIFT 0x11
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS__SHIFT 0x14
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE__SHIFT 0x1c
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS_MASK 0x00000003L
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE_MASK 0x00000008L
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ_MASK 0x00010000L
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG_MASK 0x00020000L
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS_MASK 0x00100000L
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE_MASK 0x70000000L
++//DC_I2C_DDC1_SPEED
++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT 0x0
++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL__SHIFT 0x8
++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT 0x10
++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK 0x00000003L
++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L
++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL_MASK 0x00000300L
++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK 0xFFFF0000L
++//DC_I2C_DDC1_SETUP
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT 0x0
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT 0x1
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT 0x4
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT 0x5
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT 0x6
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT 0x7
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT 0x8
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT 0x10
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT 0x18
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK 0x00000001L
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK 0x00000002L
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK 0x00000010L
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK 0x00000020L
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK 0x00000040L
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK 0x00000080L
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK 0x0000FF00L
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK 0xFF000000L
++//DC_I2C_DDC2_SPEED
++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT 0x0
++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL__SHIFT 0x8
++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT 0x10
++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK 0x00000003L
++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L
++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL_MASK 0x00000300L
++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK 0xFFFF0000L
++//DC_I2C_DDC2_SETUP
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT 0x0
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT 0x1
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT 0x4
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT 0x5
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT 0x6
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT 0x7
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT 0x8
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT 0x10
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT 0x18
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK 0x00000001L
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK 0x00000002L
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK 0x00000010L
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK 0x00000020L
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK 0x00000040L
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK 0x00000080L
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK 0x0000FF00L
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK 0xFF000000L
++//DC_I2C_DDC3_SPEED
++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT 0x0
++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL__SHIFT 0x8
++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT 0x10
++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK 0x00000003L
++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L
++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL_MASK 0x00000300L
++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK 0xFFFF0000L
++//DC_I2C_DDC3_SETUP
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT 0x0
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT 0x1
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT 0x4
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT 0x5
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT 0x6
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT 0x7
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT 0x8
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT 0x10
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT 0x18
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK 0x00000001L
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK 0x00000002L
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK 0x00000010L
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK 0x00000020L
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK 0x00000040L
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK 0x00000080L
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK 0x0000FF00L
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK 0xFF000000L
++//DC_I2C_DDC4_SPEED
++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT 0x0
++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL__SHIFT 0x8
++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT 0x10
++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK 0x00000003L
++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L
++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL_MASK 0x00000300L
++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK 0xFFFF0000L
++//DC_I2C_DDC4_SETUP
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT 0x0
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT 0x1
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT 0x4
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT 0x5
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT 0x6
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT 0x7
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT 0x8
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT 0x10
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT 0x18
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK 0x00000001L
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK 0x00000002L
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK 0x00000010L
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK 0x00000020L
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK 0x00000040L
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK 0x00000080L
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK 0x0000FF00L
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK 0xFF000000L
++//DC_I2C_DDC5_SPEED
++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT 0x0
++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL__SHIFT 0x8
++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT 0x10
++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK 0x00000003L
++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L
++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL_MASK 0x00000300L
++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK 0xFFFF0000L
++//DC_I2C_DDC5_SETUP
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT 0x0
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT 0x1
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT 0x4
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT 0x5
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT 0x6
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT 0x7
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT 0x8
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT 0x10
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT 0x18
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK 0x00000001L
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK 0x00000002L
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK 0x00000010L
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK 0x00000020L
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK 0x00000040L
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK 0x00000080L
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK 0x0000FF00L
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK 0xFF000000L
++//DC_I2C_DDC6_SPEED
++#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD__SHIFT 0x0
++#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
++#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_START_STOP_TIMING_CNTL__SHIFT 0x8
++#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE__SHIFT 0x10
++#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD_MASK 0x00000003L
++#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L
++#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_START_STOP_TIMING_CNTL_MASK 0x00000300L
++#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE_MASK 0xFFFF0000L
++//DC_I2C_DDC6_SETUP
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN__SHIFT 0x0
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL__SHIFT 0x1
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE__SHIFT 0x4
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE__SHIFT 0x5
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE__SHIFT 0x6
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN__SHIFT 0x7
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY__SHIFT 0x8
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY__SHIFT 0x10
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT__SHIFT 0x18
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN_MASK 0x00000001L
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL_MASK 0x00000002L
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE_MASK 0x00000010L
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE_MASK 0x00000020L
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE_MASK 0x00000040L
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN_MASK 0x00000080L
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY_MASK 0x0000FF00L
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT_MASK 0xFF000000L
++//DC_I2C_TRANSACTION0
++#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT 0x0
++#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT 0x8
++#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT 0xc
++#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT 0xd
++#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT 0x10
++#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK 0x00000001L
++#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK 0x00000100L
++#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK 0x00001000L
++#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK 0x00002000L
++#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK 0x03FF0000L
++//DC_I2C_TRANSACTION1
++#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT 0x0
++#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT 0x8
++#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT 0xc
++#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT 0xd
++#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT 0x10
++#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK 0x00000001L
++#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK 0x00000100L
++#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK 0x00001000L
++#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK 0x00002000L
++#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK 0x03FF0000L
++//DC_I2C_TRANSACTION2
++#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT 0x0
++#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT 0x8
++#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT 0xc
++#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT 0xd
++#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT 0x10
++#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK 0x00000001L
++#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK 0x00000100L
++#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK 0x00001000L
++#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK 0x00002000L
++#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK 0x03FF0000L
++//DC_I2C_TRANSACTION3
++#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT 0x0
++#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT 0x8
++#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT 0xc
++#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT 0xd
++#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT 0x10
++#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK 0x00000001L
++#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK 0x00000100L
++#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK 0x00001000L
++#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK 0x00002000L
++#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK 0x03FF0000L
++//DC_I2C_DATA
++#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT 0x0
++#define DC_I2C_DATA__DC_I2C_DATA__SHIFT 0x8
++#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT 0x10
++#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT 0x1f
++#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK 0x00000001L
++#define DC_I2C_DATA__DC_I2C_DATA_MASK 0x0000FF00L
++#define DC_I2C_DATA__DC_I2C_INDEX_MASK 0x03FF0000L
++#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK 0x80000000L
++//DC_I2C_DDCVGA_HW_STATUS
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS__SHIFT 0x0
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE__SHIFT 0x3
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ__SHIFT 0x10
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG__SHIFT 0x11
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS__SHIFT 0x14
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE__SHIFT 0x1c
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS_MASK 0x00000003L
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE_MASK 0x00000008L
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ_MASK 0x00010000L
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG_MASK 0x00020000L
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS_MASK 0x00100000L
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE_MASK 0x70000000L
++//DC_I2C_DDCVGA_SPEED
++#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD__SHIFT 0x0
++#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
++#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_START_STOP_TIMING_CNTL__SHIFT 0x8
++#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE__SHIFT 0x10
++#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD_MASK 0x00000003L
++#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L
++#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_START_STOP_TIMING_CNTL_MASK 0x00000300L
++#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE_MASK 0xFFFF0000L
++//DC_I2C_DDCVGA_SETUP
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN__SHIFT 0x0
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL__SHIFT 0x1
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE__SHIFT 0x4
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE__SHIFT 0x5
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE__SHIFT 0x6
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN__SHIFT 0x7
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY__SHIFT 0x8
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY__SHIFT 0x10
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT__SHIFT 0x18
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN_MASK 0x00000001L
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL_MASK 0x00000002L
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE_MASK 0x00000010L
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE_MASK 0x00000020L
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE_MASK 0x00000040L
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN_MASK 0x00000080L
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY_MASK 0x0000FF00L
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT_MASK 0xFF000000L
++//DC_I2C_EDID_DETECT_CTRL
++#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT 0x0
++#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT 0x14
++#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT 0x1c
++#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK 0x0000FFFFL
++#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK 0x00F00000L
++#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK 0x10000000L
++//DC_I2C_READ_REQUEST_INTERRUPT
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED__SHIFT 0x0
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT__SHIFT 0x1
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK__SHIFT 0x2
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK__SHIFT 0x3
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED__SHIFT 0x4
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT__SHIFT 0x5
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK__SHIFT 0x6
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK__SHIFT 0x7
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED__SHIFT 0x8
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT__SHIFT 0x9
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK__SHIFT 0xa
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK__SHIFT 0xb
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED__SHIFT 0xc
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT__SHIFT 0xd
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK__SHIFT 0xe
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK__SHIFT 0xf
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED__SHIFT 0x10
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT__SHIFT 0x11
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK__SHIFT 0x12
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK__SHIFT 0x13
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED__SHIFT 0x14
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT__SHIFT 0x15
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK__SHIFT 0x16
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK__SHIFT 0x17
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED__SHIFT 0x18
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT__SHIFT 0x19
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK__SHIFT 0x1a
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK__SHIFT 0x1b
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE__SHIFT 0x1e
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT 0x1f
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED_MASK 0x00000001L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT_MASK 0x00000002L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK_MASK 0x00000004L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK_MASK 0x00000008L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED_MASK 0x00000010L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT_MASK 0x00000020L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK_MASK 0x00000040L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK_MASK 0x00000080L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED_MASK 0x00000100L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT_MASK 0x00000200L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK_MASK 0x00000400L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK_MASK 0x00000800L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED_MASK 0x00001000L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT_MASK 0x00002000L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK_MASK 0x00004000L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK_MASK 0x00008000L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED_MASK 0x00010000L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT_MASK 0x00020000L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK_MASK 0x00040000L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK_MASK 0x00080000L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED_MASK 0x00100000L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT_MASK 0x00200000L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK_MASK 0x00400000L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK_MASK 0x00800000L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED_MASK 0x01000000L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT_MASK 0x02000000L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK_MASK 0x04000000L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK_MASK 0x08000000L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE_MASK 0x40000000L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK 0x80000000L
++//GENERIC_I2C_CONTROL
++#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO__SHIFT 0x0
++#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET__SHIFT 0x1
++#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET__SHIFT 0x2
++#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE__SHIFT 0x3
++#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO_MASK 0x00000001L
++#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET_MASK 0x00000002L
++#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET_MASK 0x00000004L
++#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE_MASK 0x00000008L
++//GENERIC_I2C_INTERRUPT_CONTROL
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT__SHIFT 0x0
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK__SHIFT 0x1
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK__SHIFT 0x2
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT_MASK 0x00000001L
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK_MASK 0x00000002L
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK_MASK 0x00000004L
++//GENERIC_I2C_STATUS
++#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS__SHIFT 0x0
++#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE__SHIFT 0x4
++#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED__SHIFT 0x5
++#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT__SHIFT 0x6
++#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK__SHIFT 0x9
++#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK__SHIFT 0xa
++#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS_MASK 0x0000000FL
++#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE_MASK 0x00000010L
++#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED_MASK 0x00000020L
++#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT_MASK 0x00000040L
++#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK_MASK 0x00000200L
++#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK_MASK 0x00000400L
++//GENERIC_I2C_SPEED
++#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD__SHIFT 0x0
++#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
++#define GENERIC_I2C_SPEED__GENERIC_I2C_START_STOP_TIMING_CNTL__SHIFT 0x8
++#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE__SHIFT 0x10
++#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD_MASK 0x00000003L
++#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L
++#define GENERIC_I2C_SPEED__GENERIC_I2C_START_STOP_TIMING_CNTL_MASK 0x00000300L
++#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE_MASK 0xFFFF0000L
++//GENERIC_I2C_SETUP
++#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN__SHIFT 0x0
++#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL__SHIFT 0x1
++#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN__SHIFT 0x7
++#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY__SHIFT 0x8
++#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT__SHIFT 0x18
++#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN_MASK 0x00000001L
++#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL_MASK 0x00000002L
++#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN_MASK 0x00000080L
++#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY_MASK 0x0000FF00L
++#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT_MASK 0xFF000000L
++//GENERIC_I2C_TRANSACTION
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW__SHIFT 0x0
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK__SHIFT 0x8
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ__SHIFT 0x9
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START__SHIFT 0xc
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP__SHIFT 0xd
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT__SHIFT 0x10
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW_MASK 0x00000001L
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK_MASK 0x00000100L
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ_MASK 0x00000200L
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START_MASK 0x00001000L
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_MASK 0x00002000L
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT_MASK 0x000F0000L
++//GENERIC_I2C_DATA
++#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW__SHIFT 0x0
++#define GENERIC_I2C_DATA__GENERIC_I2C_DATA__SHIFT 0x8
++#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX__SHIFT 0x10
++#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE__SHIFT 0x1f
++#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW_MASK 0x00000001L
++#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_MASK 0x0000FF00L
++#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_MASK 0x000F0000L
++#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE_MASK 0x80000000L
++//GENERIC_I2C_PIN_SELECTION
++#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL__SHIFT 0x0
++#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL__SHIFT 0x8
++#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL_MASK 0x0000007FL
++#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL_MASK 0x00007F00L
++//DCO_SCRATCH0
++#define DCO_SCRATCH0__DCO_SCRATCH0__SHIFT 0x0
++#define DCO_SCRATCH0__DCO_SCRATCH0_MASK 0xFFFFFFFFL
++//DCO_SCRATCH1
++#define DCO_SCRATCH1__DCO_SCRATCH1__SHIFT 0x0
++#define DCO_SCRATCH1__DCO_SCRATCH1_MASK 0xFFFFFFFFL
++//DCO_SCRATCH2
++#define DCO_SCRATCH2__DCO_SCRATCH2__SHIFT 0x0
++#define DCO_SCRATCH2__DCO_SCRATCH2_MASK 0xFFFFFFFFL
++//DCO_SCRATCH3
++#define DCO_SCRATCH3__DCO_SCRATCH3__SHIFT 0x0
++#define DCO_SCRATCH3__DCO_SCRATCH3_MASK 0xFFFFFFFFL
++//DCO_SCRATCH4
++#define DCO_SCRATCH4__DCO_SCRATCH4__SHIFT 0x0
++#define DCO_SCRATCH4__DCO_SCRATCH4_MASK 0xFFFFFFFFL
++//DCO_SCRATCH5
++#define DCO_SCRATCH5__DCO_SCRATCH5__SHIFT 0x0
++#define DCO_SCRATCH5__DCO_SCRATCH5_MASK 0xFFFFFFFFL
++//DCO_SCRATCH6
++#define DCO_SCRATCH6__DCO_SCRATCH6__SHIFT 0x0
++#define DCO_SCRATCH6__DCO_SCRATCH6_MASK 0xFFFFFFFFL
++//DCO_SCRATCH7
++#define DCO_SCRATCH7__DCO_SCRATCH7__SHIFT 0x0
++#define DCO_SCRATCH7__DCO_SCRATCH7_MASK 0xFFFFFFFFL
++//DCE_VCE_CONTROL
++#define DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT__SHIFT 0x0
++#define DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT__SHIFT 0x4
++#define DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT_MASK 0x00000007L
++#define DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT_MASK 0x00000070L
++//DISP_INTERRUPT_STATUS
++#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT__SHIFT 0x0
++#define DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
++#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT__SHIFT 0x2
++#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT__SHIFT 0x3
++#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
++#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT__SHIFT 0x7
++#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT__SHIFT 0x8
++#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT__SHIFT 0x9
++#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT 0x18
++#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT 0x1c
++#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT 0x1d
++#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT 0x1e
++#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT 0x1f
++#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT_MASK 0x00000001L
++#define DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L
++#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK 0x00000004L
++#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK 0x00000008L
++#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT_MASK 0x00000010L
++#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L
++#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L
++#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT_MASK 0x00000080L
++#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT_MASK 0x00000100L
++#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT_MASK 0x00000200L
++#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L
++#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L
++#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L
++#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x00020000L
++#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK 0x00040000L
++#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK 0x00080000L
++#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK 0x00100000L
++#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT_MASK 0x00400000L
++#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT_MASK 0x00800000L
++#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK 0x01000000L
++#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT_MASK 0x02000000L
++#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK 0x04000000L
++#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK 0x10000000L
++#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK 0x20000000L
++#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK 0x40000000L
++#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK 0x80000000L
++//DISP_INTERRUPT_STATUS_CONTINUE
++#define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT__SHIFT 0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT__SHIFT 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT__SHIFT 0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT__SHIFT 0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT__SHIFT 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT__SHIFT 0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D1_VLINE2_INTERRUPT__SHIFT 0x15
++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE2_INTERRUPT__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D3_VLINE2_INTERRUPT__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT0__SHIFT 0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT1__SHIFT 0x1d
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT2__SHIFT 0x1e
++#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT 0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT_MASK 0x00000001L
++#define DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L
++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK 0x00000004L
++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK 0x00000008L
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT_MASK 0x00000010L
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT_MASK 0x00000080L
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT_MASK 0x00000100L
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT_MASK 0x00000200L
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L
++#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L
++#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L
++#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x00020000L
++#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK 0x00040000L
++#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK 0x00080000L
++#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK 0x00100000L
++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D1_VLINE2_INTERRUPT_MASK 0x00200000L
++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE2_INTERRUPT_MASK 0x00400000L
++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D3_VLINE2_INTERRUPT_MASK 0x00800000L
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x02000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_INTERRUPT_MASK 0x04000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x08000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT0_MASK 0x10000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT1_MASK 0x20000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT2_MASK 0x40000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK 0x80000000L
++//DISP_INTERRUPT_STATUS_CONTINUE2
++#define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT__SHIFT 0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT__SHIFT 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT__SHIFT 0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT__SHIFT 0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT__SHIFT 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT__SHIFT 0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D4_VLINE2_INTERRUPT__SHIFT 0x15
++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D5_VLINE2_INTERRUPT__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D6_VLINE2_INTERRUPT__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT0__SHIFT 0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT1__SHIFT 0x1d
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT2__SHIFT 0x1e
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT 0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT_MASK 0x00000001L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK 0x00000004L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK 0x00000008L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT_MASK 0x00000010L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT_MASK 0x00000080L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT_MASK 0x00000100L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT_MASK 0x00000200L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x00020000L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK 0x00040000L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK 0x00080000L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK 0x00100000L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D4_VLINE2_INTERRUPT_MASK 0x00200000L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D5_VLINE2_INTERRUPT_MASK 0x00400000L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D6_VLINE2_INTERRUPT_MASK 0x00800000L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x02000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_INTERRUPT_MASK 0x04000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x08000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT0_MASK 0x10000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT1_MASK 0x20000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT2_MASK 0x40000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK 0x80000000L
++//DISP_INTERRUPT_STATUS_CONTINUE3
++#define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT__SHIFT 0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT__SHIFT 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT__SHIFT 0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT__SHIFT 0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT__SHIFT 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT__SHIFT 0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE3__BUFMGR_IHIF_INTERRUPT__SHIFT 0x15
++#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_HOST_CONFLICT_INTERRUPT__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_DATA_OVERFLOW_INTERRUPT__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT0__SHIFT 0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT1__SHIFT 0x1d
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT2__SHIFT 0x1e
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT 0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT_MASK 0x00000001L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK 0x00000004L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK 0x00000008L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT_MASK 0x00000010L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT_MASK 0x00000080L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT_MASK 0x00000100L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT_MASK 0x00000200L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x00020000L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK 0x00040000L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK 0x00080000L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK 0x00100000L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__BUFMGR_IHIF_INTERRUPT_MASK 0x00200000L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_HOST_CONFLICT_INTERRUPT_MASK 0x00400000L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_DATA_OVERFLOW_INTERRUPT_MASK 0x00800000L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x02000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_INTERRUPT_MASK 0x04000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x08000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT0_MASK 0x10000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT1_MASK 0x20000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT2_MASK 0x40000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK 0x80000000L
++//DISP_INTERRUPT_STATUS_CONTINUE4
++#define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT__SHIFT 0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT__SHIFT 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT__SHIFT 0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT__SHIFT 0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT__SHIFT 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT__SHIFT 0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT0__SHIFT 0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT1__SHIFT 0x1d
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT2__SHIFT 0x1e
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT 0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT_MASK 0x00000001L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK 0x00000004L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK 0x00000008L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT_MASK 0x00000010L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT_MASK 0x00000080L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT_MASK 0x00000100L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT_MASK 0x00000200L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x00020000L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK 0x00040000L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK 0x00080000L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK 0x00100000L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x00400000L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_INTERRUPT_MASK 0x00800000L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x01000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x02000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_INTERRUPT_MASK 0x04000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x08000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT0_MASK 0x10000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT1_MASK 0x20000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT2_MASK 0x40000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK 0x80000000L
++//DISP_INTERRUPT_STATUS_CONTINUE5
++#define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT__SHIFT 0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT__SHIFT 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT__SHIFT 0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT__SHIFT 0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT__SHIFT 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT__SHIFT 0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT0__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT1__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT2__SHIFT 0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT0__SHIFT 0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT1__SHIFT 0x1d
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT2__SHIFT 0x1e
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT 0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT_MASK 0x00000001L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK 0x00000004L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK 0x00000008L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT_MASK 0x00000010L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT_MASK 0x00000080L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT_MASK 0x00000100L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT_MASK 0x00000200L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x00020000L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK 0x00040000L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK 0x00080000L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK 0x00100000L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x00400000L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_INTERRUPT_MASK 0x00800000L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x01000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT0_MASK 0x02000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT1_MASK 0x04000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT2_MASK 0x08000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT0_MASK 0x10000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT1_MASK 0x20000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT2_MASK 0x40000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK 0x80000000L
++//DISP_INTERRUPT_STATUS_CONTINUE6
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB0_IHIF_INTERRUPT__SHIFT 0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB1_IHIF_INTERRUPT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x15
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x18
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT 0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER2_INTERRUPT_MASK 0x00000004L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER3_INTERRUPT_MASK 0x00000008L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER4_INTERRUPT_MASK 0x00000010L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER5_INTERRUPT_MASK 0x00000020L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER6_INTERRUPT_MASK 0x00000040L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER7_INTERRUPT_MASK 0x00000080L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x00000100L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB0_IHIF_INTERRUPT_MASK 0x00000200L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB1_IHIF_INTERRUPT_MASK 0x00000400L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00020000L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT_MASK 0x00040000L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00080000L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT_MASK 0x00100000L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00200000L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT_MASK 0x00400000L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00800000L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT_MASK 0x01000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x02000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT_MASK 0x04000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x08000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT_MASK 0x10000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK 0x80000000L
++//DISP_INTERRUPT_STATUS_CONTINUE7
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x1d
++#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x1e
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT 0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT_MASK 0x00000004L
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER3_INTERRUPT_MASK 0x00000008L
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER4_INTERRUPT_MASK 0x00000010L
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER5_INTERRUPT_MASK 0x00000020L
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER6_INTERRUPT_MASK 0x00000040L
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER7_INTERRUPT_MASK 0x00000080L
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x00000100L
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER2_INTERRUPT_MASK 0x00000800L
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER3_INTERRUPT_MASK 0x00001000L
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER4_INTERRUPT_MASK 0x00002000L
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER5_INTERRUPT_MASK 0x00004000L
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER6_INTERRUPT_MASK 0x00008000L
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER7_INTERRUPT_MASK 0x00010000L
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x00020000L
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER2_INTERRUPT_MASK 0x00100000L
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER3_INTERRUPT_MASK 0x00200000L
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER4_INTERRUPT_MASK 0x00400000L
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER5_INTERRUPT_MASK 0x00800000L
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER6_INTERRUPT_MASK 0x01000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER7_INTERRUPT_MASK 0x02000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x04000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER0_INTERRUPT_MASK 0x08000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER1_INTERRUPT_MASK 0x10000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER2_INTERRUPT_MASK 0x20000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER3_INTERRUPT_MASK 0x40000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK 0x80000000L
++//DISP_INTERRUPT_STATUS_CONTINUE8
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x1d
++#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x1e
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT 0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT_MASK 0x00000004L
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER3_INTERRUPT_MASK 0x00000008L
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER4_INTERRUPT_MASK 0x00000010L
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER5_INTERRUPT_MASK 0x00000020L
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER6_INTERRUPT_MASK 0x00000040L
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER7_INTERRUPT_MASK 0x00000080L
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x00000100L
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER2_INTERRUPT_MASK 0x00000800L
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER3_INTERRUPT_MASK 0x00001000L
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER4_INTERRUPT_MASK 0x00002000L
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER5_INTERRUPT_MASK 0x00004000L
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER6_INTERRUPT_MASK 0x00008000L
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER7_INTERRUPT_MASK 0x00010000L
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x00020000L
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER2_INTERRUPT_MASK 0x00100000L
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER3_INTERRUPT_MASK 0x00200000L
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER4_INTERRUPT_MASK 0x00400000L
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER5_INTERRUPT_MASK 0x00800000L
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER6_INTERRUPT_MASK 0x01000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER7_INTERRUPT_MASK 0x02000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x04000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER4_INTERRUPT_MASK 0x08000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER5_INTERRUPT_MASK 0x10000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER6_INTERRUPT_MASK 0x20000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER7_INTERRUPT_MASK 0x40000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK 0x80000000L
++//DISP_INTERRUPT_STATUS_CONTINUE9
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE9__WB_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10__SHIFT 0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT_MASK 0x00000004L
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER3_INTERRUPT_MASK 0x00000008L
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER4_INTERRUPT_MASK 0x00000010L
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER5_INTERRUPT_MASK 0x00000020L
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER6_INTERRUPT_MASK 0x00000040L
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER7_INTERRUPT_MASK 0x00000080L
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x00000100L
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER2_INTERRUPT_MASK 0x00000800L
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER3_INTERRUPT_MASK 0x00001000L
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER4_INTERRUPT_MASK 0x00002000L
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER5_INTERRUPT_MASK 0x00004000L
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER6_INTERRUPT_MASK 0x00008000L
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER7_INTERRUPT_MASK 0x00010000L
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x00020000L
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER2_INTERRUPT_MASK 0x00100000L
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER3_INTERRUPT_MASK 0x00200000L
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER4_INTERRUPT_MASK 0x00400000L
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER5_INTERRUPT_MASK 0x00800000L
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER6_INTERRUPT_MASK 0x01000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER7_INTERRUPT_MASK 0x02000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x04000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE9__WB_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x08000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10_MASK 0x80000000L
++//DCO_MEM_PWR_STATUS
++#define DCO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE__SHIFT 0x0
++#define DCO_MEM_PWR_STATUS__MVP_MEM_PWR_STATE__SHIFT 0x2
++#define DCO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE__SHIFT 0x3
++#define DCO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE__SHIFT 0x4
++#define DCO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE__SHIFT 0x5
++#define DCO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE__SHIFT 0x6
++#define DCO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE__SHIFT 0x7
++#define DCO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE__SHIFT 0x8
++#define DCO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE__SHIFT 0x9
++#define DCO_MEM_PWR_STATUS__HDMI0_MEM_PWR_STATE__SHIFT 0xa
++#define DCO_MEM_PWR_STATUS__HDMI1_MEM_PWR_STATE__SHIFT 0xc
++#define DCO_MEM_PWR_STATUS__HDMI2_MEM_PWR_STATE__SHIFT 0xe
++#define DCO_MEM_PWR_STATUS__HDMI3_MEM_PWR_STATE__SHIFT 0x10
++#define DCO_MEM_PWR_STATUS__HDMI4_MEM_PWR_STATE__SHIFT 0x12
++#define DCO_MEM_PWR_STATUS__HDMI5_MEM_PWR_STATE__SHIFT 0x14
++#define DCO_MEM_PWR_STATUS__HDMI6_MEM_PWR_STATE__SHIFT 0x16
++#define DCO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE_MASK 0x00000001L
++#define DCO_MEM_PWR_STATUS__MVP_MEM_PWR_STATE_MASK 0x00000004L
++#define DCO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE_MASK 0x00000008L
++#define DCO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE_MASK 0x00000010L
++#define DCO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE_MASK 0x00000020L
++#define DCO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE_MASK 0x00000040L
++#define DCO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE_MASK 0x00000080L
++#define DCO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE_MASK 0x00000100L
++#define DCO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE_MASK 0x00000200L
++#define DCO_MEM_PWR_STATUS__HDMI0_MEM_PWR_STATE_MASK 0x00000C00L
++#define DCO_MEM_PWR_STATUS__HDMI1_MEM_PWR_STATE_MASK 0x00003000L
++#define DCO_MEM_PWR_STATUS__HDMI2_MEM_PWR_STATE_MASK 0x0000C000L
++#define DCO_MEM_PWR_STATUS__HDMI3_MEM_PWR_STATE_MASK 0x00030000L
++#define DCO_MEM_PWR_STATUS__HDMI4_MEM_PWR_STATE_MASK 0x000C0000L
++#define DCO_MEM_PWR_STATUS__HDMI5_MEM_PWR_STATE_MASK 0x00300000L
++#define DCO_MEM_PWR_STATUS__HDMI6_MEM_PWR_STATE_MASK 0x00C00000L
++//DCO_MEM_PWR_CTRL
++#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE__SHIFT 0x0
++#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS__SHIFT 0x1
++#define DCO_MEM_PWR_CTRL__MVP_LIGHT_SLEEP_DIS__SHIFT 0x3
++#define DCO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS__SHIFT 0x4
++#define DCO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS__SHIFT 0x5
++#define DCO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS__SHIFT 0x6
++#define DCO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS__SHIFT 0x7
++#define DCO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS__SHIFT 0x8
++#define DCO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS__SHIFT 0x9
++#define DCO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS__SHIFT 0xa
++#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_FORCE__SHIFT 0xb
++#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_DIS__SHIFT 0xd
++#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_FORCE__SHIFT 0xe
++#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_DIS__SHIFT 0x10
++#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_FORCE__SHIFT 0x11
++#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_DIS__SHIFT 0x13
++#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_FORCE__SHIFT 0x14
++#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_DIS__SHIFT 0x16
++#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_FORCE__SHIFT 0x17
++#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_DIS__SHIFT 0x19
++#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE__SHIFT 0x1a
++#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_DIS__SHIFT 0x1c
++#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE__SHIFT 0x1d
++#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_DIS__SHIFT 0x1f
++#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE_MASK 0x00000001L
++#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS_MASK 0x00000002L
++#define DCO_MEM_PWR_CTRL__MVP_LIGHT_SLEEP_DIS_MASK 0x00000008L
++#define DCO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS_MASK 0x00000010L
++#define DCO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS_MASK 0x00000020L
++#define DCO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS_MASK 0x00000040L
++#define DCO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS_MASK 0x00000080L
++#define DCO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS_MASK 0x00000100L
++#define DCO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS_MASK 0x00000200L
++#define DCO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS_MASK 0x00000400L
++#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_FORCE_MASK 0x00001800L
++#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_DIS_MASK 0x00002000L
++#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_FORCE_MASK 0x0000C000L
++#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_DIS_MASK 0x00010000L
++#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_FORCE_MASK 0x00060000L
++#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_DIS_MASK 0x00080000L
++#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_FORCE_MASK 0x00300000L
++#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_DIS_MASK 0x00400000L
++#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_FORCE_MASK 0x01800000L
++#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_DIS_MASK 0x02000000L
++#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE_MASK 0x0C000000L
++#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_DIS_MASK 0x10000000L
++#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE_MASK 0x60000000L
++#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_DIS_MASK 0x80000000L
++//DCO_MEM_PWR_CTRL2
++#define DCO_MEM_PWR_CTRL2__HDMI_MEM_PWR_MODE_SEL__SHIFT 0x0
++#define DCO_MEM_PWR_CTRL2__DPLPA_LIGHT_SLEEP_DIS__SHIFT 0x2
++#define DCO_MEM_PWR_CTRL2__DPLPB_LIGHT_SLEEP_DIS__SHIFT 0x3
++#define DCO_MEM_PWR_CTRL2__HDMILP0_MEM_PWR_FORCE__SHIFT 0x10
++#define DCO_MEM_PWR_CTRL2__HDMILP0_MEM_PWR_DIS__SHIFT 0x12
++#define DCO_MEM_PWR_CTRL2__HDMILP1_MEM_PWR_FORCE__SHIFT 0x13
++#define DCO_MEM_PWR_CTRL2__HDMILP1_MEM_PWR_DIS__SHIFT 0x15
++#define DCO_MEM_PWR_CTRL2__HDMI_MEM_PWR_MODE_SEL_MASK 0x00000003L
++#define DCO_MEM_PWR_CTRL2__DPLPA_LIGHT_SLEEP_DIS_MASK 0x00000004L
++#define DCO_MEM_PWR_CTRL2__DPLPB_LIGHT_SLEEP_DIS_MASK 0x00000008L
++#define DCO_MEM_PWR_CTRL2__HDMILP0_MEM_PWR_FORCE_MASK 0x00030000L
++#define DCO_MEM_PWR_CTRL2__HDMILP0_MEM_PWR_DIS_MASK 0x00040000L
++#define DCO_MEM_PWR_CTRL2__HDMILP1_MEM_PWR_FORCE_MASK 0x00180000L
++#define DCO_MEM_PWR_CTRL2__HDMILP1_MEM_PWR_DIS_MASK 0x00200000L
++//DCO_CLK_CNTL
++#define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS__SHIFT 0x5
++#define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS__SHIFT 0x6
++#define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS__SHIFT 0x7
++#define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS__SHIFT 0x8
++#define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS__SHIFT 0x9
++#define DCO_CLK_CNTL__REFCLK_R_DCO_GATE_DIS__SHIFT 0xa
++#define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS__SHIFT 0x10
++#define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS__SHIFT 0x11
++#define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS__SHIFT 0x12
++#define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS__SHIFT 0x13
++#define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS__SHIFT 0x14
++#define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS__SHIFT 0x15
++#define DCO_CLK_CNTL__DISPCLK_G_DIGLPA_GATE_DIS__SHIFT 0x16
++#define DCO_CLK_CNTL__DISPCLK_G_DIGLPB_GATE_DIS__SHIFT 0x17
++#define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT 0x18
++#define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT 0x19
++#define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT 0x1a
++#define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT 0x1b
++#define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT 0x1c
++#define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT 0x1d
++#define DCO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS__SHIFT 0x1e
++#define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS_MASK 0x00000020L
++#define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS_MASK 0x00000040L
++#define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS_MASK 0x00000080L
++#define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS_MASK 0x00000100L
++#define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS_MASK 0x00000200L
++#define DCO_CLK_CNTL__REFCLK_R_DCO_GATE_DIS_MASK 0x00000400L
++#define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS_MASK 0x00010000L
++#define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS_MASK 0x00020000L
++#define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS_MASK 0x00040000L
++#define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS_MASK 0x00080000L
++#define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS_MASK 0x00100000L
++#define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS_MASK 0x00200000L
++#define DCO_CLK_CNTL__DISPCLK_G_DIGLPA_GATE_DIS_MASK 0x00400000L
++#define DCO_CLK_CNTL__DISPCLK_G_DIGLPB_GATE_DIS_MASK 0x00800000L
++#define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK 0x01000000L
++#define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK 0x02000000L
++#define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK 0x04000000L
++#define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK 0x08000000L
++#define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK 0x10000000L
++#define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK 0x20000000L
++#define DCO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS_MASK 0x40000000L
++//DCO_POWER_MANAGEMENT_CNTL
++#define DCO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT 0x0
++#define DCO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT 0x8
++#define DCO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK 0x00000001L
++#define DCO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK 0x00000100L
++//DIG_SOFT_RESET_2
++#define DIG_SOFT_RESET_2__DIGLPA_FE_SOFT_RESET__SHIFT 0x0
++#define DIG_SOFT_RESET_2__DIGLPA_BE_SOFT_RESET__SHIFT 0x1
++#define DIG_SOFT_RESET_2__DIGLPB_FE_SOFT_RESET__SHIFT 0x4
++#define DIG_SOFT_RESET_2__DIGLPB_BE_SOFT_RESET__SHIFT 0x5
++#define DIG_SOFT_RESET_2__DIGLPA_FE_SOFT_RESET_MASK 0x00000001L
++#define DIG_SOFT_RESET_2__DIGLPA_BE_SOFT_RESET_MASK 0x00000002L
++#define DIG_SOFT_RESET_2__DIGLPB_FE_SOFT_RESET_MASK 0x00000010L
++#define DIG_SOFT_RESET_2__DIGLPB_BE_SOFT_RESET_MASK 0x00000020L
++//DCO_STEREOSYNC_SEL
++#define DCO_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL__SHIFT 0x0
++#define DCO_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL__SHIFT 0x10
++#define DCO_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL_MASK 0x00000007L
++#define DCO_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL_MASK 0x00070000L
++//DCO_SOFT_RESET
++#define DCO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x0
++#define DCO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET__SHIFT 0x4
++#define DCO_SOFT_RESET__I2S1_SOFT_RESET__SHIFT 0x5
++#define DCO_SOFT_RESET__SPDIF1_SOFT_RESET__SHIFT 0x6
++#define DCO_SOFT_RESET__DB_CLK_SOFT_RESET__SHIFT 0xc
++#define DCO_SOFT_RESET__FMT0_SOFT_RESET__SHIFT 0x10
++#define DCO_SOFT_RESET__FMT1_SOFT_RESET__SHIFT 0x11
++#define DCO_SOFT_RESET__FMT2_SOFT_RESET__SHIFT 0x12
++#define DCO_SOFT_RESET__FMT3_SOFT_RESET__SHIFT 0x13
++#define DCO_SOFT_RESET__FMT4_SOFT_RESET__SHIFT 0x14
++#define DCO_SOFT_RESET__FMT5_SOFT_RESET__SHIFT 0x15
++#define DCO_SOFT_RESET__MVP_SOFT_RESET__SHIFT 0x18
++#define DCO_SOFT_RESET__ABM_SOFT_RESET__SHIFT 0x19
++#define DCO_SOFT_RESET__DVO_SOFT_RESET__SHIFT 0x1b
++#define DCO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x00000001L
++#define DCO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET_MASK 0x00000010L
++#define DCO_SOFT_RESET__I2S1_SOFT_RESET_MASK 0x00000020L
++#define DCO_SOFT_RESET__SPDIF1_SOFT_RESET_MASK 0x00000040L
++#define DCO_SOFT_RESET__DB_CLK_SOFT_RESET_MASK 0x00001000L
++#define DCO_SOFT_RESET__FMT0_SOFT_RESET_MASK 0x00010000L
++#define DCO_SOFT_RESET__FMT1_SOFT_RESET_MASK 0x00020000L
++#define DCO_SOFT_RESET__FMT2_SOFT_RESET_MASK 0x00040000L
++#define DCO_SOFT_RESET__FMT3_SOFT_RESET_MASK 0x00080000L
++#define DCO_SOFT_RESET__FMT4_SOFT_RESET_MASK 0x00100000L
++#define DCO_SOFT_RESET__FMT5_SOFT_RESET_MASK 0x00200000L
++#define DCO_SOFT_RESET__MVP_SOFT_RESET_MASK 0x01000000L
++#define DCO_SOFT_RESET__ABM_SOFT_RESET_MASK 0x02000000L
++#define DCO_SOFT_RESET__DVO_SOFT_RESET_MASK 0x08000000L
++//DIG_SOFT_RESET
++#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT 0x0
++#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT 0x1
++#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT 0x4
++#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT 0x5
++#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT 0x8
++#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT 0x9
++#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT 0xc
++#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT 0xd
++#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT 0x10
++#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT 0x11
++#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT 0x14
++#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT 0x15
++#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET__SHIFT 0x18
++#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET__SHIFT 0x19
++#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK 0x00000001L
++#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK 0x00000002L
++#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK 0x00000010L
++#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK 0x00000020L
++#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK 0x00000100L
++#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK 0x00000200L
++#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK 0x00001000L
++#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK 0x00002000L
++#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK 0x00010000L
++#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK 0x00020000L
++#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK 0x00100000L
++#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK 0x00200000L
++#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET_MASK 0x01000000L
++#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET_MASK 0x02000000L
++//DCO_MEM_PWR_STATUS1
++#define DCO_MEM_PWR_STATUS1__DPLPA_MEM_PWR_STATE__SHIFT 0x0
++#define DCO_MEM_PWR_STATUS1__DPLPB_MEM_PWR_STATE__SHIFT 0x1
++#define DCO_MEM_PWR_STATUS1__HDMILP0_MEM_PWR_STATE__SHIFT 0xa
++#define DCO_MEM_PWR_STATUS1__HDMILP1_MEM_PWR_STATE__SHIFT 0xc
++#define DCO_MEM_PWR_STATUS1__DPLPA_MEM_PWR_STATE_MASK 0x00000001L
++#define DCO_MEM_PWR_STATUS1__DPLPB_MEM_PWR_STATE_MASK 0x00000002L
++#define DCO_MEM_PWR_STATUS1__HDMILP0_MEM_PWR_STATE_MASK 0x00000C00L
++#define DCO_MEM_PWR_STATUS1__HDMILP1_MEM_PWR_STATE_MASK 0x00003000L
++//DISP_INTERRUPT_STATUS_CONTINUE10
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0xb
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT__SHIFT 0xc
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT__SHIFT 0xd
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER2_INTERRUPT__SHIFT 0xe
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER3_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER4_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER5_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER6_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER7_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER_OFF_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE10__CRTC1_RANGE_TIMING_UPDATE__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE10__CRTC2_RANGE_TIMING_UPDATE__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE10__CRTC3_RANGE_TIMING_UPDATE__SHIFT 0x18
++#define DISP_INTERRUPT_STATUS_CONTINUE10__CRTC4_RANGE_TIMING_UPDATE__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE10__CRTC5_RANGE_TIMING_UPDATE__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE10__CRTC6_RANGE_TIMING_UPDATE__SHIFT 0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11__SHIFT 0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00000010L
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00000020L
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00000400L
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00000800L
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT_MASK 0x00001000L
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT_MASK 0x00002000L
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER2_INTERRUPT_MASK 0x00004000L
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER3_INTERRUPT_MASK 0x00008000L
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER4_INTERRUPT_MASK 0x00010000L
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER5_INTERRUPT_MASK 0x00020000L
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER6_INTERRUPT_MASK 0x00040000L
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER7_INTERRUPT_MASK 0x00080000L
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER_OFF_INTERRUPT_MASK 0x00100000L
++#define DISP_INTERRUPT_STATUS_CONTINUE10__CRTC1_RANGE_TIMING_UPDATE_MASK 0x00400000L
++#define DISP_INTERRUPT_STATUS_CONTINUE10__CRTC2_RANGE_TIMING_UPDATE_MASK 0x00800000L
++#define DISP_INTERRUPT_STATUS_CONTINUE10__CRTC3_RANGE_TIMING_UPDATE_MASK 0x01000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE10__CRTC4_RANGE_TIMING_UPDATE_MASK 0x02000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE10__CRTC5_RANGE_TIMING_UPDATE_MASK 0x04000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE10__CRTC6_RANGE_TIMING_UPDATE_MASK 0x08000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11_MASK 0x80000000L
++//DCO_CLK_CNTL2
++#define DCO_CLK_CNTL2__DCO_TEST_CLK_SEL__SHIFT 0x0
++#define DCO_CLK_CNTL2__SCLK_G_AFMTA_GATE_DIS__SHIFT 0x7
++#define DCO_CLK_CNTL2__SCLK_G_AFMTB_GATE_DIS__SHIFT 0x8
++#define DCO_CLK_CNTL2__SCLK_G_AFMTC_GATE_DIS__SHIFT 0x9
++#define DCO_CLK_CNTL2__SCLK_G_AFMTD_GATE_DIS__SHIFT 0xa
++#define DCO_CLK_CNTL2__SCLK_G_AFMTE_GATE_DIS__SHIFT 0xb
++#define DCO_CLK_CNTL2__SCLK_G_AFMTF_GATE_DIS__SHIFT 0xc
++#define DCO_CLK_CNTL2__SCLK_G_AFMTG_GATE_DIS__SHIFT 0xd
++#define DCO_CLK_CNTL2__SCLK_G_AFMTLPA_GATE_DIS__SHIFT 0xf
++#define DCO_CLK_CNTL2__SCLK_G_AFMTLPB_GATE_DIS__SHIFT 0x10
++#define DCO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS__SHIFT 0x11
++#define DCO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS__SHIFT 0x12
++#define DCO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS__SHIFT 0x13
++#define DCO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS__SHIFT 0x14
++#define DCO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS__SHIFT 0x15
++#define DCO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS__SHIFT 0x16
++#define DCO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS__SHIFT 0x17
++#define DCO_CLK_CNTL2__SYMCLKLPA_FE_G_AFMT_GATE_DIS__SHIFT 0x19
++#define DCO_CLK_CNTL2__SYMCLKLPB_FE_G_AFMT_GATE_DIS__SHIFT 0x1a
++#define DCO_CLK_CNTL2__DCO_TEST_CLK_SEL_MASK 0x0000007FL
++#define DCO_CLK_CNTL2__SCLK_G_AFMTA_GATE_DIS_MASK 0x00000080L
++#define DCO_CLK_CNTL2__SCLK_G_AFMTB_GATE_DIS_MASK 0x00000100L
++#define DCO_CLK_CNTL2__SCLK_G_AFMTC_GATE_DIS_MASK 0x00000200L
++#define DCO_CLK_CNTL2__SCLK_G_AFMTD_GATE_DIS_MASK 0x00000400L
++#define DCO_CLK_CNTL2__SCLK_G_AFMTE_GATE_DIS_MASK 0x00000800L
++#define DCO_CLK_CNTL2__SCLK_G_AFMTF_GATE_DIS_MASK 0x00001000L
++#define DCO_CLK_CNTL2__SCLK_G_AFMTG_GATE_DIS_MASK 0x00002000L
++#define DCO_CLK_CNTL2__SCLK_G_AFMTLPA_GATE_DIS_MASK 0x00008000L
++#define DCO_CLK_CNTL2__SCLK_G_AFMTLPB_GATE_DIS_MASK 0x00010000L
++#define DCO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS_MASK 0x00020000L
++#define DCO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS_MASK 0x00040000L
++#define DCO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS_MASK 0x00080000L
++#define DCO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS_MASK 0x00100000L
++#define DCO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS_MASK 0x00200000L
++#define DCO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS_MASK 0x00400000L
++#define DCO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS_MASK 0x00800000L
++#define DCO_CLK_CNTL2__SYMCLKLPA_FE_G_AFMT_GATE_DIS_MASK 0x02000000L
++#define DCO_CLK_CNTL2__SYMCLKLPB_FE_G_AFMT_GATE_DIS_MASK 0x04000000L
++//DCO_CLK_CNTL3
++#define DCO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS__SHIFT 0x0
++#define DCO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS__SHIFT 0x1
++#define DCO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS__SHIFT 0x2
++#define DCO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS__SHIFT 0x3
++#define DCO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS__SHIFT 0x4
++#define DCO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS__SHIFT 0x5
++#define DCO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS__SHIFT 0x6
++#define DCO_CLK_CNTL3__SYMCLKLPA_FE_G_TMDS_GATE_DIS__SHIFT 0x8
++#define DCO_CLK_CNTL3__SYMCLKLPB_FE_G_TMDS_GATE_DIS__SHIFT 0x9
++#define DCO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS__SHIFT 0xa
++#define DCO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS__SHIFT 0xb
++#define DCO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS__SHIFT 0xc
++#define DCO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS__SHIFT 0xd
++#define DCO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS__SHIFT 0xe
++#define DCO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS__SHIFT 0xf
++#define DCO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS__SHIFT 0x10
++#define DCO_CLK_CNTL3__SYMCLKLPA_G_TMDS_GATE_DIS__SHIFT 0x12
++#define DCO_CLK_CNTL3__SYMCLKLPB_G_TMDS_GATE_DIS__SHIFT 0x13
++#define DCO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS_MASK 0x00000001L
++#define DCO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS_MASK 0x00000002L
++#define DCO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS_MASK 0x00000004L
++#define DCO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS_MASK 0x00000008L
++#define DCO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS_MASK 0x00000010L
++#define DCO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS_MASK 0x00000020L
++#define DCO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS_MASK 0x00000040L
++#define DCO_CLK_CNTL3__SYMCLKLPA_FE_G_TMDS_GATE_DIS_MASK 0x00000100L
++#define DCO_CLK_CNTL3__SYMCLKLPB_FE_G_TMDS_GATE_DIS_MASK 0x00000200L
++#define DCO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS_MASK 0x00000400L
++#define DCO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS_MASK 0x00000800L
++#define DCO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS_MASK 0x00001000L
++#define DCO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS_MASK 0x00002000L
++#define DCO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS_MASK 0x00004000L
++#define DCO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS_MASK 0x00008000L
++#define DCO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS_MASK 0x00010000L
++#define DCO_CLK_CNTL3__SYMCLKLPA_G_TMDS_GATE_DIS_MASK 0x00040000L
++#define DCO_CLK_CNTL3__SYMCLKLPB_G_TMDS_GATE_DIS_MASK 0x00080000L
++//DCO_HDMI_RXSTATUS_TIMER_CONTROL
++#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_ENABLE__SHIFT 0x0
++#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_TYPE__SHIFT 0x4
++#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_STATUS__SHIFT 0x8
++#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_MASK__SHIFT 0xc
++#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_INTERVAL__SHIFT 0x10
++#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_ENABLE_MASK 0x00000001L
++#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_TYPE_MASK 0x00000010L
++#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_STATUS_MASK 0x00000100L
++#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_MASK_MASK 0x00001000L
++#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_INTERVAL_MASK 0x0FFF0000L
++//DCO_PSP_INTERRUPT_STATUS
++#define DCO_PSP_INTERRUPT_STATUS__DCO_PSP_INTERRUPT_STATUS__SHIFT 0x0
++#define DCO_PSP_INTERRUPT_STATUS__DCO_PSP_INTERRUPT_MESSAGE__SHIFT 0x1
++#define DCO_PSP_INTERRUPT_STATUS__DCO_PSP_INTERRUPT_STATUS_MASK 0x00000001L
++#define DCO_PSP_INTERRUPT_STATUS__DCO_PSP_INTERRUPT_MESSAGE_MASK 0xFFFFFFFEL
++//DCO_PSP_INTERRUPT_CLEAR
++#define DCO_PSP_INTERRUPT_CLEAR__DCO_PSP_INTERRUPT_CLEAR__SHIFT 0x0
++#define DCO_PSP_INTERRUPT_CLEAR__DCO_PSP_INTERRUPT_CLEAR_MASK 0x00000001L
++//DCO_GENERIC_INTERRUPT_MESSAGE
++#define DCO_GENERIC_INTERRUPT_MESSAGE__DCO_GENERIC_INTERRUPT_STATUS__SHIFT 0x0
++#define DCO_GENERIC_INTERRUPT_MESSAGE__DCO_GENERIC_INTERRUPT_MESSAGE__SHIFT 0x1
++#define DCO_GENERIC_INTERRUPT_MESSAGE__DCO_GENERIC_INTERRUPT_STATUS_MASK 0x00000001L
++#define DCO_GENERIC_INTERRUPT_MESSAGE__DCO_GENERIC_INTERRUPT_MESSAGE_MASK 0xFFFFFFFEL
++//DCO_GENERIC_INTERRUPT_CLEAR
++#define DCO_GENERIC_INTERRUPT_CLEAR__DCO_GENERIC_INTERRUPT_CLEAR__SHIFT 0x0
++#define DCO_GENERIC_INTERRUPT_CLEAR__DCO_GENERIC_INTERRUPT_CLEAR_MASK 0x00000001L
++//FMT_MEMORY0_CONTROL
++#define FMT_MEMORY0_CONTROL__FMT420_MEM0_SOURCE_SEL__SHIFT 0x0
++#define FMT_MEMORY0_CONTROL__FMT420_MEM0_PWR_FORCE__SHIFT 0x4
++#define FMT_MEMORY0_CONTROL__FMT420_MEM0_PWR_DIS__SHIFT 0x8
++#define FMT_MEMORY0_CONTROL__FMT420_MEM0_PWR_STATE__SHIFT 0xc
++#define FMT_MEMORY0_CONTROL__FMT420_MEM0_SOURCE_SEL_MASK 0x00000007L
++#define FMT_MEMORY0_CONTROL__FMT420_MEM0_PWR_FORCE_MASK 0x00000030L
++#define FMT_MEMORY0_CONTROL__FMT420_MEM0_PWR_DIS_MASK 0x00000100L
++#define FMT_MEMORY0_CONTROL__FMT420_MEM0_PWR_STATE_MASK 0x00003000L
++//FMT_MEMORY1_CONTROL
++#define FMT_MEMORY1_CONTROL__FMT420_MEM1_SOURCE_SEL__SHIFT 0x0
++#define FMT_MEMORY1_CONTROL__FMT420_MEM1_PWR_FORCE__SHIFT 0x4
++#define FMT_MEMORY1_CONTROL__FMT420_MEM1_PWR_DIS__SHIFT 0x8
++#define FMT_MEMORY1_CONTROL__FMT420_MEM1_PWR_STATE__SHIFT 0xc
++#define FMT_MEMORY1_CONTROL__FMT420_MEM1_SOURCE_SEL_MASK 0x00000007L
++#define FMT_MEMORY1_CONTROL__FMT420_MEM1_PWR_FORCE_MASK 0x00000030L
++#define FMT_MEMORY1_CONTROL__FMT420_MEM1_PWR_DIS_MASK 0x00000100L
++#define FMT_MEMORY1_CONTROL__FMT420_MEM1_PWR_STATE_MASK 0x00003000L
++//FMT_MEMORY2_CONTROL
++#define FMT_MEMORY2_CONTROL__FMT420_MEM2_SOURCE_SEL__SHIFT 0x0
++#define FMT_MEMORY2_CONTROL__FMT420_MEM2_PWR_FORCE__SHIFT 0x4
++#define FMT_MEMORY2_CONTROL__FMT420_MEM2_PWR_DIS__SHIFT 0x8
++#define FMT_MEMORY2_CONTROL__FMT420_MEM2_PWR_STATE__SHIFT 0xc
++#define FMT_MEMORY2_CONTROL__FMT420_MEM2_SOURCE_SEL_MASK 0x00000007L
++#define FMT_MEMORY2_CONTROL__FMT420_MEM2_PWR_FORCE_MASK 0x00000030L
++#define FMT_MEMORY2_CONTROL__FMT420_MEM2_PWR_DIS_MASK 0x00000100L
++#define FMT_MEMORY2_CONTROL__FMT420_MEM2_PWR_STATE_MASK 0x00003000L
++//FMT_MEMORY3_CONTROL
++#define FMT_MEMORY3_CONTROL__FMT420_MEM3_SOURCE_SEL__SHIFT 0x0
++#define FMT_MEMORY3_CONTROL__FMT420_MEM3_PWR_FORCE__SHIFT 0x4
++#define FMT_MEMORY3_CONTROL__FMT420_MEM3_PWR_DIS__SHIFT 0x8
++#define FMT_MEMORY3_CONTROL__FMT420_MEM3_PWR_STATE__SHIFT 0xc
++#define FMT_MEMORY3_CONTROL__FMT420_MEM3_SOURCE_SEL_MASK 0x00000007L
++#define FMT_MEMORY3_CONTROL__FMT420_MEM3_PWR_FORCE_MASK 0x00000030L
++#define FMT_MEMORY3_CONTROL__FMT420_MEM3_PWR_DIS_MASK 0x00000100L
++#define FMT_MEMORY3_CONTROL__FMT420_MEM3_PWR_STATE_MASK 0x00003000L
++//FMT_MEMORY4_CONTROL
++#define FMT_MEMORY4_CONTROL__FMT420_MEM4_SOURCE_SEL__SHIFT 0x0
++#define FMT_MEMORY4_CONTROL__FMT420_MEM4_PWR_FORCE__SHIFT 0x4
++#define FMT_MEMORY4_CONTROL__FMT420_MEM4_PWR_DIS__SHIFT 0x8
++#define FMT_MEMORY4_CONTROL__FMT420_MEM4_PWR_STATE__SHIFT 0xc
++#define FMT_MEMORY4_CONTROL__FMT420_MEM4_SOURCE_SEL_MASK 0x00000007L
++#define FMT_MEMORY4_CONTROL__FMT420_MEM4_PWR_FORCE_MASK 0x00000030L
++#define FMT_MEMORY4_CONTROL__FMT420_MEM4_PWR_DIS_MASK 0x00000100L
++#define FMT_MEMORY4_CONTROL__FMT420_MEM4_PWR_STATE_MASK 0x00003000L
++//FMT_MEMORY5_CONTROL
++#define FMT_MEMORY5_CONTROL__FMT420_MEM5_SOURCE_SEL__SHIFT 0x0
++#define FMT_MEMORY5_CONTROL__FMT420_MEM5_PWR_FORCE__SHIFT 0x4
++#define FMT_MEMORY5_CONTROL__FMT420_MEM5_PWR_DIS__SHIFT 0x8
++#define FMT_MEMORY5_CONTROL__FMT420_MEM5_PWR_STATE__SHIFT 0xc
++#define FMT_MEMORY5_CONTROL__FMT420_MEM5_SOURCE_SEL_MASK 0x00000007L
++#define FMT_MEMORY5_CONTROL__FMT420_MEM5_PWR_FORCE_MASK 0x00000030L
++#define FMT_MEMORY5_CONTROL__FMT420_MEM5_PWR_DIS_MASK 0x00000100L
++#define FMT_MEMORY5_CONTROL__FMT420_MEM5_PWR_STATE_MASK 0x00003000L
++//DISP_INTERRUPT_STATUS_CONTINUE11
++#define DISP_INTERRUPT_STATUS_CONTINUE11__DCP0_xdma_vsync_flip_timeout_interrupt__SHIFT 0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE11__DCP1_xdma_vsync_flip_timeout_interrupt__SHIFT 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE11__DCP2_xdma_vsync_flip_timeout_interrupt__SHIFT 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE11__DCP3_xdma_vsync_flip_timeout_interrupt__SHIFT 0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE11__DCP4_xdma_vsync_flip_timeout_interrupt__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE11__DCP5_xdma_vsync_flip_timeout_interrupt__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE11__DCP0_xdma_vsync_flip_timeout_interrupt_MASK 0x00000001L
++#define DISP_INTERRUPT_STATUS_CONTINUE11__DCP1_xdma_vsync_flip_timeout_interrupt_MASK 0x00000002L
++#define DISP_INTERRUPT_STATUS_CONTINUE11__DCP2_xdma_vsync_flip_timeout_interrupt_MASK 0x00000004L
++#define DISP_INTERRUPT_STATUS_CONTINUE11__DCP3_xdma_vsync_flip_timeout_interrupt_MASK 0x00000008L
++#define DISP_INTERRUPT_STATUS_CONTINUE11__DCP4_xdma_vsync_flip_timeout_interrupt_MASK 0x00000010L
++#define DISP_INTERRUPT_STATUS_CONTINUE11__DCP5_xdma_vsync_flip_timeout_interrupt_MASK 0x00000020L
++//DC_GENERICA
++#define DC_GENERICA__GENERICA_EN__SHIFT 0x0
++#define DC_GENERICA__GENERICA_SEL__SHIFT 0x7
++#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc
++#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10
++#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14
++#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18
++#define DC_GENERICA__GENERICA_EN_MASK 0x00000001L
++#define DC_GENERICA__GENERICA_SEL_MASK 0x00000F80L
++#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK 0x0000F000L
++#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK 0x000F0000L
++#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x00F00000L
++#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x0F000000L
++//DC_GENERICB
++#define DC_GENERICB__GENERICB_EN__SHIFT 0x0
++#define DC_GENERICB__GENERICB_SEL__SHIFT 0x8
++#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc
++#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10
++#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14
++#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18
++#define DC_GENERICB__GENERICB_EN_MASK 0x00000001L
++#define DC_GENERICB__GENERICB_SEL_MASK 0x00000F00L
++#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK 0x0000F000L
++#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK 0x000F0000L
++#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x00F00000L
++#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x0F000000L
++//DC_PAD_EXTERN_SIG
++#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL__SHIFT 0x0
++#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS__SHIFT 0x4
++#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL_MASK 0x0000000FL
++#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS_MASK 0x00000030L
++//DC_REF_CLK_CNTL
++#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0
++#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x8
++#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x00000003L
++#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x00000300L
++//DC_GPIO_DEBUG
++#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG__SHIFT 0x0
++#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG__SHIFT 0x8
++#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL__SHIFT 0x10
++#define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN__SHIFT 0x11
++#define DC_GPIO_DEBUG__DPRX_LOOPBACK_ENABLE__SHIFT 0x1f
++#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG_MASK 0x00000001L
++#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG_MASK 0x00000300L
++#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_MASK 0x00010000L
++#define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN_MASK 0x00020000L
++#define DC_GPIO_DEBUG__DPRX_LOOPBACK_ENABLE_MASK 0x80000000L
++//UNIPHYA_LINK_CNTL
++#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
++#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
++#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
++#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
++#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
++#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
++#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
++#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
++#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
++#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L
++#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L
++#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L
++#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
++#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
++#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
++#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
++#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L
++#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L
++//UNIPHYA_CHANNEL_XBAR_CNTL
++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L
++//UNIPHYB_LINK_CNTL
++#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
++#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
++#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
++#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
++#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
++#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
++#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
++#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
++#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
++#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L
++#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L
++#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L
++#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
++#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
++#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
++#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
++#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L
++#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L
++//UNIPHYB_CHANNEL_XBAR_CNTL
++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L
++//UNIPHYC_LINK_CNTL
++#define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
++#define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
++#define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
++#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
++#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
++#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
++#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
++#define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
++#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
++#define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L
++#define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L
++#define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L
++#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
++#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
++#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
++#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
++#define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L
++#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L
++//UNIPHYC_CHANNEL_XBAR_CNTL
++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L
++//UNIPHYD_LINK_CNTL
++#define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
++#define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
++#define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
++#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
++#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
++#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
++#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
++#define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
++#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
++#define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L
++#define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L
++#define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L
++#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
++#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
++#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
++#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
++#define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L
++#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L
++//UNIPHYD_CHANNEL_XBAR_CNTL
++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L
++//UNIPHYE_LINK_CNTL
++#define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
++#define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
++#define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
++#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
++#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
++#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
++#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
++#define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
++#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
++#define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L
++#define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L
++#define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L
++#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
++#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
++#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
++#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
++#define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L
++#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L
++//UNIPHYE_CHANNEL_XBAR_CNTL
++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L
++//UNIPHYF_LINK_CNTL
++#define UNIPHYF_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
++#define UNIPHYF_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
++#define UNIPHYF_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
++#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
++#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
++#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
++#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
++#define UNIPHYF_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
++#define UNIPHYF_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
++#define UNIPHYF_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L
++#define UNIPHYF_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L
++#define UNIPHYF_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L
++#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
++#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
++#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
++#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
++#define UNIPHYF_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L
++#define UNIPHYF_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L
++//UNIPHYF_CHANNEL_XBAR_CNTL
++#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
++#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
++#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
++#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
++#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
++#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
++#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
++#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
++#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
++#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L
++//UNIPHYG_LINK_CNTL
++#define UNIPHYG_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
++#define UNIPHYG_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
++#define UNIPHYG_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
++#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
++#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
++#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
++#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
++#define UNIPHYG_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
++#define UNIPHYG_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
++#define UNIPHYG_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L
++#define UNIPHYG_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L
++#define UNIPHYG_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L
++#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
++#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
++#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
++#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
++#define UNIPHYG_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L
++#define UNIPHYG_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L
++//UNIPHYG_CHANNEL_XBAR_CNTL
++#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
++#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
++#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
++#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
++#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
++#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
++#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
++#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
++#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
++#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L
++//DCIO_WRCMD_DELAY
++#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT 0x0
++#define DCIO_WRCMD_DELAY__DAC_DELAY__SHIFT 0x4
++#define DCIO_WRCMD_DELAY__DPHY_DELAY__SHIFT 0x8
++#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY__SHIFT 0xc
++#define DCIO_WRCMD_DELAY__ZCAL_DELAY__SHIFT 0x10
++#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK 0x0000000FL
++#define DCIO_WRCMD_DELAY__DAC_DELAY_MASK 0x000000F0L
++#define DCIO_WRCMD_DELAY__DPHY_DELAY_MASK 0x00000F00L
++#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY_MASK 0x0000F000L
++#define DCIO_WRCMD_DELAY__ZCAL_DELAY_MASK 0x000F0000L
++//DC_DVODATA_CONFIG
++#define DC_DVODATA_CONFIG__VIP_MUX_EN__SHIFT 0x13
++#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN__SHIFT 0x14
++#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN__SHIFT 0x15
++#define DC_DVODATA_CONFIG__VIP_MUX_EN_MASK 0x00080000L
++#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN_MASK 0x00100000L
++#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN_MASK 0x00200000L
++//LVTMA_PWRSEQ_CNTL
++#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN__SHIFT 0x0
++#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN__SHIFT 0x1
++#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE__SHIFT 0x4
++#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT 0x8
++#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD__SHIFT 0x9
++#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT 0xa
++#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT 0x10
++#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x11
++#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT 0x12
++#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT 0x18
++#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT 0x19
++#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL__SHIFT 0x1a
++#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN_MASK 0x00000001L
++#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN_MASK 0x00000002L
++#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE_MASK 0x00000010L
++#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK 0x00000100L
++#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD_MASK 0x00000200L
++#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK 0x00000400L
++#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_MASK 0x00010000L
++#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD_MASK 0x00020000L
++#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL_MASK 0x00040000L
++#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_MASK 0x01000000L
++#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD_MASK 0x02000000L
++#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL_MASK 0x04000000L
++//LVTMA_PWRSEQ_STATE
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT 0x0
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON__SHIFT 0x1
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN__SHIFT 0x2
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON__SHIFT 0x3
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE__SHIFT 0x4
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT 0x8
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R_MASK 0x00000001L
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK 0x00000002L
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN_MASK 0x00000004L
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON_MASK 0x00000008L
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE_MASK 0x00000010L
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE_MASK 0x00000F00L
++//LVTMA_PWRSEQ_REF_DIV
++#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV__SHIFT 0x0
++#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT 0x10
++#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV_MASK 0x00000FFFL
++#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xFFFF0000L
++//LVTMA_PWRSEQ_DELAY1
++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1__SHIFT 0x0
++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2__SHIFT 0x8
++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1__SHIFT 0x10
++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2__SHIFT 0x18
++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1_MASK 0x000000FFL
++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2_MASK 0x0000FF00L
++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1_MASK 0x00FF0000L
++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2_MASK 0xFF000000L
++//LVTMA_PWRSEQ_DELAY2
++#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH__SHIFT 0x0
++#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3__SHIFT 0x8
++#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3__SHIFT 0x10
++#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN__SHIFT 0x18
++#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH_MASK 0x000000FFL
++#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3_MASK 0x0000FF00L
++#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3_MASK 0x00FF0000L
++#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN_MASK 0x01000000L
++//BL_PWM_CNTL
++#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT 0x0
++#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT 0x1e
++#define BL_PWM_CNTL__BL_PWM_EN__SHIFT 0x1f
++#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK 0x0000FFFFL
++#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK 0x40000000L
++#define BL_PWM_CNTL__BL_PWM_EN_MASK 0x80000000L
++//BL_PWM_CNTL2
++#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x0
++#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT 0x1e
++#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__SHIFT 0x1f
++#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0x0000FFFFL
++#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK 0x40000000L
++#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_MASK 0x80000000L
++//BL_PWM_PERIOD_CNTL
++#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT 0x0
++#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT 0x10
++#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0x0000FFFFL
++#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK 0x000F0000L
++//BL_PWM_GRP1_REG_LOCK
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT 0x0
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT 0x8
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT 0x10
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL__SHIFT 0x11
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT 0x18
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK 0x00000001L
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK 0x00000100L
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK 0x00010000L
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL_MASK 0x000E0000L
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L
++//DCIO_GSL_GENLK_PAD_CNTL
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL__SHIFT 0x0
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL__SHIFT 0x4
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x8
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL__SHIFT 0x10
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL__SHIFT 0x14
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x18
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL_MASK 0x00000003L
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL_MASK 0x00000030L
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x00000300L
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL_MASK 0x00030000L
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL_MASK 0x00300000L
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x03000000L
++//DCIO_GSL_SWAPLOCK_PAD_CNTL
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL__SHIFT 0x0
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL__SHIFT 0x4
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x8
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL__SHIFT 0x10
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL__SHIFT 0x14
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x18
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL_MASK 0x00000003L
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL_MASK 0x00000030L
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x00000300L
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL_MASK 0x00030000L
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL_MASK 0x00300000L
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x03000000L
++//DCIO_GSL0_CNTL
++#define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL__SHIFT 0x0
++#define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL__SHIFT 0x8
++#define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL__SHIFT 0x10
++#define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL_MASK 0x00000007L
++#define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL_MASK 0x00000700L
++#define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL_MASK 0x00070000L
++//DCIO_GSL1_CNTL
++#define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL__SHIFT 0x0
++#define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL__SHIFT 0x8
++#define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL__SHIFT 0x10
++#define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL_MASK 0x00000007L
++#define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL_MASK 0x00000700L
++#define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL_MASK 0x00070000L
++//DCIO_GSL2_CNTL
++#define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL__SHIFT 0x0
++#define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL__SHIFT 0x8
++#define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL__SHIFT 0x10
++#define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL_MASK 0x00000007L
++#define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL_MASK 0x00000700L
++#define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL_MASK 0x00070000L
++//DC_GPU_TIMER_START_POSITION_V_UPDATE
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT 0x0
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT 0x4
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT 0x8
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT 0xc
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT 0x10
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT 0x14
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK 0x00000007L
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK 0x00000070L
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK 0x00000700L
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK 0x00007000L
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK 0x00070000L
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK 0x00700000L
++//DC_GPU_TIMER_START_POSITION_P_FLIP
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP__SHIFT 0x0
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP__SHIFT 0x4
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP__SHIFT 0x8
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP__SHIFT 0xc
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP__SHIFT 0x10
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP__SHIFT 0x14
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_DCFEV0_P_FLIP__SHIFT 0x17
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_DCFEV1_P_FLIP__SHIFT 0x1a
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP_MASK 0x00000007L
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP_MASK 0x00000070L
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP_MASK 0x00000700L
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP_MASK 0x00007000L
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP_MASK 0x00070000L
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP_MASK 0x00700000L
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_DCFEV0_P_FLIP_MASK 0x03800000L
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_DCFEV1_P_FLIP_MASK 0x1C000000L
++//DC_GPU_TIMER_READ
++#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x0
++#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK 0xFFFFFFFFL
++//DC_GPU_TIMER_READ_CNTL
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT 0x0
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT 0x8
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT 0xb
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT 0xe
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT 0x11
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT 0x14
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT 0x17
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK 0x0000003FL
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK 0x00000700L
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK 0x00003800L
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK 0x0001C000L
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK 0x000E0000L
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK 0x00700000L
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK 0x03800000L
++//DCIO_CLOCK_CNTL
++#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT 0x0
++#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT 0x5
++#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK 0x0000001FL
++#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK 0x00000020L
++//DCO_DCFE_EXT_VSYNC_CNTL
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX__SHIFT 0x0
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX__SHIFT 0x4
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX__SHIFT 0x8
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX__SHIFT 0xc
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX__SHIFT 0x10
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX__SHIFT 0x14
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK__SHIFT 0x18
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK__SHIFT 0x1c
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL__SHIFT 0x1f
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX_MASK 0x00000007L
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX_MASK 0x00000070L
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX_MASK 0x00000700L
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX_MASK 0x00007000L
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX_MASK 0x00070000L
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX_MASK 0x00700000L
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK_MASK 0x07000000L
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK_MASK 0x70000000L
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL_MASK 0x80000000L
++//DCIO_SOFT_RESET
++#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT 0x0
++#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT 0x1
++#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT 0x2
++#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT 0x3
++#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT 0x4
++#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT 0x5
++#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT 0x6
++#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT 0x7
++#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT 0x8
++#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT 0x9
++#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT 0xa
++#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT 0xb
++#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT 0xc
++#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT 0xd
++#define DCIO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x10
++#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET__SHIFT 0x14
++#define DCIO_SOFT_RESET__DPHY_SOFT_RESET__SHIFT 0x18
++#define DCIO_SOFT_RESET__ZCAL_SOFT_RESET__SHIFT 0x1a
++#define DCIO_SOFT_RESET__UNIPHYLPA_SOFT_RESET__SHIFT 0x1c
++#define DCIO_SOFT_RESET__DSYNCLPA_SOFT_RESET__SHIFT 0x1d
++#define DCIO_SOFT_RESET__UNIPHYLPB_SOFT_RESET__SHIFT 0x1e
++#define DCIO_SOFT_RESET__DSYNCLPB_SOFT_RESET__SHIFT 0x1f
++#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK 0x00000001L
++#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET_MASK 0x00000002L
++#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK 0x00000004L
++#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET_MASK 0x00000008L
++#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK 0x00000010L
++#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET_MASK 0x00000020L
++#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK 0x00000040L
++#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET_MASK 0x00000080L
++#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK 0x00000100L
++#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET_MASK 0x00000200L
++#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK 0x00000400L
++#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET_MASK 0x00000800L
++#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK 0x00001000L
++#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET_MASK 0x00002000L
++#define DCIO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x00010000L
++#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET_MASK 0x00100000L
++#define DCIO_SOFT_RESET__DPHY_SOFT_RESET_MASK 0x01000000L
++#define DCIO_SOFT_RESET__ZCAL_SOFT_RESET_MASK 0x04000000L
++#define DCIO_SOFT_RESET__UNIPHYLPA_SOFT_RESET_MASK 0x10000000L
++#define DCIO_SOFT_RESET__DSYNCLPA_SOFT_RESET_MASK 0x20000000L
++#define DCIO_SOFT_RESET__UNIPHYLPB_SOFT_RESET_MASK 0x40000000L
++#define DCIO_SOFT_RESET__DSYNCLPB_SOFT_RESET_MASK 0x80000000L
++//DCIO_DPHY_SEL
++#define DCIO_DPHY_SEL__DPHY_LANE0_SEL__SHIFT 0x0
++#define DCIO_DPHY_SEL__DPHY_LANE1_SEL__SHIFT 0x2
++#define DCIO_DPHY_SEL__DPHY_LANE2_SEL__SHIFT 0x4
++#define DCIO_DPHY_SEL__DPHY_LANE3_SEL__SHIFT 0x6
++#define DCIO_DPHY_SEL__DPHY_LANE0_SEL_MASK 0x00000003L
++#define DCIO_DPHY_SEL__DPHY_LANE1_SEL_MASK 0x0000000CL
++#define DCIO_DPHY_SEL__DPHY_LANE2_SEL_MASK 0x00000030L
++#define DCIO_DPHY_SEL__DPHY_LANE3_SEL_MASK 0x000000C0L
++//UNIPHY_IMPCAL_LINKA
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA__SHIFT 0x0
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA__SHIFT 0x8
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA__SHIFT 0x9
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK__SHIFT 0xa
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA__SHIFT 0x10
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA__SHIFT 0x14
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA__SHIFT 0x18
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA__SHIFT 0x1c
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA__SHIFT 0x1e
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA_MASK 0x00000001L
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA_MASK 0x00000100L
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_MASK 0x00000200L
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK_MASK 0x00000400L
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA_MASK 0x000F0000L
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA_MASK 0x00F00000L
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA_MASK 0x0F000000L
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA_MASK 0x10000000L
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA_MASK 0x40000000L
++//UNIPHY_IMPCAL_LINKB
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB__SHIFT 0x0
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB__SHIFT 0x8
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB__SHIFT 0x9
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK__SHIFT 0xa
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB__SHIFT 0x10
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB__SHIFT 0x14
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB__SHIFT 0x18
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB__SHIFT 0x1c
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB__SHIFT 0x1e
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB_MASK 0x00000001L
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB_MASK 0x00000100L
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_MASK 0x00000200L
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK_MASK 0x00000400L
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB_MASK 0x000F0000L
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB_MASK 0x00F00000L
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB_MASK 0x0F000000L
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB_MASK 0x10000000L
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB_MASK 0x40000000L
++//UNIPHY_IMPCAL_PERIOD
++#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD__SHIFT 0x0
++#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD_MASK 0xFFFFFFFFL
++//AUXP_IMPCAL
++#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE__SHIFT 0x0
++#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT__SHIFT 0x8
++#define AUXP_IMPCAL__AUXP_CALOUT_ERROR__SHIFT 0x9
++#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK__SHIFT 0xa
++#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE__SHIFT 0x10
++#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY__SHIFT 0x14
++#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE__SHIFT 0x18
++#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c
++#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE_MASK 0x00000001L
++#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT_MASK 0x00000100L
++#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_MASK 0x00000200L
++#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK_MASK 0x00000400L
++#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE_MASK 0x000F0000L
++#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY_MASK 0x00F00000L
++#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_MASK 0x0F000000L
++#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000L
++//AUXN_IMPCAL
++#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE__SHIFT 0x0
++#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT__SHIFT 0x8
++#define AUXN_IMPCAL__AUXN_CALOUT_ERROR__SHIFT 0x9
++#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK__SHIFT 0xa
++#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE__SHIFT 0x10
++#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY__SHIFT 0x14
++#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE__SHIFT 0x18
++#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c
++#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE_MASK 0x00000001L
++#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT_MASK 0x00000100L
++#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_MASK 0x00000200L
++#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK_MASK 0x00000400L
++#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE_MASK 0x000F0000L
++#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY_MASK 0x00F00000L
++#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_MASK 0x0F000000L
++#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000L
++//DCIO_IMPCAL_CNTL
++#define DCIO_IMPCAL_CNTL__CALR_CNTL_OVERRIDE__SHIFT 0x0
++#define DCIO_IMPCAL_CNTL__IMPCAL_SOFT_RESET__SHIFT 0x5
++#define DCIO_IMPCAL_CNTL__IMPCAL_STATUS__SHIFT 0x8
++#define DCIO_IMPCAL_CNTL__IMPCAL_ARB_STATE__SHIFT 0xc
++#define DCIO_IMPCAL_CNTL__AUX_IMPCAL_INTERVAL__SHIFT 0xf
++#define DCIO_IMPCAL_CNTL__CALR_CNTL_OVERRIDE_MASK 0x0000000FL
++#define DCIO_IMPCAL_CNTL__IMPCAL_SOFT_RESET_MASK 0x00000020L
++#define DCIO_IMPCAL_CNTL__IMPCAL_STATUS_MASK 0x00000300L
++#define DCIO_IMPCAL_CNTL__IMPCAL_ARB_STATE_MASK 0x00007000L
++#define DCIO_IMPCAL_CNTL__AUX_IMPCAL_INTERVAL_MASK 0x00078000L
++//UNIPHY_IMPCAL_PSW_AB
++#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA__SHIFT 0x0
++#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB__SHIFT 0x10
++#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA_MASK 0x00007FFFL
++#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB_MASK 0x7FFF0000L
++//UNIPHY_IMPCAL_LINKC
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC__SHIFT 0x0
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC__SHIFT 0x8
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC__SHIFT 0x9
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK__SHIFT 0xa
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC__SHIFT 0x10
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC__SHIFT 0x14
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC__SHIFT 0x18
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC__SHIFT 0x1c
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC__SHIFT 0x1e
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC_MASK 0x00000001L
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC_MASK 0x00000100L
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_MASK 0x00000200L
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK_MASK 0x00000400L
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC_MASK 0x000F0000L
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC_MASK 0x00F00000L
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC_MASK 0x0F000000L
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC_MASK 0x10000000L
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC_MASK 0x40000000L
++//UNIPHY_IMPCAL_LINKD
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD__SHIFT 0x0
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD__SHIFT 0x8
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD__SHIFT 0x9
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK__SHIFT 0xa
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD__SHIFT 0x10
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD__SHIFT 0x14
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD__SHIFT 0x18
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD__SHIFT 0x1c
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD__SHIFT 0x1e
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD_MASK 0x00000001L
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD_MASK 0x00000100L
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_MASK 0x00000200L
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK_MASK 0x00000400L
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD_MASK 0x000F0000L
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD_MASK 0x00F00000L
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD_MASK 0x0F000000L
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD_MASK 0x10000000L
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD_MASK 0x40000000L
++//DCIO_IMPCAL_CNTL_CD
++#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE__SHIFT 0x0
++#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET__SHIFT 0x5
++#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS__SHIFT 0x8
++#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE__SHIFT 0xc
++#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE_MASK 0x0000000FL
++#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET_MASK 0x00000020L
++#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS_MASK 0x00000300L
++#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE_MASK 0x00007000L
++//UNIPHY_IMPCAL_PSW_CD
++#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC__SHIFT 0x0
++#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD__SHIFT 0x10
++#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC_MASK 0x00007FFFL
++#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD_MASK 0x7FFF0000L
++//UNIPHY_IMPCAL_LINKE
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE__SHIFT 0x0
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE__SHIFT 0x8
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE__SHIFT 0x9
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK__SHIFT 0xa
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE__SHIFT 0x10
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE__SHIFT 0x14
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE__SHIFT 0x18
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE__SHIFT 0x1c
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE__SHIFT 0x1e
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE_MASK 0x00000001L
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE_MASK 0x00000100L
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_MASK 0x00000200L
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK_MASK 0x00000400L
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE_MASK 0x000F0000L
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE_MASK 0x00F00000L
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE_MASK 0x0F000000L
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE_MASK 0x10000000L
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE_MASK 0x40000000L
++//UNIPHY_IMPCAL_LINKF
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF__SHIFT 0x0
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF__SHIFT 0x8
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF__SHIFT 0x9
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK__SHIFT 0xa
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF__SHIFT 0x10
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF__SHIFT 0x14
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF__SHIFT 0x18
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF__SHIFT 0x1c
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF__SHIFT 0x1e
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF_MASK 0x00000001L
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF_MASK 0x00000100L
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_MASK 0x00000200L
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK_MASK 0x00000400L
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF_MASK 0x000F0000L
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF_MASK 0x00F00000L
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF_MASK 0x0F000000L
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF_MASK 0x10000000L
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF_MASK 0x40000000L
++//DCIO_IMPCAL_CNTL_EF
++#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE__SHIFT 0x0
++#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET__SHIFT 0x5
++#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS__SHIFT 0x8
++#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE__SHIFT 0xc
++#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE_MASK 0x0000000FL
++#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET_MASK 0x00000020L
++#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS_MASK 0x00000300L
++#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE_MASK 0x00007000L
++//UNIPHY_IMPCAL_PSW_EF
++#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE__SHIFT 0x0
++#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF__SHIFT 0x10
++#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE_MASK 0x00007FFFL
++#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF_MASK 0x7FFF0000L
++//UNIPHYLPA_LINK_CNTL
++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_PFREQCHG__SHIFT 0x0
++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_PIXVLD_RESET__SHIFT 0x4
++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL0_INVERT__SHIFT 0xc
++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL1_INVERT__SHIFT 0xd
++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL2_INVERT__SHIFT 0xe
++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL3_INVERT__SHIFT 0xf
++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_LANE_STAGGER_DELAY__SHIFT 0x14
++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_LINK_ENABLE_HPD_MASK__SHIFT 0x18
++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_PFREQCHG_MASK 0x00000001L
++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_PIXVLD_RESET_MASK 0x00000010L
++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L
++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL0_INVERT_MASK 0x00001000L
++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL1_INVERT_MASK 0x00002000L
++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL2_INVERT_MASK 0x00004000L
++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL3_INVERT_MASK 0x00008000L
++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_LANE_STAGGER_DELAY_MASK 0x00700000L
++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_LINK_ENABLE_HPD_MASK_MASK 0x03000000L
++//UNIPHYLPB_LINK_CNTL
++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_PFREQCHG__SHIFT 0x0
++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_PIXVLD_RESET__SHIFT 0x4
++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL0_INVERT__SHIFT 0xc
++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL1_INVERT__SHIFT 0xd
++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL2_INVERT__SHIFT 0xe
++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL3_INVERT__SHIFT 0xf
++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_LANE_STAGGER_DELAY__SHIFT 0x14
++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_LINK_ENABLE_HPD_MASK__SHIFT 0x18
++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_PFREQCHG_MASK 0x00000001L
++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_PIXVLD_RESET_MASK 0x00000010L
++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L
++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL0_INVERT_MASK 0x00001000L
++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL1_INVERT_MASK 0x00002000L
++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL2_INVERT_MASK 0x00004000L
++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL3_INVERT_MASK 0x00008000L
++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_LANE_STAGGER_DELAY_MASK 0x00700000L
++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_LINK_ENABLE_HPD_MASK_MASK 0x03000000L
++//UNIPHYLPA_CHANNEL_XBAR_CNTL
++#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
++#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
++#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
++#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
++#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_LINK_ENABLE__SHIFT 0x1c
++#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
++#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
++#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
++#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
++#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_LINK_ENABLE_MASK 0x10000000L
++//UNIPHYLPB_CHANNEL_XBAR_CNTL
++#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
++#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
++#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
++#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
++#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_LINK_ENABLE__SHIFT 0x1c
++#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
++#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
++#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
++#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
++#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_LINK_ENABLE_MASK 0x10000000L
++//DCIO_DPCS_TX_INTERRUPT
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_TYPE__SHIFT 0x0
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_MASK__SHIFT 0x1
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_OCCUR__SHIFT 0x2
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_TYPE__SHIFT 0x3
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_MASK__SHIFT 0x4
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_OCCUR__SHIFT 0x5
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_TYPE__SHIFT 0x6
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_MASK__SHIFT 0x7
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_OCCUR__SHIFT 0x8
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_TYPE__SHIFT 0x9
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_MASK__SHIFT 0xa
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_OCCUR__SHIFT 0xb
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_TYPE__SHIFT 0xc
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_MASK__SHIFT 0xd
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_OCCUR__SHIFT 0xe
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_TYPE__SHIFT 0xf
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_MASK__SHIFT 0x10
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_OCCUR__SHIFT 0x11
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_TYPE__SHIFT 0x12
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_MASK__SHIFT 0x13
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_OCCUR__SHIFT 0x14
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPA_INT_TYPE__SHIFT 0x18
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPA_INT_MASK__SHIFT 0x19
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPA_INT_OCCUR__SHIFT 0x1a
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPB_INT_TYPE__SHIFT 0x1b
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPB_INT_MASK__SHIFT 0x1c
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPB_INT_OCCUR__SHIFT 0x1d
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_TYPE_MASK 0x00000001L
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_MASK_MASK 0x00000002L
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_OCCUR_MASK 0x00000004L
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_TYPE_MASK 0x00000008L
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_MASK_MASK 0x00000010L
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_OCCUR_MASK 0x00000020L
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_TYPE_MASK 0x00000040L
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_MASK_MASK 0x00000080L
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_OCCUR_MASK 0x00000100L
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_TYPE_MASK 0x00000200L
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_MASK_MASK 0x00000400L
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_OCCUR_MASK 0x00000800L
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_TYPE_MASK 0x00001000L
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_MASK_MASK 0x00002000L
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_OCCUR_MASK 0x00004000L
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_TYPE_MASK 0x00008000L
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_MASK_MASK 0x00010000L
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_OCCUR_MASK 0x00020000L
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_TYPE_MASK 0x00040000L
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_MASK_MASK 0x00080000L
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_OCCUR_MASK 0x00100000L
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPA_INT_TYPE_MASK 0x01000000L
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPA_INT_MASK_MASK 0x02000000L
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPA_INT_OCCUR_MASK 0x04000000L
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPB_INT_TYPE_MASK 0x08000000L
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPB_INT_MASK_MASK 0x10000000L
++#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPB_INT_OCCUR_MASK 0x20000000L
++//DCIO_DPCS_RX_INTERRUPT
++#define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_TYPE__SHIFT 0x0
++#define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_MASK__SHIFT 0x1
++#define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_OCCUR__SHIFT 0x2
++#define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_TYPE_MASK 0x00000001L
++#define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_MASK_MASK 0x00000002L
++#define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_OCCUR_MASK 0x00000004L
++//DCIO_SEMAPHORE0
++#define DCIO_SEMAPHORE0__DCIO_SEMAPHORE0_REQ__SHIFT 0x0
++#define DCIO_SEMAPHORE0__DCIO_SEMAPHORE0_GNT__SHIFT 0x10
++#define DCIO_SEMAPHORE0__DCIO_SEMAPHORE0_REQ_MASK 0x0000FFFFL
++#define DCIO_SEMAPHORE0__DCIO_SEMAPHORE0_GNT_MASK 0xFFFF0000L
++//DCIO_SEMAPHORE1
++#define DCIO_SEMAPHORE1__DCIO_SEMAPHORE1_REQ__SHIFT 0x0
++#define DCIO_SEMAPHORE1__DCIO_SEMAPHORE1_GNT__SHIFT 0x10
++#define DCIO_SEMAPHORE1__DCIO_SEMAPHORE1_REQ_MASK 0x0000FFFFL
++#define DCIO_SEMAPHORE1__DCIO_SEMAPHORE1_GNT_MASK 0xFFFF0000L
++//DCIO_SEMAPHORE2
++#define DCIO_SEMAPHORE2__DCIO_SEMAPHORE2_REQ__SHIFT 0x0
++#define DCIO_SEMAPHORE2__DCIO_SEMAPHORE2_GNT__SHIFT 0x10
++#define DCIO_SEMAPHORE2__DCIO_SEMAPHORE2_REQ_MASK 0x0000FFFFL
++#define DCIO_SEMAPHORE2__DCIO_SEMAPHORE2_GNT_MASK 0xFFFF0000L
++//DCIO_SEMAPHORE3
++#define DCIO_SEMAPHORE3__DCIO_SEMAPHORE3_REQ__SHIFT 0x0
++#define DCIO_SEMAPHORE3__DCIO_SEMAPHORE3_GNT__SHIFT 0x10
++#define DCIO_SEMAPHORE3__DCIO_SEMAPHORE3_REQ_MASK 0x0000FFFFL
++#define DCIO_SEMAPHORE3__DCIO_SEMAPHORE3_GNT_MASK 0xFFFF0000L
++//DCIO_SEMAPHORE4
++#define DCIO_SEMAPHORE4__DCIO_SEMAPHORE4_REQ__SHIFT 0x0
++#define DCIO_SEMAPHORE4__DCIO_SEMAPHORE4_GNT__SHIFT 0x10
++#define DCIO_SEMAPHORE4__DCIO_SEMAPHORE4_REQ_MASK 0x0000FFFFL
++#define DCIO_SEMAPHORE4__DCIO_SEMAPHORE4_GNT_MASK 0xFFFF0000L
++//DCIO_SEMAPHORE5
++#define DCIO_SEMAPHORE5__DCIO_SEMAPHORE5_REQ__SHIFT 0x0
++#define DCIO_SEMAPHORE5__DCIO_SEMAPHORE5_GNT__SHIFT 0x10
++#define DCIO_SEMAPHORE5__DCIO_SEMAPHORE5_REQ_MASK 0x0000FFFFL
++#define DCIO_SEMAPHORE5__DCIO_SEMAPHORE5_GNT_MASK 0xFFFF0000L
++//DCIO_SEMAPHORE6
++#define DCIO_SEMAPHORE6__DCIO_SEMAPHORE6_REQ__SHIFT 0x0
++#define DCIO_SEMAPHORE6__DCIO_SEMAPHORE6_GNT__SHIFT 0x10
++#define DCIO_SEMAPHORE6__DCIO_SEMAPHORE6_REQ_MASK 0x0000FFFFL
++#define DCIO_SEMAPHORE6__DCIO_SEMAPHORE6_GNT_MASK 0xFFFF0000L
++//DCIO_SEMAPHORE7
++#define DCIO_SEMAPHORE7__DCIO_SEMAPHORE7_REQ__SHIFT 0x0
++#define DCIO_SEMAPHORE7__DCIO_SEMAPHORE7_GNT__SHIFT 0x10
++#define DCIO_SEMAPHORE7__DCIO_SEMAPHORE7_REQ_MASK 0x0000FFFFL
++#define DCIO_SEMAPHORE7__DCIO_SEMAPHORE7_GNT_MASK 0xFFFF0000L
++//DC_GPIO_GENERIC_MASK
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT 0x0
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT 0x1
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT 0x2
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT 0x4
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT 0x5
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT 0x6
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT 0x8
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT 0x9
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT 0xa
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT 0xc
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT 0xd
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT 0xe
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT 0x10
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT 0x11
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT 0x12
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT 0x14
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT 0x15
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT 0x16
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT 0x18
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT 0x19
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT 0x1a
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK 0x00000001L
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK 0x00000002L
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK 0x0000000CL
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK 0x00000010L
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK 0x00000020L
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK 0x000000C0L
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK 0x00000100L
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK 0x00000200L
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK 0x00000C00L
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK 0x00001000L
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK 0x00002000L
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK 0x0000C000L
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK 0x00010000L
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK 0x00020000L
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK 0x000C0000L
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK 0x00100000L
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK 0x00200000L
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK 0x00C00000L
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK 0x01000000L
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK 0x02000000L
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK 0x0C000000L
++//DC_GPIO_GENERIC_A
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT 0x0
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT 0x8
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT 0x10
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT 0x14
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT 0x15
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT 0x16
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT 0x17
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK 0x00000001L
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK 0x00000100L
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK 0x00010000L
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK 0x00100000L
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK 0x00200000L
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK 0x00400000L
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK 0x00800000L
++//DC_GPIO_GENERIC_EN
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT 0x0
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT 0x8
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT 0x10
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT 0x14
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT 0x15
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT 0x16
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT 0x17
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK 0x00000001L
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK 0x00000100L
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK 0x00010000L
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK 0x00100000L
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK 0x00200000L
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK 0x00400000L
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK 0x00800000L
++//DC_GPIO_GENERIC_Y
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT 0x0
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT 0x8
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT 0x10
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT 0x14
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT 0x15
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT 0x16
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT 0x17
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK 0x00000001L
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK 0x00000100L
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK 0x00010000L
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK 0x00100000L
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK 0x00200000L
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK 0x00400000L
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK 0x00800000L
++//DC_GPIO_DVODATA_MASK
++#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK__SHIFT 0x0
++#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK__SHIFT 0x18
++#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK__SHIFT 0x1d
++#define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK__SHIFT 0x1e
++#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK_MASK 0x00FFFFFFL
++#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK_MASK 0x1F000000L
++#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK_MASK 0x20000000L
++#define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK_MASK 0xC0000000L
++//DC_GPIO_DVODATA_A
++#define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A__SHIFT 0x0
++#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A__SHIFT 0x18
++#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A__SHIFT 0x1d
++#define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A__SHIFT 0x1e
++#define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A_MASK 0x00FFFFFFL
++#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A_MASK 0x1F000000L
++#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A_MASK 0x20000000L
++#define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A_MASK 0xC0000000L
++//DC_GPIO_DVODATA_EN
++#define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN__SHIFT 0x0
++#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN__SHIFT 0x18
++#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN__SHIFT 0x1d
++#define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN__SHIFT 0x1e
++#define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN_MASK 0x00FFFFFFL
++#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN_MASK 0x1F000000L
++#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN_MASK 0x20000000L
++#define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN_MASK 0xC0000000L
++//DC_GPIO_DVODATA_Y
++#define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y__SHIFT 0x0
++#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y__SHIFT 0x18
++#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y__SHIFT 0x1d
++#define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y__SHIFT 0x1e
++#define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y_MASK 0x00FFFFFFL
++#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y_MASK 0x1F000000L
++#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y_MASK 0x20000000L
++#define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y_MASK 0xC0000000L
++//DC_GPIO_DDC1_MASK
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT 0x0
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT 0x4
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT 0x6
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT 0x8
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT 0xc
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT 0xe
++#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x10
++#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x14
++#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT 0x16
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT 0x18
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT 0x1c
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK 0x00000001L
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK 0x00000010L
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK 0x00000040L
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK 0x00000100L
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK 0x00001000L
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK 0x00004000L
++#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x00010000L
++#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x00100000L
++#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK 0x00400000L
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK 0x0F000000L
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK 0xF0000000L
++//DC_GPIO_DDC1_A
++#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT 0x0
++#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT 0x8
++#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK 0x00000001L
++#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK 0x00000100L
++//DC_GPIO_DDC1_EN
++#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT 0x0
++#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT 0x8
++#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK 0x00000001L
++#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK 0x00000100L
++//DC_GPIO_DDC1_Y
++#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT 0x0
++#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT 0x8
++#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK 0x00000001L
++#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK 0x00000100L
++//DC_GPIO_DDC2_MASK
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT 0x0
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT 0x4
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT 0x6
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT 0x8
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT 0xc
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT 0xe
++#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x10
++#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x14
++#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT 0x16
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT 0x18
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT 0x1c
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK 0x00000001L
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK 0x00000010L
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK 0x00000040L
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK 0x00000100L
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK 0x00001000L
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK 0x00004000L
++#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x00010000L
++#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x00100000L
++#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK 0x00400000L
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK 0x0F000000L
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK 0xF0000000L
++//DC_GPIO_DDC2_A
++#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT 0x0
++#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT 0x8
++#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK 0x00000001L
++#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK 0x00000100L
++//DC_GPIO_DDC2_EN
++#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT 0x0
++#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT 0x8
++#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK 0x00000001L
++#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK 0x00000100L
++//DC_GPIO_DDC2_Y
++#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT 0x0
++#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT 0x8
++#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK 0x00000001L
++#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK 0x00000100L
++//DC_GPIO_DDC3_MASK
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT 0x0
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT 0x4
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT 0x6
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT 0x8
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT 0xc
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT 0xe
++#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT 0x10
++#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT 0x14
++#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT 0x16
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT 0x18
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT 0x1c
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK 0x00000001L
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK 0x00000010L
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK 0x00000040L
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK 0x00000100L
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK 0x00001000L
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK 0x00004000L
++#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK 0x00010000L
++#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK 0x00100000L
++#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK 0x00400000L
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK 0x0F000000L
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK 0xF0000000L
++//DC_GPIO_DDC3_A
++#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT 0x0
++#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT 0x8
++#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK 0x00000001L
++#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK 0x00000100L
++//DC_GPIO_DDC3_EN
++#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT 0x0
++#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT 0x8
++#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK 0x00000001L
++#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK 0x00000100L
++//DC_GPIO_DDC3_Y
++#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT 0x0
++#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT 0x8
++#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK 0x00000001L
++#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK 0x00000100L
++//DC_GPIO_DDC4_MASK
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT 0x0
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT 0x4
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT 0x6
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT 0x8
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT 0xc
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT 0xe
++#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT 0x10
++#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT 0x14
++#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT 0x16
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT 0x18
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT 0x1c
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK 0x00000001L
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK 0x00000010L
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK 0x00000040L
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK 0x00000100L
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK 0x00001000L
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK 0x00004000L
++#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK 0x00010000L
++#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK 0x00100000L
++#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK 0x00400000L
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK 0x0F000000L
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK 0xF0000000L
++//DC_GPIO_DDC4_A
++#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT 0x0
++#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT 0x8
++#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK 0x00000001L
++#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK 0x00000100L
++//DC_GPIO_DDC4_EN
++#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT 0x0
++#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT 0x8
++#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK 0x00000001L
++#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK 0x00000100L
++//DC_GPIO_DDC4_Y
++#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT 0x0
++#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT 0x8
++#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK 0x00000001L
++#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK 0x00000100L
++//DC_GPIO_DDC5_MASK
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT 0x0
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT 0x4
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT 0x6
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT 0x8
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT 0xc
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT 0xe
++#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x10
++#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT 0x14
++#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT 0x16
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT 0x18
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT 0x1c
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK 0x00000001L
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK 0x00000010L
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK 0x00000040L
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK 0x00000100L
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK 0x00001000L
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK 0x00004000L
++#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK 0x00010000L
++#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK 0x00100000L
++#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK 0x00400000L
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK 0x0F000000L
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK 0xF0000000L
++//DC_GPIO_DDC5_A
++#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT 0x0
++#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT 0x8
++#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK 0x00000001L
++#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK 0x00000100L
++//DC_GPIO_DDC5_EN
++#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT 0x0
++#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT 0x8
++#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK 0x00000001L
++#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK 0x00000100L
++//DC_GPIO_DDC5_Y
++#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT 0x0
++#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT 0x8
++#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK 0x00000001L
++#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK 0x00000100L
++//DC_GPIO_DDC6_MASK
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK__SHIFT 0x0
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN__SHIFT 0x4
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV__SHIFT 0x6
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK__SHIFT 0x8
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN__SHIFT 0xc
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV__SHIFT 0xe
++#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE__SHIFT 0x10
++#define DC_GPIO_DDC6_MASK__AUX6_POL__SHIFT 0x14
++#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN__SHIFT 0x16
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR__SHIFT 0x18
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR__SHIFT 0x1c
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK_MASK 0x00000001L
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN_MASK 0x00000010L
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV_MASK 0x00000040L
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK_MASK 0x00000100L
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN_MASK 0x00001000L
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV_MASK 0x00004000L
++#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE_MASK 0x00010000L
++#define DC_GPIO_DDC6_MASK__AUX6_POL_MASK 0x00100000L
++#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN_MASK 0x00400000L
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR_MASK 0x0F000000L
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR_MASK 0xF0000000L
++//DC_GPIO_DDC6_A
++#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A__SHIFT 0x0
++#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A__SHIFT 0x8
++#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK 0x00000001L
++#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK 0x00000100L
++//DC_GPIO_DDC6_EN
++#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN__SHIFT 0x0
++#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN__SHIFT 0x8
++#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN_MASK 0x00000001L
++#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN_MASK 0x00000100L
++//DC_GPIO_DDC6_Y
++#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y__SHIFT 0x0
++#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y__SHIFT 0x8
++#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y_MASK 0x00000001L
++#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y_MASK 0x00000100L
++//DC_GPIO_DDCVGA_MASK
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x0
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x6
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x8
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0xc
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0xe
++#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT 0x10
++#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x14
++#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x16
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT 0x18
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x1c
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x00000001L
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x00000040L
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x00000100L
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x00001000L
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x00004000L
++#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK 0x00010000L
++#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x00100000L
++#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x00400000L
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK 0x0F000000L
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xF0000000L
++//DC_GPIO_DDCVGA_A
++#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x0
++#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x8
++#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x00000001L
++#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x00000100L
++//DC_GPIO_DDCVGA_EN
++#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x0
++#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x8
++#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x00000001L
++#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x00000100L
++//DC_GPIO_DDCVGA_Y
++#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x0
++#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x8
++#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x00000001L
++#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x00000100L
++//DC_GPIO_SYNCA_MASK
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK__SHIFT 0x0
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS__SHIFT 0x4
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV__SHIFT 0x6
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK__SHIFT 0x8
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS__SHIFT 0xc
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV__SHIFT 0xe
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK__SHIFT 0x18
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK__SHIFT 0x1c
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK_MASK 0x00000001L
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS_MASK 0x00000010L
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV_MASK 0x000000C0L
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK_MASK 0x00000100L
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS_MASK 0x00001000L
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV_MASK 0x0000C000L
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK_MASK 0x07000000L
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK_MASK 0x70000000L
++//DC_GPIO_SYNCA_A
++#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A__SHIFT 0x0
++#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A__SHIFT 0x8
++#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK 0x00000001L
++#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK 0x00000100L
++//DC_GPIO_SYNCA_EN
++#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN__SHIFT 0x0
++#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN__SHIFT 0x8
++#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN_MASK 0x00000001L
++#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN_MASK 0x00000100L
++//DC_GPIO_SYNCA_Y
++#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y__SHIFT 0x0
++#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y__SHIFT 0x8
++#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y_MASK 0x00000001L
++#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y_MASK 0x00000100L
++//DC_GPIO_GENLK_MASK
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT 0x0
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT 0x1
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT 0x3
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT 0x4
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT 0x8
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT 0x9
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT 0xb
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT 0xc
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT 0x10
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT 0x11
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT 0x13
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT 0x14
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT 0x18
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT 0x19
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT 0x1b
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT 0x1c
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK 0x00000001L
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK 0x00000002L
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK 0x00000008L
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK 0x00000030L
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK 0x00000100L
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK 0x00000200L
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK 0x00000800L
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK 0x00003000L
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK 0x00010000L
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK 0x00020000L
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK 0x00080000L
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK 0x00300000L
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK 0x01000000L
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK 0x02000000L
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK 0x08000000L
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK 0x30000000L
++//DC_GPIO_GENLK_A
++#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT 0x0
++#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT 0x8
++#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT 0x10
++#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT 0x18
++#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK 0x00000001L
++#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK 0x00000100L
++#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK 0x00010000L
++#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK 0x01000000L
++//DC_GPIO_GENLK_EN
++#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT 0x0
++#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT 0x8
++#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT 0x10
++#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT 0x18
++#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK 0x00000001L
++#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK 0x00000100L
++#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK 0x00010000L
++#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK 0x01000000L
++//DC_GPIO_GENLK_Y
++#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT 0x0
++#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT 0x8
++#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT 0x10
++#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT 0x18
++#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK 0x00000001L
++#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK 0x00000100L
++#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK 0x00010000L
++#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK 0x01000000L
++//DC_GPIO_HPD_MASK
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT 0x0
++#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK__SHIFT 0x1
++#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS__SHIFT 0x2
++#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL__SHIFT 0x3
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT 0x4
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT 0x6
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT 0x8
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT 0x9
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT 0xa
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT 0x10
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT 0x11
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT 0x12
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT 0x14
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT 0x15
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT 0x16
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT 0x18
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT 0x19
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT 0x1a
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT 0x1c
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT 0x1d
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT 0x1e
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK 0x00000001L
++#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK_MASK 0x00000002L
++#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS_MASK 0x00000004L
++#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL_MASK 0x00000008L
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK 0x00000010L
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK 0x000000C0L
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK 0x00000100L
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK 0x00000200L
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK 0x00000C00L
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK 0x00010000L
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK 0x00020000L
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK 0x000C0000L
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK 0x00100000L
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK 0x00200000L
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK 0x00C00000L
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK 0x01000000L
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK 0x02000000L
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK 0x0C000000L
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK 0x10000000L
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK 0x20000000L
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK 0xC0000000L
++//DC_GPIO_HPD_A
++#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT 0x0
++#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT 0x8
++#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT 0x10
++#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT 0x18
++#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT 0x1a
++#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT 0x1c
++#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK 0x00000001L
++#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK 0x00000100L
++#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK 0x00010000L
++#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK 0x01000000L
++#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK 0x04000000L
++#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK 0x10000000L
++//DC_GPIO_HPD_EN
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT 0x0
++#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI__SHIFT 0x1
++#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE__SHIFT 0x2
++#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI__SHIFT 0x3
++#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE__SHIFT 0x4
++#define DC_GPIO_HPD_EN__HPD12_SPARE0__SHIFT 0x5
++#define DC_GPIO_HPD_EN__HPD1_SEL0__SHIFT 0x6
++#define DC_GPIO_HPD_EN__RX_HPD_SEL0__SHIFT 0x7
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT 0x8
++#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI__SHIFT 0x9
++#define DC_GPIO_HPD_EN__HPD12_SPARE1__SHIFT 0xa
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT 0x10
++#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI__SHIFT 0x11
++#define DC_GPIO_HPD_EN__HPD34_SPARE0__SHIFT 0x12
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT 0x14
++#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI__SHIFT 0x15
++#define DC_GPIO_HPD_EN__HPD34_SPARE1__SHIFT 0x16
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT 0x18
++#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI__SHIFT 0x19
++#define DC_GPIO_HPD_EN__HPD56_SPARE0__SHIFT 0x1a
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT 0x1c
++#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI__SHIFT 0x1d
++#define DC_GPIO_HPD_EN__HPD56_SPARE1__SHIFT 0x1e
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK 0x00000001L
++#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI_MASK 0x00000002L
++#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE_MASK 0x00000004L
++#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI_MASK 0x00000008L
++#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE_MASK 0x00000010L
++#define DC_GPIO_HPD_EN__HPD12_SPARE0_MASK 0x00000020L
++#define DC_GPIO_HPD_EN__HPD1_SEL0_MASK 0x00000040L
++#define DC_GPIO_HPD_EN__RX_HPD_SEL0_MASK 0x00000080L
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK 0x00000100L
++#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI_MASK 0x00000200L
++#define DC_GPIO_HPD_EN__HPD12_SPARE1_MASK 0x00000400L
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK 0x00010000L
++#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI_MASK 0x00020000L
++#define DC_GPIO_HPD_EN__HPD34_SPARE0_MASK 0x00040000L
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK 0x00100000L
++#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI_MASK 0x00200000L
++#define DC_GPIO_HPD_EN__HPD34_SPARE1_MASK 0x00400000L
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK 0x01000000L
++#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI_MASK 0x02000000L
++#define DC_GPIO_HPD_EN__HPD56_SPARE0_MASK 0x04000000L
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK 0x10000000L
++#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI_MASK 0x20000000L
++#define DC_GPIO_HPD_EN__HPD56_SPARE1_MASK 0x40000000L
++//DC_GPIO_HPD_Y
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT 0x0
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT 0x8
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT 0x10
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT 0x18
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT 0x1a
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT 0x1c
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK 0x00000001L
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK 0x00000100L
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK 0x00010000L
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK 0x01000000L
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK 0x04000000L
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK 0x10000000L
++//DC_GPIO_PWRSEQ_MASK
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT 0x0
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT 0x4
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT 0x6
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT 0x8
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT 0xc
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0xe
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK__SHIFT 0x10
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS__SHIFT 0x14
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV__SHIFT 0x16
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK__SHIFT 0x18
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS__SHIFT 0x19
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV__SHIFT 0x1a
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK__SHIFT 0x1c
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS__SHIFT 0x1d
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV__SHIFT 0x1e
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK 0x00000001L
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK 0x00000010L
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK 0x000000C0L
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK 0x00000100L
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK 0x00001000L
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK 0x0000C000L
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK_MASK 0x00010000L
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS_MASK 0x00100000L
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV_MASK 0x00C00000L
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK_MASK 0x01000000L
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS_MASK 0x02000000L
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV_MASK 0x04000000L
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK_MASK 0x10000000L
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS_MASK 0x20000000L
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV_MASK 0x40000000L
++//DC_GPIO_PWRSEQ_A
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A__SHIFT 0x0
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A__SHIFT 0x8
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A__SHIFT 0x10
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A__SHIFT 0x18
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A__SHIFT 0x1f
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A_MASK 0x00000001L
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A_MASK 0x00000100L
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A_MASK 0x00010000L
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A_MASK 0x01000000L
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A_MASK 0x80000000L
++//DC_GPIO_PWRSEQ_EN
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT 0x0
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x1
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT 0x8
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN__SHIFT 0x10
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN__SHIFT 0x18
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN__SHIFT 0x1f
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK 0x00000001L
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x00000002L
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK 0x00000100L
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN_MASK 0x00010000L
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN_MASK 0x01000000L
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN_MASK 0x80000000L
++//DC_GPIO_PWRSEQ_Y
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y__SHIFT 0x0
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y__SHIFT 0x8
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y__SHIFT 0x10
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN__SHIFT 0x18
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN__SHIFT 0x1f
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y_MASK 0x00000001L
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y_MASK 0x00000100L
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y_MASK 0x00010000L
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN_MASK 0x01000000L
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN_MASK 0x80000000L
++//DC_GPIO_PAD_STRENGTH_1
++#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x0
++#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x4
++#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN__SHIFT 0x8
++#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP__SHIFT 0xc
++#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN__SHIFT 0x10
++#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP__SHIFT 0x14
++#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x18
++#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x1c
++#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0x0000000FL
++#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0x000000F0L
++#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN_MASK 0x00000F00L
++#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP_MASK 0x0000F000L
++#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN_MASK 0x000F0000L
++#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP_MASK 0x00F00000L
++#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0x0F000000L
++#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xF0000000L
++//DC_GPIO_PAD_STRENGTH_2
++#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT 0x0
++#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT 0x4
++#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT 0x8
++#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT 0xc
++#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN__SHIFT 0x10
++#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP__SHIFT 0x14
++#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT 0x1e
++#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK 0x0000000FL
++#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK 0x000000F0L
++#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK 0x00000700L
++#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK 0x00007000L
++#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN_MASK 0x000F0000L
++#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP_MASK 0x00F00000L
++#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK 0xC0000000L
++//PHY_AUX_CNTL
++#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN__SHIFT 0x0
++#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE__SHIFT 0x1
++#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL__SHIFT 0x2
++#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE__SHIFT 0x3
++#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN__SHIFT 0x4
++#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN__SHIFT 0x5
++#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN__SHIFT 0x6
++#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN__SHIFT 0x7
++#define PHY_AUX_CNTL__AUX_PAD_SLEWN__SHIFT 0xc
++#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN__SHIFT 0xd
++#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0xe
++#define PHY_AUX_CNTL__AUX_PAD_RXSEL__SHIFT 0x10
++#define PHY_AUX_CNTL__AUX_CAL_BIASENTST__SHIFT 0x14
++#define PHY_AUX_CNTL__AUX_CAL_RESBIASEN__SHIFT 0x17
++#define PHY_AUX_CNTL__AUX_CAL_SPARE__SHIFT 0x18
++#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN_MASK 0x00000001L
++#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE_MASK 0x00000002L
++#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL_MASK 0x00000004L
++#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE_MASK 0x00000008L
++#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN_MASK 0x00000010L
++#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN_MASK 0x00000020L
++#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN_MASK 0x00000040L
++#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN_MASK 0x00000080L
++#define PHY_AUX_CNTL__AUX_PAD_SLEWN_MASK 0x00001000L
++#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN_MASK 0x00002000L
++#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK 0x00004000L
++#define PHY_AUX_CNTL__AUX_PAD_RXSEL_MASK 0x00030000L
++#define PHY_AUX_CNTL__AUX_CAL_BIASENTST_MASK 0x00700000L
++#define PHY_AUX_CNTL__AUX_CAL_RESBIASEN_MASK 0x00800000L
++#define PHY_AUX_CNTL__AUX_CAL_SPARE_MASK 0x03000000L
++//DC_GPIO_I2CPAD_MASK
++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK__SHIFT 0x0
++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS__SHIFT 0x1
++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV__SHIFT 0x2
++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK__SHIFT 0x4
++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS__SHIFT 0x5
++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV__SHIFT 0x6
++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK_MASK 0x00000001L
++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS_MASK 0x00000002L
++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV_MASK 0x00000004L
++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK_MASK 0x00000010L
++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS_MASK 0x00000020L
++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV_MASK 0x00000040L
++//DC_GPIO_I2CPAD_A
++#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A__SHIFT 0x0
++#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A__SHIFT 0x1
++#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A_MASK 0x00000001L
++#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A_MASK 0x00000002L
++//DC_GPIO_I2CPAD_EN
++#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN__SHIFT 0x0
++#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN__SHIFT 0x1
++#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN_MASK 0x00000001L
++#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN_MASK 0x00000002L
++//DC_GPIO_I2CPAD_Y
++#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y__SHIFT 0x0
++#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y__SHIFT 0x1
++#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y_MASK 0x00000001L
++#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y_MASK 0x00000002L
++//DC_GPIO_I2CPAD_STRENGTH
++#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN__SHIFT 0x0
++#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP__SHIFT 0x4
++#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN_MASK 0x0000000FL
++#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP_MASK 0x000000F0L
++//DVO_STRENGTH_CONTROL
++#define DVO_STRENGTH_CONTROL__DVO_SP__SHIFT 0x0
++#define DVO_STRENGTH_CONTROL__DVO_SN__SHIFT 0x4
++#define DVO_STRENGTH_CONTROL__DVOCLK_SP__SHIFT 0x8
++#define DVO_STRENGTH_CONTROL__DVOCLK_SN__SHIFT 0xc
++#define DVO_STRENGTH_CONTROL__DVO_DRVSTRENGTH__SHIFT 0x10
++#define DVO_STRENGTH_CONTROL__DVOCLK_DRVSTRENGTH__SHIFT 0x14
++#define DVO_STRENGTH_CONTROL__FLDO_VITNE_DRVSTRENGTH__SHIFT 0x18
++#define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE__SHIFT 0x1c
++#define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE__SHIFT 0x1d
++#define DVO_STRENGTH_CONTROL__DVO_SP_MASK 0x0000000FL
++#define DVO_STRENGTH_CONTROL__DVO_SN_MASK 0x000000F0L
++#define DVO_STRENGTH_CONTROL__DVOCLK_SP_MASK 0x00000F00L
++#define DVO_STRENGTH_CONTROL__DVOCLK_SN_MASK 0x0000F000L
++#define DVO_STRENGTH_CONTROL__DVO_DRVSTRENGTH_MASK 0x00070000L
++#define DVO_STRENGTH_CONTROL__DVOCLK_DRVSTRENGTH_MASK 0x00700000L
++#define DVO_STRENGTH_CONTROL__FLDO_VITNE_DRVSTRENGTH_MASK 0x07000000L
++#define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE_MASK 0x10000000L
++#define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE_MASK 0x20000000L
++//DVO_VREF_CONTROL
++#define DVO_VREF_CONTROL__DVO_VREFPON__SHIFT 0x0
++#define DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT 0x1
++#define DVO_VREF_CONTROL__DVO_VREFCAL__SHIFT 0x4
++#define DVO_VREF_CONTROL__DVO_VREFPON_MASK 0x00000001L
++#define DVO_VREF_CONTROL__DVO_VREFSEL_MASK 0x00000002L
++#define DVO_VREF_CONTROL__DVO_VREFCAL_MASK 0x000000F0L
++//DVO_SKEW_ADJUST
++#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST__SHIFT 0x0
++#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST_MASK 0xFFFFFFFFL
++//DC_GPIO_I2S_SPDIF_MASK
++#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA0_MASK__SHIFT 0x0
++#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK0_MASK__SHIFT 0x4
++#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK0_MASK__SHIFT 0x5
++#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK0_MASK__SHIFT 0x6
++#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF0_MASK__SHIFT 0x7
++#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA1_MASK__SHIFT 0x8
++#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK1_MASK__SHIFT 0x9
++#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK1_MASK__SHIFT 0xa
++#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK1_MASK__SHIFT 0xb
++#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF1_MASK__SHIFT 0xc
++#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA0_MASK_MASK 0x0000000FL
++#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK0_MASK_MASK 0x00000010L
++#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK0_MASK_MASK 0x00000020L
++#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK0_MASK_MASK 0x00000040L
++#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF0_MASK_MASK 0x00000080L
++#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA1_MASK_MASK 0x00000100L
++#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK1_MASK_MASK 0x00000200L
++#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK1_MASK_MASK 0x00000400L
++#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK1_MASK_MASK 0x00000800L
++#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF1_MASK_MASK 0x00001000L
++//DC_GPIO_I2S_SPDIF_A
++#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA0_A__SHIFT 0x0
++#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK0_A__SHIFT 0x4
++#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK0_A__SHIFT 0x5
++#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK0_A__SHIFT 0x6
++#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF0_A__SHIFT 0x7
++#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA1_A__SHIFT 0x8
++#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK1_A__SHIFT 0x9
++#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK1_A__SHIFT 0xa
++#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK1_A__SHIFT 0xb
++#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF1_A__SHIFT 0xc
++#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA0_A_MASK 0x0000000FL
++#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK0_A_MASK 0x00000010L
++#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK0_A_MASK 0x00000020L
++#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK0_A_MASK 0x00000040L
++#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF0_A_MASK 0x00000080L
++#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA1_A_MASK 0x00000100L
++#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK1_A_MASK 0x00000200L
++#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK1_A_MASK 0x00000400L
++#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK1_A_MASK 0x00000800L
++#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF1_A_MASK 0x00001000L
++//DC_GPIO_I2S_SPDIF_EN
++#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA0_EN__SHIFT 0x0
++#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK0_EN__SHIFT 0x4
++#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK0_EN__SHIFT 0x5
++#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK0_EN__SHIFT 0x6
++#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF0_EN__SHIFT 0x7
++#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA1_EN__SHIFT 0x8
++#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK1_EN__SHIFT 0x9
++#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK1_EN__SHIFT 0xa
++#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK1_EN__SHIFT 0xb
++#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF1_EN__SHIFT 0xc
++#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_APORT__SHIFT 0xd
++#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_PU__SHIFT 0xe
++#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_RXSEL__SHIFT 0xf
++#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_SCHMEN__SHIFT 0x10
++#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_SMODE_EN__SHIFT 0x11
++#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_IMODE__SHIFT 0x12
++#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA0_EN_MASK 0x0000000FL
++#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK0_EN_MASK 0x00000010L
++#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK0_EN_MASK 0x00000020L
++#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK0_EN_MASK 0x00000040L
++#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF0_EN_MASK 0x00000080L
++#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA1_EN_MASK 0x00000100L
++#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK1_EN_MASK 0x00000200L
++#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK1_EN_MASK 0x00000400L
++#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK1_EN_MASK 0x00000800L
++#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF1_EN_MASK 0x00001000L
++#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_APORT_MASK 0x00002000L
++#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_PU_MASK 0x00004000L
++#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_RXSEL_MASK 0x00008000L
++#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_SCHMEN_MASK 0x00010000L
++#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_SMODE_EN_MASK 0x00020000L
++#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_IMODE_MASK 0x00040000L
++//DC_GPIO_I2S_SPDIF_Y
++#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA0_Y__SHIFT 0x0
++#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK0_Y__SHIFT 0x4
++#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK0_Y__SHIFT 0x5
++#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK0_Y__SHIFT 0x6
++#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF0_Y__SHIFT 0x7
++#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA1_Y__SHIFT 0x8
++#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK1_Y__SHIFT 0x9
++#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK1_Y__SHIFT 0xa
++#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK1_Y__SHIFT 0xb
++#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF1_Y__SHIFT 0xc
++#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA0_Y_MASK 0x0000000FL
++#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK0_Y_MASK 0x00000010L
++#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK0_Y_MASK 0x00000020L
++#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK0_Y_MASK 0x00000040L
++#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF0_Y_MASK 0x00000080L
++#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA1_Y_MASK 0x00000100L
++#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK1_Y_MASK 0x00000200L
++#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK1_Y_MASK 0x00000400L
++#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK1_Y_MASK 0x00000800L
++#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF1_Y_MASK 0x00001000L
++//DC_GPIO_I2S_SPDIF_STRENGTH
++#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S0_DRVSTRENGTH__SHIFT 0x0
++#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_SN__SHIFT 0x8
++#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_SP__SHIFT 0xb
++#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S1_DRVSTRENGTH__SHIFT 0x10
++#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH_SN__SHIFT 0x18
++#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH_SP__SHIFT 0x1b
++#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S0_DRVSTRENGTH_MASK 0x00000007L
++#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_SN_MASK 0x00000700L
++#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_SP_MASK 0x00003800L
++#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S1_DRVSTRENGTH_MASK 0x00070000L
++#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH_SN_MASK 0x07000000L
++#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH_SP_MASK 0x38000000L
++//DC_GPIO_TX12_EN
++#define DC_GPIO_TX12_EN__DC_GPIO_BLON_TX12_EN__SHIFT 0x0
++#define DC_GPIO_TX12_EN__DC_GPIO_DIGON_TX12_EN__SHIFT 0x1
++#define DC_GPIO_TX12_EN__DC_GPIO_ENA_BL_TX12_EN__SHIFT 0x2
++#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN__SHIFT 0x3
++#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN__SHIFT 0x4
++#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN__SHIFT 0x5
++#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN__SHIFT 0x6
++#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN__SHIFT 0x7
++#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN__SHIFT 0x8
++#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN__SHIFT 0x9
++#define DC_GPIO_TX12_EN__DC_GPIO_HSYNC_TX12_EN__SHIFT 0xa
++#define DC_GPIO_TX12_EN__DC_GPIO_VSYNC_TX12_EN__SHIFT 0xb
++#define DC_GPIO_TX12_EN__DC_GPIO_GENLK_CLK_TX12_EN__SHIFT 0xc
++#define DC_GPIO_TX12_EN__DC_GPIO_GENLK_VSYNC_TX12_EN__SHIFT 0xd
++#define DC_GPIO_TX12_EN__DC_GPIO_SWAPLOCKA_TX12_EN__SHIFT 0xe
++#define DC_GPIO_TX12_EN__DC_GPIO_SWAPLOCKB_TX12_EN__SHIFT 0xf
++#define DC_GPIO_TX12_EN__DC_GPIO_SCL_TX12_EN__SHIFT 0x10
++#define DC_GPIO_TX12_EN__DC_GPIO_SDA_TX12_EN__SHIFT 0x11
++#define DC_GPIO_TX12_EN__DC_GPIO_HPD1_TX12_EN__SHIFT 0x12
++#define DC_GPIO_TX12_EN__DC_GPIO_BLON_TX12_EN_MASK 0x00000001L
++#define DC_GPIO_TX12_EN__DC_GPIO_DIGON_TX12_EN_MASK 0x00000002L
++#define DC_GPIO_TX12_EN__DC_GPIO_ENA_BL_TX12_EN_MASK 0x00000004L
++#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN_MASK 0x00000008L
++#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN_MASK 0x00000010L
++#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN_MASK 0x00000020L
++#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN_MASK 0x00000040L
++#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN_MASK 0x00000080L
++#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN_MASK 0x00000100L
++#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN_MASK 0x00000200L
++#define DC_GPIO_TX12_EN__DC_GPIO_HSYNC_TX12_EN_MASK 0x00000400L
++#define DC_GPIO_TX12_EN__DC_GPIO_VSYNC_TX12_EN_MASK 0x00000800L
++#define DC_GPIO_TX12_EN__DC_GPIO_GENLK_CLK_TX12_EN_MASK 0x00001000L
++#define DC_GPIO_TX12_EN__DC_GPIO_GENLK_VSYNC_TX12_EN_MASK 0x00002000L
++#define DC_GPIO_TX12_EN__DC_GPIO_SWAPLOCKA_TX12_EN_MASK 0x00004000L
++#define DC_GPIO_TX12_EN__DC_GPIO_SWAPLOCKB_TX12_EN_MASK 0x00008000L
++#define DC_GPIO_TX12_EN__DC_GPIO_SCL_TX12_EN_MASK 0x00010000L
++#define DC_GPIO_TX12_EN__DC_GPIO_SDA_TX12_EN_MASK 0x00020000L
++#define DC_GPIO_TX12_EN__DC_GPIO_HPD1_TX12_EN_MASK 0x00040000L
++//DC_GPIO_AUX_CTRL_0
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL__SHIFT 0x0
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL__SHIFT 0x2
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL__SHIFT 0x4
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL__SHIFT 0x6
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL__SHIFT 0x8
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL__SHIFT 0xa
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL__SHIFT 0xc
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_GENI2C_FALLSLEWSEL__SHIFT 0xe
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN__SHIFT 0x10
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN__SHIFT 0x11
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN__SHIFT 0x12
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN__SHIFT 0x13
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN__SHIFT 0x14
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN__SHIFT 0x15
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN__SHIFT 0x16
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_GENI2C_SPIKERCEN__SHIFT 0x17
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL__SHIFT 0x18
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL__SHIFT 0x19
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL__SHIFT 0x1a
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL__SHIFT 0x1b
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL__SHIFT 0x1c
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL__SHIFT 0x1d
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL__SHIFT 0x1e
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_GENI2C_SPIKERCSEL__SHIFT 0x1f
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL_MASK 0x00000003L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL_MASK 0x0000000CL
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL_MASK 0x00000030L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL_MASK 0x000000C0L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL_MASK 0x00000300L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL_MASK 0x00000C00L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL_MASK 0x00003000L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_GENI2C_FALLSLEWSEL_MASK 0x0000C000L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN_MASK 0x00010000L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN_MASK 0x00020000L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN_MASK 0x00040000L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN_MASK 0x00080000L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN_MASK 0x00100000L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN_MASK 0x00200000L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN_MASK 0x00400000L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_GENI2C_SPIKERCEN_MASK 0x00800000L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL_MASK 0x01000000L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL_MASK 0x02000000L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL_MASK 0x04000000L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL_MASK 0x08000000L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL_MASK 0x10000000L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL_MASK 0x20000000L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL_MASK 0x40000000L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_GENI2C_SPIKERCSEL_MASK 0x80000000L
++//DC_GPIO_AUX_CTRL_1
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9__SHIFT 0x0
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1__SHIFT 0x1
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9__SHIFT 0x2
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1__SHIFT 0x3
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9__SHIFT 0x4
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1__SHIFT 0x5
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9__SHIFT 0x6
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1__SHIFT 0x7
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN__SHIFT 0x8
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN__SHIFT 0x9
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN__SHIFT 0xa
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN__SHIFT 0xb
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_COMPSEL__SHIFT 0xc
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_COMPSEL__SHIFT 0xd
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE__SHIFT 0xe
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_SPARE__SHIFT 0x10
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN__SHIFT 0x12
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_SLEWN__SHIFT 0x13
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL__SHIFT 0x14
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_RXSEL__SHIFT 0x16
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_PDEN__SHIFT 0x18
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9_MASK 0x00000001L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1_MASK 0x00000002L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9_MASK 0x00000004L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1_MASK 0x00000008L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9_MASK 0x00000010L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1_MASK 0x00000020L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9_MASK 0x00000040L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1_MASK 0x00000080L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN_MASK 0x00000100L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN_MASK 0x00000200L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN_MASK 0x00000400L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN_MASK 0x00000800L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_COMPSEL_MASK 0x00001000L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_COMPSEL_MASK 0x00002000L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE_MASK 0x0000C000L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_SPARE_MASK 0x00030000L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN_MASK 0x00040000L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_SLEWN_MASK 0x00080000L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL_MASK 0x00300000L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_RXSEL_MASK 0x00C00000L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_PDEN_MASK 0x01000000L
++//DC_GPIO_AUX_CTRL_2
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL__SHIFT 0x0
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL__SHIFT 0x2
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL__SHIFT 0x4
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN__SHIFT 0x8
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN__SHIFT 0x9
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN__SHIFT 0xa
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL__SHIFT 0xc
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL__SHIFT 0xd
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL__SHIFT 0xe
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9__SHIFT 0x10
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1__SHIFT 0x11
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9__SHIFT 0x12
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1__SHIFT 0x13
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN__SHIFT 0x14
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN__SHIFT 0x18
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN__SHIFT 0x19
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN__SHIFT 0x1a
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL_MASK 0x00000003L
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL_MASK 0x0000000CL
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL_MASK 0x00000030L
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN_MASK 0x00000100L
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN_MASK 0x00000200L
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN_MASK 0x00000400L
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL_MASK 0x00001000L
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL_MASK 0x00002000L
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL_MASK 0x00004000L
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9_MASK 0x00010000L
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1_MASK 0x00020000L
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9_MASK 0x00040000L
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1_MASK 0x00080000L
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN_MASK 0x00100000L
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN_MASK 0x01000000L
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN_MASK 0x02000000L
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN_MASK 0x04000000L
++//DC_GPIO_RXEN
++#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN__SHIFT 0x0
++#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN__SHIFT 0x1
++#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN__SHIFT 0x2
++#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN__SHIFT 0x3
++#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN__SHIFT 0x4
++#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN__SHIFT 0x5
++#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN__SHIFT 0x6
++#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN__SHIFT 0x8
++#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN__SHIFT 0x9
++#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN__SHIFT 0xa
++#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN__SHIFT 0xb
++#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN__SHIFT 0xc
++#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN__SHIFT 0xd
++#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN__SHIFT 0xe
++#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN__SHIFT 0xf
++#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN__SHIFT 0x10
++#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN__SHIFT 0x11
++#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN__SHIFT 0x12
++#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN__SHIFT 0x13
++#define DC_GPIO_RXEN__DC_GPIO_BLON_RXEN__SHIFT 0x14
++#define DC_GPIO_RXEN__DC_GPIO_DIGON_RXEN__SHIFT 0x15
++#define DC_GPIO_RXEN__DC_GPIO_ENA_BL_RXEN__SHIFT 0x16
++#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN_MASK 0x00000001L
++#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN_MASK 0x00000002L
++#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN_MASK 0x00000004L
++#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN_MASK 0x00000008L
++#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN_MASK 0x00000010L
++#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN_MASK 0x00000020L
++#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN_MASK 0x00000040L
++#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN_MASK 0x00000100L
++#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN_MASK 0x00000200L
++#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN_MASK 0x00000400L
++#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN_MASK 0x00000800L
++#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN_MASK 0x00001000L
++#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN_MASK 0x00002000L
++#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN_MASK 0x00004000L
++#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN_MASK 0x00008000L
++#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN_MASK 0x00010000L
++#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN_MASK 0x00020000L
++#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN_MASK 0x00040000L
++#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN_MASK 0x00080000L
++#define DC_GPIO_RXEN__DC_GPIO_BLON_RXEN_MASK 0x00100000L
++#define DC_GPIO_RXEN__DC_GPIO_DIGON_RXEN_MASK 0x00200000L
++#define DC_GPIO_RXEN__DC_GPIO_ENA_BL_RXEN_MASK 0x00400000L
++//BPHYC_DAC_MACRO_CNTL
++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL__SHIFT 0x0
++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL__SHIFT 0x8
++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT__SHIFT 0x10
++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR__SHIFT 0x18
++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON__SHIFT 0x1c
++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL_MASK 0x00000003L
++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL_MASK 0x00003F00L
++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT_MASK 0x003F0000L
++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR_MASK 0x0F000000L
++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON_MASK 0x10000000L
++//DAC_MACRO_CNTL_RESERVED0
++#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//BPHYC_DAC_AUTO_CALIB_CONTROL
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB__SHIFT 0x0
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN__SHIFT 0x1
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN__SHIFT 0x2
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST__SHIFT 0x4
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK__SHIFT 0x14
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE__SHIFT 0x1c
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB_MASK 0x00000001L
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN_MASK 0x00000002L
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN_MASK 0x00000004L
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST_MASK 0x00003FF0L
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK_MASK 0x00700000L
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE_MASK 0x10000000L
++//DAC_MACRO_CNTL_RESERVED1
++#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DAC_MACRO_CNTL_RESERVED2
++#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DAC_MACRO_CNTL_RESERVED3
++#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DISP_DSI_DUAL_CTRL
++#define DISP_DSI_DUAL_CTRL__DUAL_PIPE_MODE__SHIFT 0x0
++#define DISP_DSI_DUAL_CTRL__DUAL_PIPE_MODE_MASK 0x00000001L
++//DPHY_MACRO_CNTL_RESERVED0
++#define DPHY_MACRO_CNTL_RESERVED0__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED0__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED1
++#define DPHY_MACRO_CNTL_RESERVED1__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED1__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED2
++#define DPHY_MACRO_CNTL_RESERVED2__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED2__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED3
++#define DPHY_MACRO_CNTL_RESERVED3__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED3__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED4
++#define DPHY_MACRO_CNTL_RESERVED4__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED4__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED5
++#define DPHY_MACRO_CNTL_RESERVED5__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED5__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED6
++#define DPHY_MACRO_CNTL_RESERVED6__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED6__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED7
++#define DPHY_MACRO_CNTL_RESERVED7__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED7__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED8
++#define DPHY_MACRO_CNTL_RESERVED8__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED8__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED9
++#define DPHY_MACRO_CNTL_RESERVED9__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED9__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED10
++#define DPHY_MACRO_CNTL_RESERVED10__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED10__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED11
++#define DPHY_MACRO_CNTL_RESERVED11__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED11__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED12
++#define DPHY_MACRO_CNTL_RESERVED12__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED12__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED13
++#define DPHY_MACRO_CNTL_RESERVED13__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED13__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED14
++#define DPHY_MACRO_CNTL_RESERVED14__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED14__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED15
++#define DPHY_MACRO_CNTL_RESERVED15__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED15__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED16
++#define DPHY_MACRO_CNTL_RESERVED16__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED16__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED17
++#define DPHY_MACRO_CNTL_RESERVED17__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED17__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED18
++#define DPHY_MACRO_CNTL_RESERVED18__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED18__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED19
++#define DPHY_MACRO_CNTL_RESERVED19__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED19__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED20
++#define DPHY_MACRO_CNTL_RESERVED20__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED20__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED21
++#define DPHY_MACRO_CNTL_RESERVED21__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED21__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED22
++#define DPHY_MACRO_CNTL_RESERVED22__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED22__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED23
++#define DPHY_MACRO_CNTL_RESERVED23__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED23__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED24
++#define DPHY_MACRO_CNTL_RESERVED24__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED24__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED25
++#define DPHY_MACRO_CNTL_RESERVED25__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED25__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED26
++#define DPHY_MACRO_CNTL_RESERVED26__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED26__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED27
++#define DPHY_MACRO_CNTL_RESERVED27__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED27__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED28
++#define DPHY_MACRO_CNTL_RESERVED28__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED28__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED29
++#define DPHY_MACRO_CNTL_RESERVED29__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED29__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED30
++#define DPHY_MACRO_CNTL_RESERVED30__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED30__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED31
++#define DPHY_MACRO_CNTL_RESERVED31__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED31__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED32
++#define DPHY_MACRO_CNTL_RESERVED32__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED32__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED33
++#define DPHY_MACRO_CNTL_RESERVED33__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED33__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED34
++#define DPHY_MACRO_CNTL_RESERVED34__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED34__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED35
++#define DPHY_MACRO_CNTL_RESERVED35__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED35__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED36
++#define DPHY_MACRO_CNTL_RESERVED36__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED36__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED37
++#define DPHY_MACRO_CNTL_RESERVED37__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED37__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED38
++#define DPHY_MACRO_CNTL_RESERVED38__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED38__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED39
++#define DPHY_MACRO_CNTL_RESERVED39__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED39__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED40
++#define DPHY_MACRO_CNTL_RESERVED40__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED40__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED41
++#define DPHY_MACRO_CNTL_RESERVED41__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED41__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED42
++#define DPHY_MACRO_CNTL_RESERVED42__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED42__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED43
++#define DPHY_MACRO_CNTL_RESERVED43__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED43__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED44
++#define DPHY_MACRO_CNTL_RESERVED44__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED44__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED45
++#define DPHY_MACRO_CNTL_RESERVED45__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED45__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED46
++#define DPHY_MACRO_CNTL_RESERVED46__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED46__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED47
++#define DPHY_MACRO_CNTL_RESERVED47__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED47__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED48
++#define DPHY_MACRO_CNTL_RESERVED48__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED48__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED49
++#define DPHY_MACRO_CNTL_RESERVED49__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED49__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED50
++#define DPHY_MACRO_CNTL_RESERVED50__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED50__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED51
++#define DPHY_MACRO_CNTL_RESERVED51__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED51__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED52
++#define DPHY_MACRO_CNTL_RESERVED52__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED52__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED53
++#define DPHY_MACRO_CNTL_RESERVED53__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED53__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED54
++#define DPHY_MACRO_CNTL_RESERVED54__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED54__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED55
++#define DPHY_MACRO_CNTL_RESERVED55__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED55__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED56
++#define DPHY_MACRO_CNTL_RESERVED56__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED56__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED57
++#define DPHY_MACRO_CNTL_RESERVED57__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED57__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED58
++#define DPHY_MACRO_CNTL_RESERVED58__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED58__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED59
++#define DPHY_MACRO_CNTL_RESERVED59__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED59__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED60
++#define DPHY_MACRO_CNTL_RESERVED60__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED60__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED61
++#define DPHY_MACRO_CNTL_RESERVED61__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED61__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED62
++#define DPHY_MACRO_CNTL_RESERVED62__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED62__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPHY_MACRO_CNTL_RESERVED63
++#define DPHY_MACRO_CNTL_RESERVED63__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED63__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DPRX_AUX_REFERENCE_PULSE_DIV
++#define DPRX_AUX_REFERENCE_PULSE_DIV__DPRX_AUX_1_MICROSECOND_DIV__SHIFT 0x0
++#define DPRX_AUX_REFERENCE_PULSE_DIV__DPRX_AUX_1_MICROSECOND_SOURCE_SEL__SHIFT 0xf
++#define DPRX_AUX_REFERENCE_PULSE_DIV__DPRX_AUX_100_MICROSECOND_DIV__SHIFT 0x10
++#define DPRX_AUX_REFERENCE_PULSE_DIV__DPRX_AUX_1_MILLISECOND_DIV__SHIFT 0x18
++#define DPRX_AUX_REFERENCE_PULSE_DIV__DPRX_AUX_1_MICROSECOND_DIV_MASK 0x000003FFL
++#define DPRX_AUX_REFERENCE_PULSE_DIV__DPRX_AUX_1_MICROSECOND_SOURCE_SEL_MASK 0x00008000L
++#define DPRX_AUX_REFERENCE_PULSE_DIV__DPRX_AUX_100_MICROSECOND_DIV_MASK 0x00FF0000L
++#define DPRX_AUX_REFERENCE_PULSE_DIV__DPRX_AUX_1_MILLISECOND_DIV_MASK 0x3F000000L
++//DPRX_AUX_CONTROL
++#define DPRX_AUX_CONTROL__DPRX_AUX_EN__SHIFT 0x0
++#define DPRX_AUX_CONTROL__DPRX_AUX_REQUEST_TIMEOUT_LEN__SHIFT 0x8
++#define DPRX_AUX_CONTROL__DPRX_AUX_IMPCAL_REQ_EN__SHIFT 0x18
++#define DPRX_AUX_CONTROL__DPRX_AUX_TEST_MODE__SHIFT 0x1c
++#define DPRX_AUX_CONTROL__DPRX_AUX_DEGLITCH_EN__SHIFT 0x1d
++#define DPRX_AUX_CONTROL__DPRX_AUX_SPARE_0__SHIFT 0x1e
++#define DPRX_AUX_CONTROL__DPRX_AUX_SPARE_1__SHIFT 0x1f
++#define DPRX_AUX_CONTROL__DPRX_AUX_EN_MASK 0x00000001L
++#define DPRX_AUX_CONTROL__DPRX_AUX_REQUEST_TIMEOUT_LEN_MASK 0x0001FF00L
++#define DPRX_AUX_CONTROL__DPRX_AUX_IMPCAL_REQ_EN_MASK 0x01000000L
++#define DPRX_AUX_CONTROL__DPRX_AUX_TEST_MODE_MASK 0x10000000L
++#define DPRX_AUX_CONTROL__DPRX_AUX_DEGLITCH_EN_MASK 0x20000000L
++#define DPRX_AUX_CONTROL__DPRX_AUX_SPARE_0_MASK 0x40000000L
++#define DPRX_AUX_CONTROL__DPRX_AUX_SPARE_1_MASK 0x80000000L
++//DPRX_AUX_HPD_CONTROL1
++#define DPRX_AUX_HPD_CONTROL1__DPRX_AUX_HPD_IRQ_PULSE_WIDTH__SHIFT 0x0
++#define DPRX_AUX_HPD_CONTROL1__DPRX_AUX_HPD_IRQ_GAP__SHIFT 0x8
++#define DPRX_AUX_HPD_CONTROL1__DPRX_AUX_HPD_A__SHIFT 0x10
++#define DPRX_AUX_HPD_CONTROL1__DPRX_AUX_HPD_EN__SHIFT 0x11
++#define DPRX_AUX_HPD_CONTROL1__DPRX_AUX_HPD_IRQ_PULSE_WIDTH_MASK 0x0000000FL
++#define DPRX_AUX_HPD_CONTROL1__DPRX_AUX_HPD_IRQ_GAP_MASK 0x00003F00L
++#define DPRX_AUX_HPD_CONTROL1__DPRX_AUX_HPD_A_MASK 0x00010000L
++#define DPRX_AUX_HPD_CONTROL1__DPRX_AUX_HPD_EN_MASK 0x00020000L
++//DPRX_AUX_HPD_CONTROL2
++#define DPRX_AUX_HPD_CONTROL2__DPRX_AUX_HPD_IRQ_TRIGGER__SHIFT 0x0
++#define DPRX_AUX_HPD_CONTROL2__DPRX_AUX_NEW_HPD_IRQ_READY__SHIFT 0x1
++#define DPRX_AUX_HPD_CONTROL2__DPRX_AUX_HPD_IRQ_TRIGGER_MASK 0x00000001L
++#define DPRX_AUX_HPD_CONTROL2__DPRX_AUX_NEW_HPD_IRQ_READY_MASK 0x00000002L
++//DPRX_AUX_RX_STATUS
++#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_STATUS_CLEAR__SHIFT 0x0
++#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_DONE__SHIFT 0x7
++#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_OVERFLOW__SHIFT 0x8
++#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_TIMEOUT__SHIFT 0x9
++#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_PARTIAL_BYTE__SHIFT 0xa
++#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_MIN_COUNT_VIOL__SHIFT 0xc
++#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_INVALID_STOP__SHIFT 0xe
++#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_SYNC_INVALID_L__SHIFT 0x11
++#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_SYNC_INVALID_H__SHIFT 0x12
++#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_INVALID_START__SHIFT 0x13
++#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_RECV_NO_DET__SHIFT 0x14
++#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_RECV_INVALID_H__SHIFT 0x16
++#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_RECV_INVALID_L__SHIFT 0x17
++#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_BYTE_COUNT__SHIFT 0x18
++#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_STATUS_CLEAR_MASK 0x00000001L
++#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_DONE_MASK 0x00000080L
++#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_OVERFLOW_MASK 0x00000100L
++#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_TIMEOUT_MASK 0x00000200L
++#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_PARTIAL_BYTE_MASK 0x00000400L
++#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_MIN_COUNT_VIOL_MASK 0x00001000L
++#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_INVALID_STOP_MASK 0x00004000L
++#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_SYNC_INVALID_L_MASK 0x00020000L
++#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_SYNC_INVALID_H_MASK 0x00040000L
++#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_INVALID_START_MASK 0x00080000L
++#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_RECV_NO_DET_MASK 0x00100000L
++#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_RECV_INVALID_H_MASK 0x00400000L
++#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_RECV_INVALID_L_MASK 0x00800000L
++#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_BYTE_COUNT_MASK 0x1F000000L
++//DPRX_AUX_RX_ERROR_MASK
++#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_OVERFLOW_MASK__SHIFT 0x8
++#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_TIMEOUT_MASK__SHIFT 0x9
++#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_PARTIAL_BYTE_MASK__SHIFT 0xa
++#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_MIN_COUNT_VIOL_MASK__SHIFT 0xc
++#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_INVALID_STOP_MASK__SHIFT 0xe
++#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_SYNC_INVALID_L_MASK__SHIFT 0x11
++#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_SYNC_INVALID_H_MASK__SHIFT 0x12
++#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_INVALID_START_MASK__SHIFT 0x13
++#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_RECV_NO_DET_MASK__SHIFT 0x14
++#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_RECV_INVALID_H_MASK__SHIFT 0x16
++#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_RECV_INVALID_L_MASK__SHIFT 0x17
++#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_OVERFLOW_MASK_MASK 0x00000100L
++#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_TIMEOUT_MASK_MASK 0x00000200L
++#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_PARTIAL_BYTE_MASK_MASK 0x00000400L
++#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_MIN_COUNT_VIOL_MASK_MASK 0x00001000L
++#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_INVALID_STOP_MASK_MASK 0x00004000L
++#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_SYNC_INVALID_L_MASK_MASK 0x00020000L
++#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_SYNC_INVALID_H_MASK_MASK 0x00040000L
++#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_INVALID_START_MASK_MASK 0x00080000L
++#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_RECV_NO_DET_MASK_MASK 0x00100000L
++#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_RECV_INVALID_H_MASK_MASK 0x00400000L
++#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_RECV_INVALID_L_MASK_MASK 0x00800000L
++//DPRX_AUX_DPHY_TX_REF_CONTROL
++#define DPRX_AUX_DPHY_TX_REF_CONTROL__DPRX_AUX_TX_REF_SEL__SHIFT 0x0
++#define DPRX_AUX_DPHY_TX_REF_CONTROL__DPRX_AUX_TX_RATE__SHIFT 0x4
++#define DPRX_AUX_DPHY_TX_REF_CONTROL__DPRX_AUX_TX_REF_DIV__SHIFT 0x10
++#define DPRX_AUX_DPHY_TX_REF_CONTROL__DPRX_AUX_TX_REF_SEL_MASK 0x00000001L
++#define DPRX_AUX_DPHY_TX_REF_CONTROL__DPRX_AUX_TX_RATE_MASK 0x00000030L
++#define DPRX_AUX_DPHY_TX_REF_CONTROL__DPRX_AUX_TX_REF_DIV_MASK 0x01FF0000L
++//DPRX_AUX_DPHY_TX_CONTROL
++#define DPRX_AUX_DPHY_TX_CONTROL__DPRX_AUX_TX_PRECHARGE_LEN__SHIFT 0x0
++#define DPRX_AUX_DPHY_TX_CONTROL__DPRX_AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8
++#define DPRX_AUX_DPHY_TX_CONTROL__DPRX_AUX_TX_PRECHARGE_LEN_MASK 0x00000007L
++#define DPRX_AUX_DPHY_TX_CONTROL__DPRX_AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L
++//DPRX_AUX_DPHY_RX_CONTROL0
++#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_START_WINDOW__SHIFT 0x4
++#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_RECEIVE_WINDOW__SHIFT 0x8
++#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc
++#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10
++#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11
++#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12
++#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13
++#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14
++#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c
++#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_START_WINDOW_MASK 0x00000070L
++#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L
++#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L
++#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L
++#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L
++#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L
++#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L
++#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L
++#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L
++//DPRX_AUX_DPHY_RX_CONTROL1
++#define DPRX_AUX_DPHY_RX_CONTROL1__DPRX_AUX_RX_PRECHARGE_SKIP__SHIFT 0x0
++#define DPRX_AUX_DPHY_RX_CONTROL1__DPRX_AUX_RX_TIMEOUT_LEN__SHIFT 0x8
++#define DPRX_AUX_DPHY_RX_CONTROL1__DPRX_AUX_RX_TIMEOUT_COUNTER_START__SHIFT 0x18
++#define DPRX_AUX_DPHY_RX_CONTROL1__DPRX_AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL
++#define DPRX_AUX_DPHY_RX_CONTROL1__DPRX_AUX_RX_TIMEOUT_LEN_MASK 0x0001FF00L
++#define DPRX_AUX_DPHY_RX_CONTROL1__DPRX_AUX_RX_TIMEOUT_COUNTER_START_MASK 0x1F000000L
++//DPRX_AUX_DPHY_TX_STATUS
++#define DPRX_AUX_DPHY_TX_STATUS__DPRX_AUX_TX_ACTIVE__SHIFT 0x0
++#define DPRX_AUX_DPHY_TX_STATUS__DPRX_AUX_TX_STATE__SHIFT 0x4
++#define DPRX_AUX_DPHY_TX_STATUS__DPRX_AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10
++#define DPRX_AUX_DPHY_TX_STATUS__DPRX_AUX_TX_ACTIVE_MASK 0x00000001L
++#define DPRX_AUX_DPHY_TX_STATUS__DPRX_AUX_TX_STATE_MASK 0x000000F0L
++#define DPRX_AUX_DPHY_TX_STATUS__DPRX_AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L
++//DPRX_AUX_DPHY_RX_STATUS
++#define DPRX_AUX_DPHY_RX_STATUS__DPRX_AUX_RX_STATE__SHIFT 0x0
++#define DPRX_AUX_DPHY_RX_STATUS__DPRX_AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8
++#define DPRX_AUX_DPHY_RX_STATUS__DPRX_AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10
++#define DPRX_AUX_DPHY_RX_STATUS__DPRX_AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15
++#define DPRX_AUX_DPHY_RX_STATUS__DPRX_AUX_RX_STATE_MASK 0x00000007L
++#define DPRX_AUX_DPHY_RX_STATUS__DPRX_AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L
++#define DPRX_AUX_DPHY_RX_STATUS__DPRX_AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L
++#define DPRX_AUX_DPHY_RX_STATUS__DPRX_AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L
++//DPRX_AUX_DMCU_HW_INT_STATUS
++#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_AUX_INT_STATUS__SHIFT 0x0
++#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_I2C_INT_STATUS__SHIFT 0x1
++#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG1_TIMEOUT_INT_STATUS__SHIFT 0x2
++#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG2_TIMEOUT_INT_STATUS__SHIFT 0x3
++#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG3_TIMEOUT_INT_STATUS__SHIFT 0x4
++#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG4_TIMEOUT_INT_STATUS__SHIFT 0x5
++#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_AUX_INT_MASK__SHIFT 0x8
++#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_I2C_INT_MASK__SHIFT 0x9
++#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG1_TIMEOUT_INT_MASK__SHIFT 0xa
++#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG2_TIMEOUT_INT_MASK__SHIFT 0xb
++#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG3_TIMEOUT_INT_MASK__SHIFT 0xc
++#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG4_TIMEOUT_INT_MASK__SHIFT 0xd
++#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_AUX_EVENT_OCCURRED__SHIFT 0x10
++#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_I2C_EVENT_OCCURRED__SHIFT 0x11
++#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG1_TIMEOUT_EVENT_OCCURRED__SHIFT 0x12
++#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG2_TIMEOUT_EVENT_OCCURRED__SHIFT 0x13
++#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG3_TIMEOUT_EVENT_OCCURRED__SHIFT 0x14
++#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG4_TIMEOUT_EVENT_OCCURRED__SHIFT 0x15
++#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_AUX_INT_STATUS_MASK 0x00000001L
++#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_I2C_INT_STATUS_MASK 0x00000002L
++#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG1_TIMEOUT_INT_STATUS_MASK 0x00000004L
++#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG2_TIMEOUT_INT_STATUS_MASK 0x00000008L
++#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG3_TIMEOUT_INT_STATUS_MASK 0x00000010L
++#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG4_TIMEOUT_INT_STATUS_MASK 0x00000020L
++#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_AUX_INT_MASK_MASK 0x00000100L
++#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_I2C_INT_MASK_MASK 0x00000200L
++#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG1_TIMEOUT_INT_MASK_MASK 0x00000400L
++#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG2_TIMEOUT_INT_MASK_MASK 0x00000800L
++#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG3_TIMEOUT_INT_MASK_MASK 0x00001000L
++#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG4_TIMEOUT_INT_MASK_MASK 0x00002000L
++#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_AUX_EVENT_OCCURRED_MASK 0x00010000L
++#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_I2C_EVENT_OCCURRED_MASK 0x00020000L
++#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG1_TIMEOUT_EVENT_OCCURRED_MASK 0x00040000L
++#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG2_TIMEOUT_EVENT_OCCURRED_MASK 0x00080000L
++#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG3_TIMEOUT_EVENT_OCCURRED_MASK 0x00100000L
++#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG4_TIMEOUT_EVENT_OCCURRED_MASK 0x00200000L
++//DPRX_AUX_DMCU_HW_INT_ACK
++#define DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_AUX_INT_ACK__SHIFT 0x0
++#define DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_I2C_INT_ACK__SHIFT 0x1
++#define DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_MSG1_TIMEOUT_INT_ACK__SHIFT 0x2
++#define DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_MSG2_TIMEOUT_INT_ACK__SHIFT 0x3
++#define DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_MSG3_TIMEOUT_INT_ACK__SHIFT 0x4
++#define DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_MSG4_TIMEOUT_INT_ACK__SHIFT 0x5
++#define DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_AUX_INT_ACK_MASK 0x00000001L
++#define DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_I2C_INT_ACK_MASK 0x00000002L
++#define DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_MSG1_TIMEOUT_INT_ACK_MASK 0x00000004L
++#define DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_MSG2_TIMEOUT_INT_ACK_MASK 0x00000008L
++#define DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_MSG3_TIMEOUT_INT_ACK_MASK 0x00000010L
++#define DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_MSG4_TIMEOUT_INT_ACK_MASK 0x00000020L
++//DPRX_AUX_CPU_TO_DMCU_INTERRUPT1
++#define DPRX_AUX_CPU_TO_DMCU_INTERRUPT1__DPRX_AUX_CPU_TO_DMCU_INT_TRIGGER__SHIFT 0x0
++#define DPRX_AUX_CPU_TO_DMCU_INTERRUPT1__DPRX_AUX_CPU_TO_DMCU_INT_TRIGGER_MASK 0x00000001L
++//DPRX_AUX_CPU_TO_DMCU_INTERRUPT2
++#define DPRX_AUX_CPU_TO_DMCU_INTERRUPT2__DPRX_AUX_CPU_TO_DMCU_INT_MASK__SHIFT 0x0
++#define DPRX_AUX_CPU_TO_DMCU_INTERRUPT2__DPRX_AUX_CPU_TO_DMCU_INT_ACK__SHIFT 0x8
++#define DPRX_AUX_CPU_TO_DMCU_INTERRUPT2__DPRX_AUX_CPU_TO_DMCU_INT_STATUS__SHIFT 0x10
++#define DPRX_AUX_CPU_TO_DMCU_INTERRUPT2__DPRX_AUX_CPU_TO_DMCU_INT_MASK_MASK 0x00000001L
++#define DPRX_AUX_CPU_TO_DMCU_INTERRUPT2__DPRX_AUX_CPU_TO_DMCU_INT_ACK_MASK 0x00000100L
++#define DPRX_AUX_CPU_TO_DMCU_INTERRUPT2__DPRX_AUX_CPU_TO_DMCU_INT_STATUS_MASK 0x00010000L
++//DPRX_AUX_DMCU_TO_CPU_INTERRUPT1
++#define DPRX_AUX_DMCU_TO_CPU_INTERRUPT1__DPRX_AUX_DMCU_TO_CPU_INT_TRIGGER__SHIFT 0x0
++#define DPRX_AUX_DMCU_TO_CPU_INTERRUPT1__DPRX_AUX_DMCU_TO_CPU_INT_TRIGGER_MASK 0x00000001L
++//DPRX_AUX_DMCU_TO_CPU_INTERRUPT2
++#define DPRX_AUX_DMCU_TO_CPU_INTERRUPT2__DPRX_AUX_DMCU_TO_CPU_INT_MASK__SHIFT 0x0
++#define DPRX_AUX_DMCU_TO_CPU_INTERRUPT2__DPRX_AUX_DMCU_TO_CPU_INT_TYPE__SHIFT 0x1
++#define DPRX_AUX_DMCU_TO_CPU_INTERRUPT2__DPRX_AUX_DMCU_TO_CPU_INT_ACK__SHIFT 0x8
++#define DPRX_AUX_DMCU_TO_CPU_INTERRUPT2__DPRX_AUX_DMCU_TO_CPU_INT_OCCURRED__SHIFT 0x10
++#define DPRX_AUX_DMCU_TO_CPU_INTERRUPT2__DPRX_AUX_DMCU_TO_CPU_INT_MASK_MASK 0x00000001L
++#define DPRX_AUX_DMCU_TO_CPU_INTERRUPT2__DPRX_AUX_DMCU_TO_CPU_INT_TYPE_MASK 0x00000002L
++#define DPRX_AUX_DMCU_TO_CPU_INTERRUPT2__DPRX_AUX_DMCU_TO_CPU_INT_ACK_MASK 0x00000100L
++#define DPRX_AUX_DMCU_TO_CPU_INTERRUPT2__DPRX_AUX_DMCU_TO_CPU_INT_OCCURRED_MASK 0x00010000L
++//DPRX_AUX_AUX_BUF_INDEX
++#define DPRX_AUX_AUX_BUF_INDEX__DPRX_AUX_AUX_BUF_INDEX__SHIFT 0x0
++#define DPRX_AUX_AUX_BUF_INDEX__DPRX_AUX_AUX_BUF_INDEX_MASK 0x0000007FL
++//DPRX_AUX_AUX_BUF_DATA
++#define DPRX_AUX_AUX_BUF_DATA__DPRX_AUX_AUX_BUF_DATA__SHIFT 0x0
++#define DPRX_AUX_AUX_BUF_DATA__DPRX_AUX_AUX_BUF_DATA_MASK 0xFFFFFFFFL
++//DPRX_AUX_EDID_INDEX
++#define DPRX_AUX_EDID_INDEX__DPRX_AUX_EDID_INDEX__SHIFT 0x0
++#define DPRX_AUX_EDID_INDEX__DPRX_AUX_EDID_MODE__SHIFT 0x10
++#define DPRX_AUX_EDID_INDEX__DPRX_AUX_EDID_INDEX_MASK 0x000003FFL
++#define DPRX_AUX_EDID_INDEX__DPRX_AUX_EDID_MODE_MASK 0x00010000L
++//DPRX_AUX_EDID_DATA
++#define DPRX_AUX_EDID_DATA__DPRX_AUX_EDID_DATA__SHIFT 0x0
++#define DPRX_AUX_EDID_DATA__DPRX_AUX_EDID_DATA_MASK 0xFFFFFFFFL
++//DPRX_AUX_DPCD_INDEX1
++#define DPRX_AUX_DPCD_INDEX1__DPRX_AUX_DPCD_INDEX1__SHIFT 0x0
++#define DPRX_AUX_DPCD_INDEX1__DPRX_AUX_DPCD_MODE1__SHIFT 0x10
++#define DPRX_AUX_DPCD_INDEX1__DPRX_AUX_DPCD_INDEX1_MASK 0x000007FFL
++#define DPRX_AUX_DPCD_INDEX1__DPRX_AUX_DPCD_MODE1_MASK 0x00010000L
++//DPRX_AUX_DPCD_DATA1
++#define DPRX_AUX_DPCD_DATA1__DPRX_AUX_DPCD_DATA1__SHIFT 0x0
++#define DPRX_AUX_DPCD_DATA1__DPRX_AUX_DPCD_DATA1_MASK 0xFFFFFFFFL
++//DPRX_AUX_DPCD_INDEX2
++#define DPRX_AUX_DPCD_INDEX2__DPRX_AUX_DPCD_INDEX2__SHIFT 0x0
++#define DPRX_AUX_DPCD_INDEX2__DPRX_AUX_DPCD_MODE2__SHIFT 0x10
++#define DPRX_AUX_DPCD_INDEX2__DPRX_AUX_DPCD_INDEX2_MASK 0x000007FFL
++#define DPRX_AUX_DPCD_INDEX2__DPRX_AUX_DPCD_MODE2_MASK 0x00010000L
++//DPRX_AUX_DPCD_DATA2
++#define DPRX_AUX_DPCD_DATA2__DPRX_AUX_DPCD_DATA2__SHIFT 0x0
++#define DPRX_AUX_DPCD_DATA2__DPRX_AUX_DPCD_DATA2_MASK 0xFFFFFFFFL
++//DPRX_AUX_MSG_INDEX1
++#define DPRX_AUX_MSG_INDEX1__DPRX_AUX_MSG_INDEX1__SHIFT 0x0
++#define DPRX_AUX_MSG_INDEX1__DPRX_AUX_MSG_MODE1__SHIFT 0x10
++#define DPRX_AUX_MSG_INDEX1__DPRX_AUX_MSG_INDEX1_MASK 0x000003FFL
++#define DPRX_AUX_MSG_INDEX1__DPRX_AUX_MSG_MODE1_MASK 0x00010000L
++//DPRX_AUX_MSG_DATA1
++#define DPRX_AUX_MSG_DATA1__DPRX_AUX_MSG_DATA1__SHIFT 0x0
++#define DPRX_AUX_MSG_DATA1__DPRX_AUX_MSG_DATA1_MASK 0xFFFFFFFFL
++//DPRX_AUX_MSG_INDEX2
++#define DPRX_AUX_MSG_INDEX2__DPRX_AUX_MSG_INDEX2__SHIFT 0x0
++#define DPRX_AUX_MSG_INDEX2__DPRX_AUX_MSG_MODE2__SHIFT 0x10
++#define DPRX_AUX_MSG_INDEX2__DPRX_AUX_MSG_INDEX2_MASK 0x000003FFL
++#define DPRX_AUX_MSG_INDEX2__DPRX_AUX_MSG_MODE2_MASK 0x00010000L
++//DPRX_AUX_MSG_DATA2
++#define DPRX_AUX_MSG_DATA2__DPRX_AUX_MSG_DATA2__SHIFT 0x0
++#define DPRX_AUX_MSG_DATA2__DPRX_AUX_MSG_DATA2_MASK 0xFFFFFFFFL
++//DPRX_AUX_KSV_INDEX1
++#define DPRX_AUX_KSV_INDEX1__DPRX_AUX_KSV_INDEX1__SHIFT 0x0
++#define DPRX_AUX_KSV_INDEX1__DPRX_AUX_KSV_MODE1__SHIFT 0x10
++#define DPRX_AUX_KSV_INDEX1__DPRX_AUX_KSV_INDEX1_MASK 0x000003FFL
++#define DPRX_AUX_KSV_INDEX1__DPRX_AUX_KSV_MODE1_MASK 0x00010000L
++//DPRX_AUX_KSV_DATA1
++#define DPRX_AUX_KSV_DATA1__DPRX_AUX_KSV_DATA1__SHIFT 0x0
++#define DPRX_AUX_KSV_DATA1__DPRX_AUX_KSV_DATA1_MASK 0xFFFFFFFFL
++//DPRX_AUX_KSV_INDEX2
++#define DPRX_AUX_KSV_INDEX2__DPRX_AUX_KSV_INDEX2__SHIFT 0x0
++#define DPRX_AUX_KSV_INDEX2__DPRX_AUX_KSV_MODE2__SHIFT 0x10
++#define DPRX_AUX_KSV_INDEX2__DPRX_AUX_KSV_INDEX2_MASK 0x000003FFL
++#define DPRX_AUX_KSV_INDEX2__DPRX_AUX_KSV_MODE2_MASK 0x00010000L
++//DPRX_AUX_KSV_DATA2
++#define DPRX_AUX_KSV_DATA2__DPRX_AUX_KSV_DATA2__SHIFT 0x0
++#define DPRX_AUX_KSV_DATA2__DPRX_AUX_KSV_DATA2_MASK 0xFFFFFFFFL
++//DPRX_AUX_MSG_TIMEOUT_CONTROL
++#define DPRX_AUX_MSG_TIMEOUT_CONTROL__DPRX_AUX_MSG_TIMEOUT_LEN__SHIFT 0x0
++#define DPRX_AUX_MSG_TIMEOUT_CONTROL__DPRX_AUX_MSG_TIMEOUT_LEN_MASK 0x000000FFL
++//DPRX_AUX_MSG_BUF_CONTROL1
++#define DPRX_AUX_MSG_BUF_CONTROL1__DPRX_AUX_MSG_REP_WRITE_REQ1__SHIFT 0x0
++#define DPRX_AUX_MSG_BUF_CONTROL1__DPRX_AUX_MSG_REP_WRITE_GNT1__SHIFT 0x1
++#define DPRX_AUX_MSG_BUF_CONTROL1__DPRX_AUX_MSG_REP_WRITE_REQ1_MASK 0x00000001L
++#define DPRX_AUX_MSG_BUF_CONTROL1__DPRX_AUX_MSG_REP_WRITE_GNT1_MASK 0x00000002L
++//DPRX_AUX_MSG_BUF_CONTROL2
++#define DPRX_AUX_MSG_BUF_CONTROL2__DPRX_AUX_MSG_REP_WRITE_REQ2__SHIFT 0x0
++#define DPRX_AUX_MSG_BUF_CONTROL2__DPRX_AUX_MSG_REP_WRITE_GNT2__SHIFT 0x1
++#define DPRX_AUX_MSG_BUF_CONTROL2__DPRX_AUX_MSG_REP_WRITE_REQ2_MASK 0x00000001L
++#define DPRX_AUX_MSG_BUF_CONTROL2__DPRX_AUX_MSG_REP_WRITE_GNT2_MASK 0x00000002L
++//DPRX_AUX_SCRATCH1
++#define DPRX_AUX_SCRATCH1__DPRX_AUX_SCRATCH1__SHIFT 0x0
++#define DPRX_AUX_SCRATCH1__DPRX_AUX_SCRATCH1_MASK 0xFFFFFFFFL
++//DPRX_AUX_SCRATCH2
++#define DPRX_AUX_SCRATCH2__DPRX_AUX_SCRATCH2__SHIFT 0x0
++#define DPRX_AUX_SCRATCH2__DPRX_AUX_SCRATCH2_MASK 0xFFFFFFFFL
++//DPRX_AUX_MSG1_PENDING
++#define DPRX_AUX_MSG1_PENDING__DPRX_AUX_MSG1_PENDING__SHIFT 0x0
++#define DPRX_AUX_MSG1_PENDING__DPRX_AUX_MSG1_PENDING_MASK 0x00000001L
++//DPRX_AUX_MSG2_PENDING
++#define DPRX_AUX_MSG2_PENDING__DPRX_AUX_MSG2_PENDING__SHIFT 0x0
++#define DPRX_AUX_MSG2_PENDING__DPRX_AUX_MSG2_PENDING_MASK 0x00000001L
++//DPRX_AUX_MSG3_PENDING
++#define DPRX_AUX_MSG3_PENDING__DPRX_AUX_MSG3_PENDING__SHIFT 0x0
++#define DPRX_AUX_MSG3_PENDING__DPRX_AUX_MSG3_PENDING_MASK 0x00000001L
++//DPRX_AUX_MSG4_PENDING
++#define DPRX_AUX_MSG4_PENDING__DPRX_AUX_MSG4_PENDING__SHIFT 0x0
++#define DPRX_AUX_MSG4_PENDING__DPRX_AUX_MSG4_PENDING_MASK 0x00000001L
++//DPRX_DPHY_DPCD_LANE_COUNT_SET
++#define DPRX_DPHY_DPCD_LANE_COUNT_SET__LANE_COUNT_SET__SHIFT 0x0
++#define DPRX_DPHY_DPCD_LANE_COUNT_SET__LANE_COUNT_SET_MASK 0x0000001FL
++//DPRX_DPHY_DPCD_TRAINING_PATTERN_SET
++#define DPRX_DPHY_DPCD_TRAINING_PATTERN_SET__TRAINING_PATTERN_SET__SHIFT 0x0
++#define DPRX_DPHY_DPCD_TRAINING_PATTERN_SET__TRAINING_PATTERN_SET_MASK 0x00000003L
++//DPRX_DPHY_DPCD_MSTM_CTRL
++#define DPRX_DPHY_DPCD_MSTM_CTRL__MST_EN__SHIFT 0x0
++#define DPRX_DPHY_DPCD_MSTM_CTRL__MST_EN_MASK 0x00000001L
++//DPRX_DPHY_DPCD_LINK_QUAL_LANE0_SET
++#define DPRX_DPHY_DPCD_LINK_QUAL_LANE0_SET__LANE0_LINK_QUAL_PATTERN_SET__SHIFT 0x0
++#define DPRX_DPHY_DPCD_LINK_QUAL_LANE0_SET__LANE0_LINK_QUAL_PATTERN_SET_MASK 0x00000007L
++//DPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS
++#define DPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS__LANE0_LINK_QUAL_PATTERN_DETECT__SHIFT 0x0
++#define DPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS__LANE0_HBR2_COMPL_EYE_PATTERN_DETECT__SHIFT 0x3
++#define DPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS__LANE0_LINK_QUAL_PATTERN_DETECT_MASK 0x00000007L
++#define DPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS__LANE0_HBR2_COMPL_EYE_PATTERN_DETECT_MASK 0x00000018L
++//DPRX_DPHY_DPCD_LINK_QUAL_LANE1_SET
++#define DPRX_DPHY_DPCD_LINK_QUAL_LANE1_SET__LANE1_LINK_QUAL_PATTERN_SET__SHIFT 0x0
++#define DPRX_DPHY_DPCD_LINK_QUAL_LANE1_SET__LANE1_LINK_QUAL_PATTERN_SET_MASK 0x00000007L
++//DPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS
++#define DPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS__LANE1_LINK_QUAL_PATTERN_DETECT__SHIFT 0x0
++#define DPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS__LANE1_HBR2_COMPL_EYE_PATTERN_DETECT__SHIFT 0x3
++#define DPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS__LANE1_LINK_QUAL_PATTERN_DETECT_MASK 0x00000007L
++#define DPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS__LANE1_HBR2_COMPL_EYE_PATTERN_DETECT_MASK 0x00000018L
++//DPRX_DPHY_DPCD_LINK_QUAL_LANE2_SET
++#define DPRX_DPHY_DPCD_LINK_QUAL_LANE2_SET__LANE2_LINK_QUAL_PATTERN_SET__SHIFT 0x0
++#define DPRX_DPHY_DPCD_LINK_QUAL_LANE2_SET__LANE2_LINK_QUAL_PATTERN_SET_MASK 0x00000007L
++//DPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS
++#define DPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS__LANE2_LINK_QUAL_PATTERN_DETECT__SHIFT 0x0
++#define DPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS__LANE2_HBR2_COMPL_EYE_PATTERN_DETECT__SHIFT 0x3
++#define DPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS__LANE2_LINK_QUAL_PATTERN_DETECT_MASK 0x00000007L
++#define DPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS__LANE2_HBR2_COMPL_EYE_PATTERN_DETECT_MASK 0x00000018L
++//DPRX_DPHY_DPCD_LINK_QUAL_LANE3_SET
++#define DPRX_DPHY_DPCD_LINK_QUAL_LANE3_SET__LANE3_LINK_QUAL_PATTERN_SET__SHIFT 0x0
++#define DPRX_DPHY_DPCD_LINK_QUAL_LANE3_SET__LANE3_LINK_QUAL_PATTERN_SET_MASK 0x00000007L
++//DPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS
++#define DPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS__LANE3_LINK_QUAL_PATTERN_DETECT__SHIFT 0x0
++#define DPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS__LANE3_HBR2_COMPL_EYE_PATTERN_DETECT__SHIFT 0x3
++#define DPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS__LANE3_LINK_QUAL_PATTERN_DETECT_MASK 0x00000007L
++#define DPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS__LANE3_HBR2_COMPL_EYE_PATTERN_DETECT_MASK 0x00000018L
++//DPRX_DPHY_READY
++#define DPRX_DPHY_READY__CP_READY__SHIFT 0x0
++#define DPRX_DPHY_READY__ACT_READY__SHIFT 0x1
++#define DPRX_DPHY_READY__SDOUT_READY__SHIFT 0x2
++#define DPRX_DPHY_READY__ACT_READY_CLR__SHIFT 0x3
++#define DPRX_DPHY_READY__MVOTE_DATA_ERROR__SHIFT 0x4
++#define DPRX_DPHY_READY__MVOTE_DATA_ERROR_CLR__SHIFT 0x5
++#define DPRX_DPHY_READY__MVOTE_KCODE_ERROR__SHIFT 0x6
++#define DPRX_DPHY_READY__MVOTE_KCODE_ERROR_CLR__SHIFT 0x7
++#define DPRX_DPHY_READY__CP_READY_MASK 0x00000001L
++#define DPRX_DPHY_READY__ACT_READY_MASK 0x00000002L
++#define DPRX_DPHY_READY__SDOUT_READY_MASK 0x00000004L
++#define DPRX_DPHY_READY__ACT_READY_CLR_MASK 0x00000008L
++#define DPRX_DPHY_READY__MVOTE_DATA_ERROR_MASK 0x00000010L
++#define DPRX_DPHY_READY__MVOTE_DATA_ERROR_CLR_MASK 0x00000020L
++#define DPRX_DPHY_READY__MVOTE_KCODE_ERROR_MASK 0x00000040L
++#define DPRX_DPHY_READY__MVOTE_KCODE_ERROR_CLR_MASK 0x00000080L
++//DPRX_DPHY_COMMA_STATUS
++#define DPRX_DPHY_COMMA_STATUS__LANE0_COMMA_LOCKED__SHIFT 0x0
++#define DPRX_DPHY_COMMA_STATUS__LANE1_COMMA_LOCKED__SHIFT 0x1
++#define DPRX_DPHY_COMMA_STATUS__LANE2_COMMA_LOCKED__SHIFT 0x2
++#define DPRX_DPHY_COMMA_STATUS__LANE3_COMMA_LOCKED__SHIFT 0x3
++#define DPRX_DPHY_COMMA_STATUS__LANE0_SR_LOCKED__SHIFT 0x4
++#define DPRX_DPHY_COMMA_STATUS__LANE1_SR_LOCKED__SHIFT 0x5
++#define DPRX_DPHY_COMMA_STATUS__LANE2_SR_LOCKED__SHIFT 0x6
++#define DPRX_DPHY_COMMA_STATUS__LANE3_SR_LOCKED__SHIFT 0x7
++#define DPRX_DPHY_COMMA_STATUS__LANE0_COMMA_LOCKED_MASK 0x00000001L
++#define DPRX_DPHY_COMMA_STATUS__LANE1_COMMA_LOCKED_MASK 0x00000002L
++#define DPRX_DPHY_COMMA_STATUS__LANE2_COMMA_LOCKED_MASK 0x00000004L
++#define DPRX_DPHY_COMMA_STATUS__LANE3_COMMA_LOCKED_MASK 0x00000008L
++#define DPRX_DPHY_COMMA_STATUS__LANE0_SR_LOCKED_MASK 0x00000010L
++#define DPRX_DPHY_COMMA_STATUS__LANE1_SR_LOCKED_MASK 0x00000020L
++#define DPRX_DPHY_COMMA_STATUS__LANE2_SR_LOCKED_MASK 0x00000040L
++#define DPRX_DPHY_COMMA_STATUS__LANE3_SR_LOCKED_MASK 0x00000080L
++//DPRX_DPHY_LANE_ALIGN_ERROR_STATUS_UPDATED
++#define DPRX_DPHY_LANE_ALIGN_ERROR_STATUS_UPDATED__LANE0_INTERLANE_ALIGN_ERROR_COUNT__SHIFT 0x0
++#define DPRX_DPHY_LANE_ALIGN_ERROR_STATUS_UPDATED__LANE0_INTERLANE_ALIGN_ERROR_COUNT_MASK 0x0000000FL
++//DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED
++#define DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED__INTERLANE_ALIGN_DONE__SHIFT 0x0
++#define DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED__INTERLANE_ALIGN_CHECK_DONE__SHIFT 0x1
++#define DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED__INTERLANE_ALIGN_FIFO_LEVEL__SHIFT 0x2
++#define DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED__INTERLANE_ALIGN_STATE__SHIFT 0x19
++#define DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED__INTERLANE_ALIGN_WAIT_COUNT__SHIFT 0x1b
++#define DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED__INTERLANE_ALIGN_DONE_MASK 0x00000001L
++#define DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED__INTERLANE_ALIGN_CHECK_DONE_MASK 0x00000002L
++#define DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED__INTERLANE_ALIGN_FIFO_LEVEL_MASK 0x0003FFFCL
++#define DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED__INTERLANE_ALIGN_STATE_MASK 0x06000000L
++#define DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED__INTERLANE_ALIGN_WAIT_COUNT_MASK 0xF8000000L
++//DPRX_DPHY_ERROR_THRESH_A_LANE0
++#define DPRX_DPHY_ERROR_THRESH_A_LANE0__LANE0_SYMBOL_ERROR_COUNT_THRESH__SHIFT 0x0
++#define DPRX_DPHY_ERROR_THRESH_A_LANE0__LANE0_DISPARITY_ERROR_COUNT_THRESH__SHIFT 0x8
++#define DPRX_DPHY_ERROR_THRESH_A_LANE0__LANE0_TEST_PATTERN_ERROR_THRESH__SHIFT 0x18
++#define DPRX_DPHY_ERROR_THRESH_A_LANE0__LANE0_SYMBOL_ERROR_COUNT_THRESH_MASK 0x000000FFL
++#define DPRX_DPHY_ERROR_THRESH_A_LANE0__LANE0_DISPARITY_ERROR_COUNT_THRESH_MASK 0x0000FF00L
++#define DPRX_DPHY_ERROR_THRESH_A_LANE0__LANE0_TEST_PATTERN_ERROR_THRESH_MASK 0xFF000000L
++//DPRX_DPHY_ERROR_COUNT_A_LANE0
++#define DPRX_DPHY_ERROR_COUNT_A_LANE0__LANE0_SYMBOL_ERROR_COUNT__SHIFT 0x0
++#define DPRX_DPHY_ERROR_COUNT_A_LANE0__LANE0_SYMBOL_ERROR_COUNT_VALID__SHIFT 0xf
++#define DPRX_DPHY_ERROR_COUNT_A_LANE0__LANE0_DISPARITY_ERROR_COUNT__SHIFT 0x10
++#define DPRX_DPHY_ERROR_COUNT_A_LANE0__LANE0_DISPARITY_ERROR_COUNT_VALID__SHIFT 0x1f
++#define DPRX_DPHY_ERROR_COUNT_A_LANE0__LANE0_SYMBOL_ERROR_COUNT_MASK 0x00007FFFL
++#define DPRX_DPHY_ERROR_COUNT_A_LANE0__LANE0_SYMBOL_ERROR_COUNT_VALID_MASK 0x00008000L
++#define DPRX_DPHY_ERROR_COUNT_A_LANE0__LANE0_DISPARITY_ERROR_COUNT_MASK 0x7FFF0000L
++#define DPRX_DPHY_ERROR_COUNT_A_LANE0__LANE0_DISPARITY_ERROR_COUNT_VALID_MASK 0x80000000L
++//DPRX_DPHY_ERROR_COUNT_B_LANE0
++#define DPRX_DPHY_ERROR_COUNT_B_LANE0__LANE0_TEST_PATTERN_ERROR_COUNT__SHIFT 0x10
++#define DPRX_DPHY_ERROR_COUNT_B_LANE0__LANE0_TEST_PATTERN_ERROR_COUNT_VALID__SHIFT 0x1f
++#define DPRX_DPHY_ERROR_COUNT_B_LANE0__LANE0_TEST_PATTERN_ERROR_COUNT_MASK 0x7FFF0000L
++#define DPRX_DPHY_ERROR_COUNT_B_LANE0__LANE0_TEST_PATTERN_ERROR_COUNT_VALID_MASK 0x80000000L
++//DPRX_DPHY_ERROR_COUNT_C_LANE0
++#define DPRX_DPHY_ERROR_COUNT_C_LANE0__LANE0_SYMBOL_ERROR_COUNT_CLR__SHIFT 0x1b
++#define DPRX_DPHY_ERROR_COUNT_C_LANE0__LANE0_DISPARITY_ERROR_COUNT_CLR__SHIFT 0x1c
++#define DPRX_DPHY_ERROR_COUNT_C_LANE0__LANE0_TEST_PATTERN_ERROR_COUNT_CLR__SHIFT 0x1e
++#define DPRX_DPHY_ERROR_COUNT_C_LANE0__LANE0_SYMBOL_ERROR_COUNT_CLR_MASK 0x08000000L
++#define DPRX_DPHY_ERROR_COUNT_C_LANE0__LANE0_DISPARITY_ERROR_COUNT_CLR_MASK 0x10000000L
++#define DPRX_DPHY_ERROR_COUNT_C_LANE0__LANE0_TEST_PATTERN_ERROR_COUNT_CLR_MASK 0x40000000L
++//DPRX_DPHY_ERROR_THRESH_A_LANE1
++#define DPRX_DPHY_ERROR_THRESH_A_LANE1__LANE1_SYMBOL_ERROR_COUNT_THRESH__SHIFT 0x0
++#define DPRX_DPHY_ERROR_THRESH_A_LANE1__LANE1_DISPARITY_ERROR_COUNT_THRESH__SHIFT 0x8
++#define DPRX_DPHY_ERROR_THRESH_A_LANE1__LANE1_TEST_PATTERN_ERROR_THRESH__SHIFT 0x18
++#define DPRX_DPHY_ERROR_THRESH_A_LANE1__LANE1_SYMBOL_ERROR_COUNT_THRESH_MASK 0x000000FFL
++#define DPRX_DPHY_ERROR_THRESH_A_LANE1__LANE1_DISPARITY_ERROR_COUNT_THRESH_MASK 0x0000FF00L
++#define DPRX_DPHY_ERROR_THRESH_A_LANE1__LANE1_TEST_PATTERN_ERROR_THRESH_MASK 0xFF000000L
++//DPRX_DPHY_ERROR_COUNT_A_LANE1
++#define DPRX_DPHY_ERROR_COUNT_A_LANE1__LANE1_SYMBOL_ERROR_COUNT__SHIFT 0x0
++#define DPRX_DPHY_ERROR_COUNT_A_LANE1__LANE1_SYMBOL_ERROR_COUNT_VALID__SHIFT 0xf
++#define DPRX_DPHY_ERROR_COUNT_A_LANE1__LANE1_DISPARITY_ERROR_COUNT__SHIFT 0x10
++#define DPRX_DPHY_ERROR_COUNT_A_LANE1__LANE1_DISPARITY_ERROR_COUNT_VALID__SHIFT 0x1f
++#define DPRX_DPHY_ERROR_COUNT_A_LANE1__LANE1_SYMBOL_ERROR_COUNT_MASK 0x00007FFFL
++#define DPRX_DPHY_ERROR_COUNT_A_LANE1__LANE1_SYMBOL_ERROR_COUNT_VALID_MASK 0x00008000L
++#define DPRX_DPHY_ERROR_COUNT_A_LANE1__LANE1_DISPARITY_ERROR_COUNT_MASK 0x7FFF0000L
++#define DPRX_DPHY_ERROR_COUNT_A_LANE1__LANE1_DISPARITY_ERROR_COUNT_VALID_MASK 0x80000000L
++//DPRX_DPHY_ERROR_COUNT_B_LANE1
++#define DPRX_DPHY_ERROR_COUNT_B_LANE1__LANE1_TEST_PATTERN_ERROR_COUNT__SHIFT 0x10
++#define DPRX_DPHY_ERROR_COUNT_B_LANE1__LANE1_TEST_PATTERN_ERROR_COUNT_VALID__SHIFT 0x1f
++#define DPRX_DPHY_ERROR_COUNT_B_LANE1__LANE1_TEST_PATTERN_ERROR_COUNT_MASK 0x7FFF0000L
++#define DPRX_DPHY_ERROR_COUNT_B_LANE1__LANE1_TEST_PATTERN_ERROR_COUNT_VALID_MASK 0x80000000L
++//DPRX_DPHY_ERROR_COUNT_C_LANE1
++#define DPRX_DPHY_ERROR_COUNT_C_LANE1__LANE1_SYMBOL_ERROR_COUNT_CLR__SHIFT 0x1b
++#define DPRX_DPHY_ERROR_COUNT_C_LANE1__LANE1_DISPARITY_ERROR_COUNT_CLR__SHIFT 0x1c
++#define DPRX_DPHY_ERROR_COUNT_C_LANE1__LANE1_TEST_PATTERN_ERROR_COUNT_CLR__SHIFT 0x1e
++#define DPRX_DPHY_ERROR_COUNT_C_LANE1__LANE1_SYMBOL_ERROR_COUNT_CLR_MASK 0x08000000L
++#define DPRX_DPHY_ERROR_COUNT_C_LANE1__LANE1_DISPARITY_ERROR_COUNT_CLR_MASK 0x10000000L
++#define DPRX_DPHY_ERROR_COUNT_C_LANE1__LANE1_TEST_PATTERN_ERROR_COUNT_CLR_MASK 0x40000000L
++//DPRX_DPHY_ERROR_THRESH_A_LANE2
++#define DPRX_DPHY_ERROR_THRESH_A_LANE2__LANE2_SYMBOL_ERROR_COUNT_THRESH__SHIFT 0x0
++#define DPRX_DPHY_ERROR_THRESH_A_LANE2__LANE2_DISPARITY_ERROR_COUNT_THRESH__SHIFT 0x8
++#define DPRX_DPHY_ERROR_THRESH_A_LANE2__LANE2_TEST_PATTERN_ERROR_THRESH__SHIFT 0x18
++#define DPRX_DPHY_ERROR_THRESH_A_LANE2__LANE2_SYMBOL_ERROR_COUNT_THRESH_MASK 0x000000FFL
++#define DPRX_DPHY_ERROR_THRESH_A_LANE2__LANE2_DISPARITY_ERROR_COUNT_THRESH_MASK 0x0000FF00L
++#define DPRX_DPHY_ERROR_THRESH_A_LANE2__LANE2_TEST_PATTERN_ERROR_THRESH_MASK 0xFF000000L
++//DPRX_DPHY_ERROR_COUNT_A_LANE2
++#define DPRX_DPHY_ERROR_COUNT_A_LANE2__LANE2_SYMBOL_ERROR_COUNT__SHIFT 0x0
++#define DPRX_DPHY_ERROR_COUNT_A_LANE2__LANE2_SYMBOL_ERROR_COUNT_VALID__SHIFT 0xf
++#define DPRX_DPHY_ERROR_COUNT_A_LANE2__LANE2_DISPARITY_ERROR_COUNT__SHIFT 0x10
++#define DPRX_DPHY_ERROR_COUNT_A_LANE2__LANE2_DISPARITY_ERROR_COUNT_VALID__SHIFT 0x1f
++#define DPRX_DPHY_ERROR_COUNT_A_LANE2__LANE2_SYMBOL_ERROR_COUNT_MASK 0x00007FFFL
++#define DPRX_DPHY_ERROR_COUNT_A_LANE2__LANE2_SYMBOL_ERROR_COUNT_VALID_MASK 0x00008000L
++#define DPRX_DPHY_ERROR_COUNT_A_LANE2__LANE2_DISPARITY_ERROR_COUNT_MASK 0x7FFF0000L
++#define DPRX_DPHY_ERROR_COUNT_A_LANE2__LANE2_DISPARITY_ERROR_COUNT_VALID_MASK 0x80000000L
++//DPRX_DPHY_ERROR_COUNT_B_LANE2
++#define DPRX_DPHY_ERROR_COUNT_B_LANE2__LANE2_TEST_PATTERN_ERROR_COUNT__SHIFT 0x10
++#define DPRX_DPHY_ERROR_COUNT_B_LANE2__LANE2_TEST_PATTERN_ERROR_COUNT_VALID__SHIFT 0x1f
++#define DPRX_DPHY_ERROR_COUNT_B_LANE2__LANE2_TEST_PATTERN_ERROR_COUNT_MASK 0x7FFF0000L
++#define DPRX_DPHY_ERROR_COUNT_B_LANE2__LANE2_TEST_PATTERN_ERROR_COUNT_VALID_MASK 0x80000000L
++//DPRX_DPHY_ERROR_COUNT_C_LANE2
++#define DPRX_DPHY_ERROR_COUNT_C_LANE2__LANE2_SYMBOL_ERROR_COUNT_CLR__SHIFT 0x1b
++#define DPRX_DPHY_ERROR_COUNT_C_LANE2__LANE2_DISPARITY_ERROR_COUNT_CLR__SHIFT 0x1c
++#define DPRX_DPHY_ERROR_COUNT_C_LANE2__LANE2_TEST_PATTERN_ERROR_COUNT_CLR__SHIFT 0x1e
++#define DPRX_DPHY_ERROR_COUNT_C_LANE2__LANE2_SYMBOL_ERROR_COUNT_CLR_MASK 0x08000000L
++#define DPRX_DPHY_ERROR_COUNT_C_LANE2__LANE2_DISPARITY_ERROR_COUNT_CLR_MASK 0x10000000L
++#define DPRX_DPHY_ERROR_COUNT_C_LANE2__LANE2_TEST_PATTERN_ERROR_COUNT_CLR_MASK 0x40000000L
++//DPRX_DPHY_ERROR_THRESH_A_LANE3
++#define DPRX_DPHY_ERROR_THRESH_A_LANE3__LANE3_SYMBOL_ERROR_COUNT_THRESH__SHIFT 0x0
++#define DPRX_DPHY_ERROR_THRESH_A_LANE3__LANE3_DISPARITY_ERROR_COUNT_THRESH__SHIFT 0x8
++#define DPRX_DPHY_ERROR_THRESH_A_LANE3__LANE3_TEST_PATTERN_ERROR_THRESH__SHIFT 0x18
++#define DPRX_DPHY_ERROR_THRESH_A_LANE3__LANE3_SYMBOL_ERROR_COUNT_THRESH_MASK 0x000000FFL
++#define DPRX_DPHY_ERROR_THRESH_A_LANE3__LANE3_DISPARITY_ERROR_COUNT_THRESH_MASK 0x0000FF00L
++#define DPRX_DPHY_ERROR_THRESH_A_LANE3__LANE3_TEST_PATTERN_ERROR_THRESH_MASK 0xFF000000L
++//DPRX_DPHY_ERROR_COUNT_A_LANE3
++#define DPRX_DPHY_ERROR_COUNT_A_LANE3__LANE3_SYMBOL_ERROR_COUNT__SHIFT 0x0
++#define DPRX_DPHY_ERROR_COUNT_A_LANE3__LANE3_SYMBOL_ERROR_COUNT_VALID__SHIFT 0xf
++#define DPRX_DPHY_ERROR_COUNT_A_LANE3__LANE3_DISPARITY_ERROR_COUNT__SHIFT 0x10
++#define DPRX_DPHY_ERROR_COUNT_A_LANE3__LANE3_DISPARITY_ERROR_COUNT_VALID__SHIFT 0x1f
++#define DPRX_DPHY_ERROR_COUNT_A_LANE3__LANE3_SYMBOL_ERROR_COUNT_MASK 0x00007FFFL
++#define DPRX_DPHY_ERROR_COUNT_A_LANE3__LANE3_SYMBOL_ERROR_COUNT_VALID_MASK 0x00008000L
++#define DPRX_DPHY_ERROR_COUNT_A_LANE3__LANE3_DISPARITY_ERROR_COUNT_MASK 0x7FFF0000L
++#define DPRX_DPHY_ERROR_COUNT_A_LANE3__LANE3_DISPARITY_ERROR_COUNT_VALID_MASK 0x80000000L
++//DPRX_DPHY_ERROR_COUNT_B_LANE3
++#define DPRX_DPHY_ERROR_COUNT_B_LANE3__LANE3_TEST_PATTERN_ERROR_COUNT__SHIFT 0x10
++#define DPRX_DPHY_ERROR_COUNT_B_LANE3__LANE3_TEST_PATTERN_ERROR_COUNT_VALID__SHIFT 0x1f
++#define DPRX_DPHY_ERROR_COUNT_B_LANE3__LANE3_TEST_PATTERN_ERROR_COUNT_MASK 0x7FFF0000L
++#define DPRX_DPHY_ERROR_COUNT_B_LANE3__LANE3_TEST_PATTERN_ERROR_COUNT_VALID_MASK 0x80000000L
++//DPRX_DPHY_ERROR_COUNT_C_LANE3
++#define DPRX_DPHY_ERROR_COUNT_C_LANE3__LANE3_SYMBOL_ERROR_COUNT_CLR__SHIFT 0x1b
++#define DPRX_DPHY_ERROR_COUNT_C_LANE3__LANE3_DISPARITY_ERROR_COUNT_CLR__SHIFT 0x1c
++#define DPRX_DPHY_ERROR_COUNT_C_LANE3__LANE3_TEST_PATTERN_ERROR_COUNT_CLR__SHIFT 0x1e
++#define DPRX_DPHY_ERROR_COUNT_C_LANE3__LANE3_SYMBOL_ERROR_COUNT_CLR_MASK 0x08000000L
++#define DPRX_DPHY_ERROR_COUNT_C_LANE3__LANE3_DISPARITY_ERROR_COUNT_CLR_MASK 0x10000000L
++#define DPRX_DPHY_ERROR_COUNT_C_LANE3__LANE3_TEST_PATTERN_ERROR_COUNT_CLR_MASK 0x40000000L
++//DPRX_DPHY_BS_ERROR_THRESH_GLOBAL
++#define DPRX_DPHY_BS_ERROR_THRESH_GLOBAL__BS_INTERVAL_ERROR_THRESH__SHIFT 0x0
++#define DPRX_DPHY_BS_ERROR_THRESH_GLOBAL__BS_INTERVAL_UNCERTAINTY_THRESH__SHIFT 0x8
++#define DPRX_DPHY_BS_ERROR_THRESH_GLOBAL__BS_INTERVAL_ERROR_THRESH_MASK 0x0000001FL
++#define DPRX_DPHY_BS_ERROR_THRESH_GLOBAL__BS_INTERVAL_UNCERTAINTY_THRESH_MASK 0x0000FF00L
++//DPRX_DPHY_SR_ERROR_COUNT_A
++#define DPRX_DPHY_SR_ERROR_COUNT_A__SR_ERROR_COUNT__SHIFT 0x0
++#define DPRX_DPHY_SR_ERROR_COUNT_A__SR_INTERVAL_COUNT__SHIFT 0x8
++#define DPRX_DPHY_SR_ERROR_COUNT_A__SR_ERROR_COUNT_CLR__SHIFT 0x19
++#define DPRX_DPHY_SR_ERROR_COUNT_A__SR_ERROR_COUNT_MASK 0x000000FFL
++#define DPRX_DPHY_SR_ERROR_COUNT_A__SR_INTERVAL_COUNT_MASK 0x01FFFF00L
++#define DPRX_DPHY_SR_ERROR_COUNT_A__SR_ERROR_COUNT_CLR_MASK 0x02000000L
++//DPRX_DPHY_BS_ERROR_COUNT_A
++#define DPRX_DPHY_BS_ERROR_COUNT_A__BS_ERROR_COUNT__SHIFT 0x0
++#define DPRX_DPHY_BS_ERROR_COUNT_A__BS_INTERVAL_COUNT__SHIFT 0x8
++#define DPRX_DPHY_BS_ERROR_COUNT_A__BS_ERROR_COUNT_CLR__SHIFT 0x19
++#define DPRX_DPHY_BS_ERROR_COUNT_A__BS_ERROR_COUNT_MASK 0x000000FFL
++#define DPRX_DPHY_BS_ERROR_COUNT_A__BS_INTERVAL_COUNT_MASK 0x01FFFF00L
++#define DPRX_DPHY_BS_ERROR_COUNT_A__BS_ERROR_COUNT_CLR_MASK 0x02000000L
++//DPRX_DPHY_BS_ERROR_COUNT_B
++#define DPRX_DPHY_BS_ERROR_COUNT_B__BS_INTERVAL_UNCERTAINTY_COUNT__SHIFT 0x0
++#define DPRX_DPHY_BS_ERROR_COUNT_B__BS_INTERVAL_ERROR_COUNT__SHIFT 0x8
++#define DPRX_DPHY_BS_ERROR_COUNT_B__BS_INTERVAL_ERROR_COUNT_CLR__SHIFT 0x11
++#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE0_CPBS_ERROR_CLR__SHIFT 0x14
++#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE1_CPBS_ERROR_CLR__SHIFT 0x15
++#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE2_CPBS_ERROR_CLR__SHIFT 0x16
++#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE3_CPBS_ERROR_CLR__SHIFT 0x17
++#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE0_CPBS_ERROR__SHIFT 0x18
++#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE1_CPBS_ERROR__SHIFT 0x1a
++#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE2_CPBS_ERROR__SHIFT 0x1c
++#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE3_CPBS_ERROR__SHIFT 0x1e
++#define DPRX_DPHY_BS_ERROR_COUNT_B__BS_INTERVAL_UNCERTAINTY_COUNT_MASK 0x000000FFL
++#define DPRX_DPHY_BS_ERROR_COUNT_B__BS_INTERVAL_ERROR_COUNT_MASK 0x00001F00L
++#define DPRX_DPHY_BS_ERROR_COUNT_B__BS_INTERVAL_ERROR_COUNT_CLR_MASK 0x00020000L
++#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE0_CPBS_ERROR_CLR_MASK 0x00100000L
++#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE1_CPBS_ERROR_CLR_MASK 0x00200000L
++#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE2_CPBS_ERROR_CLR_MASK 0x00400000L
++#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE3_CPBS_ERROR_CLR_MASK 0x00800000L
++#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE0_CPBS_ERROR_MASK 0x03000000L
++#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE1_CPBS_ERROR_MASK 0x0C000000L
++#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE2_CPBS_ERROR_MASK 0x30000000L
++#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE3_CPBS_ERROR_MASK 0xC0000000L
++//DPRX_DPHY_LANESETUP0
++#define DPRX_DPHY_LANESETUP0__LANE_MAP__SHIFT 0x0
++#define DPRX_DPHY_LANESETUP0__LANE_MAP_MASK 0x000000FFL
++//DPRX_DPHY_LANESETUP1
++#define DPRX_DPHY_LANESETUP1__LANEINV__SHIFT 0x0
++#define DPRX_DPHY_LANESETUP1__LANEINV_MASK 0x0000000FL
++//DPRX_DPHY_LFSRADV
++#define DPRX_DPHY_LFSRADV__TWOSYMCORRECTMIDDLE_ENABLE__SHIFT 0x1
++#define DPRX_DPHY_LFSRADV__TWOSYMCORRECTLR_ENABLE__SHIFT 0x2
++#define DPRX_DPHY_LFSRADV__SEVENSYMBOLWINDOW_ENABLE__SHIFT 0x3
++#define DPRX_DPHY_LFSRADV__SUPPRESS_SINGLE_BS_BF_CP_SR_EN__SHIFT 0x4
++#define DPRX_DPHY_LFSRADV__IGNORE_ERROR_FLAG_FOR_BS_INTERVAL__SHIFT 0x5
++#define DPRX_DPHY_LFSRADV__TWOSYMCORRECTMIDDLE_ENABLE_MASK 0x00000002L
++#define DPRX_DPHY_LFSRADV__TWOSYMCORRECTLR_ENABLE_MASK 0x00000004L
++#define DPRX_DPHY_LFSRADV__SEVENSYMBOLWINDOW_ENABLE_MASK 0x00000008L
++#define DPRX_DPHY_LFSRADV__SUPPRESS_SINGLE_BS_BF_CP_SR_EN_MASK 0x00000010L
++#define DPRX_DPHY_LFSRADV__IGNORE_ERROR_FLAG_FOR_BS_INTERVAL_MASK 0x00000020L
++//DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT
++#define DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT__SEVENSYMBOLWINDOW_ERROR_DETECT_LANE0__SHIFT 0x0
++#define DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT__SEVENSYMBOLWINDOW_ERROR_DETECT_LANE1__SHIFT 0x8
++#define DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT__SEVENSYMBOLWINDOW_ERROR_DETECT_LANE2__SHIFT 0x10
++#define DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT__SEVENSYMBOLWINDOW_ERROR_DETECT_LANE3__SHIFT 0x18
++#define DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT__SEVENSYMBOLWINDOW_ERROR_DETECT_CLEAR__SHIFT 0x1f
++#define DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT__SEVENSYMBOLWINDOW_ERROR_DETECT_LANE0_MASK 0x0000007FL
++#define DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT__SEVENSYMBOLWINDOW_ERROR_DETECT_LANE1_MASK 0x00007F00L
++#define DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT__SEVENSYMBOLWINDOW_ERROR_DETECT_LANE2_MASK 0x007F0000L
++#define DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT__SEVENSYMBOLWINDOW_ERROR_DETECT_LANE3_MASK 0x7F000000L
++#define DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT__SEVENSYMBOLWINDOW_ERROR_DETECT_CLEAR_MASK 0x80000000L
++//DPRX_DPHY_SET_ENABLE
++#define DPRX_DPHY_SET_ENABLE__SET_ENABLE__SHIFT 0x0
++#define DPRX_DPHY_SET_ENABLE__CLOCK_ENABLE__SHIFT 0x8
++#define DPRX_DPHY_SET_ENABLE__CLOCK_ON__SHIFT 0xc
++#define DPRX_DPHY_SET_ENABLE__SET_ENABLE_MASK 0x00000003L
++#define DPRX_DPHY_SET_ENABLE__CLOCK_ENABLE_MASK 0x00000100L
++#define DPRX_DPHY_SET_ENABLE__CLOCK_ON_MASK 0x00001000L
++//DPRX_DPHY_ECF_LSB
++#define DPRX_DPHY_ECF_LSB__ECF_LSB__SHIFT 0x0
++#define DPRX_DPHY_ECF_LSB__ECF_LSB_MASK 0xFFFFFFFFL
++//DPRX_DPHY_ECF_MSB
++#define DPRX_DPHY_ECF_MSB__ECF_MSB__SHIFT 0x0
++#define DPRX_DPHY_ECF_MSB__ECF_MSB_MASK 0xFFFFFFFFL
++//DPRX_DPHY_ENHANCED_FRAME_EN
++#define DPRX_DPHY_ENHANCED_FRAME_EN__ENHANCED_FRAME_EN__SHIFT 0x0
++#define DPRX_DPHY_ENHANCED_FRAME_EN__ENHANCED_FRAME_EN_MASK 0x00000001L
++//DPRX_DPHY_MTP_HEADER_COUNT_FORCE
++#define DPRX_DPHY_MTP_HEADER_COUNT_FORCE__MTP_HEADER_COUNT_FORCE__SHIFT 0x0
++#define DPRX_DPHY_MTP_HEADER_COUNT_FORCE__USE_TRAILING_BF__SHIFT 0x11
++#define DPRX_DPHY_MTP_HEADER_COUNT_FORCE__LINK_LINE_COUNT_FORCE__SHIFT 0x12
++#define DPRX_DPHY_MTP_HEADER_COUNT_FORCE__BS_COUNT_FORCE__SHIFT 0x14
++#define DPRX_DPHY_MTP_HEADER_COUNT_FORCE__MTP_HEADER_COUNT_FORCE_MASK 0x000003FFL
++#define DPRX_DPHY_MTP_HEADER_COUNT_FORCE__USE_TRAILING_BF_MASK 0x00020000L
++#define DPRX_DPHY_MTP_HEADER_COUNT_FORCE__LINK_LINE_COUNT_FORCE_MASK 0x000C0000L
++#define DPRX_DPHY_MTP_HEADER_COUNT_FORCE__BS_COUNT_FORCE_MASK 0x3FF00000L
++//DPRX_DPHY_DYNAMIC_DESKEW_DATA
++#define DPRX_DPHY_DYNAMIC_DESKEW_DATA__MATCH0_DATA__SHIFT 0x0
++#define DPRX_DPHY_DYNAMIC_DESKEW_DATA__MATCH1_DATA__SHIFT 0x8
++#define DPRX_DPHY_DYNAMIC_DESKEW_DATA__MATCH2_DATA__SHIFT 0x10
++#define DPRX_DPHY_DYNAMIC_DESKEW_DATA__MATCH3_DATA__SHIFT 0x18
++#define DPRX_DPHY_DYNAMIC_DESKEW_DATA__MATCH0_DATA_MASK 0x000000FFL
++#define DPRX_DPHY_DYNAMIC_DESKEW_DATA__MATCH1_DATA_MASK 0x0000FF00L
++#define DPRX_DPHY_DYNAMIC_DESKEW_DATA__MATCH2_DATA_MASK 0x00FF0000L
++#define DPRX_DPHY_DYNAMIC_DESKEW_DATA__MATCH3_DATA_MASK 0xFF000000L
++//DPRX_DPHY_DYNAMIC_DESKEW_CONTROL
++#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__DESKEW_WAIT_COUNT__SHIFT 0x0
++#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH0_KCODE__SHIFT 0x5
++#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH0_DATA_DONTCARE__SHIFT 0x6
++#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH0_KCODE_DONTCARE__SHIFT 0x7
++#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH1_KCODE__SHIFT 0x8
++#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH1_DATA_DONTCARE__SHIFT 0x9
++#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH1_KCODE_DONTCARE__SHIFT 0xa
++#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH2_KCODE__SHIFT 0xb
++#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH2_DATA_DONTCARE__SHIFT 0xc
++#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH2_KCODE_DONTCARE__SHIFT 0xd
++#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH3_KCODE__SHIFT 0xe
++#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH3_DATA_DONTCARE__SHIFT 0xf
++#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH3_KCODE_DONTCARE__SHIFT 0x10
++#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__INTERLANE_ALIGN_CHECK_COUNT__SHIFT 0x11
++#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__FIFO_LEN_IGNORE_DURING_DS_RST__SHIFT 0x1f
++#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__DESKEW_WAIT_COUNT_MASK 0x0000001FL
++#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH0_KCODE_MASK 0x00000020L
++#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH0_DATA_DONTCARE_MASK 0x00000040L
++#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH0_KCODE_DONTCARE_MASK 0x00000080L
++#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH1_KCODE_MASK 0x00000100L
++#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH1_DATA_DONTCARE_MASK 0x00000200L
++#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH1_KCODE_DONTCARE_MASK 0x00000400L
++#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH2_KCODE_MASK 0x00000800L
++#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH2_DATA_DONTCARE_MASK 0x00001000L
++#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH2_KCODE_DONTCARE_MASK 0x00002000L
++#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH3_KCODE_MASK 0x00004000L
++#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH3_DATA_DONTCARE_MASK 0x00008000L
++#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH3_KCODE_DONTCARE_MASK 0x00010000L
++#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__INTERLANE_ALIGN_CHECK_COUNT_MASK 0x007E0000L
++#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__FIFO_LEN_IGNORE_DURING_DS_RST_MASK 0x80000000L
++//DPRX_DPHY_BYPASS
++#define DPRX_DPHY_BYPASS__LANE0_SDESKEW_BYPASS__SHIFT 0x4
++#define DPRX_DPHY_BYPASS__LANE1_SDESKEW_BYPASS__SHIFT 0x5
++#define DPRX_DPHY_BYPASS__LANE2_SDESKEW_BYPASS__SHIFT 0x6
++#define DPRX_DPHY_BYPASS__LANE3_SDESKEW_BYPASS__SHIFT 0x7
++#define DPRX_DPHY_BYPASS__LANE0_SDESKEW_BYPASS_MASK 0x00000010L
++#define DPRX_DPHY_BYPASS__LANE1_SDESKEW_BYPASS_MASK 0x00000020L
++#define DPRX_DPHY_BYPASS__LANE2_SDESKEW_BYPASS_MASK 0x00000040L
++#define DPRX_DPHY_BYPASS__LANE3_SDESKEW_BYPASS_MASK 0x00000080L
++//DPRX_DPHY_INT_RESET
++#define DPRX_DPHY_INT_RESET__LANE0_ALIGN_RESET__SHIFT 0x0
++#define DPRX_DPHY_INT_RESET__LANE1_ALIGN_RESET__SHIFT 0x1
++#define DPRX_DPHY_INT_RESET__LANE2_ALIGN_RESET__SHIFT 0x2
++#define DPRX_DPHY_INT_RESET__LANE3_ALIGN_RESET__SHIFT 0x3
++#define DPRX_DPHY_INT_RESET__LANE0_SDESKEW_RESET__SHIFT 0x4
++#define DPRX_DPHY_INT_RESET__LANE1_SDESKEW_RESET__SHIFT 0x5
++#define DPRX_DPHY_INT_RESET__LANE2_SDESKEW_RESET__SHIFT 0x6
++#define DPRX_DPHY_INT_RESET__LANE3_SDESKEW_RESET__SHIFT 0x7
++#define DPRX_DPHY_INT_RESET__LANE0_8B10BDEC_RESET__SHIFT 0x8
++#define DPRX_DPHY_INT_RESET__LANE1_8B10BDEC_RESET__SHIFT 0x9
++#define DPRX_DPHY_INT_RESET__LANE2_8B10BDEC_RESET__SHIFT 0xa
++#define DPRX_DPHY_INT_RESET__LANE3_8B10BDEC_RESET__SHIFT 0xb
++#define DPRX_DPHY_INT_RESET__LANE0_LCOUNT_RESET__SHIFT 0x10
++#define DPRX_DPHY_INT_RESET__LANE1_LCOUNT_RESET__SHIFT 0x11
++#define DPRX_DPHY_INT_RESET__LANE2_LCOUNT_RESET__SHIFT 0x12
++#define DPRX_DPHY_INT_RESET__LANE3_LCOUNT_RESET__SHIFT 0x13
++#define DPRX_DPHY_INT_RESET__LANE0_DDESKEW_RESET__SHIFT 0x14
++#define DPRX_DPHY_INT_RESET__LANE1_DDESKEW_RESET__SHIFT 0x15
++#define DPRX_DPHY_INT_RESET__LANE2_DDESKEW_RESET__SHIFT 0x16
++#define DPRX_DPHY_INT_RESET__LANE3_DDESKEW_RESET__SHIFT 0x17
++#define DPRX_DPHY_INT_RESET__INV_RESET__SHIFT 0x18
++#define DPRX_DPHY_INT_RESET__LANEREV_RESET__SHIFT 0x19
++#define DPRX_DPHY_INT_RESET__ENABLE_RESET__SHIFT 0x1a
++#define DPRX_DPHY_INT_RESET__CTL_RESET__SHIFT 0x1b
++#define DPRX_DPHY_INT_RESET__CTL_DS_RESET__SHIFT 0x1c
++#define DPRX_DPHY_INT_RESET__CTL_TRN_RESET__SHIFT 0x1d
++#define DPRX_DPHY_INT_RESET__HEADERPARSE_RESET__SHIFT 0x1e
++#define DPRX_DPHY_INT_RESET__SDOUT_RESET__SHIFT 0x1f
++#define DPRX_DPHY_INT_RESET__LANE0_ALIGN_RESET_MASK 0x00000001L
++#define DPRX_DPHY_INT_RESET__LANE1_ALIGN_RESET_MASK 0x00000002L
++#define DPRX_DPHY_INT_RESET__LANE2_ALIGN_RESET_MASK 0x00000004L
++#define DPRX_DPHY_INT_RESET__LANE3_ALIGN_RESET_MASK 0x00000008L
++#define DPRX_DPHY_INT_RESET__LANE0_SDESKEW_RESET_MASK 0x00000010L
++#define DPRX_DPHY_INT_RESET__LANE1_SDESKEW_RESET_MASK 0x00000020L
++#define DPRX_DPHY_INT_RESET__LANE2_SDESKEW_RESET_MASK 0x00000040L
++#define DPRX_DPHY_INT_RESET__LANE3_SDESKEW_RESET_MASK 0x00000080L
++#define DPRX_DPHY_INT_RESET__LANE0_8B10BDEC_RESET_MASK 0x00000100L
++#define DPRX_DPHY_INT_RESET__LANE1_8B10BDEC_RESET_MASK 0x00000200L
++#define DPRX_DPHY_INT_RESET__LANE2_8B10BDEC_RESET_MASK 0x00000400L
++#define DPRX_DPHY_INT_RESET__LANE3_8B10BDEC_RESET_MASK 0x00000800L
++#define DPRX_DPHY_INT_RESET__LANE0_LCOUNT_RESET_MASK 0x00010000L
++#define DPRX_DPHY_INT_RESET__LANE1_LCOUNT_RESET_MASK 0x00020000L
++#define DPRX_DPHY_INT_RESET__LANE2_LCOUNT_RESET_MASK 0x00040000L
++#define DPRX_DPHY_INT_RESET__LANE3_LCOUNT_RESET_MASK 0x00080000L
++#define DPRX_DPHY_INT_RESET__LANE0_DDESKEW_RESET_MASK 0x00100000L
++#define DPRX_DPHY_INT_RESET__LANE1_DDESKEW_RESET_MASK 0x00200000L
++#define DPRX_DPHY_INT_RESET__LANE2_DDESKEW_RESET_MASK 0x00400000L
++#define DPRX_DPHY_INT_RESET__LANE3_DDESKEW_RESET_MASK 0x00800000L
++#define DPRX_DPHY_INT_RESET__INV_RESET_MASK 0x01000000L
++#define DPRX_DPHY_INT_RESET__LANEREV_RESET_MASK 0x02000000L
++#define DPRX_DPHY_INT_RESET__ENABLE_RESET_MASK 0x04000000L
++#define DPRX_DPHY_INT_RESET__CTL_RESET_MASK 0x08000000L
++#define DPRX_DPHY_INT_RESET__CTL_DS_RESET_MASK 0x10000000L
++#define DPRX_DPHY_INT_RESET__CTL_TRN_RESET_MASK 0x20000000L
++#define DPRX_DPHY_INT_RESET__HEADERPARSE_RESET_MASK 0x40000000L
++#define DPRX_DPHY_INT_RESET__SDOUT_RESET_MASK 0x80000000L
++//DPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS
++#define DPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS__BS_INTERVAL_ERROR_THRESH_EXCEEDED_FLAG__SHIFT 0x0
++#define DPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS__BS_INTERVAL_ERROR_THRESH_EXCEEDED_ACK__SHIFT 0x4
++#define DPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS__BS_INTERVAL_ERROR_THRESH_EXCEEDED_MASK__SHIFT 0x8
++#define DPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS__BS_INTERVAL_ERROR_THRESH_EXCEEDED_FLAG_MASK 0x00000001L
++#define DPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS__BS_INTERVAL_ERROR_THRESH_EXCEEDED_ACK_MASK 0x00000010L
++#define DPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS__BS_INTERVAL_ERROR_THRESH_EXCEEDED_MASK_MASK 0x00000100L
++//DPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS
++#define DPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS__SYMBOL_ERROR_THRESH_EXCEEDED_FLAG__SHIFT 0x0
++#define DPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS__SYMBOL_ERROR_THRESH_EXCEEDED_ACK__SHIFT 0x4
++#define DPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS__SYMBOL_ERROR_THRESH_EXCEEDED_MASK__SHIFT 0x8
++#define DPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS__SYMBOL_ERROR_THRESH_EXCEEDED_FLAG_MASK 0x00000001L
++#define DPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS__SYMBOL_ERROR_THRESH_EXCEEDED_ACK_MASK 0x00000010L
++#define DPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS__SYMBOL_ERROR_THRESH_EXCEEDED_MASK_MASK 0x00000100L
++//DPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS
++#define DPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS__DISPARITY_ERROR_THRESH_EXCEEDED_FLAG__SHIFT 0x0
++#define DPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS__DISPARITY_ERROR_THRESH_EXCEEDED_ACK__SHIFT 0x4
++#define DPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS__DISPARITY_ERROR_THRESH_EXCEEDED_MASK__SHIFT 0x8
++#define DPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS__DISPARITY_ERROR_THRESH_EXCEEDED_FLAG_MASK 0x00000001L
++#define DPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS__DISPARITY_ERROR_THRESH_EXCEEDED_ACK_MASK 0x00000010L
++#define DPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS__DISPARITY_ERROR_THRESH_EXCEEDED_MASK_MASK 0x00000100L
++//DPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS
++#define DPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS__TEST_PATTERN_ERROR_THRESH_EXCEEDED_FLAG__SHIFT 0x0
++#define DPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS__TEST_PATTERN_ERROR_THRESH_EXCEEDED_ACK__SHIFT 0x4
++#define DPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS__TEST_PATTERN_ERROR_THRESH_EXCEEDED_MASK__SHIFT 0x8
++#define DPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS__TEST_PATTERN_ERROR_THRESH_EXCEEDED_FLAG_MASK 0x00000001L
++#define DPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS__TEST_PATTERN_ERROR_THRESH_EXCEEDED_ACK_MASK 0x00000010L
++#define DPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS__TEST_PATTERN_ERROR_THRESH_EXCEEDED_MASK_MASK 0x00000100L
++//DPRX_DPHY_DETECT_SR_LOCK_STATUS
++#define DPRX_DPHY_DETECT_SR_LOCK_STATUS__DETECT_SR_LOCK_STATUS_FLAG__SHIFT 0x0
++#define DPRX_DPHY_DETECT_SR_LOCK_STATUS__DETECT_SR_LOCK_STATUS_ACK__SHIFT 0x4
++#define DPRX_DPHY_DETECT_SR_LOCK_STATUS__DETECT_SR_LOCK_STATUS_MASK__SHIFT 0x8
++#define DPRX_DPHY_DETECT_SR_LOCK_STATUS__DETECT_SR_LOCK_STATUS_TYPE__SHIFT 0xc
++#define DPRX_DPHY_DETECT_SR_LOCK_STATUS__DETECT_SR_LOCK_STATUS_FLAG_MASK 0x00000001L
++#define DPRX_DPHY_DETECT_SR_LOCK_STATUS__DETECT_SR_LOCK_STATUS_ACK_MASK 0x00000010L
++#define DPRX_DPHY_DETECT_SR_LOCK_STATUS__DETECT_SR_LOCK_STATUS_MASK_MASK 0x00000100L
++#define DPRX_DPHY_DETECT_SR_LOCK_STATUS__DETECT_SR_LOCK_STATUS_TYPE_MASK 0x00001000L
++//DPRX_DPHY_LOSS_OF_ALIGN_STATUS
++#define DPRX_DPHY_LOSS_OF_ALIGN_STATUS__LOSS_OF_ALIGN_FLAG__SHIFT 0x0
++#define DPRX_DPHY_LOSS_OF_ALIGN_STATUS__LOSS_OF_ALIGN_ACK__SHIFT 0x4
++#define DPRX_DPHY_LOSS_OF_ALIGN_STATUS__LOSS_OF_ALIGN_MASK__SHIFT 0x8
++#define DPRX_DPHY_LOSS_OF_ALIGN_STATUS__LOSS_OF_ALIGN_FLAG_MASK 0x00000001L
++#define DPRX_DPHY_LOSS_OF_ALIGN_STATUS__LOSS_OF_ALIGN_ACK_MASK 0x00000010L
++#define DPRX_DPHY_LOSS_OF_ALIGN_STATUS__LOSS_OF_ALIGN_MASK_MASK 0x00000100L
++//DPRX_DPHY_LOSS_OF_DESKEW_STATUS
++#define DPRX_DPHY_LOSS_OF_DESKEW_STATUS__LOSS_OF_DESKEW_FLAG__SHIFT 0x0
++#define DPRX_DPHY_LOSS_OF_DESKEW_STATUS__LOSS_OF_DESKEW_ACK__SHIFT 0x4
++#define DPRX_DPHY_LOSS_OF_DESKEW_STATUS__LOSS_OF_DESKEW_MASK__SHIFT 0x8
++#define DPRX_DPHY_LOSS_OF_DESKEW_STATUS__LOSS_OF_DESKEW_FLAG_MASK 0x00000001L
++#define DPRX_DPHY_LOSS_OF_DESKEW_STATUS__LOSS_OF_DESKEW_ACK_MASK 0x00000010L
++#define DPRX_DPHY_LOSS_OF_DESKEW_STATUS__LOSS_OF_DESKEW_MASK_MASK 0x00000100L
++//DPRX_DPHY_EXCESSIVE_ERROR_STATUS
++#define DPRX_DPHY_EXCESSIVE_ERROR_STATUS__EXCESSIVE_ERROR_FLAG__SHIFT 0x0
++#define DPRX_DPHY_EXCESSIVE_ERROR_STATUS__EXCESSIVE_ERROR_ACK__SHIFT 0x4
++#define DPRX_DPHY_EXCESSIVE_ERROR_STATUS__EXCESSIVE_ERROR_MASK__SHIFT 0x8
++#define DPRX_DPHY_EXCESSIVE_ERROR_STATUS__EXCESSIVE_ERROR_FLAG_MASK 0x00000001L
++#define DPRX_DPHY_EXCESSIVE_ERROR_STATUS__EXCESSIVE_ERROR_ACK_MASK 0x00000010L
++#define DPRX_DPHY_EXCESSIVE_ERROR_STATUS__EXCESSIVE_ERROR_MASK_MASK 0x00000100L
++//DPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS
++#define DPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS__DESKEW_FIFO_OVERFLOW_FLAG__SHIFT 0x0
++#define DPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS__DESKEW_FIFO_OVERFLOW_ACK__SHIFT 0x4
++#define DPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS__DESKEW_FIFO_OVERFLOW_MASK__SHIFT 0x8
++#define DPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS__DESKEW_FIFO_OVERFLOW_FLAG_MASK 0x00000001L
++#define DPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS__DESKEW_FIFO_OVERFLOW_ACK_MASK 0x00000010L
++#define DPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS__DESKEW_FIFO_OVERFLOW_MASK_MASK 0x00000100L
++//DPRX_DPHY_SPARE
++#define DPRX_DPHY_SPARE__DPHY_SPARE__SHIFT 0x0
++#define DPRX_DPHY_SPARE__DPHY_SPARE_MASK 0xFFFFFFFFL
++//DCRX_GATE_DISABLE_CNTL
++#define DCRX_GATE_DISABLE_CNTL__DCRX_DISPCLK_CWB0_SD0_GATE_DISABLE__SHIFT 0x0
++#define DCRX_GATE_DISABLE_CNTL__DCRX_DISPCLK_CWB1_SD1_GATE_DISABLE__SHIFT 0x1
++#define DCRX_GATE_DISABLE_CNTL__DCRX_DISPCLK_AUX_GATE_DISABLE__SHIFT 0x2
++#define DCRX_GATE_DISABLE_CNTL__DCRX_DISPCLK_R_GATE_DISABLE__SHIFT 0x3
++#define DCRX_GATE_DISABLE_CNTL__DCRX_SYMCLK_RX_SD0_GATE_DISABLE__SHIFT 0x8
++#define DCRX_GATE_DISABLE_CNTL__DCRX_SYMCLK_RX_SD1_GATE_DISABLE__SHIFT 0x9
++#define DCRX_GATE_DISABLE_CNTL__DCRX_SYMCLK_RX_DPHY_GATE_DISABLE__SHIFT 0xa
++#define DCRX_GATE_DISABLE_CNTL__DCRX_SYMCLK_RX_P_GATE_DISABLE__SHIFT 0xc
++#define DCRX_GATE_DISABLE_CNTL__DCRX_DISPCLK_CWB0_SD0_GATE_DISABLE_MASK 0x00000001L
++#define DCRX_GATE_DISABLE_CNTL__DCRX_DISPCLK_CWB1_SD1_GATE_DISABLE_MASK 0x00000002L
++#define DCRX_GATE_DISABLE_CNTL__DCRX_DISPCLK_AUX_GATE_DISABLE_MASK 0x00000004L
++#define DCRX_GATE_DISABLE_CNTL__DCRX_DISPCLK_R_GATE_DISABLE_MASK 0x00000008L
++#define DCRX_GATE_DISABLE_CNTL__DCRX_SYMCLK_RX_SD0_GATE_DISABLE_MASK 0x00000100L
++#define DCRX_GATE_DISABLE_CNTL__DCRX_SYMCLK_RX_SD1_GATE_DISABLE_MASK 0x00000200L
++#define DCRX_GATE_DISABLE_CNTL__DCRX_SYMCLK_RX_DPHY_GATE_DISABLE_MASK 0x00000400L
++#define DCRX_GATE_DISABLE_CNTL__DCRX_SYMCLK_RX_P_GATE_DISABLE_MASK 0x00001000L
++//DCRX_SOFT_RESET
++#define DCRX_SOFT_RESET__DCRX_DISPCLK_CWB0_SD0_SOFT_RESET__SHIFT 0x0
++#define DCRX_SOFT_RESET__DCRX_DISPCLK_CWB1_SD1_SOFT_RESET__SHIFT 0x1
++#define DCRX_SOFT_RESET__DCRX_DISPCLK_AUX_SOFT_RESET__SHIFT 0x2
++#define DCRX_SOFT_RESET__DCRX_DISPCLK_P_SOFT_RESET__SHIFT 0x4
++#define DCRX_SOFT_RESET__DCRX_SYMCLK_RX_SD0_SOFT_RESET__SHIFT 0x8
++#define DCRX_SOFT_RESET__DCRX_SYMCLK_RX_SD1_SOFT_RESET__SHIFT 0x9
++#define DCRX_SOFT_RESET__DCRX_SYMCLK_RX_DPHY_SOFT_RESET__SHIFT 0xa
++#define DCRX_SOFT_RESET__DCRX_SYMCLK_RX_P_SOFT_RESET__SHIFT 0xc
++#define DCRX_SOFT_RESET__DCRX_REFCLK_SOFT_RESET__SHIFT 0x10
++#define DCRX_SOFT_RESET__DCRX_SCLK_SOFT_RESET__SHIFT 0x11
++#define DCRX_SOFT_RESET__DCRX_DISPCLK_CWB0_SD0_SOFT_RESET_MASK 0x00000001L
++#define DCRX_SOFT_RESET__DCRX_DISPCLK_CWB1_SD1_SOFT_RESET_MASK 0x00000002L
++#define DCRX_SOFT_RESET__DCRX_DISPCLK_AUX_SOFT_RESET_MASK 0x00000004L
++#define DCRX_SOFT_RESET__DCRX_DISPCLK_P_SOFT_RESET_MASK 0x00000010L
++#define DCRX_SOFT_RESET__DCRX_SYMCLK_RX_SD0_SOFT_RESET_MASK 0x00000100L
++#define DCRX_SOFT_RESET__DCRX_SYMCLK_RX_SD1_SOFT_RESET_MASK 0x00000200L
++#define DCRX_SOFT_RESET__DCRX_SYMCLK_RX_DPHY_SOFT_RESET_MASK 0x00000400L
++#define DCRX_SOFT_RESET__DCRX_SYMCLK_RX_P_SOFT_RESET_MASK 0x00001000L
++#define DCRX_SOFT_RESET__DCRX_REFCLK_SOFT_RESET_MASK 0x00010000L
++#define DCRX_SOFT_RESET__DCRX_SCLK_SOFT_RESET_MASK 0x00020000L
++//DCRX_LIGHT_SLEEP_CNTL
++#define DCRX_LIGHT_SLEEP_CNTL__DCRX_AUX_LIGHT_SLEEP_DIS__SHIFT 0x0
++#define DCRX_LIGHT_SLEEP_CNTL__DCRX_DPRX_LIGHT_SLEEP_DIS__SHIFT 0x8
++#define DCRX_LIGHT_SLEEP_CNTL__DCRX_AUX_LIGHT_SLEEP_DIS_MASK 0x00000001L
++#define DCRX_LIGHT_SLEEP_CNTL__DCRX_DPRX_LIGHT_SLEEP_DIS_MASK 0x00000100L
++//DCRX_DISPCLK_GATE_CNTL
++#define DCRX_DISPCLK_GATE_CNTL__DCRX_DISPCLK_TURN_ON_DELAY__SHIFT 0x0
++#define DCRX_DISPCLK_GATE_CNTL__DCRX_DISPCLK_TURN_OFF_DELAY__SHIFT 0x4
++#define DCRX_DISPCLK_GATE_CNTL__DCRX_DISPCLK_TURN_ON_DELAY_MASK 0x0000000FL
++#define DCRX_DISPCLK_GATE_CNTL__DCRX_DISPCLK_TURN_OFF_DELAY_MASK 0x00000FF0L
++//DCRX_CLK_CNTL
++#define DCRX_CLK_CNTL__DCRX_SYMCLK_RX_P_ENABLE__SHIFT 0x2
++#define DCRX_CLK_CNTL__DCRX_SYMCLK_RX_P_ENABLE_MASK 0x00000004L
++//DCRX_TEST_CLK_CNTL
++#define DCRX_TEST_CLK_CNTL__DCRX_TEST_CLK_GENERICA_SEL__SHIFT 0x0
++#define DCRX_TEST_CLK_CNTL__DCRX_TEST_CLK_GENERICA_INV__SHIFT 0x7
++#define DCRX_TEST_CLK_CNTL__DCRX_TEST_CLK_GENERICB_SEL__SHIFT 0x8
++#define DCRX_TEST_CLK_CNTL__DCRX_TEST_CLK_GENERICB_INV__SHIFT 0xf
++#define DCRX_TEST_CLK_CNTL__DCRX_TEST_CLK_GENERICA_SEL_MASK 0x0000001FL
++#define DCRX_TEST_CLK_CNTL__DCRX_TEST_CLK_GENERICA_INV_MASK 0x00000080L
++#define DCRX_TEST_CLK_CNTL__DCRX_TEST_CLK_GENERICB_SEL_MASK 0x00001F00L
++#define DCRX_TEST_CLK_CNTL__DCRX_TEST_CLK_GENERICB_INV_MASK 0x00008000L
++//DCRX_PHY_MACRO_CNTL_RESERVED0
++#define DCRX_PHY_MACRO_CNTL_RESERVED0__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED0__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED1
++#define DCRX_PHY_MACRO_CNTL_RESERVED1__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED1__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED2
++#define DCRX_PHY_MACRO_CNTL_RESERVED2__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED2__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED3
++#define DCRX_PHY_MACRO_CNTL_RESERVED3__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED3__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED4
++#define DCRX_PHY_MACRO_CNTL_RESERVED4__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED4__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED5
++#define DCRX_PHY_MACRO_CNTL_RESERVED5__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED5__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED6
++#define DCRX_PHY_MACRO_CNTL_RESERVED6__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED6__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED7
++#define DCRX_PHY_MACRO_CNTL_RESERVED7__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED7__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED8
++#define DCRX_PHY_MACRO_CNTL_RESERVED8__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED8__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED9
++#define DCRX_PHY_MACRO_CNTL_RESERVED9__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED9__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED10
++#define DCRX_PHY_MACRO_CNTL_RESERVED10__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED10__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED11
++#define DCRX_PHY_MACRO_CNTL_RESERVED11__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED11__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED12
++#define DCRX_PHY_MACRO_CNTL_RESERVED12__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED12__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED13
++#define DCRX_PHY_MACRO_CNTL_RESERVED13__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED13__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED14
++#define DCRX_PHY_MACRO_CNTL_RESERVED14__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED14__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED15
++#define DCRX_PHY_MACRO_CNTL_RESERVED15__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED15__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED16
++#define DCRX_PHY_MACRO_CNTL_RESERVED16__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED16__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED17
++#define DCRX_PHY_MACRO_CNTL_RESERVED17__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED17__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED18
++#define DCRX_PHY_MACRO_CNTL_RESERVED18__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED18__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED19
++#define DCRX_PHY_MACRO_CNTL_RESERVED19__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED19__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED20
++#define DCRX_PHY_MACRO_CNTL_RESERVED20__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED20__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED21
++#define DCRX_PHY_MACRO_CNTL_RESERVED21__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED21__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED22
++#define DCRX_PHY_MACRO_CNTL_RESERVED22__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED22__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED23
++#define DCRX_PHY_MACRO_CNTL_RESERVED23__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED23__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED24
++#define DCRX_PHY_MACRO_CNTL_RESERVED24__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED24__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED25
++#define DCRX_PHY_MACRO_CNTL_RESERVED25__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED25__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED26
++#define DCRX_PHY_MACRO_CNTL_RESERVED26__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED26__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED27
++#define DCRX_PHY_MACRO_CNTL_RESERVED27__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED27__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED28
++#define DCRX_PHY_MACRO_CNTL_RESERVED28__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED28__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED29
++#define DCRX_PHY_MACRO_CNTL_RESERVED29__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED29__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED30
++#define DCRX_PHY_MACRO_CNTL_RESERVED30__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED30__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED31
++#define DCRX_PHY_MACRO_CNTL_RESERVED31__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED31__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED32
++#define DCRX_PHY_MACRO_CNTL_RESERVED32__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED32__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED33
++#define DCRX_PHY_MACRO_CNTL_RESERVED33__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED33__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED34
++#define DCRX_PHY_MACRO_CNTL_RESERVED34__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED34__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED35
++#define DCRX_PHY_MACRO_CNTL_RESERVED35__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED35__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED36
++#define DCRX_PHY_MACRO_CNTL_RESERVED36__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED36__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED37
++#define DCRX_PHY_MACRO_CNTL_RESERVED37__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED37__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED38
++#define DCRX_PHY_MACRO_CNTL_RESERVED38__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED38__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED39
++#define DCRX_PHY_MACRO_CNTL_RESERVED39__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED39__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED40
++#define DCRX_PHY_MACRO_CNTL_RESERVED40__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED40__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED41
++#define DCRX_PHY_MACRO_CNTL_RESERVED41__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED41__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED42
++#define DCRX_PHY_MACRO_CNTL_RESERVED42__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED42__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED43
++#define DCRX_PHY_MACRO_CNTL_RESERVED43__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED43__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED44
++#define DCRX_PHY_MACRO_CNTL_RESERVED44__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED44__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED45
++#define DCRX_PHY_MACRO_CNTL_RESERVED45__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED45__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED46
++#define DCRX_PHY_MACRO_CNTL_RESERVED46__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED46__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED47
++#define DCRX_PHY_MACRO_CNTL_RESERVED47__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED47__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED48
++#define DCRX_PHY_MACRO_CNTL_RESERVED48__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED48__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED49
++#define DCRX_PHY_MACRO_CNTL_RESERVED49__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED49__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED50
++#define DCRX_PHY_MACRO_CNTL_RESERVED50__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED50__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED51
++#define DCRX_PHY_MACRO_CNTL_RESERVED51__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED51__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED52
++#define DCRX_PHY_MACRO_CNTL_RESERVED52__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED52__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED53
++#define DCRX_PHY_MACRO_CNTL_RESERVED53__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED53__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED54
++#define DCRX_PHY_MACRO_CNTL_RESERVED54__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED54__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED55
++#define DCRX_PHY_MACRO_CNTL_RESERVED55__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED55__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED56
++#define DCRX_PHY_MACRO_CNTL_RESERVED56__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED56__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED57
++#define DCRX_PHY_MACRO_CNTL_RESERVED57__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED57__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED58
++#define DCRX_PHY_MACRO_CNTL_RESERVED58__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED58__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED59
++#define DCRX_PHY_MACRO_CNTL_RESERVED59__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED59__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED60
++#define DCRX_PHY_MACRO_CNTL_RESERVED60__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED60__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED61
++#define DCRX_PHY_MACRO_CNTL_RESERVED61__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED61__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED62
++#define DCRX_PHY_MACRO_CNTL_RESERVED62__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED62__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED63
++#define DCRX_PHY_MACRO_CNTL_RESERVED63__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED63__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED64
++#define DCRX_PHY_MACRO_CNTL_RESERVED64__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED64__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED65
++#define DCRX_PHY_MACRO_CNTL_RESERVED65__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED65__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED66
++#define DCRX_PHY_MACRO_CNTL_RESERVED66__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED66__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED67
++#define DCRX_PHY_MACRO_CNTL_RESERVED67__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED67__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED68
++#define DCRX_PHY_MACRO_CNTL_RESERVED68__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED68__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED69
++#define DCRX_PHY_MACRO_CNTL_RESERVED69__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED69__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED70
++#define DCRX_PHY_MACRO_CNTL_RESERVED70__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED70__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED71
++#define DCRX_PHY_MACRO_CNTL_RESERVED71__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED71__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED72
++#define DCRX_PHY_MACRO_CNTL_RESERVED72__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED72__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED73
++#define DCRX_PHY_MACRO_CNTL_RESERVED73__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED73__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED74
++#define DCRX_PHY_MACRO_CNTL_RESERVED74__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED74__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED75
++#define DCRX_PHY_MACRO_CNTL_RESERVED75__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED75__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED76
++#define DCRX_PHY_MACRO_CNTL_RESERVED76__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED76__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED77
++#define DCRX_PHY_MACRO_CNTL_RESERVED77__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED77__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED78
++#define DCRX_PHY_MACRO_CNTL_RESERVED78__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED78__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED79
++#define DCRX_PHY_MACRO_CNTL_RESERVED79__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED79__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED80
++#define DCRX_PHY_MACRO_CNTL_RESERVED80__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED80__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED81
++#define DCRX_PHY_MACRO_CNTL_RESERVED81__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED81__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED82
++#define DCRX_PHY_MACRO_CNTL_RESERVED82__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED82__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED83
++#define DCRX_PHY_MACRO_CNTL_RESERVED83__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED83__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED84
++#define DCRX_PHY_MACRO_CNTL_RESERVED84__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED84__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED85
++#define DCRX_PHY_MACRO_CNTL_RESERVED85__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED85__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED86
++#define DCRX_PHY_MACRO_CNTL_RESERVED86__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED86__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED87
++#define DCRX_PHY_MACRO_CNTL_RESERVED87__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED87__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED88
++#define DCRX_PHY_MACRO_CNTL_RESERVED88__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED88__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED89
++#define DCRX_PHY_MACRO_CNTL_RESERVED89__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED89__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED90
++#define DCRX_PHY_MACRO_CNTL_RESERVED90__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED90__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED91
++#define DCRX_PHY_MACRO_CNTL_RESERVED91__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED91__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED92
++#define DCRX_PHY_MACRO_CNTL_RESERVED92__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED92__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED93
++#define DCRX_PHY_MACRO_CNTL_RESERVED93__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED93__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED94
++#define DCRX_PHY_MACRO_CNTL_RESERVED94__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED94__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED95
++#define DCRX_PHY_MACRO_CNTL_RESERVED95__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED95__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED96
++#define DCRX_PHY_MACRO_CNTL_RESERVED96__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED96__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED97
++#define DCRX_PHY_MACRO_CNTL_RESERVED97__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED97__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED98
++#define DCRX_PHY_MACRO_CNTL_RESERVED98__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED98__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED99
++#define DCRX_PHY_MACRO_CNTL_RESERVED99__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED99__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED100
++#define DCRX_PHY_MACRO_CNTL_RESERVED100__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED100__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED101
++#define DCRX_PHY_MACRO_CNTL_RESERVED101__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED101__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED102
++#define DCRX_PHY_MACRO_CNTL_RESERVED102__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED102__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED103
++#define DCRX_PHY_MACRO_CNTL_RESERVED103__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED103__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED104
++#define DCRX_PHY_MACRO_CNTL_RESERVED104__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED104__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED105
++#define DCRX_PHY_MACRO_CNTL_RESERVED105__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED105__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED106
++#define DCRX_PHY_MACRO_CNTL_RESERVED106__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED106__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED107
++#define DCRX_PHY_MACRO_CNTL_RESERVED107__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED107__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED108
++#define DCRX_PHY_MACRO_CNTL_RESERVED108__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED108__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED109
++#define DCRX_PHY_MACRO_CNTL_RESERVED109__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED109__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED110
++#define DCRX_PHY_MACRO_CNTL_RESERVED110__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED110__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED111
++#define DCRX_PHY_MACRO_CNTL_RESERVED111__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED111__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED112
++#define DCRX_PHY_MACRO_CNTL_RESERVED112__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED112__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED113
++#define DCRX_PHY_MACRO_CNTL_RESERVED113__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED113__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED114
++#define DCRX_PHY_MACRO_CNTL_RESERVED114__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED114__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED115
++#define DCRX_PHY_MACRO_CNTL_RESERVED115__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED115__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED116
++#define DCRX_PHY_MACRO_CNTL_RESERVED116__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED116__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED117
++#define DCRX_PHY_MACRO_CNTL_RESERVED117__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED117__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED118
++#define DCRX_PHY_MACRO_CNTL_RESERVED118__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED118__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED119
++#define DCRX_PHY_MACRO_CNTL_RESERVED119__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED119__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED120
++#define DCRX_PHY_MACRO_CNTL_RESERVED120__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED120__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED121
++#define DCRX_PHY_MACRO_CNTL_RESERVED121__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED121__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED122
++#define DCRX_PHY_MACRO_CNTL_RESERVED122__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED122__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED123
++#define DCRX_PHY_MACRO_CNTL_RESERVED123__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED123__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED124
++#define DCRX_PHY_MACRO_CNTL_RESERVED124__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED124__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED125
++#define DCRX_PHY_MACRO_CNTL_RESERVED125__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED125__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED126
++#define DCRX_PHY_MACRO_CNTL_RESERVED126__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED126__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED127
++#define DCRX_PHY_MACRO_CNTL_RESERVED127__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED127__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED128
++#define DCRX_PHY_MACRO_CNTL_RESERVED128__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED128__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED129
++#define DCRX_PHY_MACRO_CNTL_RESERVED129__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED129__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED130
++#define DCRX_PHY_MACRO_CNTL_RESERVED130__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED130__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED131
++#define DCRX_PHY_MACRO_CNTL_RESERVED131__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED131__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED132
++#define DCRX_PHY_MACRO_CNTL_RESERVED132__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED132__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED133
++#define DCRX_PHY_MACRO_CNTL_RESERVED133__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED133__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED134
++#define DCRX_PHY_MACRO_CNTL_RESERVED134__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED134__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED135
++#define DCRX_PHY_MACRO_CNTL_RESERVED135__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED135__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED136
++#define DCRX_PHY_MACRO_CNTL_RESERVED136__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED136__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED137
++#define DCRX_PHY_MACRO_CNTL_RESERVED137__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED137__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED138
++#define DCRX_PHY_MACRO_CNTL_RESERVED138__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED138__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED139
++#define DCRX_PHY_MACRO_CNTL_RESERVED139__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED139__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED140
++#define DCRX_PHY_MACRO_CNTL_RESERVED140__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED140__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED141
++#define DCRX_PHY_MACRO_CNTL_RESERVED141__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED141__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED142
++#define DCRX_PHY_MACRO_CNTL_RESERVED142__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED142__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED143
++#define DCRX_PHY_MACRO_CNTL_RESERVED143__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED143__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED144
++#define DCRX_PHY_MACRO_CNTL_RESERVED144__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED144__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED145
++#define DCRX_PHY_MACRO_CNTL_RESERVED145__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED145__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED146
++#define DCRX_PHY_MACRO_CNTL_RESERVED146__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED146__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED147
++#define DCRX_PHY_MACRO_CNTL_RESERVED147__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED147__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED148
++#define DCRX_PHY_MACRO_CNTL_RESERVED148__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED148__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED149
++#define DCRX_PHY_MACRO_CNTL_RESERVED149__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED149__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED150
++#define DCRX_PHY_MACRO_CNTL_RESERVED150__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED150__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED151
++#define DCRX_PHY_MACRO_CNTL_RESERVED151__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED151__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED152
++#define DCRX_PHY_MACRO_CNTL_RESERVED152__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED152__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED153
++#define DCRX_PHY_MACRO_CNTL_RESERVED153__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED153__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED154
++#define DCRX_PHY_MACRO_CNTL_RESERVED154__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED154__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED155
++#define DCRX_PHY_MACRO_CNTL_RESERVED155__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED155__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED156
++#define DCRX_PHY_MACRO_CNTL_RESERVED156__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED156__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED157
++#define DCRX_PHY_MACRO_CNTL_RESERVED157__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED157__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED158
++#define DCRX_PHY_MACRO_CNTL_RESERVED158__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED158__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED159
++#define DCRX_PHY_MACRO_CNTL_RESERVED159__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED159__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED160
++#define DCRX_PHY_MACRO_CNTL_RESERVED160__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED160__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED161
++#define DCRX_PHY_MACRO_CNTL_RESERVED161__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED161__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED162
++#define DCRX_PHY_MACRO_CNTL_RESERVED162__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED162__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED163
++#define DCRX_PHY_MACRO_CNTL_RESERVED163__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED163__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED164
++#define DCRX_PHY_MACRO_CNTL_RESERVED164__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED164__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED165
++#define DCRX_PHY_MACRO_CNTL_RESERVED165__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED165__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED166
++#define DCRX_PHY_MACRO_CNTL_RESERVED166__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED166__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED167
++#define DCRX_PHY_MACRO_CNTL_RESERVED167__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED167__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED168
++#define DCRX_PHY_MACRO_CNTL_RESERVED168__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED168__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED169
++#define DCRX_PHY_MACRO_CNTL_RESERVED169__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED169__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED170
++#define DCRX_PHY_MACRO_CNTL_RESERVED170__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED170__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED171
++#define DCRX_PHY_MACRO_CNTL_RESERVED171__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED171__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED172
++#define DCRX_PHY_MACRO_CNTL_RESERVED172__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED172__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED173
++#define DCRX_PHY_MACRO_CNTL_RESERVED173__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED173__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED174
++#define DCRX_PHY_MACRO_CNTL_RESERVED174__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED174__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED175
++#define DCRX_PHY_MACRO_CNTL_RESERVED175__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED175__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED176
++#define DCRX_PHY_MACRO_CNTL_RESERVED176__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED176__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED177
++#define DCRX_PHY_MACRO_CNTL_RESERVED177__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED177__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED178
++#define DCRX_PHY_MACRO_CNTL_RESERVED178__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED178__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED179
++#define DCRX_PHY_MACRO_CNTL_RESERVED179__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED179__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED180
++#define DCRX_PHY_MACRO_CNTL_RESERVED180__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED180__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED181
++#define DCRX_PHY_MACRO_CNTL_RESERVED181__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED181__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED182
++#define DCRX_PHY_MACRO_CNTL_RESERVED182__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED182__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED183
++#define DCRX_PHY_MACRO_CNTL_RESERVED183__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED183__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED184
++#define DCRX_PHY_MACRO_CNTL_RESERVED184__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED184__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED185
++#define DCRX_PHY_MACRO_CNTL_RESERVED185__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED185__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED186
++#define DCRX_PHY_MACRO_CNTL_RESERVED186__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED186__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED187
++#define DCRX_PHY_MACRO_CNTL_RESERVED187__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED187__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED188
++#define DCRX_PHY_MACRO_CNTL_RESERVED188__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED188__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED189
++#define DCRX_PHY_MACRO_CNTL_RESERVED189__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED189__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED190
++#define DCRX_PHY_MACRO_CNTL_RESERVED190__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED190__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED191
++#define DCRX_PHY_MACRO_CNTL_RESERVED191__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED191__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED192
++#define DCRX_PHY_MACRO_CNTL_RESERVED192__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED192__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED193
++#define DCRX_PHY_MACRO_CNTL_RESERVED193__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED193__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED194
++#define DCRX_PHY_MACRO_CNTL_RESERVED194__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED194__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED195
++#define DCRX_PHY_MACRO_CNTL_RESERVED195__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED195__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED196
++#define DCRX_PHY_MACRO_CNTL_RESERVED196__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED196__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED197
++#define DCRX_PHY_MACRO_CNTL_RESERVED197__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED197__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED198
++#define DCRX_PHY_MACRO_CNTL_RESERVED198__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED198__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED199
++#define DCRX_PHY_MACRO_CNTL_RESERVED199__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED199__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED200
++#define DCRX_PHY_MACRO_CNTL_RESERVED200__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED200__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED201
++#define DCRX_PHY_MACRO_CNTL_RESERVED201__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED201__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED202
++#define DCRX_PHY_MACRO_CNTL_RESERVED202__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED202__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED203
++#define DCRX_PHY_MACRO_CNTL_RESERVED203__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED203__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED204
++#define DCRX_PHY_MACRO_CNTL_RESERVED204__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED204__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED205
++#define DCRX_PHY_MACRO_CNTL_RESERVED205__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED205__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED206
++#define DCRX_PHY_MACRO_CNTL_RESERVED206__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED206__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED207
++#define DCRX_PHY_MACRO_CNTL_RESERVED207__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED207__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED208
++#define DCRX_PHY_MACRO_CNTL_RESERVED208__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED208__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED209
++#define DCRX_PHY_MACRO_CNTL_RESERVED209__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED209__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED210
++#define DCRX_PHY_MACRO_CNTL_RESERVED210__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED210__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED211
++#define DCRX_PHY_MACRO_CNTL_RESERVED211__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED211__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED212
++#define DCRX_PHY_MACRO_CNTL_RESERVED212__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED212__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED213
++#define DCRX_PHY_MACRO_CNTL_RESERVED213__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED213__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED214
++#define DCRX_PHY_MACRO_CNTL_RESERVED214__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED214__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED215
++#define DCRX_PHY_MACRO_CNTL_RESERVED215__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED215__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED216
++#define DCRX_PHY_MACRO_CNTL_RESERVED216__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED216__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED217
++#define DCRX_PHY_MACRO_CNTL_RESERVED217__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED217__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED218
++#define DCRX_PHY_MACRO_CNTL_RESERVED218__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED218__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED219
++#define DCRX_PHY_MACRO_CNTL_RESERVED219__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED219__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED220
++#define DCRX_PHY_MACRO_CNTL_RESERVED220__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED220__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED221
++#define DCRX_PHY_MACRO_CNTL_RESERVED221__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED221__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED222
++#define DCRX_PHY_MACRO_CNTL_RESERVED222__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED222__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED223
++#define DCRX_PHY_MACRO_CNTL_RESERVED223__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED223__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED224
++#define DCRX_PHY_MACRO_CNTL_RESERVED224__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED224__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED225
++#define DCRX_PHY_MACRO_CNTL_RESERVED225__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED225__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED226
++#define DCRX_PHY_MACRO_CNTL_RESERVED226__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED226__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED227
++#define DCRX_PHY_MACRO_CNTL_RESERVED227__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED227__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED228
++#define DCRX_PHY_MACRO_CNTL_RESERVED228__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED228__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED229
++#define DCRX_PHY_MACRO_CNTL_RESERVED229__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED229__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED230
++#define DCRX_PHY_MACRO_CNTL_RESERVED230__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED230__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED231
++#define DCRX_PHY_MACRO_CNTL_RESERVED231__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED231__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED232
++#define DCRX_PHY_MACRO_CNTL_RESERVED232__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED232__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED233
++#define DCRX_PHY_MACRO_CNTL_RESERVED233__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED233__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED234
++#define DCRX_PHY_MACRO_CNTL_RESERVED234__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED234__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED235
++#define DCRX_PHY_MACRO_CNTL_RESERVED235__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED235__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED236
++#define DCRX_PHY_MACRO_CNTL_RESERVED236__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED236__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED237
++#define DCRX_PHY_MACRO_CNTL_RESERVED237__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED237__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED238
++#define DCRX_PHY_MACRO_CNTL_RESERVED238__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED238__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED239
++#define DCRX_PHY_MACRO_CNTL_RESERVED239__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED239__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED240
++#define DCRX_PHY_MACRO_CNTL_RESERVED240__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED240__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED241
++#define DCRX_PHY_MACRO_CNTL_RESERVED241__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED241__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED242
++#define DCRX_PHY_MACRO_CNTL_RESERVED242__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED242__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED243
++#define DCRX_PHY_MACRO_CNTL_RESERVED243__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED243__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED244
++#define DCRX_PHY_MACRO_CNTL_RESERVED244__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED244__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED245
++#define DCRX_PHY_MACRO_CNTL_RESERVED245__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED245__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED246
++#define DCRX_PHY_MACRO_CNTL_RESERVED246__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED246__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED247
++#define DCRX_PHY_MACRO_CNTL_RESERVED247__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED247__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED248
++#define DCRX_PHY_MACRO_CNTL_RESERVED248__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED248__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED249
++#define DCRX_PHY_MACRO_CNTL_RESERVED249__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED249__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED250
++#define DCRX_PHY_MACRO_CNTL_RESERVED250__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED250__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED251
++#define DCRX_PHY_MACRO_CNTL_RESERVED251__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED251__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED252
++#define DCRX_PHY_MACRO_CNTL_RESERVED252__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED252__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED253
++#define DCRX_PHY_MACRO_CNTL_RESERVED253__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED253__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED254
++#define DCRX_PHY_MACRO_CNTL_RESERVED254__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED254__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED255
++#define DCRX_PHY_MACRO_CNTL_RESERVED255__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED255__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED256
++#define DCRX_PHY_MACRO_CNTL_RESERVED256__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED256__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED257
++#define DCRX_PHY_MACRO_CNTL_RESERVED257__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED257__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED258
++#define DCRX_PHY_MACRO_CNTL_RESERVED258__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED258__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED259
++#define DCRX_PHY_MACRO_CNTL_RESERVED259__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED259__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED260
++#define DCRX_PHY_MACRO_CNTL_RESERVED260__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED260__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED261
++#define DCRX_PHY_MACRO_CNTL_RESERVED261__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED261__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED262
++#define DCRX_PHY_MACRO_CNTL_RESERVED262__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED262__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED263
++#define DCRX_PHY_MACRO_CNTL_RESERVED263__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED263__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED264
++#define DCRX_PHY_MACRO_CNTL_RESERVED264__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED264__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED265
++#define DCRX_PHY_MACRO_CNTL_RESERVED265__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED265__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED266
++#define DCRX_PHY_MACRO_CNTL_RESERVED266__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED266__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED267
++#define DCRX_PHY_MACRO_CNTL_RESERVED267__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED267__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED268
++#define DCRX_PHY_MACRO_CNTL_RESERVED268__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED268__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED269
++#define DCRX_PHY_MACRO_CNTL_RESERVED269__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED269__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED270
++#define DCRX_PHY_MACRO_CNTL_RESERVED270__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED270__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED271
++#define DCRX_PHY_MACRO_CNTL_RESERVED271__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED271__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED272
++#define DCRX_PHY_MACRO_CNTL_RESERVED272__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED272__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED273
++#define DCRX_PHY_MACRO_CNTL_RESERVED273__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED273__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED274
++#define DCRX_PHY_MACRO_CNTL_RESERVED274__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED274__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED275
++#define DCRX_PHY_MACRO_CNTL_RESERVED275__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED275__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED276
++#define DCRX_PHY_MACRO_CNTL_RESERVED276__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED276__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED277
++#define DCRX_PHY_MACRO_CNTL_RESERVED277__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED277__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED278
++#define DCRX_PHY_MACRO_CNTL_RESERVED278__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED278__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED279
++#define DCRX_PHY_MACRO_CNTL_RESERVED279__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED279__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED280
++#define DCRX_PHY_MACRO_CNTL_RESERVED280__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED280__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED281
++#define DCRX_PHY_MACRO_CNTL_RESERVED281__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED281__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED282
++#define DCRX_PHY_MACRO_CNTL_RESERVED282__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED282__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED283
++#define DCRX_PHY_MACRO_CNTL_RESERVED283__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED283__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED284
++#define DCRX_PHY_MACRO_CNTL_RESERVED284__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED284__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED285
++#define DCRX_PHY_MACRO_CNTL_RESERVED285__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED285__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED286
++#define DCRX_PHY_MACRO_CNTL_RESERVED286__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED286__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED287
++#define DCRX_PHY_MACRO_CNTL_RESERVED287__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED287__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED288
++#define DCRX_PHY_MACRO_CNTL_RESERVED288__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED288__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED289
++#define DCRX_PHY_MACRO_CNTL_RESERVED289__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED289__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED290
++#define DCRX_PHY_MACRO_CNTL_RESERVED290__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED290__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED291
++#define DCRX_PHY_MACRO_CNTL_RESERVED291__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED291__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED292
++#define DCRX_PHY_MACRO_CNTL_RESERVED292__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED292__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED293
++#define DCRX_PHY_MACRO_CNTL_RESERVED293__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED293__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED294
++#define DCRX_PHY_MACRO_CNTL_RESERVED294__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED294__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED295
++#define DCRX_PHY_MACRO_CNTL_RESERVED295__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED295__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED296
++#define DCRX_PHY_MACRO_CNTL_RESERVED296__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED296__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED297
++#define DCRX_PHY_MACRO_CNTL_RESERVED297__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED297__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED298
++#define DCRX_PHY_MACRO_CNTL_RESERVED298__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED298__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED299
++#define DCRX_PHY_MACRO_CNTL_RESERVED299__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED299__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED300
++#define DCRX_PHY_MACRO_CNTL_RESERVED300__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED300__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED301
++#define DCRX_PHY_MACRO_CNTL_RESERVED301__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED301__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED302
++#define DCRX_PHY_MACRO_CNTL_RESERVED302__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED302__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED303
++#define DCRX_PHY_MACRO_CNTL_RESERVED303__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED303__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED304
++#define DCRX_PHY_MACRO_CNTL_RESERVED304__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED304__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED305
++#define DCRX_PHY_MACRO_CNTL_RESERVED305__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED305__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED306
++#define DCRX_PHY_MACRO_CNTL_RESERVED306__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED306__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED307
++#define DCRX_PHY_MACRO_CNTL_RESERVED307__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED307__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED308
++#define DCRX_PHY_MACRO_CNTL_RESERVED308__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED308__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED309
++#define DCRX_PHY_MACRO_CNTL_RESERVED309__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED309__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED310
++#define DCRX_PHY_MACRO_CNTL_RESERVED310__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED310__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED311
++#define DCRX_PHY_MACRO_CNTL_RESERVED311__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED311__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED312
++#define DCRX_PHY_MACRO_CNTL_RESERVED312__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED312__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED313
++#define DCRX_PHY_MACRO_CNTL_RESERVED313__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED313__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED314
++#define DCRX_PHY_MACRO_CNTL_RESERVED314__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED314__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED315
++#define DCRX_PHY_MACRO_CNTL_RESERVED315__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED315__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED316
++#define DCRX_PHY_MACRO_CNTL_RESERVED316__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED316__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED317
++#define DCRX_PHY_MACRO_CNTL_RESERVED317__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED317__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED318
++#define DCRX_PHY_MACRO_CNTL_RESERVED318__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED318__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED319
++#define DCRX_PHY_MACRO_CNTL_RESERVED319__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED319__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED320
++#define DCRX_PHY_MACRO_CNTL_RESERVED320__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED320__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED321
++#define DCRX_PHY_MACRO_CNTL_RESERVED321__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED321__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED322
++#define DCRX_PHY_MACRO_CNTL_RESERVED322__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED322__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED323
++#define DCRX_PHY_MACRO_CNTL_RESERVED323__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED323__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED324
++#define DCRX_PHY_MACRO_CNTL_RESERVED324__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED324__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED325
++#define DCRX_PHY_MACRO_CNTL_RESERVED325__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED325__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED326
++#define DCRX_PHY_MACRO_CNTL_RESERVED326__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED326__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED327
++#define DCRX_PHY_MACRO_CNTL_RESERVED327__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED327__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED328
++#define DCRX_PHY_MACRO_CNTL_RESERVED328__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED328__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED329
++#define DCRX_PHY_MACRO_CNTL_RESERVED329__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED329__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED330
++#define DCRX_PHY_MACRO_CNTL_RESERVED330__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED330__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED331
++#define DCRX_PHY_MACRO_CNTL_RESERVED331__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED331__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED332
++#define DCRX_PHY_MACRO_CNTL_RESERVED332__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED332__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED333
++#define DCRX_PHY_MACRO_CNTL_RESERVED333__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED333__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED334
++#define DCRX_PHY_MACRO_CNTL_RESERVED334__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED334__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED335
++#define DCRX_PHY_MACRO_CNTL_RESERVED335__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED335__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED336
++#define DCRX_PHY_MACRO_CNTL_RESERVED336__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED336__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED337
++#define DCRX_PHY_MACRO_CNTL_RESERVED337__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED337__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED338
++#define DCRX_PHY_MACRO_CNTL_RESERVED338__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED338__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED339
++#define DCRX_PHY_MACRO_CNTL_RESERVED339__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED339__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED340
++#define DCRX_PHY_MACRO_CNTL_RESERVED340__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED340__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED341
++#define DCRX_PHY_MACRO_CNTL_RESERVED341__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED341__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED342
++#define DCRX_PHY_MACRO_CNTL_RESERVED342__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED342__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED343
++#define DCRX_PHY_MACRO_CNTL_RESERVED343__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED343__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED344
++#define DCRX_PHY_MACRO_CNTL_RESERVED344__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED344__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED345
++#define DCRX_PHY_MACRO_CNTL_RESERVED345__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED345__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED346
++#define DCRX_PHY_MACRO_CNTL_RESERVED346__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED346__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED347
++#define DCRX_PHY_MACRO_CNTL_RESERVED347__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED347__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED348
++#define DCRX_PHY_MACRO_CNTL_RESERVED348__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED348__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED349
++#define DCRX_PHY_MACRO_CNTL_RESERVED349__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED349__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED350
++#define DCRX_PHY_MACRO_CNTL_RESERVED350__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED350__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED351
++#define DCRX_PHY_MACRO_CNTL_RESERVED351__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED351__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED352
++#define DCRX_PHY_MACRO_CNTL_RESERVED352__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED352__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED353
++#define DCRX_PHY_MACRO_CNTL_RESERVED353__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED353__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED354
++#define DCRX_PHY_MACRO_CNTL_RESERVED354__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED354__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED355
++#define DCRX_PHY_MACRO_CNTL_RESERVED355__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED355__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED356
++#define DCRX_PHY_MACRO_CNTL_RESERVED356__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED356__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED357
++#define DCRX_PHY_MACRO_CNTL_RESERVED357__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED357__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED358
++#define DCRX_PHY_MACRO_CNTL_RESERVED358__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED358__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED359
++#define DCRX_PHY_MACRO_CNTL_RESERVED359__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED359__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED360
++#define DCRX_PHY_MACRO_CNTL_RESERVED360__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED360__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED361
++#define DCRX_PHY_MACRO_CNTL_RESERVED361__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED361__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED362
++#define DCRX_PHY_MACRO_CNTL_RESERVED362__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED362__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED363
++#define DCRX_PHY_MACRO_CNTL_RESERVED363__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED363__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED364
++#define DCRX_PHY_MACRO_CNTL_RESERVED364__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED364__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED365
++#define DCRX_PHY_MACRO_CNTL_RESERVED365__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED365__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED366
++#define DCRX_PHY_MACRO_CNTL_RESERVED366__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED366__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED367
++#define DCRX_PHY_MACRO_CNTL_RESERVED367__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED367__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED368
++#define DCRX_PHY_MACRO_CNTL_RESERVED368__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED368__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED369
++#define DCRX_PHY_MACRO_CNTL_RESERVED369__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED369__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED370
++#define DCRX_PHY_MACRO_CNTL_RESERVED370__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED370__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED371
++#define DCRX_PHY_MACRO_CNTL_RESERVED371__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED371__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED372
++#define DCRX_PHY_MACRO_CNTL_RESERVED372__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED372__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED373
++#define DCRX_PHY_MACRO_CNTL_RESERVED373__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED373__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED374
++#define DCRX_PHY_MACRO_CNTL_RESERVED374__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED374__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED375
++#define DCRX_PHY_MACRO_CNTL_RESERVED375__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED375__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED376
++#define DCRX_PHY_MACRO_CNTL_RESERVED376__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED376__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED377
++#define DCRX_PHY_MACRO_CNTL_RESERVED377__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED377__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED378
++#define DCRX_PHY_MACRO_CNTL_RESERVED378__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED378__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCRX_PHY_MACRO_CNTL_RESERVED379
++#define DCRX_PHY_MACRO_CNTL_RESERVED379__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED379__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//I2S0_CNTL
++#define I2S0_CNTL__I2S0_WORD_SIZE__SHIFT 0x0
++#define I2S0_CNTL__I2S0_SAMPLE_ALIGNMENT__SHIFT 0x4
++#define I2S0_CNTL__I2S0_SAMPLE_BIT_ORDER__SHIFT 0x8
++#define I2S0_CNTL__I2S0_LRCLK_POLARITY__SHIFT 0xc
++#define I2S0_CNTL__I2S0_WORD_ALIGNMENT__SHIFT 0x10
++#define I2S0_CNTL__I2S0_ENABLE__SHIFT 0x1a
++#define I2S0_CNTL__I2S0_FIFO_START_ADDR__SHIFT 0x1e
++#define I2S0_CNTL__I2S0_WORD_SIZE_MASK 0x00000001L
++#define I2S0_CNTL__I2S0_SAMPLE_ALIGNMENT_MASK 0x00000010L
++#define I2S0_CNTL__I2S0_SAMPLE_BIT_ORDER_MASK 0x00000100L
++#define I2S0_CNTL__I2S0_LRCLK_POLARITY_MASK 0x00001000L
++#define I2S0_CNTL__I2S0_WORD_ALIGNMENT_MASK 0x00010000L
++#define I2S0_CNTL__I2S0_ENABLE_MASK 0x04000000L
++#define I2S0_CNTL__I2S0_FIFO_START_ADDR_MASK 0x40000000L
++//SPDIF0_CNTL
++#define SPDIF0_CNTL__SPDIF0_EN__SHIFT 0x0
++#define SPDIF0_CNTL__SPDIF0_FIFO_START_ADDR__SHIFT 0x4
++#define SPDIF0_CNTL__SPDIF0_EN_MASK 0x00000001L
++#define SPDIF0_CNTL__SPDIF0_FIFO_START_ADDR_MASK 0x00000010L
++//I2S1_CNTL
++#define I2S1_CNTL__I2S1_WORD_SIZE__SHIFT 0x0
++#define I2S1_CNTL__I2S1_SAMPLE_ALIGNMENT__SHIFT 0x4
++#define I2S1_CNTL__I2S1_SAMPLE_BIT_ORDER__SHIFT 0x8
++#define I2S1_CNTL__I2S1_LRCLK_POLARITY__SHIFT 0xc
++#define I2S1_CNTL__I2S1_WORD_ALIGNMENT__SHIFT 0x10
++#define I2S1_CNTL__I2S1_ENABLE__SHIFT 0x1a
++#define I2S1_CNTL__I2S1_FIFO_START_ADDR__SHIFT 0x1e
++#define I2S1_CNTL__I2S1_WORD_SIZE_MASK 0x00000001L
++#define I2S1_CNTL__I2S1_SAMPLE_ALIGNMENT_MASK 0x00000010L
++#define I2S1_CNTL__I2S1_SAMPLE_BIT_ORDER_MASK 0x00000100L
++#define I2S1_CNTL__I2S1_LRCLK_POLARITY_MASK 0x00001000L
++#define I2S1_CNTL__I2S1_WORD_ALIGNMENT_MASK 0x00010000L
++#define I2S1_CNTL__I2S1_ENABLE_MASK 0x04000000L
++#define I2S1_CNTL__I2S1_FIFO_START_ADDR_MASK 0x40000000L
++//SPDIF1_CNTL
++#define SPDIF1_CNTL__SPDIF1_EN__SHIFT 0x0
++#define SPDIF1_CNTL__SPDIF1_FIFO_START_ADDR__SHIFT 0x4
++#define SPDIF1_CNTL__SPDIF1_INVERT_EN__SHIFT 0x8
++#define SPDIF1_CNTL__SPDIF1_EN_MASK 0x00000001L
++#define SPDIF1_CNTL__SPDIF1_FIFO_START_ADDR_MASK 0x00000010L
++#define SPDIF1_CNTL__SPDIF1_INVERT_EN_MASK 0x00000100L
++//I2S0_STATUS
++#define I2S0_STATUS__STREAM0_AUDIO_ENABLE__SHIFT 0x0
++#define I2S0_STATUS__STREAM0_IDLE__SHIFT 0x1
++#define I2S0_STATUS__I2S0_DATA_RDY__SHIFT 0x2
++#define I2S0_STATUS__I2S0_SAMPLE_RATE__SHIFT 0x3
++#define I2S0_STATUS__STREAM0_AUDIO_ENABLE_MASK 0x00000001L
++#define I2S0_STATUS__STREAM0_IDLE_MASK 0x00000002L
++#define I2S0_STATUS__I2S0_DATA_RDY_MASK 0x00000004L
++#define I2S0_STATUS__I2S0_SAMPLE_RATE_MASK 0x00000038L
++//I2S1_STATUS
++#define I2S1_STATUS__STREAM1_AUDIO_ENABLE__SHIFT 0x0
++#define I2S1_STATUS__STREAM1_IDLE__SHIFT 0x1
++#define I2S1_STATUS__I2S1_DATA_RDY__SHIFT 0x2
++#define I2S1_STATUS__I2S1_SAMPLE_RATE__SHIFT 0x3
++#define I2S1_STATUS__STREAM1_AUDIO_ENABLE_MASK 0x00000001L
++#define I2S1_STATUS__STREAM1_IDLE_MASK 0x00000002L
++#define I2S1_STATUS__I2S1_DATA_RDY_MASK 0x00000004L
++#define I2S1_STATUS__I2S1_SAMPLE_RATE_MASK 0x00000038L
++//I2S0_CRC_TEST_CNTL
++#define I2S0_CRC_TEST_CNTL__I2S0_CRC_TEST_EN__SHIFT 0x0
++#define I2S0_CRC_TEST_CNTL__I2S0_CRC_SOFT_RESET__SHIFT 0x1
++#define I2S0_CRC_TEST_CNTL__I2S0_CRC_TEST_CONT_EN__SHIFT 0x4
++#define I2S0_CRC_TEST_CNTL__I2S0_CRC_TEST_NUMBER_OF_SAMPLES__SHIFT 0x8
++#define I2S0_CRC_TEST_CNTL__I2S0_CRC_TEST_EN_MASK 0x00000001L
++#define I2S0_CRC_TEST_CNTL__I2S0_CRC_SOFT_RESET_MASK 0x00000002L
++#define I2S0_CRC_TEST_CNTL__I2S0_CRC_TEST_CONT_EN_MASK 0x00000010L
++#define I2S0_CRC_TEST_CNTL__I2S0_CRC_TEST_NUMBER_OF_SAMPLES_MASK 0xFFFFFF00L
++//I2S0_CRC_TEST_DATA_01
++#define I2S0_CRC_TEST_DATA_01__I2S0_CRC_TEST_DATA0__SHIFT 0x0
++#define I2S0_CRC_TEST_DATA_01__I2S0_CRC_TEST_DATA1__SHIFT 0x10
++#define I2S0_CRC_TEST_DATA_01__I2S0_CRC_TEST_DATA0_MASK 0x0000FFFFL
++#define I2S0_CRC_TEST_DATA_01__I2S0_CRC_TEST_DATA1_MASK 0xFFFF0000L
++//I2S0_CRC_TEST_DATA_23
++#define I2S0_CRC_TEST_DATA_23__I2S0_CRC_TEST_DATA2__SHIFT 0x0
++#define I2S0_CRC_TEST_DATA_23__I2S0_CRC_TEST_DATA3__SHIFT 0x10
++#define I2S0_CRC_TEST_DATA_23__I2S0_CRC_TEST_DATA2_MASK 0x0000FFFFL
++#define I2S0_CRC_TEST_DATA_23__I2S0_CRC_TEST_DATA3_MASK 0xFFFF0000L
++//I2S1_CRC_TEST_CNTL
++#define I2S1_CRC_TEST_CNTL__I2S1_CRC_TEST_EN__SHIFT 0x0
++#define I2S1_CRC_TEST_CNTL__I2S1_CRC_SOFT_RESET__SHIFT 0x1
++#define I2S1_CRC_TEST_CNTL__I2S1_CRC_TEST_CONT_EN__SHIFT 0x4
++#define I2S1_CRC_TEST_CNTL__I2S1_CRC_TEST_NUMBER_OF_SAMPLES__SHIFT 0x8
++#define I2S1_CRC_TEST_CNTL__I2S1_CRC_TEST_EN_MASK 0x00000001L
++#define I2S1_CRC_TEST_CNTL__I2S1_CRC_SOFT_RESET_MASK 0x00000002L
++#define I2S1_CRC_TEST_CNTL__I2S1_CRC_TEST_CONT_EN_MASK 0x00000010L
++#define I2S1_CRC_TEST_CNTL__I2S1_CRC_TEST_NUMBER_OF_SAMPLES_MASK 0xFFFFFF00L
++//I2S1_CRC_TEST_DATA_0
++#define I2S1_CRC_TEST_DATA_0__I2S1_CRC_TEST_DATA0__SHIFT 0x0
++#define I2S1_CRC_TEST_DATA_0__I2S1_CRC_TEST_DATA0_MASK 0x0000FFFFL
++//SPDIF0_CRC_TEST_CNTL
++#define SPDIF0_CRC_TEST_CNTL__SPDIF0_CRC_TEST_EN__SHIFT 0x0
++#define SPDIF0_CRC_TEST_CNTL__SPDIF0_CRC_SOFT_RESET__SHIFT 0x1
++#define SPDIF0_CRC_TEST_CNTL__SPDIF0_CRC_TEST_CONT_EN__SHIFT 0x4
++#define SPDIF0_CRC_TEST_CNTL__SPDIF0_CRC_TEST_NUMBER_OF_SAMPLES__SHIFT 0x8
++#define SPDIF0_CRC_TEST_CNTL__SPDIF0_CRC_TEST_EN_MASK 0x00000001L
++#define SPDIF0_CRC_TEST_CNTL__SPDIF0_CRC_SOFT_RESET_MASK 0x00000002L
++#define SPDIF0_CRC_TEST_CNTL__SPDIF0_CRC_TEST_CONT_EN_MASK 0x00000010L
++#define SPDIF0_CRC_TEST_CNTL__SPDIF0_CRC_TEST_NUMBER_OF_SAMPLES_MASK 0xFFFFFF00L
++//SPDIF0_CRC_TEST_DATA_0
++#define SPDIF0_CRC_TEST_DATA_0__SPDIF0_CRC_TEST_DATA0__SHIFT 0x0
++#define SPDIF0_CRC_TEST_DATA_0__SPDIF0_CRC_TEST_DATA0_MASK 0x0000FFFFL
++//SPDIF1_CRC_TEST_CNTL
++#define SPDIF1_CRC_TEST_CNTL__SPDIF1_CRC_TEST_EN__SHIFT 0x0
++#define SPDIF1_CRC_TEST_CNTL__SPDIF1_CRC_SOFT_RESET__SHIFT 0x1
++#define SPDIF1_CRC_TEST_CNTL__SPDIF1_CRC_TEST_CONT_EN__SHIFT 0x4
++#define SPDIF1_CRC_TEST_CNTL__SPDIF1_CRC_TEST_NUMBER_OF_SAMPLES__SHIFT 0x8
++#define SPDIF1_CRC_TEST_CNTL__SPDIF1_CRC_TEST_EN_MASK 0x00000001L
++#define SPDIF1_CRC_TEST_CNTL__SPDIF1_CRC_SOFT_RESET_MASK 0x00000002L
++#define SPDIF1_CRC_TEST_CNTL__SPDIF1_CRC_TEST_CONT_EN_MASK 0x00000010L
++#define SPDIF1_CRC_TEST_CNTL__SPDIF1_CRC_TEST_NUMBER_OF_SAMPLES_MASK 0xFFFFFF00L
++//SPDIF1_CRC_TEST_DATA
++#define SPDIF1_CRC_TEST_DATA__SPDIF1_CRC_TEST_DATA__SHIFT 0x0
++#define SPDIF1_CRC_TEST_DATA__SPDIF1_CRC_TEST_DATA_MASK 0x0000FFFFL
++//CRC_I2S_CONT_REPEAT_NUM
++#define CRC_I2S_CONT_REPEAT_NUM__I2S0_CRC_CONT_REPEAT_NUM__SHIFT 0x0
++#define CRC_I2S_CONT_REPEAT_NUM__I2S1_CRC_CONT_REPEAT_NUM__SHIFT 0x10
++#define CRC_I2S_CONT_REPEAT_NUM__I2S0_CRC_CONT_REPEAT_NUM_MASK 0x0000FFFFL
++#define CRC_I2S_CONT_REPEAT_NUM__I2S1_CRC_CONT_REPEAT_NUM_MASK 0xFFFF0000L
++//CRC_SPDIF_CONT_REPEAT_NUM
++#define CRC_SPDIF_CONT_REPEAT_NUM__SPDIF0_CRC_CONT_REPEAT_NUM__SHIFT 0x0
++#define CRC_SPDIF_CONT_REPEAT_NUM__SPDIF1_CRC_CONT_REPEAT_NUM__SHIFT 0x10
++#define CRC_SPDIF_CONT_REPEAT_NUM__SPDIF0_CRC_CONT_REPEAT_NUM_MASK 0x0000FFFFL
++#define CRC_SPDIF_CONT_REPEAT_NUM__SPDIF1_CRC_CONT_REPEAT_NUM_MASK 0xFFFF0000L
++//ZCAL_MACRO_CNTL_RESERVED0
++#define ZCAL_MACRO_CNTL_RESERVED0__ZCAL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define ZCAL_MACRO_CNTL_RESERVED0__ZCAL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//ZCAL_MACRO_CNTL_RESERVED1
++#define ZCAL_MACRO_CNTL_RESERVED1__ZCAL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define ZCAL_MACRO_CNTL_RESERVED1__ZCAL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//ZCAL_MACRO_CNTL_RESERVED2
++#define ZCAL_MACRO_CNTL_RESERVED2__ZCAL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define ZCAL_MACRO_CNTL_RESERVED2__ZCAL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//ZCAL_MACRO_CNTL_RESERVED3
++#define ZCAL_MACRO_CNTL_RESERVED3__ZCAL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define ZCAL_MACRO_CNTL_RESERVED3__ZCAL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//ZCAL_MACRO_CNTL_RESERVED4
++#define ZCAL_MACRO_CNTL_RESERVED4__ZCAL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define ZCAL_MACRO_CNTL_RESERVED4__ZCAL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_azf0stream0_dispdec
++//AZF0STREAM0_AZALIA_STREAM_INDEX
++#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
++#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
++#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
++#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
++//AZF0STREAM0_AZALIA_STREAM_DATA
++#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
++#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_azf0stream1_dispdec
++//AZF0STREAM1_AZALIA_STREAM_INDEX
++#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
++#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
++#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
++#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
++//AZF0STREAM1_AZALIA_STREAM_DATA
++#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
++#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_azf0stream2_dispdec
++//AZF0STREAM2_AZALIA_STREAM_INDEX
++#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
++#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
++#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
++#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
++//AZF0STREAM2_AZALIA_STREAM_DATA
++#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
++#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_azf0stream3_dispdec
++//AZF0STREAM3_AZALIA_STREAM_INDEX
++#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
++#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
++#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
++#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
++//AZF0STREAM3_AZALIA_STREAM_DATA
++#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
++#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_azf0stream4_dispdec
++//AZF0STREAM4_AZALIA_STREAM_INDEX
++#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
++#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
++#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
++#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
++//AZF0STREAM4_AZALIA_STREAM_DATA
++#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
++#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_azf0stream5_dispdec
++//AZF0STREAM5_AZALIA_STREAM_INDEX
++#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
++#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
++#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
++#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
++//AZF0STREAM5_AZALIA_STREAM_DATA
++#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
++#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_azf0stream6_dispdec
++//AZF0STREAM6_AZALIA_STREAM_INDEX
++#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
++#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
++#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
++#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
++//AZF0STREAM6_AZALIA_STREAM_DATA
++#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
++#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_azf0stream7_dispdec
++//AZF0STREAM7_AZALIA_STREAM_INDEX
++#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
++#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
++#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
++#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
++//AZF0STREAM7_AZALIA_STREAM_DATA
++#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
++#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_azf0endpoint0_dispdec
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_azf0endpoint1_dispdec
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_azf0endpoint2_dispdec
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_azf0endpoint3_dispdec
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_azf0endpoint4_dispdec
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_azf0endpoint5_dispdec
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_azf0endpoint6_dispdec
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_azf0endpoint7_dispdec
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_azf0stream8_dispdec
++//AZF0STREAM8_AZALIA_STREAM_INDEX
++#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
++#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
++#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
++#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
++//AZF0STREAM8_AZALIA_STREAM_DATA
++#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
++#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_azf0stream9_dispdec
++//AZF0STREAM9_AZALIA_STREAM_INDEX
++#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
++#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
++#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
++#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
++//AZF0STREAM9_AZALIA_STREAM_DATA
++#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
++#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_azf0stream10_dispdec
++//AZF0STREAM10_AZALIA_STREAM_INDEX
++#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
++#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
++#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
++#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
++//AZF0STREAM10_AZALIA_STREAM_DATA
++#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
++#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_azf0stream11_dispdec
++//AZF0STREAM11_AZALIA_STREAM_INDEX
++#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
++#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
++#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
++#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
++//AZF0STREAM11_AZALIA_STREAM_DATA
++#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
++#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_azf0stream12_dispdec
++//AZF0STREAM12_AZALIA_STREAM_INDEX
++#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
++#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
++#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
++#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
++//AZF0STREAM12_AZALIA_STREAM_DATA
++#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
++#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_azf0stream13_dispdec
++//AZF0STREAM13_AZALIA_STREAM_INDEX
++#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
++#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
++#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
++#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
++//AZF0STREAM13_AZALIA_STREAM_DATA
++#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
++#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_azf0stream14_dispdec
++//AZF0STREAM14_AZALIA_STREAM_INDEX
++#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
++#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
++#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
++#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
++//AZF0STREAM14_AZALIA_STREAM_DATA
++#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
++#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_azf0stream15_dispdec
++//AZF0STREAM15_AZALIA_STREAM_INDEX
++#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
++#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
++#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
++#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
++//AZF0STREAM15_AZALIA_STREAM_DATA
++#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
++#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_azf0inputendpoint0_dispdec
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_azf0inputendpoint1_dispdec
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_azf0inputendpoint2_dispdec
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_azf0inputendpoint3_dispdec
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_azf0inputendpoint4_dispdec
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_azf0inputendpoint5_dispdec
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_azf0inputendpoint6_dispdec
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_azf0inputendpoint7_dispdec
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dcp0_dispdec
++//DCP0_GRPH_ENABLE
++#define DCP0_GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0
++#define DCP0_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL__SHIFT 0x1
++#define DCP0_GRPH_ENABLE__GRPH_ENABLE_MASK 0x00000001L
++#define DCP0_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL_MASK 0x00000002L
++//DCP0_GRPH_CONTROL
++#define DCP0_GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0
++#define DCP0_GRPH_CONTROL__GRPH_SE_ENABLE__SHIFT 0x2
++#define DCP0_GRPH_CONTROL__GRPH_Z__SHIFT 0x4
++#define DCP0_GRPH_CONTROL__GRPH_DIM_TYPE__SHIFT 0x6
++#define DCP0_GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8
++#define DCP0_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0xc
++#define DCP0_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10
++#define DCP0_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11
++#define DCP0_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES__SHIFT 0x12
++#define DCP0_GRPH_CONTROL__GRPH_SW_MODE__SHIFT 0x14
++#define DCP0_GRPH_CONTROL__GRPH_NUM_PIPES__SHIFT 0x1c
++#define DCP0_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f
++#define DCP0_GRPH_CONTROL__GRPH_DEPTH_MASK 0x00000003L
++#define DCP0_GRPH_CONTROL__GRPH_SE_ENABLE_MASK 0x00000004L
++#define DCP0_GRPH_CONTROL__GRPH_Z_MASK 0x00000030L
++#define DCP0_GRPH_CONTROL__GRPH_DIM_TYPE_MASK 0x000000C0L
++#define DCP0_GRPH_CONTROL__GRPH_FORMAT_MASK 0x00000700L
++#define DCP0_GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0x00007000L
++#define DCP0_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x00010000L
++#define DCP0_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x00020000L
++#define DCP0_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES_MASK 0x000C0000L
++#define DCP0_GRPH_CONTROL__GRPH_SW_MODE_MASK 0x01F00000L
++#define DCP0_GRPH_CONTROL__GRPH_NUM_PIPES_MASK 0x70000000L
++#define DCP0_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000L
++//DCP0_GRPH_LUT_10BIT_BYPASS
++#define DCP0_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT 0x8
++#define DCP0_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x10
++#define DCP0_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK 0x00000100L
++#define DCP0_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x00010000L
++//DCP0_GRPH_SWAP_CNTL
++#define DCP0_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0
++#define DCP0_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4
++#define DCP0_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6
++#define DCP0_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8
++#define DCP0_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT 0xa
++#define DCP0_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x00000003L
++#define DCP0_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x00000030L
++#define DCP0_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0x000000C0L
++#define DCP0_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x00000300L
++#define DCP0_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK 0x00000C00L
++//DCP0_GRPH_PRIMARY_SURFACE_ADDRESS
++#define DCP0_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT 0x0
++#define DCP0_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT 0x8
++#define DCP0_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK 0x00000001L
++#define DCP0_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
++//DCP0_GRPH_SECONDARY_SURFACE_ADDRESS
++#define DCP0_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT 0x0
++#define DCP0_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8
++#define DCP0_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK 0x00000001L
++#define DCP0_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
++//DCP0_GRPH_PITCH
++#define DCP0_GRPH_PITCH__GRPH_PITCH__SHIFT 0x0
++#define DCP0_GRPH_PITCH__GRPH_PITCH_MASK 0x00007FFFL
++//DCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
++#define DCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define DCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
++//DCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
++#define DCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define DCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
++//DCP0_GRPH_SURFACE_OFFSET_X
++#define DCP0_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT 0x0
++#define DCP0_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK 0x00003FFFL
++//DCP0_GRPH_SURFACE_OFFSET_Y
++#define DCP0_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT 0x0
++#define DCP0_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK 0x00003FFFL
++//DCP0_GRPH_X_START
++#define DCP0_GRPH_X_START__GRPH_X_START__SHIFT 0x0
++#define DCP0_GRPH_X_START__GRPH_X_START_MASK 0x00003FFFL
++//DCP0_GRPH_Y_START
++#define DCP0_GRPH_Y_START__GRPH_Y_START__SHIFT 0x0
++#define DCP0_GRPH_Y_START__GRPH_Y_START_MASK 0x00003FFFL
++//DCP0_GRPH_X_END
++#define DCP0_GRPH_X_END__GRPH_X_END__SHIFT 0x0
++#define DCP0_GRPH_X_END__GRPH_X_END_MASK 0x00007FFFL
++//DCP0_GRPH_Y_END
++#define DCP0_GRPH_Y_END__GRPH_Y_END__SHIFT 0x0
++#define DCP0_GRPH_Y_END__GRPH_Y_END_MASK 0x00007FFFL
++//DCP0_INPUT_GAMMA_CONTROL
++#define DCP0_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x0
++#define DCP0_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK 0x00000001L
++//DCP0_GRPH_UPDATE
++#define DCP0_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0
++#define DCP0_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1
++#define DCP0_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2
++#define DCP0_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3
++#define DCP0_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR__SHIFT 0x8
++#define DCP0_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE__SHIFT 0x9
++#define DCP0_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE__SHIFT 0xa
++#define DCP0_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10
++#define DCP0_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14
++#define DCP0_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
++#define DCP0_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c
++#define DCP0_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x00000001L
++#define DCP0_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x00000002L
++#define DCP0_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x00000004L
++#define DCP0_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x00000008L
++#define DCP0_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR_MASK 0x00000100L
++#define DCP0_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE_MASK 0x00000200L
++#define DCP0_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE_MASK 0x00000400L
++#define DCP0_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x00010000L
++#define DCP0_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x00100000L
++#define DCP0_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
++#define DCP0_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000L
++//DCP0_GRPH_FLIP_CONTROL
++#define DCP0_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT 0x0
++#define DCP0_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN__SHIFT 0x1
++#define DCP0_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN__SHIFT 0x4
++#define DCP0_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT 0x5
++#define DCP0_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK 0x00000001L
++#define DCP0_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN_MASK 0x00000002L
++#define DCP0_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN_MASK 0x00000010L
++#define DCP0_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK 0x00000020L
++//DCP0_GRPH_SURFACE_ADDRESS_INUSE
++#define DCP0_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT 0x8
++#define DCP0_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK 0xFFFFFF00L
++//DCP0_GRPH_DFQ_CONTROL
++#define DCP0_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x0
++#define DCP0_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x4
++#define DCP0_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8
++#define DCP0_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x00000001L
++#define DCP0_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x00000070L
++#define DCP0_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x00000700L
++//DCP0_GRPH_DFQ_STATUS
++#define DCP0_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x0
++#define DCP0_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4
++#define DCP0_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x8
++#define DCP0_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x9
++#define DCP0_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0x0000000FL
++#define DCP0_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0x000000F0L
++#define DCP0_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x00000100L
++#define DCP0_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x00000200L
++//DCP0_GRPH_INTERRUPT_STATUS
++#define DCP0_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0
++#define DCP0_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8
++#define DCP0_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x00000001L
++#define DCP0_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x00000100L
++//DCP0_GRPH_INTERRUPT_CONTROL
++#define DCP0_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0
++#define DCP0_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8
++#define DCP0_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x00000001L
++#define DCP0_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x00000100L
++//DCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE
++#define DCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0
++#define DCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK 0x000000FFL
++//DCP0_GRPH_COMPRESS_SURFACE_ADDRESS
++#define DCP0_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT 0x8
++#define DCP0_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK 0xFFFFFF00L
++//DCP0_GRPH_COMPRESS_PITCH
++#define DCP0_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT 0x6
++#define DCP0_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK 0x0001FFC0L
++//DCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH
++#define DCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define DCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
++//DCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT
++#define DCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__SHIFT 0x0
++#define DCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_MASK 0x000000FFL
++//DCP0_PRESCALE_GRPH_CONTROL
++#define DCP0_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT 0x0
++#define DCP0_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT 0x1
++#define DCP0_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x2
++#define DCP0_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT 0x3
++#define DCP0_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT 0x4
++#define DCP0_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK 0x00000001L
++#define DCP0_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x00000002L
++#define DCP0_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK 0x00000004L
++#define DCP0_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK 0x00000008L
++#define DCP0_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK 0x00000010L
++//DCP0_PRESCALE_VALUES_GRPH_R
++#define DCP0_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT 0x0
++#define DCP0_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT 0x10
++#define DCP0_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK 0x0000FFFFL
++#define DCP0_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK 0xFFFF0000L
++//DCP0_PRESCALE_VALUES_GRPH_G
++#define DCP0_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT 0x0
++#define DCP0_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT 0x10
++#define DCP0_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK 0x0000FFFFL
++#define DCP0_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK 0xFFFF0000L
++//DCP0_PRESCALE_VALUES_GRPH_B
++#define DCP0_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT 0x0
++#define DCP0_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT 0x10
++#define DCP0_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK 0x0000FFFFL
++#define DCP0_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK 0xFFFF0000L
++//DCP0_INPUT_CSC_CONTROL
++#define DCP0_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT 0x0
++#define DCP0_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK 0x00000003L
++//DCP0_INPUT_CSC_C11_C12
++#define DCP0_INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT 0x0
++#define DCP0_INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT 0x10
++#define DCP0_INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK 0x0000FFFFL
++#define DCP0_INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK 0xFFFF0000L
++//DCP0_INPUT_CSC_C13_C14
++#define DCP0_INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT 0x0
++#define DCP0_INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT 0x10
++#define DCP0_INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK 0x0000FFFFL
++#define DCP0_INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK 0xFFFF0000L
++//DCP0_INPUT_CSC_C21_C22
++#define DCP0_INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT 0x0
++#define DCP0_INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT 0x10
++#define DCP0_INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK 0x0000FFFFL
++#define DCP0_INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK 0xFFFF0000L
++//DCP0_INPUT_CSC_C23_C24
++#define DCP0_INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT 0x0
++#define DCP0_INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT 0x10
++#define DCP0_INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK 0x0000FFFFL
++#define DCP0_INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK 0xFFFF0000L
++//DCP0_INPUT_CSC_C31_C32
++#define DCP0_INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT 0x0
++#define DCP0_INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT 0x10
++#define DCP0_INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK 0x0000FFFFL
++#define DCP0_INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK 0xFFFF0000L
++//DCP0_INPUT_CSC_C33_C34
++#define DCP0_INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT 0x0
++#define DCP0_INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT 0x10
++#define DCP0_INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK 0x0000FFFFL
++#define DCP0_INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK 0xFFFF0000L
++//DCP0_OUTPUT_CSC_CONTROL
++#define DCP0_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT 0x0
++#define DCP0_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK 0x00000007L
++//DCP0_OUTPUT_CSC_C11_C12
++#define DCP0_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT 0x0
++#define DCP0_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT 0x10
++#define DCP0_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK 0x0000FFFFL
++#define DCP0_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK 0xFFFF0000L
++//DCP0_OUTPUT_CSC_C13_C14
++#define DCP0_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT 0x0
++#define DCP0_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT 0x10
++#define DCP0_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK 0x0000FFFFL
++#define DCP0_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK 0xFFFF0000L
++//DCP0_OUTPUT_CSC_C21_C22
++#define DCP0_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT 0x0
++#define DCP0_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT 0x10
++#define DCP0_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK 0x0000FFFFL
++#define DCP0_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK 0xFFFF0000L
++//DCP0_OUTPUT_CSC_C23_C24
++#define DCP0_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT 0x0
++#define DCP0_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT 0x10
++#define DCP0_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK 0x0000FFFFL
++#define DCP0_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK 0xFFFF0000L
++//DCP0_OUTPUT_CSC_C31_C32
++#define DCP0_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT 0x0
++#define DCP0_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT 0x10
++#define DCP0_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK 0x0000FFFFL
++#define DCP0_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK 0xFFFF0000L
++//DCP0_OUTPUT_CSC_C33_C34
++#define DCP0_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT 0x0
++#define DCP0_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT 0x10
++#define DCP0_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK 0x0000FFFFL
++#define DCP0_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK 0xFFFF0000L
++//DCP0_COMM_MATRIXA_TRANS_C11_C12
++#define DCP0_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT 0x0
++#define DCP0_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT 0x10
++#define DCP0_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK 0x0000FFFFL
++#define DCP0_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK 0xFFFF0000L
++//DCP0_COMM_MATRIXA_TRANS_C13_C14
++#define DCP0_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT 0x0
++#define DCP0_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT 0x10
++#define DCP0_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK 0x0000FFFFL
++#define DCP0_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK 0xFFFF0000L
++//DCP0_COMM_MATRIXA_TRANS_C21_C22
++#define DCP0_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT 0x0
++#define DCP0_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT 0x10
++#define DCP0_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK 0x0000FFFFL
++#define DCP0_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK 0xFFFF0000L
++//DCP0_COMM_MATRIXA_TRANS_C23_C24
++#define DCP0_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT 0x0
++#define DCP0_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT 0x10
++#define DCP0_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK 0x0000FFFFL
++#define DCP0_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK 0xFFFF0000L
++//DCP0_COMM_MATRIXA_TRANS_C31_C32
++#define DCP0_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT 0x0
++#define DCP0_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT 0x10
++#define DCP0_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK 0x0000FFFFL
++#define DCP0_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK 0xFFFF0000L
++//DCP0_COMM_MATRIXA_TRANS_C33_C34
++#define DCP0_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT 0x0
++#define DCP0_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT 0x10
++#define DCP0_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK 0x0000FFFFL
++#define DCP0_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK 0xFFFF0000L
++//DCP0_COMM_MATRIXB_TRANS_C11_C12
++#define DCP0_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT 0x0
++#define DCP0_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT 0x10
++#define DCP0_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK 0x0000FFFFL
++#define DCP0_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK 0xFFFF0000L
++//DCP0_COMM_MATRIXB_TRANS_C13_C14
++#define DCP0_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT 0x0
++#define DCP0_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT 0x10
++#define DCP0_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK 0x0000FFFFL
++#define DCP0_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK 0xFFFF0000L
++//DCP0_COMM_MATRIXB_TRANS_C21_C22
++#define DCP0_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT 0x0
++#define DCP0_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT 0x10
++#define DCP0_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK 0x0000FFFFL
++#define DCP0_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK 0xFFFF0000L
++//DCP0_COMM_MATRIXB_TRANS_C23_C24
++#define DCP0_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT 0x0
++#define DCP0_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT 0x10
++#define DCP0_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK 0x0000FFFFL
++#define DCP0_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK 0xFFFF0000L
++//DCP0_COMM_MATRIXB_TRANS_C31_C32
++#define DCP0_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT 0x0
++#define DCP0_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT 0x10
++#define DCP0_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK 0x0000FFFFL
++#define DCP0_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK 0xFFFF0000L
++//DCP0_COMM_MATRIXB_TRANS_C33_C34
++#define DCP0_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT 0x0
++#define DCP0_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT 0x10
++#define DCP0_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK 0x0000FFFFL
++#define DCP0_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK 0xFFFF0000L
++//DCP0_DENORM_CONTROL
++#define DCP0_DENORM_CONTROL__DENORM_MODE__SHIFT 0x0
++#define DCP0_DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT 0x4
++#define DCP0_DENORM_CONTROL__DENORM_MODE_MASK 0x00000007L
++#define DCP0_DENORM_CONTROL__DENORM_14BIT_OUT_MASK 0x00000010L
++//DCP0_OUT_ROUND_CONTROL
++#define DCP0_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT 0x0
++#define DCP0_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK 0x0000000FL
++//DCP0_OUT_CLAMP_CONTROL_R_CR
++#define DCP0_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT 0x0
++#define DCP0_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT 0x10
++#define DCP0_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK 0x00003FFFL
++#define DCP0_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK 0x3FFF0000L
++//DCP0_OUT_CLAMP_CONTROL_G_Y
++#define DCP0_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT 0x0
++#define DCP0_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT 0x10
++#define DCP0_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK 0x00003FFFL
++#define DCP0_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK 0x3FFF0000L
++//DCP0_OUT_CLAMP_CONTROL_B_CB
++#define DCP0_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT 0x0
++#define DCP0_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT 0x10
++#define DCP0_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK 0x00003FFFL
++#define DCP0_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK 0x3FFF0000L
++//DCP0_KEY_CONTROL
++#define DCP0_KEY_CONTROL__KEY_MODE__SHIFT 0x1
++#define DCP0_KEY_CONTROL__KEY_MODE_MASK 0x00000006L
++//DCP0_KEY_RANGE_ALPHA
++#define DCP0_KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT 0x0
++#define DCP0_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT 0x10
++#define DCP0_KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK 0x0000FFFFL
++#define DCP0_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK 0xFFFF0000L
++//DCP0_KEY_RANGE_RED
++#define DCP0_KEY_RANGE_RED__KEY_RED_LOW__SHIFT 0x0
++#define DCP0_KEY_RANGE_RED__KEY_RED_HIGH__SHIFT 0x10
++#define DCP0_KEY_RANGE_RED__KEY_RED_LOW_MASK 0x0000FFFFL
++#define DCP0_KEY_RANGE_RED__KEY_RED_HIGH_MASK 0xFFFF0000L
++//DCP0_KEY_RANGE_GREEN
++#define DCP0_KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT 0x0
++#define DCP0_KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT 0x10
++#define DCP0_KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK 0x0000FFFFL
++#define DCP0_KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK 0xFFFF0000L
++//DCP0_KEY_RANGE_BLUE
++#define DCP0_KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT 0x0
++#define DCP0_KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT 0x10
++#define DCP0_KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK 0x0000FFFFL
++#define DCP0_KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK 0xFFFF0000L
++//DCP0_DEGAMMA_CONTROL
++#define DCP0_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x0
++#define DCP0_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT 0x8
++#define DCP0_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0xc
++#define DCP0_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x00000003L
++#define DCP0_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK 0x00000300L
++#define DCP0_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK 0x00003000L
++//DCP0_GAMUT_REMAP_CONTROL
++#define DCP0_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT 0x0
++#define DCP0_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK 0x00000003L
++//DCP0_GAMUT_REMAP_C11_C12
++#define DCP0_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT 0x0
++#define DCP0_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT 0x10
++#define DCP0_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK 0x0000FFFFL
++#define DCP0_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK 0xFFFF0000L
++//DCP0_GAMUT_REMAP_C13_C14
++#define DCP0_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT 0x0
++#define DCP0_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT 0x10
++#define DCP0_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK 0x0000FFFFL
++#define DCP0_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK 0xFFFF0000L
++//DCP0_GAMUT_REMAP_C21_C22
++#define DCP0_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT 0x0
++#define DCP0_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT 0x10
++#define DCP0_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK 0x0000FFFFL
++#define DCP0_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK 0xFFFF0000L
++//DCP0_GAMUT_REMAP_C23_C24
++#define DCP0_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT 0x0
++#define DCP0_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT 0x10
++#define DCP0_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK 0x0000FFFFL
++#define DCP0_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK 0xFFFF0000L
++//DCP0_GAMUT_REMAP_C31_C32
++#define DCP0_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT 0x0
++#define DCP0_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT 0x10
++#define DCP0_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK 0x0000FFFFL
++#define DCP0_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK 0xFFFF0000L
++//DCP0_GAMUT_REMAP_C33_C34
++#define DCP0_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT 0x0
++#define DCP0_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT 0x10
++#define DCP0_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK 0x0000FFFFL
++#define DCP0_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK 0xFFFF0000L
++//DCP0_DCP_SPATIAL_DITHER_CNTL
++#define DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT 0x0
++#define DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT 0x4
++#define DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT 0x6
++#define DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT 0x8
++#define DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT 0x9
++#define DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT 0xa
++#define DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK 0x00000001L
++#define DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK 0x00000030L
++#define DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK 0x000000C0L
++#define DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK 0x00000100L
++#define DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK 0x00000200L
++#define DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK 0x00000400L
++//DCP0_DCP_RANDOM_SEEDS
++#define DCP0_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT 0x0
++#define DCP0_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT 0x8
++#define DCP0_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT 0x10
++#define DCP0_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK 0x000000FFL
++#define DCP0_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK 0x0000FF00L
++#define DCP0_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK 0x00FF0000L
++//DCP0_DCP_FP_CONVERTED_FIELD
++#define DCP0_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT 0x0
++#define DCP0_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14
++#define DCP0_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK 0x0003FFFFL
++#define DCP0_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK 0x07F00000L
++//DCP0_CUR_CONTROL
++#define DCP0_CUR_CONTROL__CURSOR_EN__SHIFT 0x0
++#define DCP0_CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT 0x4
++#define DCP0_CUR_CONTROL__CURSOR_MODE__SHIFT 0x8
++#define DCP0_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM__SHIFT 0xb
++#define DCP0_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION__SHIFT 0xc
++#define DCP0_CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x10
++#define DCP0_CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT 0x14
++#define DCP0_CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT 0x18
++#define DCP0_CUR_CONTROL__CURSOR_EN_MASK 0x00000001L
++#define DCP0_CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK 0x00000010L
++#define DCP0_CUR_CONTROL__CURSOR_MODE_MASK 0x00000300L
++#define DCP0_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM_MASK 0x00000800L
++#define DCP0_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION_MASK 0x0000F000L
++#define DCP0_CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00010000L
++#define DCP0_CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK 0x00100000L
++#define DCP0_CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK 0x07000000L
++//DCP0_CUR_SURFACE_ADDRESS
++#define DCP0_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0
++#define DCP0_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
++//DCP0_CUR_SIZE
++#define DCP0_CUR_SIZE__CURSOR_HEIGHT__SHIFT 0x0
++#define DCP0_CUR_SIZE__CURSOR_WIDTH__SHIFT 0x10
++#define DCP0_CUR_SIZE__CURSOR_HEIGHT_MASK 0x0000007FL
++#define DCP0_CUR_SIZE__CURSOR_WIDTH_MASK 0x007F0000L
++//DCP0_CUR_SURFACE_ADDRESS_HIGH
++#define DCP0_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define DCP0_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
++//DCP0_CUR_POSITION
++#define DCP0_CUR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0
++#define DCP0_CUR_POSITION__CURSOR_X_POSITION__SHIFT 0x10
++#define DCP0_CUR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL
++#define DCP0_CUR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L
++//DCP0_CUR_HOT_SPOT
++#define DCP0_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0
++#define DCP0_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10
++#define DCP0_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x0000007FL
++#define DCP0_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x007F0000L
++//DCP0_CUR_COLOR1
++#define DCP0_CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT 0x0
++#define DCP0_CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT 0x8
++#define DCP0_CUR_COLOR1__CUR_COLOR1_RED__SHIFT 0x10
++#define DCP0_CUR_COLOR1__CUR_COLOR1_BLUE_MASK 0x000000FFL
++#define DCP0_CUR_COLOR1__CUR_COLOR1_GREEN_MASK 0x0000FF00L
++#define DCP0_CUR_COLOR1__CUR_COLOR1_RED_MASK 0x00FF0000L
++//DCP0_CUR_COLOR2
++#define DCP0_CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT 0x0
++#define DCP0_CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT 0x8
++#define DCP0_CUR_COLOR2__CUR_COLOR2_RED__SHIFT 0x10
++#define DCP0_CUR_COLOR2__CUR_COLOR2_BLUE_MASK 0x000000FFL
++#define DCP0_CUR_COLOR2__CUR_COLOR2_GREEN_MASK 0x0000FF00L
++#define DCP0_CUR_COLOR2__CUR_COLOR2_RED_MASK 0x00FF0000L
++//DCP0_CUR_UPDATE
++#define DCP0_CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT 0x0
++#define DCP0_CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT 0x1
++#define DCP0_CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT 0x10
++#define DCP0_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
++#define DCP0_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE__SHIFT 0x19
++#define DCP0_CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK 0x00000001L
++#define DCP0_CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x00000002L
++#define DCP0_CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK 0x00010000L
++#define DCP0_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
++#define DCP0_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE_MASK 0x06000000L
++//DCP0_CUR_REQUEST_FILTER_CNTL
++#define DCP0_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT 0x0
++#define DCP0_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK 0x00000001L
++//DCP0_CUR_STEREO_CONTROL
++#define DCP0_CUR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0
++#define DCP0_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4
++#define DCP0_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x10
++#define DCP0_CUR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L
++#define DCP0_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x00003FF0L
++#define DCP0_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0x03FF0000L
++//DCP0_DC_LUT_RW_MODE
++#define DCP0_DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT 0x0
++#define DCP0_DC_LUT_RW_MODE__DC_LUT_ERROR__SHIFT 0x10
++#define DCP0_DC_LUT_RW_MODE__DC_LUT_ERROR_RST__SHIFT 0x11
++#define DCP0_DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK 0x00000001L
++#define DCP0_DC_LUT_RW_MODE__DC_LUT_ERROR_MASK 0x00010000L
++#define DCP0_DC_LUT_RW_MODE__DC_LUT_ERROR_RST_MASK 0x00020000L
++//DCP0_DC_LUT_RW_INDEX
++#define DCP0_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT 0x0
++#define DCP0_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK 0x000000FFL
++//DCP0_DC_LUT_SEQ_COLOR
++#define DCP0_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT 0x0
++#define DCP0_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK 0x0000FFFFL
++//DCP0_DC_LUT_PWL_DATA
++#define DCP0_DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT 0x0
++#define DCP0_DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT 0x10
++#define DCP0_DC_LUT_PWL_DATA__DC_LUT_BASE_MASK 0x0000FFFFL
++#define DCP0_DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK 0xFFFF0000L
++//DCP0_DC_LUT_30_COLOR
++#define DCP0_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT 0x0
++#define DCP0_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT 0xa
++#define DCP0_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT 0x14
++#define DCP0_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK 0x000003FFL
++#define DCP0_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK 0x000FFC00L
++#define DCP0_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK 0x3FF00000L
++//DCP0_DC_LUT_VGA_ACCESS_ENABLE
++#define DCP0_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT 0x0
++#define DCP0_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK 0x00000001L
++//DCP0_DC_LUT_WRITE_EN_MASK
++#define DCP0_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT 0x0
++#define DCP0_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK 0x00000007L
++//DCP0_DC_LUT_AUTOFILL
++#define DCP0_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT 0x0
++#define DCP0_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT 0x1
++#define DCP0_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK 0x00000001L
++#define DCP0_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x00000002L
++//DCP0_DC_LUT_CONTROL
++#define DCP0_DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT 0x0
++#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT 0x4
++#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT 0x5
++#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT 0x6
++#define DCP0_DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT 0x8
++#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT 0xc
++#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT 0xd
++#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT 0xe
++#define DCP0_DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT 0x10
++#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT 0x14
++#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT 0x15
++#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT 0x16
++#define DCP0_DC_LUT_CONTROL__DC_LUT_INC_B_MASK 0x0000000FL
++#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK 0x00000010L
++#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK 0x00000020L
++#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK 0x000000C0L
++#define DCP0_DC_LUT_CONTROL__DC_LUT_INC_G_MASK 0x00000F00L
++#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK 0x00001000L
++#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK 0x00002000L
++#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK 0x0000C000L
++#define DCP0_DC_LUT_CONTROL__DC_LUT_INC_R_MASK 0x000F0000L
++#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK 0x00100000L
++#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK 0x00200000L
++#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK 0x00C00000L
++//DCP0_DC_LUT_BLACK_OFFSET_BLUE
++#define DCP0_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0
++#define DCP0_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK 0x0000FFFFL
++//DCP0_DC_LUT_BLACK_OFFSET_GREEN
++#define DCP0_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0
++#define DCP0_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK 0x0000FFFFL
++//DCP0_DC_LUT_BLACK_OFFSET_RED
++#define DCP0_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT 0x0
++#define DCP0_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK 0x0000FFFFL
++//DCP0_DC_LUT_WHITE_OFFSET_BLUE
++#define DCP0_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT 0x0
++#define DCP0_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK 0x0000FFFFL
++//DCP0_DC_LUT_WHITE_OFFSET_GREEN
++#define DCP0_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT 0x0
++#define DCP0_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK 0x0000FFFFL
++//DCP0_DC_LUT_WHITE_OFFSET_RED
++#define DCP0_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT 0x0
++#define DCP0_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK 0x0000FFFFL
++//DCP0_DCP_CRC_CONTROL
++#define DCP0_DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT 0x0
++#define DCP0_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x2
++#define DCP0_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT 0x8
++#define DCP0_DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK 0x00000001L
++#define DCP0_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK 0x0000001CL
++#define DCP0_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK 0x00000300L
++//DCP0_DCP_CRC_MASK
++#define DCP0_DCP_CRC_MASK__DCP_CRC_MASK__SHIFT 0x0
++#define DCP0_DCP_CRC_MASK__DCP_CRC_MASK_MASK 0xFFFFFFFFL
++//DCP0_DCP_CRC_CURRENT
++#define DCP0_DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT 0x0
++#define DCP0_DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK 0xFFFFFFFFL
++//DCP0_DVMM_PTE_CONTROL
++#define DCP0_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT 0x0
++#define DCP0_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT 0x1
++#define DCP0_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT 0x5
++#define DCP0_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT 0x9
++#define DCP0_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT 0x14
++#define DCP0_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT 0x15
++#define DCP0_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK 0x00000001L
++#define DCP0_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK 0x0000001EL
++#define DCP0_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK 0x000001E0L
++#define DCP0_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK 0x0007FE00L
++#define DCP0_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK 0x00100000L
++#define DCP0_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK 0x00200000L
++//DCP0_DCP_CRC_LAST
++#define DCP0_DCP_CRC_LAST__DCP_CRC_LAST__SHIFT 0x0
++#define DCP0_DCP_CRC_LAST__DCP_CRC_LAST_MASK 0xFFFFFFFFL
++//DCP0_DVMM_PTE_ARB_CONTROL
++#define DCP0_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT 0x0
++#define DCP0_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT 0x8
++#define DCP0_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK 0x0000003FL
++#define DCP0_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK 0x0000FF00L
++//DCP0_GRPH_FLIP_RATE_CNTL
++#define DCP0_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT 0x0
++#define DCP0_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT 0x3
++#define DCP0_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK 0x00000007L
++#define DCP0_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK 0x00000008L
++//DCP0_DCP_GSL_CONTROL
++#define DCP0_DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT 0x0
++#define DCP0_DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT 0x1
++#define DCP0_DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x2
++#define DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT 0x4
++#define DCP0_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT 0x14
++#define DCP0_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP__SHIFT 0x15
++#define DCP0_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN__SHIFT 0x17
++#define DCP0_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT 0x18
++#define DCP0_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC__SHIFT 0x1a
++#define DCP0_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT 0x1b
++#define DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT 0x1c
++#define DCP0_DCP_GSL_CONTROL__DCP_GSL0_EN_MASK 0x00000001L
++#define DCP0_DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x00000002L
++#define DCP0_DCP_GSL_CONTROL__DCP_GSL2_EN_MASK 0x00000004L
++#define DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK 0x000FFFF0L
++#define DCP0_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK 0x00100000L
++#define DCP0_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_MASK 0x00600000L
++#define DCP0_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_MASK 0x00800000L
++#define DCP0_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK 0x03000000L
++#define DCP0_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_MASK 0x04000000L
++#define DCP0_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK 0x08000000L
++#define DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK 0xF0000000L
++//DCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK
++#define DCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT 0x0
++#define DCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT 0x4
++#define DCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK 0x0000000FL
++#define DCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK 0x000001F0L
++//DCP0_GRPH_STEREOSYNC_FLIP
++#define DCP0_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0
++#define DCP0_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x8
++#define DCP0_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10
++#define DCP0_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11
++#define DCP0_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c
++#define DCP0_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x00000001L
++#define DCP0_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x00000300L
++#define DCP0_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x00010000L
++#define DCP0_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x00020000L
++#define DCP0_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000L
++//DCP0_HW_ROTATION
++#define DCP0_HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT 0x0
++#define DCP0_HW_ROTATION__GRPH_ROTATION_ANGLE_MASK 0x00000007L
++//DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL
++#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT 0x0
++#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT 0x1
++#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT 0x4
++#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK 0x00000001L
++#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK 0x00000002L
++#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK 0x0001FFF0L
++//DCP0_REGAMMA_CONTROL
++#define DCP0_REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT 0x0
++#define DCP0_REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK 0x00000007L
++//DCP0_REGAMMA_LUT_INDEX
++#define DCP0_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x0
++#define DCP0_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK 0x000001FFL
++//DCP0_REGAMMA_LUT_DATA
++#define DCP0_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT 0x0
++#define DCP0_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK 0x0007FFFFL
++//DCP0_REGAMMA_LUT_WRITE_EN_MASK
++#define DCP0_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x0
++#define DCP0_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x00000007L
++//DCP0_REGAMMA_CNTLA_START_CNTL
++#define DCP0_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x0
++#define DCP0_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14
++#define DCP0_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK 0x0003FFFFL
++#define DCP0_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
++//DCP0_REGAMMA_CNTLA_SLOPE_CNTL
++#define DCP0_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
++#define DCP0_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
++//DCP0_REGAMMA_CNTLA_END_CNTL1
++#define DCP0_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x0
++#define DCP0_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK 0x0000FFFFL
++//DCP0_REGAMMA_CNTLA_END_CNTL2
++#define DCP0_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0
++#define DCP0_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10
++#define DCP0_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
++#define DCP0_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xFFFF0000L
++//DCP0_REGAMMA_CNTLA_REGION_0_1
++#define DCP0_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
++#define DCP0_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
++#define DCP0_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
++#define DCP0_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP0_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
++#define DCP0_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP0_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP0_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
++//DCP0_REGAMMA_CNTLA_REGION_2_3
++#define DCP0_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
++#define DCP0_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
++#define DCP0_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
++#define DCP0_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP0_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
++#define DCP0_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP0_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP0_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
++//DCP0_REGAMMA_CNTLA_REGION_4_5
++#define DCP0_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
++#define DCP0_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
++#define DCP0_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
++#define DCP0_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP0_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
++#define DCP0_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP0_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP0_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
++//DCP0_REGAMMA_CNTLA_REGION_6_7
++#define DCP0_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
++#define DCP0_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
++#define DCP0_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
++#define DCP0_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP0_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
++#define DCP0_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP0_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP0_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
++//DCP0_REGAMMA_CNTLA_REGION_8_9
++#define DCP0_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
++#define DCP0_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
++#define DCP0_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
++#define DCP0_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP0_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
++#define DCP0_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP0_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP0_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
++//DCP0_REGAMMA_CNTLA_REGION_10_11
++#define DCP0_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
++#define DCP0_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
++#define DCP0_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
++#define DCP0_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP0_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
++#define DCP0_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP0_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP0_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
++//DCP0_REGAMMA_CNTLA_REGION_12_13
++#define DCP0_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
++#define DCP0_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
++#define DCP0_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
++#define DCP0_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP0_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
++#define DCP0_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP0_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP0_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
++//DCP0_REGAMMA_CNTLA_REGION_14_15
++#define DCP0_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
++#define DCP0_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
++#define DCP0_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
++#define DCP0_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP0_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
++#define DCP0_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP0_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP0_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
++//DCP0_REGAMMA_CNTLB_START_CNTL
++#define DCP0_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x0
++#define DCP0_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14
++#define DCP0_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK 0x0003FFFFL
++#define DCP0_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
++//DCP0_REGAMMA_CNTLB_SLOPE_CNTL
++#define DCP0_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
++#define DCP0_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
++//DCP0_REGAMMA_CNTLB_END_CNTL1
++#define DCP0_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x0
++#define DCP0_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK 0x0000FFFFL
++//DCP0_REGAMMA_CNTLB_END_CNTL2
++#define DCP0_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0
++#define DCP0_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10
++#define DCP0_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
++#define DCP0_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xFFFF0000L
++//DCP0_REGAMMA_CNTLB_REGION_0_1
++#define DCP0_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
++#define DCP0_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
++#define DCP0_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
++#define DCP0_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP0_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
++#define DCP0_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP0_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP0_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
++//DCP0_REGAMMA_CNTLB_REGION_2_3
++#define DCP0_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
++#define DCP0_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
++#define DCP0_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
++#define DCP0_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP0_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
++#define DCP0_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP0_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP0_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
++//DCP0_REGAMMA_CNTLB_REGION_4_5
++#define DCP0_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
++#define DCP0_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
++#define DCP0_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
++#define DCP0_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP0_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
++#define DCP0_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP0_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP0_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
++//DCP0_REGAMMA_CNTLB_REGION_6_7
++#define DCP0_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
++#define DCP0_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
++#define DCP0_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
++#define DCP0_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP0_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
++#define DCP0_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP0_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP0_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
++//DCP0_REGAMMA_CNTLB_REGION_8_9
++#define DCP0_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
++#define DCP0_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
++#define DCP0_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
++#define DCP0_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP0_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
++#define DCP0_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP0_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP0_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
++//DCP0_REGAMMA_CNTLB_REGION_10_11
++#define DCP0_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
++#define DCP0_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
++#define DCP0_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
++#define DCP0_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP0_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
++#define DCP0_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP0_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP0_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
++//DCP0_REGAMMA_CNTLB_REGION_12_13
++#define DCP0_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
++#define DCP0_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
++#define DCP0_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
++#define DCP0_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP0_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
++#define DCP0_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP0_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP0_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
++//DCP0_REGAMMA_CNTLB_REGION_14_15
++#define DCP0_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
++#define DCP0_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
++#define DCP0_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
++#define DCP0_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP0_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
++#define DCP0_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP0_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP0_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
++//DCP0_ALPHA_CONTROL
++#define DCP0_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT 0x0
++#define DCP0_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT 0x1
++#define DCP0_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK 0x00000001L
++#define DCP0_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK 0x00000002L
++//DCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS
++#define DCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT 0x8
++#define DCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
++//DCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH
++#define DCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define DCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
++//DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS
++#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT 0x0
++#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT 0x18
++#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT 0x19
++#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT 0x1a
++#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT 0x1c
++#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT 0x1d
++#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT 0x1e
++#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK 0x000FFFFFL
++#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK 0x01000000L
++#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK 0x02000000L
++#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK 0x04000000L
++#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK 0x10000000L
++#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK 0x20000000L
++#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK 0x40000000L
++//DCP0_GRPH_XDMA_FLIP_TIMEOUT
++#define DCP0_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS__SHIFT 0x0
++#define DCP0_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK__SHIFT 0x1
++#define DCP0_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK__SHIFT 0x2
++#define DCP0_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS_MASK 0x00000001L
++#define DCP0_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK_MASK 0x00000002L
++#define DCP0_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK_MASK 0x00000004L
++//DCP0_GRPH_XDMA_FLIP_AVG_DELAY
++#define DCP0_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY__SHIFT 0x0
++#define DCP0_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD__SHIFT 0x10
++#define DCP0_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY_MASK 0x0000FFFFL
++#define DCP0_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD_MASK 0x00FF0000L
++//DCP0_GRPH_SURFACE_COUNTER_CONTROL
++#define DCP0_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN__SHIFT 0x0
++#define DCP0_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT__SHIFT 0x1
++#define DCP0_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED__SHIFT 0x9
++#define DCP0_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN_MASK 0x00000001L
++#define DCP0_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT_MASK 0x0000001EL
++#define DCP0_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_MASK 0x00000200L
++//DCP0_GRPH_SURFACE_COUNTER_OUTPUT
++#define DCP0_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN__SHIFT 0x0
++#define DCP0_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX__SHIFT 0x10
++#define DCP0_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN_MASK 0x0000FFFFL
++#define DCP0_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX_MASK 0xFFFF0000L
++
++
++// addressBlock: dce_dc_lb0_dispdec
++//LB0_LB_DATA_FORMAT
++#define LB0_LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0
++#define LB0_LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2
++#define LB0_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3
++#define LB0_LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4
++#define LB0_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5
++#define LB0_LB_DATA_FORMAT__PREFILL_EN__SHIFT 0x8
++#define LB0_LB_DATA_FORMAT__PREFETCH__SHIFT 0xc
++#define LB0_LB_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18
++#define LB0_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f
++#define LB0_LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x00000003L
++#define LB0_LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x00000004L
++#define LB0_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000008L
++#define LB0_LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x00000010L
++#define LB0_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x00000020L
++#define LB0_LB_DATA_FORMAT__PREFILL_EN_MASK 0x00000100L
++#define LB0_LB_DATA_FORMAT__PREFETCH_MASK 0x00001000L
++#define LB0_LB_DATA_FORMAT__REQUEST_MODE_MASK 0x01000000L
++#define LB0_LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000L
++//LB0_LB_MEMORY_CTRL
++#define LB0_LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0
++#define LB0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
++#define LB0_LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14
++#define LB0_LB_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0x00001FFFL
++#define LB0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x000F0000L
++#define LB0_LB_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x00300000L
++//LB0_LB_MEMORY_SIZE_STATUS
++#define LB0_LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0
++#define LB0_LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0x00001FFFL
++//LB0_LB_DESKTOP_HEIGHT
++#define LB0_LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0
++#define LB0_LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x00007FFFL
++//LB0_LB_VLINE_START_END
++#define LB0_LB_VLINE_START_END__VLINE_START__SHIFT 0x0
++#define LB0_LB_VLINE_START_END__VLINE_END__SHIFT 0x10
++#define LB0_LB_VLINE_START_END__VLINE_INV__SHIFT 0x1f
++#define LB0_LB_VLINE_START_END__VLINE_START_MASK 0x00003FFFL
++#define LB0_LB_VLINE_START_END__VLINE_END_MASK 0x7FFF0000L
++#define LB0_LB_VLINE_START_END__VLINE_INV_MASK 0x80000000L
++//LB0_LB_VLINE2_START_END
++#define LB0_LB_VLINE2_START_END__VLINE2_START__SHIFT 0x0
++#define LB0_LB_VLINE2_START_END__VLINE2_END__SHIFT 0x10
++#define LB0_LB_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f
++#define LB0_LB_VLINE2_START_END__VLINE2_START_MASK 0x00003FFFL
++#define LB0_LB_VLINE2_START_END__VLINE2_END_MASK 0x7FFF0000L
++#define LB0_LB_VLINE2_START_END__VLINE2_INV_MASK 0x80000000L
++//LB0_LB_V_COUNTER
++#define LB0_LB_V_COUNTER__V_COUNTER__SHIFT 0x0
++#define LB0_LB_V_COUNTER__V_COUNTER_MASK 0x00007FFFL
++//LB0_LB_SNAPSHOT_V_COUNTER
++#define LB0_LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0
++#define LB0_LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x00007FFFL
++//LB0_LB_INTERRUPT_MASK
++#define LB0_LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0
++#define LB0_LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4
++#define LB0_LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8
++#define LB0_LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x00000001L
++#define LB0_LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x00000010L
++#define LB0_LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x00000100L
++//LB0_LB_VLINE_STATUS
++#define LB0_LB_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0
++#define LB0_LB_VLINE_STATUS__VLINE_ACK__SHIFT 0x4
++#define LB0_LB_VLINE_STATUS__VLINE_STAT__SHIFT 0xc
++#define LB0_LB_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10
++#define LB0_LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11
++#define LB0_LB_VLINE_STATUS__VLINE_OCCURRED_MASK 0x00000001L
++#define LB0_LB_VLINE_STATUS__VLINE_ACK_MASK 0x00000010L
++#define LB0_LB_VLINE_STATUS__VLINE_STAT_MASK 0x00001000L
++#define LB0_LB_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x00010000L
++#define LB0_LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x00020000L
++//LB0_LB_VLINE2_STATUS
++#define LB0_LB_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0
++#define LB0_LB_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4
++#define LB0_LB_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc
++#define LB0_LB_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10
++#define LB0_LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11
++#define LB0_LB_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x00000001L
++#define LB0_LB_VLINE2_STATUS__VLINE2_ACK_MASK 0x00000010L
++#define LB0_LB_VLINE2_STATUS__VLINE2_STAT_MASK 0x00001000L
++#define LB0_LB_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x00010000L
++#define LB0_LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x00020000L
++//LB0_LB_VBLANK_STATUS
++#define LB0_LB_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0
++#define LB0_LB_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4
++#define LB0_LB_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc
++#define LB0_LB_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10
++#define LB0_LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11
++#define LB0_LB_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x00000001L
++#define LB0_LB_VBLANK_STATUS__VBLANK_ACK_MASK 0x00000010L
++#define LB0_LB_VBLANK_STATUS__VBLANK_STAT_MASK 0x00001000L
++#define LB0_LB_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x00010000L
++#define LB0_LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x00020000L
++//LB0_LB_SYNC_RESET_SEL
++#define LB0_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0
++#define LB0_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4
++#define LB0_LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8
++#define LB0_LB_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16
++#define LB0_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x00000003L
++#define LB0_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x00000010L
++#define LB0_LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0x0000FF00L
++#define LB0_LB_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0x00C00000L
++//LB0_LB_BLACK_KEYER_R_CR
++#define LB0_LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4
++#define LB0_LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0x0000FFF0L
++//LB0_LB_BLACK_KEYER_G_Y
++#define LB0_LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4
++#define LB0_LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0x0000FFF0L
++//LB0_LB_BLACK_KEYER_B_CB
++#define LB0_LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4
++#define LB0_LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0x0000FFF0L
++//LB0_LB_KEYER_COLOR_CTRL
++#define LB0_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0
++#define LB0_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8
++#define LB0_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x00000001L
++#define LB0_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x00000100L
++//LB0_LB_KEYER_COLOR_R_CR
++#define LB0_LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4
++#define LB0_LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0x0000FFF0L
++//LB0_LB_KEYER_COLOR_G_Y
++#define LB0_LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4
++#define LB0_LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0x0000FFF0L
++//LB0_LB_KEYER_COLOR_B_CB
++#define LB0_LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4
++#define LB0_LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0x0000FFF0L
++//LB0_LB_KEYER_COLOR_REP_R_CR
++#define LB0_LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4
++#define LB0_LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0x0000FFF0L
++//LB0_LB_KEYER_COLOR_REP_G_Y
++#define LB0_LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4
++#define LB0_LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0x0000FFF0L
++//LB0_LB_KEYER_COLOR_REP_B_CB
++#define LB0_LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4
++#define LB0_LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0x0000FFF0L
++//LB0_LB_BUFFER_LEVEL_STATUS
++#define LB0_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0
++#define LB0_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa
++#define LB0_LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10
++#define LB0_LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c
++#define LB0_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x0000003FL
++#define LB0_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0x0000FC00L
++#define LB0_LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0x0FFF0000L
++#define LB0_LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xF0000000L
++//LB0_LB_BUFFER_URGENCY_CTRL
++#define LB0_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0
++#define LB0_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10
++#define LB0_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0x00000FFFL
++#define LB0_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0x0FFF0000L
++//LB0_LB_BUFFER_URGENCY_STATUS
++#define LB0_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0
++#define LB0_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10
++#define LB0_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0x00000FFFL
++#define LB0_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x00010000L
++//LB0_LB_BUFFER_STATUS
++#define LB0_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0
++#define LB0_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4
++#define LB0_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8
++#define LB0_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc
++#define LB0_LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10
++#define LB0_LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14
++#define LB0_LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18
++#define LB0_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0x0000000FL
++#define LB0_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x00000010L
++#define LB0_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x00000100L
++#define LB0_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x00001000L
++#define LB0_LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x00010000L
++#define LB0_LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x00100000L
++#define LB0_LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x01000000L
++//LB0_LB_NO_OUTSTANDING_REQ_STATUS
++#define LB0_LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0
++#define LB0_LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x00000001L
++//LB0_MVP_AFR_FLIP_MODE
++#define LB0_MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT 0x0
++#define LB0_MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK 0x00000003L
++//LB0_MVP_AFR_FLIP_FIFO_CNTL
++#define LB0_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT 0x0
++#define LB0_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT 0x4
++#define LB0_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT 0x8
++#define LB0_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT 0xc
++#define LB0_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK 0x0000000FL
++#define LB0_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK 0x00000010L
++#define LB0_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK 0x00000100L
++#define LB0_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK 0x00001000L
++//LB0_MVP_FLIP_LINE_NUM_INSERT
++#define LB0_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT 0x0
++#define LB0_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT 0x8
++#define LB0_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT 0x18
++#define LB0_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT 0x1e
++#define LB0_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK 0x00000003L
++#define LB0_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK 0x007FFF00L
++#define LB0_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK 0x3F000000L
++#define LB0_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK 0x40000000L
++//LB0_DC_MVP_LB_CONTROL
++#define LB0_DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT 0x0
++#define LB0_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT 0x8
++#define LB0_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT 0xc
++#define LB0_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT 0x10
++#define LB0_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT 0x14
++#define LB0_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT 0x1c
++#define LB0_DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT 0x1f
++#define LB0_DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK 0x00000003L
++#define LB0_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK 0x00000100L
++#define LB0_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK 0x00001000L
++#define LB0_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK 0x00010000L
++#define LB0_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK 0x00100000L
++#define LB0_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK 0x10000000L
++#define LB0_DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK 0x80000000L
++
++
++// addressBlock: dce_dc_dcfe0_dispdec
++//DCFE0_DCFE_CLOCK_CONTROL
++#define DCFE0_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x4
++#define DCFE0_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x8
++#define DCFE0_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0xc
++#define DCFE0_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE__SHIFT 0xf
++#define DCFE0_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE__SHIFT 0x11
++#define DCFE0_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL__SHIFT 0x18
++#define DCFE0_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE__SHIFT 0x1f
++#define DCFE0_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x00000010L
++#define DCFE0_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE_MASK 0x00000100L
++#define DCFE0_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE_MASK 0x00001000L
++#define DCFE0_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE_MASK 0x00008000L
++#define DCFE0_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE_MASK 0x00020000L
++#define DCFE0_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL_MASK 0x1F000000L
++#define DCFE0_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE_MASK 0x80000000L
++//DCFE0_DCFE_SOFT_RESET
++#define DCFE0_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET__SHIFT 0x0
++#define DCFE0_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET__SHIFT 0x1
++#define DCFE0_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET__SHIFT 0x2
++#define DCFE0_DCFE_SOFT_RESET__SCL_SOFT_RESET__SHIFT 0x3
++#define DCFE0_DCFE_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4
++#define DCFE0_DCFE_SOFT_RESET__PSCL_SOFT_RESET__SHIFT 0x5
++#define DCFE0_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET_MASK 0x00000001L
++#define DCFE0_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET_MASK 0x00000002L
++#define DCFE0_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET_MASK 0x00000004L
++#define DCFE0_DCFE_SOFT_RESET__SCL_SOFT_RESET_MASK 0x00000008L
++#define DCFE0_DCFE_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x00000010L
++#define DCFE0_DCFE_SOFT_RESET__PSCL_SOFT_RESET_MASK 0x00000020L
++//DCFE0_DCFE_MEM_PWR_CTRL
++#define DCFE0_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE__SHIFT 0x0
++#define DCFE0_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS__SHIFT 0x2
++#define DCFE0_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE__SHIFT 0x3
++#define DCFE0_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS__SHIFT 0x5
++#define DCFE0_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE__SHIFT 0x6
++#define DCFE0_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS__SHIFT 0x8
++#define DCFE0_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE__SHIFT 0x9
++#define DCFE0_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS__SHIFT 0xb
++#define DCFE0_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE__SHIFT 0xc
++#define DCFE0_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS__SHIFT 0xe
++#define DCFE0_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE__SHIFT 0xf
++#define DCFE0_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS__SHIFT 0x11
++#define DCFE0_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE__SHIFT 0x12
++#define DCFE0_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS__SHIFT 0x14
++#define DCFE0_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE__SHIFT 0x15
++#define DCFE0_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS__SHIFT 0x17
++#define DCFE0_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE__SHIFT 0x18
++#define DCFE0_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS__SHIFT 0x1a
++#define DCFE0_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE__SHIFT 0x1b
++#define DCFE0_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS__SHIFT 0x1d
++#define DCFE0_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE_MASK 0x00000003L
++#define DCFE0_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS_MASK 0x00000004L
++#define DCFE0_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE_MASK 0x00000018L
++#define DCFE0_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS_MASK 0x00000020L
++#define DCFE0_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE_MASK 0x000000C0L
++#define DCFE0_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS_MASK 0x00000100L
++#define DCFE0_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE_MASK 0x00000600L
++#define DCFE0_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS_MASK 0x00000800L
++#define DCFE0_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE_MASK 0x00003000L
++#define DCFE0_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS_MASK 0x00004000L
++#define DCFE0_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE_MASK 0x00018000L
++#define DCFE0_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK 0x00020000L
++#define DCFE0_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE_MASK 0x000C0000L
++#define DCFE0_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS_MASK 0x00100000L
++#define DCFE0_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE_MASK 0x00600000L
++#define DCFE0_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS_MASK 0x00800000L
++#define DCFE0_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE_MASK 0x03000000L
++#define DCFE0_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS_MASK 0x04000000L
++#define DCFE0_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE_MASK 0x18000000L
++#define DCFE0_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS_MASK 0x20000000L
++//DCFE0_DCFE_MEM_PWR_CTRL2
++#define DCFE0_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL__SHIFT 0x0
++#define DCFE0_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2
++#define DCFE0_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4
++#define DCFE0_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL__SHIFT 0x6
++#define DCFE0_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL__SHIFT 0x8
++#define DCFE0_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL__SHIFT 0xa
++#define DCFE0_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL__SHIFT 0xc
++#define DCFE0_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL__SHIFT 0xe
++#define DCFE0_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE__SHIFT 0x10
++#define DCFE0_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS__SHIFT 0x12
++#define DCFE0_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE__SHIFT 0x15
++#define DCFE0_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS__SHIFT 0x17
++#define DCFE0_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL_MASK 0x00000003L
++#define DCFE0_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL_MASK 0x0000000CL
++#define DCFE0_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL_MASK 0x00000030L
++#define DCFE0_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL_MASK 0x000000C0L
++#define DCFE0_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL_MASK 0x00000300L
++#define DCFE0_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL_MASK 0x00000C00L
++#define DCFE0_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL_MASK 0x00003000L
++#define DCFE0_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL_MASK 0x0000C000L
++#define DCFE0_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE_MASK 0x00030000L
++#define DCFE0_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS_MASK 0x00040000L
++#define DCFE0_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE_MASK 0x00600000L
++#define DCFE0_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS_MASK 0x00800000L
++//DCFE0_DCFE_MEM_PWR_STATUS
++#define DCFE0_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE__SHIFT 0x0
++#define DCFE0_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE__SHIFT 0x2
++#define DCFE0_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE__SHIFT 0x4
++#define DCFE0_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x6
++#define DCFE0_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE__SHIFT 0x8
++#define DCFE0_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE__SHIFT 0xa
++#define DCFE0_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE__SHIFT 0xc
++#define DCFE0_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE__SHIFT 0xe
++#define DCFE0_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT 0x10
++#define DCFE0_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE__SHIFT 0x12
++#define DCFE0_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE__SHIFT 0x14
++#define DCFE0_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE__SHIFT 0x16
++#define DCFE0_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK 0x00000003L
++#define DCFE0_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE_MASK 0x0000000CL
++#define DCFE0_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE_MASK 0x00000030L
++#define DCFE0_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE_MASK 0x000000C0L
++#define DCFE0_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE_MASK 0x00000300L
++#define DCFE0_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE_MASK 0x00000C00L
++#define DCFE0_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE_MASK 0x00003000L
++#define DCFE0_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE_MASK 0x0000C000L
++#define DCFE0_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE_MASK 0x00030000L
++#define DCFE0_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK 0x000C0000L
++#define DCFE0_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE_MASK 0x00300000L
++#define DCFE0_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE_MASK 0x00C00000L
++//DCFE0_DCFE_MISC
++#define DCFE0_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN__SHIFT 0x0
++#define DCFE0_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN_MASK 0x00000001L
++//DCFE0_DCFE_FLUSH
++#define DCFE0_DCFE_FLUSH__FLUSH_OCCURED__SHIFT 0x0
++#define DCFE0_DCFE_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT 0x1
++#define DCFE0_DCFE_FLUSH__FLUSH_DEEP__SHIFT 0x2
++#define DCFE0_DCFE_FLUSH__CLEAR_FLUSH_DEEP__SHIFT 0x3
++#define DCFE0_DCFE_FLUSH__ALL_MC_REQ_RET__SHIFT 0x4
++#define DCFE0_DCFE_FLUSH__FLUSH_OCCURED_MASK 0x00000001L
++#define DCFE0_DCFE_FLUSH__CLEAR_FLUSH_OCCURED_MASK 0x00000002L
++#define DCFE0_DCFE_FLUSH__FLUSH_DEEP_MASK 0x00000004L
++#define DCFE0_DCFE_FLUSH__CLEAR_FLUSH_DEEP_MASK 0x00000008L
++#define DCFE0_DCFE_FLUSH__ALL_MC_REQ_RET_MASK 0x00000010L
++
++
++// addressBlock: dce_dc_dc_perfmon3_dispdec
++//DC_PERFMON3_PERFCOUNTER_CNTL
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
++//DC_PERFMON3_PERFCOUNTER_CNTL2
++#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
++#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
++#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
++#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
++#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
++#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
++#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
++#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
++//DC_PERFMON3_PERFCOUNTER_STATE
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
++//DC_PERFMON3_PERFMON_CNTL
++#define DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
++#define DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
++#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
++#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
++#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
++#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
++#define DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
++#define DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
++#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
++#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
++#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
++#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
++//DC_PERFMON3_PERFMON_CNTL2
++#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
++#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
++#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
++#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
++#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
++#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
++#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
++#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
++//DC_PERFMON3_PERFMON_CVALUE_INT_MISC
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
++//DC_PERFMON3_PERFMON_CVALUE_LOW
++#define DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
++#define DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
++//DC_PERFMON3_PERFMON_HI
++#define DC_PERFMON3_PERFMON_HI__PERFMON_HI__SHIFT 0x0
++#define DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
++#define DC_PERFMON3_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
++#define DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
++//DC_PERFMON3_PERFMON_LOW
++#define DC_PERFMON3_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
++#define DC_PERFMON3_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dmif_pg0_dispdec
++//DMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1
++#define DMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
++#define DMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
++#define DMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0x0000FFFFL
++#define DMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xFFFF0000L
++//DMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2
++#define DMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
++#define DMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
++#define DMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0x0000FFFFL
++#define DMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xFFFF0000L
++//DMIF_PG0_DPG_WATERMARK_MASK_CONTROL
++#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
++#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x4
++#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
++#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK__SHIFT 0xc
++#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0xf
++#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x12
++#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL__SHIFT 0x13
++#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL__SHIFT 0x14
++#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000007L
++#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000070L
++#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x00000700L
++#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK_MASK 0x00007000L
++#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00038000L
++#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x00040000L
++#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL_MASK 0x00080000L
++#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL_MASK 0x3FF00000L
++//DMIF_PG0_DPG_PIPE_URGENCY_CONTROL
++#define DMIF_PG0_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
++#define DMIF_PG0_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
++#define DMIF_PG0_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0x0000FFFFL
++#define DMIF_PG0_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xFFFF0000L
++//DMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL
++#define DMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK__SHIFT 0x0
++#define DMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK__SHIFT 0x10
++#define DMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK_MASK 0x0000FFFFL
++#define DMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK_MASK 0xFFFF0000L
++//DMIF_PG0_DPG_PIPE_STUTTER_CONTROL
++#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
++#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
++#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
++#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
++#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
++#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
++#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
++#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH__SHIFT 0x10
++#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x14
++#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x15
++#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x16
++#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x17
++#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0x1a
++#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0x1b
++#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L
++#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L
++#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x00000020L
++#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x00000040L
++#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x00000080L
++#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x00000400L
++#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x00000800L
++#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH_MASK 0x00010000L
++#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x00100000L
++#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x00200000L
++#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x00400000L
++#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x00800000L
++#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x04000000L
++#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x08000000L
++//DMIF_PG0_DPG_PIPE_STUTTER_CONTROL2
++#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x0
++#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK__SHIFT 0x10
++#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0x0000FFFFL
++#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK 0xFFFF0000L
++//DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL
++#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE__SHIFT 0x0
++#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE__SHIFT 0x1
++#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
++#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
++#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
++#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
++#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK__SHIFT 0xf
++#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE_MASK 0x00000001L
++#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE_MASK 0x00000002L
++#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L
++#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x00000100L
++#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON_MASK 0x00000200L
++#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT_MASK 0x00000400L
++#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK_MASK 0xFFFF8000L
++//DMIF_PG0_DPG_REPEATER_PROGRAM
++#define DMIF_PG0_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
++#define DMIF_PG0_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
++#define DMIF_PG0_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x00000007L
++#define DMIF_PG0_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x00000070L
++//DMIF_PG0_DPG_CHK_PRE_PROC_CNTL
++#define DMIF_PG0_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0
++#define DMIF_PG0_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x00000001L
++//DMIF_PG0_DPG_DVMM_STATUS
++#define DMIF_PG0_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED__SHIFT 0x0
++#define DMIF_PG0_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED__SHIFT 0x1
++#define DMIF_PG0_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR__SHIFT 0x4
++#define DMIF_PG0_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR__SHIFT 0x5
++#define DMIF_PG0_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_MASK 0x00000001L
++#define DMIF_PG0_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_MASK 0x00000002L
++#define DMIF_PG0_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR_MASK 0x00000010L
++#define DMIF_PG0_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR_MASK 0x00000020L
++
++
++// addressBlock: dce_dc_scl0_dispdec
++//SCL0_SCL_COEF_RAM_SELECT
++#define SCL0_SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0
++#define SCL0_SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8
++#define SCL0_SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10
++#define SCL0_SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x0000000FL
++#define SCL0_SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x00000F00L
++#define SCL0_SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x00070000L
++//SCL0_SCL_COEF_RAM_TAP_DATA
++#define SCL0_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0
++#define SCL0_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
++#define SCL0_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10
++#define SCL0_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
++#define SCL0_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL
++#define SCL0_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L
++#define SCL0_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L
++#define SCL0_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L
++//SCL0_SCL_MODE
++#define SCL0_SCL_MODE__SCL_MODE__SHIFT 0x0
++#define SCL0_SCL_MODE__SCL_PSCL_EN__SHIFT 0x4
++#define SCL0_SCL_MODE__SCL_MODE_MASK 0x00000003L
++#define SCL0_SCL_MODE__SCL_PSCL_EN_MASK 0x00000010L
++//SCL0_SCL_TAP_CONTROL
++#define SCL0_SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0
++#define SCL0_SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x8
++#define SCL0_SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x00000007L
++#define SCL0_SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0x00000F00L
++//SCL0_SCL_CONTROL
++#define SCL0_SCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
++#define SCL0_SCL_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4
++#define SCL0_SCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L
++#define SCL0_SCL_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x00000010L
++//SCL0_SCL_BYPASS_CONTROL
++#define SCL0_SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT 0x0
++#define SCL0_SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x00000003L
++//SCL0_SCL_MANUAL_REPLICATE_CONTROL
++#define SCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
++#define SCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
++#define SCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL
++#define SCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L
++//SCL0_SCL_AUTOMATIC_MODE_CONTROL
++#define SCL0_SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0
++#define SCL0_SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10
++#define SCL0_SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x00000001L
++#define SCL0_SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x00010000L
++//SCL0_SCL_HORZ_FILTER_CONTROL
++#define SCL0_SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT 0x0
++#define SCL0_SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
++#define SCL0_SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK 0x00000001L
++#define SCL0_SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
++//SCL0_SCL_HORZ_FILTER_SCALE_RATIO
++#define SCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
++#define SCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL
++//SCL0_SCL_HORZ_FILTER_INIT
++#define SCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
++#define SCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
++#define SCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL
++#define SCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L
++//SCL0_SCL_VERT_FILTER_CONTROL
++#define SCL0_SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT 0x0
++#define SCL0_SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
++#define SCL0_SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK 0x00000001L
++#define SCL0_SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
++//SCL0_SCL_VERT_FILTER_SCALE_RATIO
++#define SCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
++#define SCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL
++//SCL0_SCL_VERT_FILTER_INIT
++#define SCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
++#define SCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
++#define SCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL
++#define SCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x07000000L
++//SCL0_SCL_VERT_FILTER_INIT_BOT
++#define SCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
++#define SCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
++#define SCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL
++#define SCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x07000000L
++//SCL0_SCL_ROUND_OFFSET
++#define SCL0_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0
++#define SCL0_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10
++#define SCL0_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0x0000FFFFL
++#define SCL0_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xFFFF0000L
++//SCL0_SCL_UPDATE
++#define SCL0_SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
++#define SCL0_SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8
++#define SCL0_SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10
++#define SCL0_SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18
++#define SCL0_SCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L
++#define SCL0_SCL_UPDATE__SCL_UPDATE_TAKEN_MASK 0x00000100L
++#define SCL0_SCL_UPDATE__SCL_UPDATE_LOCK_MASK 0x00010000L
++#define SCL0_SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x01000000L
++//SCL0_SCL_F_SHARP_CONTROL
++#define SCL0_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT 0x0
++#define SCL0_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT 0x4
++#define SCL0_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT 0x8
++#define SCL0_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT 0xc
++#define SCL0_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK 0x00000007L
++#define SCL0_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK 0x00000010L
++#define SCL0_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK 0x00000700L
++#define SCL0_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK 0x00001000L
++//SCL0_SCL_ALU_CONTROL
++#define SCL0_SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0
++#define SCL0_SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x00000001L
++//SCL0_SCL_COEF_RAM_CONFLICT_STATUS
++#define SCL0_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT 0x0
++#define SCL0_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT 0x8
++#define SCL0_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT 0xc
++#define SCL0_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10
++#define SCL0_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK 0x00000001L
++#define SCL0_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK 0x00000100L
++#define SCL0_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK 0x00001000L
++#define SCL0_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK 0x00010000L
++//SCL0_VIEWPORT_START_SECONDARY
++#define SCL0_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0
++#define SCL0_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10
++#define SCL0_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x00003FFFL
++#define SCL0_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3FFF0000L
++//SCL0_VIEWPORT_START
++#define SCL0_VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0
++#define SCL0_VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10
++#define SCL0_VIEWPORT_START__VIEWPORT_Y_START_MASK 0x00003FFFL
++#define SCL0_VIEWPORT_START__VIEWPORT_X_START_MASK 0x3FFF0000L
++//SCL0_VIEWPORT_SIZE
++#define SCL0_VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0
++#define SCL0_VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10
++#define SCL0_VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x00003FFFL
++#define SCL0_VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x3FFF0000L
++//SCL0_EXT_OVERSCAN_LEFT_RIGHT
++#define SCL0_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
++#define SCL0_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
++#define SCL0_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL
++#define SCL0_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L
++//SCL0_EXT_OVERSCAN_TOP_BOTTOM
++#define SCL0_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
++#define SCL0_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
++#define SCL0_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL
++#define SCL0_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L
++//SCL0_SCL_MODE_CHANGE_DET1
++#define SCL0_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0
++#define SCL0_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4
++#define SCL0_SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7
++#define SCL0_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x00000001L
++#define SCL0_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x00000010L
++#define SCL0_SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0x0FFFFF80L
++//SCL0_SCL_MODE_CHANGE_DET2
++#define SCL0_SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0
++#define SCL0_SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x001FFFFFL
++//SCL0_SCL_MODE_CHANGE_DET3
++#define SCL0_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0
++#define SCL0_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10
++#define SCL0_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x00003FFFL
++#define SCL0_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3FFF0000L
++//SCL0_SCL_MODE_CHANGE_MASK
++#define SCL0_SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0
++#define SCL0_SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x00000001L
++
++
++// addressBlock: dce_dc_blnd0_dispdec
++//BLND0_BLND_CONTROL
++#define BLND0_BLND_CONTROL__BLND_GLOBAL_GAIN__SHIFT 0x0
++#define BLND0_BLND_CONTROL__BLND_MODE__SHIFT 0x8
++#define BLND0_BLND_CONTROL__BLND_STEREO_TYPE__SHIFT 0xa
++#define BLND0_BLND_CONTROL__BLND_STEREO_POLARITY__SHIFT 0xc
++#define BLND0_BLND_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT 0xd
++#define BLND0_BLND_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10
++#define BLND0_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x12
++#define BLND0_BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14
++#define BLND0_BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18
++#define BLND0_BLND_CONTROL__BLND_GLOBAL_GAIN_MASK 0x000000FFL
++#define BLND0_BLND_CONTROL__BLND_MODE_MASK 0x00000300L
++#define BLND0_BLND_CONTROL__BLND_STEREO_TYPE_MASK 0x00000C00L
++#define BLND0_BLND_CONTROL__BLND_STEREO_POLARITY_MASK 0x00001000L
++#define BLND0_BLND_CONTROL__BLND_FEEDTHROUGH_EN_MASK 0x00002000L
++#define BLND0_BLND_CONTROL__BLND_ALPHA_MODE_MASK 0x00030000L
++#define BLND0_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00040000L
++#define BLND0_BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x00100000L
++#define BLND0_BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xFF000000L
++//BLND0_BLND_SM_CONTROL2
++#define BLND0_BLND_SM_CONTROL2__SM_MODE__SHIFT 0x0
++#define BLND0_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4
++#define BLND0_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5
++#define BLND0_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
++#define BLND0_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
++#define BLND0_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18
++#define BLND0_BLND_SM_CONTROL2__SM_MODE_MASK 0x00000007L
++#define BLND0_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x00000010L
++#define BLND0_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x00000020L
++#define BLND0_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L
++#define BLND0_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L
++#define BLND0_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x01000000L
++//BLND0_BLND_CONTROL2
++#define BLND0_BLND_CONTROL2__PTI_ENABLE__SHIFT 0x0
++#define BLND0_BLND_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT 0x4
++#define BLND0_BLND_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT 0x6
++#define BLND0_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT 0x7
++#define BLND0_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT 0x8
++#define BLND0_BLND_CONTROL2__PTI_ENABLE_MASK 0x00000001L
++#define BLND0_BLND_CONTROL2__PTI_NEW_PIXEL_GAP_MASK 0x00000030L
++#define BLND0_BLND_CONTROL2__BLND_NEW_PIXEL_MODE_MASK 0x00000040L
++#define BLND0_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK 0x00000080L
++#define BLND0_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK 0x00000100L
++//BLND0_BLND_UPDATE
++#define BLND0_BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0
++#define BLND0_BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8
++#define BLND0_BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10
++#define BLND0_BLND_UPDATE__BLND_UPDATE_PENDING_MASK 0x00000001L
++#define BLND0_BLND_UPDATE__BLND_UPDATE_TAKEN_MASK 0x00000100L
++#define BLND0_BLND_UPDATE__BLND_UPDATE_LOCK_MASK 0x00010000L
++//BLND0_BLND_UNDERFLOW_INTERRUPT
++#define BLND0_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0
++#define BLND0_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8
++#define BLND0_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc
++#define BLND0_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10
++#define BLND0_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x00000001L
++#define BLND0_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x00000100L
++#define BLND0_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x00001000L
++#define BLND0_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x00030000L
++//BLND0_BLND_V_UPDATE_LOCK
++#define BLND0_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0
++#define BLND0_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1
++#define BLND0_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10
++#define BLND0_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c
++#define BLND0_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT 0x1d
++#define BLND0_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT 0x1f
++#define BLND0_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x00000001L
++#define BLND0_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x00000002L
++#define BLND0_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x00010000L
++#define BLND0_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000L
++#define BLND0_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK 0x20000000L
++#define BLND0_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK 0x80000000L
++//BLND0_BLND_REG_UPDATE_STATUS
++#define BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT 0x0
++#define BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT 0x1
++#define BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2
++#define BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3
++#define BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT 0x6
++#define BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT 0x7
++#define BLND0_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT 0x8
++#define BLND0_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT 0x9
++#define BLND0_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT 0xa
++#define BLND0_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT 0xb
++#define BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK 0x00000001L
++#define BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK 0x00000002L
++#define BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK 0x00000004L
++#define BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK 0x00000008L
++#define BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK 0x00000040L
++#define BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK 0x00000080L
++#define BLND0_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK 0x00000100L
++#define BLND0_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK 0x00000200L
++#define BLND0_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK 0x00000400L
++#define BLND0_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK 0x00000800L
++
++
++// addressBlock: dce_dc_crtc0_dispdec
++//CRTC0_CRTC_H_BLANK_EARLY_NUM
++#define CRTC0_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0
++#define CRTC0_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10
++#define CRTC0_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x000003FFL
++#define CRTC0_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x00010000L
++//CRTC0_CRTC_H_TOTAL
++#define CRTC0_CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0
++#define CRTC0_CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x00003FFFL
++//CRTC0_CRTC_H_BLANK_START_END
++#define CRTC0_CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0
++#define CRTC0_CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10
++#define CRTC0_CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x00003FFFL
++#define CRTC0_CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3FFF0000L
++//CRTC0_CRTC_H_SYNC_A
++#define CRTC0_CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0
++#define CRTC0_CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10
++#define CRTC0_CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x00003FFFL
++#define CRTC0_CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3FFF0000L
++//CRTC0_CRTC_H_SYNC_A_CNTL
++#define CRTC0_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0
++#define CRTC0_CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10
++#define CRTC0_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11
++#define CRTC0_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x00000001L
++#define CRTC0_CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x00010000L
++#define CRTC0_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x00020000L
++//CRTC0_CRTC_H_SYNC_B
++#define CRTC0_CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0
++#define CRTC0_CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10
++#define CRTC0_CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x00003FFFL
++#define CRTC0_CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x3FFF0000L
++//CRTC0_CRTC_H_SYNC_B_CNTL
++#define CRTC0_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0
++#define CRTC0_CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10
++#define CRTC0_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11
++#define CRTC0_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x00000001L
++#define CRTC0_CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x00010000L
++#define CRTC0_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x00020000L
++//CRTC0_CRTC_VBI_END
++#define CRTC0_CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x0
++#define CRTC0_CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x10
++#define CRTC0_CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x00003FFFL
++#define CRTC0_CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x3FFF0000L
++//CRTC0_CRTC_V_TOTAL
++#define CRTC0_CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0
++#define CRTC0_CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x00003FFFL
++//CRTC0_CRTC_V_TOTAL_MIN
++#define CRTC0_CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0
++#define CRTC0_CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x00003FFFL
++//CRTC0_CRTC_V_TOTAL_MAX
++#define CRTC0_CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0
++#define CRTC0_CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10
++#define CRTC0_CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x00003FFFL
++#define CRTC0_CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x00010000L
++//CRTC0_CRTC_V_TOTAL_CONTROL
++#define CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0
++#define CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4
++#define CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8
++#define CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc
++#define CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf
++#define CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10
++#define CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x00000001L
++#define CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x00000010L
++#define CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x00000100L
++#define CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x00001000L
++#define CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00008000L
++#define CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L
++//CRTC0_CRTC_V_TOTAL_INT_STATUS
++#define CRTC0_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0
++#define CRTC0_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4
++#define CRTC0_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8
++#define CRTC0_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc
++#define CRTC0_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L
++#define CRTC0_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L
++#define CRTC0_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L
++#define CRTC0_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L
++//CRTC0_CRTC_VSYNC_NOM_INT_STATUS
++#define CRTC0_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0
++#define CRTC0_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4
++#define CRTC0_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x00000001L
++#define CRTC0_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L
++//CRTC0_CRTC_V_BLANK_START_END
++#define CRTC0_CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0
++#define CRTC0_CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10
++#define CRTC0_CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x00003FFFL
++#define CRTC0_CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3FFF0000L
++//CRTC0_CRTC_V_SYNC_A
++#define CRTC0_CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0
++#define CRTC0_CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10
++#define CRTC0_CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x00003FFFL
++#define CRTC0_CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3FFF0000L
++//CRTC0_CRTC_V_SYNC_A_CNTL
++#define CRTC0_CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0
++#define CRTC0_CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x00000001L
++//CRTC0_CRTC_V_SYNC_B
++#define CRTC0_CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0
++#define CRTC0_CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10
++#define CRTC0_CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x00003FFFL
++#define CRTC0_CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x3FFF0000L
++//CRTC0_CRTC_V_SYNC_B_CNTL
++#define CRTC0_CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0
++#define CRTC0_CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x00000001L
++//CRTC0_CRTC_DTMTEST_CNTL
++#define CRTC0_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0
++#define CRTC0_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1
++#define CRTC0_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x00000001L
++#define CRTC0_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x0000001EL
++//CRTC0_CRTC_DTMTEST_STATUS_POSITION
++#define CRTC0_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0
++#define CRTC0_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10
++#define CRTC0_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x00003FFFL
++#define CRTC0_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x3FFF0000L
++//CRTC0_CRTC_TRIGA_CNTL
++#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0
++#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5
++#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8
++#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9
++#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa
++#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb
++#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
++#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
++#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14
++#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18
++#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f
++#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x0000001FL
++#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0x000000E0L
++#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000100L
++#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x00000200L
++#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x00000400L
++#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x00000800L
++#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
++#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
++#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L
++#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1F000000L
++#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000L
++//CRTC0_CRTC_TRIGA_MANUAL_TRIG
++#define CRTC0_CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0
++#define CRTC0_CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x00000001L
++//CRTC0_CRTC_TRIGB_CNTL
++#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0
++#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5
++#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8
++#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9
++#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa
++#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb
++#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
++#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
++#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14
++#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18
++#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f
++#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x0000001FL
++#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0x000000E0L
++#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000100L
++#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x00000200L
++#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x00000400L
++#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x00000800L
++#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
++#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
++#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L
++#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1F000000L
++#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000L
++//CRTC0_CRTC_TRIGB_MANUAL_TRIG
++#define CRTC0_CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0
++#define CRTC0_CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x00000001L
++//CRTC0_CRTC_FORCE_COUNT_NOW_CNTL
++#define CRTC0_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0
++#define CRTC0_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4
++#define CRTC0_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8
++#define CRTC0_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10
++#define CRTC0_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18
++#define CRTC0_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x00000003L
++#define CRTC0_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L
++#define CRTC0_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L
++#define CRTC0_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L
++#define CRTC0_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L
++//CRTC0_CRTC_FLOW_CONTROL
++#define CRTC0_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0
++#define CRTC0_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8
++#define CRTC0_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10
++#define CRTC0_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18
++#define CRTC0_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL
++#define CRTC0_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x00000100L
++#define CRTC0_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L
++#define CRTC0_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L
++//CRTC0_CRTC_STEREO_FORCE_NEXT_EYE
++#define CRTC0_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0
++#define CRTC0_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER__SHIFT 0x8
++#define CRTC0_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER__SHIFT 0x10
++#define CRTC0_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L
++#define CRTC0_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L
++#define CRTC0_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L
++//CRTC0_CRTC_AVSYNC_COUNTER
++#define CRTC0_CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER__SHIFT 0x0
++#define CRTC0_CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER_MASK 0xFFFFFFFFL
++//CRTC0_CRTC_CONTROL
++#define CRTC0_CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x0
++#define CRTC0_CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4
++#define CRTC0_CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8
++#define CRTC0_CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc
++#define CRTC0_CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd
++#define CRTC0_CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe
++#define CRTC0_CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10
++#define CRTC0_CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14
++#define CRTC0_CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d
++#define CRTC0_CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e
++#define CRTC0_CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f
++#define CRTC0_CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x00000001L
++#define CRTC0_CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x00000010L
++#define CRTC0_CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x00000300L
++#define CRTC0_CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x00001000L
++#define CRTC0_CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x00002000L
++#define CRTC0_CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x00004000L
++#define CRTC0_CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x00010000L
++#define CRTC0_CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x00700000L
++#define CRTC0_CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000L
++#define CRTC0_CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L
++#define CRTC0_CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L
++//CRTC0_CRTC_BLANK_CONTROL
++#define CRTC0_CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0
++#define CRTC0_CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8
++#define CRTC0_CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10
++#define CRTC0_CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x00000001L
++#define CRTC0_CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x00000100L
++#define CRTC0_CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x00010000L
++//CRTC0_CRTC_INTERLACE_CONTROL
++#define CRTC0_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0
++#define CRTC0_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10
++#define CRTC0_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x00000001L
++#define CRTC0_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L
++//CRTC0_CRTC_INTERLACE_STATUS
++#define CRTC0_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0
++#define CRTC0_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1
++#define CRTC0_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x00000001L
++#define CRTC0_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x00000002L
++//CRTC0_CRTC_FIELD_INDICATION_CONTROL
++#define CRTC0_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0
++#define CRTC0_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1
++#define CRTC0_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x00000001L
++#define CRTC0_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x00000002L
++//CRTC0_CRTC_PIXEL_DATA_READBACK0
++#define CRTC0_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0
++#define CRTC0_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10
++#define CRTC0_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0x00000FFFL
++#define CRTC0_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0x0FFF0000L
++//CRTC0_CRTC_PIXEL_DATA_READBACK1
++#define CRTC0_CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0
++#define CRTC0_CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0x00000FFFL
++//CRTC0_CRTC_STATUS
++#define CRTC0_CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x0
++#define CRTC0_CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1
++#define CRTC0_CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x2
++#define CRTC0_CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x3
++#define CRTC0_CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x4
++#define CRTC0_CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5
++#define CRTC0_CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x10
++#define CRTC0_CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11
++#define CRTC0_CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x12
++#define CRTC0_CRTC_STATUS__CRTC_V_BLANK_MASK 0x00000001L
++#define CRTC0_CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x00000002L
++#define CRTC0_CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x00000004L
++#define CRTC0_CRTC_STATUS__CRTC_V_UPDATE_MASK 0x00000008L
++#define CRTC0_CRTC_STATUS__CRTC_V_START_LINE_MASK 0x00000010L
++#define CRTC0_CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x00000020L
++#define CRTC0_CRTC_STATUS__CRTC_H_BLANK_MASK 0x00010000L
++#define CRTC0_CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x00020000L
++#define CRTC0_CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x00040000L
++//CRTC0_CRTC_STATUS_POSITION
++#define CRTC0_CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0
++#define CRTC0_CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10
++#define CRTC0_CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x00003FFFL
++#define CRTC0_CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x3FFF0000L
++//CRTC0_CRTC_NOM_VERT_POSITION
++#define CRTC0_CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0
++#define CRTC0_CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x00003FFFL
++//CRTC0_CRTC_STATUS_FRAME_COUNT
++#define CRTC0_CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0
++#define CRTC0_CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0x00FFFFFFL
++//CRTC0_CRTC_STATUS_VF_COUNT
++#define CRTC0_CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0
++#define CRTC0_CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x3FFFFFFFL
++//CRTC0_CRTC_STATUS_HV_COUNT
++#define CRTC0_CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0
++#define CRTC0_CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x3FFFFFFFL
++//CRTC0_CRTC_COUNT_CONTROL
++#define CRTC0_CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0
++#define CRTC0_CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1
++#define CRTC0_CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x00000001L
++#define CRTC0_CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x0000001EL
++//CRTC0_CRTC_COUNT_RESET
++#define CRTC0_CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0
++#define CRTC0_CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x00000001L
++//CRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE
++#define CRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0
++#define CRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L
++//CRTC0_CRTC_VERT_SYNC_CONTROL
++#define CRTC0_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0
++#define CRTC0_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8
++#define CRTC0_CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10
++#define CRTC0_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L
++#define CRTC0_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L
++#define CRTC0_CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L
++//CRTC0_CRTC_STEREO_STATUS
++#define CRTC0_CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0
++#define CRTC0_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8
++#define CRTC0_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10
++#define CRTC0_CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG__SHIFT 0x14
++#define CRTC0_CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18
++#define CRTC0_CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x00000001L
++#define CRTC0_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x00000100L
++#define CRTC0_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x00010000L
++#define CRTC0_CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG_MASK 0x00100000L
++#define CRTC0_CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L
++//CRTC0_CRTC_STEREO_CONTROL
++#define CRTC0_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0
++#define CRTC0_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf
++#define CRTC0_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10
++#define CRTC0_CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11
++#define CRTC0_CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12
++#define CRTC0_CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM__SHIFT 0x13
++#define CRTC0_CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14
++#define CRTC0_CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18
++#define CRTC0_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00003FFFL
++#define CRTC0_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L
++#define CRTC0_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x00010000L
++#define CRTC0_CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L
++#define CRTC0_CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L
++#define CRTC0_CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM_MASK 0x00080000L
++#define CRTC0_CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L
++#define CRTC0_CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x01000000L
++//CRTC0_CRTC_SNAPSHOT_STATUS
++#define CRTC0_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0
++#define CRTC0_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1
++#define CRTC0_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2
++#define CRTC0_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x00000001L
++#define CRTC0_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x00000002L
++#define CRTC0_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L
++//CRTC0_CRTC_SNAPSHOT_CONTROL
++#define CRTC0_CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0
++#define CRTC0_CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L
++//CRTC0_CRTC_SNAPSHOT_POSITION
++#define CRTC0_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0
++#define CRTC0_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10
++#define CRTC0_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x00003FFFL
++#define CRTC0_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x3FFF0000L
++//CRTC0_CRTC_SNAPSHOT_FRAME
++#define CRTC0_CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0
++#define CRTC0_CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL
++//CRTC0_CRTC_START_LINE_CONTROL
++#define CRTC0_CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0
++#define CRTC0_CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x1
++#define CRTC0_CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x2
++#define CRTC0_CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x8
++#define CRTC0_CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc
++#define CRTC0_CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x00000001L
++#define CRTC0_CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x00000002L
++#define CRTC0_CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x00000004L
++#define CRTC0_CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x00000100L
++#define CRTC0_CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0x000FF000L
++//CRTC0_CRTC_INTERRUPT_CONTROL
++#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0
++#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1
++#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4
++#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5
++#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8
++#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9
++#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10
++#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11
++#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18
++#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19
++#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a
++#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b
++#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c
++#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d
++#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e
++#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f
++#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x00000001L
++#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x00000002L
++#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x00000010L
++#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x00000020L
++#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L
++#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L
++#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L
++#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L
++#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x01000000L
++#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x02000000L
++#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x04000000L
++#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x08000000L
++#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000L
++#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000L
++#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L
++#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L
++//CRTC0_CRTC_UPDATE_LOCK
++#define CRTC0_CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0
++#define CRTC0_CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x00000001L
++//CRTC0_CRTC_DOUBLE_BUFFER_CONTROL
++#define CRTC0_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0
++#define CRTC0_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8
++#define CRTC0_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10
++#define CRTC0_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18
++#define CRTC0_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x19
++#define CRTC0_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x00000001L
++#define CRTC0_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x00000100L
++#define CRTC0_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L
++#define CRTC0_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x01000000L
++#define CRTC0_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x02000000L
++//CRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE
++#define CRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0
++#define CRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x00000001L
++//CRTC0_CRTC_TEST_PATTERN_CONTROL
++#define CRTC0_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0
++#define CRTC0_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8
++#define CRTC0_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10
++#define CRTC0_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18
++#define CRTC0_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x00000001L
++#define CRTC0_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x00000700L
++#define CRTC0_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L
++#define CRTC0_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xFF000000L
++//CRTC0_CRTC_TEST_PATTERN_PARAMETERS
++#define CRTC0_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0
++#define CRTC0_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4
++#define CRTC0_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8
++#define CRTC0_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc
++#define CRTC0_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10
++#define CRTC0_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0x0000000FL
++#define CRTC0_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0x000000F0L
++#define CRTC0_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0x00000F00L
++#define CRTC0_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0x0000F000L
++#define CRTC0_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xFFFF0000L
++//CRTC0_CRTC_TEST_PATTERN_COLOR
++#define CRTC0_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0
++#define CRTC0_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10
++#define CRTC0_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0x0000FFFFL
++#define CRTC0_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x003F0000L
++//CRTC0_CRTC_MASTER_UPDATE_LOCK
++#define CRTC0_CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0
++#define CRTC0_CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8
++#define CRTC0_CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK__SHIFT 0x10
++#define CRTC0_CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x00000001L
++#define CRTC0_CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x00000100L
++#define CRTC0_CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK_MASK 0x00010000L
++//CRTC0_CRTC_MASTER_UPDATE_MODE
++#define CRTC0_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0
++#define CRTC0_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10
++#define CRTC0_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x00000007L
++#define CRTC0_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00030000L
++//CRTC0_CRTC_MVP_INBAND_CNTL_INSERT
++#define CRTC0_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0
++#define CRTC0_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8
++#define CRTC0_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x00000003L
++#define CRTC0_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xFFFFFF00L
++//CRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER
++#define CRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0
++#define CRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0x000000FFL
++//CRTC0_CRTC_MVP_STATUS
++#define CRTC0_CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0
++#define CRTC0_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4
++#define CRTC0_CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10
++#define CRTC0_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14
++#define CRTC0_CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x00000001L
++#define CRTC0_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x00000010L
++#define CRTC0_CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x00010000L
++#define CRTC0_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x00100000L
++//CRTC0_CRTC_MASTER_EN
++#define CRTC0_CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0
++#define CRTC0_CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x00000001L
++//CRTC0_CRTC_ALLOW_STOP_OFF_V_CNT
++#define CRTC0_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0
++#define CRTC0_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10
++#define CRTC0_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0x000000FFL
++#define CRTC0_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x00010000L
++//CRTC0_CRTC_V_UPDATE_INT_STATUS
++#define CRTC0_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0
++#define CRTC0_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8
++#define CRTC0_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x00000001L
++#define CRTC0_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x00000100L
++//CRTC0_CRTC_OVERSCAN_COLOR
++#define CRTC0_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0
++#define CRTC0_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa
++#define CRTC0_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14
++#define CRTC0_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x000003FFL
++#define CRTC0_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0x000FFC00L
++#define CRTC0_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3FF00000L
++//CRTC0_CRTC_OVERSCAN_COLOR_EXT
++#define CRTC0_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0
++#define CRTC0_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8
++#define CRTC0_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10
++#define CRTC0_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x00000003L
++#define CRTC0_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x00000300L
++#define CRTC0_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x00030000L
++//CRTC0_CRTC_BLANK_DATA_COLOR
++#define CRTC0_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0
++#define CRTC0_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa
++#define CRTC0_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14
++#define CRTC0_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL
++#define CRTC0_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L
++#define CRTC0_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L
++//CRTC0_CRTC_BLANK_DATA_COLOR_EXT
++#define CRTC0_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0
++#define CRTC0_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8
++#define CRTC0_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10
++#define CRTC0_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x00000003L
++#define CRTC0_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00000300L
++#define CRTC0_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x00030000L
++//CRTC0_CRTC_BLACK_COLOR
++#define CRTC0_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0
++#define CRTC0_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa
++#define CRTC0_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14
++#define CRTC0_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x000003FFL
++#define CRTC0_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0x000FFC00L
++#define CRTC0_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3FF00000L
++//CRTC0_CRTC_BLACK_COLOR_EXT
++#define CRTC0_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0
++#define CRTC0_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8
++#define CRTC0_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10
++#define CRTC0_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x00000003L
++#define CRTC0_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x00000300L
++#define CRTC0_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x00030000L
++//CRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION
++#define CRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0
++#define CRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10
++#define CRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00003FFFL
++#define CRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x3FFF0000L
++//CRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL
++#define CRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4
++#define CRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8
++#define CRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc
++#define CRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10
++#define CRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14
++#define CRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18
++#define CRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L
++#define CRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L
++#define CRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L
++#define CRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L
++#define CRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L
++#define CRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L
++//CRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION
++#define CRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0
++#define CRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00003FFFL
++//CRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL
++#define CRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8
++#define CRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc
++#define CRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10
++#define CRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14
++#define CRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18
++#define CRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L
++#define CRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L
++#define CRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L
++#define CRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L
++#define CRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L
++//CRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION
++#define CRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0
++#define CRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00003FFFL
++//CRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL
++#define CRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8
++#define CRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc
++#define CRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10
++#define CRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14
++#define CRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18
++#define CRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L
++#define CRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L
++#define CRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L
++#define CRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L
++#define CRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L
++//CRTC0_CRTC_CRC_CNTL
++#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0
++#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4
++#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8
++#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc
++#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
++#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14
++#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18
++#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC_EN_MASK 0x00000001L
++#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x00000010L
++#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x00000300L
++#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x00003000L
++#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
++#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x00700000L
++#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x07000000L
++//CRTC0_CRTC_CRC0_WINDOWA_X_CONTROL
++#define CRTC0_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0
++#define CRTC0_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10
++#define CRTC0_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x00003FFFL
++#define CRTC0_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3FFF0000L
++//CRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL
++#define CRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0
++#define CRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10
++#define CRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x00003FFFL
++#define CRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3FFF0000L
++//CRTC0_CRTC_CRC0_WINDOWB_X_CONTROL
++#define CRTC0_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0
++#define CRTC0_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10
++#define CRTC0_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x00003FFFL
++#define CRTC0_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3FFF0000L
++//CRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL
++#define CRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0
++#define CRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10
++#define CRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x00003FFFL
++#define CRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3FFF0000L
++//CRTC0_CRTC_CRC0_DATA_RG
++#define CRTC0_CRTC_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0
++#define CRTC0_CRTC_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10
++#define CRTC0_CRTC_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL
++#define CRTC0_CRTC_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L
++//CRTC0_CRTC_CRC0_DATA_B
++#define CRTC0_CRTC_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0
++#define CRTC0_CRTC_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL
++//CRTC0_CRTC_CRC1_WINDOWA_X_CONTROL
++#define CRTC0_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0
++#define CRTC0_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10
++#define CRTC0_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x00003FFFL
++#define CRTC0_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3FFF0000L
++//CRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL
++#define CRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0
++#define CRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10
++#define CRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x00003FFFL
++#define CRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3FFF0000L
++//CRTC0_CRTC_CRC1_WINDOWB_X_CONTROL
++#define CRTC0_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0
++#define CRTC0_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10
++#define CRTC0_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x00003FFFL
++#define CRTC0_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3FFF0000L
++//CRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL
++#define CRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0
++#define CRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10
++#define CRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x00003FFFL
++#define CRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3FFF0000L
++//CRTC0_CRTC_CRC1_DATA_RG
++#define CRTC0_CRTC_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0
++#define CRTC0_CRTC_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10
++#define CRTC0_CRTC_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL
++#define CRTC0_CRTC_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L
++//CRTC0_CRTC_CRC1_DATA_B
++#define CRTC0_CRTC_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0
++#define CRTC0_CRTC_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL
++//CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL
++#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE__SHIFT 0x0
++#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__SHIFT 0x3
++#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__SHIFT 0x4
++#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__SHIFT 0x5
++#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__SHIFT 0x8
++#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__SHIFT 0x9
++#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__SHIFT 0xc
++#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__SHIFT 0xd
++#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__SHIFT 0xe
++#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE__SHIFT 0x18
++#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE__SHIFT 0x1c
++#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE_MASK 0x00000003L
++#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_MASK 0x00000008L
++#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_MASK 0x00000010L
++#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_MASK 0x00000060L
++#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_MASK 0x00000100L
++#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_MASK 0x00000200L
++#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_MASK 0x00001000L
++#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_MASK 0x00002000L
++#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_MASK 0x00004000L
++#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE_MASK 0x07000000L
++#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE_MASK 0x70000000L
++//CRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START
++#define CRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X__SHIFT 0x0
++#define CRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y__SHIFT 0x10
++#define CRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X_MASK 0x00003FFFL
++#define CRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y_MASK 0x3FFF0000L
++//CRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END
++#define CRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X__SHIFT 0x0
++#define CRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y__SHIFT 0x10
++#define CRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X_MASK 0x00003FFFL
++#define CRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y_MASK 0x3FFF0000L
++//CRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL
++#define CRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__SHIFT 0x0
++#define CRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS__SHIFT 0x4
++#define CRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS__SHIFT 0x8
++#define CRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__SHIFT 0x10
++#define CRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__SHIFT 0x14
++#define CRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__SHIFT 0x1d
++#define CRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_MASK 0x00000001L
++#define CRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS_MASK 0x00000010L
++#define CRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS_MASK 0x00000100L
++#define CRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_MASK 0x00010000L
++#define CRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_MASK 0x00100000L
++#define CRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_MASK 0xE0000000L
++//CRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL
++#define CRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE__SHIFT 0x0
++#define CRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS__SHIFT 0x4
++#define CRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS__SHIFT 0x8
++#define CRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR__SHIFT 0x10
++#define CRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE__SHIFT 0x14
++#define CRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE_MASK 0x00000001L
++#define CRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS_MASK 0x00000010L
++#define CRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS_MASK 0x00000100L
++#define CRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR_MASK 0x00010000L
++#define CRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE_MASK 0x00100000L
++//CRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL
++#define CRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__SHIFT 0x0
++#define CRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS__SHIFT 0x4
++#define CRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS__SHIFT 0x8
++#define CRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__SHIFT 0x10
++#define CRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__SHIFT 0x14
++#define CRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_MASK 0x00000001L
++#define CRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS_MASK 0x00000010L
++#define CRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS_MASK 0x00000100L
++#define CRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_MASK 0x00010000L
++#define CRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_MASK 0x00100000L
++//CRTC0_CRTC_STATIC_SCREEN_CONTROL
++#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0
++#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10
++#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18
++#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19
++#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a
++#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b
++#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c
++#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e
++#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f
++#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL
++#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L
++#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x01000000L
++#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x02000000L
++#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x04000000L
++#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x08000000L
++#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000L
++#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L
++#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L
++//CRTC0_CRTC_3D_STRUCTURE_CONTROL
++#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0
++#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4
++#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8
++#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc
++#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10
++#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11
++#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12
++#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x00000001L
++#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x00000010L
++#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L
++#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L
++#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L
++#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L
++#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L
++//CRTC0_CRTC_GSL_VSYNC_GAP
++#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0
++#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8
++#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10
++#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11
++#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13
++#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14
++#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17
++#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18
++#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL
++#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L
++#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L
++#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x00060000L
++#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L
++#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L
++#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L
++#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xFF000000L
++//CRTC0_CRTC_GSL_WINDOW
++#define CRTC0_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0
++#define CRTC0_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10
++#define CRTC0_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x00003FFFL
++#define CRTC0_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x3FFF0000L
++//CRTC0_CRTC_GSL_CONTROL
++#define CRTC0_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0
++#define CRTC0_CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10
++#define CRTC0_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c
++#define CRTC0_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x00003FFFL
++#define CRTC0_CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x001F0000L
++#define CRTC0_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L
++//CRTC0_CRTC_RANGE_TIMING_INT_STATUS
++#define CRTC0_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0
++#define CRTC0_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4
++#define CRTC0_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8
++#define CRTC0_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc
++#define CRTC0_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10
++#define CRTC0_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L
++#define CRTC0_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L
++#define CRTC0_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L
++#define CRTC0_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L
++#define CRTC0_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L
++//CRTC0_CRTC_DRR_CONTROL
++#define CRTC0_CRTC_DRR_CONTROL__CRTC_XDMA_PREFETCH_DELAY__SHIFT 0x0
++#define CRTC0_CRTC_DRR_CONTROL__CRTC_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0xe
++#define CRTC0_CRTC_DRR_CONTROL__CRTC_SET_V_TOTAL_MIN_AUTO_DIS__SHIFT 0x1c
++#define CRTC0_CRTC_DRR_CONTROL__CRTC_DRR_MODE_DBUF_UPDATE_MODE__SHIFT 0x1d
++#define CRTC0_CRTC_DRR_CONTROL__CRTC_XDMA_PREFETCH_DELAY_MASK 0x00003FFFL
++#define CRTC0_CRTC_DRR_CONTROL__CRTC_V_TOTAL_LAST_USED_BY_DRR_MASK 0x0FFFC000L
++#define CRTC0_CRTC_DRR_CONTROL__CRTC_SET_V_TOTAL_MIN_AUTO_DIS_MASK 0x10000000L
++#define CRTC0_CRTC_DRR_CONTROL__CRTC_DRR_MODE_DBUF_UPDATE_MODE_MASK 0x60000000L
++
++
++// addressBlock: dce_dc_fmt0_dispdec
++//FMT0_FMT_CLAMP_COMPONENT_R
++#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0
++#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10
++#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL
++#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L
++//FMT0_FMT_CLAMP_COMPONENT_G
++#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0
++#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10
++#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL
++#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L
++//FMT0_FMT_CLAMP_COMPONENT_B
++#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0
++#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10
++#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL
++#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L
++//FMT0_FMT_DYNAMIC_EXP_CNTL
++#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0
++#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4
++#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L
++#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L
++//FMT0_FMT_CONTROL
++#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0
++#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT 0x4
++#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8
++#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc
++#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10
++#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12
++#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14
++#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15
++#define FMT0_FMT_CONTROL__FMT_SRC_SELECT__SHIFT 0x18
++#define FMT0_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED__SHIFT 0x1e
++#define FMT0_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_CLEAR__SHIFT 0x1f
++#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L
++#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK 0x00000010L
++#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L
++#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L
++#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L
++#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L
++#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L
++#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L
++#define FMT0_FMT_CONTROL__FMT_SRC_SELECT_MASK 0x07000000L
++#define FMT0_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_MASK 0x40000000L
++#define FMT0_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_CLEAR_MASK 0x80000000L
++//FMT0_FMT_BIT_DEPTH_CONTROL
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L
++//FMT0_FMT_DITHER_RAND_R_SEED
++#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0
++#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10
++#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL
++#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L
++//FMT0_FMT_DITHER_RAND_G_SEED
++#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0
++#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10
++#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL
++#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L
++//FMT0_FMT_DITHER_RAND_B_SEED
++#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0
++#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10
++#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL
++#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L
++//FMT0_FMT_CLAMP_CNTL
++#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0
++#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10
++#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L
++#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L
++//FMT0_FMT_CRC_CNTL
++#define FMT0_FMT_CRC_CNTL__FMT_CRC_EN__SHIFT 0x0
++#define FMT0_FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN__SHIFT 0x1
++#define FMT0_FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT 0x4
++#define FMT0_FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING__SHIFT 0x5
++#define FMT0_FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN__SHIFT 0x6
++#define FMT0_FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB__SHIFT 0x8
++#define FMT0_FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE__SHIFT 0x9
++#define FMT0_FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT 0xc
++#define FMT0_FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
++#define FMT0_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT 0x14
++#define FMT0_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT 0x18
++#define FMT0_FMT_CRC_CNTL__FMT_CRC_EN_MASK 0x00000001L
++#define FMT0_FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN_MASK 0x00000002L
++#define FMT0_FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK 0x00000010L
++#define FMT0_FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING_MASK 0x00000020L
++#define FMT0_FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN_MASK 0x00000040L
++#define FMT0_FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB_MASK 0x00000100L
++#define FMT0_FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE_MASK 0x00000200L
++#define FMT0_FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK 0x00003000L
++#define FMT0_FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
++#define FMT0_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK 0x00100000L
++#define FMT0_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK 0x01000000L
++//FMT0_FMT_CRC_SIG_RED_GREEN_MASK
++#define FMT0_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT 0x0
++#define FMT0_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT 0x10
++#define FMT0_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK 0x0000FFFFL
++#define FMT0_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L
++//FMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK
++#define FMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT 0x0
++#define FMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT 0x10
++#define FMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL
++#define FMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L
++//FMT0_FMT_CRC_SIG_RED_GREEN
++#define FMT0_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT 0x0
++#define FMT0_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT 0x10
++#define FMT0_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK 0x0000FFFFL
++#define FMT0_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK 0xFFFF0000L
++//FMT0_FMT_CRC_SIG_BLUE_CONTROL
++#define FMT0_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT 0x0
++#define FMT0_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT 0x10
++#define FMT0_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK 0x0000FFFFL
++#define FMT0_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK 0xFFFF0000L
++//FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL
++#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0
++#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL
++//FMT0_FMT_420_HBLANK_EARLY_START
++#define FMT0_FMT_420_HBLANK_EARLY_START__FMT_420_HBLANK_EARLY_START__SHIFT 0x0
++#define FMT0_FMT_420_HBLANK_EARLY_START__FMT_420_HBLANK_EARLY_START_MASK 0x00000FFFL
++
++
++// addressBlock: dce_dc_dcp1_dispdec
++//DCP1_GRPH_ENABLE
++#define DCP1_GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0
++#define DCP1_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL__SHIFT 0x1
++#define DCP1_GRPH_ENABLE__GRPH_ENABLE_MASK 0x00000001L
++#define DCP1_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL_MASK 0x00000002L
++//DCP1_GRPH_CONTROL
++#define DCP1_GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0
++#define DCP1_GRPH_CONTROL__GRPH_SE_ENABLE__SHIFT 0x2
++#define DCP1_GRPH_CONTROL__GRPH_Z__SHIFT 0x4
++#define DCP1_GRPH_CONTROL__GRPH_DIM_TYPE__SHIFT 0x6
++#define DCP1_GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8
++#define DCP1_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0xc
++#define DCP1_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10
++#define DCP1_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11
++#define DCP1_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES__SHIFT 0x12
++#define DCP1_GRPH_CONTROL__GRPH_SW_MODE__SHIFT 0x14
++#define DCP1_GRPH_CONTROL__GRPH_NUM_PIPES__SHIFT 0x1c
++#define DCP1_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f
++#define DCP1_GRPH_CONTROL__GRPH_DEPTH_MASK 0x00000003L
++#define DCP1_GRPH_CONTROL__GRPH_SE_ENABLE_MASK 0x00000004L
++#define DCP1_GRPH_CONTROL__GRPH_Z_MASK 0x00000030L
++#define DCP1_GRPH_CONTROL__GRPH_DIM_TYPE_MASK 0x000000C0L
++#define DCP1_GRPH_CONTROL__GRPH_FORMAT_MASK 0x00000700L
++#define DCP1_GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0x00007000L
++#define DCP1_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x00010000L
++#define DCP1_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x00020000L
++#define DCP1_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES_MASK 0x000C0000L
++#define DCP1_GRPH_CONTROL__GRPH_SW_MODE_MASK 0x01F00000L
++#define DCP1_GRPH_CONTROL__GRPH_NUM_PIPES_MASK 0x70000000L
++#define DCP1_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000L
++//DCP1_GRPH_LUT_10BIT_BYPASS
++#define DCP1_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT 0x8
++#define DCP1_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x10
++#define DCP1_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK 0x00000100L
++#define DCP1_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x00010000L
++//DCP1_GRPH_SWAP_CNTL
++#define DCP1_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0
++#define DCP1_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4
++#define DCP1_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6
++#define DCP1_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8
++#define DCP1_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT 0xa
++#define DCP1_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x00000003L
++#define DCP1_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x00000030L
++#define DCP1_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0x000000C0L
++#define DCP1_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x00000300L
++#define DCP1_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK 0x00000C00L
++//DCP1_GRPH_PRIMARY_SURFACE_ADDRESS
++#define DCP1_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT 0x0
++#define DCP1_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT 0x8
++#define DCP1_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK 0x00000001L
++#define DCP1_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
++//DCP1_GRPH_SECONDARY_SURFACE_ADDRESS
++#define DCP1_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT 0x0
++#define DCP1_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8
++#define DCP1_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK 0x00000001L
++#define DCP1_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
++//DCP1_GRPH_PITCH
++#define DCP1_GRPH_PITCH__GRPH_PITCH__SHIFT 0x0
++#define DCP1_GRPH_PITCH__GRPH_PITCH_MASK 0x00007FFFL
++//DCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
++#define DCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define DCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
++//DCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
++#define DCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define DCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
++//DCP1_GRPH_SURFACE_OFFSET_X
++#define DCP1_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT 0x0
++#define DCP1_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK 0x00003FFFL
++//DCP1_GRPH_SURFACE_OFFSET_Y
++#define DCP1_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT 0x0
++#define DCP1_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK 0x00003FFFL
++//DCP1_GRPH_X_START
++#define DCP1_GRPH_X_START__GRPH_X_START__SHIFT 0x0
++#define DCP1_GRPH_X_START__GRPH_X_START_MASK 0x00003FFFL
++//DCP1_GRPH_Y_START
++#define DCP1_GRPH_Y_START__GRPH_Y_START__SHIFT 0x0
++#define DCP1_GRPH_Y_START__GRPH_Y_START_MASK 0x00003FFFL
++//DCP1_GRPH_X_END
++#define DCP1_GRPH_X_END__GRPH_X_END__SHIFT 0x0
++#define DCP1_GRPH_X_END__GRPH_X_END_MASK 0x00007FFFL
++//DCP1_GRPH_Y_END
++#define DCP1_GRPH_Y_END__GRPH_Y_END__SHIFT 0x0
++#define DCP1_GRPH_Y_END__GRPH_Y_END_MASK 0x00007FFFL
++//DCP1_INPUT_GAMMA_CONTROL
++#define DCP1_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x0
++#define DCP1_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK 0x00000001L
++//DCP1_GRPH_UPDATE
++#define DCP1_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0
++#define DCP1_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1
++#define DCP1_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2
++#define DCP1_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3
++#define DCP1_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR__SHIFT 0x8
++#define DCP1_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE__SHIFT 0x9
++#define DCP1_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE__SHIFT 0xa
++#define DCP1_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10
++#define DCP1_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14
++#define DCP1_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
++#define DCP1_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c
++#define DCP1_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x00000001L
++#define DCP1_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x00000002L
++#define DCP1_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x00000004L
++#define DCP1_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x00000008L
++#define DCP1_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR_MASK 0x00000100L
++#define DCP1_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE_MASK 0x00000200L
++#define DCP1_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE_MASK 0x00000400L
++#define DCP1_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x00010000L
++#define DCP1_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x00100000L
++#define DCP1_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
++#define DCP1_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000L
++//DCP1_GRPH_FLIP_CONTROL
++#define DCP1_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT 0x0
++#define DCP1_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN__SHIFT 0x1
++#define DCP1_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN__SHIFT 0x4
++#define DCP1_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT 0x5
++#define DCP1_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK 0x00000001L
++#define DCP1_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN_MASK 0x00000002L
++#define DCP1_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN_MASK 0x00000010L
++#define DCP1_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK 0x00000020L
++//DCP1_GRPH_SURFACE_ADDRESS_INUSE
++#define DCP1_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT 0x8
++#define DCP1_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK 0xFFFFFF00L
++//DCP1_GRPH_DFQ_CONTROL
++#define DCP1_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x0
++#define DCP1_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x4
++#define DCP1_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8
++#define DCP1_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x00000001L
++#define DCP1_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x00000070L
++#define DCP1_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x00000700L
++//DCP1_GRPH_DFQ_STATUS
++#define DCP1_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x0
++#define DCP1_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4
++#define DCP1_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x8
++#define DCP1_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x9
++#define DCP1_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0x0000000FL
++#define DCP1_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0x000000F0L
++#define DCP1_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x00000100L
++#define DCP1_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x00000200L
++//DCP1_GRPH_INTERRUPT_STATUS
++#define DCP1_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0
++#define DCP1_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8
++#define DCP1_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x00000001L
++#define DCP1_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x00000100L
++//DCP1_GRPH_INTERRUPT_CONTROL
++#define DCP1_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0
++#define DCP1_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8
++#define DCP1_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x00000001L
++#define DCP1_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x00000100L
++//DCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE
++#define DCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0
++#define DCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK 0x000000FFL
++//DCP1_GRPH_COMPRESS_SURFACE_ADDRESS
++#define DCP1_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT 0x8
++#define DCP1_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK 0xFFFFFF00L
++//DCP1_GRPH_COMPRESS_PITCH
++#define DCP1_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT 0x6
++#define DCP1_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK 0x0001FFC0L
++//DCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH
++#define DCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define DCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
++//DCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT
++#define DCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__SHIFT 0x0
++#define DCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_MASK 0x000000FFL
++//DCP1_PRESCALE_GRPH_CONTROL
++#define DCP1_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT 0x0
++#define DCP1_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT 0x1
++#define DCP1_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x2
++#define DCP1_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT 0x3
++#define DCP1_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT 0x4
++#define DCP1_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK 0x00000001L
++#define DCP1_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x00000002L
++#define DCP1_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK 0x00000004L
++#define DCP1_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK 0x00000008L
++#define DCP1_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK 0x00000010L
++//DCP1_PRESCALE_VALUES_GRPH_R
++#define DCP1_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT 0x0
++#define DCP1_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT 0x10
++#define DCP1_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK 0x0000FFFFL
++#define DCP1_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK 0xFFFF0000L
++//DCP1_PRESCALE_VALUES_GRPH_G
++#define DCP1_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT 0x0
++#define DCP1_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT 0x10
++#define DCP1_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK 0x0000FFFFL
++#define DCP1_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK 0xFFFF0000L
++//DCP1_PRESCALE_VALUES_GRPH_B
++#define DCP1_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT 0x0
++#define DCP1_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT 0x10
++#define DCP1_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK 0x0000FFFFL
++#define DCP1_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK 0xFFFF0000L
++//DCP1_INPUT_CSC_CONTROL
++#define DCP1_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT 0x0
++#define DCP1_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK 0x00000003L
++//DCP1_INPUT_CSC_C11_C12
++#define DCP1_INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT 0x0
++#define DCP1_INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT 0x10
++#define DCP1_INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK 0x0000FFFFL
++#define DCP1_INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK 0xFFFF0000L
++//DCP1_INPUT_CSC_C13_C14
++#define DCP1_INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT 0x0
++#define DCP1_INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT 0x10
++#define DCP1_INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK 0x0000FFFFL
++#define DCP1_INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK 0xFFFF0000L
++//DCP1_INPUT_CSC_C21_C22
++#define DCP1_INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT 0x0
++#define DCP1_INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT 0x10
++#define DCP1_INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK 0x0000FFFFL
++#define DCP1_INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK 0xFFFF0000L
++//DCP1_INPUT_CSC_C23_C24
++#define DCP1_INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT 0x0
++#define DCP1_INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT 0x10
++#define DCP1_INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK 0x0000FFFFL
++#define DCP1_INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK 0xFFFF0000L
++//DCP1_INPUT_CSC_C31_C32
++#define DCP1_INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT 0x0
++#define DCP1_INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT 0x10
++#define DCP1_INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK 0x0000FFFFL
++#define DCP1_INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK 0xFFFF0000L
++//DCP1_INPUT_CSC_C33_C34
++#define DCP1_INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT 0x0
++#define DCP1_INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT 0x10
++#define DCP1_INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK 0x0000FFFFL
++#define DCP1_INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK 0xFFFF0000L
++//DCP1_OUTPUT_CSC_CONTROL
++#define DCP1_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT 0x0
++#define DCP1_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK 0x00000007L
++//DCP1_OUTPUT_CSC_C11_C12
++#define DCP1_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT 0x0
++#define DCP1_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT 0x10
++#define DCP1_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK 0x0000FFFFL
++#define DCP1_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK 0xFFFF0000L
++//DCP1_OUTPUT_CSC_C13_C14
++#define DCP1_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT 0x0
++#define DCP1_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT 0x10
++#define DCP1_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK 0x0000FFFFL
++#define DCP1_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK 0xFFFF0000L
++//DCP1_OUTPUT_CSC_C21_C22
++#define DCP1_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT 0x0
++#define DCP1_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT 0x10
++#define DCP1_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK 0x0000FFFFL
++#define DCP1_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK 0xFFFF0000L
++//DCP1_OUTPUT_CSC_C23_C24
++#define DCP1_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT 0x0
++#define DCP1_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT 0x10
++#define DCP1_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK 0x0000FFFFL
++#define DCP1_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK 0xFFFF0000L
++//DCP1_OUTPUT_CSC_C31_C32
++#define DCP1_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT 0x0
++#define DCP1_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT 0x10
++#define DCP1_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK 0x0000FFFFL
++#define DCP1_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK 0xFFFF0000L
++//DCP1_OUTPUT_CSC_C33_C34
++#define DCP1_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT 0x0
++#define DCP1_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT 0x10
++#define DCP1_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK 0x0000FFFFL
++#define DCP1_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK 0xFFFF0000L
++//DCP1_COMM_MATRIXA_TRANS_C11_C12
++#define DCP1_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT 0x0
++#define DCP1_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT 0x10
++#define DCP1_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK 0x0000FFFFL
++#define DCP1_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK 0xFFFF0000L
++//DCP1_COMM_MATRIXA_TRANS_C13_C14
++#define DCP1_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT 0x0
++#define DCP1_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT 0x10
++#define DCP1_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK 0x0000FFFFL
++#define DCP1_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK 0xFFFF0000L
++//DCP1_COMM_MATRIXA_TRANS_C21_C22
++#define DCP1_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT 0x0
++#define DCP1_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT 0x10
++#define DCP1_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK 0x0000FFFFL
++#define DCP1_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK 0xFFFF0000L
++//DCP1_COMM_MATRIXA_TRANS_C23_C24
++#define DCP1_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT 0x0
++#define DCP1_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT 0x10
++#define DCP1_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK 0x0000FFFFL
++#define DCP1_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK 0xFFFF0000L
++//DCP1_COMM_MATRIXA_TRANS_C31_C32
++#define DCP1_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT 0x0
++#define DCP1_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT 0x10
++#define DCP1_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK 0x0000FFFFL
++#define DCP1_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK 0xFFFF0000L
++//DCP1_COMM_MATRIXA_TRANS_C33_C34
++#define DCP1_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT 0x0
++#define DCP1_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT 0x10
++#define DCP1_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK 0x0000FFFFL
++#define DCP1_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK 0xFFFF0000L
++//DCP1_COMM_MATRIXB_TRANS_C11_C12
++#define DCP1_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT 0x0
++#define DCP1_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT 0x10
++#define DCP1_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK 0x0000FFFFL
++#define DCP1_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK 0xFFFF0000L
++//DCP1_COMM_MATRIXB_TRANS_C13_C14
++#define DCP1_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT 0x0
++#define DCP1_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT 0x10
++#define DCP1_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK 0x0000FFFFL
++#define DCP1_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK 0xFFFF0000L
++//DCP1_COMM_MATRIXB_TRANS_C21_C22
++#define DCP1_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT 0x0
++#define DCP1_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT 0x10
++#define DCP1_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK 0x0000FFFFL
++#define DCP1_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK 0xFFFF0000L
++//DCP1_COMM_MATRIXB_TRANS_C23_C24
++#define DCP1_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT 0x0
++#define DCP1_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT 0x10
++#define DCP1_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK 0x0000FFFFL
++#define DCP1_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK 0xFFFF0000L
++//DCP1_COMM_MATRIXB_TRANS_C31_C32
++#define DCP1_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT 0x0
++#define DCP1_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT 0x10
++#define DCP1_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK 0x0000FFFFL
++#define DCP1_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK 0xFFFF0000L
++//DCP1_COMM_MATRIXB_TRANS_C33_C34
++#define DCP1_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT 0x0
++#define DCP1_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT 0x10
++#define DCP1_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK 0x0000FFFFL
++#define DCP1_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK 0xFFFF0000L
++//DCP1_DENORM_CONTROL
++#define DCP1_DENORM_CONTROL__DENORM_MODE__SHIFT 0x0
++#define DCP1_DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT 0x4
++#define DCP1_DENORM_CONTROL__DENORM_MODE_MASK 0x00000007L
++#define DCP1_DENORM_CONTROL__DENORM_14BIT_OUT_MASK 0x00000010L
++//DCP1_OUT_ROUND_CONTROL
++#define DCP1_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT 0x0
++#define DCP1_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK 0x0000000FL
++//DCP1_OUT_CLAMP_CONTROL_R_CR
++#define DCP1_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT 0x0
++#define DCP1_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT 0x10
++#define DCP1_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK 0x00003FFFL
++#define DCP1_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK 0x3FFF0000L
++//DCP1_OUT_CLAMP_CONTROL_G_Y
++#define DCP1_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT 0x0
++#define DCP1_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT 0x10
++#define DCP1_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK 0x00003FFFL
++#define DCP1_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK 0x3FFF0000L
++//DCP1_OUT_CLAMP_CONTROL_B_CB
++#define DCP1_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT 0x0
++#define DCP1_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT 0x10
++#define DCP1_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK 0x00003FFFL
++#define DCP1_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK 0x3FFF0000L
++//DCP1_KEY_CONTROL
++#define DCP1_KEY_CONTROL__KEY_MODE__SHIFT 0x1
++#define DCP1_KEY_CONTROL__KEY_MODE_MASK 0x00000006L
++//DCP1_KEY_RANGE_ALPHA
++#define DCP1_KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT 0x0
++#define DCP1_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT 0x10
++#define DCP1_KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK 0x0000FFFFL
++#define DCP1_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK 0xFFFF0000L
++//DCP1_KEY_RANGE_RED
++#define DCP1_KEY_RANGE_RED__KEY_RED_LOW__SHIFT 0x0
++#define DCP1_KEY_RANGE_RED__KEY_RED_HIGH__SHIFT 0x10
++#define DCP1_KEY_RANGE_RED__KEY_RED_LOW_MASK 0x0000FFFFL
++#define DCP1_KEY_RANGE_RED__KEY_RED_HIGH_MASK 0xFFFF0000L
++//DCP1_KEY_RANGE_GREEN
++#define DCP1_KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT 0x0
++#define DCP1_KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT 0x10
++#define DCP1_KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK 0x0000FFFFL
++#define DCP1_KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK 0xFFFF0000L
++//DCP1_KEY_RANGE_BLUE
++#define DCP1_KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT 0x0
++#define DCP1_KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT 0x10
++#define DCP1_KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK 0x0000FFFFL
++#define DCP1_KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK 0xFFFF0000L
++//DCP1_DEGAMMA_CONTROL
++#define DCP1_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x0
++#define DCP1_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT 0x8
++#define DCP1_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0xc
++#define DCP1_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x00000003L
++#define DCP1_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK 0x00000300L
++#define DCP1_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK 0x00003000L
++//DCP1_GAMUT_REMAP_CONTROL
++#define DCP1_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT 0x0
++#define DCP1_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK 0x00000003L
++//DCP1_GAMUT_REMAP_C11_C12
++#define DCP1_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT 0x0
++#define DCP1_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT 0x10
++#define DCP1_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK 0x0000FFFFL
++#define DCP1_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK 0xFFFF0000L
++//DCP1_GAMUT_REMAP_C13_C14
++#define DCP1_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT 0x0
++#define DCP1_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT 0x10
++#define DCP1_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK 0x0000FFFFL
++#define DCP1_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK 0xFFFF0000L
++//DCP1_GAMUT_REMAP_C21_C22
++#define DCP1_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT 0x0
++#define DCP1_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT 0x10
++#define DCP1_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK 0x0000FFFFL
++#define DCP1_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK 0xFFFF0000L
++//DCP1_GAMUT_REMAP_C23_C24
++#define DCP1_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT 0x0
++#define DCP1_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT 0x10
++#define DCP1_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK 0x0000FFFFL
++#define DCP1_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK 0xFFFF0000L
++//DCP1_GAMUT_REMAP_C31_C32
++#define DCP1_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT 0x0
++#define DCP1_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT 0x10
++#define DCP1_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK 0x0000FFFFL
++#define DCP1_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK 0xFFFF0000L
++//DCP1_GAMUT_REMAP_C33_C34
++#define DCP1_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT 0x0
++#define DCP1_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT 0x10
++#define DCP1_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK 0x0000FFFFL
++#define DCP1_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK 0xFFFF0000L
++//DCP1_DCP_SPATIAL_DITHER_CNTL
++#define DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT 0x0
++#define DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT 0x4
++#define DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT 0x6
++#define DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT 0x8
++#define DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT 0x9
++#define DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT 0xa
++#define DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK 0x00000001L
++#define DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK 0x00000030L
++#define DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK 0x000000C0L
++#define DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK 0x00000100L
++#define DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK 0x00000200L
++#define DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK 0x00000400L
++//DCP1_DCP_RANDOM_SEEDS
++#define DCP1_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT 0x0
++#define DCP1_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT 0x8
++#define DCP1_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT 0x10
++#define DCP1_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK 0x000000FFL
++#define DCP1_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK 0x0000FF00L
++#define DCP1_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK 0x00FF0000L
++//DCP1_DCP_FP_CONVERTED_FIELD
++#define DCP1_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT 0x0
++#define DCP1_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14
++#define DCP1_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK 0x0003FFFFL
++#define DCP1_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK 0x07F00000L
++//DCP1_CUR_CONTROL
++#define DCP1_CUR_CONTROL__CURSOR_EN__SHIFT 0x0
++#define DCP1_CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT 0x4
++#define DCP1_CUR_CONTROL__CURSOR_MODE__SHIFT 0x8
++#define DCP1_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM__SHIFT 0xb
++#define DCP1_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION__SHIFT 0xc
++#define DCP1_CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x10
++#define DCP1_CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT 0x14
++#define DCP1_CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT 0x18
++#define DCP1_CUR_CONTROL__CURSOR_EN_MASK 0x00000001L
++#define DCP1_CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK 0x00000010L
++#define DCP1_CUR_CONTROL__CURSOR_MODE_MASK 0x00000300L
++#define DCP1_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM_MASK 0x00000800L
++#define DCP1_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION_MASK 0x0000F000L
++#define DCP1_CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00010000L
++#define DCP1_CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK 0x00100000L
++#define DCP1_CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK 0x07000000L
++//DCP1_CUR_SURFACE_ADDRESS
++#define DCP1_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0
++#define DCP1_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
++//DCP1_CUR_SIZE
++#define DCP1_CUR_SIZE__CURSOR_HEIGHT__SHIFT 0x0
++#define DCP1_CUR_SIZE__CURSOR_WIDTH__SHIFT 0x10
++#define DCP1_CUR_SIZE__CURSOR_HEIGHT_MASK 0x0000007FL
++#define DCP1_CUR_SIZE__CURSOR_WIDTH_MASK 0x007F0000L
++//DCP1_CUR_SURFACE_ADDRESS_HIGH
++#define DCP1_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define DCP1_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
++//DCP1_CUR_POSITION
++#define DCP1_CUR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0
++#define DCP1_CUR_POSITION__CURSOR_X_POSITION__SHIFT 0x10
++#define DCP1_CUR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL
++#define DCP1_CUR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L
++//DCP1_CUR_HOT_SPOT
++#define DCP1_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0
++#define DCP1_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10
++#define DCP1_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x0000007FL
++#define DCP1_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x007F0000L
++//DCP1_CUR_COLOR1
++#define DCP1_CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT 0x0
++#define DCP1_CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT 0x8
++#define DCP1_CUR_COLOR1__CUR_COLOR1_RED__SHIFT 0x10
++#define DCP1_CUR_COLOR1__CUR_COLOR1_BLUE_MASK 0x000000FFL
++#define DCP1_CUR_COLOR1__CUR_COLOR1_GREEN_MASK 0x0000FF00L
++#define DCP1_CUR_COLOR1__CUR_COLOR1_RED_MASK 0x00FF0000L
++//DCP1_CUR_COLOR2
++#define DCP1_CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT 0x0
++#define DCP1_CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT 0x8
++#define DCP1_CUR_COLOR2__CUR_COLOR2_RED__SHIFT 0x10
++#define DCP1_CUR_COLOR2__CUR_COLOR2_BLUE_MASK 0x000000FFL
++#define DCP1_CUR_COLOR2__CUR_COLOR2_GREEN_MASK 0x0000FF00L
++#define DCP1_CUR_COLOR2__CUR_COLOR2_RED_MASK 0x00FF0000L
++//DCP1_CUR_UPDATE
++#define DCP1_CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT 0x0
++#define DCP1_CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT 0x1
++#define DCP1_CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT 0x10
++#define DCP1_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
++#define DCP1_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE__SHIFT 0x19
++#define DCP1_CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK 0x00000001L
++#define DCP1_CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x00000002L
++#define DCP1_CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK 0x00010000L
++#define DCP1_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
++#define DCP1_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE_MASK 0x06000000L
++//DCP1_CUR_REQUEST_FILTER_CNTL
++#define DCP1_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT 0x0
++#define DCP1_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK 0x00000001L
++//DCP1_CUR_STEREO_CONTROL
++#define DCP1_CUR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0
++#define DCP1_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4
++#define DCP1_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x10
++#define DCP1_CUR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L
++#define DCP1_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x00003FF0L
++#define DCP1_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0x03FF0000L
++//DCP1_DC_LUT_RW_MODE
++#define DCP1_DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT 0x0
++#define DCP1_DC_LUT_RW_MODE__DC_LUT_ERROR__SHIFT 0x10
++#define DCP1_DC_LUT_RW_MODE__DC_LUT_ERROR_RST__SHIFT 0x11
++#define DCP1_DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK 0x00000001L
++#define DCP1_DC_LUT_RW_MODE__DC_LUT_ERROR_MASK 0x00010000L
++#define DCP1_DC_LUT_RW_MODE__DC_LUT_ERROR_RST_MASK 0x00020000L
++//DCP1_DC_LUT_RW_INDEX
++#define DCP1_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT 0x0
++#define DCP1_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK 0x000000FFL
++//DCP1_DC_LUT_SEQ_COLOR
++#define DCP1_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT 0x0
++#define DCP1_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK 0x0000FFFFL
++//DCP1_DC_LUT_PWL_DATA
++#define DCP1_DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT 0x0
++#define DCP1_DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT 0x10
++#define DCP1_DC_LUT_PWL_DATA__DC_LUT_BASE_MASK 0x0000FFFFL
++#define DCP1_DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK 0xFFFF0000L
++//DCP1_DC_LUT_30_COLOR
++#define DCP1_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT 0x0
++#define DCP1_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT 0xa
++#define DCP1_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT 0x14
++#define DCP1_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK 0x000003FFL
++#define DCP1_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK 0x000FFC00L
++#define DCP1_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK 0x3FF00000L
++//DCP1_DC_LUT_VGA_ACCESS_ENABLE
++#define DCP1_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT 0x0
++#define DCP1_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK 0x00000001L
++//DCP1_DC_LUT_WRITE_EN_MASK
++#define DCP1_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT 0x0
++#define DCP1_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK 0x00000007L
++//DCP1_DC_LUT_AUTOFILL
++#define DCP1_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT 0x0
++#define DCP1_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT 0x1
++#define DCP1_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK 0x00000001L
++#define DCP1_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x00000002L
++//DCP1_DC_LUT_CONTROL
++#define DCP1_DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT 0x0
++#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT 0x4
++#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT 0x5
++#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT 0x6
++#define DCP1_DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT 0x8
++#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT 0xc
++#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT 0xd
++#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT 0xe
++#define DCP1_DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT 0x10
++#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT 0x14
++#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT 0x15
++#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT 0x16
++#define DCP1_DC_LUT_CONTROL__DC_LUT_INC_B_MASK 0x0000000FL
++#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK 0x00000010L
++#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK 0x00000020L
++#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK 0x000000C0L
++#define DCP1_DC_LUT_CONTROL__DC_LUT_INC_G_MASK 0x00000F00L
++#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK 0x00001000L
++#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK 0x00002000L
++#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK 0x0000C000L
++#define DCP1_DC_LUT_CONTROL__DC_LUT_INC_R_MASK 0x000F0000L
++#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK 0x00100000L
++#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK 0x00200000L
++#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK 0x00C00000L
++//DCP1_DC_LUT_BLACK_OFFSET_BLUE
++#define DCP1_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0
++#define DCP1_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK 0x0000FFFFL
++//DCP1_DC_LUT_BLACK_OFFSET_GREEN
++#define DCP1_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0
++#define DCP1_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK 0x0000FFFFL
++//DCP1_DC_LUT_BLACK_OFFSET_RED
++#define DCP1_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT 0x0
++#define DCP1_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK 0x0000FFFFL
++//DCP1_DC_LUT_WHITE_OFFSET_BLUE
++#define DCP1_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT 0x0
++#define DCP1_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK 0x0000FFFFL
++//DCP1_DC_LUT_WHITE_OFFSET_GREEN
++#define DCP1_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT 0x0
++#define DCP1_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK 0x0000FFFFL
++//DCP1_DC_LUT_WHITE_OFFSET_RED
++#define DCP1_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT 0x0
++#define DCP1_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK 0x0000FFFFL
++//DCP1_DCP_CRC_CONTROL
++#define DCP1_DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT 0x0
++#define DCP1_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x2
++#define DCP1_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT 0x8
++#define DCP1_DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK 0x00000001L
++#define DCP1_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK 0x0000001CL
++#define DCP1_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK 0x00000300L
++//DCP1_DCP_CRC_MASK
++#define DCP1_DCP_CRC_MASK__DCP_CRC_MASK__SHIFT 0x0
++#define DCP1_DCP_CRC_MASK__DCP_CRC_MASK_MASK 0xFFFFFFFFL
++//DCP1_DCP_CRC_CURRENT
++#define DCP1_DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT 0x0
++#define DCP1_DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK 0xFFFFFFFFL
++//DCP1_DVMM_PTE_CONTROL
++#define DCP1_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT 0x0
++#define DCP1_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT 0x1
++#define DCP1_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT 0x5
++#define DCP1_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT 0x9
++#define DCP1_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT 0x14
++#define DCP1_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT 0x15
++#define DCP1_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK 0x00000001L
++#define DCP1_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK 0x0000001EL
++#define DCP1_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK 0x000001E0L
++#define DCP1_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK 0x0007FE00L
++#define DCP1_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK 0x00100000L
++#define DCP1_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK 0x00200000L
++//DCP1_DCP_CRC_LAST
++#define DCP1_DCP_CRC_LAST__DCP_CRC_LAST__SHIFT 0x0
++#define DCP1_DCP_CRC_LAST__DCP_CRC_LAST_MASK 0xFFFFFFFFL
++//DCP1_DVMM_PTE_ARB_CONTROL
++#define DCP1_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT 0x0
++#define DCP1_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT 0x8
++#define DCP1_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK 0x0000003FL
++#define DCP1_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK 0x0000FF00L
++//DCP1_GRPH_FLIP_RATE_CNTL
++#define DCP1_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT 0x0
++#define DCP1_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT 0x3
++#define DCP1_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK 0x00000007L
++#define DCP1_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK 0x00000008L
++//DCP1_DCP_GSL_CONTROL
++#define DCP1_DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT 0x0
++#define DCP1_DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT 0x1
++#define DCP1_DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x2
++#define DCP1_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT 0x4
++#define DCP1_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT 0x14
++#define DCP1_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP__SHIFT 0x15
++#define DCP1_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN__SHIFT 0x17
++#define DCP1_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT 0x18
++#define DCP1_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC__SHIFT 0x1a
++#define DCP1_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT 0x1b
++#define DCP1_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT 0x1c
++#define DCP1_DCP_GSL_CONTROL__DCP_GSL0_EN_MASK 0x00000001L
++#define DCP1_DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x00000002L
++#define DCP1_DCP_GSL_CONTROL__DCP_GSL2_EN_MASK 0x00000004L
++#define DCP1_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK 0x000FFFF0L
++#define DCP1_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK 0x00100000L
++#define DCP1_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_MASK 0x00600000L
++#define DCP1_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_MASK 0x00800000L
++#define DCP1_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK 0x03000000L
++#define DCP1_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_MASK 0x04000000L
++#define DCP1_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK 0x08000000L
++#define DCP1_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK 0xF0000000L
++//DCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK
++#define DCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT 0x0
++#define DCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT 0x4
++#define DCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK 0x0000000FL
++#define DCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK 0x000001F0L
++//DCP1_GRPH_STEREOSYNC_FLIP
++#define DCP1_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0
++#define DCP1_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x8
++#define DCP1_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10
++#define DCP1_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11
++#define DCP1_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c
++#define DCP1_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x00000001L
++#define DCP1_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x00000300L
++#define DCP1_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x00010000L
++#define DCP1_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x00020000L
++#define DCP1_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000L
++//DCP1_HW_ROTATION
++#define DCP1_HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT 0x0
++#define DCP1_HW_ROTATION__GRPH_ROTATION_ANGLE_MASK 0x00000007L
++//DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL
++#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT 0x0
++#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT 0x1
++#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT 0x4
++#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK 0x00000001L
++#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK 0x00000002L
++#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK 0x0001FFF0L
++//DCP1_REGAMMA_CONTROL
++#define DCP1_REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT 0x0
++#define DCP1_REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK 0x00000007L
++//DCP1_REGAMMA_LUT_INDEX
++#define DCP1_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x0
++#define DCP1_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK 0x000001FFL
++//DCP1_REGAMMA_LUT_DATA
++#define DCP1_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT 0x0
++#define DCP1_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK 0x0007FFFFL
++//DCP1_REGAMMA_LUT_WRITE_EN_MASK
++#define DCP1_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x0
++#define DCP1_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x00000007L
++//DCP1_REGAMMA_CNTLA_START_CNTL
++#define DCP1_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x0
++#define DCP1_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14
++#define DCP1_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK 0x0003FFFFL
++#define DCP1_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
++//DCP1_REGAMMA_CNTLA_SLOPE_CNTL
++#define DCP1_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
++#define DCP1_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
++//DCP1_REGAMMA_CNTLA_END_CNTL1
++#define DCP1_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x0
++#define DCP1_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK 0x0000FFFFL
++//DCP1_REGAMMA_CNTLA_END_CNTL2
++#define DCP1_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0
++#define DCP1_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10
++#define DCP1_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
++#define DCP1_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xFFFF0000L
++//DCP1_REGAMMA_CNTLA_REGION_0_1
++#define DCP1_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
++#define DCP1_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
++#define DCP1_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
++#define DCP1_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP1_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
++#define DCP1_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP1_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP1_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
++//DCP1_REGAMMA_CNTLA_REGION_2_3
++#define DCP1_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
++#define DCP1_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
++#define DCP1_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
++#define DCP1_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP1_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
++#define DCP1_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP1_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP1_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
++//DCP1_REGAMMA_CNTLA_REGION_4_5
++#define DCP1_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
++#define DCP1_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
++#define DCP1_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
++#define DCP1_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP1_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
++#define DCP1_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP1_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP1_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
++//DCP1_REGAMMA_CNTLA_REGION_6_7
++#define DCP1_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
++#define DCP1_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
++#define DCP1_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
++#define DCP1_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP1_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
++#define DCP1_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP1_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP1_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
++//DCP1_REGAMMA_CNTLA_REGION_8_9
++#define DCP1_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
++#define DCP1_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
++#define DCP1_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
++#define DCP1_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP1_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
++#define DCP1_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP1_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP1_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
++//DCP1_REGAMMA_CNTLA_REGION_10_11
++#define DCP1_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
++#define DCP1_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
++#define DCP1_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
++#define DCP1_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP1_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
++#define DCP1_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP1_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP1_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
++//DCP1_REGAMMA_CNTLA_REGION_12_13
++#define DCP1_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
++#define DCP1_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
++#define DCP1_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
++#define DCP1_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP1_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
++#define DCP1_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP1_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP1_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
++//DCP1_REGAMMA_CNTLA_REGION_14_15
++#define DCP1_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
++#define DCP1_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
++#define DCP1_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
++#define DCP1_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP1_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
++#define DCP1_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP1_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP1_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
++//DCP1_REGAMMA_CNTLB_START_CNTL
++#define DCP1_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x0
++#define DCP1_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14
++#define DCP1_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK 0x0003FFFFL
++#define DCP1_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
++//DCP1_REGAMMA_CNTLB_SLOPE_CNTL
++#define DCP1_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
++#define DCP1_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
++//DCP1_REGAMMA_CNTLB_END_CNTL1
++#define DCP1_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x0
++#define DCP1_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK 0x0000FFFFL
++//DCP1_REGAMMA_CNTLB_END_CNTL2
++#define DCP1_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0
++#define DCP1_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10
++#define DCP1_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
++#define DCP1_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xFFFF0000L
++//DCP1_REGAMMA_CNTLB_REGION_0_1
++#define DCP1_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
++#define DCP1_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
++#define DCP1_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
++#define DCP1_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP1_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
++#define DCP1_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP1_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP1_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
++//DCP1_REGAMMA_CNTLB_REGION_2_3
++#define DCP1_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
++#define DCP1_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
++#define DCP1_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
++#define DCP1_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP1_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
++#define DCP1_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP1_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP1_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
++//DCP1_REGAMMA_CNTLB_REGION_4_5
++#define DCP1_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
++#define DCP1_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
++#define DCP1_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
++#define DCP1_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP1_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
++#define DCP1_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP1_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP1_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
++//DCP1_REGAMMA_CNTLB_REGION_6_7
++#define DCP1_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
++#define DCP1_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
++#define DCP1_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
++#define DCP1_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP1_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
++#define DCP1_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP1_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP1_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
++//DCP1_REGAMMA_CNTLB_REGION_8_9
++#define DCP1_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
++#define DCP1_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
++#define DCP1_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
++#define DCP1_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP1_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
++#define DCP1_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP1_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP1_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
++//DCP1_REGAMMA_CNTLB_REGION_10_11
++#define DCP1_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
++#define DCP1_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
++#define DCP1_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
++#define DCP1_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP1_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
++#define DCP1_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP1_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP1_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
++//DCP1_REGAMMA_CNTLB_REGION_12_13
++#define DCP1_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
++#define DCP1_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
++#define DCP1_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
++#define DCP1_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP1_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
++#define DCP1_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP1_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP1_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
++//DCP1_REGAMMA_CNTLB_REGION_14_15
++#define DCP1_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
++#define DCP1_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
++#define DCP1_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
++#define DCP1_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP1_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
++#define DCP1_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP1_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP1_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
++//DCP1_ALPHA_CONTROL
++#define DCP1_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT 0x0
++#define DCP1_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT 0x1
++#define DCP1_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK 0x00000001L
++#define DCP1_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK 0x00000002L
++//DCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS
++#define DCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT 0x8
++#define DCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
++//DCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH
++#define DCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define DCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
++//DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS
++#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT 0x0
++#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT 0x18
++#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT 0x19
++#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT 0x1a
++#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT 0x1c
++#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT 0x1d
++#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT 0x1e
++#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK 0x000FFFFFL
++#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK 0x01000000L
++#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK 0x02000000L
++#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK 0x04000000L
++#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK 0x10000000L
++#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK 0x20000000L
++#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK 0x40000000L
++//DCP1_GRPH_XDMA_FLIP_TIMEOUT
++#define DCP1_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS__SHIFT 0x0
++#define DCP1_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK__SHIFT 0x1
++#define DCP1_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK__SHIFT 0x2
++#define DCP1_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS_MASK 0x00000001L
++#define DCP1_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK_MASK 0x00000002L
++#define DCP1_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK_MASK 0x00000004L
++//DCP1_GRPH_XDMA_FLIP_AVG_DELAY
++#define DCP1_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY__SHIFT 0x0
++#define DCP1_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD__SHIFT 0x10
++#define DCP1_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY_MASK 0x0000FFFFL
++#define DCP1_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD_MASK 0x00FF0000L
++//DCP1_GRPH_SURFACE_COUNTER_CONTROL
++#define DCP1_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN__SHIFT 0x0
++#define DCP1_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT__SHIFT 0x1
++#define DCP1_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED__SHIFT 0x9
++#define DCP1_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN_MASK 0x00000001L
++#define DCP1_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT_MASK 0x0000001EL
++#define DCP1_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_MASK 0x00000200L
++//DCP1_GRPH_SURFACE_COUNTER_OUTPUT
++#define DCP1_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN__SHIFT 0x0
++#define DCP1_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX__SHIFT 0x10
++#define DCP1_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN_MASK 0x0000FFFFL
++#define DCP1_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX_MASK 0xFFFF0000L
++
++
++// addressBlock: dce_dc_lb1_dispdec
++//LB1_LB_DATA_FORMAT
++#define LB1_LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0
++#define LB1_LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2
++#define LB1_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3
++#define LB1_LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4
++#define LB1_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5
++#define LB1_LB_DATA_FORMAT__PREFILL_EN__SHIFT 0x8
++#define LB1_LB_DATA_FORMAT__PREFETCH__SHIFT 0xc
++#define LB1_LB_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18
++#define LB1_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f
++#define LB1_LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x00000003L
++#define LB1_LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x00000004L
++#define LB1_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000008L
++#define LB1_LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x00000010L
++#define LB1_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x00000020L
++#define LB1_LB_DATA_FORMAT__PREFILL_EN_MASK 0x00000100L
++#define LB1_LB_DATA_FORMAT__PREFETCH_MASK 0x00001000L
++#define LB1_LB_DATA_FORMAT__REQUEST_MODE_MASK 0x01000000L
++#define LB1_LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000L
++//LB1_LB_MEMORY_CTRL
++#define LB1_LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0
++#define LB1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
++#define LB1_LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14
++#define LB1_LB_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0x00001FFFL
++#define LB1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x000F0000L
++#define LB1_LB_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x00300000L
++//LB1_LB_MEMORY_SIZE_STATUS
++#define LB1_LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0
++#define LB1_LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0x00001FFFL
++//LB1_LB_DESKTOP_HEIGHT
++#define LB1_LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0
++#define LB1_LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x00007FFFL
++//LB1_LB_VLINE_START_END
++#define LB1_LB_VLINE_START_END__VLINE_START__SHIFT 0x0
++#define LB1_LB_VLINE_START_END__VLINE_END__SHIFT 0x10
++#define LB1_LB_VLINE_START_END__VLINE_INV__SHIFT 0x1f
++#define LB1_LB_VLINE_START_END__VLINE_START_MASK 0x00003FFFL
++#define LB1_LB_VLINE_START_END__VLINE_END_MASK 0x7FFF0000L
++#define LB1_LB_VLINE_START_END__VLINE_INV_MASK 0x80000000L
++//LB1_LB_VLINE2_START_END
++#define LB1_LB_VLINE2_START_END__VLINE2_START__SHIFT 0x0
++#define LB1_LB_VLINE2_START_END__VLINE2_END__SHIFT 0x10
++#define LB1_LB_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f
++#define LB1_LB_VLINE2_START_END__VLINE2_START_MASK 0x00003FFFL
++#define LB1_LB_VLINE2_START_END__VLINE2_END_MASK 0x7FFF0000L
++#define LB1_LB_VLINE2_START_END__VLINE2_INV_MASK 0x80000000L
++//LB1_LB_V_COUNTER
++#define LB1_LB_V_COUNTER__V_COUNTER__SHIFT 0x0
++#define LB1_LB_V_COUNTER__V_COUNTER_MASK 0x00007FFFL
++//LB1_LB_SNAPSHOT_V_COUNTER
++#define LB1_LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0
++#define LB1_LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x00007FFFL
++//LB1_LB_INTERRUPT_MASK
++#define LB1_LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0
++#define LB1_LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4
++#define LB1_LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8
++#define LB1_LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x00000001L
++#define LB1_LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x00000010L
++#define LB1_LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x00000100L
++//LB1_LB_VLINE_STATUS
++#define LB1_LB_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0
++#define LB1_LB_VLINE_STATUS__VLINE_ACK__SHIFT 0x4
++#define LB1_LB_VLINE_STATUS__VLINE_STAT__SHIFT 0xc
++#define LB1_LB_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10
++#define LB1_LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11
++#define LB1_LB_VLINE_STATUS__VLINE_OCCURRED_MASK 0x00000001L
++#define LB1_LB_VLINE_STATUS__VLINE_ACK_MASK 0x00000010L
++#define LB1_LB_VLINE_STATUS__VLINE_STAT_MASK 0x00001000L
++#define LB1_LB_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x00010000L
++#define LB1_LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x00020000L
++//LB1_LB_VLINE2_STATUS
++#define LB1_LB_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0
++#define LB1_LB_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4
++#define LB1_LB_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc
++#define LB1_LB_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10
++#define LB1_LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11
++#define LB1_LB_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x00000001L
++#define LB1_LB_VLINE2_STATUS__VLINE2_ACK_MASK 0x00000010L
++#define LB1_LB_VLINE2_STATUS__VLINE2_STAT_MASK 0x00001000L
++#define LB1_LB_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x00010000L
++#define LB1_LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x00020000L
++//LB1_LB_VBLANK_STATUS
++#define LB1_LB_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0
++#define LB1_LB_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4
++#define LB1_LB_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc
++#define LB1_LB_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10
++#define LB1_LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11
++#define LB1_LB_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x00000001L
++#define LB1_LB_VBLANK_STATUS__VBLANK_ACK_MASK 0x00000010L
++#define LB1_LB_VBLANK_STATUS__VBLANK_STAT_MASK 0x00001000L
++#define LB1_LB_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x00010000L
++#define LB1_LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x00020000L
++//LB1_LB_SYNC_RESET_SEL
++#define LB1_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0
++#define LB1_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4
++#define LB1_LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8
++#define LB1_LB_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16
++#define LB1_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x00000003L
++#define LB1_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x00000010L
++#define LB1_LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0x0000FF00L
++#define LB1_LB_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0x00C00000L
++//LB1_LB_BLACK_KEYER_R_CR
++#define LB1_LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4
++#define LB1_LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0x0000FFF0L
++//LB1_LB_BLACK_KEYER_G_Y
++#define LB1_LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4
++#define LB1_LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0x0000FFF0L
++//LB1_LB_BLACK_KEYER_B_CB
++#define LB1_LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4
++#define LB1_LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0x0000FFF0L
++//LB1_LB_KEYER_COLOR_CTRL
++#define LB1_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0
++#define LB1_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8
++#define LB1_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x00000001L
++#define LB1_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x00000100L
++//LB1_LB_KEYER_COLOR_R_CR
++#define LB1_LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4
++#define LB1_LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0x0000FFF0L
++//LB1_LB_KEYER_COLOR_G_Y
++#define LB1_LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4
++#define LB1_LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0x0000FFF0L
++//LB1_LB_KEYER_COLOR_B_CB
++#define LB1_LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4
++#define LB1_LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0x0000FFF0L
++//LB1_LB_KEYER_COLOR_REP_R_CR
++#define LB1_LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4
++#define LB1_LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0x0000FFF0L
++//LB1_LB_KEYER_COLOR_REP_G_Y
++#define LB1_LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4
++#define LB1_LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0x0000FFF0L
++//LB1_LB_KEYER_COLOR_REP_B_CB
++#define LB1_LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4
++#define LB1_LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0x0000FFF0L
++//LB1_LB_BUFFER_LEVEL_STATUS
++#define LB1_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0
++#define LB1_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa
++#define LB1_LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10
++#define LB1_LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c
++#define LB1_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x0000003FL
++#define LB1_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0x0000FC00L
++#define LB1_LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0x0FFF0000L
++#define LB1_LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xF0000000L
++//LB1_LB_BUFFER_URGENCY_CTRL
++#define LB1_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0
++#define LB1_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10
++#define LB1_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0x00000FFFL
++#define LB1_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0x0FFF0000L
++//LB1_LB_BUFFER_URGENCY_STATUS
++#define LB1_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0
++#define LB1_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10
++#define LB1_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0x00000FFFL
++#define LB1_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x00010000L
++//LB1_LB_BUFFER_STATUS
++#define LB1_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0
++#define LB1_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4
++#define LB1_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8
++#define LB1_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc
++#define LB1_LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10
++#define LB1_LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14
++#define LB1_LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18
++#define LB1_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0x0000000FL
++#define LB1_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x00000010L
++#define LB1_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x00000100L
++#define LB1_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x00001000L
++#define LB1_LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x00010000L
++#define LB1_LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x00100000L
++#define LB1_LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x01000000L
++//LB1_LB_NO_OUTSTANDING_REQ_STATUS
++#define LB1_LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0
++#define LB1_LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x00000001L
++//LB1_MVP_AFR_FLIP_MODE
++#define LB1_MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT 0x0
++#define LB1_MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK 0x00000003L
++//LB1_MVP_AFR_FLIP_FIFO_CNTL
++#define LB1_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT 0x0
++#define LB1_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT 0x4
++#define LB1_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT 0x8
++#define LB1_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT 0xc
++#define LB1_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK 0x0000000FL
++#define LB1_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK 0x00000010L
++#define LB1_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK 0x00000100L
++#define LB1_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK 0x00001000L
++//LB1_MVP_FLIP_LINE_NUM_INSERT
++#define LB1_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT 0x0
++#define LB1_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT 0x8
++#define LB1_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT 0x18
++#define LB1_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT 0x1e
++#define LB1_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK 0x00000003L
++#define LB1_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK 0x007FFF00L
++#define LB1_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK 0x3F000000L
++#define LB1_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK 0x40000000L
++//LB1_DC_MVP_LB_CONTROL
++#define LB1_DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT 0x0
++#define LB1_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT 0x8
++#define LB1_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT 0xc
++#define LB1_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT 0x10
++#define LB1_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT 0x14
++#define LB1_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT 0x1c
++#define LB1_DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT 0x1f
++#define LB1_DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK 0x00000003L
++#define LB1_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK 0x00000100L
++#define LB1_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK 0x00001000L
++#define LB1_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK 0x00010000L
++#define LB1_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK 0x00100000L
++#define LB1_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK 0x10000000L
++#define LB1_DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK 0x80000000L
++
++
++// addressBlock: dce_dc_dcfe1_dispdec
++//DCFE1_DCFE_CLOCK_CONTROL
++#define DCFE1_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x4
++#define DCFE1_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x8
++#define DCFE1_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0xc
++#define DCFE1_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE__SHIFT 0xf
++#define DCFE1_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE__SHIFT 0x11
++#define DCFE1_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL__SHIFT 0x18
++#define DCFE1_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE__SHIFT 0x1f
++#define DCFE1_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x00000010L
++#define DCFE1_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE_MASK 0x00000100L
++#define DCFE1_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE_MASK 0x00001000L
++#define DCFE1_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE_MASK 0x00008000L
++#define DCFE1_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE_MASK 0x00020000L
++#define DCFE1_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL_MASK 0x1F000000L
++#define DCFE1_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE_MASK 0x80000000L
++//DCFE1_DCFE_SOFT_RESET
++#define DCFE1_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET__SHIFT 0x0
++#define DCFE1_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET__SHIFT 0x1
++#define DCFE1_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET__SHIFT 0x2
++#define DCFE1_DCFE_SOFT_RESET__SCL_SOFT_RESET__SHIFT 0x3
++#define DCFE1_DCFE_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4
++#define DCFE1_DCFE_SOFT_RESET__PSCL_SOFT_RESET__SHIFT 0x5
++#define DCFE1_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET_MASK 0x00000001L
++#define DCFE1_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET_MASK 0x00000002L
++#define DCFE1_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET_MASK 0x00000004L
++#define DCFE1_DCFE_SOFT_RESET__SCL_SOFT_RESET_MASK 0x00000008L
++#define DCFE1_DCFE_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x00000010L
++#define DCFE1_DCFE_SOFT_RESET__PSCL_SOFT_RESET_MASK 0x00000020L
++//DCFE1_DCFE_MEM_PWR_CTRL
++#define DCFE1_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE__SHIFT 0x0
++#define DCFE1_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS__SHIFT 0x2
++#define DCFE1_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE__SHIFT 0x3
++#define DCFE1_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS__SHIFT 0x5
++#define DCFE1_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE__SHIFT 0x6
++#define DCFE1_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS__SHIFT 0x8
++#define DCFE1_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE__SHIFT 0x9
++#define DCFE1_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS__SHIFT 0xb
++#define DCFE1_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE__SHIFT 0xc
++#define DCFE1_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS__SHIFT 0xe
++#define DCFE1_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE__SHIFT 0xf
++#define DCFE1_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS__SHIFT 0x11
++#define DCFE1_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE__SHIFT 0x12
++#define DCFE1_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS__SHIFT 0x14
++#define DCFE1_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE__SHIFT 0x15
++#define DCFE1_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS__SHIFT 0x17
++#define DCFE1_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE__SHIFT 0x18
++#define DCFE1_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS__SHIFT 0x1a
++#define DCFE1_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE__SHIFT 0x1b
++#define DCFE1_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS__SHIFT 0x1d
++#define DCFE1_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE_MASK 0x00000003L
++#define DCFE1_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS_MASK 0x00000004L
++#define DCFE1_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE_MASK 0x00000018L
++#define DCFE1_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS_MASK 0x00000020L
++#define DCFE1_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE_MASK 0x000000C0L
++#define DCFE1_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS_MASK 0x00000100L
++#define DCFE1_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE_MASK 0x00000600L
++#define DCFE1_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS_MASK 0x00000800L
++#define DCFE1_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE_MASK 0x00003000L
++#define DCFE1_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS_MASK 0x00004000L
++#define DCFE1_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE_MASK 0x00018000L
++#define DCFE1_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK 0x00020000L
++#define DCFE1_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE_MASK 0x000C0000L
++#define DCFE1_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS_MASK 0x00100000L
++#define DCFE1_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE_MASK 0x00600000L
++#define DCFE1_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS_MASK 0x00800000L
++#define DCFE1_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE_MASK 0x03000000L
++#define DCFE1_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS_MASK 0x04000000L
++#define DCFE1_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE_MASK 0x18000000L
++#define DCFE1_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS_MASK 0x20000000L
++//DCFE1_DCFE_MEM_PWR_CTRL2
++#define DCFE1_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL__SHIFT 0x0
++#define DCFE1_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2
++#define DCFE1_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4
++#define DCFE1_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL__SHIFT 0x6
++#define DCFE1_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL__SHIFT 0x8
++#define DCFE1_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL__SHIFT 0xa
++#define DCFE1_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL__SHIFT 0xc
++#define DCFE1_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL__SHIFT 0xe
++#define DCFE1_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE__SHIFT 0x10
++#define DCFE1_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS__SHIFT 0x12
++#define DCFE1_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE__SHIFT 0x15
++#define DCFE1_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS__SHIFT 0x17
++#define DCFE1_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL_MASK 0x00000003L
++#define DCFE1_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL_MASK 0x0000000CL
++#define DCFE1_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL_MASK 0x00000030L
++#define DCFE1_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL_MASK 0x000000C0L
++#define DCFE1_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL_MASK 0x00000300L
++#define DCFE1_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL_MASK 0x00000C00L
++#define DCFE1_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL_MASK 0x00003000L
++#define DCFE1_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL_MASK 0x0000C000L
++#define DCFE1_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE_MASK 0x00030000L
++#define DCFE1_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS_MASK 0x00040000L
++#define DCFE1_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE_MASK 0x00600000L
++#define DCFE1_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS_MASK 0x00800000L
++//DCFE1_DCFE_MEM_PWR_STATUS
++#define DCFE1_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE__SHIFT 0x0
++#define DCFE1_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE__SHIFT 0x2
++#define DCFE1_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE__SHIFT 0x4
++#define DCFE1_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x6
++#define DCFE1_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE__SHIFT 0x8
++#define DCFE1_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE__SHIFT 0xa
++#define DCFE1_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE__SHIFT 0xc
++#define DCFE1_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE__SHIFT 0xe
++#define DCFE1_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT 0x10
++#define DCFE1_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE__SHIFT 0x12
++#define DCFE1_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE__SHIFT 0x14
++#define DCFE1_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE__SHIFT 0x16
++#define DCFE1_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK 0x00000003L
++#define DCFE1_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE_MASK 0x0000000CL
++#define DCFE1_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE_MASK 0x00000030L
++#define DCFE1_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE_MASK 0x000000C0L
++#define DCFE1_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE_MASK 0x00000300L
++#define DCFE1_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE_MASK 0x00000C00L
++#define DCFE1_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE_MASK 0x00003000L
++#define DCFE1_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE_MASK 0x0000C000L
++#define DCFE1_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE_MASK 0x00030000L
++#define DCFE1_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK 0x000C0000L
++#define DCFE1_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE_MASK 0x00300000L
++#define DCFE1_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE_MASK 0x00C00000L
++//DCFE1_DCFE_MISC
++#define DCFE1_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN__SHIFT 0x0
++#define DCFE1_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN_MASK 0x00000001L
++//DCFE1_DCFE_FLUSH
++#define DCFE1_DCFE_FLUSH__FLUSH_OCCURED__SHIFT 0x0
++#define DCFE1_DCFE_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT 0x1
++#define DCFE1_DCFE_FLUSH__FLUSH_DEEP__SHIFT 0x2
++#define DCFE1_DCFE_FLUSH__CLEAR_FLUSH_DEEP__SHIFT 0x3
++#define DCFE1_DCFE_FLUSH__ALL_MC_REQ_RET__SHIFT 0x4
++#define DCFE1_DCFE_FLUSH__FLUSH_OCCURED_MASK 0x00000001L
++#define DCFE1_DCFE_FLUSH__CLEAR_FLUSH_OCCURED_MASK 0x00000002L
++#define DCFE1_DCFE_FLUSH__FLUSH_DEEP_MASK 0x00000004L
++#define DCFE1_DCFE_FLUSH__CLEAR_FLUSH_DEEP_MASK 0x00000008L
++#define DCFE1_DCFE_FLUSH__ALL_MC_REQ_RET_MASK 0x00000010L
++
++
++// addressBlock: dce_dc_dc_perfmon4_dispdec
++//DC_PERFMON4_PERFCOUNTER_CNTL
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
++//DC_PERFMON4_PERFCOUNTER_CNTL2
++#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
++#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
++#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
++#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
++#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
++#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
++#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
++#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
++//DC_PERFMON4_PERFCOUNTER_STATE
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
++//DC_PERFMON4_PERFMON_CNTL
++#define DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
++#define DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
++#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
++#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
++#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
++#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
++#define DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
++#define DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
++#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
++#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
++#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
++#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
++//DC_PERFMON4_PERFMON_CNTL2
++#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
++#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
++#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
++#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
++#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
++#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
++#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
++#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
++//DC_PERFMON4_PERFMON_CVALUE_INT_MISC
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
++//DC_PERFMON4_PERFMON_CVALUE_LOW
++#define DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
++#define DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
++//DC_PERFMON4_PERFMON_HI
++#define DC_PERFMON4_PERFMON_HI__PERFMON_HI__SHIFT 0x0
++#define DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
++#define DC_PERFMON4_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
++#define DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
++//DC_PERFMON4_PERFMON_LOW
++#define DC_PERFMON4_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
++#define DC_PERFMON4_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dmif_pg1_dispdec
++//DMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1
++#define DMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
++#define DMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
++#define DMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0x0000FFFFL
++#define DMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xFFFF0000L
++//DMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2
++#define DMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
++#define DMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
++#define DMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0x0000FFFFL
++#define DMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xFFFF0000L
++//DMIF_PG1_DPG_WATERMARK_MASK_CONTROL
++#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
++#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x4
++#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
++#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK__SHIFT 0xc
++#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0xf
++#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x12
++#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL__SHIFT 0x13
++#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL__SHIFT 0x14
++#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000007L
++#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000070L
++#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x00000700L
++#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK_MASK 0x00007000L
++#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00038000L
++#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x00040000L
++#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL_MASK 0x00080000L
++#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL_MASK 0x3FF00000L
++//DMIF_PG1_DPG_PIPE_URGENCY_CONTROL
++#define DMIF_PG1_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
++#define DMIF_PG1_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
++#define DMIF_PG1_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0x0000FFFFL
++#define DMIF_PG1_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xFFFF0000L
++//DMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL
++#define DMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK__SHIFT 0x0
++#define DMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK__SHIFT 0x10
++#define DMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK_MASK 0x0000FFFFL
++#define DMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK_MASK 0xFFFF0000L
++//DMIF_PG1_DPG_PIPE_STUTTER_CONTROL
++#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
++#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
++#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
++#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
++#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
++#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
++#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
++#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH__SHIFT 0x10
++#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x14
++#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x15
++#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x16
++#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x17
++#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0x1a
++#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0x1b
++#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L
++#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L
++#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x00000020L
++#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x00000040L
++#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x00000080L
++#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x00000400L
++#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x00000800L
++#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH_MASK 0x00010000L
++#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x00100000L
++#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x00200000L
++#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x00400000L
++#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x00800000L
++#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x04000000L
++#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x08000000L
++//DMIF_PG1_DPG_PIPE_STUTTER_CONTROL2
++#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x0
++#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK__SHIFT 0x10
++#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0x0000FFFFL
++#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK 0xFFFF0000L
++//DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL
++#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE__SHIFT 0x0
++#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE__SHIFT 0x1
++#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
++#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
++#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
++#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
++#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK__SHIFT 0xf
++#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE_MASK 0x00000001L
++#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE_MASK 0x00000002L
++#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L
++#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x00000100L
++#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON_MASK 0x00000200L
++#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT_MASK 0x00000400L
++#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK_MASK 0xFFFF8000L
++//DMIF_PG1_DPG_REPEATER_PROGRAM
++#define DMIF_PG1_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
++#define DMIF_PG1_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
++#define DMIF_PG1_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x00000007L
++#define DMIF_PG1_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x00000070L
++//DMIF_PG1_DPG_CHK_PRE_PROC_CNTL
++#define DMIF_PG1_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0
++#define DMIF_PG1_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x00000001L
++//DMIF_PG1_DPG_DVMM_STATUS
++#define DMIF_PG1_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED__SHIFT 0x0
++#define DMIF_PG1_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED__SHIFT 0x1
++#define DMIF_PG1_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR__SHIFT 0x4
++#define DMIF_PG1_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR__SHIFT 0x5
++#define DMIF_PG1_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_MASK 0x00000001L
++#define DMIF_PG1_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_MASK 0x00000002L
++#define DMIF_PG1_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR_MASK 0x00000010L
++#define DMIF_PG1_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR_MASK 0x00000020L
++
++
++// addressBlock: dce_dc_scl1_dispdec
++//SCL1_SCL_COEF_RAM_SELECT
++#define SCL1_SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0
++#define SCL1_SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8
++#define SCL1_SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10
++#define SCL1_SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x0000000FL
++#define SCL1_SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x00000F00L
++#define SCL1_SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x00070000L
++//SCL1_SCL_COEF_RAM_TAP_DATA
++#define SCL1_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0
++#define SCL1_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
++#define SCL1_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10
++#define SCL1_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
++#define SCL1_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL
++#define SCL1_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L
++#define SCL1_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L
++#define SCL1_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L
++//SCL1_SCL_MODE
++#define SCL1_SCL_MODE__SCL_MODE__SHIFT 0x0
++#define SCL1_SCL_MODE__SCL_PSCL_EN__SHIFT 0x4
++#define SCL1_SCL_MODE__SCL_MODE_MASK 0x00000003L
++#define SCL1_SCL_MODE__SCL_PSCL_EN_MASK 0x00000010L
++//SCL1_SCL_TAP_CONTROL
++#define SCL1_SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0
++#define SCL1_SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x8
++#define SCL1_SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x00000007L
++#define SCL1_SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0x00000F00L
++//SCL1_SCL_CONTROL
++#define SCL1_SCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
++#define SCL1_SCL_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4
++#define SCL1_SCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L
++#define SCL1_SCL_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x00000010L
++//SCL1_SCL_BYPASS_CONTROL
++#define SCL1_SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT 0x0
++#define SCL1_SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x00000003L
++//SCL1_SCL_MANUAL_REPLICATE_CONTROL
++#define SCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
++#define SCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
++#define SCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL
++#define SCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L
++//SCL1_SCL_AUTOMATIC_MODE_CONTROL
++#define SCL1_SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0
++#define SCL1_SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10
++#define SCL1_SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x00000001L
++#define SCL1_SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x00010000L
++//SCL1_SCL_HORZ_FILTER_CONTROL
++#define SCL1_SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT 0x0
++#define SCL1_SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
++#define SCL1_SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK 0x00000001L
++#define SCL1_SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
++//SCL1_SCL_HORZ_FILTER_SCALE_RATIO
++#define SCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
++#define SCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL
++//SCL1_SCL_HORZ_FILTER_INIT
++#define SCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
++#define SCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
++#define SCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL
++#define SCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L
++//SCL1_SCL_VERT_FILTER_CONTROL
++#define SCL1_SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT 0x0
++#define SCL1_SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
++#define SCL1_SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK 0x00000001L
++#define SCL1_SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
++//SCL1_SCL_VERT_FILTER_SCALE_RATIO
++#define SCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
++#define SCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL
++//SCL1_SCL_VERT_FILTER_INIT
++#define SCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
++#define SCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
++#define SCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL
++#define SCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x07000000L
++//SCL1_SCL_VERT_FILTER_INIT_BOT
++#define SCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
++#define SCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
++#define SCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL
++#define SCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x07000000L
++//SCL1_SCL_ROUND_OFFSET
++#define SCL1_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0
++#define SCL1_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10
++#define SCL1_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0x0000FFFFL
++#define SCL1_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xFFFF0000L
++//SCL1_SCL_UPDATE
++#define SCL1_SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
++#define SCL1_SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8
++#define SCL1_SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10
++#define SCL1_SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18
++#define SCL1_SCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L
++#define SCL1_SCL_UPDATE__SCL_UPDATE_TAKEN_MASK 0x00000100L
++#define SCL1_SCL_UPDATE__SCL_UPDATE_LOCK_MASK 0x00010000L
++#define SCL1_SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x01000000L
++//SCL1_SCL_F_SHARP_CONTROL
++#define SCL1_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT 0x0
++#define SCL1_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT 0x4
++#define SCL1_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT 0x8
++#define SCL1_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT 0xc
++#define SCL1_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK 0x00000007L
++#define SCL1_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK 0x00000010L
++#define SCL1_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK 0x00000700L
++#define SCL1_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK 0x00001000L
++//SCL1_SCL_ALU_CONTROL
++#define SCL1_SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0
++#define SCL1_SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x00000001L
++//SCL1_SCL_COEF_RAM_CONFLICT_STATUS
++#define SCL1_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT 0x0
++#define SCL1_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT 0x8
++#define SCL1_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT 0xc
++#define SCL1_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10
++#define SCL1_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK 0x00000001L
++#define SCL1_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK 0x00000100L
++#define SCL1_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK 0x00001000L
++#define SCL1_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK 0x00010000L
++//SCL1_VIEWPORT_START_SECONDARY
++#define SCL1_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0
++#define SCL1_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10
++#define SCL1_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x00003FFFL
++#define SCL1_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3FFF0000L
++//SCL1_VIEWPORT_START
++#define SCL1_VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0
++#define SCL1_VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10
++#define SCL1_VIEWPORT_START__VIEWPORT_Y_START_MASK 0x00003FFFL
++#define SCL1_VIEWPORT_START__VIEWPORT_X_START_MASK 0x3FFF0000L
++//SCL1_VIEWPORT_SIZE
++#define SCL1_VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0
++#define SCL1_VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10
++#define SCL1_VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x00003FFFL
++#define SCL1_VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x3FFF0000L
++//SCL1_EXT_OVERSCAN_LEFT_RIGHT
++#define SCL1_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
++#define SCL1_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
++#define SCL1_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL
++#define SCL1_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L
++//SCL1_EXT_OVERSCAN_TOP_BOTTOM
++#define SCL1_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
++#define SCL1_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
++#define SCL1_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL
++#define SCL1_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L
++//SCL1_SCL_MODE_CHANGE_DET1
++#define SCL1_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0
++#define SCL1_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4
++#define SCL1_SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7
++#define SCL1_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x00000001L
++#define SCL1_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x00000010L
++#define SCL1_SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0x0FFFFF80L
++//SCL1_SCL_MODE_CHANGE_DET2
++#define SCL1_SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0
++#define SCL1_SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x001FFFFFL
++//SCL1_SCL_MODE_CHANGE_DET3
++#define SCL1_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0
++#define SCL1_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10
++#define SCL1_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x00003FFFL
++#define SCL1_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3FFF0000L
++//SCL1_SCL_MODE_CHANGE_MASK
++#define SCL1_SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0
++#define SCL1_SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x00000001L
++
++
++// addressBlock: dce_dc_blnd1_dispdec
++//BLND1_BLND_CONTROL
++#define BLND1_BLND_CONTROL__BLND_GLOBAL_GAIN__SHIFT 0x0
++#define BLND1_BLND_CONTROL__BLND_MODE__SHIFT 0x8
++#define BLND1_BLND_CONTROL__BLND_STEREO_TYPE__SHIFT 0xa
++#define BLND1_BLND_CONTROL__BLND_STEREO_POLARITY__SHIFT 0xc
++#define BLND1_BLND_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT 0xd
++#define BLND1_BLND_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10
++#define BLND1_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x12
++#define BLND1_BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14
++#define BLND1_BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18
++#define BLND1_BLND_CONTROL__BLND_GLOBAL_GAIN_MASK 0x000000FFL
++#define BLND1_BLND_CONTROL__BLND_MODE_MASK 0x00000300L
++#define BLND1_BLND_CONTROL__BLND_STEREO_TYPE_MASK 0x00000C00L
++#define BLND1_BLND_CONTROL__BLND_STEREO_POLARITY_MASK 0x00001000L
++#define BLND1_BLND_CONTROL__BLND_FEEDTHROUGH_EN_MASK 0x00002000L
++#define BLND1_BLND_CONTROL__BLND_ALPHA_MODE_MASK 0x00030000L
++#define BLND1_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00040000L
++#define BLND1_BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x00100000L
++#define BLND1_BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xFF000000L
++//BLND1_BLND_SM_CONTROL2
++#define BLND1_BLND_SM_CONTROL2__SM_MODE__SHIFT 0x0
++#define BLND1_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4
++#define BLND1_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5
++#define BLND1_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
++#define BLND1_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
++#define BLND1_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18
++#define BLND1_BLND_SM_CONTROL2__SM_MODE_MASK 0x00000007L
++#define BLND1_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x00000010L
++#define BLND1_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x00000020L
++#define BLND1_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L
++#define BLND1_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L
++#define BLND1_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x01000000L
++//BLND1_BLND_CONTROL2
++#define BLND1_BLND_CONTROL2__PTI_ENABLE__SHIFT 0x0
++#define BLND1_BLND_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT 0x4
++#define BLND1_BLND_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT 0x6
++#define BLND1_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT 0x7
++#define BLND1_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT 0x8
++#define BLND1_BLND_CONTROL2__PTI_ENABLE_MASK 0x00000001L
++#define BLND1_BLND_CONTROL2__PTI_NEW_PIXEL_GAP_MASK 0x00000030L
++#define BLND1_BLND_CONTROL2__BLND_NEW_PIXEL_MODE_MASK 0x00000040L
++#define BLND1_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK 0x00000080L
++#define BLND1_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK 0x00000100L
++//BLND1_BLND_UPDATE
++#define BLND1_BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0
++#define BLND1_BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8
++#define BLND1_BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10
++#define BLND1_BLND_UPDATE__BLND_UPDATE_PENDING_MASK 0x00000001L
++#define BLND1_BLND_UPDATE__BLND_UPDATE_TAKEN_MASK 0x00000100L
++#define BLND1_BLND_UPDATE__BLND_UPDATE_LOCK_MASK 0x00010000L
++//BLND1_BLND_UNDERFLOW_INTERRUPT
++#define BLND1_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0
++#define BLND1_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8
++#define BLND1_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc
++#define BLND1_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10
++#define BLND1_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x00000001L
++#define BLND1_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x00000100L
++#define BLND1_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x00001000L
++#define BLND1_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x00030000L
++//BLND1_BLND_V_UPDATE_LOCK
++#define BLND1_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0
++#define BLND1_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1
++#define BLND1_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10
++#define BLND1_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c
++#define BLND1_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT 0x1d
++#define BLND1_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT 0x1f
++#define BLND1_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x00000001L
++#define BLND1_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x00000002L
++#define BLND1_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x00010000L
++#define BLND1_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000L
++#define BLND1_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK 0x20000000L
++#define BLND1_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK 0x80000000L
++//BLND1_BLND_REG_UPDATE_STATUS
++#define BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT 0x0
++#define BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT 0x1
++#define BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2
++#define BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3
++#define BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT 0x6
++#define BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT 0x7
++#define BLND1_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT 0x8
++#define BLND1_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT 0x9
++#define BLND1_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT 0xa
++#define BLND1_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT 0xb
++#define BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK 0x00000001L
++#define BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK 0x00000002L
++#define BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK 0x00000004L
++#define BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK 0x00000008L
++#define BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK 0x00000040L
++#define BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK 0x00000080L
++#define BLND1_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK 0x00000100L
++#define BLND1_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK 0x00000200L
++#define BLND1_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK 0x00000400L
++#define BLND1_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK 0x00000800L
++
++
++// addressBlock: dce_dc_crtc1_dispdec
++//CRTC1_CRTC_H_BLANK_EARLY_NUM
++#define CRTC1_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0
++#define CRTC1_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10
++#define CRTC1_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x000003FFL
++#define CRTC1_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x00010000L
++//CRTC1_CRTC_H_TOTAL
++#define CRTC1_CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0
++#define CRTC1_CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x00003FFFL
++//CRTC1_CRTC_H_BLANK_START_END
++#define CRTC1_CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0
++#define CRTC1_CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10
++#define CRTC1_CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x00003FFFL
++#define CRTC1_CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3FFF0000L
++//CRTC1_CRTC_H_SYNC_A
++#define CRTC1_CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0
++#define CRTC1_CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10
++#define CRTC1_CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x00003FFFL
++#define CRTC1_CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3FFF0000L
++//CRTC1_CRTC_H_SYNC_A_CNTL
++#define CRTC1_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0
++#define CRTC1_CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10
++#define CRTC1_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11
++#define CRTC1_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x00000001L
++#define CRTC1_CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x00010000L
++#define CRTC1_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x00020000L
++//CRTC1_CRTC_H_SYNC_B
++#define CRTC1_CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0
++#define CRTC1_CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10
++#define CRTC1_CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x00003FFFL
++#define CRTC1_CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x3FFF0000L
++//CRTC1_CRTC_H_SYNC_B_CNTL
++#define CRTC1_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0
++#define CRTC1_CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10
++#define CRTC1_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11
++#define CRTC1_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x00000001L
++#define CRTC1_CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x00010000L
++#define CRTC1_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x00020000L
++//CRTC1_CRTC_VBI_END
++#define CRTC1_CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x0
++#define CRTC1_CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x10
++#define CRTC1_CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x00003FFFL
++#define CRTC1_CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x3FFF0000L
++//CRTC1_CRTC_V_TOTAL
++#define CRTC1_CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0
++#define CRTC1_CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x00003FFFL
++//CRTC1_CRTC_V_TOTAL_MIN
++#define CRTC1_CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0
++#define CRTC1_CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x00003FFFL
++//CRTC1_CRTC_V_TOTAL_MAX
++#define CRTC1_CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0
++#define CRTC1_CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10
++#define CRTC1_CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x00003FFFL
++#define CRTC1_CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x00010000L
++//CRTC1_CRTC_V_TOTAL_CONTROL
++#define CRTC1_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0
++#define CRTC1_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4
++#define CRTC1_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8
++#define CRTC1_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc
++#define CRTC1_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf
++#define CRTC1_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10
++#define CRTC1_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x00000001L
++#define CRTC1_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x00000010L
++#define CRTC1_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x00000100L
++#define CRTC1_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x00001000L
++#define CRTC1_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00008000L
++#define CRTC1_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L
++//CRTC1_CRTC_V_TOTAL_INT_STATUS
++#define CRTC1_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0
++#define CRTC1_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4
++#define CRTC1_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8
++#define CRTC1_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc
++#define CRTC1_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L
++#define CRTC1_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L
++#define CRTC1_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L
++#define CRTC1_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L
++//CRTC1_CRTC_VSYNC_NOM_INT_STATUS
++#define CRTC1_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0
++#define CRTC1_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4
++#define CRTC1_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x00000001L
++#define CRTC1_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L
++//CRTC1_CRTC_V_BLANK_START_END
++#define CRTC1_CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0
++#define CRTC1_CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10
++#define CRTC1_CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x00003FFFL
++#define CRTC1_CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3FFF0000L
++//CRTC1_CRTC_V_SYNC_A
++#define CRTC1_CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0
++#define CRTC1_CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10
++#define CRTC1_CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x00003FFFL
++#define CRTC1_CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3FFF0000L
++//CRTC1_CRTC_V_SYNC_A_CNTL
++#define CRTC1_CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0
++#define CRTC1_CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x00000001L
++//CRTC1_CRTC_V_SYNC_B
++#define CRTC1_CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0
++#define CRTC1_CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10
++#define CRTC1_CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x00003FFFL
++#define CRTC1_CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x3FFF0000L
++//CRTC1_CRTC_V_SYNC_B_CNTL
++#define CRTC1_CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0
++#define CRTC1_CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x00000001L
++//CRTC1_CRTC_DTMTEST_CNTL
++#define CRTC1_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0
++#define CRTC1_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1
++#define CRTC1_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x00000001L
++#define CRTC1_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x0000001EL
++//CRTC1_CRTC_DTMTEST_STATUS_POSITION
++#define CRTC1_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0
++#define CRTC1_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10
++#define CRTC1_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x00003FFFL
++#define CRTC1_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x3FFF0000L
++//CRTC1_CRTC_TRIGA_CNTL
++#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0
++#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5
++#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8
++#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9
++#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa
++#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb
++#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
++#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
++#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14
++#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18
++#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f
++#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x0000001FL
++#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0x000000E0L
++#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000100L
++#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x00000200L
++#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x00000400L
++#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x00000800L
++#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
++#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
++#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L
++#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1F000000L
++#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000L
++//CRTC1_CRTC_TRIGA_MANUAL_TRIG
++#define CRTC1_CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0
++#define CRTC1_CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x00000001L
++//CRTC1_CRTC_TRIGB_CNTL
++#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0
++#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5
++#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8
++#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9
++#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa
++#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb
++#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
++#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
++#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14
++#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18
++#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f
++#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x0000001FL
++#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0x000000E0L
++#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000100L
++#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x00000200L
++#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x00000400L
++#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x00000800L
++#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
++#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
++#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L
++#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1F000000L
++#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000L
++//CRTC1_CRTC_TRIGB_MANUAL_TRIG
++#define CRTC1_CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0
++#define CRTC1_CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x00000001L
++//CRTC1_CRTC_FORCE_COUNT_NOW_CNTL
++#define CRTC1_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0
++#define CRTC1_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4
++#define CRTC1_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8
++#define CRTC1_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10
++#define CRTC1_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18
++#define CRTC1_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x00000003L
++#define CRTC1_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L
++#define CRTC1_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L
++#define CRTC1_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L
++#define CRTC1_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L
++//CRTC1_CRTC_FLOW_CONTROL
++#define CRTC1_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0
++#define CRTC1_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8
++#define CRTC1_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10
++#define CRTC1_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18
++#define CRTC1_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL
++#define CRTC1_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x00000100L
++#define CRTC1_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L
++#define CRTC1_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L
++//CRTC1_CRTC_STEREO_FORCE_NEXT_EYE
++#define CRTC1_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0
++#define CRTC1_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER__SHIFT 0x8
++#define CRTC1_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER__SHIFT 0x10
++#define CRTC1_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L
++#define CRTC1_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L
++#define CRTC1_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L
++//CRTC1_CRTC_AVSYNC_COUNTER
++#define CRTC1_CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER__SHIFT 0x0
++#define CRTC1_CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER_MASK 0xFFFFFFFFL
++//CRTC1_CRTC_CONTROL
++#define CRTC1_CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x0
++#define CRTC1_CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4
++#define CRTC1_CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8
++#define CRTC1_CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc
++#define CRTC1_CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd
++#define CRTC1_CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe
++#define CRTC1_CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10
++#define CRTC1_CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14
++#define CRTC1_CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d
++#define CRTC1_CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e
++#define CRTC1_CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f
++#define CRTC1_CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x00000001L
++#define CRTC1_CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x00000010L
++#define CRTC1_CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x00000300L
++#define CRTC1_CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x00001000L
++#define CRTC1_CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x00002000L
++#define CRTC1_CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x00004000L
++#define CRTC1_CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x00010000L
++#define CRTC1_CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x00700000L
++#define CRTC1_CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000L
++#define CRTC1_CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L
++#define CRTC1_CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L
++//CRTC1_CRTC_BLANK_CONTROL
++#define CRTC1_CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0
++#define CRTC1_CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8
++#define CRTC1_CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10
++#define CRTC1_CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x00000001L
++#define CRTC1_CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x00000100L
++#define CRTC1_CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x00010000L
++//CRTC1_CRTC_INTERLACE_CONTROL
++#define CRTC1_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0
++#define CRTC1_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10
++#define CRTC1_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x00000001L
++#define CRTC1_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L
++//CRTC1_CRTC_INTERLACE_STATUS
++#define CRTC1_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0
++#define CRTC1_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1
++#define CRTC1_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x00000001L
++#define CRTC1_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x00000002L
++//CRTC1_CRTC_FIELD_INDICATION_CONTROL
++#define CRTC1_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0
++#define CRTC1_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1
++#define CRTC1_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x00000001L
++#define CRTC1_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x00000002L
++//CRTC1_CRTC_PIXEL_DATA_READBACK0
++#define CRTC1_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0
++#define CRTC1_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10
++#define CRTC1_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0x00000FFFL
++#define CRTC1_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0x0FFF0000L
++//CRTC1_CRTC_PIXEL_DATA_READBACK1
++#define CRTC1_CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0
++#define CRTC1_CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0x00000FFFL
++//CRTC1_CRTC_STATUS
++#define CRTC1_CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x0
++#define CRTC1_CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1
++#define CRTC1_CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x2
++#define CRTC1_CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x3
++#define CRTC1_CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x4
++#define CRTC1_CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5
++#define CRTC1_CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x10
++#define CRTC1_CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11
++#define CRTC1_CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x12
++#define CRTC1_CRTC_STATUS__CRTC_V_BLANK_MASK 0x00000001L
++#define CRTC1_CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x00000002L
++#define CRTC1_CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x00000004L
++#define CRTC1_CRTC_STATUS__CRTC_V_UPDATE_MASK 0x00000008L
++#define CRTC1_CRTC_STATUS__CRTC_V_START_LINE_MASK 0x00000010L
++#define CRTC1_CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x00000020L
++#define CRTC1_CRTC_STATUS__CRTC_H_BLANK_MASK 0x00010000L
++#define CRTC1_CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x00020000L
++#define CRTC1_CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x00040000L
++//CRTC1_CRTC_STATUS_POSITION
++#define CRTC1_CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0
++#define CRTC1_CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10
++#define CRTC1_CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x00003FFFL
++#define CRTC1_CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x3FFF0000L
++//CRTC1_CRTC_NOM_VERT_POSITION
++#define CRTC1_CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0
++#define CRTC1_CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x00003FFFL
++//CRTC1_CRTC_STATUS_FRAME_COUNT
++#define CRTC1_CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0
++#define CRTC1_CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0x00FFFFFFL
++//CRTC1_CRTC_STATUS_VF_COUNT
++#define CRTC1_CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0
++#define CRTC1_CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x3FFFFFFFL
++//CRTC1_CRTC_STATUS_HV_COUNT
++#define CRTC1_CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0
++#define CRTC1_CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x3FFFFFFFL
++//CRTC1_CRTC_COUNT_CONTROL
++#define CRTC1_CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0
++#define CRTC1_CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1
++#define CRTC1_CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x00000001L
++#define CRTC1_CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x0000001EL
++//CRTC1_CRTC_COUNT_RESET
++#define CRTC1_CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0
++#define CRTC1_CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x00000001L
++//CRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE
++#define CRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0
++#define CRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L
++//CRTC1_CRTC_VERT_SYNC_CONTROL
++#define CRTC1_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0
++#define CRTC1_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8
++#define CRTC1_CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10
++#define CRTC1_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L
++#define CRTC1_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L
++#define CRTC1_CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L
++//CRTC1_CRTC_STEREO_STATUS
++#define CRTC1_CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0
++#define CRTC1_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8
++#define CRTC1_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10
++#define CRTC1_CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG__SHIFT 0x14
++#define CRTC1_CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18
++#define CRTC1_CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x00000001L
++#define CRTC1_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x00000100L
++#define CRTC1_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x00010000L
++#define CRTC1_CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG_MASK 0x00100000L
++#define CRTC1_CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L
++//CRTC1_CRTC_STEREO_CONTROL
++#define CRTC1_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0
++#define CRTC1_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf
++#define CRTC1_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10
++#define CRTC1_CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11
++#define CRTC1_CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12
++#define CRTC1_CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM__SHIFT 0x13
++#define CRTC1_CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14
++#define CRTC1_CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18
++#define CRTC1_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00003FFFL
++#define CRTC1_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L
++#define CRTC1_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x00010000L
++#define CRTC1_CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L
++#define CRTC1_CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L
++#define CRTC1_CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM_MASK 0x00080000L
++#define CRTC1_CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L
++#define CRTC1_CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x01000000L
++//CRTC1_CRTC_SNAPSHOT_STATUS
++#define CRTC1_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0
++#define CRTC1_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1
++#define CRTC1_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2
++#define CRTC1_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x00000001L
++#define CRTC1_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x00000002L
++#define CRTC1_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L
++//CRTC1_CRTC_SNAPSHOT_CONTROL
++#define CRTC1_CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0
++#define CRTC1_CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L
++//CRTC1_CRTC_SNAPSHOT_POSITION
++#define CRTC1_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0
++#define CRTC1_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10
++#define CRTC1_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x00003FFFL
++#define CRTC1_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x3FFF0000L
++//CRTC1_CRTC_SNAPSHOT_FRAME
++#define CRTC1_CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0
++#define CRTC1_CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL
++//CRTC1_CRTC_START_LINE_CONTROL
++#define CRTC1_CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0
++#define CRTC1_CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x1
++#define CRTC1_CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x2
++#define CRTC1_CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x8
++#define CRTC1_CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc
++#define CRTC1_CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x00000001L
++#define CRTC1_CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x00000002L
++#define CRTC1_CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x00000004L
++#define CRTC1_CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x00000100L
++#define CRTC1_CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0x000FF000L
++//CRTC1_CRTC_INTERRUPT_CONTROL
++#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0
++#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1
++#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4
++#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5
++#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8
++#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9
++#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10
++#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11
++#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18
++#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19
++#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a
++#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b
++#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c
++#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d
++#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e
++#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f
++#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x00000001L
++#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x00000002L
++#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x00000010L
++#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x00000020L
++#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L
++#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L
++#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L
++#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L
++#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x01000000L
++#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x02000000L
++#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x04000000L
++#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x08000000L
++#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000L
++#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000L
++#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L
++#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L
++//CRTC1_CRTC_UPDATE_LOCK
++#define CRTC1_CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0
++#define CRTC1_CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x00000001L
++//CRTC1_CRTC_DOUBLE_BUFFER_CONTROL
++#define CRTC1_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0
++#define CRTC1_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8
++#define CRTC1_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10
++#define CRTC1_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18
++#define CRTC1_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x19
++#define CRTC1_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x00000001L
++#define CRTC1_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x00000100L
++#define CRTC1_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L
++#define CRTC1_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x01000000L
++#define CRTC1_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x02000000L
++//CRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE
++#define CRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0
++#define CRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x00000001L
++//CRTC1_CRTC_TEST_PATTERN_CONTROL
++#define CRTC1_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0
++#define CRTC1_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8
++#define CRTC1_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10
++#define CRTC1_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18
++#define CRTC1_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x00000001L
++#define CRTC1_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x00000700L
++#define CRTC1_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L
++#define CRTC1_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xFF000000L
++//CRTC1_CRTC_TEST_PATTERN_PARAMETERS
++#define CRTC1_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0
++#define CRTC1_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4
++#define CRTC1_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8
++#define CRTC1_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc
++#define CRTC1_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10
++#define CRTC1_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0x0000000FL
++#define CRTC1_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0x000000F0L
++#define CRTC1_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0x00000F00L
++#define CRTC1_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0x0000F000L
++#define CRTC1_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xFFFF0000L
++//CRTC1_CRTC_TEST_PATTERN_COLOR
++#define CRTC1_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0
++#define CRTC1_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10
++#define CRTC1_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0x0000FFFFL
++#define CRTC1_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x003F0000L
++//CRTC1_CRTC_MASTER_UPDATE_LOCK
++#define CRTC1_CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0
++#define CRTC1_CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8
++#define CRTC1_CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK__SHIFT 0x10
++#define CRTC1_CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x00000001L
++#define CRTC1_CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x00000100L
++#define CRTC1_CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK_MASK 0x00010000L
++//CRTC1_CRTC_MASTER_UPDATE_MODE
++#define CRTC1_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0
++#define CRTC1_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10
++#define CRTC1_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x00000007L
++#define CRTC1_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00030000L
++//CRTC1_CRTC_MVP_INBAND_CNTL_INSERT
++#define CRTC1_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0
++#define CRTC1_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8
++#define CRTC1_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x00000003L
++#define CRTC1_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xFFFFFF00L
++//CRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER
++#define CRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0
++#define CRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0x000000FFL
++//CRTC1_CRTC_MVP_STATUS
++#define CRTC1_CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0
++#define CRTC1_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4
++#define CRTC1_CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10
++#define CRTC1_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14
++#define CRTC1_CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x00000001L
++#define CRTC1_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x00000010L
++#define CRTC1_CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x00010000L
++#define CRTC1_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x00100000L
++//CRTC1_CRTC_MASTER_EN
++#define CRTC1_CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0
++#define CRTC1_CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x00000001L
++//CRTC1_CRTC_ALLOW_STOP_OFF_V_CNT
++#define CRTC1_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0
++#define CRTC1_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10
++#define CRTC1_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0x000000FFL
++#define CRTC1_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x00010000L
++//CRTC1_CRTC_V_UPDATE_INT_STATUS
++#define CRTC1_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0
++#define CRTC1_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8
++#define CRTC1_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x00000001L
++#define CRTC1_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x00000100L
++//CRTC1_CRTC_OVERSCAN_COLOR
++#define CRTC1_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0
++#define CRTC1_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa
++#define CRTC1_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14
++#define CRTC1_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x000003FFL
++#define CRTC1_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0x000FFC00L
++#define CRTC1_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3FF00000L
++//CRTC1_CRTC_OVERSCAN_COLOR_EXT
++#define CRTC1_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0
++#define CRTC1_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8
++#define CRTC1_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10
++#define CRTC1_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x00000003L
++#define CRTC1_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x00000300L
++#define CRTC1_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x00030000L
++//CRTC1_CRTC_BLANK_DATA_COLOR
++#define CRTC1_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0
++#define CRTC1_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa
++#define CRTC1_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14
++#define CRTC1_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL
++#define CRTC1_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L
++#define CRTC1_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L
++//CRTC1_CRTC_BLANK_DATA_COLOR_EXT
++#define CRTC1_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0
++#define CRTC1_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8
++#define CRTC1_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10
++#define CRTC1_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x00000003L
++#define CRTC1_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00000300L
++#define CRTC1_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x00030000L
++//CRTC1_CRTC_BLACK_COLOR
++#define CRTC1_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0
++#define CRTC1_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa
++#define CRTC1_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14
++#define CRTC1_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x000003FFL
++#define CRTC1_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0x000FFC00L
++#define CRTC1_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3FF00000L
++//CRTC1_CRTC_BLACK_COLOR_EXT
++#define CRTC1_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0
++#define CRTC1_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8
++#define CRTC1_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10
++#define CRTC1_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x00000003L
++#define CRTC1_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x00000300L
++#define CRTC1_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x00030000L
++//CRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION
++#define CRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0
++#define CRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10
++#define CRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00003FFFL
++#define CRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x3FFF0000L
++//CRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL
++#define CRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4
++#define CRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8
++#define CRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc
++#define CRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10
++#define CRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14
++#define CRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18
++#define CRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L
++#define CRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L
++#define CRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L
++#define CRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L
++#define CRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L
++#define CRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L
++//CRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION
++#define CRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0
++#define CRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00003FFFL
++//CRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL
++#define CRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8
++#define CRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc
++#define CRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10
++#define CRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14
++#define CRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18
++#define CRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L
++#define CRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L
++#define CRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L
++#define CRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L
++#define CRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L
++//CRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION
++#define CRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0
++#define CRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00003FFFL
++//CRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL
++#define CRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8
++#define CRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc
++#define CRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10
++#define CRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14
++#define CRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18
++#define CRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L
++#define CRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L
++#define CRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L
++#define CRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L
++#define CRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L
++//CRTC1_CRTC_CRC_CNTL
++#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0
++#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4
++#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8
++#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc
++#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
++#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14
++#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18
++#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC_EN_MASK 0x00000001L
++#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x00000010L
++#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x00000300L
++#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x00003000L
++#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
++#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x00700000L
++#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x07000000L
++//CRTC1_CRTC_CRC0_WINDOWA_X_CONTROL
++#define CRTC1_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0
++#define CRTC1_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10
++#define CRTC1_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x00003FFFL
++#define CRTC1_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3FFF0000L
++//CRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL
++#define CRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0
++#define CRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10
++#define CRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x00003FFFL
++#define CRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3FFF0000L
++//CRTC1_CRTC_CRC0_WINDOWB_X_CONTROL
++#define CRTC1_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0
++#define CRTC1_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10
++#define CRTC1_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x00003FFFL
++#define CRTC1_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3FFF0000L
++//CRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL
++#define CRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0
++#define CRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10
++#define CRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x00003FFFL
++#define CRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3FFF0000L
++//CRTC1_CRTC_CRC0_DATA_RG
++#define CRTC1_CRTC_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0
++#define CRTC1_CRTC_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10
++#define CRTC1_CRTC_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL
++#define CRTC1_CRTC_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L
++//CRTC1_CRTC_CRC0_DATA_B
++#define CRTC1_CRTC_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0
++#define CRTC1_CRTC_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL
++//CRTC1_CRTC_CRC1_WINDOWA_X_CONTROL
++#define CRTC1_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0
++#define CRTC1_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10
++#define CRTC1_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x00003FFFL
++#define CRTC1_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3FFF0000L
++//CRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL
++#define CRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0
++#define CRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10
++#define CRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x00003FFFL
++#define CRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3FFF0000L
++//CRTC1_CRTC_CRC1_WINDOWB_X_CONTROL
++#define CRTC1_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0
++#define CRTC1_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10
++#define CRTC1_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x00003FFFL
++#define CRTC1_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3FFF0000L
++//CRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL
++#define CRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0
++#define CRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10
++#define CRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x00003FFFL
++#define CRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3FFF0000L
++//CRTC1_CRTC_CRC1_DATA_RG
++#define CRTC1_CRTC_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0
++#define CRTC1_CRTC_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10
++#define CRTC1_CRTC_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL
++#define CRTC1_CRTC_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L
++//CRTC1_CRTC_CRC1_DATA_B
++#define CRTC1_CRTC_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0
++#define CRTC1_CRTC_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL
++//CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL
++#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE__SHIFT 0x0
++#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__SHIFT 0x3
++#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__SHIFT 0x4
++#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__SHIFT 0x5
++#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__SHIFT 0x8
++#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__SHIFT 0x9
++#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__SHIFT 0xc
++#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__SHIFT 0xd
++#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__SHIFT 0xe
++#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE__SHIFT 0x18
++#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE__SHIFT 0x1c
++#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE_MASK 0x00000003L
++#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_MASK 0x00000008L
++#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_MASK 0x00000010L
++#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_MASK 0x00000060L
++#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_MASK 0x00000100L
++#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_MASK 0x00000200L
++#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_MASK 0x00001000L
++#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_MASK 0x00002000L
++#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_MASK 0x00004000L
++#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE_MASK 0x07000000L
++#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE_MASK 0x70000000L
++//CRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START
++#define CRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X__SHIFT 0x0
++#define CRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y__SHIFT 0x10
++#define CRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X_MASK 0x00003FFFL
++#define CRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y_MASK 0x3FFF0000L
++//CRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END
++#define CRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X__SHIFT 0x0
++#define CRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y__SHIFT 0x10
++#define CRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X_MASK 0x00003FFFL
++#define CRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y_MASK 0x3FFF0000L
++//CRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL
++#define CRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__SHIFT 0x0
++#define CRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS__SHIFT 0x4
++#define CRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS__SHIFT 0x8
++#define CRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__SHIFT 0x10
++#define CRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__SHIFT 0x14
++#define CRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__SHIFT 0x1d
++#define CRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_MASK 0x00000001L
++#define CRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS_MASK 0x00000010L
++#define CRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS_MASK 0x00000100L
++#define CRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_MASK 0x00010000L
++#define CRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_MASK 0x00100000L
++#define CRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_MASK 0xE0000000L
++//CRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL
++#define CRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE__SHIFT 0x0
++#define CRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS__SHIFT 0x4
++#define CRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS__SHIFT 0x8
++#define CRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR__SHIFT 0x10
++#define CRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE__SHIFT 0x14
++#define CRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE_MASK 0x00000001L
++#define CRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS_MASK 0x00000010L
++#define CRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS_MASK 0x00000100L
++#define CRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR_MASK 0x00010000L
++#define CRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE_MASK 0x00100000L
++//CRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL
++#define CRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__SHIFT 0x0
++#define CRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS__SHIFT 0x4
++#define CRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS__SHIFT 0x8
++#define CRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__SHIFT 0x10
++#define CRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__SHIFT 0x14
++#define CRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_MASK 0x00000001L
++#define CRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS_MASK 0x00000010L
++#define CRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS_MASK 0x00000100L
++#define CRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_MASK 0x00010000L
++#define CRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_MASK 0x00100000L
++//CRTC1_CRTC_STATIC_SCREEN_CONTROL
++#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0
++#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10
++#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18
++#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19
++#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a
++#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b
++#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c
++#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e
++#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f
++#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL
++#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L
++#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x01000000L
++#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x02000000L
++#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x04000000L
++#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x08000000L
++#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000L
++#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L
++#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L
++//CRTC1_CRTC_3D_STRUCTURE_CONTROL
++#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0
++#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4
++#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8
++#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc
++#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10
++#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11
++#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12
++#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x00000001L
++#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x00000010L
++#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L
++#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L
++#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L
++#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L
++#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L
++//CRTC1_CRTC_GSL_VSYNC_GAP
++#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0
++#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8
++#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10
++#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11
++#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13
++#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14
++#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17
++#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18
++#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL
++#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L
++#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L
++#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x00060000L
++#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L
++#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L
++#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L
++#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xFF000000L
++//CRTC1_CRTC_GSL_WINDOW
++#define CRTC1_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0
++#define CRTC1_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10
++#define CRTC1_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x00003FFFL
++#define CRTC1_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x3FFF0000L
++//CRTC1_CRTC_GSL_CONTROL
++#define CRTC1_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0
++#define CRTC1_CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10
++#define CRTC1_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c
++#define CRTC1_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x00003FFFL
++#define CRTC1_CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x001F0000L
++#define CRTC1_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L
++//CRTC1_CRTC_RANGE_TIMING_INT_STATUS
++#define CRTC1_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0
++#define CRTC1_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4
++#define CRTC1_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8
++#define CRTC1_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc
++#define CRTC1_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10
++#define CRTC1_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L
++#define CRTC1_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L
++#define CRTC1_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L
++#define CRTC1_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L
++#define CRTC1_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L
++//CRTC1_CRTC_DRR_CONTROL
++#define CRTC1_CRTC_DRR_CONTROL__CRTC_XDMA_PREFETCH_DELAY__SHIFT 0x0
++#define CRTC1_CRTC_DRR_CONTROL__CRTC_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0xe
++#define CRTC1_CRTC_DRR_CONTROL__CRTC_SET_V_TOTAL_MIN_AUTO_DIS__SHIFT 0x1c
++#define CRTC1_CRTC_DRR_CONTROL__CRTC_DRR_MODE_DBUF_UPDATE_MODE__SHIFT 0x1d
++#define CRTC1_CRTC_DRR_CONTROL__CRTC_XDMA_PREFETCH_DELAY_MASK 0x00003FFFL
++#define CRTC1_CRTC_DRR_CONTROL__CRTC_V_TOTAL_LAST_USED_BY_DRR_MASK 0x0FFFC000L
++#define CRTC1_CRTC_DRR_CONTROL__CRTC_SET_V_TOTAL_MIN_AUTO_DIS_MASK 0x10000000L
++#define CRTC1_CRTC_DRR_CONTROL__CRTC_DRR_MODE_DBUF_UPDATE_MODE_MASK 0x60000000L
++
++
++// addressBlock: dce_dc_fmt1_dispdec
++//FMT1_FMT_CLAMP_COMPONENT_R
++#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0
++#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10
++#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL
++#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L
++//FMT1_FMT_CLAMP_COMPONENT_G
++#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0
++#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10
++#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL
++#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L
++//FMT1_FMT_CLAMP_COMPONENT_B
++#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0
++#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10
++#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL
++#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L
++//FMT1_FMT_DYNAMIC_EXP_CNTL
++#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0
++#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4
++#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L
++#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L
++//FMT1_FMT_CONTROL
++#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0
++#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT 0x4
++#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8
++#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc
++#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10
++#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12
++#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14
++#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15
++#define FMT1_FMT_CONTROL__FMT_SRC_SELECT__SHIFT 0x18
++#define FMT1_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED__SHIFT 0x1e
++#define FMT1_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_CLEAR__SHIFT 0x1f
++#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L
++#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK 0x00000010L
++#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L
++#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L
++#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L
++#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L
++#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L
++#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L
++#define FMT1_FMT_CONTROL__FMT_SRC_SELECT_MASK 0x07000000L
++#define FMT1_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_MASK 0x40000000L
++#define FMT1_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_CLEAR_MASK 0x80000000L
++//FMT1_FMT_BIT_DEPTH_CONTROL
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L
++//FMT1_FMT_DITHER_RAND_R_SEED
++#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0
++#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10
++#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL
++#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L
++//FMT1_FMT_DITHER_RAND_G_SEED
++#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0
++#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10
++#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL
++#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L
++//FMT1_FMT_DITHER_RAND_B_SEED
++#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0
++#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10
++#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL
++#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L
++//FMT1_FMT_CLAMP_CNTL
++#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0
++#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10
++#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L
++#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L
++//FMT1_FMT_CRC_CNTL
++#define FMT1_FMT_CRC_CNTL__FMT_CRC_EN__SHIFT 0x0
++#define FMT1_FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN__SHIFT 0x1
++#define FMT1_FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT 0x4
++#define FMT1_FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING__SHIFT 0x5
++#define FMT1_FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN__SHIFT 0x6
++#define FMT1_FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB__SHIFT 0x8
++#define FMT1_FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE__SHIFT 0x9
++#define FMT1_FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT 0xc
++#define FMT1_FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
++#define FMT1_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT 0x14
++#define FMT1_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT 0x18
++#define FMT1_FMT_CRC_CNTL__FMT_CRC_EN_MASK 0x00000001L
++#define FMT1_FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN_MASK 0x00000002L
++#define FMT1_FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK 0x00000010L
++#define FMT1_FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING_MASK 0x00000020L
++#define FMT1_FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN_MASK 0x00000040L
++#define FMT1_FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB_MASK 0x00000100L
++#define FMT1_FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE_MASK 0x00000200L
++#define FMT1_FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK 0x00003000L
++#define FMT1_FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
++#define FMT1_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK 0x00100000L
++#define FMT1_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK 0x01000000L
++//FMT1_FMT_CRC_SIG_RED_GREEN_MASK
++#define FMT1_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT 0x0
++#define FMT1_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT 0x10
++#define FMT1_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK 0x0000FFFFL
++#define FMT1_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L
++//FMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK
++#define FMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT 0x0
++#define FMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT 0x10
++#define FMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL
++#define FMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L
++//FMT1_FMT_CRC_SIG_RED_GREEN
++#define FMT1_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT 0x0
++#define FMT1_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT 0x10
++#define FMT1_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK 0x0000FFFFL
++#define FMT1_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK 0xFFFF0000L
++//FMT1_FMT_CRC_SIG_BLUE_CONTROL
++#define FMT1_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT 0x0
++#define FMT1_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT 0x10
++#define FMT1_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK 0x0000FFFFL
++#define FMT1_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK 0xFFFF0000L
++//FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL
++#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0
++#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL
++//FMT1_FMT_420_HBLANK_EARLY_START
++#define FMT1_FMT_420_HBLANK_EARLY_START__FMT_420_HBLANK_EARLY_START__SHIFT 0x0
++#define FMT1_FMT_420_HBLANK_EARLY_START__FMT_420_HBLANK_EARLY_START_MASK 0x00000FFFL
++
++
++// addressBlock: dce_dc_dcp2_dispdec
++//DCP2_GRPH_ENABLE
++#define DCP2_GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0
++#define DCP2_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL__SHIFT 0x1
++#define DCP2_GRPH_ENABLE__GRPH_ENABLE_MASK 0x00000001L
++#define DCP2_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL_MASK 0x00000002L
++//DCP2_GRPH_CONTROL
++#define DCP2_GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0
++#define DCP2_GRPH_CONTROL__GRPH_SE_ENABLE__SHIFT 0x2
++#define DCP2_GRPH_CONTROL__GRPH_Z__SHIFT 0x4
++#define DCP2_GRPH_CONTROL__GRPH_DIM_TYPE__SHIFT 0x6
++#define DCP2_GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8
++#define DCP2_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0xc
++#define DCP2_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10
++#define DCP2_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11
++#define DCP2_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES__SHIFT 0x12
++#define DCP2_GRPH_CONTROL__GRPH_SW_MODE__SHIFT 0x14
++#define DCP2_GRPH_CONTROL__GRPH_NUM_PIPES__SHIFT 0x1c
++#define DCP2_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f
++#define DCP2_GRPH_CONTROL__GRPH_DEPTH_MASK 0x00000003L
++#define DCP2_GRPH_CONTROL__GRPH_SE_ENABLE_MASK 0x00000004L
++#define DCP2_GRPH_CONTROL__GRPH_Z_MASK 0x00000030L
++#define DCP2_GRPH_CONTROL__GRPH_DIM_TYPE_MASK 0x000000C0L
++#define DCP2_GRPH_CONTROL__GRPH_FORMAT_MASK 0x00000700L
++#define DCP2_GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0x00007000L
++#define DCP2_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x00010000L
++#define DCP2_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x00020000L
++#define DCP2_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES_MASK 0x000C0000L
++#define DCP2_GRPH_CONTROL__GRPH_SW_MODE_MASK 0x01F00000L
++#define DCP2_GRPH_CONTROL__GRPH_NUM_PIPES_MASK 0x70000000L
++#define DCP2_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000L
++//DCP2_GRPH_LUT_10BIT_BYPASS
++#define DCP2_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT 0x8
++#define DCP2_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x10
++#define DCP2_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK 0x00000100L
++#define DCP2_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x00010000L
++//DCP2_GRPH_SWAP_CNTL
++#define DCP2_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0
++#define DCP2_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4
++#define DCP2_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6
++#define DCP2_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8
++#define DCP2_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT 0xa
++#define DCP2_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x00000003L
++#define DCP2_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x00000030L
++#define DCP2_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0x000000C0L
++#define DCP2_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x00000300L
++#define DCP2_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK 0x00000C00L
++//DCP2_GRPH_PRIMARY_SURFACE_ADDRESS
++#define DCP2_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT 0x0
++#define DCP2_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT 0x8
++#define DCP2_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK 0x00000001L
++#define DCP2_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
++//DCP2_GRPH_SECONDARY_SURFACE_ADDRESS
++#define DCP2_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT 0x0
++#define DCP2_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8
++#define DCP2_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK 0x00000001L
++#define DCP2_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
++//DCP2_GRPH_PITCH
++#define DCP2_GRPH_PITCH__GRPH_PITCH__SHIFT 0x0
++#define DCP2_GRPH_PITCH__GRPH_PITCH_MASK 0x00007FFFL
++//DCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
++#define DCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define DCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
++//DCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
++#define DCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define DCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
++//DCP2_GRPH_SURFACE_OFFSET_X
++#define DCP2_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT 0x0
++#define DCP2_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK 0x00003FFFL
++//DCP2_GRPH_SURFACE_OFFSET_Y
++#define DCP2_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT 0x0
++#define DCP2_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK 0x00003FFFL
++//DCP2_GRPH_X_START
++#define DCP2_GRPH_X_START__GRPH_X_START__SHIFT 0x0
++#define DCP2_GRPH_X_START__GRPH_X_START_MASK 0x00003FFFL
++//DCP2_GRPH_Y_START
++#define DCP2_GRPH_Y_START__GRPH_Y_START__SHIFT 0x0
++#define DCP2_GRPH_Y_START__GRPH_Y_START_MASK 0x00003FFFL
++//DCP2_GRPH_X_END
++#define DCP2_GRPH_X_END__GRPH_X_END__SHIFT 0x0
++#define DCP2_GRPH_X_END__GRPH_X_END_MASK 0x00007FFFL
++//DCP2_GRPH_Y_END
++#define DCP2_GRPH_Y_END__GRPH_Y_END__SHIFT 0x0
++#define DCP2_GRPH_Y_END__GRPH_Y_END_MASK 0x00007FFFL
++//DCP2_INPUT_GAMMA_CONTROL
++#define DCP2_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x0
++#define DCP2_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK 0x00000001L
++//DCP2_GRPH_UPDATE
++#define DCP2_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0
++#define DCP2_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1
++#define DCP2_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2
++#define DCP2_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3
++#define DCP2_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR__SHIFT 0x8
++#define DCP2_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE__SHIFT 0x9
++#define DCP2_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE__SHIFT 0xa
++#define DCP2_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10
++#define DCP2_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14
++#define DCP2_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
++#define DCP2_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c
++#define DCP2_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x00000001L
++#define DCP2_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x00000002L
++#define DCP2_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x00000004L
++#define DCP2_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x00000008L
++#define DCP2_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR_MASK 0x00000100L
++#define DCP2_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE_MASK 0x00000200L
++#define DCP2_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE_MASK 0x00000400L
++#define DCP2_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x00010000L
++#define DCP2_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x00100000L
++#define DCP2_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
++#define DCP2_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000L
++//DCP2_GRPH_FLIP_CONTROL
++#define DCP2_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT 0x0
++#define DCP2_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN__SHIFT 0x1
++#define DCP2_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN__SHIFT 0x4
++#define DCP2_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT 0x5
++#define DCP2_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK 0x00000001L
++#define DCP2_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN_MASK 0x00000002L
++#define DCP2_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN_MASK 0x00000010L
++#define DCP2_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK 0x00000020L
++//DCP2_GRPH_SURFACE_ADDRESS_INUSE
++#define DCP2_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT 0x8
++#define DCP2_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK 0xFFFFFF00L
++//DCP2_GRPH_DFQ_CONTROL
++#define DCP2_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x0
++#define DCP2_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x4
++#define DCP2_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8
++#define DCP2_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x00000001L
++#define DCP2_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x00000070L
++#define DCP2_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x00000700L
++//DCP2_GRPH_DFQ_STATUS
++#define DCP2_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x0
++#define DCP2_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4
++#define DCP2_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x8
++#define DCP2_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x9
++#define DCP2_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0x0000000FL
++#define DCP2_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0x000000F0L
++#define DCP2_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x00000100L
++#define DCP2_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x00000200L
++//DCP2_GRPH_INTERRUPT_STATUS
++#define DCP2_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0
++#define DCP2_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8
++#define DCP2_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x00000001L
++#define DCP2_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x00000100L
++//DCP2_GRPH_INTERRUPT_CONTROL
++#define DCP2_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0
++#define DCP2_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8
++#define DCP2_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x00000001L
++#define DCP2_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x00000100L
++//DCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE
++#define DCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0
++#define DCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK 0x000000FFL
++//DCP2_GRPH_COMPRESS_SURFACE_ADDRESS
++#define DCP2_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT 0x8
++#define DCP2_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK 0xFFFFFF00L
++//DCP2_GRPH_COMPRESS_PITCH
++#define DCP2_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT 0x6
++#define DCP2_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK 0x0001FFC0L
++//DCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH
++#define DCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define DCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
++//DCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT
++#define DCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__SHIFT 0x0
++#define DCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_MASK 0x000000FFL
++//DCP2_PRESCALE_GRPH_CONTROL
++#define DCP2_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT 0x0
++#define DCP2_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT 0x1
++#define DCP2_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x2
++#define DCP2_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT 0x3
++#define DCP2_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT 0x4
++#define DCP2_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK 0x00000001L
++#define DCP2_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x00000002L
++#define DCP2_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK 0x00000004L
++#define DCP2_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK 0x00000008L
++#define DCP2_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK 0x00000010L
++//DCP2_PRESCALE_VALUES_GRPH_R
++#define DCP2_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT 0x0
++#define DCP2_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT 0x10
++#define DCP2_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK 0x0000FFFFL
++#define DCP2_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK 0xFFFF0000L
++//DCP2_PRESCALE_VALUES_GRPH_G
++#define DCP2_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT 0x0
++#define DCP2_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT 0x10
++#define DCP2_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK 0x0000FFFFL
++#define DCP2_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK 0xFFFF0000L
++//DCP2_PRESCALE_VALUES_GRPH_B
++#define DCP2_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT 0x0
++#define DCP2_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT 0x10
++#define DCP2_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK 0x0000FFFFL
++#define DCP2_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK 0xFFFF0000L
++//DCP2_INPUT_CSC_CONTROL
++#define DCP2_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT 0x0
++#define DCP2_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK 0x00000003L
++//DCP2_INPUT_CSC_C11_C12
++#define DCP2_INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT 0x0
++#define DCP2_INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT 0x10
++#define DCP2_INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK 0x0000FFFFL
++#define DCP2_INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK 0xFFFF0000L
++//DCP2_INPUT_CSC_C13_C14
++#define DCP2_INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT 0x0
++#define DCP2_INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT 0x10
++#define DCP2_INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK 0x0000FFFFL
++#define DCP2_INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK 0xFFFF0000L
++//DCP2_INPUT_CSC_C21_C22
++#define DCP2_INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT 0x0
++#define DCP2_INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT 0x10
++#define DCP2_INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK 0x0000FFFFL
++#define DCP2_INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK 0xFFFF0000L
++//DCP2_INPUT_CSC_C23_C24
++#define DCP2_INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT 0x0
++#define DCP2_INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT 0x10
++#define DCP2_INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK 0x0000FFFFL
++#define DCP2_INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK 0xFFFF0000L
++//DCP2_INPUT_CSC_C31_C32
++#define DCP2_INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT 0x0
++#define DCP2_INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT 0x10
++#define DCP2_INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK 0x0000FFFFL
++#define DCP2_INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK 0xFFFF0000L
++//DCP2_INPUT_CSC_C33_C34
++#define DCP2_INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT 0x0
++#define DCP2_INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT 0x10
++#define DCP2_INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK 0x0000FFFFL
++#define DCP2_INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK 0xFFFF0000L
++//DCP2_OUTPUT_CSC_CONTROL
++#define DCP2_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT 0x0
++#define DCP2_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK 0x00000007L
++//DCP2_OUTPUT_CSC_C11_C12
++#define DCP2_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT 0x0
++#define DCP2_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT 0x10
++#define DCP2_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK 0x0000FFFFL
++#define DCP2_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK 0xFFFF0000L
++//DCP2_OUTPUT_CSC_C13_C14
++#define DCP2_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT 0x0
++#define DCP2_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT 0x10
++#define DCP2_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK 0x0000FFFFL
++#define DCP2_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK 0xFFFF0000L
++//DCP2_OUTPUT_CSC_C21_C22
++#define DCP2_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT 0x0
++#define DCP2_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT 0x10
++#define DCP2_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK 0x0000FFFFL
++#define DCP2_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK 0xFFFF0000L
++//DCP2_OUTPUT_CSC_C23_C24
++#define DCP2_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT 0x0
++#define DCP2_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT 0x10
++#define DCP2_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK 0x0000FFFFL
++#define DCP2_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK 0xFFFF0000L
++//DCP2_OUTPUT_CSC_C31_C32
++#define DCP2_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT 0x0
++#define DCP2_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT 0x10
++#define DCP2_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK 0x0000FFFFL
++#define DCP2_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK 0xFFFF0000L
++//DCP2_OUTPUT_CSC_C33_C34
++#define DCP2_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT 0x0
++#define DCP2_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT 0x10
++#define DCP2_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK 0x0000FFFFL
++#define DCP2_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK 0xFFFF0000L
++//DCP2_COMM_MATRIXA_TRANS_C11_C12
++#define DCP2_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT 0x0
++#define DCP2_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT 0x10
++#define DCP2_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK 0x0000FFFFL
++#define DCP2_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK 0xFFFF0000L
++//DCP2_COMM_MATRIXA_TRANS_C13_C14
++#define DCP2_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT 0x0
++#define DCP2_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT 0x10
++#define DCP2_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK 0x0000FFFFL
++#define DCP2_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK 0xFFFF0000L
++//DCP2_COMM_MATRIXA_TRANS_C21_C22
++#define DCP2_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT 0x0
++#define DCP2_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT 0x10
++#define DCP2_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK 0x0000FFFFL
++#define DCP2_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK 0xFFFF0000L
++//DCP2_COMM_MATRIXA_TRANS_C23_C24
++#define DCP2_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT 0x0
++#define DCP2_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT 0x10
++#define DCP2_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK 0x0000FFFFL
++#define DCP2_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK 0xFFFF0000L
++//DCP2_COMM_MATRIXA_TRANS_C31_C32
++#define DCP2_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT 0x0
++#define DCP2_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT 0x10
++#define DCP2_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK 0x0000FFFFL
++#define DCP2_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK 0xFFFF0000L
++//DCP2_COMM_MATRIXA_TRANS_C33_C34
++#define DCP2_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT 0x0
++#define DCP2_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT 0x10
++#define DCP2_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK 0x0000FFFFL
++#define DCP2_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK 0xFFFF0000L
++//DCP2_COMM_MATRIXB_TRANS_C11_C12
++#define DCP2_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT 0x0
++#define DCP2_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT 0x10
++#define DCP2_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK 0x0000FFFFL
++#define DCP2_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK 0xFFFF0000L
++//DCP2_COMM_MATRIXB_TRANS_C13_C14
++#define DCP2_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT 0x0
++#define DCP2_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT 0x10
++#define DCP2_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK 0x0000FFFFL
++#define DCP2_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK 0xFFFF0000L
++//DCP2_COMM_MATRIXB_TRANS_C21_C22
++#define DCP2_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT 0x0
++#define DCP2_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT 0x10
++#define DCP2_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK 0x0000FFFFL
++#define DCP2_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK 0xFFFF0000L
++//DCP2_COMM_MATRIXB_TRANS_C23_C24
++#define DCP2_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT 0x0
++#define DCP2_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT 0x10
++#define DCP2_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK 0x0000FFFFL
++#define DCP2_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK 0xFFFF0000L
++//DCP2_COMM_MATRIXB_TRANS_C31_C32
++#define DCP2_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT 0x0
++#define DCP2_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT 0x10
++#define DCP2_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK 0x0000FFFFL
++#define DCP2_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK 0xFFFF0000L
++//DCP2_COMM_MATRIXB_TRANS_C33_C34
++#define DCP2_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT 0x0
++#define DCP2_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT 0x10
++#define DCP2_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK 0x0000FFFFL
++#define DCP2_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK 0xFFFF0000L
++//DCP2_DENORM_CONTROL
++#define DCP2_DENORM_CONTROL__DENORM_MODE__SHIFT 0x0
++#define DCP2_DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT 0x4
++#define DCP2_DENORM_CONTROL__DENORM_MODE_MASK 0x00000007L
++#define DCP2_DENORM_CONTROL__DENORM_14BIT_OUT_MASK 0x00000010L
++//DCP2_OUT_ROUND_CONTROL
++#define DCP2_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT 0x0
++#define DCP2_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK 0x0000000FL
++//DCP2_OUT_CLAMP_CONTROL_R_CR
++#define DCP2_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT 0x0
++#define DCP2_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT 0x10
++#define DCP2_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK 0x00003FFFL
++#define DCP2_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK 0x3FFF0000L
++//DCP2_OUT_CLAMP_CONTROL_G_Y
++#define DCP2_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT 0x0
++#define DCP2_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT 0x10
++#define DCP2_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK 0x00003FFFL
++#define DCP2_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK 0x3FFF0000L
++//DCP2_OUT_CLAMP_CONTROL_B_CB
++#define DCP2_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT 0x0
++#define DCP2_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT 0x10
++#define DCP2_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK 0x00003FFFL
++#define DCP2_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK 0x3FFF0000L
++//DCP2_KEY_CONTROL
++#define DCP2_KEY_CONTROL__KEY_MODE__SHIFT 0x1
++#define DCP2_KEY_CONTROL__KEY_MODE_MASK 0x00000006L
++//DCP2_KEY_RANGE_ALPHA
++#define DCP2_KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT 0x0
++#define DCP2_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT 0x10
++#define DCP2_KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK 0x0000FFFFL
++#define DCP2_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK 0xFFFF0000L
++//DCP2_KEY_RANGE_RED
++#define DCP2_KEY_RANGE_RED__KEY_RED_LOW__SHIFT 0x0
++#define DCP2_KEY_RANGE_RED__KEY_RED_HIGH__SHIFT 0x10
++#define DCP2_KEY_RANGE_RED__KEY_RED_LOW_MASK 0x0000FFFFL
++#define DCP2_KEY_RANGE_RED__KEY_RED_HIGH_MASK 0xFFFF0000L
++//DCP2_KEY_RANGE_GREEN
++#define DCP2_KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT 0x0
++#define DCP2_KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT 0x10
++#define DCP2_KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK 0x0000FFFFL
++#define DCP2_KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK 0xFFFF0000L
++//DCP2_KEY_RANGE_BLUE
++#define DCP2_KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT 0x0
++#define DCP2_KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT 0x10
++#define DCP2_KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK 0x0000FFFFL
++#define DCP2_KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK 0xFFFF0000L
++//DCP2_DEGAMMA_CONTROL
++#define DCP2_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x0
++#define DCP2_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT 0x8
++#define DCP2_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0xc
++#define DCP2_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x00000003L
++#define DCP2_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK 0x00000300L
++#define DCP2_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK 0x00003000L
++//DCP2_GAMUT_REMAP_CONTROL
++#define DCP2_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT 0x0
++#define DCP2_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK 0x00000003L
++//DCP2_GAMUT_REMAP_C11_C12
++#define DCP2_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT 0x0
++#define DCP2_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT 0x10
++#define DCP2_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK 0x0000FFFFL
++#define DCP2_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK 0xFFFF0000L
++//DCP2_GAMUT_REMAP_C13_C14
++#define DCP2_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT 0x0
++#define DCP2_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT 0x10
++#define DCP2_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK 0x0000FFFFL
++#define DCP2_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK 0xFFFF0000L
++//DCP2_GAMUT_REMAP_C21_C22
++#define DCP2_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT 0x0
++#define DCP2_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT 0x10
++#define DCP2_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK 0x0000FFFFL
++#define DCP2_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK 0xFFFF0000L
++//DCP2_GAMUT_REMAP_C23_C24
++#define DCP2_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT 0x0
++#define DCP2_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT 0x10
++#define DCP2_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK 0x0000FFFFL
++#define DCP2_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK 0xFFFF0000L
++//DCP2_GAMUT_REMAP_C31_C32
++#define DCP2_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT 0x0
++#define DCP2_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT 0x10
++#define DCP2_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK 0x0000FFFFL
++#define DCP2_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK 0xFFFF0000L
++//DCP2_GAMUT_REMAP_C33_C34
++#define DCP2_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT 0x0
++#define DCP2_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT 0x10
++#define DCP2_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK 0x0000FFFFL
++#define DCP2_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK 0xFFFF0000L
++//DCP2_DCP_SPATIAL_DITHER_CNTL
++#define DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT 0x0
++#define DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT 0x4
++#define DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT 0x6
++#define DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT 0x8
++#define DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT 0x9
++#define DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT 0xa
++#define DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK 0x00000001L
++#define DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK 0x00000030L
++#define DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK 0x000000C0L
++#define DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK 0x00000100L
++#define DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK 0x00000200L
++#define DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK 0x00000400L
++//DCP2_DCP_RANDOM_SEEDS
++#define DCP2_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT 0x0
++#define DCP2_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT 0x8
++#define DCP2_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT 0x10
++#define DCP2_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK 0x000000FFL
++#define DCP2_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK 0x0000FF00L
++#define DCP2_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK 0x00FF0000L
++//DCP2_DCP_FP_CONVERTED_FIELD
++#define DCP2_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT 0x0
++#define DCP2_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14
++#define DCP2_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK 0x0003FFFFL
++#define DCP2_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK 0x07F00000L
++//DCP2_CUR_CONTROL
++#define DCP2_CUR_CONTROL__CURSOR_EN__SHIFT 0x0
++#define DCP2_CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT 0x4
++#define DCP2_CUR_CONTROL__CURSOR_MODE__SHIFT 0x8
++#define DCP2_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM__SHIFT 0xb
++#define DCP2_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION__SHIFT 0xc
++#define DCP2_CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x10
++#define DCP2_CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT 0x14
++#define DCP2_CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT 0x18
++#define DCP2_CUR_CONTROL__CURSOR_EN_MASK 0x00000001L
++#define DCP2_CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK 0x00000010L
++#define DCP2_CUR_CONTROL__CURSOR_MODE_MASK 0x00000300L
++#define DCP2_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM_MASK 0x00000800L
++#define DCP2_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION_MASK 0x0000F000L
++#define DCP2_CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00010000L
++#define DCP2_CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK 0x00100000L
++#define DCP2_CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK 0x07000000L
++//DCP2_CUR_SURFACE_ADDRESS
++#define DCP2_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0
++#define DCP2_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
++//DCP2_CUR_SIZE
++#define DCP2_CUR_SIZE__CURSOR_HEIGHT__SHIFT 0x0
++#define DCP2_CUR_SIZE__CURSOR_WIDTH__SHIFT 0x10
++#define DCP2_CUR_SIZE__CURSOR_HEIGHT_MASK 0x0000007FL
++#define DCP2_CUR_SIZE__CURSOR_WIDTH_MASK 0x007F0000L
++//DCP2_CUR_SURFACE_ADDRESS_HIGH
++#define DCP2_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define DCP2_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
++//DCP2_CUR_POSITION
++#define DCP2_CUR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0
++#define DCP2_CUR_POSITION__CURSOR_X_POSITION__SHIFT 0x10
++#define DCP2_CUR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL
++#define DCP2_CUR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L
++//DCP2_CUR_HOT_SPOT
++#define DCP2_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0
++#define DCP2_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10
++#define DCP2_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x0000007FL
++#define DCP2_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x007F0000L
++//DCP2_CUR_COLOR1
++#define DCP2_CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT 0x0
++#define DCP2_CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT 0x8
++#define DCP2_CUR_COLOR1__CUR_COLOR1_RED__SHIFT 0x10
++#define DCP2_CUR_COLOR1__CUR_COLOR1_BLUE_MASK 0x000000FFL
++#define DCP2_CUR_COLOR1__CUR_COLOR1_GREEN_MASK 0x0000FF00L
++#define DCP2_CUR_COLOR1__CUR_COLOR1_RED_MASK 0x00FF0000L
++//DCP2_CUR_COLOR2
++#define DCP2_CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT 0x0
++#define DCP2_CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT 0x8
++#define DCP2_CUR_COLOR2__CUR_COLOR2_RED__SHIFT 0x10
++#define DCP2_CUR_COLOR2__CUR_COLOR2_BLUE_MASK 0x000000FFL
++#define DCP2_CUR_COLOR2__CUR_COLOR2_GREEN_MASK 0x0000FF00L
++#define DCP2_CUR_COLOR2__CUR_COLOR2_RED_MASK 0x00FF0000L
++//DCP2_CUR_UPDATE
++#define DCP2_CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT 0x0
++#define DCP2_CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT 0x1
++#define DCP2_CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT 0x10
++#define DCP2_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
++#define DCP2_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE__SHIFT 0x19
++#define DCP2_CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK 0x00000001L
++#define DCP2_CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x00000002L
++#define DCP2_CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK 0x00010000L
++#define DCP2_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
++#define DCP2_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE_MASK 0x06000000L
++//DCP2_CUR_REQUEST_FILTER_CNTL
++#define DCP2_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT 0x0
++#define DCP2_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK 0x00000001L
++//DCP2_CUR_STEREO_CONTROL
++#define DCP2_CUR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0
++#define DCP2_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4
++#define DCP2_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x10
++#define DCP2_CUR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L
++#define DCP2_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x00003FF0L
++#define DCP2_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0x03FF0000L
++//DCP2_DC_LUT_RW_MODE
++#define DCP2_DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT 0x0
++#define DCP2_DC_LUT_RW_MODE__DC_LUT_ERROR__SHIFT 0x10
++#define DCP2_DC_LUT_RW_MODE__DC_LUT_ERROR_RST__SHIFT 0x11
++#define DCP2_DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK 0x00000001L
++#define DCP2_DC_LUT_RW_MODE__DC_LUT_ERROR_MASK 0x00010000L
++#define DCP2_DC_LUT_RW_MODE__DC_LUT_ERROR_RST_MASK 0x00020000L
++//DCP2_DC_LUT_RW_INDEX
++#define DCP2_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT 0x0
++#define DCP2_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK 0x000000FFL
++//DCP2_DC_LUT_SEQ_COLOR
++#define DCP2_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT 0x0
++#define DCP2_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK 0x0000FFFFL
++//DCP2_DC_LUT_PWL_DATA
++#define DCP2_DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT 0x0
++#define DCP2_DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT 0x10
++#define DCP2_DC_LUT_PWL_DATA__DC_LUT_BASE_MASK 0x0000FFFFL
++#define DCP2_DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK 0xFFFF0000L
++//DCP2_DC_LUT_30_COLOR
++#define DCP2_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT 0x0
++#define DCP2_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT 0xa
++#define DCP2_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT 0x14
++#define DCP2_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK 0x000003FFL
++#define DCP2_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK 0x000FFC00L
++#define DCP2_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK 0x3FF00000L
++//DCP2_DC_LUT_VGA_ACCESS_ENABLE
++#define DCP2_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT 0x0
++#define DCP2_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK 0x00000001L
++//DCP2_DC_LUT_WRITE_EN_MASK
++#define DCP2_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT 0x0
++#define DCP2_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK 0x00000007L
++//DCP2_DC_LUT_AUTOFILL
++#define DCP2_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT 0x0
++#define DCP2_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT 0x1
++#define DCP2_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK 0x00000001L
++#define DCP2_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x00000002L
++//DCP2_DC_LUT_CONTROL
++#define DCP2_DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT 0x0
++#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT 0x4
++#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT 0x5
++#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT 0x6
++#define DCP2_DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT 0x8
++#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT 0xc
++#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT 0xd
++#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT 0xe
++#define DCP2_DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT 0x10
++#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT 0x14
++#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT 0x15
++#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT 0x16
++#define DCP2_DC_LUT_CONTROL__DC_LUT_INC_B_MASK 0x0000000FL
++#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK 0x00000010L
++#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK 0x00000020L
++#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK 0x000000C0L
++#define DCP2_DC_LUT_CONTROL__DC_LUT_INC_G_MASK 0x00000F00L
++#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK 0x00001000L
++#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK 0x00002000L
++#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK 0x0000C000L
++#define DCP2_DC_LUT_CONTROL__DC_LUT_INC_R_MASK 0x000F0000L
++#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK 0x00100000L
++#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK 0x00200000L
++#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK 0x00C00000L
++//DCP2_DC_LUT_BLACK_OFFSET_BLUE
++#define DCP2_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0
++#define DCP2_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK 0x0000FFFFL
++//DCP2_DC_LUT_BLACK_OFFSET_GREEN
++#define DCP2_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0
++#define DCP2_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK 0x0000FFFFL
++//DCP2_DC_LUT_BLACK_OFFSET_RED
++#define DCP2_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT 0x0
++#define DCP2_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK 0x0000FFFFL
++//DCP2_DC_LUT_WHITE_OFFSET_BLUE
++#define DCP2_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT 0x0
++#define DCP2_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK 0x0000FFFFL
++//DCP2_DC_LUT_WHITE_OFFSET_GREEN
++#define DCP2_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT 0x0
++#define DCP2_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK 0x0000FFFFL
++//DCP2_DC_LUT_WHITE_OFFSET_RED
++#define DCP2_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT 0x0
++#define DCP2_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK 0x0000FFFFL
++//DCP2_DCP_CRC_CONTROL
++#define DCP2_DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT 0x0
++#define DCP2_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x2
++#define DCP2_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT 0x8
++#define DCP2_DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK 0x00000001L
++#define DCP2_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK 0x0000001CL
++#define DCP2_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK 0x00000300L
++//DCP2_DCP_CRC_MASK
++#define DCP2_DCP_CRC_MASK__DCP_CRC_MASK__SHIFT 0x0
++#define DCP2_DCP_CRC_MASK__DCP_CRC_MASK_MASK 0xFFFFFFFFL
++//DCP2_DCP_CRC_CURRENT
++#define DCP2_DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT 0x0
++#define DCP2_DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK 0xFFFFFFFFL
++//DCP2_DVMM_PTE_CONTROL
++#define DCP2_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT 0x0
++#define DCP2_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT 0x1
++#define DCP2_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT 0x5
++#define DCP2_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT 0x9
++#define DCP2_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT 0x14
++#define DCP2_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT 0x15
++#define DCP2_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK 0x00000001L
++#define DCP2_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK 0x0000001EL
++#define DCP2_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK 0x000001E0L
++#define DCP2_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK 0x0007FE00L
++#define DCP2_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK 0x00100000L
++#define DCP2_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK 0x00200000L
++//DCP2_DCP_CRC_LAST
++#define DCP2_DCP_CRC_LAST__DCP_CRC_LAST__SHIFT 0x0
++#define DCP2_DCP_CRC_LAST__DCP_CRC_LAST_MASK 0xFFFFFFFFL
++//DCP2_DVMM_PTE_ARB_CONTROL
++#define DCP2_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT 0x0
++#define DCP2_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT 0x8
++#define DCP2_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK 0x0000003FL
++#define DCP2_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK 0x0000FF00L
++//DCP2_GRPH_FLIP_RATE_CNTL
++#define DCP2_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT 0x0
++#define DCP2_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT 0x3
++#define DCP2_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK 0x00000007L
++#define DCP2_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK 0x00000008L
++//DCP2_DCP_GSL_CONTROL
++#define DCP2_DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT 0x0
++#define DCP2_DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT 0x1
++#define DCP2_DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x2
++#define DCP2_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT 0x4
++#define DCP2_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT 0x14
++#define DCP2_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP__SHIFT 0x15
++#define DCP2_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN__SHIFT 0x17
++#define DCP2_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT 0x18
++#define DCP2_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC__SHIFT 0x1a
++#define DCP2_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT 0x1b
++#define DCP2_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT 0x1c
++#define DCP2_DCP_GSL_CONTROL__DCP_GSL0_EN_MASK 0x00000001L
++#define DCP2_DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x00000002L
++#define DCP2_DCP_GSL_CONTROL__DCP_GSL2_EN_MASK 0x00000004L
++#define DCP2_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK 0x000FFFF0L
++#define DCP2_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK 0x00100000L
++#define DCP2_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_MASK 0x00600000L
++#define DCP2_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_MASK 0x00800000L
++#define DCP2_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK 0x03000000L
++#define DCP2_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_MASK 0x04000000L
++#define DCP2_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK 0x08000000L
++#define DCP2_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK 0xF0000000L
++//DCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK
++#define DCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT 0x0
++#define DCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT 0x4
++#define DCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK 0x0000000FL
++#define DCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK 0x000001F0L
++//DCP2_GRPH_STEREOSYNC_FLIP
++#define DCP2_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0
++#define DCP2_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x8
++#define DCP2_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10
++#define DCP2_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11
++#define DCP2_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c
++#define DCP2_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x00000001L
++#define DCP2_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x00000300L
++#define DCP2_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x00010000L
++#define DCP2_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x00020000L
++#define DCP2_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000L
++//DCP2_HW_ROTATION
++#define DCP2_HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT 0x0
++#define DCP2_HW_ROTATION__GRPH_ROTATION_ANGLE_MASK 0x00000007L
++//DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL
++#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT 0x0
++#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT 0x1
++#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT 0x4
++#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK 0x00000001L
++#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK 0x00000002L
++#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK 0x0001FFF0L
++//DCP2_REGAMMA_CONTROL
++#define DCP2_REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT 0x0
++#define DCP2_REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK 0x00000007L
++//DCP2_REGAMMA_LUT_INDEX
++#define DCP2_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x0
++#define DCP2_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK 0x000001FFL
++//DCP2_REGAMMA_LUT_DATA
++#define DCP2_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT 0x0
++#define DCP2_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK 0x0007FFFFL
++//DCP2_REGAMMA_LUT_WRITE_EN_MASK
++#define DCP2_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x0
++#define DCP2_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x00000007L
++//DCP2_REGAMMA_CNTLA_START_CNTL
++#define DCP2_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x0
++#define DCP2_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14
++#define DCP2_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK 0x0003FFFFL
++#define DCP2_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
++//DCP2_REGAMMA_CNTLA_SLOPE_CNTL
++#define DCP2_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
++#define DCP2_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
++//DCP2_REGAMMA_CNTLA_END_CNTL1
++#define DCP2_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x0
++#define DCP2_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK 0x0000FFFFL
++//DCP2_REGAMMA_CNTLA_END_CNTL2
++#define DCP2_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0
++#define DCP2_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10
++#define DCP2_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
++#define DCP2_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xFFFF0000L
++//DCP2_REGAMMA_CNTLA_REGION_0_1
++#define DCP2_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
++#define DCP2_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
++#define DCP2_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
++#define DCP2_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP2_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
++#define DCP2_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP2_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP2_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
++//DCP2_REGAMMA_CNTLA_REGION_2_3
++#define DCP2_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
++#define DCP2_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
++#define DCP2_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
++#define DCP2_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP2_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
++#define DCP2_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP2_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP2_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
++//DCP2_REGAMMA_CNTLA_REGION_4_5
++#define DCP2_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
++#define DCP2_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
++#define DCP2_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
++#define DCP2_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP2_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
++#define DCP2_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP2_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP2_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
++//DCP2_REGAMMA_CNTLA_REGION_6_7
++#define DCP2_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
++#define DCP2_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
++#define DCP2_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
++#define DCP2_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP2_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
++#define DCP2_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP2_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP2_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
++//DCP2_REGAMMA_CNTLA_REGION_8_9
++#define DCP2_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
++#define DCP2_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
++#define DCP2_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
++#define DCP2_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP2_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
++#define DCP2_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP2_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP2_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
++//DCP2_REGAMMA_CNTLA_REGION_10_11
++#define DCP2_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
++#define DCP2_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
++#define DCP2_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
++#define DCP2_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP2_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
++#define DCP2_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP2_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP2_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
++//DCP2_REGAMMA_CNTLA_REGION_12_13
++#define DCP2_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
++#define DCP2_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
++#define DCP2_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
++#define DCP2_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP2_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
++#define DCP2_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP2_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP2_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
++//DCP2_REGAMMA_CNTLA_REGION_14_15
++#define DCP2_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
++#define DCP2_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
++#define DCP2_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
++#define DCP2_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP2_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
++#define DCP2_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP2_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP2_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
++//DCP2_REGAMMA_CNTLB_START_CNTL
++#define DCP2_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x0
++#define DCP2_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14
++#define DCP2_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK 0x0003FFFFL
++#define DCP2_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
++//DCP2_REGAMMA_CNTLB_SLOPE_CNTL
++#define DCP2_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
++#define DCP2_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
++//DCP2_REGAMMA_CNTLB_END_CNTL1
++#define DCP2_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x0
++#define DCP2_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK 0x0000FFFFL
++//DCP2_REGAMMA_CNTLB_END_CNTL2
++#define DCP2_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0
++#define DCP2_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10
++#define DCP2_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
++#define DCP2_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xFFFF0000L
++//DCP2_REGAMMA_CNTLB_REGION_0_1
++#define DCP2_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
++#define DCP2_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
++#define DCP2_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
++#define DCP2_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP2_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
++#define DCP2_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP2_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP2_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
++//DCP2_REGAMMA_CNTLB_REGION_2_3
++#define DCP2_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
++#define DCP2_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
++#define DCP2_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
++#define DCP2_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP2_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
++#define DCP2_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP2_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP2_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
++//DCP2_REGAMMA_CNTLB_REGION_4_5
++#define DCP2_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
++#define DCP2_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
++#define DCP2_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
++#define DCP2_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP2_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
++#define DCP2_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP2_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP2_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
++//DCP2_REGAMMA_CNTLB_REGION_6_7
++#define DCP2_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
++#define DCP2_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
++#define DCP2_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
++#define DCP2_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP2_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
++#define DCP2_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP2_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP2_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
++//DCP2_REGAMMA_CNTLB_REGION_8_9
++#define DCP2_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
++#define DCP2_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
++#define DCP2_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
++#define DCP2_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP2_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
++#define DCP2_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP2_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP2_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
++//DCP2_REGAMMA_CNTLB_REGION_10_11
++#define DCP2_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
++#define DCP2_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
++#define DCP2_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
++#define DCP2_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP2_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
++#define DCP2_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP2_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP2_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
++//DCP2_REGAMMA_CNTLB_REGION_12_13
++#define DCP2_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
++#define DCP2_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
++#define DCP2_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
++#define DCP2_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP2_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
++#define DCP2_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP2_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP2_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
++//DCP2_REGAMMA_CNTLB_REGION_14_15
++#define DCP2_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
++#define DCP2_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
++#define DCP2_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
++#define DCP2_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP2_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
++#define DCP2_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP2_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP2_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
++//DCP2_ALPHA_CONTROL
++#define DCP2_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT 0x0
++#define DCP2_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT 0x1
++#define DCP2_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK 0x00000001L
++#define DCP2_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK 0x00000002L
++//DCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS
++#define DCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT 0x8
++#define DCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
++//DCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH
++#define DCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define DCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
++//DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS
++#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT 0x0
++#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT 0x18
++#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT 0x19
++#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT 0x1a
++#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT 0x1c
++#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT 0x1d
++#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT 0x1e
++#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK 0x000FFFFFL
++#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK 0x01000000L
++#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK 0x02000000L
++#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK 0x04000000L
++#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK 0x10000000L
++#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK 0x20000000L
++#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK 0x40000000L
++//DCP2_GRPH_XDMA_FLIP_TIMEOUT
++#define DCP2_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS__SHIFT 0x0
++#define DCP2_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK__SHIFT 0x1
++#define DCP2_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK__SHIFT 0x2
++#define DCP2_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS_MASK 0x00000001L
++#define DCP2_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK_MASK 0x00000002L
++#define DCP2_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK_MASK 0x00000004L
++//DCP2_GRPH_XDMA_FLIP_AVG_DELAY
++#define DCP2_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY__SHIFT 0x0
++#define DCP2_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD__SHIFT 0x10
++#define DCP2_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY_MASK 0x0000FFFFL
++#define DCP2_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD_MASK 0x00FF0000L
++//DCP2_GRPH_SURFACE_COUNTER_CONTROL
++#define DCP2_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN__SHIFT 0x0
++#define DCP2_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT__SHIFT 0x1
++#define DCP2_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED__SHIFT 0x9
++#define DCP2_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN_MASK 0x00000001L
++#define DCP2_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT_MASK 0x0000001EL
++#define DCP2_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_MASK 0x00000200L
++//DCP2_GRPH_SURFACE_COUNTER_OUTPUT
++#define DCP2_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN__SHIFT 0x0
++#define DCP2_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX__SHIFT 0x10
++#define DCP2_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN_MASK 0x0000FFFFL
++#define DCP2_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX_MASK 0xFFFF0000L
++
++
++// addressBlock: dce_dc_lb2_dispdec
++//LB2_LB_DATA_FORMAT
++#define LB2_LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0
++#define LB2_LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2
++#define LB2_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3
++#define LB2_LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4
++#define LB2_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5
++#define LB2_LB_DATA_FORMAT__PREFILL_EN__SHIFT 0x8
++#define LB2_LB_DATA_FORMAT__PREFETCH__SHIFT 0xc
++#define LB2_LB_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18
++#define LB2_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f
++#define LB2_LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x00000003L
++#define LB2_LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x00000004L
++#define LB2_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000008L
++#define LB2_LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x00000010L
++#define LB2_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x00000020L
++#define LB2_LB_DATA_FORMAT__PREFILL_EN_MASK 0x00000100L
++#define LB2_LB_DATA_FORMAT__PREFETCH_MASK 0x00001000L
++#define LB2_LB_DATA_FORMAT__REQUEST_MODE_MASK 0x01000000L
++#define LB2_LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000L
++//LB2_LB_MEMORY_CTRL
++#define LB2_LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0
++#define LB2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
++#define LB2_LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14
++#define LB2_LB_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0x00001FFFL
++#define LB2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x000F0000L
++#define LB2_LB_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x00300000L
++//LB2_LB_MEMORY_SIZE_STATUS
++#define LB2_LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0
++#define LB2_LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0x00001FFFL
++//LB2_LB_DESKTOP_HEIGHT
++#define LB2_LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0
++#define LB2_LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x00007FFFL
++//LB2_LB_VLINE_START_END
++#define LB2_LB_VLINE_START_END__VLINE_START__SHIFT 0x0
++#define LB2_LB_VLINE_START_END__VLINE_END__SHIFT 0x10
++#define LB2_LB_VLINE_START_END__VLINE_INV__SHIFT 0x1f
++#define LB2_LB_VLINE_START_END__VLINE_START_MASK 0x00003FFFL
++#define LB2_LB_VLINE_START_END__VLINE_END_MASK 0x7FFF0000L
++#define LB2_LB_VLINE_START_END__VLINE_INV_MASK 0x80000000L
++//LB2_LB_VLINE2_START_END
++#define LB2_LB_VLINE2_START_END__VLINE2_START__SHIFT 0x0
++#define LB2_LB_VLINE2_START_END__VLINE2_END__SHIFT 0x10
++#define LB2_LB_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f
++#define LB2_LB_VLINE2_START_END__VLINE2_START_MASK 0x00003FFFL
++#define LB2_LB_VLINE2_START_END__VLINE2_END_MASK 0x7FFF0000L
++#define LB2_LB_VLINE2_START_END__VLINE2_INV_MASK 0x80000000L
++//LB2_LB_V_COUNTER
++#define LB2_LB_V_COUNTER__V_COUNTER__SHIFT 0x0
++#define LB2_LB_V_COUNTER__V_COUNTER_MASK 0x00007FFFL
++//LB2_LB_SNAPSHOT_V_COUNTER
++#define LB2_LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0
++#define LB2_LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x00007FFFL
++//LB2_LB_INTERRUPT_MASK
++#define LB2_LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0
++#define LB2_LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4
++#define LB2_LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8
++#define LB2_LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x00000001L
++#define LB2_LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x00000010L
++#define LB2_LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x00000100L
++//LB2_LB_VLINE_STATUS
++#define LB2_LB_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0
++#define LB2_LB_VLINE_STATUS__VLINE_ACK__SHIFT 0x4
++#define LB2_LB_VLINE_STATUS__VLINE_STAT__SHIFT 0xc
++#define LB2_LB_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10
++#define LB2_LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11
++#define LB2_LB_VLINE_STATUS__VLINE_OCCURRED_MASK 0x00000001L
++#define LB2_LB_VLINE_STATUS__VLINE_ACK_MASK 0x00000010L
++#define LB2_LB_VLINE_STATUS__VLINE_STAT_MASK 0x00001000L
++#define LB2_LB_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x00010000L
++#define LB2_LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x00020000L
++//LB2_LB_VLINE2_STATUS
++#define LB2_LB_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0
++#define LB2_LB_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4
++#define LB2_LB_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc
++#define LB2_LB_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10
++#define LB2_LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11
++#define LB2_LB_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x00000001L
++#define LB2_LB_VLINE2_STATUS__VLINE2_ACK_MASK 0x00000010L
++#define LB2_LB_VLINE2_STATUS__VLINE2_STAT_MASK 0x00001000L
++#define LB2_LB_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x00010000L
++#define LB2_LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x00020000L
++//LB2_LB_VBLANK_STATUS
++#define LB2_LB_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0
++#define LB2_LB_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4
++#define LB2_LB_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc
++#define LB2_LB_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10
++#define LB2_LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11
++#define LB2_LB_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x00000001L
++#define LB2_LB_VBLANK_STATUS__VBLANK_ACK_MASK 0x00000010L
++#define LB2_LB_VBLANK_STATUS__VBLANK_STAT_MASK 0x00001000L
++#define LB2_LB_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x00010000L
++#define LB2_LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x00020000L
++//LB2_LB_SYNC_RESET_SEL
++#define LB2_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0
++#define LB2_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4
++#define LB2_LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8
++#define LB2_LB_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16
++#define LB2_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x00000003L
++#define LB2_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x00000010L
++#define LB2_LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0x0000FF00L
++#define LB2_LB_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0x00C00000L
++//LB2_LB_BLACK_KEYER_R_CR
++#define LB2_LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4
++#define LB2_LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0x0000FFF0L
++//LB2_LB_BLACK_KEYER_G_Y
++#define LB2_LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4
++#define LB2_LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0x0000FFF0L
++//LB2_LB_BLACK_KEYER_B_CB
++#define LB2_LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4
++#define LB2_LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0x0000FFF0L
++//LB2_LB_KEYER_COLOR_CTRL
++#define LB2_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0
++#define LB2_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8
++#define LB2_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x00000001L
++#define LB2_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x00000100L
++//LB2_LB_KEYER_COLOR_R_CR
++#define LB2_LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4
++#define LB2_LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0x0000FFF0L
++//LB2_LB_KEYER_COLOR_G_Y
++#define LB2_LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4
++#define LB2_LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0x0000FFF0L
++//LB2_LB_KEYER_COLOR_B_CB
++#define LB2_LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4
++#define LB2_LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0x0000FFF0L
++//LB2_LB_KEYER_COLOR_REP_R_CR
++#define LB2_LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4
++#define LB2_LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0x0000FFF0L
++//LB2_LB_KEYER_COLOR_REP_G_Y
++#define LB2_LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4
++#define LB2_LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0x0000FFF0L
++//LB2_LB_KEYER_COLOR_REP_B_CB
++#define LB2_LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4
++#define LB2_LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0x0000FFF0L
++//LB2_LB_BUFFER_LEVEL_STATUS
++#define LB2_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0
++#define LB2_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa
++#define LB2_LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10
++#define LB2_LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c
++#define LB2_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x0000003FL
++#define LB2_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0x0000FC00L
++#define LB2_LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0x0FFF0000L
++#define LB2_LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xF0000000L
++//LB2_LB_BUFFER_URGENCY_CTRL
++#define LB2_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0
++#define LB2_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10
++#define LB2_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0x00000FFFL
++#define LB2_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0x0FFF0000L
++//LB2_LB_BUFFER_URGENCY_STATUS
++#define LB2_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0
++#define LB2_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10
++#define LB2_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0x00000FFFL
++#define LB2_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x00010000L
++//LB2_LB_BUFFER_STATUS
++#define LB2_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0
++#define LB2_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4
++#define LB2_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8
++#define LB2_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc
++#define LB2_LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10
++#define LB2_LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14
++#define LB2_LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18
++#define LB2_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0x0000000FL
++#define LB2_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x00000010L
++#define LB2_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x00000100L
++#define LB2_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x00001000L
++#define LB2_LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x00010000L
++#define LB2_LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x00100000L
++#define LB2_LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x01000000L
++//LB2_LB_NO_OUTSTANDING_REQ_STATUS
++#define LB2_LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0
++#define LB2_LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x00000001L
++//LB2_MVP_AFR_FLIP_MODE
++#define LB2_MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT 0x0
++#define LB2_MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK 0x00000003L
++//LB2_MVP_AFR_FLIP_FIFO_CNTL
++#define LB2_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT 0x0
++#define LB2_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT 0x4
++#define LB2_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT 0x8
++#define LB2_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT 0xc
++#define LB2_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK 0x0000000FL
++#define LB2_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK 0x00000010L
++#define LB2_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK 0x00000100L
++#define LB2_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK 0x00001000L
++//LB2_MVP_FLIP_LINE_NUM_INSERT
++#define LB2_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT 0x0
++#define LB2_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT 0x8
++#define LB2_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT 0x18
++#define LB2_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT 0x1e
++#define LB2_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK 0x00000003L
++#define LB2_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK 0x007FFF00L
++#define LB2_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK 0x3F000000L
++#define LB2_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK 0x40000000L
++//LB2_DC_MVP_LB_CONTROL
++#define LB2_DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT 0x0
++#define LB2_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT 0x8
++#define LB2_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT 0xc
++#define LB2_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT 0x10
++#define LB2_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT 0x14
++#define LB2_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT 0x1c
++#define LB2_DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT 0x1f
++#define LB2_DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK 0x00000003L
++#define LB2_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK 0x00000100L
++#define LB2_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK 0x00001000L
++#define LB2_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK 0x00010000L
++#define LB2_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK 0x00100000L
++#define LB2_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK 0x10000000L
++#define LB2_DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK 0x80000000L
++
++
++// addressBlock: dce_dc_dcfe2_dispdec
++//DCFE2_DCFE_CLOCK_CONTROL
++#define DCFE2_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x4
++#define DCFE2_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x8
++#define DCFE2_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0xc
++#define DCFE2_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE__SHIFT 0xf
++#define DCFE2_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE__SHIFT 0x11
++#define DCFE2_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL__SHIFT 0x18
++#define DCFE2_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE__SHIFT 0x1f
++#define DCFE2_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x00000010L
++#define DCFE2_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE_MASK 0x00000100L
++#define DCFE2_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE_MASK 0x00001000L
++#define DCFE2_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE_MASK 0x00008000L
++#define DCFE2_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE_MASK 0x00020000L
++#define DCFE2_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL_MASK 0x1F000000L
++#define DCFE2_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE_MASK 0x80000000L
++//DCFE2_DCFE_SOFT_RESET
++#define DCFE2_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET__SHIFT 0x0
++#define DCFE2_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET__SHIFT 0x1
++#define DCFE2_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET__SHIFT 0x2
++#define DCFE2_DCFE_SOFT_RESET__SCL_SOFT_RESET__SHIFT 0x3
++#define DCFE2_DCFE_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4
++#define DCFE2_DCFE_SOFT_RESET__PSCL_SOFT_RESET__SHIFT 0x5
++#define DCFE2_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET_MASK 0x00000001L
++#define DCFE2_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET_MASK 0x00000002L
++#define DCFE2_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET_MASK 0x00000004L
++#define DCFE2_DCFE_SOFT_RESET__SCL_SOFT_RESET_MASK 0x00000008L
++#define DCFE2_DCFE_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x00000010L
++#define DCFE2_DCFE_SOFT_RESET__PSCL_SOFT_RESET_MASK 0x00000020L
++//DCFE2_DCFE_MEM_PWR_CTRL
++#define DCFE2_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE__SHIFT 0x0
++#define DCFE2_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS__SHIFT 0x2
++#define DCFE2_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE__SHIFT 0x3
++#define DCFE2_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS__SHIFT 0x5
++#define DCFE2_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE__SHIFT 0x6
++#define DCFE2_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS__SHIFT 0x8
++#define DCFE2_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE__SHIFT 0x9
++#define DCFE2_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS__SHIFT 0xb
++#define DCFE2_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE__SHIFT 0xc
++#define DCFE2_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS__SHIFT 0xe
++#define DCFE2_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE__SHIFT 0xf
++#define DCFE2_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS__SHIFT 0x11
++#define DCFE2_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE__SHIFT 0x12
++#define DCFE2_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS__SHIFT 0x14
++#define DCFE2_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE__SHIFT 0x15
++#define DCFE2_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS__SHIFT 0x17
++#define DCFE2_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE__SHIFT 0x18
++#define DCFE2_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS__SHIFT 0x1a
++#define DCFE2_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE__SHIFT 0x1b
++#define DCFE2_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS__SHIFT 0x1d
++#define DCFE2_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE_MASK 0x00000003L
++#define DCFE2_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS_MASK 0x00000004L
++#define DCFE2_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE_MASK 0x00000018L
++#define DCFE2_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS_MASK 0x00000020L
++#define DCFE2_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE_MASK 0x000000C0L
++#define DCFE2_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS_MASK 0x00000100L
++#define DCFE2_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE_MASK 0x00000600L
++#define DCFE2_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS_MASK 0x00000800L
++#define DCFE2_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE_MASK 0x00003000L
++#define DCFE2_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS_MASK 0x00004000L
++#define DCFE2_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE_MASK 0x00018000L
++#define DCFE2_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK 0x00020000L
++#define DCFE2_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE_MASK 0x000C0000L
++#define DCFE2_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS_MASK 0x00100000L
++#define DCFE2_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE_MASK 0x00600000L
++#define DCFE2_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS_MASK 0x00800000L
++#define DCFE2_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE_MASK 0x03000000L
++#define DCFE2_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS_MASK 0x04000000L
++#define DCFE2_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE_MASK 0x18000000L
++#define DCFE2_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS_MASK 0x20000000L
++//DCFE2_DCFE_MEM_PWR_CTRL2
++#define DCFE2_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL__SHIFT 0x0
++#define DCFE2_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2
++#define DCFE2_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4
++#define DCFE2_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL__SHIFT 0x6
++#define DCFE2_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL__SHIFT 0x8
++#define DCFE2_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL__SHIFT 0xa
++#define DCFE2_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL__SHIFT 0xc
++#define DCFE2_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL__SHIFT 0xe
++#define DCFE2_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE__SHIFT 0x10
++#define DCFE2_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS__SHIFT 0x12
++#define DCFE2_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE__SHIFT 0x15
++#define DCFE2_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS__SHIFT 0x17
++#define DCFE2_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL_MASK 0x00000003L
++#define DCFE2_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL_MASK 0x0000000CL
++#define DCFE2_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL_MASK 0x00000030L
++#define DCFE2_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL_MASK 0x000000C0L
++#define DCFE2_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL_MASK 0x00000300L
++#define DCFE2_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL_MASK 0x00000C00L
++#define DCFE2_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL_MASK 0x00003000L
++#define DCFE2_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL_MASK 0x0000C000L
++#define DCFE2_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE_MASK 0x00030000L
++#define DCFE2_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS_MASK 0x00040000L
++#define DCFE2_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE_MASK 0x00600000L
++#define DCFE2_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS_MASK 0x00800000L
++//DCFE2_DCFE_MEM_PWR_STATUS
++#define DCFE2_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE__SHIFT 0x0
++#define DCFE2_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE__SHIFT 0x2
++#define DCFE2_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE__SHIFT 0x4
++#define DCFE2_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x6
++#define DCFE2_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE__SHIFT 0x8
++#define DCFE2_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE__SHIFT 0xa
++#define DCFE2_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE__SHIFT 0xc
++#define DCFE2_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE__SHIFT 0xe
++#define DCFE2_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT 0x10
++#define DCFE2_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE__SHIFT 0x12
++#define DCFE2_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE__SHIFT 0x14
++#define DCFE2_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE__SHIFT 0x16
++#define DCFE2_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK 0x00000003L
++#define DCFE2_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE_MASK 0x0000000CL
++#define DCFE2_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE_MASK 0x00000030L
++#define DCFE2_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE_MASK 0x000000C0L
++#define DCFE2_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE_MASK 0x00000300L
++#define DCFE2_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE_MASK 0x00000C00L
++#define DCFE2_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE_MASK 0x00003000L
++#define DCFE2_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE_MASK 0x0000C000L
++#define DCFE2_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE_MASK 0x00030000L
++#define DCFE2_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK 0x000C0000L
++#define DCFE2_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE_MASK 0x00300000L
++#define DCFE2_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE_MASK 0x00C00000L
++//DCFE2_DCFE_MISC
++#define DCFE2_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN__SHIFT 0x0
++#define DCFE2_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN_MASK 0x00000001L
++//DCFE2_DCFE_FLUSH
++#define DCFE2_DCFE_FLUSH__FLUSH_OCCURED__SHIFT 0x0
++#define DCFE2_DCFE_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT 0x1
++#define DCFE2_DCFE_FLUSH__FLUSH_DEEP__SHIFT 0x2
++#define DCFE2_DCFE_FLUSH__CLEAR_FLUSH_DEEP__SHIFT 0x3
++#define DCFE2_DCFE_FLUSH__ALL_MC_REQ_RET__SHIFT 0x4
++#define DCFE2_DCFE_FLUSH__FLUSH_OCCURED_MASK 0x00000001L
++#define DCFE2_DCFE_FLUSH__CLEAR_FLUSH_OCCURED_MASK 0x00000002L
++#define DCFE2_DCFE_FLUSH__FLUSH_DEEP_MASK 0x00000004L
++#define DCFE2_DCFE_FLUSH__CLEAR_FLUSH_DEEP_MASK 0x00000008L
++#define DCFE2_DCFE_FLUSH__ALL_MC_REQ_RET_MASK 0x00000010L
++
++
++// addressBlock: dce_dc_dc_perfmon5_dispdec
++//DC_PERFMON5_PERFCOUNTER_CNTL
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
++//DC_PERFMON5_PERFCOUNTER_CNTL2
++#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
++#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
++#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
++#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
++#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
++#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
++#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
++#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
++//DC_PERFMON5_PERFCOUNTER_STATE
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
++//DC_PERFMON5_PERFMON_CNTL
++#define DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
++#define DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
++#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
++#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
++#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
++#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
++#define DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
++#define DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
++#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
++#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
++#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
++#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
++//DC_PERFMON5_PERFMON_CNTL2
++#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
++#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
++#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
++#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
++#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
++#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
++#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
++#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
++//DC_PERFMON5_PERFMON_CVALUE_INT_MISC
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
++//DC_PERFMON5_PERFMON_CVALUE_LOW
++#define DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
++#define DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
++//DC_PERFMON5_PERFMON_HI
++#define DC_PERFMON5_PERFMON_HI__PERFMON_HI__SHIFT 0x0
++#define DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
++#define DC_PERFMON5_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
++#define DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
++//DC_PERFMON5_PERFMON_LOW
++#define DC_PERFMON5_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
++#define DC_PERFMON5_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dmif_pg2_dispdec
++//DMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1
++#define DMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
++#define DMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
++#define DMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0x0000FFFFL
++#define DMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xFFFF0000L
++//DMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2
++#define DMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
++#define DMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
++#define DMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0x0000FFFFL
++#define DMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xFFFF0000L
++//DMIF_PG2_DPG_WATERMARK_MASK_CONTROL
++#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
++#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x4
++#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
++#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK__SHIFT 0xc
++#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0xf
++#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x12
++#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL__SHIFT 0x13
++#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL__SHIFT 0x14
++#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000007L
++#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000070L
++#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x00000700L
++#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK_MASK 0x00007000L
++#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00038000L
++#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x00040000L
++#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL_MASK 0x00080000L
++#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL_MASK 0x3FF00000L
++//DMIF_PG2_DPG_PIPE_URGENCY_CONTROL
++#define DMIF_PG2_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
++#define DMIF_PG2_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
++#define DMIF_PG2_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0x0000FFFFL
++#define DMIF_PG2_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xFFFF0000L
++//DMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL
++#define DMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK__SHIFT 0x0
++#define DMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK__SHIFT 0x10
++#define DMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK_MASK 0x0000FFFFL
++#define DMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK_MASK 0xFFFF0000L
++//DMIF_PG2_DPG_PIPE_STUTTER_CONTROL
++#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
++#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
++#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
++#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
++#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
++#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
++#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
++#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH__SHIFT 0x10
++#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x14
++#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x15
++#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x16
++#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x17
++#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0x1a
++#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0x1b
++#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L
++#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L
++#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x00000020L
++#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x00000040L
++#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x00000080L
++#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x00000400L
++#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x00000800L
++#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH_MASK 0x00010000L
++#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x00100000L
++#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x00200000L
++#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x00400000L
++#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x00800000L
++#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x04000000L
++#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x08000000L
++//DMIF_PG2_DPG_PIPE_STUTTER_CONTROL2
++#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x0
++#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK__SHIFT 0x10
++#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0x0000FFFFL
++#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK 0xFFFF0000L
++//DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL
++#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE__SHIFT 0x0
++#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE__SHIFT 0x1
++#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
++#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
++#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
++#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
++#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK__SHIFT 0xf
++#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE_MASK 0x00000001L
++#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE_MASK 0x00000002L
++#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L
++#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x00000100L
++#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON_MASK 0x00000200L
++#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT_MASK 0x00000400L
++#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK_MASK 0xFFFF8000L
++//DMIF_PG2_DPG_REPEATER_PROGRAM
++#define DMIF_PG2_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
++#define DMIF_PG2_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
++#define DMIF_PG2_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x00000007L
++#define DMIF_PG2_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x00000070L
++//DMIF_PG2_DPG_CHK_PRE_PROC_CNTL
++#define DMIF_PG2_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0
++#define DMIF_PG2_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x00000001L
++//DMIF_PG2_DPG_DVMM_STATUS
++#define DMIF_PG2_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED__SHIFT 0x0
++#define DMIF_PG2_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED__SHIFT 0x1
++#define DMIF_PG2_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR__SHIFT 0x4
++#define DMIF_PG2_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR__SHIFT 0x5
++#define DMIF_PG2_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_MASK 0x00000001L
++#define DMIF_PG2_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_MASK 0x00000002L
++#define DMIF_PG2_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR_MASK 0x00000010L
++#define DMIF_PG2_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR_MASK 0x00000020L
++
++
++// addressBlock: dce_dc_scl2_dispdec
++//SCL2_SCL_COEF_RAM_SELECT
++#define SCL2_SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0
++#define SCL2_SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8
++#define SCL2_SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10
++#define SCL2_SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x0000000FL
++#define SCL2_SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x00000F00L
++#define SCL2_SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x00070000L
++//SCL2_SCL_COEF_RAM_TAP_DATA
++#define SCL2_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0
++#define SCL2_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
++#define SCL2_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10
++#define SCL2_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
++#define SCL2_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL
++#define SCL2_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L
++#define SCL2_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L
++#define SCL2_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L
++//SCL2_SCL_MODE
++#define SCL2_SCL_MODE__SCL_MODE__SHIFT 0x0
++#define SCL2_SCL_MODE__SCL_PSCL_EN__SHIFT 0x4
++#define SCL2_SCL_MODE__SCL_MODE_MASK 0x00000003L
++#define SCL2_SCL_MODE__SCL_PSCL_EN_MASK 0x00000010L
++//SCL2_SCL_TAP_CONTROL
++#define SCL2_SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0
++#define SCL2_SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x8
++#define SCL2_SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x00000007L
++#define SCL2_SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0x00000F00L
++//SCL2_SCL_CONTROL
++#define SCL2_SCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
++#define SCL2_SCL_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4
++#define SCL2_SCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L
++#define SCL2_SCL_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x00000010L
++//SCL2_SCL_BYPASS_CONTROL
++#define SCL2_SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT 0x0
++#define SCL2_SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x00000003L
++//SCL2_SCL_MANUAL_REPLICATE_CONTROL
++#define SCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
++#define SCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
++#define SCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL
++#define SCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L
++//SCL2_SCL_AUTOMATIC_MODE_CONTROL
++#define SCL2_SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0
++#define SCL2_SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10
++#define SCL2_SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x00000001L
++#define SCL2_SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x00010000L
++//SCL2_SCL_HORZ_FILTER_CONTROL
++#define SCL2_SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT 0x0
++#define SCL2_SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
++#define SCL2_SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK 0x00000001L
++#define SCL2_SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
++//SCL2_SCL_HORZ_FILTER_SCALE_RATIO
++#define SCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
++#define SCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL
++//SCL2_SCL_HORZ_FILTER_INIT
++#define SCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
++#define SCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
++#define SCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL
++#define SCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L
++//SCL2_SCL_VERT_FILTER_CONTROL
++#define SCL2_SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT 0x0
++#define SCL2_SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
++#define SCL2_SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK 0x00000001L
++#define SCL2_SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
++//SCL2_SCL_VERT_FILTER_SCALE_RATIO
++#define SCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
++#define SCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL
++//SCL2_SCL_VERT_FILTER_INIT
++#define SCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
++#define SCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
++#define SCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL
++#define SCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x07000000L
++//SCL2_SCL_VERT_FILTER_INIT_BOT
++#define SCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
++#define SCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
++#define SCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL
++#define SCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x07000000L
++//SCL2_SCL_ROUND_OFFSET
++#define SCL2_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0
++#define SCL2_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10
++#define SCL2_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0x0000FFFFL
++#define SCL2_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xFFFF0000L
++//SCL2_SCL_UPDATE
++#define SCL2_SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
++#define SCL2_SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8
++#define SCL2_SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10
++#define SCL2_SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18
++#define SCL2_SCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L
++#define SCL2_SCL_UPDATE__SCL_UPDATE_TAKEN_MASK 0x00000100L
++#define SCL2_SCL_UPDATE__SCL_UPDATE_LOCK_MASK 0x00010000L
++#define SCL2_SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x01000000L
++//SCL2_SCL_F_SHARP_CONTROL
++#define SCL2_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT 0x0
++#define SCL2_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT 0x4
++#define SCL2_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT 0x8
++#define SCL2_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT 0xc
++#define SCL2_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK 0x00000007L
++#define SCL2_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK 0x00000010L
++#define SCL2_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK 0x00000700L
++#define SCL2_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK 0x00001000L
++//SCL2_SCL_ALU_CONTROL
++#define SCL2_SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0
++#define SCL2_SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x00000001L
++//SCL2_SCL_COEF_RAM_CONFLICT_STATUS
++#define SCL2_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT 0x0
++#define SCL2_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT 0x8
++#define SCL2_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT 0xc
++#define SCL2_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10
++#define SCL2_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK 0x00000001L
++#define SCL2_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK 0x00000100L
++#define SCL2_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK 0x00001000L
++#define SCL2_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK 0x00010000L
++//SCL2_VIEWPORT_START_SECONDARY
++#define SCL2_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0
++#define SCL2_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10
++#define SCL2_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x00003FFFL
++#define SCL2_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3FFF0000L
++//SCL2_VIEWPORT_START
++#define SCL2_VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0
++#define SCL2_VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10
++#define SCL2_VIEWPORT_START__VIEWPORT_Y_START_MASK 0x00003FFFL
++#define SCL2_VIEWPORT_START__VIEWPORT_X_START_MASK 0x3FFF0000L
++//SCL2_VIEWPORT_SIZE
++#define SCL2_VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0
++#define SCL2_VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10
++#define SCL2_VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x00003FFFL
++#define SCL2_VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x3FFF0000L
++//SCL2_EXT_OVERSCAN_LEFT_RIGHT
++#define SCL2_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
++#define SCL2_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
++#define SCL2_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL
++#define SCL2_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L
++//SCL2_EXT_OVERSCAN_TOP_BOTTOM
++#define SCL2_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
++#define SCL2_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
++#define SCL2_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL
++#define SCL2_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L
++//SCL2_SCL_MODE_CHANGE_DET1
++#define SCL2_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0
++#define SCL2_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4
++#define SCL2_SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7
++#define SCL2_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x00000001L
++#define SCL2_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x00000010L
++#define SCL2_SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0x0FFFFF80L
++//SCL2_SCL_MODE_CHANGE_DET2
++#define SCL2_SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0
++#define SCL2_SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x001FFFFFL
++//SCL2_SCL_MODE_CHANGE_DET3
++#define SCL2_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0
++#define SCL2_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10
++#define SCL2_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x00003FFFL
++#define SCL2_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3FFF0000L
++//SCL2_SCL_MODE_CHANGE_MASK
++#define SCL2_SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0
++#define SCL2_SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x00000001L
++
++
++// addressBlock: dce_dc_blnd2_dispdec
++//BLND2_BLND_CONTROL
++#define BLND2_BLND_CONTROL__BLND_GLOBAL_GAIN__SHIFT 0x0
++#define BLND2_BLND_CONTROL__BLND_MODE__SHIFT 0x8
++#define BLND2_BLND_CONTROL__BLND_STEREO_TYPE__SHIFT 0xa
++#define BLND2_BLND_CONTROL__BLND_STEREO_POLARITY__SHIFT 0xc
++#define BLND2_BLND_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT 0xd
++#define BLND2_BLND_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10
++#define BLND2_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x12
++#define BLND2_BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14
++#define BLND2_BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18
++#define BLND2_BLND_CONTROL__BLND_GLOBAL_GAIN_MASK 0x000000FFL
++#define BLND2_BLND_CONTROL__BLND_MODE_MASK 0x00000300L
++#define BLND2_BLND_CONTROL__BLND_STEREO_TYPE_MASK 0x00000C00L
++#define BLND2_BLND_CONTROL__BLND_STEREO_POLARITY_MASK 0x00001000L
++#define BLND2_BLND_CONTROL__BLND_FEEDTHROUGH_EN_MASK 0x00002000L
++#define BLND2_BLND_CONTROL__BLND_ALPHA_MODE_MASK 0x00030000L
++#define BLND2_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00040000L
++#define BLND2_BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x00100000L
++#define BLND2_BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xFF000000L
++//BLND2_BLND_SM_CONTROL2
++#define BLND2_BLND_SM_CONTROL2__SM_MODE__SHIFT 0x0
++#define BLND2_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4
++#define BLND2_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5
++#define BLND2_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
++#define BLND2_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
++#define BLND2_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18
++#define BLND2_BLND_SM_CONTROL2__SM_MODE_MASK 0x00000007L
++#define BLND2_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x00000010L
++#define BLND2_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x00000020L
++#define BLND2_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L
++#define BLND2_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L
++#define BLND2_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x01000000L
++//BLND2_BLND_CONTROL2
++#define BLND2_BLND_CONTROL2__PTI_ENABLE__SHIFT 0x0
++#define BLND2_BLND_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT 0x4
++#define BLND2_BLND_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT 0x6
++#define BLND2_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT 0x7
++#define BLND2_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT 0x8
++#define BLND2_BLND_CONTROL2__PTI_ENABLE_MASK 0x00000001L
++#define BLND2_BLND_CONTROL2__PTI_NEW_PIXEL_GAP_MASK 0x00000030L
++#define BLND2_BLND_CONTROL2__BLND_NEW_PIXEL_MODE_MASK 0x00000040L
++#define BLND2_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK 0x00000080L
++#define BLND2_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK 0x00000100L
++//BLND2_BLND_UPDATE
++#define BLND2_BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0
++#define BLND2_BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8
++#define BLND2_BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10
++#define BLND2_BLND_UPDATE__BLND_UPDATE_PENDING_MASK 0x00000001L
++#define BLND2_BLND_UPDATE__BLND_UPDATE_TAKEN_MASK 0x00000100L
++#define BLND2_BLND_UPDATE__BLND_UPDATE_LOCK_MASK 0x00010000L
++//BLND2_BLND_UNDERFLOW_INTERRUPT
++#define BLND2_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0
++#define BLND2_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8
++#define BLND2_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc
++#define BLND2_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10
++#define BLND2_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x00000001L
++#define BLND2_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x00000100L
++#define BLND2_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x00001000L
++#define BLND2_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x00030000L
++//BLND2_BLND_V_UPDATE_LOCK
++#define BLND2_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0
++#define BLND2_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1
++#define BLND2_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10
++#define BLND2_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c
++#define BLND2_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT 0x1d
++#define BLND2_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT 0x1f
++#define BLND2_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x00000001L
++#define BLND2_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x00000002L
++#define BLND2_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x00010000L
++#define BLND2_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000L
++#define BLND2_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK 0x20000000L
++#define BLND2_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK 0x80000000L
++//BLND2_BLND_REG_UPDATE_STATUS
++#define BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT 0x0
++#define BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT 0x1
++#define BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2
++#define BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3
++#define BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT 0x6
++#define BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT 0x7
++#define BLND2_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT 0x8
++#define BLND2_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT 0x9
++#define BLND2_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT 0xa
++#define BLND2_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT 0xb
++#define BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK 0x00000001L
++#define BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK 0x00000002L
++#define BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK 0x00000004L
++#define BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK 0x00000008L
++#define BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK 0x00000040L
++#define BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK 0x00000080L
++#define BLND2_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK 0x00000100L
++#define BLND2_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK 0x00000200L
++#define BLND2_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK 0x00000400L
++#define BLND2_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK 0x00000800L
++
++
++// addressBlock: dce_dc_crtc2_dispdec
++//CRTC2_CRTC_H_BLANK_EARLY_NUM
++#define CRTC2_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0
++#define CRTC2_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10
++#define CRTC2_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x000003FFL
++#define CRTC2_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x00010000L
++//CRTC2_CRTC_H_TOTAL
++#define CRTC2_CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0
++#define CRTC2_CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x00003FFFL
++//CRTC2_CRTC_H_BLANK_START_END
++#define CRTC2_CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0
++#define CRTC2_CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10
++#define CRTC2_CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x00003FFFL
++#define CRTC2_CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3FFF0000L
++//CRTC2_CRTC_H_SYNC_A
++#define CRTC2_CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0
++#define CRTC2_CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10
++#define CRTC2_CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x00003FFFL
++#define CRTC2_CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3FFF0000L
++//CRTC2_CRTC_H_SYNC_A_CNTL
++#define CRTC2_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0
++#define CRTC2_CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10
++#define CRTC2_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11
++#define CRTC2_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x00000001L
++#define CRTC2_CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x00010000L
++#define CRTC2_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x00020000L
++//CRTC2_CRTC_H_SYNC_B
++#define CRTC2_CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0
++#define CRTC2_CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10
++#define CRTC2_CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x00003FFFL
++#define CRTC2_CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x3FFF0000L
++//CRTC2_CRTC_H_SYNC_B_CNTL
++#define CRTC2_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0
++#define CRTC2_CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10
++#define CRTC2_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11
++#define CRTC2_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x00000001L
++#define CRTC2_CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x00010000L
++#define CRTC2_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x00020000L
++//CRTC2_CRTC_VBI_END
++#define CRTC2_CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x0
++#define CRTC2_CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x10
++#define CRTC2_CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x00003FFFL
++#define CRTC2_CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x3FFF0000L
++//CRTC2_CRTC_V_TOTAL
++#define CRTC2_CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0
++#define CRTC2_CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x00003FFFL
++//CRTC2_CRTC_V_TOTAL_MIN
++#define CRTC2_CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0
++#define CRTC2_CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x00003FFFL
++//CRTC2_CRTC_V_TOTAL_MAX
++#define CRTC2_CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0
++#define CRTC2_CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10
++#define CRTC2_CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x00003FFFL
++#define CRTC2_CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x00010000L
++//CRTC2_CRTC_V_TOTAL_CONTROL
++#define CRTC2_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0
++#define CRTC2_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4
++#define CRTC2_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8
++#define CRTC2_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc
++#define CRTC2_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf
++#define CRTC2_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10
++#define CRTC2_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x00000001L
++#define CRTC2_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x00000010L
++#define CRTC2_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x00000100L
++#define CRTC2_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x00001000L
++#define CRTC2_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00008000L
++#define CRTC2_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L
++//CRTC2_CRTC_V_TOTAL_INT_STATUS
++#define CRTC2_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0
++#define CRTC2_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4
++#define CRTC2_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8
++#define CRTC2_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc
++#define CRTC2_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L
++#define CRTC2_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L
++#define CRTC2_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L
++#define CRTC2_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L
++//CRTC2_CRTC_VSYNC_NOM_INT_STATUS
++#define CRTC2_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0
++#define CRTC2_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4
++#define CRTC2_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x00000001L
++#define CRTC2_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L
++//CRTC2_CRTC_V_BLANK_START_END
++#define CRTC2_CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0
++#define CRTC2_CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10
++#define CRTC2_CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x00003FFFL
++#define CRTC2_CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3FFF0000L
++//CRTC2_CRTC_V_SYNC_A
++#define CRTC2_CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0
++#define CRTC2_CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10
++#define CRTC2_CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x00003FFFL
++#define CRTC2_CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3FFF0000L
++//CRTC2_CRTC_V_SYNC_A_CNTL
++#define CRTC2_CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0
++#define CRTC2_CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x00000001L
++//CRTC2_CRTC_V_SYNC_B
++#define CRTC2_CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0
++#define CRTC2_CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10
++#define CRTC2_CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x00003FFFL
++#define CRTC2_CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x3FFF0000L
++//CRTC2_CRTC_V_SYNC_B_CNTL
++#define CRTC2_CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0
++#define CRTC2_CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x00000001L
++//CRTC2_CRTC_DTMTEST_CNTL
++#define CRTC2_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0
++#define CRTC2_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1
++#define CRTC2_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x00000001L
++#define CRTC2_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x0000001EL
++//CRTC2_CRTC_DTMTEST_STATUS_POSITION
++#define CRTC2_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0
++#define CRTC2_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10
++#define CRTC2_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x00003FFFL
++#define CRTC2_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x3FFF0000L
++//CRTC2_CRTC_TRIGA_CNTL
++#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0
++#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5
++#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8
++#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9
++#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa
++#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb
++#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
++#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
++#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14
++#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18
++#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f
++#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x0000001FL
++#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0x000000E0L
++#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000100L
++#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x00000200L
++#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x00000400L
++#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x00000800L
++#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
++#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
++#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L
++#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1F000000L
++#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000L
++//CRTC2_CRTC_TRIGA_MANUAL_TRIG
++#define CRTC2_CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0
++#define CRTC2_CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x00000001L
++//CRTC2_CRTC_TRIGB_CNTL
++#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0
++#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5
++#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8
++#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9
++#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa
++#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb
++#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
++#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
++#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14
++#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18
++#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f
++#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x0000001FL
++#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0x000000E0L
++#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000100L
++#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x00000200L
++#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x00000400L
++#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x00000800L
++#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
++#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
++#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L
++#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1F000000L
++#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000L
++//CRTC2_CRTC_TRIGB_MANUAL_TRIG
++#define CRTC2_CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0
++#define CRTC2_CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x00000001L
++//CRTC2_CRTC_FORCE_COUNT_NOW_CNTL
++#define CRTC2_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0
++#define CRTC2_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4
++#define CRTC2_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8
++#define CRTC2_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10
++#define CRTC2_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18
++#define CRTC2_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x00000003L
++#define CRTC2_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L
++#define CRTC2_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L
++#define CRTC2_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L
++#define CRTC2_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L
++//CRTC2_CRTC_FLOW_CONTROL
++#define CRTC2_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0
++#define CRTC2_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8
++#define CRTC2_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10
++#define CRTC2_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18
++#define CRTC2_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL
++#define CRTC2_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x00000100L
++#define CRTC2_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L
++#define CRTC2_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L
++//CRTC2_CRTC_STEREO_FORCE_NEXT_EYE
++#define CRTC2_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0
++#define CRTC2_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER__SHIFT 0x8
++#define CRTC2_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER__SHIFT 0x10
++#define CRTC2_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L
++#define CRTC2_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L
++#define CRTC2_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L
++//CRTC2_CRTC_AVSYNC_COUNTER
++#define CRTC2_CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER__SHIFT 0x0
++#define CRTC2_CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER_MASK 0xFFFFFFFFL
++//CRTC2_CRTC_CONTROL
++#define CRTC2_CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x0
++#define CRTC2_CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4
++#define CRTC2_CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8
++#define CRTC2_CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc
++#define CRTC2_CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd
++#define CRTC2_CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe
++#define CRTC2_CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10
++#define CRTC2_CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14
++#define CRTC2_CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d
++#define CRTC2_CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e
++#define CRTC2_CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f
++#define CRTC2_CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x00000001L
++#define CRTC2_CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x00000010L
++#define CRTC2_CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x00000300L
++#define CRTC2_CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x00001000L
++#define CRTC2_CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x00002000L
++#define CRTC2_CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x00004000L
++#define CRTC2_CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x00010000L
++#define CRTC2_CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x00700000L
++#define CRTC2_CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000L
++#define CRTC2_CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L
++#define CRTC2_CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L
++//CRTC2_CRTC_BLANK_CONTROL
++#define CRTC2_CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0
++#define CRTC2_CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8
++#define CRTC2_CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10
++#define CRTC2_CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x00000001L
++#define CRTC2_CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x00000100L
++#define CRTC2_CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x00010000L
++//CRTC2_CRTC_INTERLACE_CONTROL
++#define CRTC2_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0
++#define CRTC2_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10
++#define CRTC2_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x00000001L
++#define CRTC2_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L
++//CRTC2_CRTC_INTERLACE_STATUS
++#define CRTC2_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0
++#define CRTC2_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1
++#define CRTC2_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x00000001L
++#define CRTC2_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x00000002L
++//CRTC2_CRTC_FIELD_INDICATION_CONTROL
++#define CRTC2_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0
++#define CRTC2_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1
++#define CRTC2_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x00000001L
++#define CRTC2_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x00000002L
++//CRTC2_CRTC_PIXEL_DATA_READBACK0
++#define CRTC2_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0
++#define CRTC2_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10
++#define CRTC2_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0x00000FFFL
++#define CRTC2_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0x0FFF0000L
++//CRTC2_CRTC_PIXEL_DATA_READBACK1
++#define CRTC2_CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0
++#define CRTC2_CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0x00000FFFL
++//CRTC2_CRTC_STATUS
++#define CRTC2_CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x0
++#define CRTC2_CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1
++#define CRTC2_CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x2
++#define CRTC2_CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x3
++#define CRTC2_CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x4
++#define CRTC2_CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5
++#define CRTC2_CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x10
++#define CRTC2_CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11
++#define CRTC2_CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x12
++#define CRTC2_CRTC_STATUS__CRTC_V_BLANK_MASK 0x00000001L
++#define CRTC2_CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x00000002L
++#define CRTC2_CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x00000004L
++#define CRTC2_CRTC_STATUS__CRTC_V_UPDATE_MASK 0x00000008L
++#define CRTC2_CRTC_STATUS__CRTC_V_START_LINE_MASK 0x00000010L
++#define CRTC2_CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x00000020L
++#define CRTC2_CRTC_STATUS__CRTC_H_BLANK_MASK 0x00010000L
++#define CRTC2_CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x00020000L
++#define CRTC2_CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x00040000L
++//CRTC2_CRTC_STATUS_POSITION
++#define CRTC2_CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0
++#define CRTC2_CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10
++#define CRTC2_CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x00003FFFL
++#define CRTC2_CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x3FFF0000L
++//CRTC2_CRTC_NOM_VERT_POSITION
++#define CRTC2_CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0
++#define CRTC2_CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x00003FFFL
++//CRTC2_CRTC_STATUS_FRAME_COUNT
++#define CRTC2_CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0
++#define CRTC2_CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0x00FFFFFFL
++//CRTC2_CRTC_STATUS_VF_COUNT
++#define CRTC2_CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0
++#define CRTC2_CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x3FFFFFFFL
++//CRTC2_CRTC_STATUS_HV_COUNT
++#define CRTC2_CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0
++#define CRTC2_CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x3FFFFFFFL
++//CRTC2_CRTC_COUNT_CONTROL
++#define CRTC2_CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0
++#define CRTC2_CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1
++#define CRTC2_CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x00000001L
++#define CRTC2_CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x0000001EL
++//CRTC2_CRTC_COUNT_RESET
++#define CRTC2_CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0
++#define CRTC2_CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x00000001L
++//CRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE
++#define CRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0
++#define CRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L
++//CRTC2_CRTC_VERT_SYNC_CONTROL
++#define CRTC2_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0
++#define CRTC2_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8
++#define CRTC2_CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10
++#define CRTC2_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L
++#define CRTC2_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L
++#define CRTC2_CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L
++//CRTC2_CRTC_STEREO_STATUS
++#define CRTC2_CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0
++#define CRTC2_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8
++#define CRTC2_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10
++#define CRTC2_CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG__SHIFT 0x14
++#define CRTC2_CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18
++#define CRTC2_CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x00000001L
++#define CRTC2_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x00000100L
++#define CRTC2_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x00010000L
++#define CRTC2_CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG_MASK 0x00100000L
++#define CRTC2_CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L
++//CRTC2_CRTC_STEREO_CONTROL
++#define CRTC2_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0
++#define CRTC2_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf
++#define CRTC2_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10
++#define CRTC2_CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11
++#define CRTC2_CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12
++#define CRTC2_CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM__SHIFT 0x13
++#define CRTC2_CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14
++#define CRTC2_CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18
++#define CRTC2_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00003FFFL
++#define CRTC2_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L
++#define CRTC2_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x00010000L
++#define CRTC2_CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L
++#define CRTC2_CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L
++#define CRTC2_CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM_MASK 0x00080000L
++#define CRTC2_CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L
++#define CRTC2_CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x01000000L
++//CRTC2_CRTC_SNAPSHOT_STATUS
++#define CRTC2_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0
++#define CRTC2_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1
++#define CRTC2_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2
++#define CRTC2_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x00000001L
++#define CRTC2_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x00000002L
++#define CRTC2_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L
++//CRTC2_CRTC_SNAPSHOT_CONTROL
++#define CRTC2_CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0
++#define CRTC2_CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L
++//CRTC2_CRTC_SNAPSHOT_POSITION
++#define CRTC2_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0
++#define CRTC2_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10
++#define CRTC2_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x00003FFFL
++#define CRTC2_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x3FFF0000L
++//CRTC2_CRTC_SNAPSHOT_FRAME
++#define CRTC2_CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0
++#define CRTC2_CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL
++//CRTC2_CRTC_START_LINE_CONTROL
++#define CRTC2_CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0
++#define CRTC2_CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x1
++#define CRTC2_CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x2
++#define CRTC2_CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x8
++#define CRTC2_CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc
++#define CRTC2_CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x00000001L
++#define CRTC2_CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x00000002L
++#define CRTC2_CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x00000004L
++#define CRTC2_CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x00000100L
++#define CRTC2_CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0x000FF000L
++//CRTC2_CRTC_INTERRUPT_CONTROL
++#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0
++#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1
++#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4
++#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5
++#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8
++#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9
++#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10
++#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11
++#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18
++#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19
++#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a
++#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b
++#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c
++#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d
++#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e
++#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f
++#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x00000001L
++#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x00000002L
++#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x00000010L
++#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x00000020L
++#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L
++#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L
++#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L
++#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L
++#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x01000000L
++#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x02000000L
++#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x04000000L
++#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x08000000L
++#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000L
++#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000L
++#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L
++#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L
++//CRTC2_CRTC_UPDATE_LOCK
++#define CRTC2_CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0
++#define CRTC2_CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x00000001L
++//CRTC2_CRTC_DOUBLE_BUFFER_CONTROL
++#define CRTC2_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0
++#define CRTC2_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8
++#define CRTC2_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10
++#define CRTC2_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18
++#define CRTC2_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x19
++#define CRTC2_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x00000001L
++#define CRTC2_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x00000100L
++#define CRTC2_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L
++#define CRTC2_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x01000000L
++#define CRTC2_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x02000000L
++//CRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE
++#define CRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0
++#define CRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x00000001L
++//CRTC2_CRTC_TEST_PATTERN_CONTROL
++#define CRTC2_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0
++#define CRTC2_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8
++#define CRTC2_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10
++#define CRTC2_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18
++#define CRTC2_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x00000001L
++#define CRTC2_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x00000700L
++#define CRTC2_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L
++#define CRTC2_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xFF000000L
++//CRTC2_CRTC_TEST_PATTERN_PARAMETERS
++#define CRTC2_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0
++#define CRTC2_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4
++#define CRTC2_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8
++#define CRTC2_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc
++#define CRTC2_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10
++#define CRTC2_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0x0000000FL
++#define CRTC2_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0x000000F0L
++#define CRTC2_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0x00000F00L
++#define CRTC2_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0x0000F000L
++#define CRTC2_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xFFFF0000L
++//CRTC2_CRTC_TEST_PATTERN_COLOR
++#define CRTC2_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0
++#define CRTC2_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10
++#define CRTC2_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0x0000FFFFL
++#define CRTC2_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x003F0000L
++//CRTC2_CRTC_MASTER_UPDATE_LOCK
++#define CRTC2_CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0
++#define CRTC2_CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8
++#define CRTC2_CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK__SHIFT 0x10
++#define CRTC2_CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x00000001L
++#define CRTC2_CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x00000100L
++#define CRTC2_CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK_MASK 0x00010000L
++//CRTC2_CRTC_MASTER_UPDATE_MODE
++#define CRTC2_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0
++#define CRTC2_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10
++#define CRTC2_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x00000007L
++#define CRTC2_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00030000L
++//CRTC2_CRTC_MVP_INBAND_CNTL_INSERT
++#define CRTC2_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0
++#define CRTC2_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8
++#define CRTC2_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x00000003L
++#define CRTC2_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xFFFFFF00L
++//CRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER
++#define CRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0
++#define CRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0x000000FFL
++//CRTC2_CRTC_MVP_STATUS
++#define CRTC2_CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0
++#define CRTC2_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4
++#define CRTC2_CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10
++#define CRTC2_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14
++#define CRTC2_CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x00000001L
++#define CRTC2_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x00000010L
++#define CRTC2_CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x00010000L
++#define CRTC2_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x00100000L
++//CRTC2_CRTC_MASTER_EN
++#define CRTC2_CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0
++#define CRTC2_CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x00000001L
++//CRTC2_CRTC_ALLOW_STOP_OFF_V_CNT
++#define CRTC2_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0
++#define CRTC2_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10
++#define CRTC2_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0x000000FFL
++#define CRTC2_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x00010000L
++//CRTC2_CRTC_V_UPDATE_INT_STATUS
++#define CRTC2_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0
++#define CRTC2_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8
++#define CRTC2_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x00000001L
++#define CRTC2_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x00000100L
++//CRTC2_CRTC_OVERSCAN_COLOR
++#define CRTC2_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0
++#define CRTC2_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa
++#define CRTC2_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14
++#define CRTC2_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x000003FFL
++#define CRTC2_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0x000FFC00L
++#define CRTC2_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3FF00000L
++//CRTC2_CRTC_OVERSCAN_COLOR_EXT
++#define CRTC2_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0
++#define CRTC2_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8
++#define CRTC2_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10
++#define CRTC2_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x00000003L
++#define CRTC2_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x00000300L
++#define CRTC2_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x00030000L
++//CRTC2_CRTC_BLANK_DATA_COLOR
++#define CRTC2_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0
++#define CRTC2_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa
++#define CRTC2_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14
++#define CRTC2_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL
++#define CRTC2_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L
++#define CRTC2_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L
++//CRTC2_CRTC_BLANK_DATA_COLOR_EXT
++#define CRTC2_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0
++#define CRTC2_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8
++#define CRTC2_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10
++#define CRTC2_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x00000003L
++#define CRTC2_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00000300L
++#define CRTC2_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x00030000L
++//CRTC2_CRTC_BLACK_COLOR
++#define CRTC2_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0
++#define CRTC2_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa
++#define CRTC2_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14
++#define CRTC2_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x000003FFL
++#define CRTC2_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0x000FFC00L
++#define CRTC2_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3FF00000L
++//CRTC2_CRTC_BLACK_COLOR_EXT
++#define CRTC2_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0
++#define CRTC2_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8
++#define CRTC2_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10
++#define CRTC2_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x00000003L
++#define CRTC2_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x00000300L
++#define CRTC2_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x00030000L
++//CRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION
++#define CRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0
++#define CRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10
++#define CRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00003FFFL
++#define CRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x3FFF0000L
++//CRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL
++#define CRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4
++#define CRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8
++#define CRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc
++#define CRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10
++#define CRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14
++#define CRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18
++#define CRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L
++#define CRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L
++#define CRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L
++#define CRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L
++#define CRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L
++#define CRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L
++//CRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION
++#define CRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0
++#define CRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00003FFFL
++//CRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL
++#define CRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8
++#define CRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc
++#define CRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10
++#define CRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14
++#define CRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18
++#define CRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L
++#define CRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L
++#define CRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L
++#define CRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L
++#define CRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L
++//CRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION
++#define CRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0
++#define CRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00003FFFL
++//CRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL
++#define CRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8
++#define CRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc
++#define CRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10
++#define CRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14
++#define CRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18
++#define CRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L
++#define CRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L
++#define CRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L
++#define CRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L
++#define CRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L
++//CRTC2_CRTC_CRC_CNTL
++#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0
++#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4
++#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8
++#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc
++#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
++#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14
++#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18
++#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC_EN_MASK 0x00000001L
++#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x00000010L
++#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x00000300L
++#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x00003000L
++#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
++#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x00700000L
++#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x07000000L
++//CRTC2_CRTC_CRC0_WINDOWA_X_CONTROL
++#define CRTC2_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0
++#define CRTC2_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10
++#define CRTC2_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x00003FFFL
++#define CRTC2_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3FFF0000L
++//CRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL
++#define CRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0
++#define CRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10
++#define CRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x00003FFFL
++#define CRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3FFF0000L
++//CRTC2_CRTC_CRC0_WINDOWB_X_CONTROL
++#define CRTC2_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0
++#define CRTC2_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10
++#define CRTC2_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x00003FFFL
++#define CRTC2_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3FFF0000L
++//CRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL
++#define CRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0
++#define CRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10
++#define CRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x00003FFFL
++#define CRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3FFF0000L
++//CRTC2_CRTC_CRC0_DATA_RG
++#define CRTC2_CRTC_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0
++#define CRTC2_CRTC_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10
++#define CRTC2_CRTC_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL
++#define CRTC2_CRTC_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L
++//CRTC2_CRTC_CRC0_DATA_B
++#define CRTC2_CRTC_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0
++#define CRTC2_CRTC_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL
++//CRTC2_CRTC_CRC1_WINDOWA_X_CONTROL
++#define CRTC2_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0
++#define CRTC2_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10
++#define CRTC2_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x00003FFFL
++#define CRTC2_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3FFF0000L
++//CRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL
++#define CRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0
++#define CRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10
++#define CRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x00003FFFL
++#define CRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3FFF0000L
++//CRTC2_CRTC_CRC1_WINDOWB_X_CONTROL
++#define CRTC2_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0
++#define CRTC2_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10
++#define CRTC2_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x00003FFFL
++#define CRTC2_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3FFF0000L
++//CRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL
++#define CRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0
++#define CRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10
++#define CRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x00003FFFL
++#define CRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3FFF0000L
++//CRTC2_CRTC_CRC1_DATA_RG
++#define CRTC2_CRTC_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0
++#define CRTC2_CRTC_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10
++#define CRTC2_CRTC_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL
++#define CRTC2_CRTC_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L
++//CRTC2_CRTC_CRC1_DATA_B
++#define CRTC2_CRTC_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0
++#define CRTC2_CRTC_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL
++//CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL
++#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE__SHIFT 0x0
++#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__SHIFT 0x3
++#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__SHIFT 0x4
++#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__SHIFT 0x5
++#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__SHIFT 0x8
++#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__SHIFT 0x9
++#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__SHIFT 0xc
++#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__SHIFT 0xd
++#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__SHIFT 0xe
++#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE__SHIFT 0x18
++#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE__SHIFT 0x1c
++#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE_MASK 0x00000003L
++#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_MASK 0x00000008L
++#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_MASK 0x00000010L
++#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_MASK 0x00000060L
++#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_MASK 0x00000100L
++#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_MASK 0x00000200L
++#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_MASK 0x00001000L
++#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_MASK 0x00002000L
++#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_MASK 0x00004000L
++#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE_MASK 0x07000000L
++#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE_MASK 0x70000000L
++//CRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START
++#define CRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X__SHIFT 0x0
++#define CRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y__SHIFT 0x10
++#define CRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X_MASK 0x00003FFFL
++#define CRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y_MASK 0x3FFF0000L
++//CRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END
++#define CRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X__SHIFT 0x0
++#define CRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y__SHIFT 0x10
++#define CRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X_MASK 0x00003FFFL
++#define CRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y_MASK 0x3FFF0000L
++//CRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL
++#define CRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__SHIFT 0x0
++#define CRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS__SHIFT 0x4
++#define CRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS__SHIFT 0x8
++#define CRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__SHIFT 0x10
++#define CRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__SHIFT 0x14
++#define CRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__SHIFT 0x1d
++#define CRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_MASK 0x00000001L
++#define CRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS_MASK 0x00000010L
++#define CRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS_MASK 0x00000100L
++#define CRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_MASK 0x00010000L
++#define CRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_MASK 0x00100000L
++#define CRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_MASK 0xE0000000L
++//CRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL
++#define CRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE__SHIFT 0x0
++#define CRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS__SHIFT 0x4
++#define CRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS__SHIFT 0x8
++#define CRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR__SHIFT 0x10
++#define CRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE__SHIFT 0x14
++#define CRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE_MASK 0x00000001L
++#define CRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS_MASK 0x00000010L
++#define CRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS_MASK 0x00000100L
++#define CRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR_MASK 0x00010000L
++#define CRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE_MASK 0x00100000L
++//CRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL
++#define CRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__SHIFT 0x0
++#define CRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS__SHIFT 0x4
++#define CRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS__SHIFT 0x8
++#define CRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__SHIFT 0x10
++#define CRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__SHIFT 0x14
++#define CRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_MASK 0x00000001L
++#define CRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS_MASK 0x00000010L
++#define CRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS_MASK 0x00000100L
++#define CRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_MASK 0x00010000L
++#define CRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_MASK 0x00100000L
++//CRTC2_CRTC_STATIC_SCREEN_CONTROL
++#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0
++#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10
++#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18
++#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19
++#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a
++#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b
++#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c
++#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e
++#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f
++#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL
++#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L
++#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x01000000L
++#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x02000000L
++#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x04000000L
++#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x08000000L
++#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000L
++#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L
++#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L
++//CRTC2_CRTC_3D_STRUCTURE_CONTROL
++#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0
++#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4
++#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8
++#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc
++#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10
++#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11
++#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12
++#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x00000001L
++#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x00000010L
++#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L
++#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L
++#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L
++#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L
++#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L
++//CRTC2_CRTC_GSL_VSYNC_GAP
++#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0
++#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8
++#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10
++#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11
++#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13
++#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14
++#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17
++#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18
++#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL
++#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L
++#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L
++#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x00060000L
++#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L
++#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L
++#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L
++#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xFF000000L
++//CRTC2_CRTC_GSL_WINDOW
++#define CRTC2_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0
++#define CRTC2_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10
++#define CRTC2_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x00003FFFL
++#define CRTC2_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x3FFF0000L
++//CRTC2_CRTC_GSL_CONTROL
++#define CRTC2_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0
++#define CRTC2_CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10
++#define CRTC2_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c
++#define CRTC2_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x00003FFFL
++#define CRTC2_CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x001F0000L
++#define CRTC2_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L
++//CRTC2_CRTC_RANGE_TIMING_INT_STATUS
++#define CRTC2_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0
++#define CRTC2_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4
++#define CRTC2_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8
++#define CRTC2_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc
++#define CRTC2_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10
++#define CRTC2_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L
++#define CRTC2_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L
++#define CRTC2_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L
++#define CRTC2_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L
++#define CRTC2_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L
++//CRTC2_CRTC_DRR_CONTROL
++#define CRTC2_CRTC_DRR_CONTROL__CRTC_XDMA_PREFETCH_DELAY__SHIFT 0x0
++#define CRTC2_CRTC_DRR_CONTROL__CRTC_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0xe
++#define CRTC2_CRTC_DRR_CONTROL__CRTC_SET_V_TOTAL_MIN_AUTO_DIS__SHIFT 0x1c
++#define CRTC2_CRTC_DRR_CONTROL__CRTC_DRR_MODE_DBUF_UPDATE_MODE__SHIFT 0x1d
++#define CRTC2_CRTC_DRR_CONTROL__CRTC_XDMA_PREFETCH_DELAY_MASK 0x00003FFFL
++#define CRTC2_CRTC_DRR_CONTROL__CRTC_V_TOTAL_LAST_USED_BY_DRR_MASK 0x0FFFC000L
++#define CRTC2_CRTC_DRR_CONTROL__CRTC_SET_V_TOTAL_MIN_AUTO_DIS_MASK 0x10000000L
++#define CRTC2_CRTC_DRR_CONTROL__CRTC_DRR_MODE_DBUF_UPDATE_MODE_MASK 0x60000000L
++
++
++// addressBlock: dce_dc_fmt2_dispdec
++//FMT2_FMT_CLAMP_COMPONENT_R
++#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0
++#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10
++#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL
++#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L
++//FMT2_FMT_CLAMP_COMPONENT_G
++#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0
++#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10
++#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL
++#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L
++//FMT2_FMT_CLAMP_COMPONENT_B
++#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0
++#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10
++#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL
++#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L
++//FMT2_FMT_DYNAMIC_EXP_CNTL
++#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0
++#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4
++#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L
++#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L
++//FMT2_FMT_CONTROL
++#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0
++#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT 0x4
++#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8
++#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc
++#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10
++#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12
++#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14
++#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15
++#define FMT2_FMT_CONTROL__FMT_SRC_SELECT__SHIFT 0x18
++#define FMT2_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED__SHIFT 0x1e
++#define FMT2_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_CLEAR__SHIFT 0x1f
++#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L
++#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK 0x00000010L
++#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L
++#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L
++#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L
++#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L
++#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L
++#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L
++#define FMT2_FMT_CONTROL__FMT_SRC_SELECT_MASK 0x07000000L
++#define FMT2_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_MASK 0x40000000L
++#define FMT2_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_CLEAR_MASK 0x80000000L
++//FMT2_FMT_BIT_DEPTH_CONTROL
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L
++//FMT2_FMT_DITHER_RAND_R_SEED
++#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0
++#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10
++#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL
++#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L
++//FMT2_FMT_DITHER_RAND_G_SEED
++#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0
++#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10
++#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL
++#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L
++//FMT2_FMT_DITHER_RAND_B_SEED
++#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0
++#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10
++#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL
++#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L
++//FMT2_FMT_CLAMP_CNTL
++#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0
++#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10
++#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L
++#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L
++//FMT2_FMT_CRC_CNTL
++#define FMT2_FMT_CRC_CNTL__FMT_CRC_EN__SHIFT 0x0
++#define FMT2_FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN__SHIFT 0x1
++#define FMT2_FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT 0x4
++#define FMT2_FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING__SHIFT 0x5
++#define FMT2_FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN__SHIFT 0x6
++#define FMT2_FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB__SHIFT 0x8
++#define FMT2_FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE__SHIFT 0x9
++#define FMT2_FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT 0xc
++#define FMT2_FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
++#define FMT2_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT 0x14
++#define FMT2_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT 0x18
++#define FMT2_FMT_CRC_CNTL__FMT_CRC_EN_MASK 0x00000001L
++#define FMT2_FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN_MASK 0x00000002L
++#define FMT2_FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK 0x00000010L
++#define FMT2_FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING_MASK 0x00000020L
++#define FMT2_FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN_MASK 0x00000040L
++#define FMT2_FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB_MASK 0x00000100L
++#define FMT2_FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE_MASK 0x00000200L
++#define FMT2_FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK 0x00003000L
++#define FMT2_FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
++#define FMT2_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK 0x00100000L
++#define FMT2_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK 0x01000000L
++//FMT2_FMT_CRC_SIG_RED_GREEN_MASK
++#define FMT2_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT 0x0
++#define FMT2_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT 0x10
++#define FMT2_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK 0x0000FFFFL
++#define FMT2_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L
++//FMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK
++#define FMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT 0x0
++#define FMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT 0x10
++#define FMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL
++#define FMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L
++//FMT2_FMT_CRC_SIG_RED_GREEN
++#define FMT2_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT 0x0
++#define FMT2_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT 0x10
++#define FMT2_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK 0x0000FFFFL
++#define FMT2_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK 0xFFFF0000L
++//FMT2_FMT_CRC_SIG_BLUE_CONTROL
++#define FMT2_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT 0x0
++#define FMT2_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT 0x10
++#define FMT2_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK 0x0000FFFFL
++#define FMT2_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK 0xFFFF0000L
++//FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL
++#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0
++#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL
++//FMT2_FMT_420_HBLANK_EARLY_START
++#define FMT2_FMT_420_HBLANK_EARLY_START__FMT_420_HBLANK_EARLY_START__SHIFT 0x0
++#define FMT2_FMT_420_HBLANK_EARLY_START__FMT_420_HBLANK_EARLY_START_MASK 0x00000FFFL
++
++
++// addressBlock: dce_dc_dcp3_dispdec
++//DCP3_GRPH_ENABLE
++#define DCP3_GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0
++#define DCP3_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL__SHIFT 0x1
++#define DCP3_GRPH_ENABLE__GRPH_ENABLE_MASK 0x00000001L
++#define DCP3_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL_MASK 0x00000002L
++//DCP3_GRPH_CONTROL
++#define DCP3_GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0
++#define DCP3_GRPH_CONTROL__GRPH_SE_ENABLE__SHIFT 0x2
++#define DCP3_GRPH_CONTROL__GRPH_Z__SHIFT 0x4
++#define DCP3_GRPH_CONTROL__GRPH_DIM_TYPE__SHIFT 0x6
++#define DCP3_GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8
++#define DCP3_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0xc
++#define DCP3_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10
++#define DCP3_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11
++#define DCP3_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES__SHIFT 0x12
++#define DCP3_GRPH_CONTROL__GRPH_SW_MODE__SHIFT 0x14
++#define DCP3_GRPH_CONTROL__GRPH_NUM_PIPES__SHIFT 0x1c
++#define DCP3_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f
++#define DCP3_GRPH_CONTROL__GRPH_DEPTH_MASK 0x00000003L
++#define DCP3_GRPH_CONTROL__GRPH_SE_ENABLE_MASK 0x00000004L
++#define DCP3_GRPH_CONTROL__GRPH_Z_MASK 0x00000030L
++#define DCP3_GRPH_CONTROL__GRPH_DIM_TYPE_MASK 0x000000C0L
++#define DCP3_GRPH_CONTROL__GRPH_FORMAT_MASK 0x00000700L
++#define DCP3_GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0x00007000L
++#define DCP3_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x00010000L
++#define DCP3_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x00020000L
++#define DCP3_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES_MASK 0x000C0000L
++#define DCP3_GRPH_CONTROL__GRPH_SW_MODE_MASK 0x01F00000L
++#define DCP3_GRPH_CONTROL__GRPH_NUM_PIPES_MASK 0x70000000L
++#define DCP3_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000L
++//DCP3_GRPH_LUT_10BIT_BYPASS
++#define DCP3_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT 0x8
++#define DCP3_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x10
++#define DCP3_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK 0x00000100L
++#define DCP3_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x00010000L
++//DCP3_GRPH_SWAP_CNTL
++#define DCP3_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0
++#define DCP3_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4
++#define DCP3_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6
++#define DCP3_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8
++#define DCP3_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT 0xa
++#define DCP3_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x00000003L
++#define DCP3_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x00000030L
++#define DCP3_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0x000000C0L
++#define DCP3_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x00000300L
++#define DCP3_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK 0x00000C00L
++//DCP3_GRPH_PRIMARY_SURFACE_ADDRESS
++#define DCP3_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT 0x0
++#define DCP3_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT 0x8
++#define DCP3_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK 0x00000001L
++#define DCP3_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
++//DCP3_GRPH_SECONDARY_SURFACE_ADDRESS
++#define DCP3_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT 0x0
++#define DCP3_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8
++#define DCP3_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK 0x00000001L
++#define DCP3_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
++//DCP3_GRPH_PITCH
++#define DCP3_GRPH_PITCH__GRPH_PITCH__SHIFT 0x0
++#define DCP3_GRPH_PITCH__GRPH_PITCH_MASK 0x00007FFFL
++//DCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
++#define DCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define DCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
++//DCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
++#define DCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define DCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
++//DCP3_GRPH_SURFACE_OFFSET_X
++#define DCP3_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT 0x0
++#define DCP3_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK 0x00003FFFL
++//DCP3_GRPH_SURFACE_OFFSET_Y
++#define DCP3_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT 0x0
++#define DCP3_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK 0x00003FFFL
++//DCP3_GRPH_X_START
++#define DCP3_GRPH_X_START__GRPH_X_START__SHIFT 0x0
++#define DCP3_GRPH_X_START__GRPH_X_START_MASK 0x00003FFFL
++//DCP3_GRPH_Y_START
++#define DCP3_GRPH_Y_START__GRPH_Y_START__SHIFT 0x0
++#define DCP3_GRPH_Y_START__GRPH_Y_START_MASK 0x00003FFFL
++//DCP3_GRPH_X_END
++#define DCP3_GRPH_X_END__GRPH_X_END__SHIFT 0x0
++#define DCP3_GRPH_X_END__GRPH_X_END_MASK 0x00007FFFL
++//DCP3_GRPH_Y_END
++#define DCP3_GRPH_Y_END__GRPH_Y_END__SHIFT 0x0
++#define DCP3_GRPH_Y_END__GRPH_Y_END_MASK 0x00007FFFL
++//DCP3_INPUT_GAMMA_CONTROL
++#define DCP3_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x0
++#define DCP3_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK 0x00000001L
++//DCP3_GRPH_UPDATE
++#define DCP3_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0
++#define DCP3_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1
++#define DCP3_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2
++#define DCP3_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3
++#define DCP3_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR__SHIFT 0x8
++#define DCP3_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE__SHIFT 0x9
++#define DCP3_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE__SHIFT 0xa
++#define DCP3_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10
++#define DCP3_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14
++#define DCP3_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
++#define DCP3_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c
++#define DCP3_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x00000001L
++#define DCP3_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x00000002L
++#define DCP3_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x00000004L
++#define DCP3_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x00000008L
++#define DCP3_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR_MASK 0x00000100L
++#define DCP3_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE_MASK 0x00000200L
++#define DCP3_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE_MASK 0x00000400L
++#define DCP3_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x00010000L
++#define DCP3_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x00100000L
++#define DCP3_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
++#define DCP3_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000L
++//DCP3_GRPH_FLIP_CONTROL
++#define DCP3_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT 0x0
++#define DCP3_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN__SHIFT 0x1
++#define DCP3_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN__SHIFT 0x4
++#define DCP3_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT 0x5
++#define DCP3_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK 0x00000001L
++#define DCP3_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN_MASK 0x00000002L
++#define DCP3_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN_MASK 0x00000010L
++#define DCP3_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK 0x00000020L
++//DCP3_GRPH_SURFACE_ADDRESS_INUSE
++#define DCP3_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT 0x8
++#define DCP3_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK 0xFFFFFF00L
++//DCP3_GRPH_DFQ_CONTROL
++#define DCP3_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x0
++#define DCP3_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x4
++#define DCP3_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8
++#define DCP3_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x00000001L
++#define DCP3_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x00000070L
++#define DCP3_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x00000700L
++//DCP3_GRPH_DFQ_STATUS
++#define DCP3_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x0
++#define DCP3_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4
++#define DCP3_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x8
++#define DCP3_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x9
++#define DCP3_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0x0000000FL
++#define DCP3_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0x000000F0L
++#define DCP3_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x00000100L
++#define DCP3_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x00000200L
++//DCP3_GRPH_INTERRUPT_STATUS
++#define DCP3_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0
++#define DCP3_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8
++#define DCP3_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x00000001L
++#define DCP3_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x00000100L
++//DCP3_GRPH_INTERRUPT_CONTROL
++#define DCP3_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0
++#define DCP3_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8
++#define DCP3_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x00000001L
++#define DCP3_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x00000100L
++//DCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE
++#define DCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0
++#define DCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK 0x000000FFL
++//DCP3_GRPH_COMPRESS_SURFACE_ADDRESS
++#define DCP3_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT 0x8
++#define DCP3_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK 0xFFFFFF00L
++//DCP3_GRPH_COMPRESS_PITCH
++#define DCP3_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT 0x6
++#define DCP3_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK 0x0001FFC0L
++//DCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH
++#define DCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define DCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
++//DCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT
++#define DCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__SHIFT 0x0
++#define DCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_MASK 0x000000FFL
++//DCP3_PRESCALE_GRPH_CONTROL
++#define DCP3_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT 0x0
++#define DCP3_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT 0x1
++#define DCP3_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x2
++#define DCP3_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT 0x3
++#define DCP3_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT 0x4
++#define DCP3_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK 0x00000001L
++#define DCP3_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x00000002L
++#define DCP3_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK 0x00000004L
++#define DCP3_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK 0x00000008L
++#define DCP3_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK 0x00000010L
++//DCP3_PRESCALE_VALUES_GRPH_R
++#define DCP3_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT 0x0
++#define DCP3_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT 0x10
++#define DCP3_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK 0x0000FFFFL
++#define DCP3_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK 0xFFFF0000L
++//DCP3_PRESCALE_VALUES_GRPH_G
++#define DCP3_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT 0x0
++#define DCP3_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT 0x10
++#define DCP3_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK 0x0000FFFFL
++#define DCP3_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK 0xFFFF0000L
++//DCP3_PRESCALE_VALUES_GRPH_B
++#define DCP3_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT 0x0
++#define DCP3_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT 0x10
++#define DCP3_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK 0x0000FFFFL
++#define DCP3_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK 0xFFFF0000L
++//DCP3_INPUT_CSC_CONTROL
++#define DCP3_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT 0x0
++#define DCP3_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK 0x00000003L
++//DCP3_INPUT_CSC_C11_C12
++#define DCP3_INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT 0x0
++#define DCP3_INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT 0x10
++#define DCP3_INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK 0x0000FFFFL
++#define DCP3_INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK 0xFFFF0000L
++//DCP3_INPUT_CSC_C13_C14
++#define DCP3_INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT 0x0
++#define DCP3_INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT 0x10
++#define DCP3_INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK 0x0000FFFFL
++#define DCP3_INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK 0xFFFF0000L
++//DCP3_INPUT_CSC_C21_C22
++#define DCP3_INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT 0x0
++#define DCP3_INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT 0x10
++#define DCP3_INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK 0x0000FFFFL
++#define DCP3_INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK 0xFFFF0000L
++//DCP3_INPUT_CSC_C23_C24
++#define DCP3_INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT 0x0
++#define DCP3_INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT 0x10
++#define DCP3_INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK 0x0000FFFFL
++#define DCP3_INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK 0xFFFF0000L
++//DCP3_INPUT_CSC_C31_C32
++#define DCP3_INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT 0x0
++#define DCP3_INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT 0x10
++#define DCP3_INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK 0x0000FFFFL
++#define DCP3_INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK 0xFFFF0000L
++//DCP3_INPUT_CSC_C33_C34
++#define DCP3_INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT 0x0
++#define DCP3_INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT 0x10
++#define DCP3_INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK 0x0000FFFFL
++#define DCP3_INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK 0xFFFF0000L
++//DCP3_OUTPUT_CSC_CONTROL
++#define DCP3_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT 0x0
++#define DCP3_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK 0x00000007L
++//DCP3_OUTPUT_CSC_C11_C12
++#define DCP3_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT 0x0
++#define DCP3_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT 0x10
++#define DCP3_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK 0x0000FFFFL
++#define DCP3_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK 0xFFFF0000L
++//DCP3_OUTPUT_CSC_C13_C14
++#define DCP3_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT 0x0
++#define DCP3_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT 0x10
++#define DCP3_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK 0x0000FFFFL
++#define DCP3_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK 0xFFFF0000L
++//DCP3_OUTPUT_CSC_C21_C22
++#define DCP3_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT 0x0
++#define DCP3_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT 0x10
++#define DCP3_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK 0x0000FFFFL
++#define DCP3_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK 0xFFFF0000L
++//DCP3_OUTPUT_CSC_C23_C24
++#define DCP3_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT 0x0
++#define DCP3_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT 0x10
++#define DCP3_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK 0x0000FFFFL
++#define DCP3_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK 0xFFFF0000L
++//DCP3_OUTPUT_CSC_C31_C32
++#define DCP3_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT 0x0
++#define DCP3_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT 0x10
++#define DCP3_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK 0x0000FFFFL
++#define DCP3_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK 0xFFFF0000L
++//DCP3_OUTPUT_CSC_C33_C34
++#define DCP3_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT 0x0
++#define DCP3_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT 0x10
++#define DCP3_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK 0x0000FFFFL
++#define DCP3_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK 0xFFFF0000L
++//DCP3_COMM_MATRIXA_TRANS_C11_C12
++#define DCP3_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT 0x0
++#define DCP3_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT 0x10
++#define DCP3_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK 0x0000FFFFL
++#define DCP3_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK 0xFFFF0000L
++//DCP3_COMM_MATRIXA_TRANS_C13_C14
++#define DCP3_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT 0x0
++#define DCP3_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT 0x10
++#define DCP3_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK 0x0000FFFFL
++#define DCP3_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK 0xFFFF0000L
++//DCP3_COMM_MATRIXA_TRANS_C21_C22
++#define DCP3_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT 0x0
++#define DCP3_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT 0x10
++#define DCP3_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK 0x0000FFFFL
++#define DCP3_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK 0xFFFF0000L
++//DCP3_COMM_MATRIXA_TRANS_C23_C24
++#define DCP3_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT 0x0
++#define DCP3_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT 0x10
++#define DCP3_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK 0x0000FFFFL
++#define DCP3_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK 0xFFFF0000L
++//DCP3_COMM_MATRIXA_TRANS_C31_C32
++#define DCP3_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT 0x0
++#define DCP3_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT 0x10
++#define DCP3_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK 0x0000FFFFL
++#define DCP3_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK 0xFFFF0000L
++//DCP3_COMM_MATRIXA_TRANS_C33_C34
++#define DCP3_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT 0x0
++#define DCP3_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT 0x10
++#define DCP3_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK 0x0000FFFFL
++#define DCP3_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK 0xFFFF0000L
++//DCP3_COMM_MATRIXB_TRANS_C11_C12
++#define DCP3_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT 0x0
++#define DCP3_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT 0x10
++#define DCP3_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK 0x0000FFFFL
++#define DCP3_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK 0xFFFF0000L
++//DCP3_COMM_MATRIXB_TRANS_C13_C14
++#define DCP3_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT 0x0
++#define DCP3_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT 0x10
++#define DCP3_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK 0x0000FFFFL
++#define DCP3_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK 0xFFFF0000L
++//DCP3_COMM_MATRIXB_TRANS_C21_C22
++#define DCP3_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT 0x0
++#define DCP3_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT 0x10
++#define DCP3_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK 0x0000FFFFL
++#define DCP3_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK 0xFFFF0000L
++//DCP3_COMM_MATRIXB_TRANS_C23_C24
++#define DCP3_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT 0x0
++#define DCP3_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT 0x10
++#define DCP3_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK 0x0000FFFFL
++#define DCP3_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK 0xFFFF0000L
++//DCP3_COMM_MATRIXB_TRANS_C31_C32
++#define DCP3_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT 0x0
++#define DCP3_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT 0x10
++#define DCP3_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK 0x0000FFFFL
++#define DCP3_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK 0xFFFF0000L
++//DCP3_COMM_MATRIXB_TRANS_C33_C34
++#define DCP3_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT 0x0
++#define DCP3_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT 0x10
++#define DCP3_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK 0x0000FFFFL
++#define DCP3_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK 0xFFFF0000L
++//DCP3_DENORM_CONTROL
++#define DCP3_DENORM_CONTROL__DENORM_MODE__SHIFT 0x0
++#define DCP3_DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT 0x4
++#define DCP3_DENORM_CONTROL__DENORM_MODE_MASK 0x00000007L
++#define DCP3_DENORM_CONTROL__DENORM_14BIT_OUT_MASK 0x00000010L
++//DCP3_OUT_ROUND_CONTROL
++#define DCP3_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT 0x0
++#define DCP3_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK 0x0000000FL
++//DCP3_OUT_CLAMP_CONTROL_R_CR
++#define DCP3_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT 0x0
++#define DCP3_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT 0x10
++#define DCP3_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK 0x00003FFFL
++#define DCP3_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK 0x3FFF0000L
++//DCP3_OUT_CLAMP_CONTROL_G_Y
++#define DCP3_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT 0x0
++#define DCP3_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT 0x10
++#define DCP3_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK 0x00003FFFL
++#define DCP3_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK 0x3FFF0000L
++//DCP3_OUT_CLAMP_CONTROL_B_CB
++#define DCP3_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT 0x0
++#define DCP3_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT 0x10
++#define DCP3_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK 0x00003FFFL
++#define DCP3_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK 0x3FFF0000L
++//DCP3_KEY_CONTROL
++#define DCP3_KEY_CONTROL__KEY_MODE__SHIFT 0x1
++#define DCP3_KEY_CONTROL__KEY_MODE_MASK 0x00000006L
++//DCP3_KEY_RANGE_ALPHA
++#define DCP3_KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT 0x0
++#define DCP3_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT 0x10
++#define DCP3_KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK 0x0000FFFFL
++#define DCP3_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK 0xFFFF0000L
++//DCP3_KEY_RANGE_RED
++#define DCP3_KEY_RANGE_RED__KEY_RED_LOW__SHIFT 0x0
++#define DCP3_KEY_RANGE_RED__KEY_RED_HIGH__SHIFT 0x10
++#define DCP3_KEY_RANGE_RED__KEY_RED_LOW_MASK 0x0000FFFFL
++#define DCP3_KEY_RANGE_RED__KEY_RED_HIGH_MASK 0xFFFF0000L
++//DCP3_KEY_RANGE_GREEN
++#define DCP3_KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT 0x0
++#define DCP3_KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT 0x10
++#define DCP3_KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK 0x0000FFFFL
++#define DCP3_KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK 0xFFFF0000L
++//DCP3_KEY_RANGE_BLUE
++#define DCP3_KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT 0x0
++#define DCP3_KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT 0x10
++#define DCP3_KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK 0x0000FFFFL
++#define DCP3_KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK 0xFFFF0000L
++//DCP3_DEGAMMA_CONTROL
++#define DCP3_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x0
++#define DCP3_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT 0x8
++#define DCP3_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0xc
++#define DCP3_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x00000003L
++#define DCP3_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK 0x00000300L
++#define DCP3_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK 0x00003000L
++//DCP3_GAMUT_REMAP_CONTROL
++#define DCP3_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT 0x0
++#define DCP3_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK 0x00000003L
++//DCP3_GAMUT_REMAP_C11_C12
++#define DCP3_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT 0x0
++#define DCP3_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT 0x10
++#define DCP3_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK 0x0000FFFFL
++#define DCP3_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK 0xFFFF0000L
++//DCP3_GAMUT_REMAP_C13_C14
++#define DCP3_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT 0x0
++#define DCP3_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT 0x10
++#define DCP3_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK 0x0000FFFFL
++#define DCP3_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK 0xFFFF0000L
++//DCP3_GAMUT_REMAP_C21_C22
++#define DCP3_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT 0x0
++#define DCP3_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT 0x10
++#define DCP3_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK 0x0000FFFFL
++#define DCP3_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK 0xFFFF0000L
++//DCP3_GAMUT_REMAP_C23_C24
++#define DCP3_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT 0x0
++#define DCP3_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT 0x10
++#define DCP3_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK 0x0000FFFFL
++#define DCP3_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK 0xFFFF0000L
++//DCP3_GAMUT_REMAP_C31_C32
++#define DCP3_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT 0x0
++#define DCP3_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT 0x10
++#define DCP3_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK 0x0000FFFFL
++#define DCP3_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK 0xFFFF0000L
++//DCP3_GAMUT_REMAP_C33_C34
++#define DCP3_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT 0x0
++#define DCP3_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT 0x10
++#define DCP3_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK 0x0000FFFFL
++#define DCP3_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK 0xFFFF0000L
++//DCP3_DCP_SPATIAL_DITHER_CNTL
++#define DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT 0x0
++#define DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT 0x4
++#define DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT 0x6
++#define DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT 0x8
++#define DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT 0x9
++#define DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT 0xa
++#define DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK 0x00000001L
++#define DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK 0x00000030L
++#define DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK 0x000000C0L
++#define DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK 0x00000100L
++#define DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK 0x00000200L
++#define DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK 0x00000400L
++//DCP3_DCP_RANDOM_SEEDS
++#define DCP3_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT 0x0
++#define DCP3_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT 0x8
++#define DCP3_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT 0x10
++#define DCP3_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK 0x000000FFL
++#define DCP3_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK 0x0000FF00L
++#define DCP3_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK 0x00FF0000L
++//DCP3_DCP_FP_CONVERTED_FIELD
++#define DCP3_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT 0x0
++#define DCP3_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14
++#define DCP3_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK 0x0003FFFFL
++#define DCP3_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK 0x07F00000L
++//DCP3_CUR_CONTROL
++#define DCP3_CUR_CONTROL__CURSOR_EN__SHIFT 0x0
++#define DCP3_CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT 0x4
++#define DCP3_CUR_CONTROL__CURSOR_MODE__SHIFT 0x8
++#define DCP3_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM__SHIFT 0xb
++#define DCP3_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION__SHIFT 0xc
++#define DCP3_CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x10
++#define DCP3_CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT 0x14
++#define DCP3_CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT 0x18
++#define DCP3_CUR_CONTROL__CURSOR_EN_MASK 0x00000001L
++#define DCP3_CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK 0x00000010L
++#define DCP3_CUR_CONTROL__CURSOR_MODE_MASK 0x00000300L
++#define DCP3_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM_MASK 0x00000800L
++#define DCP3_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION_MASK 0x0000F000L
++#define DCP3_CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00010000L
++#define DCP3_CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK 0x00100000L
++#define DCP3_CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK 0x07000000L
++//DCP3_CUR_SURFACE_ADDRESS
++#define DCP3_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0
++#define DCP3_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
++//DCP3_CUR_SIZE
++#define DCP3_CUR_SIZE__CURSOR_HEIGHT__SHIFT 0x0
++#define DCP3_CUR_SIZE__CURSOR_WIDTH__SHIFT 0x10
++#define DCP3_CUR_SIZE__CURSOR_HEIGHT_MASK 0x0000007FL
++#define DCP3_CUR_SIZE__CURSOR_WIDTH_MASK 0x007F0000L
++//DCP3_CUR_SURFACE_ADDRESS_HIGH
++#define DCP3_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define DCP3_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
++//DCP3_CUR_POSITION
++#define DCP3_CUR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0
++#define DCP3_CUR_POSITION__CURSOR_X_POSITION__SHIFT 0x10
++#define DCP3_CUR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL
++#define DCP3_CUR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L
++//DCP3_CUR_HOT_SPOT
++#define DCP3_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0
++#define DCP3_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10
++#define DCP3_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x0000007FL
++#define DCP3_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x007F0000L
++//DCP3_CUR_COLOR1
++#define DCP3_CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT 0x0
++#define DCP3_CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT 0x8
++#define DCP3_CUR_COLOR1__CUR_COLOR1_RED__SHIFT 0x10
++#define DCP3_CUR_COLOR1__CUR_COLOR1_BLUE_MASK 0x000000FFL
++#define DCP3_CUR_COLOR1__CUR_COLOR1_GREEN_MASK 0x0000FF00L
++#define DCP3_CUR_COLOR1__CUR_COLOR1_RED_MASK 0x00FF0000L
++//DCP3_CUR_COLOR2
++#define DCP3_CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT 0x0
++#define DCP3_CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT 0x8
++#define DCP3_CUR_COLOR2__CUR_COLOR2_RED__SHIFT 0x10
++#define DCP3_CUR_COLOR2__CUR_COLOR2_BLUE_MASK 0x000000FFL
++#define DCP3_CUR_COLOR2__CUR_COLOR2_GREEN_MASK 0x0000FF00L
++#define DCP3_CUR_COLOR2__CUR_COLOR2_RED_MASK 0x00FF0000L
++//DCP3_CUR_UPDATE
++#define DCP3_CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT 0x0
++#define DCP3_CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT 0x1
++#define DCP3_CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT 0x10
++#define DCP3_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
++#define DCP3_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE__SHIFT 0x19
++#define DCP3_CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK 0x00000001L
++#define DCP3_CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x00000002L
++#define DCP3_CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK 0x00010000L
++#define DCP3_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
++#define DCP3_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE_MASK 0x06000000L
++//DCP3_CUR_REQUEST_FILTER_CNTL
++#define DCP3_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT 0x0
++#define DCP3_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK 0x00000001L
++//DCP3_CUR_STEREO_CONTROL
++#define DCP3_CUR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0
++#define DCP3_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4
++#define DCP3_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x10
++#define DCP3_CUR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L
++#define DCP3_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x00003FF0L
++#define DCP3_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0x03FF0000L
++//DCP3_DC_LUT_RW_MODE
++#define DCP3_DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT 0x0
++#define DCP3_DC_LUT_RW_MODE__DC_LUT_ERROR__SHIFT 0x10
++#define DCP3_DC_LUT_RW_MODE__DC_LUT_ERROR_RST__SHIFT 0x11
++#define DCP3_DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK 0x00000001L
++#define DCP3_DC_LUT_RW_MODE__DC_LUT_ERROR_MASK 0x00010000L
++#define DCP3_DC_LUT_RW_MODE__DC_LUT_ERROR_RST_MASK 0x00020000L
++//DCP3_DC_LUT_RW_INDEX
++#define DCP3_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT 0x0
++#define DCP3_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK 0x000000FFL
++//DCP3_DC_LUT_SEQ_COLOR
++#define DCP3_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT 0x0
++#define DCP3_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK 0x0000FFFFL
++//DCP3_DC_LUT_PWL_DATA
++#define DCP3_DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT 0x0
++#define DCP3_DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT 0x10
++#define DCP3_DC_LUT_PWL_DATA__DC_LUT_BASE_MASK 0x0000FFFFL
++#define DCP3_DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK 0xFFFF0000L
++//DCP3_DC_LUT_30_COLOR
++#define DCP3_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT 0x0
++#define DCP3_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT 0xa
++#define DCP3_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT 0x14
++#define DCP3_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK 0x000003FFL
++#define DCP3_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK 0x000FFC00L
++#define DCP3_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK 0x3FF00000L
++//DCP3_DC_LUT_VGA_ACCESS_ENABLE
++#define DCP3_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT 0x0
++#define DCP3_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK 0x00000001L
++//DCP3_DC_LUT_WRITE_EN_MASK
++#define DCP3_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT 0x0
++#define DCP3_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK 0x00000007L
++//DCP3_DC_LUT_AUTOFILL
++#define DCP3_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT 0x0
++#define DCP3_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT 0x1
++#define DCP3_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK 0x00000001L
++#define DCP3_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x00000002L
++//DCP3_DC_LUT_CONTROL
++#define DCP3_DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT 0x0
++#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT 0x4
++#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT 0x5
++#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT 0x6
++#define DCP3_DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT 0x8
++#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT 0xc
++#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT 0xd
++#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT 0xe
++#define DCP3_DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT 0x10
++#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT 0x14
++#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT 0x15
++#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT 0x16
++#define DCP3_DC_LUT_CONTROL__DC_LUT_INC_B_MASK 0x0000000FL
++#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK 0x00000010L
++#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK 0x00000020L
++#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK 0x000000C0L
++#define DCP3_DC_LUT_CONTROL__DC_LUT_INC_G_MASK 0x00000F00L
++#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK 0x00001000L
++#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK 0x00002000L
++#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK 0x0000C000L
++#define DCP3_DC_LUT_CONTROL__DC_LUT_INC_R_MASK 0x000F0000L
++#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK 0x00100000L
++#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK 0x00200000L
++#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK 0x00C00000L
++//DCP3_DC_LUT_BLACK_OFFSET_BLUE
++#define DCP3_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0
++#define DCP3_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK 0x0000FFFFL
++//DCP3_DC_LUT_BLACK_OFFSET_GREEN
++#define DCP3_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0
++#define DCP3_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK 0x0000FFFFL
++//DCP3_DC_LUT_BLACK_OFFSET_RED
++#define DCP3_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT 0x0
++#define DCP3_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK 0x0000FFFFL
++//DCP3_DC_LUT_WHITE_OFFSET_BLUE
++#define DCP3_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT 0x0
++#define DCP3_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK 0x0000FFFFL
++//DCP3_DC_LUT_WHITE_OFFSET_GREEN
++#define DCP3_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT 0x0
++#define DCP3_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK 0x0000FFFFL
++//DCP3_DC_LUT_WHITE_OFFSET_RED
++#define DCP3_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT 0x0
++#define DCP3_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK 0x0000FFFFL
++//DCP3_DCP_CRC_CONTROL
++#define DCP3_DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT 0x0
++#define DCP3_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x2
++#define DCP3_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT 0x8
++#define DCP3_DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK 0x00000001L
++#define DCP3_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK 0x0000001CL
++#define DCP3_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK 0x00000300L
++//DCP3_DCP_CRC_MASK
++#define DCP3_DCP_CRC_MASK__DCP_CRC_MASK__SHIFT 0x0
++#define DCP3_DCP_CRC_MASK__DCP_CRC_MASK_MASK 0xFFFFFFFFL
++//DCP3_DCP_CRC_CURRENT
++#define DCP3_DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT 0x0
++#define DCP3_DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK 0xFFFFFFFFL
++//DCP3_DVMM_PTE_CONTROL
++#define DCP3_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT 0x0
++#define DCP3_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT 0x1
++#define DCP3_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT 0x5
++#define DCP3_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT 0x9
++#define DCP3_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT 0x14
++#define DCP3_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT 0x15
++#define DCP3_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK 0x00000001L
++#define DCP3_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK 0x0000001EL
++#define DCP3_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK 0x000001E0L
++#define DCP3_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK 0x0007FE00L
++#define DCP3_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK 0x00100000L
++#define DCP3_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK 0x00200000L
++//DCP3_DCP_CRC_LAST
++#define DCP3_DCP_CRC_LAST__DCP_CRC_LAST__SHIFT 0x0
++#define DCP3_DCP_CRC_LAST__DCP_CRC_LAST_MASK 0xFFFFFFFFL
++//DCP3_DVMM_PTE_ARB_CONTROL
++#define DCP3_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT 0x0
++#define DCP3_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT 0x8
++#define DCP3_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK 0x0000003FL
++#define DCP3_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK 0x0000FF00L
++//DCP3_GRPH_FLIP_RATE_CNTL
++#define DCP3_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT 0x0
++#define DCP3_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT 0x3
++#define DCP3_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK 0x00000007L
++#define DCP3_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK 0x00000008L
++//DCP3_DCP_GSL_CONTROL
++#define DCP3_DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT 0x0
++#define DCP3_DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT 0x1
++#define DCP3_DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x2
++#define DCP3_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT 0x4
++#define DCP3_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT 0x14
++#define DCP3_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP__SHIFT 0x15
++#define DCP3_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN__SHIFT 0x17
++#define DCP3_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT 0x18
++#define DCP3_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC__SHIFT 0x1a
++#define DCP3_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT 0x1b
++#define DCP3_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT 0x1c
++#define DCP3_DCP_GSL_CONTROL__DCP_GSL0_EN_MASK 0x00000001L
++#define DCP3_DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x00000002L
++#define DCP3_DCP_GSL_CONTROL__DCP_GSL2_EN_MASK 0x00000004L
++#define DCP3_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK 0x000FFFF0L
++#define DCP3_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK 0x00100000L
++#define DCP3_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_MASK 0x00600000L
++#define DCP3_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_MASK 0x00800000L
++#define DCP3_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK 0x03000000L
++#define DCP3_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_MASK 0x04000000L
++#define DCP3_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK 0x08000000L
++#define DCP3_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK 0xF0000000L
++//DCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK
++#define DCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT 0x0
++#define DCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT 0x4
++#define DCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK 0x0000000FL
++#define DCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK 0x000001F0L
++//DCP3_GRPH_STEREOSYNC_FLIP
++#define DCP3_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0
++#define DCP3_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x8
++#define DCP3_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10
++#define DCP3_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11
++#define DCP3_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c
++#define DCP3_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x00000001L
++#define DCP3_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x00000300L
++#define DCP3_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x00010000L
++#define DCP3_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x00020000L
++#define DCP3_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000L
++//DCP3_HW_ROTATION
++#define DCP3_HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT 0x0
++#define DCP3_HW_ROTATION__GRPH_ROTATION_ANGLE_MASK 0x00000007L
++//DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL
++#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT 0x0
++#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT 0x1
++#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT 0x4
++#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK 0x00000001L
++#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK 0x00000002L
++#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK 0x0001FFF0L
++//DCP3_REGAMMA_CONTROL
++#define DCP3_REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT 0x0
++#define DCP3_REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK 0x00000007L
++//DCP3_REGAMMA_LUT_INDEX
++#define DCP3_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x0
++#define DCP3_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK 0x000001FFL
++//DCP3_REGAMMA_LUT_DATA
++#define DCP3_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT 0x0
++#define DCP3_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK 0x0007FFFFL
++//DCP3_REGAMMA_LUT_WRITE_EN_MASK
++#define DCP3_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x0
++#define DCP3_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x00000007L
++//DCP3_REGAMMA_CNTLA_START_CNTL
++#define DCP3_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x0
++#define DCP3_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14
++#define DCP3_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK 0x0003FFFFL
++#define DCP3_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
++//DCP3_REGAMMA_CNTLA_SLOPE_CNTL
++#define DCP3_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
++#define DCP3_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
++//DCP3_REGAMMA_CNTLA_END_CNTL1
++#define DCP3_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x0
++#define DCP3_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK 0x0000FFFFL
++//DCP3_REGAMMA_CNTLA_END_CNTL2
++#define DCP3_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0
++#define DCP3_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10
++#define DCP3_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
++#define DCP3_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xFFFF0000L
++//DCP3_REGAMMA_CNTLA_REGION_0_1
++#define DCP3_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
++#define DCP3_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
++#define DCP3_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
++#define DCP3_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP3_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
++#define DCP3_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP3_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP3_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
++//DCP3_REGAMMA_CNTLA_REGION_2_3
++#define DCP3_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
++#define DCP3_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
++#define DCP3_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
++#define DCP3_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP3_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
++#define DCP3_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP3_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP3_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
++//DCP3_REGAMMA_CNTLA_REGION_4_5
++#define DCP3_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
++#define DCP3_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
++#define DCP3_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
++#define DCP3_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP3_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
++#define DCP3_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP3_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP3_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
++//DCP3_REGAMMA_CNTLA_REGION_6_7
++#define DCP3_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
++#define DCP3_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
++#define DCP3_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
++#define DCP3_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP3_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
++#define DCP3_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP3_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP3_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
++//DCP3_REGAMMA_CNTLA_REGION_8_9
++#define DCP3_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
++#define DCP3_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
++#define DCP3_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
++#define DCP3_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP3_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
++#define DCP3_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP3_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP3_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
++//DCP3_REGAMMA_CNTLA_REGION_10_11
++#define DCP3_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
++#define DCP3_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
++#define DCP3_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
++#define DCP3_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP3_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
++#define DCP3_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP3_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP3_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
++//DCP3_REGAMMA_CNTLA_REGION_12_13
++#define DCP3_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
++#define DCP3_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
++#define DCP3_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
++#define DCP3_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP3_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
++#define DCP3_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP3_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP3_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
++//DCP3_REGAMMA_CNTLA_REGION_14_15
++#define DCP3_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
++#define DCP3_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
++#define DCP3_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
++#define DCP3_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP3_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
++#define DCP3_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP3_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP3_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
++//DCP3_REGAMMA_CNTLB_START_CNTL
++#define DCP3_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x0
++#define DCP3_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14
++#define DCP3_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK 0x0003FFFFL
++#define DCP3_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
++//DCP3_REGAMMA_CNTLB_SLOPE_CNTL
++#define DCP3_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
++#define DCP3_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
++//DCP3_REGAMMA_CNTLB_END_CNTL1
++#define DCP3_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x0
++#define DCP3_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK 0x0000FFFFL
++//DCP3_REGAMMA_CNTLB_END_CNTL2
++#define DCP3_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0
++#define DCP3_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10
++#define DCP3_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
++#define DCP3_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xFFFF0000L
++//DCP3_REGAMMA_CNTLB_REGION_0_1
++#define DCP3_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
++#define DCP3_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
++#define DCP3_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
++#define DCP3_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP3_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
++#define DCP3_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP3_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP3_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
++//DCP3_REGAMMA_CNTLB_REGION_2_3
++#define DCP3_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
++#define DCP3_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
++#define DCP3_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
++#define DCP3_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP3_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
++#define DCP3_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP3_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP3_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
++//DCP3_REGAMMA_CNTLB_REGION_4_5
++#define DCP3_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
++#define DCP3_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
++#define DCP3_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
++#define DCP3_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP3_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
++#define DCP3_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP3_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP3_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
++//DCP3_REGAMMA_CNTLB_REGION_6_7
++#define DCP3_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
++#define DCP3_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
++#define DCP3_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
++#define DCP3_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP3_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
++#define DCP3_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP3_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP3_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
++//DCP3_REGAMMA_CNTLB_REGION_8_9
++#define DCP3_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
++#define DCP3_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
++#define DCP3_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
++#define DCP3_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP3_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
++#define DCP3_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP3_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP3_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
++//DCP3_REGAMMA_CNTLB_REGION_10_11
++#define DCP3_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
++#define DCP3_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
++#define DCP3_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
++#define DCP3_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP3_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
++#define DCP3_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP3_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP3_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
++//DCP3_REGAMMA_CNTLB_REGION_12_13
++#define DCP3_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
++#define DCP3_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
++#define DCP3_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
++#define DCP3_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP3_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
++#define DCP3_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP3_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP3_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
++//DCP3_REGAMMA_CNTLB_REGION_14_15
++#define DCP3_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
++#define DCP3_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
++#define DCP3_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
++#define DCP3_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP3_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
++#define DCP3_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP3_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP3_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
++//DCP3_ALPHA_CONTROL
++#define DCP3_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT 0x0
++#define DCP3_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT 0x1
++#define DCP3_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK 0x00000001L
++#define DCP3_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK 0x00000002L
++//DCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS
++#define DCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT 0x8
++#define DCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
++//DCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH
++#define DCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define DCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
++//DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS
++#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT 0x0
++#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT 0x18
++#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT 0x19
++#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT 0x1a
++#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT 0x1c
++#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT 0x1d
++#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT 0x1e
++#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK 0x000FFFFFL
++#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK 0x01000000L
++#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK 0x02000000L
++#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK 0x04000000L
++#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK 0x10000000L
++#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK 0x20000000L
++#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK 0x40000000L
++//DCP3_GRPH_XDMA_FLIP_TIMEOUT
++#define DCP3_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS__SHIFT 0x0
++#define DCP3_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK__SHIFT 0x1
++#define DCP3_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK__SHIFT 0x2
++#define DCP3_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS_MASK 0x00000001L
++#define DCP3_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK_MASK 0x00000002L
++#define DCP3_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK_MASK 0x00000004L
++//DCP3_GRPH_XDMA_FLIP_AVG_DELAY
++#define DCP3_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY__SHIFT 0x0
++#define DCP3_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD__SHIFT 0x10
++#define DCP3_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY_MASK 0x0000FFFFL
++#define DCP3_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD_MASK 0x00FF0000L
++//DCP3_GRPH_SURFACE_COUNTER_CONTROL
++#define DCP3_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN__SHIFT 0x0
++#define DCP3_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT__SHIFT 0x1
++#define DCP3_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED__SHIFT 0x9
++#define DCP3_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN_MASK 0x00000001L
++#define DCP3_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT_MASK 0x0000001EL
++#define DCP3_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_MASK 0x00000200L
++//DCP3_GRPH_SURFACE_COUNTER_OUTPUT
++#define DCP3_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN__SHIFT 0x0
++#define DCP3_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX__SHIFT 0x10
++#define DCP3_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN_MASK 0x0000FFFFL
++#define DCP3_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX_MASK 0xFFFF0000L
++
++
++// addressBlock: dce_dc_lb3_dispdec
++//LB3_LB_DATA_FORMAT
++#define LB3_LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0
++#define LB3_LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2
++#define LB3_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3
++#define LB3_LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4
++#define LB3_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5
++#define LB3_LB_DATA_FORMAT__PREFILL_EN__SHIFT 0x8
++#define LB3_LB_DATA_FORMAT__PREFETCH__SHIFT 0xc
++#define LB3_LB_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18
++#define LB3_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f
++#define LB3_LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x00000003L
++#define LB3_LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x00000004L
++#define LB3_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000008L
++#define LB3_LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x00000010L
++#define LB3_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x00000020L
++#define LB3_LB_DATA_FORMAT__PREFILL_EN_MASK 0x00000100L
++#define LB3_LB_DATA_FORMAT__PREFETCH_MASK 0x00001000L
++#define LB3_LB_DATA_FORMAT__REQUEST_MODE_MASK 0x01000000L
++#define LB3_LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000L
++//LB3_LB_MEMORY_CTRL
++#define LB3_LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0
++#define LB3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
++#define LB3_LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14
++#define LB3_LB_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0x00001FFFL
++#define LB3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x000F0000L
++#define LB3_LB_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x00300000L
++//LB3_LB_MEMORY_SIZE_STATUS
++#define LB3_LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0
++#define LB3_LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0x00001FFFL
++//LB3_LB_DESKTOP_HEIGHT
++#define LB3_LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0
++#define LB3_LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x00007FFFL
++//LB3_LB_VLINE_START_END
++#define LB3_LB_VLINE_START_END__VLINE_START__SHIFT 0x0
++#define LB3_LB_VLINE_START_END__VLINE_END__SHIFT 0x10
++#define LB3_LB_VLINE_START_END__VLINE_INV__SHIFT 0x1f
++#define LB3_LB_VLINE_START_END__VLINE_START_MASK 0x00003FFFL
++#define LB3_LB_VLINE_START_END__VLINE_END_MASK 0x7FFF0000L
++#define LB3_LB_VLINE_START_END__VLINE_INV_MASK 0x80000000L
++//LB3_LB_VLINE2_START_END
++#define LB3_LB_VLINE2_START_END__VLINE2_START__SHIFT 0x0
++#define LB3_LB_VLINE2_START_END__VLINE2_END__SHIFT 0x10
++#define LB3_LB_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f
++#define LB3_LB_VLINE2_START_END__VLINE2_START_MASK 0x00003FFFL
++#define LB3_LB_VLINE2_START_END__VLINE2_END_MASK 0x7FFF0000L
++#define LB3_LB_VLINE2_START_END__VLINE2_INV_MASK 0x80000000L
++//LB3_LB_V_COUNTER
++#define LB3_LB_V_COUNTER__V_COUNTER__SHIFT 0x0
++#define LB3_LB_V_COUNTER__V_COUNTER_MASK 0x00007FFFL
++//LB3_LB_SNAPSHOT_V_COUNTER
++#define LB3_LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0
++#define LB3_LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x00007FFFL
++//LB3_LB_INTERRUPT_MASK
++#define LB3_LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0
++#define LB3_LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4
++#define LB3_LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8
++#define LB3_LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x00000001L
++#define LB3_LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x00000010L
++#define LB3_LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x00000100L
++//LB3_LB_VLINE_STATUS
++#define LB3_LB_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0
++#define LB3_LB_VLINE_STATUS__VLINE_ACK__SHIFT 0x4
++#define LB3_LB_VLINE_STATUS__VLINE_STAT__SHIFT 0xc
++#define LB3_LB_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10
++#define LB3_LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11
++#define LB3_LB_VLINE_STATUS__VLINE_OCCURRED_MASK 0x00000001L
++#define LB3_LB_VLINE_STATUS__VLINE_ACK_MASK 0x00000010L
++#define LB3_LB_VLINE_STATUS__VLINE_STAT_MASK 0x00001000L
++#define LB3_LB_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x00010000L
++#define LB3_LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x00020000L
++//LB3_LB_VLINE2_STATUS
++#define LB3_LB_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0
++#define LB3_LB_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4
++#define LB3_LB_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc
++#define LB3_LB_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10
++#define LB3_LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11
++#define LB3_LB_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x00000001L
++#define LB3_LB_VLINE2_STATUS__VLINE2_ACK_MASK 0x00000010L
++#define LB3_LB_VLINE2_STATUS__VLINE2_STAT_MASK 0x00001000L
++#define LB3_LB_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x00010000L
++#define LB3_LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x00020000L
++//LB3_LB_VBLANK_STATUS
++#define LB3_LB_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0
++#define LB3_LB_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4
++#define LB3_LB_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc
++#define LB3_LB_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10
++#define LB3_LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11
++#define LB3_LB_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x00000001L
++#define LB3_LB_VBLANK_STATUS__VBLANK_ACK_MASK 0x00000010L
++#define LB3_LB_VBLANK_STATUS__VBLANK_STAT_MASK 0x00001000L
++#define LB3_LB_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x00010000L
++#define LB3_LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x00020000L
++//LB3_LB_SYNC_RESET_SEL
++#define LB3_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0
++#define LB3_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4
++#define LB3_LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8
++#define LB3_LB_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16
++#define LB3_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x00000003L
++#define LB3_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x00000010L
++#define LB3_LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0x0000FF00L
++#define LB3_LB_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0x00C00000L
++//LB3_LB_BLACK_KEYER_R_CR
++#define LB3_LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4
++#define LB3_LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0x0000FFF0L
++//LB3_LB_BLACK_KEYER_G_Y
++#define LB3_LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4
++#define LB3_LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0x0000FFF0L
++//LB3_LB_BLACK_KEYER_B_CB
++#define LB3_LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4
++#define LB3_LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0x0000FFF0L
++//LB3_LB_KEYER_COLOR_CTRL
++#define LB3_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0
++#define LB3_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8
++#define LB3_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x00000001L
++#define LB3_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x00000100L
++//LB3_LB_KEYER_COLOR_R_CR
++#define LB3_LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4
++#define LB3_LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0x0000FFF0L
++//LB3_LB_KEYER_COLOR_G_Y
++#define LB3_LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4
++#define LB3_LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0x0000FFF0L
++//LB3_LB_KEYER_COLOR_B_CB
++#define LB3_LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4
++#define LB3_LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0x0000FFF0L
++//LB3_LB_KEYER_COLOR_REP_R_CR
++#define LB3_LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4
++#define LB3_LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0x0000FFF0L
++//LB3_LB_KEYER_COLOR_REP_G_Y
++#define LB3_LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4
++#define LB3_LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0x0000FFF0L
++//LB3_LB_KEYER_COLOR_REP_B_CB
++#define LB3_LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4
++#define LB3_LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0x0000FFF0L
++//LB3_LB_BUFFER_LEVEL_STATUS
++#define LB3_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0
++#define LB3_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa
++#define LB3_LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10
++#define LB3_LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c
++#define LB3_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x0000003FL
++#define LB3_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0x0000FC00L
++#define LB3_LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0x0FFF0000L
++#define LB3_LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xF0000000L
++//LB3_LB_BUFFER_URGENCY_CTRL
++#define LB3_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0
++#define LB3_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10
++#define LB3_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0x00000FFFL
++#define LB3_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0x0FFF0000L
++//LB3_LB_BUFFER_URGENCY_STATUS
++#define LB3_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0
++#define LB3_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10
++#define LB3_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0x00000FFFL
++#define LB3_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x00010000L
++//LB3_LB_BUFFER_STATUS
++#define LB3_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0
++#define LB3_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4
++#define LB3_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8
++#define LB3_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc
++#define LB3_LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10
++#define LB3_LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14
++#define LB3_LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18
++#define LB3_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0x0000000FL
++#define LB3_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x00000010L
++#define LB3_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x00000100L
++#define LB3_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x00001000L
++#define LB3_LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x00010000L
++#define LB3_LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x00100000L
++#define LB3_LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x01000000L
++//LB3_LB_NO_OUTSTANDING_REQ_STATUS
++#define LB3_LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0
++#define LB3_LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x00000001L
++//LB3_MVP_AFR_FLIP_MODE
++#define LB3_MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT 0x0
++#define LB3_MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK 0x00000003L
++//LB3_MVP_AFR_FLIP_FIFO_CNTL
++#define LB3_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT 0x0
++#define LB3_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT 0x4
++#define LB3_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT 0x8
++#define LB3_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT 0xc
++#define LB3_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK 0x0000000FL
++#define LB3_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK 0x00000010L
++#define LB3_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK 0x00000100L
++#define LB3_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK 0x00001000L
++//LB3_MVP_FLIP_LINE_NUM_INSERT
++#define LB3_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT 0x0
++#define LB3_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT 0x8
++#define LB3_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT 0x18
++#define LB3_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT 0x1e
++#define LB3_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK 0x00000003L
++#define LB3_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK 0x007FFF00L
++#define LB3_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK 0x3F000000L
++#define LB3_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK 0x40000000L
++//LB3_DC_MVP_LB_CONTROL
++#define LB3_DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT 0x0
++#define LB3_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT 0x8
++#define LB3_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT 0xc
++#define LB3_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT 0x10
++#define LB3_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT 0x14
++#define LB3_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT 0x1c
++#define LB3_DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT 0x1f
++#define LB3_DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK 0x00000003L
++#define LB3_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK 0x00000100L
++#define LB3_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK 0x00001000L
++#define LB3_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK 0x00010000L
++#define LB3_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK 0x00100000L
++#define LB3_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK 0x10000000L
++#define LB3_DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK 0x80000000L
++
++
++// addressBlock: dce_dc_dcfe3_dispdec
++//DCFE3_DCFE_CLOCK_CONTROL
++#define DCFE3_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x4
++#define DCFE3_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x8
++#define DCFE3_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0xc
++#define DCFE3_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE__SHIFT 0xf
++#define DCFE3_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE__SHIFT 0x11
++#define DCFE3_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL__SHIFT 0x18
++#define DCFE3_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE__SHIFT 0x1f
++#define DCFE3_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x00000010L
++#define DCFE3_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE_MASK 0x00000100L
++#define DCFE3_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE_MASK 0x00001000L
++#define DCFE3_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE_MASK 0x00008000L
++#define DCFE3_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE_MASK 0x00020000L
++#define DCFE3_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL_MASK 0x1F000000L
++#define DCFE3_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE_MASK 0x80000000L
++//DCFE3_DCFE_SOFT_RESET
++#define DCFE3_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET__SHIFT 0x0
++#define DCFE3_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET__SHIFT 0x1
++#define DCFE3_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET__SHIFT 0x2
++#define DCFE3_DCFE_SOFT_RESET__SCL_SOFT_RESET__SHIFT 0x3
++#define DCFE3_DCFE_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4
++#define DCFE3_DCFE_SOFT_RESET__PSCL_SOFT_RESET__SHIFT 0x5
++#define DCFE3_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET_MASK 0x00000001L
++#define DCFE3_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET_MASK 0x00000002L
++#define DCFE3_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET_MASK 0x00000004L
++#define DCFE3_DCFE_SOFT_RESET__SCL_SOFT_RESET_MASK 0x00000008L
++#define DCFE3_DCFE_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x00000010L
++#define DCFE3_DCFE_SOFT_RESET__PSCL_SOFT_RESET_MASK 0x00000020L
++//DCFE3_DCFE_MEM_PWR_CTRL
++#define DCFE3_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE__SHIFT 0x0
++#define DCFE3_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS__SHIFT 0x2
++#define DCFE3_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE__SHIFT 0x3
++#define DCFE3_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS__SHIFT 0x5
++#define DCFE3_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE__SHIFT 0x6
++#define DCFE3_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS__SHIFT 0x8
++#define DCFE3_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE__SHIFT 0x9
++#define DCFE3_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS__SHIFT 0xb
++#define DCFE3_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE__SHIFT 0xc
++#define DCFE3_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS__SHIFT 0xe
++#define DCFE3_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE__SHIFT 0xf
++#define DCFE3_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS__SHIFT 0x11
++#define DCFE3_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE__SHIFT 0x12
++#define DCFE3_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS__SHIFT 0x14
++#define DCFE3_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE__SHIFT 0x15
++#define DCFE3_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS__SHIFT 0x17
++#define DCFE3_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE__SHIFT 0x18
++#define DCFE3_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS__SHIFT 0x1a
++#define DCFE3_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE__SHIFT 0x1b
++#define DCFE3_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS__SHIFT 0x1d
++#define DCFE3_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE_MASK 0x00000003L
++#define DCFE3_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS_MASK 0x00000004L
++#define DCFE3_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE_MASK 0x00000018L
++#define DCFE3_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS_MASK 0x00000020L
++#define DCFE3_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE_MASK 0x000000C0L
++#define DCFE3_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS_MASK 0x00000100L
++#define DCFE3_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE_MASK 0x00000600L
++#define DCFE3_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS_MASK 0x00000800L
++#define DCFE3_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE_MASK 0x00003000L
++#define DCFE3_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS_MASK 0x00004000L
++#define DCFE3_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE_MASK 0x00018000L
++#define DCFE3_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK 0x00020000L
++#define DCFE3_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE_MASK 0x000C0000L
++#define DCFE3_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS_MASK 0x00100000L
++#define DCFE3_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE_MASK 0x00600000L
++#define DCFE3_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS_MASK 0x00800000L
++#define DCFE3_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE_MASK 0x03000000L
++#define DCFE3_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS_MASK 0x04000000L
++#define DCFE3_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE_MASK 0x18000000L
++#define DCFE3_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS_MASK 0x20000000L
++//DCFE3_DCFE_MEM_PWR_CTRL2
++#define DCFE3_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL__SHIFT 0x0
++#define DCFE3_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2
++#define DCFE3_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4
++#define DCFE3_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL__SHIFT 0x6
++#define DCFE3_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL__SHIFT 0x8
++#define DCFE3_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL__SHIFT 0xa
++#define DCFE3_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL__SHIFT 0xc
++#define DCFE3_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL__SHIFT 0xe
++#define DCFE3_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE__SHIFT 0x10
++#define DCFE3_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS__SHIFT 0x12
++#define DCFE3_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE__SHIFT 0x15
++#define DCFE3_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS__SHIFT 0x17
++#define DCFE3_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL_MASK 0x00000003L
++#define DCFE3_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL_MASK 0x0000000CL
++#define DCFE3_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL_MASK 0x00000030L
++#define DCFE3_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL_MASK 0x000000C0L
++#define DCFE3_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL_MASK 0x00000300L
++#define DCFE3_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL_MASK 0x00000C00L
++#define DCFE3_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL_MASK 0x00003000L
++#define DCFE3_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL_MASK 0x0000C000L
++#define DCFE3_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE_MASK 0x00030000L
++#define DCFE3_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS_MASK 0x00040000L
++#define DCFE3_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE_MASK 0x00600000L
++#define DCFE3_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS_MASK 0x00800000L
++//DCFE3_DCFE_MEM_PWR_STATUS
++#define DCFE3_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE__SHIFT 0x0
++#define DCFE3_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE__SHIFT 0x2
++#define DCFE3_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE__SHIFT 0x4
++#define DCFE3_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x6
++#define DCFE3_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE__SHIFT 0x8
++#define DCFE3_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE__SHIFT 0xa
++#define DCFE3_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE__SHIFT 0xc
++#define DCFE3_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE__SHIFT 0xe
++#define DCFE3_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT 0x10
++#define DCFE3_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE__SHIFT 0x12
++#define DCFE3_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE__SHIFT 0x14
++#define DCFE3_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE__SHIFT 0x16
++#define DCFE3_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK 0x00000003L
++#define DCFE3_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE_MASK 0x0000000CL
++#define DCFE3_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE_MASK 0x00000030L
++#define DCFE3_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE_MASK 0x000000C0L
++#define DCFE3_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE_MASK 0x00000300L
++#define DCFE3_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE_MASK 0x00000C00L
++#define DCFE3_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE_MASK 0x00003000L
++#define DCFE3_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE_MASK 0x0000C000L
++#define DCFE3_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE_MASK 0x00030000L
++#define DCFE3_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK 0x000C0000L
++#define DCFE3_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE_MASK 0x00300000L
++#define DCFE3_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE_MASK 0x00C00000L
++//DCFE3_DCFE_MISC
++#define DCFE3_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN__SHIFT 0x0
++#define DCFE3_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN_MASK 0x00000001L
++//DCFE3_DCFE_FLUSH
++#define DCFE3_DCFE_FLUSH__FLUSH_OCCURED__SHIFT 0x0
++#define DCFE3_DCFE_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT 0x1
++#define DCFE3_DCFE_FLUSH__FLUSH_DEEP__SHIFT 0x2
++#define DCFE3_DCFE_FLUSH__CLEAR_FLUSH_DEEP__SHIFT 0x3
++#define DCFE3_DCFE_FLUSH__ALL_MC_REQ_RET__SHIFT 0x4
++#define DCFE3_DCFE_FLUSH__FLUSH_OCCURED_MASK 0x00000001L
++#define DCFE3_DCFE_FLUSH__CLEAR_FLUSH_OCCURED_MASK 0x00000002L
++#define DCFE3_DCFE_FLUSH__FLUSH_DEEP_MASK 0x00000004L
++#define DCFE3_DCFE_FLUSH__CLEAR_FLUSH_DEEP_MASK 0x00000008L
++#define DCFE3_DCFE_FLUSH__ALL_MC_REQ_RET_MASK 0x00000010L
++
++
++// addressBlock: dce_dc_dc_perfmon6_dispdec
++//DC_PERFMON6_PERFCOUNTER_CNTL
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
++//DC_PERFMON6_PERFCOUNTER_CNTL2
++#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
++#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
++#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
++#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
++#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
++#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
++#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
++#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
++//DC_PERFMON6_PERFCOUNTER_STATE
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
++//DC_PERFMON6_PERFMON_CNTL
++#define DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
++#define DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
++#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
++#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
++#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
++#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
++#define DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
++#define DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
++#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
++#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
++#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
++#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
++//DC_PERFMON6_PERFMON_CNTL2
++#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
++#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
++#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
++#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
++#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
++#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
++#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
++#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
++//DC_PERFMON6_PERFMON_CVALUE_INT_MISC
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
++//DC_PERFMON6_PERFMON_CVALUE_LOW
++#define DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
++#define DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
++//DC_PERFMON6_PERFMON_HI
++#define DC_PERFMON6_PERFMON_HI__PERFMON_HI__SHIFT 0x0
++#define DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
++#define DC_PERFMON6_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
++#define DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
++//DC_PERFMON6_PERFMON_LOW
++#define DC_PERFMON6_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
++#define DC_PERFMON6_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dmif_pg3_dispdec
++//DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1
++#define DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
++#define DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
++#define DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0x0000FFFFL
++#define DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xFFFF0000L
++//DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2
++#define DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
++#define DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
++#define DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0x0000FFFFL
++#define DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xFFFF0000L
++//DMIF_PG3_DPG_WATERMARK_MASK_CONTROL
++#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
++#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x4
++#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
++#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK__SHIFT 0xc
++#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0xf
++#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x12
++#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL__SHIFT 0x13
++#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL__SHIFT 0x14
++#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000007L
++#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000070L
++#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x00000700L
++#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK_MASK 0x00007000L
++#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00038000L
++#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x00040000L
++#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL_MASK 0x00080000L
++#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL_MASK 0x3FF00000L
++//DMIF_PG3_DPG_PIPE_URGENCY_CONTROL
++#define DMIF_PG3_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
++#define DMIF_PG3_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
++#define DMIF_PG3_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0x0000FFFFL
++#define DMIF_PG3_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xFFFF0000L
++//DMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL
++#define DMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK__SHIFT 0x0
++#define DMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK__SHIFT 0x10
++#define DMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK_MASK 0x0000FFFFL
++#define DMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK_MASK 0xFFFF0000L
++//DMIF_PG3_DPG_PIPE_STUTTER_CONTROL
++#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
++#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
++#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
++#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
++#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
++#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
++#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
++#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH__SHIFT 0x10
++#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x14
++#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x15
++#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x16
++#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x17
++#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0x1a
++#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0x1b
++#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L
++#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L
++#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x00000020L
++#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x00000040L
++#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x00000080L
++#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x00000400L
++#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x00000800L
++#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH_MASK 0x00010000L
++#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x00100000L
++#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x00200000L
++#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x00400000L
++#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x00800000L
++#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x04000000L
++#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x08000000L
++//DMIF_PG3_DPG_PIPE_STUTTER_CONTROL2
++#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x0
++#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK__SHIFT 0x10
++#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0x0000FFFFL
++#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK 0xFFFF0000L
++//DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL
++#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE__SHIFT 0x0
++#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE__SHIFT 0x1
++#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
++#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
++#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
++#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
++#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK__SHIFT 0xf
++#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE_MASK 0x00000001L
++#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE_MASK 0x00000002L
++#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L
++#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x00000100L
++#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON_MASK 0x00000200L
++#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT_MASK 0x00000400L
++#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK_MASK 0xFFFF8000L
++//DMIF_PG3_DPG_REPEATER_PROGRAM
++#define DMIF_PG3_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
++#define DMIF_PG3_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
++#define DMIF_PG3_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x00000007L
++#define DMIF_PG3_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x00000070L
++//DMIF_PG3_DPG_CHK_PRE_PROC_CNTL
++#define DMIF_PG3_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0
++#define DMIF_PG3_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x00000001L
++//DMIF_PG3_DPG_DVMM_STATUS
++#define DMIF_PG3_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED__SHIFT 0x0
++#define DMIF_PG3_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED__SHIFT 0x1
++#define DMIF_PG3_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR__SHIFT 0x4
++#define DMIF_PG3_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR__SHIFT 0x5
++#define DMIF_PG3_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_MASK 0x00000001L
++#define DMIF_PG3_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_MASK 0x00000002L
++#define DMIF_PG3_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR_MASK 0x00000010L
++#define DMIF_PG3_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR_MASK 0x00000020L
++
++
++// addressBlock: dce_dc_scl3_dispdec
++//SCL3_SCL_COEF_RAM_SELECT
++#define SCL3_SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0
++#define SCL3_SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8
++#define SCL3_SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10
++#define SCL3_SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x0000000FL
++#define SCL3_SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x00000F00L
++#define SCL3_SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x00070000L
++//SCL3_SCL_COEF_RAM_TAP_DATA
++#define SCL3_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0
++#define SCL3_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
++#define SCL3_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10
++#define SCL3_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
++#define SCL3_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL
++#define SCL3_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L
++#define SCL3_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L
++#define SCL3_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L
++//SCL3_SCL_MODE
++#define SCL3_SCL_MODE__SCL_MODE__SHIFT 0x0
++#define SCL3_SCL_MODE__SCL_PSCL_EN__SHIFT 0x4
++#define SCL3_SCL_MODE__SCL_MODE_MASK 0x00000003L
++#define SCL3_SCL_MODE__SCL_PSCL_EN_MASK 0x00000010L
++//SCL3_SCL_TAP_CONTROL
++#define SCL3_SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0
++#define SCL3_SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x8
++#define SCL3_SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x00000007L
++#define SCL3_SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0x00000F00L
++//SCL3_SCL_CONTROL
++#define SCL3_SCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
++#define SCL3_SCL_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4
++#define SCL3_SCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L
++#define SCL3_SCL_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x00000010L
++//SCL3_SCL_BYPASS_CONTROL
++#define SCL3_SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT 0x0
++#define SCL3_SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x00000003L
++//SCL3_SCL_MANUAL_REPLICATE_CONTROL
++#define SCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
++#define SCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
++#define SCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL
++#define SCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L
++//SCL3_SCL_AUTOMATIC_MODE_CONTROL
++#define SCL3_SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0
++#define SCL3_SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10
++#define SCL3_SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x00000001L
++#define SCL3_SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x00010000L
++//SCL3_SCL_HORZ_FILTER_CONTROL
++#define SCL3_SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT 0x0
++#define SCL3_SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
++#define SCL3_SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK 0x00000001L
++#define SCL3_SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
++//SCL3_SCL_HORZ_FILTER_SCALE_RATIO
++#define SCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
++#define SCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL
++//SCL3_SCL_HORZ_FILTER_INIT
++#define SCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
++#define SCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
++#define SCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL
++#define SCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L
++//SCL3_SCL_VERT_FILTER_CONTROL
++#define SCL3_SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT 0x0
++#define SCL3_SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
++#define SCL3_SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK 0x00000001L
++#define SCL3_SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
++//SCL3_SCL_VERT_FILTER_SCALE_RATIO
++#define SCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
++#define SCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL
++//SCL3_SCL_VERT_FILTER_INIT
++#define SCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
++#define SCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
++#define SCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL
++#define SCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x07000000L
++//SCL3_SCL_VERT_FILTER_INIT_BOT
++#define SCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
++#define SCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
++#define SCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL
++#define SCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x07000000L
++//SCL3_SCL_ROUND_OFFSET
++#define SCL3_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0
++#define SCL3_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10
++#define SCL3_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0x0000FFFFL
++#define SCL3_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xFFFF0000L
++//SCL3_SCL_UPDATE
++#define SCL3_SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
++#define SCL3_SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8
++#define SCL3_SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10
++#define SCL3_SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18
++#define SCL3_SCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L
++#define SCL3_SCL_UPDATE__SCL_UPDATE_TAKEN_MASK 0x00000100L
++#define SCL3_SCL_UPDATE__SCL_UPDATE_LOCK_MASK 0x00010000L
++#define SCL3_SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x01000000L
++//SCL3_SCL_F_SHARP_CONTROL
++#define SCL3_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT 0x0
++#define SCL3_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT 0x4
++#define SCL3_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT 0x8
++#define SCL3_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT 0xc
++#define SCL3_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK 0x00000007L
++#define SCL3_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK 0x00000010L
++#define SCL3_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK 0x00000700L
++#define SCL3_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK 0x00001000L
++//SCL3_SCL_ALU_CONTROL
++#define SCL3_SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0
++#define SCL3_SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x00000001L
++//SCL3_SCL_COEF_RAM_CONFLICT_STATUS
++#define SCL3_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT 0x0
++#define SCL3_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT 0x8
++#define SCL3_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT 0xc
++#define SCL3_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10
++#define SCL3_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK 0x00000001L
++#define SCL3_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK 0x00000100L
++#define SCL3_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK 0x00001000L
++#define SCL3_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK 0x00010000L
++//SCL3_VIEWPORT_START_SECONDARY
++#define SCL3_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0
++#define SCL3_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10
++#define SCL3_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x00003FFFL
++#define SCL3_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3FFF0000L
++//SCL3_VIEWPORT_START
++#define SCL3_VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0
++#define SCL3_VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10
++#define SCL3_VIEWPORT_START__VIEWPORT_Y_START_MASK 0x00003FFFL
++#define SCL3_VIEWPORT_START__VIEWPORT_X_START_MASK 0x3FFF0000L
++//SCL3_VIEWPORT_SIZE
++#define SCL3_VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0
++#define SCL3_VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10
++#define SCL3_VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x00003FFFL
++#define SCL3_VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x3FFF0000L
++//SCL3_EXT_OVERSCAN_LEFT_RIGHT
++#define SCL3_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
++#define SCL3_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
++#define SCL3_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL
++#define SCL3_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L
++//SCL3_EXT_OVERSCAN_TOP_BOTTOM
++#define SCL3_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
++#define SCL3_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
++#define SCL3_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL
++#define SCL3_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L
++//SCL3_SCL_MODE_CHANGE_DET1
++#define SCL3_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0
++#define SCL3_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4
++#define SCL3_SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7
++#define SCL3_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x00000001L
++#define SCL3_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x00000010L
++#define SCL3_SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0x0FFFFF80L
++//SCL3_SCL_MODE_CHANGE_DET2
++#define SCL3_SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0
++#define SCL3_SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x001FFFFFL
++//SCL3_SCL_MODE_CHANGE_DET3
++#define SCL3_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0
++#define SCL3_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10
++#define SCL3_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x00003FFFL
++#define SCL3_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3FFF0000L
++//SCL3_SCL_MODE_CHANGE_MASK
++#define SCL3_SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0
++#define SCL3_SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x00000001L
++
++
++// addressBlock: dce_dc_blnd3_dispdec
++//BLND3_BLND_CONTROL
++#define BLND3_BLND_CONTROL__BLND_GLOBAL_GAIN__SHIFT 0x0
++#define BLND3_BLND_CONTROL__BLND_MODE__SHIFT 0x8
++#define BLND3_BLND_CONTROL__BLND_STEREO_TYPE__SHIFT 0xa
++#define BLND3_BLND_CONTROL__BLND_STEREO_POLARITY__SHIFT 0xc
++#define BLND3_BLND_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT 0xd
++#define BLND3_BLND_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10
++#define BLND3_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x12
++#define BLND3_BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14
++#define BLND3_BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18
++#define BLND3_BLND_CONTROL__BLND_GLOBAL_GAIN_MASK 0x000000FFL
++#define BLND3_BLND_CONTROL__BLND_MODE_MASK 0x00000300L
++#define BLND3_BLND_CONTROL__BLND_STEREO_TYPE_MASK 0x00000C00L
++#define BLND3_BLND_CONTROL__BLND_STEREO_POLARITY_MASK 0x00001000L
++#define BLND3_BLND_CONTROL__BLND_FEEDTHROUGH_EN_MASK 0x00002000L
++#define BLND3_BLND_CONTROL__BLND_ALPHA_MODE_MASK 0x00030000L
++#define BLND3_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00040000L
++#define BLND3_BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x00100000L
++#define BLND3_BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xFF000000L
++//BLND3_BLND_SM_CONTROL2
++#define BLND3_BLND_SM_CONTROL2__SM_MODE__SHIFT 0x0
++#define BLND3_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4
++#define BLND3_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5
++#define BLND3_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
++#define BLND3_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
++#define BLND3_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18
++#define BLND3_BLND_SM_CONTROL2__SM_MODE_MASK 0x00000007L
++#define BLND3_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x00000010L
++#define BLND3_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x00000020L
++#define BLND3_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L
++#define BLND3_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L
++#define BLND3_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x01000000L
++//BLND3_BLND_CONTROL2
++#define BLND3_BLND_CONTROL2__PTI_ENABLE__SHIFT 0x0
++#define BLND3_BLND_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT 0x4
++#define BLND3_BLND_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT 0x6
++#define BLND3_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT 0x7
++#define BLND3_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT 0x8
++#define BLND3_BLND_CONTROL2__PTI_ENABLE_MASK 0x00000001L
++#define BLND3_BLND_CONTROL2__PTI_NEW_PIXEL_GAP_MASK 0x00000030L
++#define BLND3_BLND_CONTROL2__BLND_NEW_PIXEL_MODE_MASK 0x00000040L
++#define BLND3_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK 0x00000080L
++#define BLND3_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK 0x00000100L
++//BLND3_BLND_UPDATE
++#define BLND3_BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0
++#define BLND3_BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8
++#define BLND3_BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10
++#define BLND3_BLND_UPDATE__BLND_UPDATE_PENDING_MASK 0x00000001L
++#define BLND3_BLND_UPDATE__BLND_UPDATE_TAKEN_MASK 0x00000100L
++#define BLND3_BLND_UPDATE__BLND_UPDATE_LOCK_MASK 0x00010000L
++//BLND3_BLND_UNDERFLOW_INTERRUPT
++#define BLND3_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0
++#define BLND3_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8
++#define BLND3_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc
++#define BLND3_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10
++#define BLND3_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x00000001L
++#define BLND3_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x00000100L
++#define BLND3_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x00001000L
++#define BLND3_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x00030000L
++//BLND3_BLND_V_UPDATE_LOCK
++#define BLND3_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0
++#define BLND3_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1
++#define BLND3_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10
++#define BLND3_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c
++#define BLND3_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT 0x1d
++#define BLND3_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT 0x1f
++#define BLND3_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x00000001L
++#define BLND3_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x00000002L
++#define BLND3_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x00010000L
++#define BLND3_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000L
++#define BLND3_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK 0x20000000L
++#define BLND3_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK 0x80000000L
++//BLND3_BLND_REG_UPDATE_STATUS
++#define BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT 0x0
++#define BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT 0x1
++#define BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2
++#define BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3
++#define BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT 0x6
++#define BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT 0x7
++#define BLND3_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT 0x8
++#define BLND3_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT 0x9
++#define BLND3_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT 0xa
++#define BLND3_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT 0xb
++#define BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK 0x00000001L
++#define BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK 0x00000002L
++#define BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK 0x00000004L
++#define BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK 0x00000008L
++#define BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK 0x00000040L
++#define BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK 0x00000080L
++#define BLND3_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK 0x00000100L
++#define BLND3_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK 0x00000200L
++#define BLND3_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK 0x00000400L
++#define BLND3_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK 0x00000800L
++
++
++// addressBlock: dce_dc_crtc3_dispdec
++//CRTC3_CRTC_H_BLANK_EARLY_NUM
++#define CRTC3_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0
++#define CRTC3_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10
++#define CRTC3_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x000003FFL
++#define CRTC3_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x00010000L
++//CRTC3_CRTC_H_TOTAL
++#define CRTC3_CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0
++#define CRTC3_CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x00003FFFL
++//CRTC3_CRTC_H_BLANK_START_END
++#define CRTC3_CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0
++#define CRTC3_CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10
++#define CRTC3_CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x00003FFFL
++#define CRTC3_CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3FFF0000L
++//CRTC3_CRTC_H_SYNC_A
++#define CRTC3_CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0
++#define CRTC3_CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10
++#define CRTC3_CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x00003FFFL
++#define CRTC3_CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3FFF0000L
++//CRTC3_CRTC_H_SYNC_A_CNTL
++#define CRTC3_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0
++#define CRTC3_CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10
++#define CRTC3_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11
++#define CRTC3_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x00000001L
++#define CRTC3_CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x00010000L
++#define CRTC3_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x00020000L
++//CRTC3_CRTC_H_SYNC_B
++#define CRTC3_CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0
++#define CRTC3_CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10
++#define CRTC3_CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x00003FFFL
++#define CRTC3_CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x3FFF0000L
++//CRTC3_CRTC_H_SYNC_B_CNTL
++#define CRTC3_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0
++#define CRTC3_CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10
++#define CRTC3_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11
++#define CRTC3_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x00000001L
++#define CRTC3_CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x00010000L
++#define CRTC3_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x00020000L
++//CRTC3_CRTC_VBI_END
++#define CRTC3_CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x0
++#define CRTC3_CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x10
++#define CRTC3_CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x00003FFFL
++#define CRTC3_CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x3FFF0000L
++//CRTC3_CRTC_V_TOTAL
++#define CRTC3_CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0
++#define CRTC3_CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x00003FFFL
++//CRTC3_CRTC_V_TOTAL_MIN
++#define CRTC3_CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0
++#define CRTC3_CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x00003FFFL
++//CRTC3_CRTC_V_TOTAL_MAX
++#define CRTC3_CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0
++#define CRTC3_CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10
++#define CRTC3_CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x00003FFFL
++#define CRTC3_CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x00010000L
++//CRTC3_CRTC_V_TOTAL_CONTROL
++#define CRTC3_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0
++#define CRTC3_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4
++#define CRTC3_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8
++#define CRTC3_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc
++#define CRTC3_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf
++#define CRTC3_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10
++#define CRTC3_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x00000001L
++#define CRTC3_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x00000010L
++#define CRTC3_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x00000100L
++#define CRTC3_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x00001000L
++#define CRTC3_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00008000L
++#define CRTC3_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L
++//CRTC3_CRTC_V_TOTAL_INT_STATUS
++#define CRTC3_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0
++#define CRTC3_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4
++#define CRTC3_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8
++#define CRTC3_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc
++#define CRTC3_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L
++#define CRTC3_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L
++#define CRTC3_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L
++#define CRTC3_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L
++//CRTC3_CRTC_VSYNC_NOM_INT_STATUS
++#define CRTC3_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0
++#define CRTC3_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4
++#define CRTC3_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x00000001L
++#define CRTC3_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L
++//CRTC3_CRTC_V_BLANK_START_END
++#define CRTC3_CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0
++#define CRTC3_CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10
++#define CRTC3_CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x00003FFFL
++#define CRTC3_CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3FFF0000L
++//CRTC3_CRTC_V_SYNC_A
++#define CRTC3_CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0
++#define CRTC3_CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10
++#define CRTC3_CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x00003FFFL
++#define CRTC3_CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3FFF0000L
++//CRTC3_CRTC_V_SYNC_A_CNTL
++#define CRTC3_CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0
++#define CRTC3_CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x00000001L
++//CRTC3_CRTC_V_SYNC_B
++#define CRTC3_CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0
++#define CRTC3_CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10
++#define CRTC3_CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x00003FFFL
++#define CRTC3_CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x3FFF0000L
++//CRTC3_CRTC_V_SYNC_B_CNTL
++#define CRTC3_CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0
++#define CRTC3_CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x00000001L
++//CRTC3_CRTC_DTMTEST_CNTL
++#define CRTC3_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0
++#define CRTC3_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1
++#define CRTC3_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x00000001L
++#define CRTC3_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x0000001EL
++//CRTC3_CRTC_DTMTEST_STATUS_POSITION
++#define CRTC3_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0
++#define CRTC3_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10
++#define CRTC3_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x00003FFFL
++#define CRTC3_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x3FFF0000L
++//CRTC3_CRTC_TRIGA_CNTL
++#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0
++#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5
++#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8
++#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9
++#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa
++#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb
++#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
++#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
++#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14
++#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18
++#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f
++#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x0000001FL
++#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0x000000E0L
++#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000100L
++#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x00000200L
++#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x00000400L
++#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x00000800L
++#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
++#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
++#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L
++#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1F000000L
++#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000L
++//CRTC3_CRTC_TRIGA_MANUAL_TRIG
++#define CRTC3_CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0
++#define CRTC3_CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x00000001L
++//CRTC3_CRTC_TRIGB_CNTL
++#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0
++#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5
++#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8
++#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9
++#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa
++#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb
++#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
++#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
++#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14
++#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18
++#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f
++#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x0000001FL
++#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0x000000E0L
++#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000100L
++#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x00000200L
++#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x00000400L
++#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x00000800L
++#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
++#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
++#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L
++#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1F000000L
++#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000L
++//CRTC3_CRTC_TRIGB_MANUAL_TRIG
++#define CRTC3_CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0
++#define CRTC3_CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x00000001L
++//CRTC3_CRTC_FORCE_COUNT_NOW_CNTL
++#define CRTC3_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0
++#define CRTC3_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4
++#define CRTC3_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8
++#define CRTC3_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10
++#define CRTC3_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18
++#define CRTC3_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x00000003L
++#define CRTC3_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L
++#define CRTC3_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L
++#define CRTC3_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L
++#define CRTC3_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L
++//CRTC3_CRTC_FLOW_CONTROL
++#define CRTC3_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0
++#define CRTC3_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8
++#define CRTC3_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10
++#define CRTC3_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18
++#define CRTC3_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL
++#define CRTC3_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x00000100L
++#define CRTC3_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L
++#define CRTC3_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L
++//CRTC3_CRTC_STEREO_FORCE_NEXT_EYE
++#define CRTC3_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0
++#define CRTC3_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER__SHIFT 0x8
++#define CRTC3_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER__SHIFT 0x10
++#define CRTC3_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L
++#define CRTC3_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L
++#define CRTC3_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L
++//CRTC3_CRTC_AVSYNC_COUNTER
++#define CRTC3_CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER__SHIFT 0x0
++#define CRTC3_CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER_MASK 0xFFFFFFFFL
++//CRTC3_CRTC_CONTROL
++#define CRTC3_CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x0
++#define CRTC3_CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4
++#define CRTC3_CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8
++#define CRTC3_CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc
++#define CRTC3_CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd
++#define CRTC3_CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe
++#define CRTC3_CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10
++#define CRTC3_CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14
++#define CRTC3_CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d
++#define CRTC3_CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e
++#define CRTC3_CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f
++#define CRTC3_CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x00000001L
++#define CRTC3_CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x00000010L
++#define CRTC3_CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x00000300L
++#define CRTC3_CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x00001000L
++#define CRTC3_CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x00002000L
++#define CRTC3_CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x00004000L
++#define CRTC3_CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x00010000L
++#define CRTC3_CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x00700000L
++#define CRTC3_CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000L
++#define CRTC3_CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L
++#define CRTC3_CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L
++//CRTC3_CRTC_BLANK_CONTROL
++#define CRTC3_CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0
++#define CRTC3_CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8
++#define CRTC3_CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10
++#define CRTC3_CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x00000001L
++#define CRTC3_CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x00000100L
++#define CRTC3_CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x00010000L
++//CRTC3_CRTC_INTERLACE_CONTROL
++#define CRTC3_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0
++#define CRTC3_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10
++#define CRTC3_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x00000001L
++#define CRTC3_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L
++//CRTC3_CRTC_INTERLACE_STATUS
++#define CRTC3_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0
++#define CRTC3_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1
++#define CRTC3_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x00000001L
++#define CRTC3_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x00000002L
++//CRTC3_CRTC_FIELD_INDICATION_CONTROL
++#define CRTC3_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0
++#define CRTC3_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1
++#define CRTC3_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x00000001L
++#define CRTC3_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x00000002L
++//CRTC3_CRTC_PIXEL_DATA_READBACK0
++#define CRTC3_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0
++#define CRTC3_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10
++#define CRTC3_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0x00000FFFL
++#define CRTC3_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0x0FFF0000L
++//CRTC3_CRTC_PIXEL_DATA_READBACK1
++#define CRTC3_CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0
++#define CRTC3_CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0x00000FFFL
++//CRTC3_CRTC_STATUS
++#define CRTC3_CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x0
++#define CRTC3_CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1
++#define CRTC3_CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x2
++#define CRTC3_CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x3
++#define CRTC3_CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x4
++#define CRTC3_CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5
++#define CRTC3_CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x10
++#define CRTC3_CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11
++#define CRTC3_CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x12
++#define CRTC3_CRTC_STATUS__CRTC_V_BLANK_MASK 0x00000001L
++#define CRTC3_CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x00000002L
++#define CRTC3_CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x00000004L
++#define CRTC3_CRTC_STATUS__CRTC_V_UPDATE_MASK 0x00000008L
++#define CRTC3_CRTC_STATUS__CRTC_V_START_LINE_MASK 0x00000010L
++#define CRTC3_CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x00000020L
++#define CRTC3_CRTC_STATUS__CRTC_H_BLANK_MASK 0x00010000L
++#define CRTC3_CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x00020000L
++#define CRTC3_CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x00040000L
++//CRTC3_CRTC_STATUS_POSITION
++#define CRTC3_CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0
++#define CRTC3_CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10
++#define CRTC3_CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x00003FFFL
++#define CRTC3_CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x3FFF0000L
++//CRTC3_CRTC_NOM_VERT_POSITION
++#define CRTC3_CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0
++#define CRTC3_CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x00003FFFL
++//CRTC3_CRTC_STATUS_FRAME_COUNT
++#define CRTC3_CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0
++#define CRTC3_CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0x00FFFFFFL
++//CRTC3_CRTC_STATUS_VF_COUNT
++#define CRTC3_CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0
++#define CRTC3_CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x3FFFFFFFL
++//CRTC3_CRTC_STATUS_HV_COUNT
++#define CRTC3_CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0
++#define CRTC3_CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x3FFFFFFFL
++//CRTC3_CRTC_COUNT_CONTROL
++#define CRTC3_CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0
++#define CRTC3_CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1
++#define CRTC3_CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x00000001L
++#define CRTC3_CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x0000001EL
++//CRTC3_CRTC_COUNT_RESET
++#define CRTC3_CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0
++#define CRTC3_CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x00000001L
++//CRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE
++#define CRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0
++#define CRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L
++//CRTC3_CRTC_VERT_SYNC_CONTROL
++#define CRTC3_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0
++#define CRTC3_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8
++#define CRTC3_CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10
++#define CRTC3_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L
++#define CRTC3_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L
++#define CRTC3_CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L
++//CRTC3_CRTC_STEREO_STATUS
++#define CRTC3_CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0
++#define CRTC3_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8
++#define CRTC3_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10
++#define CRTC3_CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG__SHIFT 0x14
++#define CRTC3_CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18
++#define CRTC3_CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x00000001L
++#define CRTC3_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x00000100L
++#define CRTC3_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x00010000L
++#define CRTC3_CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG_MASK 0x00100000L
++#define CRTC3_CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L
++//CRTC3_CRTC_STEREO_CONTROL
++#define CRTC3_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0
++#define CRTC3_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf
++#define CRTC3_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10
++#define CRTC3_CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11
++#define CRTC3_CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12
++#define CRTC3_CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM__SHIFT 0x13
++#define CRTC3_CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14
++#define CRTC3_CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18
++#define CRTC3_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00003FFFL
++#define CRTC3_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L
++#define CRTC3_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x00010000L
++#define CRTC3_CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L
++#define CRTC3_CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L
++#define CRTC3_CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM_MASK 0x00080000L
++#define CRTC3_CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L
++#define CRTC3_CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x01000000L
++//CRTC3_CRTC_SNAPSHOT_STATUS
++#define CRTC3_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0
++#define CRTC3_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1
++#define CRTC3_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2
++#define CRTC3_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x00000001L
++#define CRTC3_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x00000002L
++#define CRTC3_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L
++//CRTC3_CRTC_SNAPSHOT_CONTROL
++#define CRTC3_CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0
++#define CRTC3_CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L
++//CRTC3_CRTC_SNAPSHOT_POSITION
++#define CRTC3_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0
++#define CRTC3_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10
++#define CRTC3_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x00003FFFL
++#define CRTC3_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x3FFF0000L
++//CRTC3_CRTC_SNAPSHOT_FRAME
++#define CRTC3_CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0
++#define CRTC3_CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL
++//CRTC3_CRTC_START_LINE_CONTROL
++#define CRTC3_CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0
++#define CRTC3_CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x1
++#define CRTC3_CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x2
++#define CRTC3_CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x8
++#define CRTC3_CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc
++#define CRTC3_CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x00000001L
++#define CRTC3_CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x00000002L
++#define CRTC3_CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x00000004L
++#define CRTC3_CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x00000100L
++#define CRTC3_CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0x000FF000L
++//CRTC3_CRTC_INTERRUPT_CONTROL
++#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0
++#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1
++#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4
++#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5
++#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8
++#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9
++#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10
++#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11
++#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18
++#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19
++#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a
++#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b
++#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c
++#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d
++#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e
++#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f
++#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x00000001L
++#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x00000002L
++#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x00000010L
++#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x00000020L
++#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L
++#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L
++#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L
++#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L
++#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x01000000L
++#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x02000000L
++#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x04000000L
++#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x08000000L
++#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000L
++#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000L
++#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L
++#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L
++//CRTC3_CRTC_UPDATE_LOCK
++#define CRTC3_CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0
++#define CRTC3_CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x00000001L
++//CRTC3_CRTC_DOUBLE_BUFFER_CONTROL
++#define CRTC3_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0
++#define CRTC3_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8
++#define CRTC3_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10
++#define CRTC3_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18
++#define CRTC3_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x19
++#define CRTC3_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x00000001L
++#define CRTC3_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x00000100L
++#define CRTC3_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L
++#define CRTC3_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x01000000L
++#define CRTC3_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x02000000L
++//CRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE
++#define CRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0
++#define CRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x00000001L
++//CRTC3_CRTC_TEST_PATTERN_CONTROL
++#define CRTC3_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0
++#define CRTC3_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8
++#define CRTC3_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10
++#define CRTC3_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18
++#define CRTC3_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x00000001L
++#define CRTC3_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x00000700L
++#define CRTC3_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L
++#define CRTC3_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xFF000000L
++//CRTC3_CRTC_TEST_PATTERN_PARAMETERS
++#define CRTC3_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0
++#define CRTC3_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4
++#define CRTC3_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8
++#define CRTC3_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc
++#define CRTC3_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10
++#define CRTC3_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0x0000000FL
++#define CRTC3_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0x000000F0L
++#define CRTC3_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0x00000F00L
++#define CRTC3_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0x0000F000L
++#define CRTC3_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xFFFF0000L
++//CRTC3_CRTC_TEST_PATTERN_COLOR
++#define CRTC3_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0
++#define CRTC3_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10
++#define CRTC3_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0x0000FFFFL
++#define CRTC3_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x003F0000L
++//CRTC3_CRTC_MASTER_UPDATE_LOCK
++#define CRTC3_CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0
++#define CRTC3_CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8
++#define CRTC3_CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK__SHIFT 0x10
++#define CRTC3_CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x00000001L
++#define CRTC3_CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x00000100L
++#define CRTC3_CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK_MASK 0x00010000L
++//CRTC3_CRTC_MASTER_UPDATE_MODE
++#define CRTC3_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0
++#define CRTC3_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10
++#define CRTC3_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x00000007L
++#define CRTC3_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00030000L
++//CRTC3_CRTC_MVP_INBAND_CNTL_INSERT
++#define CRTC3_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0
++#define CRTC3_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8
++#define CRTC3_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x00000003L
++#define CRTC3_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xFFFFFF00L
++//CRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER
++#define CRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0
++#define CRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0x000000FFL
++//CRTC3_CRTC_MVP_STATUS
++#define CRTC3_CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0
++#define CRTC3_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4
++#define CRTC3_CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10
++#define CRTC3_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14
++#define CRTC3_CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x00000001L
++#define CRTC3_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x00000010L
++#define CRTC3_CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x00010000L
++#define CRTC3_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x00100000L
++//CRTC3_CRTC_MASTER_EN
++#define CRTC3_CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0
++#define CRTC3_CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x00000001L
++//CRTC3_CRTC_ALLOW_STOP_OFF_V_CNT
++#define CRTC3_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0
++#define CRTC3_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10
++#define CRTC3_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0x000000FFL
++#define CRTC3_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x00010000L
++//CRTC3_CRTC_V_UPDATE_INT_STATUS
++#define CRTC3_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0
++#define CRTC3_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8
++#define CRTC3_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x00000001L
++#define CRTC3_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x00000100L
++//CRTC3_CRTC_OVERSCAN_COLOR
++#define CRTC3_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0
++#define CRTC3_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa
++#define CRTC3_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14
++#define CRTC3_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x000003FFL
++#define CRTC3_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0x000FFC00L
++#define CRTC3_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3FF00000L
++//CRTC3_CRTC_OVERSCAN_COLOR_EXT
++#define CRTC3_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0
++#define CRTC3_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8
++#define CRTC3_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10
++#define CRTC3_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x00000003L
++#define CRTC3_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x00000300L
++#define CRTC3_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x00030000L
++//CRTC3_CRTC_BLANK_DATA_COLOR
++#define CRTC3_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0
++#define CRTC3_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa
++#define CRTC3_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14
++#define CRTC3_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL
++#define CRTC3_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L
++#define CRTC3_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L
++//CRTC3_CRTC_BLANK_DATA_COLOR_EXT
++#define CRTC3_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0
++#define CRTC3_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8
++#define CRTC3_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10
++#define CRTC3_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x00000003L
++#define CRTC3_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00000300L
++#define CRTC3_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x00030000L
++//CRTC3_CRTC_BLACK_COLOR
++#define CRTC3_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0
++#define CRTC3_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa
++#define CRTC3_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14
++#define CRTC3_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x000003FFL
++#define CRTC3_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0x000FFC00L
++#define CRTC3_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3FF00000L
++//CRTC3_CRTC_BLACK_COLOR_EXT
++#define CRTC3_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0
++#define CRTC3_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8
++#define CRTC3_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10
++#define CRTC3_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x00000003L
++#define CRTC3_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x00000300L
++#define CRTC3_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x00030000L
++//CRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION
++#define CRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0
++#define CRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10
++#define CRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00003FFFL
++#define CRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x3FFF0000L
++//CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL
++#define CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4
++#define CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8
++#define CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc
++#define CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10
++#define CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14
++#define CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18
++#define CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L
++#define CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L
++#define CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L
++#define CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L
++#define CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L
++#define CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L
++//CRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION
++#define CRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0
++#define CRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00003FFFL
++//CRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL
++#define CRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8
++#define CRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc
++#define CRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10
++#define CRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14
++#define CRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18
++#define CRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L
++#define CRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L
++#define CRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L
++#define CRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L
++#define CRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L
++//CRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION
++#define CRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0
++#define CRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00003FFFL
++//CRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL
++#define CRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8
++#define CRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc
++#define CRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10
++#define CRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14
++#define CRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18
++#define CRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L
++#define CRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L
++#define CRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L
++#define CRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L
++#define CRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L
++//CRTC3_CRTC_CRC_CNTL
++#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0
++#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4
++#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8
++#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc
++#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
++#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14
++#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18
++#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC_EN_MASK 0x00000001L
++#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x00000010L
++#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x00000300L
++#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x00003000L
++#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
++#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x00700000L
++#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x07000000L
++//CRTC3_CRTC_CRC0_WINDOWA_X_CONTROL
++#define CRTC3_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0
++#define CRTC3_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10
++#define CRTC3_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x00003FFFL
++#define CRTC3_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3FFF0000L
++//CRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL
++#define CRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0
++#define CRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10
++#define CRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x00003FFFL
++#define CRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3FFF0000L
++//CRTC3_CRTC_CRC0_WINDOWB_X_CONTROL
++#define CRTC3_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0
++#define CRTC3_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10
++#define CRTC3_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x00003FFFL
++#define CRTC3_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3FFF0000L
++//CRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL
++#define CRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0
++#define CRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10
++#define CRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x00003FFFL
++#define CRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3FFF0000L
++//CRTC3_CRTC_CRC0_DATA_RG
++#define CRTC3_CRTC_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0
++#define CRTC3_CRTC_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10
++#define CRTC3_CRTC_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL
++#define CRTC3_CRTC_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L
++//CRTC3_CRTC_CRC0_DATA_B
++#define CRTC3_CRTC_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0
++#define CRTC3_CRTC_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL
++//CRTC3_CRTC_CRC1_WINDOWA_X_CONTROL
++#define CRTC3_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0
++#define CRTC3_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10
++#define CRTC3_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x00003FFFL
++#define CRTC3_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3FFF0000L
++//CRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL
++#define CRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0
++#define CRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10
++#define CRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x00003FFFL
++#define CRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3FFF0000L
++//CRTC3_CRTC_CRC1_WINDOWB_X_CONTROL
++#define CRTC3_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0
++#define CRTC3_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10
++#define CRTC3_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x00003FFFL
++#define CRTC3_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3FFF0000L
++//CRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL
++#define CRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0
++#define CRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10
++#define CRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x00003FFFL
++#define CRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3FFF0000L
++//CRTC3_CRTC_CRC1_DATA_RG
++#define CRTC3_CRTC_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0
++#define CRTC3_CRTC_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10
++#define CRTC3_CRTC_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL
++#define CRTC3_CRTC_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L
++//CRTC3_CRTC_CRC1_DATA_B
++#define CRTC3_CRTC_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0
++#define CRTC3_CRTC_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL
++//CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL
++#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE__SHIFT 0x0
++#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__SHIFT 0x3
++#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__SHIFT 0x4
++#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__SHIFT 0x5
++#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__SHIFT 0x8
++#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__SHIFT 0x9
++#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__SHIFT 0xc
++#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__SHIFT 0xd
++#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__SHIFT 0xe
++#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE__SHIFT 0x18
++#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE__SHIFT 0x1c
++#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE_MASK 0x00000003L
++#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_MASK 0x00000008L
++#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_MASK 0x00000010L
++#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_MASK 0x00000060L
++#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_MASK 0x00000100L
++#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_MASK 0x00000200L
++#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_MASK 0x00001000L
++#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_MASK 0x00002000L
++#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_MASK 0x00004000L
++#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE_MASK 0x07000000L
++#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE_MASK 0x70000000L
++//CRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START
++#define CRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X__SHIFT 0x0
++#define CRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y__SHIFT 0x10
++#define CRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X_MASK 0x00003FFFL
++#define CRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y_MASK 0x3FFF0000L
++//CRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END
++#define CRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X__SHIFT 0x0
++#define CRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y__SHIFT 0x10
++#define CRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X_MASK 0x00003FFFL
++#define CRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y_MASK 0x3FFF0000L
++//CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL
++#define CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__SHIFT 0x0
++#define CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS__SHIFT 0x4
++#define CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS__SHIFT 0x8
++#define CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__SHIFT 0x10
++#define CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__SHIFT 0x14
++#define CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__SHIFT 0x1d
++#define CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_MASK 0x00000001L
++#define CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS_MASK 0x00000010L
++#define CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS_MASK 0x00000100L
++#define CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_MASK 0x00010000L
++#define CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_MASK 0x00100000L
++#define CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_MASK 0xE0000000L
++//CRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL
++#define CRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE__SHIFT 0x0
++#define CRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS__SHIFT 0x4
++#define CRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS__SHIFT 0x8
++#define CRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR__SHIFT 0x10
++#define CRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE__SHIFT 0x14
++#define CRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE_MASK 0x00000001L
++#define CRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS_MASK 0x00000010L
++#define CRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS_MASK 0x00000100L
++#define CRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR_MASK 0x00010000L
++#define CRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE_MASK 0x00100000L
++//CRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL
++#define CRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__SHIFT 0x0
++#define CRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS__SHIFT 0x4
++#define CRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS__SHIFT 0x8
++#define CRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__SHIFT 0x10
++#define CRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__SHIFT 0x14
++#define CRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_MASK 0x00000001L
++#define CRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS_MASK 0x00000010L
++#define CRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS_MASK 0x00000100L
++#define CRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_MASK 0x00010000L
++#define CRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_MASK 0x00100000L
++//CRTC3_CRTC_STATIC_SCREEN_CONTROL
++#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0
++#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10
++#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18
++#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19
++#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a
++#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b
++#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c
++#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e
++#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f
++#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL
++#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L
++#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x01000000L
++#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x02000000L
++#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x04000000L
++#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x08000000L
++#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000L
++#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L
++#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L
++//CRTC3_CRTC_3D_STRUCTURE_CONTROL
++#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0
++#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4
++#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8
++#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc
++#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10
++#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11
++#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12
++#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x00000001L
++#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x00000010L
++#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L
++#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L
++#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L
++#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L
++#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L
++//CRTC3_CRTC_GSL_VSYNC_GAP
++#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0
++#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8
++#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10
++#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11
++#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13
++#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14
++#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17
++#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18
++#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL
++#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L
++#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L
++#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x00060000L
++#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L
++#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L
++#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L
++#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xFF000000L
++//CRTC3_CRTC_GSL_WINDOW
++#define CRTC3_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0
++#define CRTC3_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10
++#define CRTC3_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x00003FFFL
++#define CRTC3_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x3FFF0000L
++//CRTC3_CRTC_GSL_CONTROL
++#define CRTC3_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0
++#define CRTC3_CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10
++#define CRTC3_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c
++#define CRTC3_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x00003FFFL
++#define CRTC3_CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x001F0000L
++#define CRTC3_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L
++//CRTC3_CRTC_RANGE_TIMING_INT_STATUS
++#define CRTC3_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0
++#define CRTC3_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4
++#define CRTC3_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8
++#define CRTC3_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc
++#define CRTC3_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10
++#define CRTC3_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L
++#define CRTC3_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L
++#define CRTC3_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L
++#define CRTC3_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L
++#define CRTC3_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L
++//CRTC3_CRTC_DRR_CONTROL
++#define CRTC3_CRTC_DRR_CONTROL__CRTC_XDMA_PREFETCH_DELAY__SHIFT 0x0
++#define CRTC3_CRTC_DRR_CONTROL__CRTC_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0xe
++#define CRTC3_CRTC_DRR_CONTROL__CRTC_SET_V_TOTAL_MIN_AUTO_DIS__SHIFT 0x1c
++#define CRTC3_CRTC_DRR_CONTROL__CRTC_DRR_MODE_DBUF_UPDATE_MODE__SHIFT 0x1d
++#define CRTC3_CRTC_DRR_CONTROL__CRTC_XDMA_PREFETCH_DELAY_MASK 0x00003FFFL
++#define CRTC3_CRTC_DRR_CONTROL__CRTC_V_TOTAL_LAST_USED_BY_DRR_MASK 0x0FFFC000L
++#define CRTC3_CRTC_DRR_CONTROL__CRTC_SET_V_TOTAL_MIN_AUTO_DIS_MASK 0x10000000L
++#define CRTC3_CRTC_DRR_CONTROL__CRTC_DRR_MODE_DBUF_UPDATE_MODE_MASK 0x60000000L
++
++
++// addressBlock: dce_dc_fmt3_dispdec
++//FMT3_FMT_CLAMP_COMPONENT_R
++#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0
++#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10
++#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL
++#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L
++//FMT3_FMT_CLAMP_COMPONENT_G
++#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0
++#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10
++#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL
++#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L
++//FMT3_FMT_CLAMP_COMPONENT_B
++#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0
++#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10
++#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL
++#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L
++//FMT3_FMT_DYNAMIC_EXP_CNTL
++#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0
++#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4
++#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L
++#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L
++//FMT3_FMT_CONTROL
++#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0
++#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT 0x4
++#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8
++#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc
++#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10
++#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12
++#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14
++#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15
++#define FMT3_FMT_CONTROL__FMT_SRC_SELECT__SHIFT 0x18
++#define FMT3_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED__SHIFT 0x1e
++#define FMT3_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_CLEAR__SHIFT 0x1f
++#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L
++#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK 0x00000010L
++#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L
++#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L
++#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L
++#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L
++#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L
++#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L
++#define FMT3_FMT_CONTROL__FMT_SRC_SELECT_MASK 0x07000000L
++#define FMT3_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_MASK 0x40000000L
++#define FMT3_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_CLEAR_MASK 0x80000000L
++//FMT3_FMT_BIT_DEPTH_CONTROL
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L
++//FMT3_FMT_DITHER_RAND_R_SEED
++#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0
++#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10
++#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL
++#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L
++//FMT3_FMT_DITHER_RAND_G_SEED
++#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0
++#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10
++#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL
++#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L
++//FMT3_FMT_DITHER_RAND_B_SEED
++#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0
++#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10
++#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL
++#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L
++//FMT3_FMT_CLAMP_CNTL
++#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0
++#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10
++#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L
++#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L
++//FMT3_FMT_CRC_CNTL
++#define FMT3_FMT_CRC_CNTL__FMT_CRC_EN__SHIFT 0x0
++#define FMT3_FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN__SHIFT 0x1
++#define FMT3_FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT 0x4
++#define FMT3_FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING__SHIFT 0x5
++#define FMT3_FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN__SHIFT 0x6
++#define FMT3_FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB__SHIFT 0x8
++#define FMT3_FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE__SHIFT 0x9
++#define FMT3_FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT 0xc
++#define FMT3_FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
++#define FMT3_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT 0x14
++#define FMT3_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT 0x18
++#define FMT3_FMT_CRC_CNTL__FMT_CRC_EN_MASK 0x00000001L
++#define FMT3_FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN_MASK 0x00000002L
++#define FMT3_FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK 0x00000010L
++#define FMT3_FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING_MASK 0x00000020L
++#define FMT3_FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN_MASK 0x00000040L
++#define FMT3_FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB_MASK 0x00000100L
++#define FMT3_FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE_MASK 0x00000200L
++#define FMT3_FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK 0x00003000L
++#define FMT3_FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
++#define FMT3_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK 0x00100000L
++#define FMT3_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK 0x01000000L
++//FMT3_FMT_CRC_SIG_RED_GREEN_MASK
++#define FMT3_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT 0x0
++#define FMT3_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT 0x10
++#define FMT3_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK 0x0000FFFFL
++#define FMT3_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L
++//FMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK
++#define FMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT 0x0
++#define FMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT 0x10
++#define FMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL
++#define FMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L
++//FMT3_FMT_CRC_SIG_RED_GREEN
++#define FMT3_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT 0x0
++#define FMT3_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT 0x10
++#define FMT3_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK 0x0000FFFFL
++#define FMT3_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK 0xFFFF0000L
++//FMT3_FMT_CRC_SIG_BLUE_CONTROL
++#define FMT3_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT 0x0
++#define FMT3_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT 0x10
++#define FMT3_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK 0x0000FFFFL
++#define FMT3_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK 0xFFFF0000L
++//FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL
++#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0
++#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL
++//FMT3_FMT_420_HBLANK_EARLY_START
++#define FMT3_FMT_420_HBLANK_EARLY_START__FMT_420_HBLANK_EARLY_START__SHIFT 0x0
++#define FMT3_FMT_420_HBLANK_EARLY_START__FMT_420_HBLANK_EARLY_START_MASK 0x00000FFFL
++
++
++// addressBlock: dce_dc_dcp4_dispdec
++//DCP4_GRPH_ENABLE
++#define DCP4_GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0
++#define DCP4_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL__SHIFT 0x1
++#define DCP4_GRPH_ENABLE__GRPH_ENABLE_MASK 0x00000001L
++#define DCP4_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL_MASK 0x00000002L
++//DCP4_GRPH_CONTROL
++#define DCP4_GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0
++#define DCP4_GRPH_CONTROL__GRPH_SE_ENABLE__SHIFT 0x2
++#define DCP4_GRPH_CONTROL__GRPH_Z__SHIFT 0x4
++#define DCP4_GRPH_CONTROL__GRPH_DIM_TYPE__SHIFT 0x6
++#define DCP4_GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8
++#define DCP4_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0xc
++#define DCP4_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10
++#define DCP4_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11
++#define DCP4_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES__SHIFT 0x12
++#define DCP4_GRPH_CONTROL__GRPH_SW_MODE__SHIFT 0x14
++#define DCP4_GRPH_CONTROL__GRPH_NUM_PIPES__SHIFT 0x1c
++#define DCP4_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f
++#define DCP4_GRPH_CONTROL__GRPH_DEPTH_MASK 0x00000003L
++#define DCP4_GRPH_CONTROL__GRPH_SE_ENABLE_MASK 0x00000004L
++#define DCP4_GRPH_CONTROL__GRPH_Z_MASK 0x00000030L
++#define DCP4_GRPH_CONTROL__GRPH_DIM_TYPE_MASK 0x000000C0L
++#define DCP4_GRPH_CONTROL__GRPH_FORMAT_MASK 0x00000700L
++#define DCP4_GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0x00007000L
++#define DCP4_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x00010000L
++#define DCP4_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x00020000L
++#define DCP4_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES_MASK 0x000C0000L
++#define DCP4_GRPH_CONTROL__GRPH_SW_MODE_MASK 0x01F00000L
++#define DCP4_GRPH_CONTROL__GRPH_NUM_PIPES_MASK 0x70000000L
++#define DCP4_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000L
++//DCP4_GRPH_LUT_10BIT_BYPASS
++#define DCP4_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT 0x8
++#define DCP4_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x10
++#define DCP4_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK 0x00000100L
++#define DCP4_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x00010000L
++//DCP4_GRPH_SWAP_CNTL
++#define DCP4_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0
++#define DCP4_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4
++#define DCP4_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6
++#define DCP4_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8
++#define DCP4_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT 0xa
++#define DCP4_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x00000003L
++#define DCP4_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x00000030L
++#define DCP4_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0x000000C0L
++#define DCP4_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x00000300L
++#define DCP4_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK 0x00000C00L
++//DCP4_GRPH_PRIMARY_SURFACE_ADDRESS
++#define DCP4_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT 0x0
++#define DCP4_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT 0x8
++#define DCP4_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK 0x00000001L
++#define DCP4_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
++//DCP4_GRPH_SECONDARY_SURFACE_ADDRESS
++#define DCP4_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT 0x0
++#define DCP4_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8
++#define DCP4_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK 0x00000001L
++#define DCP4_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
++//DCP4_GRPH_PITCH
++#define DCP4_GRPH_PITCH__GRPH_PITCH__SHIFT 0x0
++#define DCP4_GRPH_PITCH__GRPH_PITCH_MASK 0x00007FFFL
++//DCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
++#define DCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define DCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
++//DCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
++#define DCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define DCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
++//DCP4_GRPH_SURFACE_OFFSET_X
++#define DCP4_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT 0x0
++#define DCP4_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK 0x00003FFFL
++//DCP4_GRPH_SURFACE_OFFSET_Y
++#define DCP4_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT 0x0
++#define DCP4_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK 0x00003FFFL
++//DCP4_GRPH_X_START
++#define DCP4_GRPH_X_START__GRPH_X_START__SHIFT 0x0
++#define DCP4_GRPH_X_START__GRPH_X_START_MASK 0x00003FFFL
++//DCP4_GRPH_Y_START
++#define DCP4_GRPH_Y_START__GRPH_Y_START__SHIFT 0x0
++#define DCP4_GRPH_Y_START__GRPH_Y_START_MASK 0x00003FFFL
++//DCP4_GRPH_X_END
++#define DCP4_GRPH_X_END__GRPH_X_END__SHIFT 0x0
++#define DCP4_GRPH_X_END__GRPH_X_END_MASK 0x00007FFFL
++//DCP4_GRPH_Y_END
++#define DCP4_GRPH_Y_END__GRPH_Y_END__SHIFT 0x0
++#define DCP4_GRPH_Y_END__GRPH_Y_END_MASK 0x00007FFFL
++//DCP4_INPUT_GAMMA_CONTROL
++#define DCP4_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x0
++#define DCP4_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK 0x00000001L
++//DCP4_GRPH_UPDATE
++#define DCP4_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0
++#define DCP4_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1
++#define DCP4_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2
++#define DCP4_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3
++#define DCP4_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR__SHIFT 0x8
++#define DCP4_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE__SHIFT 0x9
++#define DCP4_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE__SHIFT 0xa
++#define DCP4_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10
++#define DCP4_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14
++#define DCP4_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
++#define DCP4_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c
++#define DCP4_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x00000001L
++#define DCP4_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x00000002L
++#define DCP4_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x00000004L
++#define DCP4_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x00000008L
++#define DCP4_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR_MASK 0x00000100L
++#define DCP4_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE_MASK 0x00000200L
++#define DCP4_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE_MASK 0x00000400L
++#define DCP4_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x00010000L
++#define DCP4_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x00100000L
++#define DCP4_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
++#define DCP4_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000L
++//DCP4_GRPH_FLIP_CONTROL
++#define DCP4_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT 0x0
++#define DCP4_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN__SHIFT 0x1
++#define DCP4_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN__SHIFT 0x4
++#define DCP4_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT 0x5
++#define DCP4_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK 0x00000001L
++#define DCP4_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN_MASK 0x00000002L
++#define DCP4_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN_MASK 0x00000010L
++#define DCP4_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK 0x00000020L
++//DCP4_GRPH_SURFACE_ADDRESS_INUSE
++#define DCP4_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT 0x8
++#define DCP4_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK 0xFFFFFF00L
++//DCP4_GRPH_DFQ_CONTROL
++#define DCP4_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x0
++#define DCP4_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x4
++#define DCP4_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8
++#define DCP4_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x00000001L
++#define DCP4_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x00000070L
++#define DCP4_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x00000700L
++//DCP4_GRPH_DFQ_STATUS
++#define DCP4_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x0
++#define DCP4_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4
++#define DCP4_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x8
++#define DCP4_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x9
++#define DCP4_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0x0000000FL
++#define DCP4_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0x000000F0L
++#define DCP4_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x00000100L
++#define DCP4_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x00000200L
++//DCP4_GRPH_INTERRUPT_STATUS
++#define DCP4_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0
++#define DCP4_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8
++#define DCP4_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x00000001L
++#define DCP4_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x00000100L
++//DCP4_GRPH_INTERRUPT_CONTROL
++#define DCP4_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0
++#define DCP4_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8
++#define DCP4_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x00000001L
++#define DCP4_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x00000100L
++//DCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE
++#define DCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0
++#define DCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK 0x000000FFL
++//DCP4_GRPH_COMPRESS_SURFACE_ADDRESS
++#define DCP4_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT 0x8
++#define DCP4_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK 0xFFFFFF00L
++//DCP4_GRPH_COMPRESS_PITCH
++#define DCP4_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT 0x6
++#define DCP4_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK 0x0001FFC0L
++//DCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH
++#define DCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define DCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
++//DCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT
++#define DCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__SHIFT 0x0
++#define DCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_MASK 0x000000FFL
++//DCP4_PRESCALE_GRPH_CONTROL
++#define DCP4_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT 0x0
++#define DCP4_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT 0x1
++#define DCP4_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x2
++#define DCP4_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT 0x3
++#define DCP4_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT 0x4
++#define DCP4_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK 0x00000001L
++#define DCP4_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x00000002L
++#define DCP4_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK 0x00000004L
++#define DCP4_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK 0x00000008L
++#define DCP4_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK 0x00000010L
++//DCP4_PRESCALE_VALUES_GRPH_R
++#define DCP4_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT 0x0
++#define DCP4_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT 0x10
++#define DCP4_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK 0x0000FFFFL
++#define DCP4_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK 0xFFFF0000L
++//DCP4_PRESCALE_VALUES_GRPH_G
++#define DCP4_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT 0x0
++#define DCP4_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT 0x10
++#define DCP4_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK 0x0000FFFFL
++#define DCP4_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK 0xFFFF0000L
++//DCP4_PRESCALE_VALUES_GRPH_B
++#define DCP4_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT 0x0
++#define DCP4_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT 0x10
++#define DCP4_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK 0x0000FFFFL
++#define DCP4_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK 0xFFFF0000L
++//DCP4_INPUT_CSC_CONTROL
++#define DCP4_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT 0x0
++#define DCP4_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK 0x00000003L
++//DCP4_INPUT_CSC_C11_C12
++#define DCP4_INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT 0x0
++#define DCP4_INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT 0x10
++#define DCP4_INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK 0x0000FFFFL
++#define DCP4_INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK 0xFFFF0000L
++//DCP4_INPUT_CSC_C13_C14
++#define DCP4_INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT 0x0
++#define DCP4_INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT 0x10
++#define DCP4_INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK 0x0000FFFFL
++#define DCP4_INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK 0xFFFF0000L
++//DCP4_INPUT_CSC_C21_C22
++#define DCP4_INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT 0x0
++#define DCP4_INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT 0x10
++#define DCP4_INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK 0x0000FFFFL
++#define DCP4_INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK 0xFFFF0000L
++//DCP4_INPUT_CSC_C23_C24
++#define DCP4_INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT 0x0
++#define DCP4_INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT 0x10
++#define DCP4_INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK 0x0000FFFFL
++#define DCP4_INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK 0xFFFF0000L
++//DCP4_INPUT_CSC_C31_C32
++#define DCP4_INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT 0x0
++#define DCP4_INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT 0x10
++#define DCP4_INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK 0x0000FFFFL
++#define DCP4_INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK 0xFFFF0000L
++//DCP4_INPUT_CSC_C33_C34
++#define DCP4_INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT 0x0
++#define DCP4_INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT 0x10
++#define DCP4_INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK 0x0000FFFFL
++#define DCP4_INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK 0xFFFF0000L
++//DCP4_OUTPUT_CSC_CONTROL
++#define DCP4_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT 0x0
++#define DCP4_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK 0x00000007L
++//DCP4_OUTPUT_CSC_C11_C12
++#define DCP4_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT 0x0
++#define DCP4_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT 0x10
++#define DCP4_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK 0x0000FFFFL
++#define DCP4_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK 0xFFFF0000L
++//DCP4_OUTPUT_CSC_C13_C14
++#define DCP4_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT 0x0
++#define DCP4_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT 0x10
++#define DCP4_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK 0x0000FFFFL
++#define DCP4_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK 0xFFFF0000L
++//DCP4_OUTPUT_CSC_C21_C22
++#define DCP4_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT 0x0
++#define DCP4_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT 0x10
++#define DCP4_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK 0x0000FFFFL
++#define DCP4_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK 0xFFFF0000L
++//DCP4_OUTPUT_CSC_C23_C24
++#define DCP4_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT 0x0
++#define DCP4_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT 0x10
++#define DCP4_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK 0x0000FFFFL
++#define DCP4_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK 0xFFFF0000L
++//DCP4_OUTPUT_CSC_C31_C32
++#define DCP4_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT 0x0
++#define DCP4_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT 0x10
++#define DCP4_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK 0x0000FFFFL
++#define DCP4_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK 0xFFFF0000L
++//DCP4_OUTPUT_CSC_C33_C34
++#define DCP4_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT 0x0
++#define DCP4_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT 0x10
++#define DCP4_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK 0x0000FFFFL
++#define DCP4_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK 0xFFFF0000L
++//DCP4_COMM_MATRIXA_TRANS_C11_C12
++#define DCP4_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT 0x0
++#define DCP4_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT 0x10
++#define DCP4_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK 0x0000FFFFL
++#define DCP4_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK 0xFFFF0000L
++//DCP4_COMM_MATRIXA_TRANS_C13_C14
++#define DCP4_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT 0x0
++#define DCP4_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT 0x10
++#define DCP4_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK 0x0000FFFFL
++#define DCP4_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK 0xFFFF0000L
++//DCP4_COMM_MATRIXA_TRANS_C21_C22
++#define DCP4_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT 0x0
++#define DCP4_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT 0x10
++#define DCP4_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK 0x0000FFFFL
++#define DCP4_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK 0xFFFF0000L
++//DCP4_COMM_MATRIXA_TRANS_C23_C24
++#define DCP4_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT 0x0
++#define DCP4_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT 0x10
++#define DCP4_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK 0x0000FFFFL
++#define DCP4_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK 0xFFFF0000L
++//DCP4_COMM_MATRIXA_TRANS_C31_C32
++#define DCP4_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT 0x0
++#define DCP4_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT 0x10
++#define DCP4_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK 0x0000FFFFL
++#define DCP4_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK 0xFFFF0000L
++//DCP4_COMM_MATRIXA_TRANS_C33_C34
++#define DCP4_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT 0x0
++#define DCP4_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT 0x10
++#define DCP4_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK 0x0000FFFFL
++#define DCP4_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK 0xFFFF0000L
++//DCP4_COMM_MATRIXB_TRANS_C11_C12
++#define DCP4_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT 0x0
++#define DCP4_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT 0x10
++#define DCP4_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK 0x0000FFFFL
++#define DCP4_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK 0xFFFF0000L
++//DCP4_COMM_MATRIXB_TRANS_C13_C14
++#define DCP4_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT 0x0
++#define DCP4_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT 0x10
++#define DCP4_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK 0x0000FFFFL
++#define DCP4_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK 0xFFFF0000L
++//DCP4_COMM_MATRIXB_TRANS_C21_C22
++#define DCP4_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT 0x0
++#define DCP4_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT 0x10
++#define DCP4_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK 0x0000FFFFL
++#define DCP4_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK 0xFFFF0000L
++//DCP4_COMM_MATRIXB_TRANS_C23_C24
++#define DCP4_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT 0x0
++#define DCP4_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT 0x10
++#define DCP4_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK 0x0000FFFFL
++#define DCP4_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK 0xFFFF0000L
++//DCP4_COMM_MATRIXB_TRANS_C31_C32
++#define DCP4_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT 0x0
++#define DCP4_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT 0x10
++#define DCP4_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK 0x0000FFFFL
++#define DCP4_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK 0xFFFF0000L
++//DCP4_COMM_MATRIXB_TRANS_C33_C34
++#define DCP4_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT 0x0
++#define DCP4_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT 0x10
++#define DCP4_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK 0x0000FFFFL
++#define DCP4_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK 0xFFFF0000L
++//DCP4_DENORM_CONTROL
++#define DCP4_DENORM_CONTROL__DENORM_MODE__SHIFT 0x0
++#define DCP4_DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT 0x4
++#define DCP4_DENORM_CONTROL__DENORM_MODE_MASK 0x00000007L
++#define DCP4_DENORM_CONTROL__DENORM_14BIT_OUT_MASK 0x00000010L
++//DCP4_OUT_ROUND_CONTROL
++#define DCP4_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT 0x0
++#define DCP4_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK 0x0000000FL
++//DCP4_OUT_CLAMP_CONTROL_R_CR
++#define DCP4_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT 0x0
++#define DCP4_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT 0x10
++#define DCP4_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK 0x00003FFFL
++#define DCP4_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK 0x3FFF0000L
++//DCP4_OUT_CLAMP_CONTROL_G_Y
++#define DCP4_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT 0x0
++#define DCP4_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT 0x10
++#define DCP4_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK 0x00003FFFL
++#define DCP4_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK 0x3FFF0000L
++//DCP4_OUT_CLAMP_CONTROL_B_CB
++#define DCP4_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT 0x0
++#define DCP4_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT 0x10
++#define DCP4_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK 0x00003FFFL
++#define DCP4_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK 0x3FFF0000L
++//DCP4_KEY_CONTROL
++#define DCP4_KEY_CONTROL__KEY_MODE__SHIFT 0x1
++#define DCP4_KEY_CONTROL__KEY_MODE_MASK 0x00000006L
++//DCP4_KEY_RANGE_ALPHA
++#define DCP4_KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT 0x0
++#define DCP4_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT 0x10
++#define DCP4_KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK 0x0000FFFFL
++#define DCP4_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK 0xFFFF0000L
++//DCP4_KEY_RANGE_RED
++#define DCP4_KEY_RANGE_RED__KEY_RED_LOW__SHIFT 0x0
++#define DCP4_KEY_RANGE_RED__KEY_RED_HIGH__SHIFT 0x10
++#define DCP4_KEY_RANGE_RED__KEY_RED_LOW_MASK 0x0000FFFFL
++#define DCP4_KEY_RANGE_RED__KEY_RED_HIGH_MASK 0xFFFF0000L
++//DCP4_KEY_RANGE_GREEN
++#define DCP4_KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT 0x0
++#define DCP4_KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT 0x10
++#define DCP4_KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK 0x0000FFFFL
++#define DCP4_KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK 0xFFFF0000L
++//DCP4_KEY_RANGE_BLUE
++#define DCP4_KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT 0x0
++#define DCP4_KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT 0x10
++#define DCP4_KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK 0x0000FFFFL
++#define DCP4_KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK 0xFFFF0000L
++//DCP4_DEGAMMA_CONTROL
++#define DCP4_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x0
++#define DCP4_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT 0x8
++#define DCP4_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0xc
++#define DCP4_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x00000003L
++#define DCP4_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK 0x00000300L
++#define DCP4_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK 0x00003000L
++//DCP4_GAMUT_REMAP_CONTROL
++#define DCP4_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT 0x0
++#define DCP4_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK 0x00000003L
++//DCP4_GAMUT_REMAP_C11_C12
++#define DCP4_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT 0x0
++#define DCP4_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT 0x10
++#define DCP4_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK 0x0000FFFFL
++#define DCP4_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK 0xFFFF0000L
++//DCP4_GAMUT_REMAP_C13_C14
++#define DCP4_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT 0x0
++#define DCP4_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT 0x10
++#define DCP4_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK 0x0000FFFFL
++#define DCP4_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK 0xFFFF0000L
++//DCP4_GAMUT_REMAP_C21_C22
++#define DCP4_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT 0x0
++#define DCP4_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT 0x10
++#define DCP4_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK 0x0000FFFFL
++#define DCP4_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK 0xFFFF0000L
++//DCP4_GAMUT_REMAP_C23_C24
++#define DCP4_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT 0x0
++#define DCP4_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT 0x10
++#define DCP4_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK 0x0000FFFFL
++#define DCP4_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK 0xFFFF0000L
++//DCP4_GAMUT_REMAP_C31_C32
++#define DCP4_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT 0x0
++#define DCP4_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT 0x10
++#define DCP4_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK 0x0000FFFFL
++#define DCP4_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK 0xFFFF0000L
++//DCP4_GAMUT_REMAP_C33_C34
++#define DCP4_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT 0x0
++#define DCP4_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT 0x10
++#define DCP4_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK 0x0000FFFFL
++#define DCP4_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK 0xFFFF0000L
++//DCP4_DCP_SPATIAL_DITHER_CNTL
++#define DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT 0x0
++#define DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT 0x4
++#define DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT 0x6
++#define DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT 0x8
++#define DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT 0x9
++#define DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT 0xa
++#define DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK 0x00000001L
++#define DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK 0x00000030L
++#define DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK 0x000000C0L
++#define DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK 0x00000100L
++#define DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK 0x00000200L
++#define DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK 0x00000400L
++//DCP4_DCP_RANDOM_SEEDS
++#define DCP4_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT 0x0
++#define DCP4_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT 0x8
++#define DCP4_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT 0x10
++#define DCP4_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK 0x000000FFL
++#define DCP4_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK 0x0000FF00L
++#define DCP4_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK 0x00FF0000L
++//DCP4_DCP_FP_CONVERTED_FIELD
++#define DCP4_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT 0x0
++#define DCP4_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14
++#define DCP4_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK 0x0003FFFFL
++#define DCP4_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK 0x07F00000L
++//DCP4_CUR_CONTROL
++#define DCP4_CUR_CONTROL__CURSOR_EN__SHIFT 0x0
++#define DCP4_CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT 0x4
++#define DCP4_CUR_CONTROL__CURSOR_MODE__SHIFT 0x8
++#define DCP4_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM__SHIFT 0xb
++#define DCP4_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION__SHIFT 0xc
++#define DCP4_CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x10
++#define DCP4_CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT 0x14
++#define DCP4_CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT 0x18
++#define DCP4_CUR_CONTROL__CURSOR_EN_MASK 0x00000001L
++#define DCP4_CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK 0x00000010L
++#define DCP4_CUR_CONTROL__CURSOR_MODE_MASK 0x00000300L
++#define DCP4_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM_MASK 0x00000800L
++#define DCP4_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION_MASK 0x0000F000L
++#define DCP4_CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00010000L
++#define DCP4_CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK 0x00100000L
++#define DCP4_CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK 0x07000000L
++//DCP4_CUR_SURFACE_ADDRESS
++#define DCP4_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0
++#define DCP4_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
++//DCP4_CUR_SIZE
++#define DCP4_CUR_SIZE__CURSOR_HEIGHT__SHIFT 0x0
++#define DCP4_CUR_SIZE__CURSOR_WIDTH__SHIFT 0x10
++#define DCP4_CUR_SIZE__CURSOR_HEIGHT_MASK 0x0000007FL
++#define DCP4_CUR_SIZE__CURSOR_WIDTH_MASK 0x007F0000L
++//DCP4_CUR_SURFACE_ADDRESS_HIGH
++#define DCP4_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define DCP4_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
++//DCP4_CUR_POSITION
++#define DCP4_CUR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0
++#define DCP4_CUR_POSITION__CURSOR_X_POSITION__SHIFT 0x10
++#define DCP4_CUR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL
++#define DCP4_CUR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L
++//DCP4_CUR_HOT_SPOT
++#define DCP4_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0
++#define DCP4_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10
++#define DCP4_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x0000007FL
++#define DCP4_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x007F0000L
++//DCP4_CUR_COLOR1
++#define DCP4_CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT 0x0
++#define DCP4_CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT 0x8
++#define DCP4_CUR_COLOR1__CUR_COLOR1_RED__SHIFT 0x10
++#define DCP4_CUR_COLOR1__CUR_COLOR1_BLUE_MASK 0x000000FFL
++#define DCP4_CUR_COLOR1__CUR_COLOR1_GREEN_MASK 0x0000FF00L
++#define DCP4_CUR_COLOR1__CUR_COLOR1_RED_MASK 0x00FF0000L
++//DCP4_CUR_COLOR2
++#define DCP4_CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT 0x0
++#define DCP4_CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT 0x8
++#define DCP4_CUR_COLOR2__CUR_COLOR2_RED__SHIFT 0x10
++#define DCP4_CUR_COLOR2__CUR_COLOR2_BLUE_MASK 0x000000FFL
++#define DCP4_CUR_COLOR2__CUR_COLOR2_GREEN_MASK 0x0000FF00L
++#define DCP4_CUR_COLOR2__CUR_COLOR2_RED_MASK 0x00FF0000L
++//DCP4_CUR_UPDATE
++#define DCP4_CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT 0x0
++#define DCP4_CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT 0x1
++#define DCP4_CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT 0x10
++#define DCP4_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
++#define DCP4_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE__SHIFT 0x19
++#define DCP4_CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK 0x00000001L
++#define DCP4_CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x00000002L
++#define DCP4_CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK 0x00010000L
++#define DCP4_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
++#define DCP4_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE_MASK 0x06000000L
++//DCP4_CUR_REQUEST_FILTER_CNTL
++#define DCP4_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT 0x0
++#define DCP4_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK 0x00000001L
++//DCP4_CUR_STEREO_CONTROL
++#define DCP4_CUR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0
++#define DCP4_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4
++#define DCP4_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x10
++#define DCP4_CUR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L
++#define DCP4_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x00003FF0L
++#define DCP4_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0x03FF0000L
++//DCP4_DC_LUT_RW_MODE
++#define DCP4_DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT 0x0
++#define DCP4_DC_LUT_RW_MODE__DC_LUT_ERROR__SHIFT 0x10
++#define DCP4_DC_LUT_RW_MODE__DC_LUT_ERROR_RST__SHIFT 0x11
++#define DCP4_DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK 0x00000001L
++#define DCP4_DC_LUT_RW_MODE__DC_LUT_ERROR_MASK 0x00010000L
++#define DCP4_DC_LUT_RW_MODE__DC_LUT_ERROR_RST_MASK 0x00020000L
++//DCP4_DC_LUT_RW_INDEX
++#define DCP4_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT 0x0
++#define DCP4_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK 0x000000FFL
++//DCP4_DC_LUT_SEQ_COLOR
++#define DCP4_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT 0x0
++#define DCP4_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK 0x0000FFFFL
++//DCP4_DC_LUT_PWL_DATA
++#define DCP4_DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT 0x0
++#define DCP4_DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT 0x10
++#define DCP4_DC_LUT_PWL_DATA__DC_LUT_BASE_MASK 0x0000FFFFL
++#define DCP4_DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK 0xFFFF0000L
++//DCP4_DC_LUT_30_COLOR
++#define DCP4_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT 0x0
++#define DCP4_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT 0xa
++#define DCP4_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT 0x14
++#define DCP4_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK 0x000003FFL
++#define DCP4_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK 0x000FFC00L
++#define DCP4_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK 0x3FF00000L
++//DCP4_DC_LUT_VGA_ACCESS_ENABLE
++#define DCP4_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT 0x0
++#define DCP4_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK 0x00000001L
++//DCP4_DC_LUT_WRITE_EN_MASK
++#define DCP4_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT 0x0
++#define DCP4_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK 0x00000007L
++//DCP4_DC_LUT_AUTOFILL
++#define DCP4_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT 0x0
++#define DCP4_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT 0x1
++#define DCP4_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK 0x00000001L
++#define DCP4_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x00000002L
++//DCP4_DC_LUT_CONTROL
++#define DCP4_DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT 0x0
++#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT 0x4
++#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT 0x5
++#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT 0x6
++#define DCP4_DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT 0x8
++#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT 0xc
++#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT 0xd
++#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT 0xe
++#define DCP4_DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT 0x10
++#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT 0x14
++#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT 0x15
++#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT 0x16
++#define DCP4_DC_LUT_CONTROL__DC_LUT_INC_B_MASK 0x0000000FL
++#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK 0x00000010L
++#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK 0x00000020L
++#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK 0x000000C0L
++#define DCP4_DC_LUT_CONTROL__DC_LUT_INC_G_MASK 0x00000F00L
++#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK 0x00001000L
++#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK 0x00002000L
++#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK 0x0000C000L
++#define DCP4_DC_LUT_CONTROL__DC_LUT_INC_R_MASK 0x000F0000L
++#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK 0x00100000L
++#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK 0x00200000L
++#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK 0x00C00000L
++//DCP4_DC_LUT_BLACK_OFFSET_BLUE
++#define DCP4_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0
++#define DCP4_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK 0x0000FFFFL
++//DCP4_DC_LUT_BLACK_OFFSET_GREEN
++#define DCP4_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0
++#define DCP4_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK 0x0000FFFFL
++//DCP4_DC_LUT_BLACK_OFFSET_RED
++#define DCP4_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT 0x0
++#define DCP4_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK 0x0000FFFFL
++//DCP4_DC_LUT_WHITE_OFFSET_BLUE
++#define DCP4_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT 0x0
++#define DCP4_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK 0x0000FFFFL
++//DCP4_DC_LUT_WHITE_OFFSET_GREEN
++#define DCP4_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT 0x0
++#define DCP4_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK 0x0000FFFFL
++//DCP4_DC_LUT_WHITE_OFFSET_RED
++#define DCP4_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT 0x0
++#define DCP4_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK 0x0000FFFFL
++//DCP4_DCP_CRC_CONTROL
++#define DCP4_DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT 0x0
++#define DCP4_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x2
++#define DCP4_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT 0x8
++#define DCP4_DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK 0x00000001L
++#define DCP4_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK 0x0000001CL
++#define DCP4_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK 0x00000300L
++//DCP4_DCP_CRC_MASK
++#define DCP4_DCP_CRC_MASK__DCP_CRC_MASK__SHIFT 0x0
++#define DCP4_DCP_CRC_MASK__DCP_CRC_MASK_MASK 0xFFFFFFFFL
++//DCP4_DCP_CRC_CURRENT
++#define DCP4_DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT 0x0
++#define DCP4_DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK 0xFFFFFFFFL
++//DCP4_DVMM_PTE_CONTROL
++#define DCP4_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT 0x0
++#define DCP4_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT 0x1
++#define DCP4_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT 0x5
++#define DCP4_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT 0x9
++#define DCP4_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT 0x14
++#define DCP4_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT 0x15
++#define DCP4_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK 0x00000001L
++#define DCP4_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK 0x0000001EL
++#define DCP4_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK 0x000001E0L
++#define DCP4_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK 0x0007FE00L
++#define DCP4_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK 0x00100000L
++#define DCP4_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK 0x00200000L
++//DCP4_DCP_CRC_LAST
++#define DCP4_DCP_CRC_LAST__DCP_CRC_LAST__SHIFT 0x0
++#define DCP4_DCP_CRC_LAST__DCP_CRC_LAST_MASK 0xFFFFFFFFL
++//DCP4_DVMM_PTE_ARB_CONTROL
++#define DCP4_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT 0x0
++#define DCP4_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT 0x8
++#define DCP4_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK 0x0000003FL
++#define DCP4_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK 0x0000FF00L
++//DCP4_GRPH_FLIP_RATE_CNTL
++#define DCP4_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT 0x0
++#define DCP4_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT 0x3
++#define DCP4_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK 0x00000007L
++#define DCP4_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK 0x00000008L
++//DCP4_DCP_GSL_CONTROL
++#define DCP4_DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT 0x0
++#define DCP4_DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT 0x1
++#define DCP4_DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x2
++#define DCP4_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT 0x4
++#define DCP4_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT 0x14
++#define DCP4_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP__SHIFT 0x15
++#define DCP4_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN__SHIFT 0x17
++#define DCP4_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT 0x18
++#define DCP4_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC__SHIFT 0x1a
++#define DCP4_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT 0x1b
++#define DCP4_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT 0x1c
++#define DCP4_DCP_GSL_CONTROL__DCP_GSL0_EN_MASK 0x00000001L
++#define DCP4_DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x00000002L
++#define DCP4_DCP_GSL_CONTROL__DCP_GSL2_EN_MASK 0x00000004L
++#define DCP4_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK 0x000FFFF0L
++#define DCP4_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK 0x00100000L
++#define DCP4_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_MASK 0x00600000L
++#define DCP4_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_MASK 0x00800000L
++#define DCP4_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK 0x03000000L
++#define DCP4_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_MASK 0x04000000L
++#define DCP4_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK 0x08000000L
++#define DCP4_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK 0xF0000000L
++//DCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK
++#define DCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT 0x0
++#define DCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT 0x4
++#define DCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK 0x0000000FL
++#define DCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK 0x000001F0L
++//DCP4_GRPH_STEREOSYNC_FLIP
++#define DCP4_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0
++#define DCP4_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x8
++#define DCP4_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10
++#define DCP4_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11
++#define DCP4_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c
++#define DCP4_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x00000001L
++#define DCP4_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x00000300L
++#define DCP4_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x00010000L
++#define DCP4_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x00020000L
++#define DCP4_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000L
++//DCP4_HW_ROTATION
++#define DCP4_HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT 0x0
++#define DCP4_HW_ROTATION__GRPH_ROTATION_ANGLE_MASK 0x00000007L
++//DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL
++#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT 0x0
++#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT 0x1
++#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT 0x4
++#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK 0x00000001L
++#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK 0x00000002L
++#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK 0x0001FFF0L
++//DCP4_REGAMMA_CONTROL
++#define DCP4_REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT 0x0
++#define DCP4_REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK 0x00000007L
++//DCP4_REGAMMA_LUT_INDEX
++#define DCP4_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x0
++#define DCP4_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK 0x000001FFL
++//DCP4_REGAMMA_LUT_DATA
++#define DCP4_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT 0x0
++#define DCP4_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK 0x0007FFFFL
++//DCP4_REGAMMA_LUT_WRITE_EN_MASK
++#define DCP4_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x0
++#define DCP4_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x00000007L
++//DCP4_REGAMMA_CNTLA_START_CNTL
++#define DCP4_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x0
++#define DCP4_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14
++#define DCP4_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK 0x0003FFFFL
++#define DCP4_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
++//DCP4_REGAMMA_CNTLA_SLOPE_CNTL
++#define DCP4_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
++#define DCP4_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
++//DCP4_REGAMMA_CNTLA_END_CNTL1
++#define DCP4_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x0
++#define DCP4_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK 0x0000FFFFL
++//DCP4_REGAMMA_CNTLA_END_CNTL2
++#define DCP4_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0
++#define DCP4_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10
++#define DCP4_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
++#define DCP4_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xFFFF0000L
++//DCP4_REGAMMA_CNTLA_REGION_0_1
++#define DCP4_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
++#define DCP4_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
++#define DCP4_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
++#define DCP4_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP4_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
++#define DCP4_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP4_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP4_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
++//DCP4_REGAMMA_CNTLA_REGION_2_3
++#define DCP4_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
++#define DCP4_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
++#define DCP4_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
++#define DCP4_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP4_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
++#define DCP4_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP4_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP4_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
++//DCP4_REGAMMA_CNTLA_REGION_4_5
++#define DCP4_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
++#define DCP4_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
++#define DCP4_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
++#define DCP4_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP4_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
++#define DCP4_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP4_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP4_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
++//DCP4_REGAMMA_CNTLA_REGION_6_7
++#define DCP4_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
++#define DCP4_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
++#define DCP4_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
++#define DCP4_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP4_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
++#define DCP4_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP4_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP4_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
++//DCP4_REGAMMA_CNTLA_REGION_8_9
++#define DCP4_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
++#define DCP4_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
++#define DCP4_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
++#define DCP4_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP4_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
++#define DCP4_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP4_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP4_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
++//DCP4_REGAMMA_CNTLA_REGION_10_11
++#define DCP4_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
++#define DCP4_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
++#define DCP4_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
++#define DCP4_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP4_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
++#define DCP4_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP4_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP4_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
++//DCP4_REGAMMA_CNTLA_REGION_12_13
++#define DCP4_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
++#define DCP4_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
++#define DCP4_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
++#define DCP4_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP4_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
++#define DCP4_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP4_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP4_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
++//DCP4_REGAMMA_CNTLA_REGION_14_15
++#define DCP4_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
++#define DCP4_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
++#define DCP4_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
++#define DCP4_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP4_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
++#define DCP4_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP4_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP4_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
++//DCP4_REGAMMA_CNTLB_START_CNTL
++#define DCP4_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x0
++#define DCP4_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14
++#define DCP4_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK 0x0003FFFFL
++#define DCP4_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
++//DCP4_REGAMMA_CNTLB_SLOPE_CNTL
++#define DCP4_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
++#define DCP4_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
++//DCP4_REGAMMA_CNTLB_END_CNTL1
++#define DCP4_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x0
++#define DCP4_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK 0x0000FFFFL
++//DCP4_REGAMMA_CNTLB_END_CNTL2
++#define DCP4_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0
++#define DCP4_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10
++#define DCP4_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
++#define DCP4_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xFFFF0000L
++//DCP4_REGAMMA_CNTLB_REGION_0_1
++#define DCP4_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
++#define DCP4_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
++#define DCP4_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
++#define DCP4_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP4_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
++#define DCP4_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP4_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP4_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
++//DCP4_REGAMMA_CNTLB_REGION_2_3
++#define DCP4_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
++#define DCP4_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
++#define DCP4_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
++#define DCP4_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP4_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
++#define DCP4_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP4_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP4_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
++//DCP4_REGAMMA_CNTLB_REGION_4_5
++#define DCP4_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
++#define DCP4_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
++#define DCP4_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
++#define DCP4_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP4_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
++#define DCP4_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP4_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP4_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
++//DCP4_REGAMMA_CNTLB_REGION_6_7
++#define DCP4_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
++#define DCP4_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
++#define DCP4_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
++#define DCP4_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP4_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
++#define DCP4_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP4_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP4_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
++//DCP4_REGAMMA_CNTLB_REGION_8_9
++#define DCP4_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
++#define DCP4_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
++#define DCP4_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
++#define DCP4_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP4_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
++#define DCP4_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP4_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP4_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
++//DCP4_REGAMMA_CNTLB_REGION_10_11
++#define DCP4_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
++#define DCP4_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
++#define DCP4_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
++#define DCP4_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP4_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
++#define DCP4_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP4_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP4_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
++//DCP4_REGAMMA_CNTLB_REGION_12_13
++#define DCP4_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
++#define DCP4_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
++#define DCP4_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
++#define DCP4_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP4_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
++#define DCP4_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP4_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP4_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
++//DCP4_REGAMMA_CNTLB_REGION_14_15
++#define DCP4_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
++#define DCP4_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
++#define DCP4_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
++#define DCP4_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP4_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
++#define DCP4_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP4_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP4_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
++//DCP4_ALPHA_CONTROL
++#define DCP4_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT 0x0
++#define DCP4_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT 0x1
++#define DCP4_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK 0x00000001L
++#define DCP4_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK 0x00000002L
++//DCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS
++#define DCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT 0x8
++#define DCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
++//DCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH
++#define DCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define DCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
++//DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS
++#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT 0x0
++#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT 0x18
++#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT 0x19
++#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT 0x1a
++#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT 0x1c
++#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT 0x1d
++#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT 0x1e
++#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK 0x000FFFFFL
++#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK 0x01000000L
++#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK 0x02000000L
++#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK 0x04000000L
++#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK 0x10000000L
++#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK 0x20000000L
++#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK 0x40000000L
++//DCP4_GRPH_XDMA_FLIP_TIMEOUT
++#define DCP4_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS__SHIFT 0x0
++#define DCP4_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK__SHIFT 0x1
++#define DCP4_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK__SHIFT 0x2
++#define DCP4_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS_MASK 0x00000001L
++#define DCP4_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK_MASK 0x00000002L
++#define DCP4_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK_MASK 0x00000004L
++//DCP4_GRPH_XDMA_FLIP_AVG_DELAY
++#define DCP4_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY__SHIFT 0x0
++#define DCP4_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD__SHIFT 0x10
++#define DCP4_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY_MASK 0x0000FFFFL
++#define DCP4_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD_MASK 0x00FF0000L
++//DCP4_GRPH_SURFACE_COUNTER_CONTROL
++#define DCP4_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN__SHIFT 0x0
++#define DCP4_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT__SHIFT 0x1
++#define DCP4_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED__SHIFT 0x9
++#define DCP4_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN_MASK 0x00000001L
++#define DCP4_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT_MASK 0x0000001EL
++#define DCP4_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_MASK 0x00000200L
++//DCP4_GRPH_SURFACE_COUNTER_OUTPUT
++#define DCP4_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN__SHIFT 0x0
++#define DCP4_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX__SHIFT 0x10
++#define DCP4_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN_MASK 0x0000FFFFL
++#define DCP4_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX_MASK 0xFFFF0000L
++
++
++// addressBlock: dce_dc_lb4_dispdec
++//LB4_LB_DATA_FORMAT
++#define LB4_LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0
++#define LB4_LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2
++#define LB4_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3
++#define LB4_LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4
++#define LB4_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5
++#define LB4_LB_DATA_FORMAT__PREFILL_EN__SHIFT 0x8
++#define LB4_LB_DATA_FORMAT__PREFETCH__SHIFT 0xc
++#define LB4_LB_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18
++#define LB4_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f
++#define LB4_LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x00000003L
++#define LB4_LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x00000004L
++#define LB4_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000008L
++#define LB4_LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x00000010L
++#define LB4_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x00000020L
++#define LB4_LB_DATA_FORMAT__PREFILL_EN_MASK 0x00000100L
++#define LB4_LB_DATA_FORMAT__PREFETCH_MASK 0x00001000L
++#define LB4_LB_DATA_FORMAT__REQUEST_MODE_MASK 0x01000000L
++#define LB4_LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000L
++//LB4_LB_MEMORY_CTRL
++#define LB4_LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0
++#define LB4_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
++#define LB4_LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14
++#define LB4_LB_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0x00001FFFL
++#define LB4_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x000F0000L
++#define LB4_LB_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x00300000L
++//LB4_LB_MEMORY_SIZE_STATUS
++#define LB4_LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0
++#define LB4_LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0x00001FFFL
++//LB4_LB_DESKTOP_HEIGHT
++#define LB4_LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0
++#define LB4_LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x00007FFFL
++//LB4_LB_VLINE_START_END
++#define LB4_LB_VLINE_START_END__VLINE_START__SHIFT 0x0
++#define LB4_LB_VLINE_START_END__VLINE_END__SHIFT 0x10
++#define LB4_LB_VLINE_START_END__VLINE_INV__SHIFT 0x1f
++#define LB4_LB_VLINE_START_END__VLINE_START_MASK 0x00003FFFL
++#define LB4_LB_VLINE_START_END__VLINE_END_MASK 0x7FFF0000L
++#define LB4_LB_VLINE_START_END__VLINE_INV_MASK 0x80000000L
++//LB4_LB_VLINE2_START_END
++#define LB4_LB_VLINE2_START_END__VLINE2_START__SHIFT 0x0
++#define LB4_LB_VLINE2_START_END__VLINE2_END__SHIFT 0x10
++#define LB4_LB_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f
++#define LB4_LB_VLINE2_START_END__VLINE2_START_MASK 0x00003FFFL
++#define LB4_LB_VLINE2_START_END__VLINE2_END_MASK 0x7FFF0000L
++#define LB4_LB_VLINE2_START_END__VLINE2_INV_MASK 0x80000000L
++//LB4_LB_V_COUNTER
++#define LB4_LB_V_COUNTER__V_COUNTER__SHIFT 0x0
++#define LB4_LB_V_COUNTER__V_COUNTER_MASK 0x00007FFFL
++//LB4_LB_SNAPSHOT_V_COUNTER
++#define LB4_LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0
++#define LB4_LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x00007FFFL
++//LB4_LB_INTERRUPT_MASK
++#define LB4_LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0
++#define LB4_LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4
++#define LB4_LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8
++#define LB4_LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x00000001L
++#define LB4_LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x00000010L
++#define LB4_LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x00000100L
++//LB4_LB_VLINE_STATUS
++#define LB4_LB_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0
++#define LB4_LB_VLINE_STATUS__VLINE_ACK__SHIFT 0x4
++#define LB4_LB_VLINE_STATUS__VLINE_STAT__SHIFT 0xc
++#define LB4_LB_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10
++#define LB4_LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11
++#define LB4_LB_VLINE_STATUS__VLINE_OCCURRED_MASK 0x00000001L
++#define LB4_LB_VLINE_STATUS__VLINE_ACK_MASK 0x00000010L
++#define LB4_LB_VLINE_STATUS__VLINE_STAT_MASK 0x00001000L
++#define LB4_LB_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x00010000L
++#define LB4_LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x00020000L
++//LB4_LB_VLINE2_STATUS
++#define LB4_LB_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0
++#define LB4_LB_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4
++#define LB4_LB_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc
++#define LB4_LB_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10
++#define LB4_LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11
++#define LB4_LB_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x00000001L
++#define LB4_LB_VLINE2_STATUS__VLINE2_ACK_MASK 0x00000010L
++#define LB4_LB_VLINE2_STATUS__VLINE2_STAT_MASK 0x00001000L
++#define LB4_LB_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x00010000L
++#define LB4_LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x00020000L
++//LB4_LB_VBLANK_STATUS
++#define LB4_LB_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0
++#define LB4_LB_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4
++#define LB4_LB_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc
++#define LB4_LB_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10
++#define LB4_LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11
++#define LB4_LB_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x00000001L
++#define LB4_LB_VBLANK_STATUS__VBLANK_ACK_MASK 0x00000010L
++#define LB4_LB_VBLANK_STATUS__VBLANK_STAT_MASK 0x00001000L
++#define LB4_LB_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x00010000L
++#define LB4_LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x00020000L
++//LB4_LB_SYNC_RESET_SEL
++#define LB4_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0
++#define LB4_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4
++#define LB4_LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8
++#define LB4_LB_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16
++#define LB4_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x00000003L
++#define LB4_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x00000010L
++#define LB4_LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0x0000FF00L
++#define LB4_LB_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0x00C00000L
++//LB4_LB_BLACK_KEYER_R_CR
++#define LB4_LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4
++#define LB4_LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0x0000FFF0L
++//LB4_LB_BLACK_KEYER_G_Y
++#define LB4_LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4
++#define LB4_LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0x0000FFF0L
++//LB4_LB_BLACK_KEYER_B_CB
++#define LB4_LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4
++#define LB4_LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0x0000FFF0L
++//LB4_LB_KEYER_COLOR_CTRL
++#define LB4_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0
++#define LB4_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8
++#define LB4_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x00000001L
++#define LB4_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x00000100L
++//LB4_LB_KEYER_COLOR_R_CR
++#define LB4_LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4
++#define LB4_LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0x0000FFF0L
++//LB4_LB_KEYER_COLOR_G_Y
++#define LB4_LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4
++#define LB4_LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0x0000FFF0L
++//LB4_LB_KEYER_COLOR_B_CB
++#define LB4_LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4
++#define LB4_LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0x0000FFF0L
++//LB4_LB_KEYER_COLOR_REP_R_CR
++#define LB4_LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4
++#define LB4_LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0x0000FFF0L
++//LB4_LB_KEYER_COLOR_REP_G_Y
++#define LB4_LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4
++#define LB4_LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0x0000FFF0L
++//LB4_LB_KEYER_COLOR_REP_B_CB
++#define LB4_LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4
++#define LB4_LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0x0000FFF0L
++//LB4_LB_BUFFER_LEVEL_STATUS
++#define LB4_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0
++#define LB4_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa
++#define LB4_LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10
++#define LB4_LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c
++#define LB4_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x0000003FL
++#define LB4_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0x0000FC00L
++#define LB4_LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0x0FFF0000L
++#define LB4_LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xF0000000L
++//LB4_LB_BUFFER_URGENCY_CTRL
++#define LB4_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0
++#define LB4_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10
++#define LB4_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0x00000FFFL
++#define LB4_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0x0FFF0000L
++//LB4_LB_BUFFER_URGENCY_STATUS
++#define LB4_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0
++#define LB4_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10
++#define LB4_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0x00000FFFL
++#define LB4_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x00010000L
++//LB4_LB_BUFFER_STATUS
++#define LB4_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0
++#define LB4_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4
++#define LB4_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8
++#define LB4_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc
++#define LB4_LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10
++#define LB4_LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14
++#define LB4_LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18
++#define LB4_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0x0000000FL
++#define LB4_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x00000010L
++#define LB4_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x00000100L
++#define LB4_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x00001000L
++#define LB4_LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x00010000L
++#define LB4_LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x00100000L
++#define LB4_LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x01000000L
++//LB4_LB_NO_OUTSTANDING_REQ_STATUS
++#define LB4_LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0
++#define LB4_LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x00000001L
++//LB4_MVP_AFR_FLIP_MODE
++#define LB4_MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT 0x0
++#define LB4_MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK 0x00000003L
++//LB4_MVP_AFR_FLIP_FIFO_CNTL
++#define LB4_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT 0x0
++#define LB4_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT 0x4
++#define LB4_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT 0x8
++#define LB4_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT 0xc
++#define LB4_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK 0x0000000FL
++#define LB4_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK 0x00000010L
++#define LB4_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK 0x00000100L
++#define LB4_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK 0x00001000L
++//LB4_MVP_FLIP_LINE_NUM_INSERT
++#define LB4_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT 0x0
++#define LB4_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT 0x8
++#define LB4_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT 0x18
++#define LB4_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT 0x1e
++#define LB4_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK 0x00000003L
++#define LB4_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK 0x007FFF00L
++#define LB4_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK 0x3F000000L
++#define LB4_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK 0x40000000L
++//LB4_DC_MVP_LB_CONTROL
++#define LB4_DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT 0x0
++#define LB4_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT 0x8
++#define LB4_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT 0xc
++#define LB4_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT 0x10
++#define LB4_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT 0x14
++#define LB4_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT 0x1c
++#define LB4_DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT 0x1f
++#define LB4_DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK 0x00000003L
++#define LB4_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK 0x00000100L
++#define LB4_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK 0x00001000L
++#define LB4_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK 0x00010000L
++#define LB4_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK 0x00100000L
++#define LB4_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK 0x10000000L
++#define LB4_DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK 0x80000000L
++
++
++// addressBlock: dce_dc_dcfe4_dispdec
++//DCFE4_DCFE_CLOCK_CONTROL
++#define DCFE4_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x4
++#define DCFE4_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x8
++#define DCFE4_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0xc
++#define DCFE4_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE__SHIFT 0xf
++#define DCFE4_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE__SHIFT 0x11
++#define DCFE4_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL__SHIFT 0x18
++#define DCFE4_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE__SHIFT 0x1f
++#define DCFE4_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x00000010L
++#define DCFE4_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE_MASK 0x00000100L
++#define DCFE4_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE_MASK 0x00001000L
++#define DCFE4_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE_MASK 0x00008000L
++#define DCFE4_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE_MASK 0x00020000L
++#define DCFE4_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL_MASK 0x1F000000L
++#define DCFE4_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE_MASK 0x80000000L
++//DCFE4_DCFE_SOFT_RESET
++#define DCFE4_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET__SHIFT 0x0
++#define DCFE4_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET__SHIFT 0x1
++#define DCFE4_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET__SHIFT 0x2
++#define DCFE4_DCFE_SOFT_RESET__SCL_SOFT_RESET__SHIFT 0x3
++#define DCFE4_DCFE_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4
++#define DCFE4_DCFE_SOFT_RESET__PSCL_SOFT_RESET__SHIFT 0x5
++#define DCFE4_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET_MASK 0x00000001L
++#define DCFE4_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET_MASK 0x00000002L
++#define DCFE4_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET_MASK 0x00000004L
++#define DCFE4_DCFE_SOFT_RESET__SCL_SOFT_RESET_MASK 0x00000008L
++#define DCFE4_DCFE_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x00000010L
++#define DCFE4_DCFE_SOFT_RESET__PSCL_SOFT_RESET_MASK 0x00000020L
++//DCFE4_DCFE_MEM_PWR_CTRL
++#define DCFE4_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE__SHIFT 0x0
++#define DCFE4_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS__SHIFT 0x2
++#define DCFE4_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE__SHIFT 0x3
++#define DCFE4_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS__SHIFT 0x5
++#define DCFE4_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE__SHIFT 0x6
++#define DCFE4_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS__SHIFT 0x8
++#define DCFE4_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE__SHIFT 0x9
++#define DCFE4_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS__SHIFT 0xb
++#define DCFE4_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE__SHIFT 0xc
++#define DCFE4_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS__SHIFT 0xe
++#define DCFE4_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE__SHIFT 0xf
++#define DCFE4_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS__SHIFT 0x11
++#define DCFE4_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE__SHIFT 0x12
++#define DCFE4_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS__SHIFT 0x14
++#define DCFE4_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE__SHIFT 0x15
++#define DCFE4_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS__SHIFT 0x17
++#define DCFE4_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE__SHIFT 0x18
++#define DCFE4_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS__SHIFT 0x1a
++#define DCFE4_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE__SHIFT 0x1b
++#define DCFE4_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS__SHIFT 0x1d
++#define DCFE4_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE_MASK 0x00000003L
++#define DCFE4_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS_MASK 0x00000004L
++#define DCFE4_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE_MASK 0x00000018L
++#define DCFE4_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS_MASK 0x00000020L
++#define DCFE4_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE_MASK 0x000000C0L
++#define DCFE4_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS_MASK 0x00000100L
++#define DCFE4_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE_MASK 0x00000600L
++#define DCFE4_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS_MASK 0x00000800L
++#define DCFE4_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE_MASK 0x00003000L
++#define DCFE4_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS_MASK 0x00004000L
++#define DCFE4_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE_MASK 0x00018000L
++#define DCFE4_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK 0x00020000L
++#define DCFE4_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE_MASK 0x000C0000L
++#define DCFE4_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS_MASK 0x00100000L
++#define DCFE4_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE_MASK 0x00600000L
++#define DCFE4_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS_MASK 0x00800000L
++#define DCFE4_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE_MASK 0x03000000L
++#define DCFE4_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS_MASK 0x04000000L
++#define DCFE4_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE_MASK 0x18000000L
++#define DCFE4_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS_MASK 0x20000000L
++//DCFE4_DCFE_MEM_PWR_CTRL2
++#define DCFE4_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL__SHIFT 0x0
++#define DCFE4_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2
++#define DCFE4_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4
++#define DCFE4_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL__SHIFT 0x6
++#define DCFE4_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL__SHIFT 0x8
++#define DCFE4_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL__SHIFT 0xa
++#define DCFE4_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL__SHIFT 0xc
++#define DCFE4_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL__SHIFT 0xe
++#define DCFE4_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE__SHIFT 0x10
++#define DCFE4_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS__SHIFT 0x12
++#define DCFE4_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE__SHIFT 0x15
++#define DCFE4_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS__SHIFT 0x17
++#define DCFE4_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL_MASK 0x00000003L
++#define DCFE4_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL_MASK 0x0000000CL
++#define DCFE4_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL_MASK 0x00000030L
++#define DCFE4_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL_MASK 0x000000C0L
++#define DCFE4_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL_MASK 0x00000300L
++#define DCFE4_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL_MASK 0x00000C00L
++#define DCFE4_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL_MASK 0x00003000L
++#define DCFE4_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL_MASK 0x0000C000L
++#define DCFE4_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE_MASK 0x00030000L
++#define DCFE4_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS_MASK 0x00040000L
++#define DCFE4_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE_MASK 0x00600000L
++#define DCFE4_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS_MASK 0x00800000L
++//DCFE4_DCFE_MEM_PWR_STATUS
++#define DCFE4_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE__SHIFT 0x0
++#define DCFE4_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE__SHIFT 0x2
++#define DCFE4_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE__SHIFT 0x4
++#define DCFE4_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x6
++#define DCFE4_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE__SHIFT 0x8
++#define DCFE4_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE__SHIFT 0xa
++#define DCFE4_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE__SHIFT 0xc
++#define DCFE4_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE__SHIFT 0xe
++#define DCFE4_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT 0x10
++#define DCFE4_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE__SHIFT 0x12
++#define DCFE4_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE__SHIFT 0x14
++#define DCFE4_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE__SHIFT 0x16
++#define DCFE4_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK 0x00000003L
++#define DCFE4_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE_MASK 0x0000000CL
++#define DCFE4_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE_MASK 0x00000030L
++#define DCFE4_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE_MASK 0x000000C0L
++#define DCFE4_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE_MASK 0x00000300L
++#define DCFE4_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE_MASK 0x00000C00L
++#define DCFE4_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE_MASK 0x00003000L
++#define DCFE4_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE_MASK 0x0000C000L
++#define DCFE4_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE_MASK 0x00030000L
++#define DCFE4_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK 0x000C0000L
++#define DCFE4_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE_MASK 0x00300000L
++#define DCFE4_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE_MASK 0x00C00000L
++//DCFE4_DCFE_MISC
++#define DCFE4_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN__SHIFT 0x0
++#define DCFE4_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN_MASK 0x00000001L
++//DCFE4_DCFE_FLUSH
++#define DCFE4_DCFE_FLUSH__FLUSH_OCCURED__SHIFT 0x0
++#define DCFE4_DCFE_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT 0x1
++#define DCFE4_DCFE_FLUSH__FLUSH_DEEP__SHIFT 0x2
++#define DCFE4_DCFE_FLUSH__CLEAR_FLUSH_DEEP__SHIFT 0x3
++#define DCFE4_DCFE_FLUSH__ALL_MC_REQ_RET__SHIFT 0x4
++#define DCFE4_DCFE_FLUSH__FLUSH_OCCURED_MASK 0x00000001L
++#define DCFE4_DCFE_FLUSH__CLEAR_FLUSH_OCCURED_MASK 0x00000002L
++#define DCFE4_DCFE_FLUSH__FLUSH_DEEP_MASK 0x00000004L
++#define DCFE4_DCFE_FLUSH__CLEAR_FLUSH_DEEP_MASK 0x00000008L
++#define DCFE4_DCFE_FLUSH__ALL_MC_REQ_RET_MASK 0x00000010L
++
++
++// addressBlock: dce_dc_dc_perfmon7_dispdec
++//DC_PERFMON7_PERFCOUNTER_CNTL
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
++//DC_PERFMON7_PERFCOUNTER_CNTL2
++#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
++#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
++#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
++#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
++#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
++#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
++#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
++#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
++//DC_PERFMON7_PERFCOUNTER_STATE
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
++//DC_PERFMON7_PERFMON_CNTL
++#define DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
++#define DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
++#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
++#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
++#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
++#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
++#define DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
++#define DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
++#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
++#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
++#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
++#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
++//DC_PERFMON7_PERFMON_CNTL2
++#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
++#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
++#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
++#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
++#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
++#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
++#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
++#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
++//DC_PERFMON7_PERFMON_CVALUE_INT_MISC
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
++//DC_PERFMON7_PERFMON_CVALUE_LOW
++#define DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
++#define DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
++//DC_PERFMON7_PERFMON_HI
++#define DC_PERFMON7_PERFMON_HI__PERFMON_HI__SHIFT 0x0
++#define DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
++#define DC_PERFMON7_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
++#define DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
++//DC_PERFMON7_PERFMON_LOW
++#define DC_PERFMON7_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
++#define DC_PERFMON7_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dmif_pg4_dispdec
++//DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1
++#define DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
++#define DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
++#define DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0x0000FFFFL
++#define DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xFFFF0000L
++//DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2
++#define DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
++#define DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
++#define DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0x0000FFFFL
++#define DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xFFFF0000L
++//DMIF_PG4_DPG_WATERMARK_MASK_CONTROL
++#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
++#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x4
++#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
++#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK__SHIFT 0xc
++#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0xf
++#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x12
++#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL__SHIFT 0x13
++#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL__SHIFT 0x14
++#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000007L
++#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000070L
++#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x00000700L
++#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK_MASK 0x00007000L
++#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00038000L
++#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x00040000L
++#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL_MASK 0x00080000L
++#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL_MASK 0x3FF00000L
++//DMIF_PG4_DPG_PIPE_URGENCY_CONTROL
++#define DMIF_PG4_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
++#define DMIF_PG4_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
++#define DMIF_PG4_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0x0000FFFFL
++#define DMIF_PG4_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xFFFF0000L
++//DMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL
++#define DMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK__SHIFT 0x0
++#define DMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK__SHIFT 0x10
++#define DMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK_MASK 0x0000FFFFL
++#define DMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK_MASK 0xFFFF0000L
++//DMIF_PG4_DPG_PIPE_STUTTER_CONTROL
++#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
++#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
++#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
++#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
++#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
++#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
++#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
++#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH__SHIFT 0x10
++#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x14
++#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x15
++#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x16
++#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x17
++#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0x1a
++#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0x1b
++#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L
++#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L
++#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x00000020L
++#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x00000040L
++#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x00000080L
++#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x00000400L
++#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x00000800L
++#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH_MASK 0x00010000L
++#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x00100000L
++#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x00200000L
++#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x00400000L
++#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x00800000L
++#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x04000000L
++#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x08000000L
++//DMIF_PG4_DPG_PIPE_STUTTER_CONTROL2
++#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x0
++#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK__SHIFT 0x10
++#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0x0000FFFFL
++#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK 0xFFFF0000L
++//DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL
++#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE__SHIFT 0x0
++#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE__SHIFT 0x1
++#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
++#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
++#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
++#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
++#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK__SHIFT 0xf
++#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE_MASK 0x00000001L
++#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE_MASK 0x00000002L
++#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L
++#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x00000100L
++#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON_MASK 0x00000200L
++#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT_MASK 0x00000400L
++#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK_MASK 0xFFFF8000L
++//DMIF_PG4_DPG_REPEATER_PROGRAM
++#define DMIF_PG4_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
++#define DMIF_PG4_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
++#define DMIF_PG4_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x00000007L
++#define DMIF_PG4_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x00000070L
++//DMIF_PG4_DPG_CHK_PRE_PROC_CNTL
++#define DMIF_PG4_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0
++#define DMIF_PG4_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x00000001L
++//DMIF_PG4_DPG_DVMM_STATUS
++#define DMIF_PG4_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED__SHIFT 0x0
++#define DMIF_PG4_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED__SHIFT 0x1
++#define DMIF_PG4_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR__SHIFT 0x4
++#define DMIF_PG4_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR__SHIFT 0x5
++#define DMIF_PG4_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_MASK 0x00000001L
++#define DMIF_PG4_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_MASK 0x00000002L
++#define DMIF_PG4_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR_MASK 0x00000010L
++#define DMIF_PG4_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR_MASK 0x00000020L
++
++
++// addressBlock: dce_dc_scl4_dispdec
++//SCL4_SCL_COEF_RAM_SELECT
++#define SCL4_SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0
++#define SCL4_SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8
++#define SCL4_SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10
++#define SCL4_SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x0000000FL
++#define SCL4_SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x00000F00L
++#define SCL4_SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x00070000L
++//SCL4_SCL_COEF_RAM_TAP_DATA
++#define SCL4_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0
++#define SCL4_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
++#define SCL4_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10
++#define SCL4_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
++#define SCL4_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL
++#define SCL4_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L
++#define SCL4_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L
++#define SCL4_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L
++//SCL4_SCL_MODE
++#define SCL4_SCL_MODE__SCL_MODE__SHIFT 0x0
++#define SCL4_SCL_MODE__SCL_PSCL_EN__SHIFT 0x4
++#define SCL4_SCL_MODE__SCL_MODE_MASK 0x00000003L
++#define SCL4_SCL_MODE__SCL_PSCL_EN_MASK 0x00000010L
++//SCL4_SCL_TAP_CONTROL
++#define SCL4_SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0
++#define SCL4_SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x8
++#define SCL4_SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x00000007L
++#define SCL4_SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0x00000F00L
++//SCL4_SCL_CONTROL
++#define SCL4_SCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
++#define SCL4_SCL_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4
++#define SCL4_SCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L
++#define SCL4_SCL_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x00000010L
++//SCL4_SCL_BYPASS_CONTROL
++#define SCL4_SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT 0x0
++#define SCL4_SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x00000003L
++//SCL4_SCL_MANUAL_REPLICATE_CONTROL
++#define SCL4_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
++#define SCL4_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
++#define SCL4_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL
++#define SCL4_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L
++//SCL4_SCL_AUTOMATIC_MODE_CONTROL
++#define SCL4_SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0
++#define SCL4_SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10
++#define SCL4_SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x00000001L
++#define SCL4_SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x00010000L
++//SCL4_SCL_HORZ_FILTER_CONTROL
++#define SCL4_SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT 0x0
++#define SCL4_SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
++#define SCL4_SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK 0x00000001L
++#define SCL4_SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
++//SCL4_SCL_HORZ_FILTER_SCALE_RATIO
++#define SCL4_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
++#define SCL4_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL
++//SCL4_SCL_HORZ_FILTER_INIT
++#define SCL4_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
++#define SCL4_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
++#define SCL4_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL
++#define SCL4_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L
++//SCL4_SCL_VERT_FILTER_CONTROL
++#define SCL4_SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT 0x0
++#define SCL4_SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
++#define SCL4_SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK 0x00000001L
++#define SCL4_SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
++//SCL4_SCL_VERT_FILTER_SCALE_RATIO
++#define SCL4_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
++#define SCL4_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL
++//SCL4_SCL_VERT_FILTER_INIT
++#define SCL4_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
++#define SCL4_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
++#define SCL4_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL
++#define SCL4_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x07000000L
++//SCL4_SCL_VERT_FILTER_INIT_BOT
++#define SCL4_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
++#define SCL4_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
++#define SCL4_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL
++#define SCL4_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x07000000L
++//SCL4_SCL_ROUND_OFFSET
++#define SCL4_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0
++#define SCL4_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10
++#define SCL4_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0x0000FFFFL
++#define SCL4_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xFFFF0000L
++//SCL4_SCL_UPDATE
++#define SCL4_SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
++#define SCL4_SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8
++#define SCL4_SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10
++#define SCL4_SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18
++#define SCL4_SCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L
++#define SCL4_SCL_UPDATE__SCL_UPDATE_TAKEN_MASK 0x00000100L
++#define SCL4_SCL_UPDATE__SCL_UPDATE_LOCK_MASK 0x00010000L
++#define SCL4_SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x01000000L
++//SCL4_SCL_F_SHARP_CONTROL
++#define SCL4_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT 0x0
++#define SCL4_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT 0x4
++#define SCL4_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT 0x8
++#define SCL4_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT 0xc
++#define SCL4_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK 0x00000007L
++#define SCL4_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK 0x00000010L
++#define SCL4_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK 0x00000700L
++#define SCL4_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK 0x00001000L
++//SCL4_SCL_ALU_CONTROL
++#define SCL4_SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0
++#define SCL4_SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x00000001L
++//SCL4_SCL_COEF_RAM_CONFLICT_STATUS
++#define SCL4_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT 0x0
++#define SCL4_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT 0x8
++#define SCL4_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT 0xc
++#define SCL4_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10
++#define SCL4_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK 0x00000001L
++#define SCL4_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK 0x00000100L
++#define SCL4_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK 0x00001000L
++#define SCL4_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK 0x00010000L
++//SCL4_VIEWPORT_START_SECONDARY
++#define SCL4_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0
++#define SCL4_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10
++#define SCL4_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x00003FFFL
++#define SCL4_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3FFF0000L
++//SCL4_VIEWPORT_START
++#define SCL4_VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0
++#define SCL4_VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10
++#define SCL4_VIEWPORT_START__VIEWPORT_Y_START_MASK 0x00003FFFL
++#define SCL4_VIEWPORT_START__VIEWPORT_X_START_MASK 0x3FFF0000L
++//SCL4_VIEWPORT_SIZE
++#define SCL4_VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0
++#define SCL4_VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10
++#define SCL4_VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x00003FFFL
++#define SCL4_VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x3FFF0000L
++//SCL4_EXT_OVERSCAN_LEFT_RIGHT
++#define SCL4_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
++#define SCL4_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
++#define SCL4_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL
++#define SCL4_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L
++//SCL4_EXT_OVERSCAN_TOP_BOTTOM
++#define SCL4_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
++#define SCL4_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
++#define SCL4_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL
++#define SCL4_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L
++//SCL4_SCL_MODE_CHANGE_DET1
++#define SCL4_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0
++#define SCL4_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4
++#define SCL4_SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7
++#define SCL4_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x00000001L
++#define SCL4_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x00000010L
++#define SCL4_SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0x0FFFFF80L
++//SCL4_SCL_MODE_CHANGE_DET2
++#define SCL4_SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0
++#define SCL4_SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x001FFFFFL
++//SCL4_SCL_MODE_CHANGE_DET3
++#define SCL4_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0
++#define SCL4_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10
++#define SCL4_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x00003FFFL
++#define SCL4_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3FFF0000L
++//SCL4_SCL_MODE_CHANGE_MASK
++#define SCL4_SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0
++#define SCL4_SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x00000001L
++
++
++// addressBlock: dce_dc_blnd4_dispdec
++//BLND4_BLND_CONTROL
++#define BLND4_BLND_CONTROL__BLND_GLOBAL_GAIN__SHIFT 0x0
++#define BLND4_BLND_CONTROL__BLND_MODE__SHIFT 0x8
++#define BLND4_BLND_CONTROL__BLND_STEREO_TYPE__SHIFT 0xa
++#define BLND4_BLND_CONTROL__BLND_STEREO_POLARITY__SHIFT 0xc
++#define BLND4_BLND_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT 0xd
++#define BLND4_BLND_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10
++#define BLND4_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x12
++#define BLND4_BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14
++#define BLND4_BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18
++#define BLND4_BLND_CONTROL__BLND_GLOBAL_GAIN_MASK 0x000000FFL
++#define BLND4_BLND_CONTROL__BLND_MODE_MASK 0x00000300L
++#define BLND4_BLND_CONTROL__BLND_STEREO_TYPE_MASK 0x00000C00L
++#define BLND4_BLND_CONTROL__BLND_STEREO_POLARITY_MASK 0x00001000L
++#define BLND4_BLND_CONTROL__BLND_FEEDTHROUGH_EN_MASK 0x00002000L
++#define BLND4_BLND_CONTROL__BLND_ALPHA_MODE_MASK 0x00030000L
++#define BLND4_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00040000L
++#define BLND4_BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x00100000L
++#define BLND4_BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xFF000000L
++//BLND4_BLND_SM_CONTROL2
++#define BLND4_BLND_SM_CONTROL2__SM_MODE__SHIFT 0x0
++#define BLND4_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4
++#define BLND4_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5
++#define BLND4_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
++#define BLND4_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
++#define BLND4_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18
++#define BLND4_BLND_SM_CONTROL2__SM_MODE_MASK 0x00000007L
++#define BLND4_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x00000010L
++#define BLND4_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x00000020L
++#define BLND4_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L
++#define BLND4_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L
++#define BLND4_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x01000000L
++//BLND4_BLND_CONTROL2
++#define BLND4_BLND_CONTROL2__PTI_ENABLE__SHIFT 0x0
++#define BLND4_BLND_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT 0x4
++#define BLND4_BLND_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT 0x6
++#define BLND4_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT 0x7
++#define BLND4_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT 0x8
++#define BLND4_BLND_CONTROL2__PTI_ENABLE_MASK 0x00000001L
++#define BLND4_BLND_CONTROL2__PTI_NEW_PIXEL_GAP_MASK 0x00000030L
++#define BLND4_BLND_CONTROL2__BLND_NEW_PIXEL_MODE_MASK 0x00000040L
++#define BLND4_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK 0x00000080L
++#define BLND4_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK 0x00000100L
++//BLND4_BLND_UPDATE
++#define BLND4_BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0
++#define BLND4_BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8
++#define BLND4_BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10
++#define BLND4_BLND_UPDATE__BLND_UPDATE_PENDING_MASK 0x00000001L
++#define BLND4_BLND_UPDATE__BLND_UPDATE_TAKEN_MASK 0x00000100L
++#define BLND4_BLND_UPDATE__BLND_UPDATE_LOCK_MASK 0x00010000L
++//BLND4_BLND_UNDERFLOW_INTERRUPT
++#define BLND4_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0
++#define BLND4_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8
++#define BLND4_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc
++#define BLND4_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10
++#define BLND4_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x00000001L
++#define BLND4_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x00000100L
++#define BLND4_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x00001000L
++#define BLND4_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x00030000L
++//BLND4_BLND_V_UPDATE_LOCK
++#define BLND4_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0
++#define BLND4_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1
++#define BLND4_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10
++#define BLND4_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c
++#define BLND4_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT 0x1d
++#define BLND4_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT 0x1f
++#define BLND4_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x00000001L
++#define BLND4_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x00000002L
++#define BLND4_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x00010000L
++#define BLND4_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000L
++#define BLND4_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK 0x20000000L
++#define BLND4_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK 0x80000000L
++//BLND4_BLND_REG_UPDATE_STATUS
++#define BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT 0x0
++#define BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT 0x1
++#define BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2
++#define BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3
++#define BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT 0x6
++#define BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT 0x7
++#define BLND4_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT 0x8
++#define BLND4_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT 0x9
++#define BLND4_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT 0xa
++#define BLND4_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT 0xb
++#define BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK 0x00000001L
++#define BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK 0x00000002L
++#define BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK 0x00000004L
++#define BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK 0x00000008L
++#define BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK 0x00000040L
++#define BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK 0x00000080L
++#define BLND4_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK 0x00000100L
++#define BLND4_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK 0x00000200L
++#define BLND4_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK 0x00000400L
++#define BLND4_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK 0x00000800L
++
++
++// addressBlock: dce_dc_crtc4_dispdec
++//CRTC4_CRTC_H_BLANK_EARLY_NUM
++#define CRTC4_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0
++#define CRTC4_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10
++#define CRTC4_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x000003FFL
++#define CRTC4_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x00010000L
++//CRTC4_CRTC_H_TOTAL
++#define CRTC4_CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0
++#define CRTC4_CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x00003FFFL
++//CRTC4_CRTC_H_BLANK_START_END
++#define CRTC4_CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0
++#define CRTC4_CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10
++#define CRTC4_CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x00003FFFL
++#define CRTC4_CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3FFF0000L
++//CRTC4_CRTC_H_SYNC_A
++#define CRTC4_CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0
++#define CRTC4_CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10
++#define CRTC4_CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x00003FFFL
++#define CRTC4_CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3FFF0000L
++//CRTC4_CRTC_H_SYNC_A_CNTL
++#define CRTC4_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0
++#define CRTC4_CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10
++#define CRTC4_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11
++#define CRTC4_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x00000001L
++#define CRTC4_CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x00010000L
++#define CRTC4_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x00020000L
++//CRTC4_CRTC_H_SYNC_B
++#define CRTC4_CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0
++#define CRTC4_CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10
++#define CRTC4_CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x00003FFFL
++#define CRTC4_CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x3FFF0000L
++//CRTC4_CRTC_H_SYNC_B_CNTL
++#define CRTC4_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0
++#define CRTC4_CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10
++#define CRTC4_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11
++#define CRTC4_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x00000001L
++#define CRTC4_CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x00010000L
++#define CRTC4_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x00020000L
++//CRTC4_CRTC_VBI_END
++#define CRTC4_CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x0
++#define CRTC4_CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x10
++#define CRTC4_CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x00003FFFL
++#define CRTC4_CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x3FFF0000L
++//CRTC4_CRTC_V_TOTAL
++#define CRTC4_CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0
++#define CRTC4_CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x00003FFFL
++//CRTC4_CRTC_V_TOTAL_MIN
++#define CRTC4_CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0
++#define CRTC4_CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x00003FFFL
++//CRTC4_CRTC_V_TOTAL_MAX
++#define CRTC4_CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0
++#define CRTC4_CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10
++#define CRTC4_CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x00003FFFL
++#define CRTC4_CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x00010000L
++//CRTC4_CRTC_V_TOTAL_CONTROL
++#define CRTC4_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0
++#define CRTC4_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4
++#define CRTC4_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8
++#define CRTC4_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc
++#define CRTC4_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf
++#define CRTC4_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10
++#define CRTC4_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x00000001L
++#define CRTC4_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x00000010L
++#define CRTC4_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x00000100L
++#define CRTC4_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x00001000L
++#define CRTC4_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00008000L
++#define CRTC4_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L
++//CRTC4_CRTC_V_TOTAL_INT_STATUS
++#define CRTC4_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0
++#define CRTC4_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4
++#define CRTC4_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8
++#define CRTC4_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc
++#define CRTC4_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L
++#define CRTC4_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L
++#define CRTC4_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L
++#define CRTC4_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L
++//CRTC4_CRTC_VSYNC_NOM_INT_STATUS
++#define CRTC4_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0
++#define CRTC4_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4
++#define CRTC4_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x00000001L
++#define CRTC4_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L
++//CRTC4_CRTC_V_BLANK_START_END
++#define CRTC4_CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0
++#define CRTC4_CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10
++#define CRTC4_CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x00003FFFL
++#define CRTC4_CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3FFF0000L
++//CRTC4_CRTC_V_SYNC_A
++#define CRTC4_CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0
++#define CRTC4_CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10
++#define CRTC4_CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x00003FFFL
++#define CRTC4_CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3FFF0000L
++//CRTC4_CRTC_V_SYNC_A_CNTL
++#define CRTC4_CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0
++#define CRTC4_CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x00000001L
++//CRTC4_CRTC_V_SYNC_B
++#define CRTC4_CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0
++#define CRTC4_CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10
++#define CRTC4_CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x00003FFFL
++#define CRTC4_CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x3FFF0000L
++//CRTC4_CRTC_V_SYNC_B_CNTL
++#define CRTC4_CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0
++#define CRTC4_CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x00000001L
++//CRTC4_CRTC_DTMTEST_CNTL
++#define CRTC4_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0
++#define CRTC4_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1
++#define CRTC4_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x00000001L
++#define CRTC4_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x0000001EL
++//CRTC4_CRTC_DTMTEST_STATUS_POSITION
++#define CRTC4_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0
++#define CRTC4_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10
++#define CRTC4_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x00003FFFL
++#define CRTC4_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x3FFF0000L
++//CRTC4_CRTC_TRIGA_CNTL
++#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0
++#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5
++#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8
++#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9
++#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa
++#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb
++#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
++#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
++#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14
++#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18
++#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f
++#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x0000001FL
++#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0x000000E0L
++#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000100L
++#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x00000200L
++#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x00000400L
++#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x00000800L
++#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
++#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
++#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L
++#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1F000000L
++#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000L
++//CRTC4_CRTC_TRIGA_MANUAL_TRIG
++#define CRTC4_CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0
++#define CRTC4_CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x00000001L
++//CRTC4_CRTC_TRIGB_CNTL
++#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0
++#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5
++#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8
++#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9
++#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa
++#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb
++#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
++#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
++#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14
++#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18
++#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f
++#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x0000001FL
++#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0x000000E0L
++#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000100L
++#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x00000200L
++#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x00000400L
++#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x00000800L
++#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
++#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
++#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L
++#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1F000000L
++#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000L
++//CRTC4_CRTC_TRIGB_MANUAL_TRIG
++#define CRTC4_CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0
++#define CRTC4_CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x00000001L
++//CRTC4_CRTC_FORCE_COUNT_NOW_CNTL
++#define CRTC4_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0
++#define CRTC4_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4
++#define CRTC4_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8
++#define CRTC4_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10
++#define CRTC4_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18
++#define CRTC4_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x00000003L
++#define CRTC4_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L
++#define CRTC4_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L
++#define CRTC4_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L
++#define CRTC4_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L
++//CRTC4_CRTC_FLOW_CONTROL
++#define CRTC4_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0
++#define CRTC4_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8
++#define CRTC4_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10
++#define CRTC4_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18
++#define CRTC4_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL
++#define CRTC4_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x00000100L
++#define CRTC4_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L
++#define CRTC4_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L
++//CRTC4_CRTC_STEREO_FORCE_NEXT_EYE
++#define CRTC4_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0
++#define CRTC4_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER__SHIFT 0x8
++#define CRTC4_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER__SHIFT 0x10
++#define CRTC4_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L
++#define CRTC4_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L
++#define CRTC4_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L
++//CRTC4_CRTC_AVSYNC_COUNTER
++#define CRTC4_CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER__SHIFT 0x0
++#define CRTC4_CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER_MASK 0xFFFFFFFFL
++//CRTC4_CRTC_CONTROL
++#define CRTC4_CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x0
++#define CRTC4_CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4
++#define CRTC4_CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8
++#define CRTC4_CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc
++#define CRTC4_CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd
++#define CRTC4_CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe
++#define CRTC4_CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10
++#define CRTC4_CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14
++#define CRTC4_CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d
++#define CRTC4_CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e
++#define CRTC4_CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f
++#define CRTC4_CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x00000001L
++#define CRTC4_CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x00000010L
++#define CRTC4_CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x00000300L
++#define CRTC4_CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x00001000L
++#define CRTC4_CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x00002000L
++#define CRTC4_CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x00004000L
++#define CRTC4_CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x00010000L
++#define CRTC4_CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x00700000L
++#define CRTC4_CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000L
++#define CRTC4_CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L
++#define CRTC4_CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L
++//CRTC4_CRTC_BLANK_CONTROL
++#define CRTC4_CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0
++#define CRTC4_CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8
++#define CRTC4_CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10
++#define CRTC4_CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x00000001L
++#define CRTC4_CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x00000100L
++#define CRTC4_CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x00010000L
++//CRTC4_CRTC_INTERLACE_CONTROL
++#define CRTC4_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0
++#define CRTC4_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10
++#define CRTC4_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x00000001L
++#define CRTC4_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L
++//CRTC4_CRTC_INTERLACE_STATUS
++#define CRTC4_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0
++#define CRTC4_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1
++#define CRTC4_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x00000001L
++#define CRTC4_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x00000002L
++//CRTC4_CRTC_FIELD_INDICATION_CONTROL
++#define CRTC4_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0
++#define CRTC4_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1
++#define CRTC4_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x00000001L
++#define CRTC4_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x00000002L
++//CRTC4_CRTC_PIXEL_DATA_READBACK0
++#define CRTC4_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0
++#define CRTC4_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10
++#define CRTC4_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0x00000FFFL
++#define CRTC4_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0x0FFF0000L
++//CRTC4_CRTC_PIXEL_DATA_READBACK1
++#define CRTC4_CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0
++#define CRTC4_CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0x00000FFFL
++//CRTC4_CRTC_STATUS
++#define CRTC4_CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x0
++#define CRTC4_CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1
++#define CRTC4_CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x2
++#define CRTC4_CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x3
++#define CRTC4_CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x4
++#define CRTC4_CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5
++#define CRTC4_CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x10
++#define CRTC4_CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11
++#define CRTC4_CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x12
++#define CRTC4_CRTC_STATUS__CRTC_V_BLANK_MASK 0x00000001L
++#define CRTC4_CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x00000002L
++#define CRTC4_CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x00000004L
++#define CRTC4_CRTC_STATUS__CRTC_V_UPDATE_MASK 0x00000008L
++#define CRTC4_CRTC_STATUS__CRTC_V_START_LINE_MASK 0x00000010L
++#define CRTC4_CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x00000020L
++#define CRTC4_CRTC_STATUS__CRTC_H_BLANK_MASK 0x00010000L
++#define CRTC4_CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x00020000L
++#define CRTC4_CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x00040000L
++//CRTC4_CRTC_STATUS_POSITION
++#define CRTC4_CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0
++#define CRTC4_CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10
++#define CRTC4_CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x00003FFFL
++#define CRTC4_CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x3FFF0000L
++//CRTC4_CRTC_NOM_VERT_POSITION
++#define CRTC4_CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0
++#define CRTC4_CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x00003FFFL
++//CRTC4_CRTC_STATUS_FRAME_COUNT
++#define CRTC4_CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0
++#define CRTC4_CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0x00FFFFFFL
++//CRTC4_CRTC_STATUS_VF_COUNT
++#define CRTC4_CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0
++#define CRTC4_CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x3FFFFFFFL
++//CRTC4_CRTC_STATUS_HV_COUNT
++#define CRTC4_CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0
++#define CRTC4_CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x3FFFFFFFL
++//CRTC4_CRTC_COUNT_CONTROL
++#define CRTC4_CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0
++#define CRTC4_CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1
++#define CRTC4_CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x00000001L
++#define CRTC4_CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x0000001EL
++//CRTC4_CRTC_COUNT_RESET
++#define CRTC4_CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0
++#define CRTC4_CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x00000001L
++//CRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE
++#define CRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0
++#define CRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L
++//CRTC4_CRTC_VERT_SYNC_CONTROL
++#define CRTC4_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0
++#define CRTC4_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8
++#define CRTC4_CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10
++#define CRTC4_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L
++#define CRTC4_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L
++#define CRTC4_CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L
++//CRTC4_CRTC_STEREO_STATUS
++#define CRTC4_CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0
++#define CRTC4_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8
++#define CRTC4_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10
++#define CRTC4_CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG__SHIFT 0x14
++#define CRTC4_CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18
++#define CRTC4_CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x00000001L
++#define CRTC4_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x00000100L
++#define CRTC4_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x00010000L
++#define CRTC4_CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG_MASK 0x00100000L
++#define CRTC4_CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L
++//CRTC4_CRTC_STEREO_CONTROL
++#define CRTC4_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0
++#define CRTC4_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf
++#define CRTC4_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10
++#define CRTC4_CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11
++#define CRTC4_CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12
++#define CRTC4_CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM__SHIFT 0x13
++#define CRTC4_CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14
++#define CRTC4_CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18
++#define CRTC4_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00003FFFL
++#define CRTC4_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L
++#define CRTC4_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x00010000L
++#define CRTC4_CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L
++#define CRTC4_CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L
++#define CRTC4_CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM_MASK 0x00080000L
++#define CRTC4_CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L
++#define CRTC4_CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x01000000L
++//CRTC4_CRTC_SNAPSHOT_STATUS
++#define CRTC4_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0
++#define CRTC4_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1
++#define CRTC4_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2
++#define CRTC4_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x00000001L
++#define CRTC4_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x00000002L
++#define CRTC4_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L
++//CRTC4_CRTC_SNAPSHOT_CONTROL
++#define CRTC4_CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0
++#define CRTC4_CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L
++//CRTC4_CRTC_SNAPSHOT_POSITION
++#define CRTC4_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0
++#define CRTC4_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10
++#define CRTC4_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x00003FFFL
++#define CRTC4_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x3FFF0000L
++//CRTC4_CRTC_SNAPSHOT_FRAME
++#define CRTC4_CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0
++#define CRTC4_CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL
++//CRTC4_CRTC_START_LINE_CONTROL
++#define CRTC4_CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0
++#define CRTC4_CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x1
++#define CRTC4_CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x2
++#define CRTC4_CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x8
++#define CRTC4_CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc
++#define CRTC4_CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x00000001L
++#define CRTC4_CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x00000002L
++#define CRTC4_CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x00000004L
++#define CRTC4_CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x00000100L
++#define CRTC4_CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0x000FF000L
++//CRTC4_CRTC_INTERRUPT_CONTROL
++#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0
++#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1
++#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4
++#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5
++#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8
++#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9
++#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10
++#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11
++#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18
++#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19
++#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a
++#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b
++#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c
++#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d
++#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e
++#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f
++#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x00000001L
++#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x00000002L
++#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x00000010L
++#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x00000020L
++#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L
++#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L
++#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L
++#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L
++#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x01000000L
++#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x02000000L
++#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x04000000L
++#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x08000000L
++#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000L
++#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000L
++#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L
++#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L
++//CRTC4_CRTC_UPDATE_LOCK
++#define CRTC4_CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0
++#define CRTC4_CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x00000001L
++//CRTC4_CRTC_DOUBLE_BUFFER_CONTROL
++#define CRTC4_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0
++#define CRTC4_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8
++#define CRTC4_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10
++#define CRTC4_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18
++#define CRTC4_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x19
++#define CRTC4_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x00000001L
++#define CRTC4_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x00000100L
++#define CRTC4_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L
++#define CRTC4_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x01000000L
++#define CRTC4_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x02000000L
++//CRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE
++#define CRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0
++#define CRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x00000001L
++//CRTC4_CRTC_TEST_PATTERN_CONTROL
++#define CRTC4_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0
++#define CRTC4_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8
++#define CRTC4_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10
++#define CRTC4_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18
++#define CRTC4_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x00000001L
++#define CRTC4_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x00000700L
++#define CRTC4_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L
++#define CRTC4_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xFF000000L
++//CRTC4_CRTC_TEST_PATTERN_PARAMETERS
++#define CRTC4_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0
++#define CRTC4_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4
++#define CRTC4_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8
++#define CRTC4_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc
++#define CRTC4_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10
++#define CRTC4_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0x0000000FL
++#define CRTC4_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0x000000F0L
++#define CRTC4_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0x00000F00L
++#define CRTC4_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0x0000F000L
++#define CRTC4_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xFFFF0000L
++//CRTC4_CRTC_TEST_PATTERN_COLOR
++#define CRTC4_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0
++#define CRTC4_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10
++#define CRTC4_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0x0000FFFFL
++#define CRTC4_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x003F0000L
++//CRTC4_CRTC_MASTER_UPDATE_LOCK
++#define CRTC4_CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0
++#define CRTC4_CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8
++#define CRTC4_CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK__SHIFT 0x10
++#define CRTC4_CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x00000001L
++#define CRTC4_CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x00000100L
++#define CRTC4_CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK_MASK 0x00010000L
++//CRTC4_CRTC_MASTER_UPDATE_MODE
++#define CRTC4_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0
++#define CRTC4_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10
++#define CRTC4_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x00000007L
++#define CRTC4_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00030000L
++//CRTC4_CRTC_MVP_INBAND_CNTL_INSERT
++#define CRTC4_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0
++#define CRTC4_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8
++#define CRTC4_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x00000003L
++#define CRTC4_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xFFFFFF00L
++//CRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER
++#define CRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0
++#define CRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0x000000FFL
++//CRTC4_CRTC_MVP_STATUS
++#define CRTC4_CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0
++#define CRTC4_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4
++#define CRTC4_CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10
++#define CRTC4_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14
++#define CRTC4_CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x00000001L
++#define CRTC4_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x00000010L
++#define CRTC4_CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x00010000L
++#define CRTC4_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x00100000L
++//CRTC4_CRTC_MASTER_EN
++#define CRTC4_CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0
++#define CRTC4_CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x00000001L
++//CRTC4_CRTC_ALLOW_STOP_OFF_V_CNT
++#define CRTC4_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0
++#define CRTC4_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10
++#define CRTC4_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0x000000FFL
++#define CRTC4_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x00010000L
++//CRTC4_CRTC_V_UPDATE_INT_STATUS
++#define CRTC4_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0
++#define CRTC4_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8
++#define CRTC4_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x00000001L
++#define CRTC4_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x00000100L
++//CRTC4_CRTC_OVERSCAN_COLOR
++#define CRTC4_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0
++#define CRTC4_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa
++#define CRTC4_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14
++#define CRTC4_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x000003FFL
++#define CRTC4_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0x000FFC00L
++#define CRTC4_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3FF00000L
++//CRTC4_CRTC_OVERSCAN_COLOR_EXT
++#define CRTC4_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0
++#define CRTC4_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8
++#define CRTC4_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10
++#define CRTC4_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x00000003L
++#define CRTC4_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x00000300L
++#define CRTC4_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x00030000L
++//CRTC4_CRTC_BLANK_DATA_COLOR
++#define CRTC4_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0
++#define CRTC4_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa
++#define CRTC4_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14
++#define CRTC4_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL
++#define CRTC4_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L
++#define CRTC4_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L
++//CRTC4_CRTC_BLANK_DATA_COLOR_EXT
++#define CRTC4_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0
++#define CRTC4_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8
++#define CRTC4_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10
++#define CRTC4_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x00000003L
++#define CRTC4_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00000300L
++#define CRTC4_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x00030000L
++//CRTC4_CRTC_BLACK_COLOR
++#define CRTC4_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0
++#define CRTC4_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa
++#define CRTC4_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14
++#define CRTC4_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x000003FFL
++#define CRTC4_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0x000FFC00L
++#define CRTC4_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3FF00000L
++//CRTC4_CRTC_BLACK_COLOR_EXT
++#define CRTC4_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0
++#define CRTC4_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8
++#define CRTC4_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10
++#define CRTC4_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x00000003L
++#define CRTC4_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x00000300L
++#define CRTC4_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x00030000L
++//CRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION
++#define CRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0
++#define CRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10
++#define CRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00003FFFL
++#define CRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x3FFF0000L
++//CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL
++#define CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4
++#define CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8
++#define CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc
++#define CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10
++#define CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14
++#define CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18
++#define CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L
++#define CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L
++#define CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L
++#define CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L
++#define CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L
++#define CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L
++//CRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION
++#define CRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0
++#define CRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00003FFFL
++//CRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL
++#define CRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8
++#define CRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc
++#define CRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10
++#define CRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14
++#define CRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18
++#define CRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L
++#define CRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L
++#define CRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L
++#define CRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L
++#define CRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L
++//CRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION
++#define CRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0
++#define CRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00003FFFL
++//CRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL
++#define CRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8
++#define CRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc
++#define CRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10
++#define CRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14
++#define CRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18
++#define CRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L
++#define CRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L
++#define CRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L
++#define CRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L
++#define CRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L
++//CRTC4_CRTC_CRC_CNTL
++#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0
++#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4
++#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8
++#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc
++#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
++#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14
++#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18
++#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC_EN_MASK 0x00000001L
++#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x00000010L
++#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x00000300L
++#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x00003000L
++#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
++#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x00700000L
++#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x07000000L
++//CRTC4_CRTC_CRC0_WINDOWA_X_CONTROL
++#define CRTC4_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0
++#define CRTC4_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10
++#define CRTC4_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x00003FFFL
++#define CRTC4_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3FFF0000L
++//CRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL
++#define CRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0
++#define CRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10
++#define CRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x00003FFFL
++#define CRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3FFF0000L
++//CRTC4_CRTC_CRC0_WINDOWB_X_CONTROL
++#define CRTC4_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0
++#define CRTC4_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10
++#define CRTC4_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x00003FFFL
++#define CRTC4_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3FFF0000L
++//CRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL
++#define CRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0
++#define CRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10
++#define CRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x00003FFFL
++#define CRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3FFF0000L
++//CRTC4_CRTC_CRC0_DATA_RG
++#define CRTC4_CRTC_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0
++#define CRTC4_CRTC_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10
++#define CRTC4_CRTC_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL
++#define CRTC4_CRTC_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L
++//CRTC4_CRTC_CRC0_DATA_B
++#define CRTC4_CRTC_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0
++#define CRTC4_CRTC_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL
++//CRTC4_CRTC_CRC1_WINDOWA_X_CONTROL
++#define CRTC4_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0
++#define CRTC4_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10
++#define CRTC4_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x00003FFFL
++#define CRTC4_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3FFF0000L
++//CRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL
++#define CRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0
++#define CRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10
++#define CRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x00003FFFL
++#define CRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3FFF0000L
++//CRTC4_CRTC_CRC1_WINDOWB_X_CONTROL
++#define CRTC4_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0
++#define CRTC4_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10
++#define CRTC4_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x00003FFFL
++#define CRTC4_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3FFF0000L
++//CRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL
++#define CRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0
++#define CRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10
++#define CRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x00003FFFL
++#define CRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3FFF0000L
++//CRTC4_CRTC_CRC1_DATA_RG
++#define CRTC4_CRTC_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0
++#define CRTC4_CRTC_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10
++#define CRTC4_CRTC_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL
++#define CRTC4_CRTC_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L
++//CRTC4_CRTC_CRC1_DATA_B
++#define CRTC4_CRTC_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0
++#define CRTC4_CRTC_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL
++//CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL
++#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE__SHIFT 0x0
++#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__SHIFT 0x3
++#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__SHIFT 0x4
++#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__SHIFT 0x5
++#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__SHIFT 0x8
++#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__SHIFT 0x9
++#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__SHIFT 0xc
++#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__SHIFT 0xd
++#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__SHIFT 0xe
++#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE__SHIFT 0x18
++#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE__SHIFT 0x1c
++#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE_MASK 0x00000003L
++#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_MASK 0x00000008L
++#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_MASK 0x00000010L
++#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_MASK 0x00000060L
++#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_MASK 0x00000100L
++#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_MASK 0x00000200L
++#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_MASK 0x00001000L
++#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_MASK 0x00002000L
++#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_MASK 0x00004000L
++#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE_MASK 0x07000000L
++#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE_MASK 0x70000000L
++//CRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START
++#define CRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X__SHIFT 0x0
++#define CRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y__SHIFT 0x10
++#define CRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X_MASK 0x00003FFFL
++#define CRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y_MASK 0x3FFF0000L
++//CRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END
++#define CRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X__SHIFT 0x0
++#define CRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y__SHIFT 0x10
++#define CRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X_MASK 0x00003FFFL
++#define CRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y_MASK 0x3FFF0000L
++//CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL
++#define CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__SHIFT 0x0
++#define CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS__SHIFT 0x4
++#define CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS__SHIFT 0x8
++#define CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__SHIFT 0x10
++#define CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__SHIFT 0x14
++#define CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__SHIFT 0x1d
++#define CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_MASK 0x00000001L
++#define CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS_MASK 0x00000010L
++#define CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS_MASK 0x00000100L
++#define CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_MASK 0x00010000L
++#define CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_MASK 0x00100000L
++#define CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_MASK 0xE0000000L
++//CRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL
++#define CRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE__SHIFT 0x0
++#define CRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS__SHIFT 0x4
++#define CRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS__SHIFT 0x8
++#define CRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR__SHIFT 0x10
++#define CRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE__SHIFT 0x14
++#define CRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE_MASK 0x00000001L
++#define CRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS_MASK 0x00000010L
++#define CRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS_MASK 0x00000100L
++#define CRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR_MASK 0x00010000L
++#define CRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE_MASK 0x00100000L
++//CRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL
++#define CRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__SHIFT 0x0
++#define CRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS__SHIFT 0x4
++#define CRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS__SHIFT 0x8
++#define CRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__SHIFT 0x10
++#define CRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__SHIFT 0x14
++#define CRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_MASK 0x00000001L
++#define CRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS_MASK 0x00000010L
++#define CRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS_MASK 0x00000100L
++#define CRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_MASK 0x00010000L
++#define CRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_MASK 0x00100000L
++//CRTC4_CRTC_STATIC_SCREEN_CONTROL
++#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0
++#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10
++#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18
++#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19
++#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a
++#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b
++#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c
++#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e
++#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f
++#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL
++#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L
++#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x01000000L
++#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x02000000L
++#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x04000000L
++#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x08000000L
++#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000L
++#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L
++#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L
++//CRTC4_CRTC_3D_STRUCTURE_CONTROL
++#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0
++#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4
++#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8
++#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc
++#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10
++#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11
++#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12
++#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x00000001L
++#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x00000010L
++#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L
++#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L
++#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L
++#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L
++#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L
++//CRTC4_CRTC_GSL_VSYNC_GAP
++#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0
++#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8
++#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10
++#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11
++#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13
++#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14
++#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17
++#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18
++#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL
++#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L
++#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L
++#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x00060000L
++#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L
++#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L
++#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L
++#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xFF000000L
++//CRTC4_CRTC_GSL_WINDOW
++#define CRTC4_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0
++#define CRTC4_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10
++#define CRTC4_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x00003FFFL
++#define CRTC4_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x3FFF0000L
++//CRTC4_CRTC_GSL_CONTROL
++#define CRTC4_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0
++#define CRTC4_CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10
++#define CRTC4_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c
++#define CRTC4_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x00003FFFL
++#define CRTC4_CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x001F0000L
++#define CRTC4_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L
++//CRTC4_CRTC_RANGE_TIMING_INT_STATUS
++#define CRTC4_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0
++#define CRTC4_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4
++#define CRTC4_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8
++#define CRTC4_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc
++#define CRTC4_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10
++#define CRTC4_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L
++#define CRTC4_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L
++#define CRTC4_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L
++#define CRTC4_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L
++#define CRTC4_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L
++//CRTC4_CRTC_DRR_CONTROL
++#define CRTC4_CRTC_DRR_CONTROL__CRTC_XDMA_PREFETCH_DELAY__SHIFT 0x0
++#define CRTC4_CRTC_DRR_CONTROL__CRTC_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0xe
++#define CRTC4_CRTC_DRR_CONTROL__CRTC_SET_V_TOTAL_MIN_AUTO_DIS__SHIFT 0x1c
++#define CRTC4_CRTC_DRR_CONTROL__CRTC_DRR_MODE_DBUF_UPDATE_MODE__SHIFT 0x1d
++#define CRTC4_CRTC_DRR_CONTROL__CRTC_XDMA_PREFETCH_DELAY_MASK 0x00003FFFL
++#define CRTC4_CRTC_DRR_CONTROL__CRTC_V_TOTAL_LAST_USED_BY_DRR_MASK 0x0FFFC000L
++#define CRTC4_CRTC_DRR_CONTROL__CRTC_SET_V_TOTAL_MIN_AUTO_DIS_MASK 0x10000000L
++#define CRTC4_CRTC_DRR_CONTROL__CRTC_DRR_MODE_DBUF_UPDATE_MODE_MASK 0x60000000L
++
++
++// addressBlock: dce_dc_fmt4_dispdec
++//FMT4_FMT_CLAMP_COMPONENT_R
++#define FMT4_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0
++#define FMT4_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10
++#define FMT4_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL
++#define FMT4_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L
++//FMT4_FMT_CLAMP_COMPONENT_G
++#define FMT4_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0
++#define FMT4_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10
++#define FMT4_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL
++#define FMT4_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L
++//FMT4_FMT_CLAMP_COMPONENT_B
++#define FMT4_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0
++#define FMT4_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10
++#define FMT4_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL
++#define FMT4_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L
++//FMT4_FMT_DYNAMIC_EXP_CNTL
++#define FMT4_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0
++#define FMT4_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4
++#define FMT4_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L
++#define FMT4_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L
++//FMT4_FMT_CONTROL
++#define FMT4_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0
++#define FMT4_FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT 0x4
++#define FMT4_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8
++#define FMT4_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc
++#define FMT4_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10
++#define FMT4_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12
++#define FMT4_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14
++#define FMT4_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15
++#define FMT4_FMT_CONTROL__FMT_SRC_SELECT__SHIFT 0x18
++#define FMT4_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED__SHIFT 0x1e
++#define FMT4_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_CLEAR__SHIFT 0x1f
++#define FMT4_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L
++#define FMT4_FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK 0x00000010L
++#define FMT4_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L
++#define FMT4_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L
++#define FMT4_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L
++#define FMT4_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L
++#define FMT4_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L
++#define FMT4_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L
++#define FMT4_FMT_CONTROL__FMT_SRC_SELECT_MASK 0x07000000L
++#define FMT4_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_MASK 0x40000000L
++#define FMT4_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_CLEAR_MASK 0x80000000L
++//FMT4_FMT_BIT_DEPTH_CONTROL
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L
++//FMT4_FMT_DITHER_RAND_R_SEED
++#define FMT4_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0
++#define FMT4_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10
++#define FMT4_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL
++#define FMT4_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L
++//FMT4_FMT_DITHER_RAND_G_SEED
++#define FMT4_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0
++#define FMT4_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10
++#define FMT4_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL
++#define FMT4_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L
++//FMT4_FMT_DITHER_RAND_B_SEED
++#define FMT4_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0
++#define FMT4_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10
++#define FMT4_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL
++#define FMT4_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L
++//FMT4_FMT_CLAMP_CNTL
++#define FMT4_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0
++#define FMT4_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10
++#define FMT4_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L
++#define FMT4_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L
++//FMT4_FMT_CRC_CNTL
++#define FMT4_FMT_CRC_CNTL__FMT_CRC_EN__SHIFT 0x0
++#define FMT4_FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN__SHIFT 0x1
++#define FMT4_FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT 0x4
++#define FMT4_FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING__SHIFT 0x5
++#define FMT4_FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN__SHIFT 0x6
++#define FMT4_FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB__SHIFT 0x8
++#define FMT4_FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE__SHIFT 0x9
++#define FMT4_FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT 0xc
++#define FMT4_FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
++#define FMT4_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT 0x14
++#define FMT4_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT 0x18
++#define FMT4_FMT_CRC_CNTL__FMT_CRC_EN_MASK 0x00000001L
++#define FMT4_FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN_MASK 0x00000002L
++#define FMT4_FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK 0x00000010L
++#define FMT4_FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING_MASK 0x00000020L
++#define FMT4_FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN_MASK 0x00000040L
++#define FMT4_FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB_MASK 0x00000100L
++#define FMT4_FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE_MASK 0x00000200L
++#define FMT4_FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK 0x00003000L
++#define FMT4_FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
++#define FMT4_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK 0x00100000L
++#define FMT4_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK 0x01000000L
++//FMT4_FMT_CRC_SIG_RED_GREEN_MASK
++#define FMT4_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT 0x0
++#define FMT4_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT 0x10
++#define FMT4_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK 0x0000FFFFL
++#define FMT4_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L
++//FMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK
++#define FMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT 0x0
++#define FMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT 0x10
++#define FMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL
++#define FMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L
++//FMT4_FMT_CRC_SIG_RED_GREEN
++#define FMT4_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT 0x0
++#define FMT4_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT 0x10
++#define FMT4_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK 0x0000FFFFL
++#define FMT4_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK 0xFFFF0000L
++//FMT4_FMT_CRC_SIG_BLUE_CONTROL
++#define FMT4_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT 0x0
++#define FMT4_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT 0x10
++#define FMT4_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK 0x0000FFFFL
++#define FMT4_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK 0xFFFF0000L
++//FMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL
++#define FMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0
++#define FMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL
++//FMT4_FMT_420_HBLANK_EARLY_START
++#define FMT4_FMT_420_HBLANK_EARLY_START__FMT_420_HBLANK_EARLY_START__SHIFT 0x0
++#define FMT4_FMT_420_HBLANK_EARLY_START__FMT_420_HBLANK_EARLY_START_MASK 0x00000FFFL
++
++
++// addressBlock: dce_dc_dcp5_dispdec
++//DCP5_GRPH_ENABLE
++#define DCP5_GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0
++#define DCP5_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL__SHIFT 0x1
++#define DCP5_GRPH_ENABLE__GRPH_ENABLE_MASK 0x00000001L
++#define DCP5_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL_MASK 0x00000002L
++//DCP5_GRPH_CONTROL
++#define DCP5_GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0
++#define DCP5_GRPH_CONTROL__GRPH_SE_ENABLE__SHIFT 0x2
++#define DCP5_GRPH_CONTROL__GRPH_Z__SHIFT 0x4
++#define DCP5_GRPH_CONTROL__GRPH_DIM_TYPE__SHIFT 0x6
++#define DCP5_GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8
++#define DCP5_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0xc
++#define DCP5_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10
++#define DCP5_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11
++#define DCP5_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES__SHIFT 0x12
++#define DCP5_GRPH_CONTROL__GRPH_SW_MODE__SHIFT 0x14
++#define DCP5_GRPH_CONTROL__GRPH_NUM_PIPES__SHIFT 0x1c
++#define DCP5_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f
++#define DCP5_GRPH_CONTROL__GRPH_DEPTH_MASK 0x00000003L
++#define DCP5_GRPH_CONTROL__GRPH_SE_ENABLE_MASK 0x00000004L
++#define DCP5_GRPH_CONTROL__GRPH_Z_MASK 0x00000030L
++#define DCP5_GRPH_CONTROL__GRPH_DIM_TYPE_MASK 0x000000C0L
++#define DCP5_GRPH_CONTROL__GRPH_FORMAT_MASK 0x00000700L
++#define DCP5_GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0x00007000L
++#define DCP5_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x00010000L
++#define DCP5_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x00020000L
++#define DCP5_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES_MASK 0x000C0000L
++#define DCP5_GRPH_CONTROL__GRPH_SW_MODE_MASK 0x01F00000L
++#define DCP5_GRPH_CONTROL__GRPH_NUM_PIPES_MASK 0x70000000L
++#define DCP5_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000L
++//DCP5_GRPH_LUT_10BIT_BYPASS
++#define DCP5_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT 0x8
++#define DCP5_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x10
++#define DCP5_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK 0x00000100L
++#define DCP5_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x00010000L
++//DCP5_GRPH_SWAP_CNTL
++#define DCP5_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0
++#define DCP5_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4
++#define DCP5_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6
++#define DCP5_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8
++#define DCP5_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT 0xa
++#define DCP5_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x00000003L
++#define DCP5_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x00000030L
++#define DCP5_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0x000000C0L
++#define DCP5_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x00000300L
++#define DCP5_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK 0x00000C00L
++//DCP5_GRPH_PRIMARY_SURFACE_ADDRESS
++#define DCP5_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT 0x0
++#define DCP5_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT 0x8
++#define DCP5_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK 0x00000001L
++#define DCP5_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
++//DCP5_GRPH_SECONDARY_SURFACE_ADDRESS
++#define DCP5_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT 0x0
++#define DCP5_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8
++#define DCP5_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK 0x00000001L
++#define DCP5_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
++//DCP5_GRPH_PITCH
++#define DCP5_GRPH_PITCH__GRPH_PITCH__SHIFT 0x0
++#define DCP5_GRPH_PITCH__GRPH_PITCH_MASK 0x00007FFFL
++//DCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
++#define DCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define DCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
++//DCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
++#define DCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define DCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
++//DCP5_GRPH_SURFACE_OFFSET_X
++#define DCP5_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT 0x0
++#define DCP5_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK 0x00003FFFL
++//DCP5_GRPH_SURFACE_OFFSET_Y
++#define DCP5_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT 0x0
++#define DCP5_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK 0x00003FFFL
++//DCP5_GRPH_X_START
++#define DCP5_GRPH_X_START__GRPH_X_START__SHIFT 0x0
++#define DCP5_GRPH_X_START__GRPH_X_START_MASK 0x00003FFFL
++//DCP5_GRPH_Y_START
++#define DCP5_GRPH_Y_START__GRPH_Y_START__SHIFT 0x0
++#define DCP5_GRPH_Y_START__GRPH_Y_START_MASK 0x00003FFFL
++//DCP5_GRPH_X_END
++#define DCP5_GRPH_X_END__GRPH_X_END__SHIFT 0x0
++#define DCP5_GRPH_X_END__GRPH_X_END_MASK 0x00007FFFL
++//DCP5_GRPH_Y_END
++#define DCP5_GRPH_Y_END__GRPH_Y_END__SHIFT 0x0
++#define DCP5_GRPH_Y_END__GRPH_Y_END_MASK 0x00007FFFL
++//DCP5_INPUT_GAMMA_CONTROL
++#define DCP5_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x0
++#define DCP5_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK 0x00000001L
++//DCP5_GRPH_UPDATE
++#define DCP5_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0
++#define DCP5_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1
++#define DCP5_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2
++#define DCP5_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3
++#define DCP5_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR__SHIFT 0x8
++#define DCP5_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE__SHIFT 0x9
++#define DCP5_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE__SHIFT 0xa
++#define DCP5_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10
++#define DCP5_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14
++#define DCP5_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
++#define DCP5_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c
++#define DCP5_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x00000001L
++#define DCP5_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x00000002L
++#define DCP5_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x00000004L
++#define DCP5_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x00000008L
++#define DCP5_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR_MASK 0x00000100L
++#define DCP5_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE_MASK 0x00000200L
++#define DCP5_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE_MASK 0x00000400L
++#define DCP5_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x00010000L
++#define DCP5_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x00100000L
++#define DCP5_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
++#define DCP5_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000L
++//DCP5_GRPH_FLIP_CONTROL
++#define DCP5_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT 0x0
++#define DCP5_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN__SHIFT 0x1
++#define DCP5_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN__SHIFT 0x4
++#define DCP5_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT 0x5
++#define DCP5_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK 0x00000001L
++#define DCP5_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN_MASK 0x00000002L
++#define DCP5_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN_MASK 0x00000010L
++#define DCP5_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK 0x00000020L
++//DCP5_GRPH_SURFACE_ADDRESS_INUSE
++#define DCP5_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT 0x8
++#define DCP5_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK 0xFFFFFF00L
++//DCP5_GRPH_DFQ_CONTROL
++#define DCP5_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x0
++#define DCP5_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x4
++#define DCP5_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8
++#define DCP5_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x00000001L
++#define DCP5_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x00000070L
++#define DCP5_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x00000700L
++//DCP5_GRPH_DFQ_STATUS
++#define DCP5_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x0
++#define DCP5_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4
++#define DCP5_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x8
++#define DCP5_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x9
++#define DCP5_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0x0000000FL
++#define DCP5_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0x000000F0L
++#define DCP5_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x00000100L
++#define DCP5_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x00000200L
++//DCP5_GRPH_INTERRUPT_STATUS
++#define DCP5_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0
++#define DCP5_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8
++#define DCP5_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x00000001L
++#define DCP5_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x00000100L
++//DCP5_GRPH_INTERRUPT_CONTROL
++#define DCP5_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0
++#define DCP5_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8
++#define DCP5_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x00000001L
++#define DCP5_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x00000100L
++//DCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE
++#define DCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0
++#define DCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK 0x000000FFL
++//DCP5_GRPH_COMPRESS_SURFACE_ADDRESS
++#define DCP5_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT 0x8
++#define DCP5_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK 0xFFFFFF00L
++//DCP5_GRPH_COMPRESS_PITCH
++#define DCP5_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT 0x6
++#define DCP5_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK 0x0001FFC0L
++//DCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH
++#define DCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define DCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
++//DCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT
++#define DCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__SHIFT 0x0
++#define DCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_MASK 0x000000FFL
++//DCP5_PRESCALE_GRPH_CONTROL
++#define DCP5_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT 0x0
++#define DCP5_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT 0x1
++#define DCP5_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x2
++#define DCP5_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT 0x3
++#define DCP5_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT 0x4
++#define DCP5_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK 0x00000001L
++#define DCP5_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x00000002L
++#define DCP5_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK 0x00000004L
++#define DCP5_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK 0x00000008L
++#define DCP5_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK 0x00000010L
++//DCP5_PRESCALE_VALUES_GRPH_R
++#define DCP5_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT 0x0
++#define DCP5_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT 0x10
++#define DCP5_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK 0x0000FFFFL
++#define DCP5_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK 0xFFFF0000L
++//DCP5_PRESCALE_VALUES_GRPH_G
++#define DCP5_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT 0x0
++#define DCP5_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT 0x10
++#define DCP5_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK 0x0000FFFFL
++#define DCP5_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK 0xFFFF0000L
++//DCP5_PRESCALE_VALUES_GRPH_B
++#define DCP5_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT 0x0
++#define DCP5_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT 0x10
++#define DCP5_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK 0x0000FFFFL
++#define DCP5_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK 0xFFFF0000L
++//DCP5_INPUT_CSC_CONTROL
++#define DCP5_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT 0x0
++#define DCP5_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK 0x00000003L
++//DCP5_INPUT_CSC_C11_C12
++#define DCP5_INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT 0x0
++#define DCP5_INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT 0x10
++#define DCP5_INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK 0x0000FFFFL
++#define DCP5_INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK 0xFFFF0000L
++//DCP5_INPUT_CSC_C13_C14
++#define DCP5_INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT 0x0
++#define DCP5_INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT 0x10
++#define DCP5_INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK 0x0000FFFFL
++#define DCP5_INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK 0xFFFF0000L
++//DCP5_INPUT_CSC_C21_C22
++#define DCP5_INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT 0x0
++#define DCP5_INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT 0x10
++#define DCP5_INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK 0x0000FFFFL
++#define DCP5_INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK 0xFFFF0000L
++//DCP5_INPUT_CSC_C23_C24
++#define DCP5_INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT 0x0
++#define DCP5_INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT 0x10
++#define DCP5_INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK 0x0000FFFFL
++#define DCP5_INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK 0xFFFF0000L
++//DCP5_INPUT_CSC_C31_C32
++#define DCP5_INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT 0x0
++#define DCP5_INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT 0x10
++#define DCP5_INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK 0x0000FFFFL
++#define DCP5_INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK 0xFFFF0000L
++//DCP5_INPUT_CSC_C33_C34
++#define DCP5_INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT 0x0
++#define DCP5_INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT 0x10
++#define DCP5_INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK 0x0000FFFFL
++#define DCP5_INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK 0xFFFF0000L
++//DCP5_OUTPUT_CSC_CONTROL
++#define DCP5_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT 0x0
++#define DCP5_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK 0x00000007L
++//DCP5_OUTPUT_CSC_C11_C12
++#define DCP5_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT 0x0
++#define DCP5_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT 0x10
++#define DCP5_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK 0x0000FFFFL
++#define DCP5_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK 0xFFFF0000L
++//DCP5_OUTPUT_CSC_C13_C14
++#define DCP5_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT 0x0
++#define DCP5_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT 0x10
++#define DCP5_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK 0x0000FFFFL
++#define DCP5_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK 0xFFFF0000L
++//DCP5_OUTPUT_CSC_C21_C22
++#define DCP5_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT 0x0
++#define DCP5_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT 0x10
++#define DCP5_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK 0x0000FFFFL
++#define DCP5_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK 0xFFFF0000L
++//DCP5_OUTPUT_CSC_C23_C24
++#define DCP5_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT 0x0
++#define DCP5_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT 0x10
++#define DCP5_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK 0x0000FFFFL
++#define DCP5_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK 0xFFFF0000L
++//DCP5_OUTPUT_CSC_C31_C32
++#define DCP5_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT 0x0
++#define DCP5_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT 0x10
++#define DCP5_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK 0x0000FFFFL
++#define DCP5_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK 0xFFFF0000L
++//DCP5_OUTPUT_CSC_C33_C34
++#define DCP5_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT 0x0
++#define DCP5_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT 0x10
++#define DCP5_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK 0x0000FFFFL
++#define DCP5_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK 0xFFFF0000L
++//DCP5_COMM_MATRIXA_TRANS_C11_C12
++#define DCP5_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT 0x0
++#define DCP5_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT 0x10
++#define DCP5_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK 0x0000FFFFL
++#define DCP5_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK 0xFFFF0000L
++//DCP5_COMM_MATRIXA_TRANS_C13_C14
++#define DCP5_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT 0x0
++#define DCP5_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT 0x10
++#define DCP5_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK 0x0000FFFFL
++#define DCP5_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK 0xFFFF0000L
++//DCP5_COMM_MATRIXA_TRANS_C21_C22
++#define DCP5_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT 0x0
++#define DCP5_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT 0x10
++#define DCP5_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK 0x0000FFFFL
++#define DCP5_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK 0xFFFF0000L
++//DCP5_COMM_MATRIXA_TRANS_C23_C24
++#define DCP5_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT 0x0
++#define DCP5_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT 0x10
++#define DCP5_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK 0x0000FFFFL
++#define DCP5_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK 0xFFFF0000L
++//DCP5_COMM_MATRIXA_TRANS_C31_C32
++#define DCP5_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT 0x0
++#define DCP5_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT 0x10
++#define DCP5_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK 0x0000FFFFL
++#define DCP5_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK 0xFFFF0000L
++//DCP5_COMM_MATRIXA_TRANS_C33_C34
++#define DCP5_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT 0x0
++#define DCP5_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT 0x10
++#define DCP5_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK 0x0000FFFFL
++#define DCP5_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK 0xFFFF0000L
++//DCP5_COMM_MATRIXB_TRANS_C11_C12
++#define DCP5_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT 0x0
++#define DCP5_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT 0x10
++#define DCP5_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK 0x0000FFFFL
++#define DCP5_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK 0xFFFF0000L
++//DCP5_COMM_MATRIXB_TRANS_C13_C14
++#define DCP5_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT 0x0
++#define DCP5_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT 0x10
++#define DCP5_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK 0x0000FFFFL
++#define DCP5_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK 0xFFFF0000L
++//DCP5_COMM_MATRIXB_TRANS_C21_C22
++#define DCP5_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT 0x0
++#define DCP5_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT 0x10
++#define DCP5_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK 0x0000FFFFL
++#define DCP5_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK 0xFFFF0000L
++//DCP5_COMM_MATRIXB_TRANS_C23_C24
++#define DCP5_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT 0x0
++#define DCP5_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT 0x10
++#define DCP5_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK 0x0000FFFFL
++#define DCP5_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK 0xFFFF0000L
++//DCP5_COMM_MATRIXB_TRANS_C31_C32
++#define DCP5_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT 0x0
++#define DCP5_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT 0x10
++#define DCP5_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK 0x0000FFFFL
++#define DCP5_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK 0xFFFF0000L
++//DCP5_COMM_MATRIXB_TRANS_C33_C34
++#define DCP5_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT 0x0
++#define DCP5_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT 0x10
++#define DCP5_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK 0x0000FFFFL
++#define DCP5_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK 0xFFFF0000L
++//DCP5_DENORM_CONTROL
++#define DCP5_DENORM_CONTROL__DENORM_MODE__SHIFT 0x0
++#define DCP5_DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT 0x4
++#define DCP5_DENORM_CONTROL__DENORM_MODE_MASK 0x00000007L
++#define DCP5_DENORM_CONTROL__DENORM_14BIT_OUT_MASK 0x00000010L
++//DCP5_OUT_ROUND_CONTROL
++#define DCP5_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT 0x0
++#define DCP5_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK 0x0000000FL
++//DCP5_OUT_CLAMP_CONTROL_R_CR
++#define DCP5_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT 0x0
++#define DCP5_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT 0x10
++#define DCP5_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK 0x00003FFFL
++#define DCP5_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK 0x3FFF0000L
++//DCP5_OUT_CLAMP_CONTROL_G_Y
++#define DCP5_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT 0x0
++#define DCP5_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT 0x10
++#define DCP5_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK 0x00003FFFL
++#define DCP5_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK 0x3FFF0000L
++//DCP5_OUT_CLAMP_CONTROL_B_CB
++#define DCP5_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT 0x0
++#define DCP5_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT 0x10
++#define DCP5_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK 0x00003FFFL
++#define DCP5_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK 0x3FFF0000L
++//DCP5_KEY_CONTROL
++#define DCP5_KEY_CONTROL__KEY_MODE__SHIFT 0x1
++#define DCP5_KEY_CONTROL__KEY_MODE_MASK 0x00000006L
++//DCP5_KEY_RANGE_ALPHA
++#define DCP5_KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT 0x0
++#define DCP5_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT 0x10
++#define DCP5_KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK 0x0000FFFFL
++#define DCP5_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK 0xFFFF0000L
++//DCP5_KEY_RANGE_RED
++#define DCP5_KEY_RANGE_RED__KEY_RED_LOW__SHIFT 0x0
++#define DCP5_KEY_RANGE_RED__KEY_RED_HIGH__SHIFT 0x10
++#define DCP5_KEY_RANGE_RED__KEY_RED_LOW_MASK 0x0000FFFFL
++#define DCP5_KEY_RANGE_RED__KEY_RED_HIGH_MASK 0xFFFF0000L
++//DCP5_KEY_RANGE_GREEN
++#define DCP5_KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT 0x0
++#define DCP5_KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT 0x10
++#define DCP5_KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK 0x0000FFFFL
++#define DCP5_KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK 0xFFFF0000L
++//DCP5_KEY_RANGE_BLUE
++#define DCP5_KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT 0x0
++#define DCP5_KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT 0x10
++#define DCP5_KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK 0x0000FFFFL
++#define DCP5_KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK 0xFFFF0000L
++//DCP5_DEGAMMA_CONTROL
++#define DCP5_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x0
++#define DCP5_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT 0x8
++#define DCP5_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0xc
++#define DCP5_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x00000003L
++#define DCP5_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK 0x00000300L
++#define DCP5_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK 0x00003000L
++//DCP5_GAMUT_REMAP_CONTROL
++#define DCP5_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT 0x0
++#define DCP5_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK 0x00000003L
++//DCP5_GAMUT_REMAP_C11_C12
++#define DCP5_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT 0x0
++#define DCP5_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT 0x10
++#define DCP5_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK 0x0000FFFFL
++#define DCP5_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK 0xFFFF0000L
++//DCP5_GAMUT_REMAP_C13_C14
++#define DCP5_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT 0x0
++#define DCP5_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT 0x10
++#define DCP5_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK 0x0000FFFFL
++#define DCP5_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK 0xFFFF0000L
++//DCP5_GAMUT_REMAP_C21_C22
++#define DCP5_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT 0x0
++#define DCP5_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT 0x10
++#define DCP5_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK 0x0000FFFFL
++#define DCP5_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK 0xFFFF0000L
++//DCP5_GAMUT_REMAP_C23_C24
++#define DCP5_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT 0x0
++#define DCP5_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT 0x10
++#define DCP5_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK 0x0000FFFFL
++#define DCP5_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK 0xFFFF0000L
++//DCP5_GAMUT_REMAP_C31_C32
++#define DCP5_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT 0x0
++#define DCP5_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT 0x10
++#define DCP5_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK 0x0000FFFFL
++#define DCP5_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK 0xFFFF0000L
++//DCP5_GAMUT_REMAP_C33_C34
++#define DCP5_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT 0x0
++#define DCP5_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT 0x10
++#define DCP5_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK 0x0000FFFFL
++#define DCP5_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK 0xFFFF0000L
++//DCP5_DCP_SPATIAL_DITHER_CNTL
++#define DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT 0x0
++#define DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT 0x4
++#define DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT 0x6
++#define DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT 0x8
++#define DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT 0x9
++#define DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT 0xa
++#define DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK 0x00000001L
++#define DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK 0x00000030L
++#define DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK 0x000000C0L
++#define DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK 0x00000100L
++#define DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK 0x00000200L
++#define DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK 0x00000400L
++//DCP5_DCP_RANDOM_SEEDS
++#define DCP5_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT 0x0
++#define DCP5_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT 0x8
++#define DCP5_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT 0x10
++#define DCP5_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK 0x000000FFL
++#define DCP5_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK 0x0000FF00L
++#define DCP5_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK 0x00FF0000L
++//DCP5_DCP_FP_CONVERTED_FIELD
++#define DCP5_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT 0x0
++#define DCP5_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14
++#define DCP5_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK 0x0003FFFFL
++#define DCP5_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK 0x07F00000L
++//DCP5_CUR_CONTROL
++#define DCP5_CUR_CONTROL__CURSOR_EN__SHIFT 0x0
++#define DCP5_CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT 0x4
++#define DCP5_CUR_CONTROL__CURSOR_MODE__SHIFT 0x8
++#define DCP5_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM__SHIFT 0xb
++#define DCP5_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION__SHIFT 0xc
++#define DCP5_CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x10
++#define DCP5_CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT 0x14
++#define DCP5_CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT 0x18
++#define DCP5_CUR_CONTROL__CURSOR_EN_MASK 0x00000001L
++#define DCP5_CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK 0x00000010L
++#define DCP5_CUR_CONTROL__CURSOR_MODE_MASK 0x00000300L
++#define DCP5_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM_MASK 0x00000800L
++#define DCP5_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION_MASK 0x0000F000L
++#define DCP5_CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00010000L
++#define DCP5_CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK 0x00100000L
++#define DCP5_CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK 0x07000000L
++//DCP5_CUR_SURFACE_ADDRESS
++#define DCP5_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0
++#define DCP5_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
++//DCP5_CUR_SIZE
++#define DCP5_CUR_SIZE__CURSOR_HEIGHT__SHIFT 0x0
++#define DCP5_CUR_SIZE__CURSOR_WIDTH__SHIFT 0x10
++#define DCP5_CUR_SIZE__CURSOR_HEIGHT_MASK 0x0000007FL
++#define DCP5_CUR_SIZE__CURSOR_WIDTH_MASK 0x007F0000L
++//DCP5_CUR_SURFACE_ADDRESS_HIGH
++#define DCP5_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define DCP5_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
++//DCP5_CUR_POSITION
++#define DCP5_CUR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0
++#define DCP5_CUR_POSITION__CURSOR_X_POSITION__SHIFT 0x10
++#define DCP5_CUR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL
++#define DCP5_CUR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L
++//DCP5_CUR_HOT_SPOT
++#define DCP5_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0
++#define DCP5_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10
++#define DCP5_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x0000007FL
++#define DCP5_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x007F0000L
++//DCP5_CUR_COLOR1
++#define DCP5_CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT 0x0
++#define DCP5_CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT 0x8
++#define DCP5_CUR_COLOR1__CUR_COLOR1_RED__SHIFT 0x10
++#define DCP5_CUR_COLOR1__CUR_COLOR1_BLUE_MASK 0x000000FFL
++#define DCP5_CUR_COLOR1__CUR_COLOR1_GREEN_MASK 0x0000FF00L
++#define DCP5_CUR_COLOR1__CUR_COLOR1_RED_MASK 0x00FF0000L
++//DCP5_CUR_COLOR2
++#define DCP5_CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT 0x0
++#define DCP5_CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT 0x8
++#define DCP5_CUR_COLOR2__CUR_COLOR2_RED__SHIFT 0x10
++#define DCP5_CUR_COLOR2__CUR_COLOR2_BLUE_MASK 0x000000FFL
++#define DCP5_CUR_COLOR2__CUR_COLOR2_GREEN_MASK 0x0000FF00L
++#define DCP5_CUR_COLOR2__CUR_COLOR2_RED_MASK 0x00FF0000L
++//DCP5_CUR_UPDATE
++#define DCP5_CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT 0x0
++#define DCP5_CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT 0x1
++#define DCP5_CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT 0x10
++#define DCP5_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
++#define DCP5_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE__SHIFT 0x19
++#define DCP5_CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK 0x00000001L
++#define DCP5_CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x00000002L
++#define DCP5_CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK 0x00010000L
++#define DCP5_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
++#define DCP5_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE_MASK 0x06000000L
++//DCP5_CUR_REQUEST_FILTER_CNTL
++#define DCP5_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT 0x0
++#define DCP5_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK 0x00000001L
++//DCP5_CUR_STEREO_CONTROL
++#define DCP5_CUR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0
++#define DCP5_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4
++#define DCP5_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x10
++#define DCP5_CUR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L
++#define DCP5_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x00003FF0L
++#define DCP5_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0x03FF0000L
++//DCP5_DC_LUT_RW_MODE
++#define DCP5_DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT 0x0
++#define DCP5_DC_LUT_RW_MODE__DC_LUT_ERROR__SHIFT 0x10
++#define DCP5_DC_LUT_RW_MODE__DC_LUT_ERROR_RST__SHIFT 0x11
++#define DCP5_DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK 0x00000001L
++#define DCP5_DC_LUT_RW_MODE__DC_LUT_ERROR_MASK 0x00010000L
++#define DCP5_DC_LUT_RW_MODE__DC_LUT_ERROR_RST_MASK 0x00020000L
++//DCP5_DC_LUT_RW_INDEX
++#define DCP5_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT 0x0
++#define DCP5_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK 0x000000FFL
++//DCP5_DC_LUT_SEQ_COLOR
++#define DCP5_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT 0x0
++#define DCP5_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK 0x0000FFFFL
++//DCP5_DC_LUT_PWL_DATA
++#define DCP5_DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT 0x0
++#define DCP5_DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT 0x10
++#define DCP5_DC_LUT_PWL_DATA__DC_LUT_BASE_MASK 0x0000FFFFL
++#define DCP5_DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK 0xFFFF0000L
++//DCP5_DC_LUT_30_COLOR
++#define DCP5_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT 0x0
++#define DCP5_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT 0xa
++#define DCP5_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT 0x14
++#define DCP5_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK 0x000003FFL
++#define DCP5_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK 0x000FFC00L
++#define DCP5_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK 0x3FF00000L
++//DCP5_DC_LUT_VGA_ACCESS_ENABLE
++#define DCP5_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT 0x0
++#define DCP5_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK 0x00000001L
++//DCP5_DC_LUT_WRITE_EN_MASK
++#define DCP5_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT 0x0
++#define DCP5_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK 0x00000007L
++//DCP5_DC_LUT_AUTOFILL
++#define DCP5_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT 0x0
++#define DCP5_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT 0x1
++#define DCP5_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK 0x00000001L
++#define DCP5_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x00000002L
++//DCP5_DC_LUT_CONTROL
++#define DCP5_DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT 0x0
++#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT 0x4
++#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT 0x5
++#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT 0x6
++#define DCP5_DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT 0x8
++#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT 0xc
++#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT 0xd
++#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT 0xe
++#define DCP5_DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT 0x10
++#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT 0x14
++#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT 0x15
++#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT 0x16
++#define DCP5_DC_LUT_CONTROL__DC_LUT_INC_B_MASK 0x0000000FL
++#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK 0x00000010L
++#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK 0x00000020L
++#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK 0x000000C0L
++#define DCP5_DC_LUT_CONTROL__DC_LUT_INC_G_MASK 0x00000F00L
++#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK 0x00001000L
++#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK 0x00002000L
++#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK 0x0000C000L
++#define DCP5_DC_LUT_CONTROL__DC_LUT_INC_R_MASK 0x000F0000L
++#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK 0x00100000L
++#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK 0x00200000L
++#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK 0x00C00000L
++//DCP5_DC_LUT_BLACK_OFFSET_BLUE
++#define DCP5_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0
++#define DCP5_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK 0x0000FFFFL
++//DCP5_DC_LUT_BLACK_OFFSET_GREEN
++#define DCP5_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0
++#define DCP5_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK 0x0000FFFFL
++//DCP5_DC_LUT_BLACK_OFFSET_RED
++#define DCP5_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT 0x0
++#define DCP5_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK 0x0000FFFFL
++//DCP5_DC_LUT_WHITE_OFFSET_BLUE
++#define DCP5_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT 0x0
++#define DCP5_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK 0x0000FFFFL
++//DCP5_DC_LUT_WHITE_OFFSET_GREEN
++#define DCP5_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT 0x0
++#define DCP5_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK 0x0000FFFFL
++//DCP5_DC_LUT_WHITE_OFFSET_RED
++#define DCP5_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT 0x0
++#define DCP5_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK 0x0000FFFFL
++//DCP5_DCP_CRC_CONTROL
++#define DCP5_DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT 0x0
++#define DCP5_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x2
++#define DCP5_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT 0x8
++#define DCP5_DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK 0x00000001L
++#define DCP5_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK 0x0000001CL
++#define DCP5_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK 0x00000300L
++//DCP5_DCP_CRC_MASK
++#define DCP5_DCP_CRC_MASK__DCP_CRC_MASK__SHIFT 0x0
++#define DCP5_DCP_CRC_MASK__DCP_CRC_MASK_MASK 0xFFFFFFFFL
++//DCP5_DCP_CRC_CURRENT
++#define DCP5_DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT 0x0
++#define DCP5_DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK 0xFFFFFFFFL
++//DCP5_DVMM_PTE_CONTROL
++#define DCP5_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT 0x0
++#define DCP5_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT 0x1
++#define DCP5_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT 0x5
++#define DCP5_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT 0x9
++#define DCP5_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT 0x14
++#define DCP5_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT 0x15
++#define DCP5_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK 0x00000001L
++#define DCP5_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK 0x0000001EL
++#define DCP5_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK 0x000001E0L
++#define DCP5_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK 0x0007FE00L
++#define DCP5_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK 0x00100000L
++#define DCP5_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK 0x00200000L
++//DCP5_DCP_CRC_LAST
++#define DCP5_DCP_CRC_LAST__DCP_CRC_LAST__SHIFT 0x0
++#define DCP5_DCP_CRC_LAST__DCP_CRC_LAST_MASK 0xFFFFFFFFL
++//DCP5_DVMM_PTE_ARB_CONTROL
++#define DCP5_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT 0x0
++#define DCP5_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT 0x8
++#define DCP5_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK 0x0000003FL
++#define DCP5_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK 0x0000FF00L
++//DCP5_GRPH_FLIP_RATE_CNTL
++#define DCP5_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT 0x0
++#define DCP5_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT 0x3
++#define DCP5_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK 0x00000007L
++#define DCP5_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK 0x00000008L
++//DCP5_DCP_GSL_CONTROL
++#define DCP5_DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT 0x0
++#define DCP5_DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT 0x1
++#define DCP5_DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x2
++#define DCP5_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT 0x4
++#define DCP5_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT 0x14
++#define DCP5_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP__SHIFT 0x15
++#define DCP5_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN__SHIFT 0x17
++#define DCP5_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT 0x18
++#define DCP5_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC__SHIFT 0x1a
++#define DCP5_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT 0x1b
++#define DCP5_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT 0x1c
++#define DCP5_DCP_GSL_CONTROL__DCP_GSL0_EN_MASK 0x00000001L
++#define DCP5_DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x00000002L
++#define DCP5_DCP_GSL_CONTROL__DCP_GSL2_EN_MASK 0x00000004L
++#define DCP5_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK 0x000FFFF0L
++#define DCP5_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK 0x00100000L
++#define DCP5_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_MASK 0x00600000L
++#define DCP5_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_MASK 0x00800000L
++#define DCP5_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK 0x03000000L
++#define DCP5_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_MASK 0x04000000L
++#define DCP5_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK 0x08000000L
++#define DCP5_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK 0xF0000000L
++//DCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK
++#define DCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT 0x0
++#define DCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT 0x4
++#define DCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK 0x0000000FL
++#define DCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK 0x000001F0L
++//DCP5_GRPH_STEREOSYNC_FLIP
++#define DCP5_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0
++#define DCP5_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x8
++#define DCP5_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10
++#define DCP5_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11
++#define DCP5_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c
++#define DCP5_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x00000001L
++#define DCP5_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x00000300L
++#define DCP5_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x00010000L
++#define DCP5_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x00020000L
++#define DCP5_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000L
++//DCP5_HW_ROTATION
++#define DCP5_HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT 0x0
++#define DCP5_HW_ROTATION__GRPH_ROTATION_ANGLE_MASK 0x00000007L
++//DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL
++#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT 0x0
++#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT 0x1
++#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT 0x4
++#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK 0x00000001L
++#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK 0x00000002L
++#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK 0x0001FFF0L
++//DCP5_REGAMMA_CONTROL
++#define DCP5_REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT 0x0
++#define DCP5_REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK 0x00000007L
++//DCP5_REGAMMA_LUT_INDEX
++#define DCP5_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x0
++#define DCP5_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK 0x000001FFL
++//DCP5_REGAMMA_LUT_DATA
++#define DCP5_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT 0x0
++#define DCP5_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK 0x0007FFFFL
++//DCP5_REGAMMA_LUT_WRITE_EN_MASK
++#define DCP5_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x0
++#define DCP5_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x00000007L
++//DCP5_REGAMMA_CNTLA_START_CNTL
++#define DCP5_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x0
++#define DCP5_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14
++#define DCP5_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK 0x0003FFFFL
++#define DCP5_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
++//DCP5_REGAMMA_CNTLA_SLOPE_CNTL
++#define DCP5_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
++#define DCP5_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
++//DCP5_REGAMMA_CNTLA_END_CNTL1
++#define DCP5_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x0
++#define DCP5_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK 0x0000FFFFL
++//DCP5_REGAMMA_CNTLA_END_CNTL2
++#define DCP5_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0
++#define DCP5_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10
++#define DCP5_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
++#define DCP5_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xFFFF0000L
++//DCP5_REGAMMA_CNTLA_REGION_0_1
++#define DCP5_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
++#define DCP5_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
++#define DCP5_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
++#define DCP5_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP5_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
++#define DCP5_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP5_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP5_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
++//DCP5_REGAMMA_CNTLA_REGION_2_3
++#define DCP5_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
++#define DCP5_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
++#define DCP5_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
++#define DCP5_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP5_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
++#define DCP5_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP5_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP5_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
++//DCP5_REGAMMA_CNTLA_REGION_4_5
++#define DCP5_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
++#define DCP5_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
++#define DCP5_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
++#define DCP5_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP5_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
++#define DCP5_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP5_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP5_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
++//DCP5_REGAMMA_CNTLA_REGION_6_7
++#define DCP5_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
++#define DCP5_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
++#define DCP5_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
++#define DCP5_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP5_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
++#define DCP5_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP5_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP5_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
++//DCP5_REGAMMA_CNTLA_REGION_8_9
++#define DCP5_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
++#define DCP5_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
++#define DCP5_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
++#define DCP5_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP5_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
++#define DCP5_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP5_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP5_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
++//DCP5_REGAMMA_CNTLA_REGION_10_11
++#define DCP5_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
++#define DCP5_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
++#define DCP5_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
++#define DCP5_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP5_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
++#define DCP5_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP5_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP5_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
++//DCP5_REGAMMA_CNTLA_REGION_12_13
++#define DCP5_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
++#define DCP5_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
++#define DCP5_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
++#define DCP5_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP5_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
++#define DCP5_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP5_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP5_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
++//DCP5_REGAMMA_CNTLA_REGION_14_15
++#define DCP5_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
++#define DCP5_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
++#define DCP5_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
++#define DCP5_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP5_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
++#define DCP5_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP5_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP5_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
++//DCP5_REGAMMA_CNTLB_START_CNTL
++#define DCP5_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x0
++#define DCP5_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14
++#define DCP5_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK 0x0003FFFFL
++#define DCP5_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
++//DCP5_REGAMMA_CNTLB_SLOPE_CNTL
++#define DCP5_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
++#define DCP5_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
++//DCP5_REGAMMA_CNTLB_END_CNTL1
++#define DCP5_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x0
++#define DCP5_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK 0x0000FFFFL
++//DCP5_REGAMMA_CNTLB_END_CNTL2
++#define DCP5_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0
++#define DCP5_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10
++#define DCP5_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
++#define DCP5_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xFFFF0000L
++//DCP5_REGAMMA_CNTLB_REGION_0_1
++#define DCP5_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
++#define DCP5_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
++#define DCP5_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
++#define DCP5_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP5_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
++#define DCP5_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP5_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP5_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
++//DCP5_REGAMMA_CNTLB_REGION_2_3
++#define DCP5_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
++#define DCP5_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
++#define DCP5_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
++#define DCP5_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP5_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
++#define DCP5_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP5_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP5_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
++//DCP5_REGAMMA_CNTLB_REGION_4_5
++#define DCP5_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
++#define DCP5_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
++#define DCP5_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
++#define DCP5_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP5_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
++#define DCP5_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP5_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP5_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
++//DCP5_REGAMMA_CNTLB_REGION_6_7
++#define DCP5_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
++#define DCP5_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
++#define DCP5_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
++#define DCP5_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP5_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
++#define DCP5_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP5_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP5_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
++//DCP5_REGAMMA_CNTLB_REGION_8_9
++#define DCP5_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
++#define DCP5_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
++#define DCP5_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
++#define DCP5_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP5_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
++#define DCP5_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP5_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP5_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
++//DCP5_REGAMMA_CNTLB_REGION_10_11
++#define DCP5_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
++#define DCP5_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
++#define DCP5_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
++#define DCP5_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP5_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
++#define DCP5_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP5_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP5_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
++//DCP5_REGAMMA_CNTLB_REGION_12_13
++#define DCP5_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
++#define DCP5_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
++#define DCP5_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
++#define DCP5_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP5_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
++#define DCP5_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP5_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP5_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
++//DCP5_REGAMMA_CNTLB_REGION_14_15
++#define DCP5_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
++#define DCP5_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
++#define DCP5_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
++#define DCP5_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
++#define DCP5_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
++#define DCP5_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
++#define DCP5_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
++#define DCP5_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
++//DCP5_ALPHA_CONTROL
++#define DCP5_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT 0x0
++#define DCP5_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT 0x1
++#define DCP5_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK 0x00000001L
++#define DCP5_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK 0x00000002L
++//DCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS
++#define DCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT 0x8
++#define DCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
++//DCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH
++#define DCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define DCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
++//DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS
++#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT 0x0
++#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT 0x18
++#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT 0x19
++#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT 0x1a
++#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT 0x1c
++#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT 0x1d
++#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT 0x1e
++#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK 0x000FFFFFL
++#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK 0x01000000L
++#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK 0x02000000L
++#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK 0x04000000L
++#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK 0x10000000L
++#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK 0x20000000L
++#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK 0x40000000L
++//DCP5_GRPH_XDMA_FLIP_TIMEOUT
++#define DCP5_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS__SHIFT 0x0
++#define DCP5_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK__SHIFT 0x1
++#define DCP5_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK__SHIFT 0x2
++#define DCP5_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS_MASK 0x00000001L
++#define DCP5_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK_MASK 0x00000002L
++#define DCP5_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK_MASK 0x00000004L
++//DCP5_GRPH_XDMA_FLIP_AVG_DELAY
++#define DCP5_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY__SHIFT 0x0
++#define DCP5_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD__SHIFT 0x10
++#define DCP5_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY_MASK 0x0000FFFFL
++#define DCP5_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD_MASK 0x00FF0000L
++//DCP5_GRPH_SURFACE_COUNTER_CONTROL
++#define DCP5_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN__SHIFT 0x0
++#define DCP5_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT__SHIFT 0x1
++#define DCP5_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED__SHIFT 0x9
++#define DCP5_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN_MASK 0x00000001L
++#define DCP5_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT_MASK 0x0000001EL
++#define DCP5_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_MASK 0x00000200L
++//DCP5_GRPH_SURFACE_COUNTER_OUTPUT
++#define DCP5_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN__SHIFT 0x0
++#define DCP5_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX__SHIFT 0x10
++#define DCP5_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN_MASK 0x0000FFFFL
++#define DCP5_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX_MASK 0xFFFF0000L
++
++
++// addressBlock: dce_dc_lb5_dispdec
++//LB5_LB_DATA_FORMAT
++#define LB5_LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0
++#define LB5_LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2
++#define LB5_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3
++#define LB5_LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4
++#define LB5_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5
++#define LB5_LB_DATA_FORMAT__PREFILL_EN__SHIFT 0x8
++#define LB5_LB_DATA_FORMAT__PREFETCH__SHIFT 0xc
++#define LB5_LB_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18
++#define LB5_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f
++#define LB5_LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x00000003L
++#define LB5_LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x00000004L
++#define LB5_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000008L
++#define LB5_LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x00000010L
++#define LB5_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x00000020L
++#define LB5_LB_DATA_FORMAT__PREFILL_EN_MASK 0x00000100L
++#define LB5_LB_DATA_FORMAT__PREFETCH_MASK 0x00001000L
++#define LB5_LB_DATA_FORMAT__REQUEST_MODE_MASK 0x01000000L
++#define LB5_LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000L
++//LB5_LB_MEMORY_CTRL
++#define LB5_LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0
++#define LB5_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
++#define LB5_LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14
++#define LB5_LB_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0x00001FFFL
++#define LB5_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x000F0000L
++#define LB5_LB_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x00300000L
++//LB5_LB_MEMORY_SIZE_STATUS
++#define LB5_LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0
++#define LB5_LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0x00001FFFL
++//LB5_LB_DESKTOP_HEIGHT
++#define LB5_LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0
++#define LB5_LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x00007FFFL
++//LB5_LB_VLINE_START_END
++#define LB5_LB_VLINE_START_END__VLINE_START__SHIFT 0x0
++#define LB5_LB_VLINE_START_END__VLINE_END__SHIFT 0x10
++#define LB5_LB_VLINE_START_END__VLINE_INV__SHIFT 0x1f
++#define LB5_LB_VLINE_START_END__VLINE_START_MASK 0x00003FFFL
++#define LB5_LB_VLINE_START_END__VLINE_END_MASK 0x7FFF0000L
++#define LB5_LB_VLINE_START_END__VLINE_INV_MASK 0x80000000L
++//LB5_LB_VLINE2_START_END
++#define LB5_LB_VLINE2_START_END__VLINE2_START__SHIFT 0x0
++#define LB5_LB_VLINE2_START_END__VLINE2_END__SHIFT 0x10
++#define LB5_LB_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f
++#define LB5_LB_VLINE2_START_END__VLINE2_START_MASK 0x00003FFFL
++#define LB5_LB_VLINE2_START_END__VLINE2_END_MASK 0x7FFF0000L
++#define LB5_LB_VLINE2_START_END__VLINE2_INV_MASK 0x80000000L
++//LB5_LB_V_COUNTER
++#define LB5_LB_V_COUNTER__V_COUNTER__SHIFT 0x0
++#define LB5_LB_V_COUNTER__V_COUNTER_MASK 0x00007FFFL
++//LB5_LB_SNAPSHOT_V_COUNTER
++#define LB5_LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0
++#define LB5_LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x00007FFFL
++//LB5_LB_INTERRUPT_MASK
++#define LB5_LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0
++#define LB5_LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4
++#define LB5_LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8
++#define LB5_LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x00000001L
++#define LB5_LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x00000010L
++#define LB5_LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x00000100L
++//LB5_LB_VLINE_STATUS
++#define LB5_LB_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0
++#define LB5_LB_VLINE_STATUS__VLINE_ACK__SHIFT 0x4
++#define LB5_LB_VLINE_STATUS__VLINE_STAT__SHIFT 0xc
++#define LB5_LB_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10
++#define LB5_LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11
++#define LB5_LB_VLINE_STATUS__VLINE_OCCURRED_MASK 0x00000001L
++#define LB5_LB_VLINE_STATUS__VLINE_ACK_MASK 0x00000010L
++#define LB5_LB_VLINE_STATUS__VLINE_STAT_MASK 0x00001000L
++#define LB5_LB_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x00010000L
++#define LB5_LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x00020000L
++//LB5_LB_VLINE2_STATUS
++#define LB5_LB_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0
++#define LB5_LB_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4
++#define LB5_LB_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc
++#define LB5_LB_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10
++#define LB5_LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11
++#define LB5_LB_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x00000001L
++#define LB5_LB_VLINE2_STATUS__VLINE2_ACK_MASK 0x00000010L
++#define LB5_LB_VLINE2_STATUS__VLINE2_STAT_MASK 0x00001000L
++#define LB5_LB_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x00010000L
++#define LB5_LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x00020000L
++//LB5_LB_VBLANK_STATUS
++#define LB5_LB_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0
++#define LB5_LB_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4
++#define LB5_LB_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc
++#define LB5_LB_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10
++#define LB5_LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11
++#define LB5_LB_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x00000001L
++#define LB5_LB_VBLANK_STATUS__VBLANK_ACK_MASK 0x00000010L
++#define LB5_LB_VBLANK_STATUS__VBLANK_STAT_MASK 0x00001000L
++#define LB5_LB_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x00010000L
++#define LB5_LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x00020000L
++//LB5_LB_SYNC_RESET_SEL
++#define LB5_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0
++#define LB5_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4
++#define LB5_LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8
++#define LB5_LB_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16
++#define LB5_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x00000003L
++#define LB5_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x00000010L
++#define LB5_LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0x0000FF00L
++#define LB5_LB_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0x00C00000L
++//LB5_LB_BLACK_KEYER_R_CR
++#define LB5_LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4
++#define LB5_LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0x0000FFF0L
++//LB5_LB_BLACK_KEYER_G_Y
++#define LB5_LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4
++#define LB5_LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0x0000FFF0L
++//LB5_LB_BLACK_KEYER_B_CB
++#define LB5_LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4
++#define LB5_LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0x0000FFF0L
++//LB5_LB_KEYER_COLOR_CTRL
++#define LB5_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0
++#define LB5_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8
++#define LB5_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x00000001L
++#define LB5_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x00000100L
++//LB5_LB_KEYER_COLOR_R_CR
++#define LB5_LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4
++#define LB5_LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0x0000FFF0L
++//LB5_LB_KEYER_COLOR_G_Y
++#define LB5_LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4
++#define LB5_LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0x0000FFF0L
++//LB5_LB_KEYER_COLOR_B_CB
++#define LB5_LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4
++#define LB5_LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0x0000FFF0L
++//LB5_LB_KEYER_COLOR_REP_R_CR
++#define LB5_LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4
++#define LB5_LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0x0000FFF0L
++//LB5_LB_KEYER_COLOR_REP_G_Y
++#define LB5_LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4
++#define LB5_LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0x0000FFF0L
++//LB5_LB_KEYER_COLOR_REP_B_CB
++#define LB5_LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4
++#define LB5_LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0x0000FFF0L
++//LB5_LB_BUFFER_LEVEL_STATUS
++#define LB5_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0
++#define LB5_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa
++#define LB5_LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10
++#define LB5_LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c
++#define LB5_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x0000003FL
++#define LB5_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0x0000FC00L
++#define LB5_LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0x0FFF0000L
++#define LB5_LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xF0000000L
++//LB5_LB_BUFFER_URGENCY_CTRL
++#define LB5_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0
++#define LB5_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10
++#define LB5_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0x00000FFFL
++#define LB5_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0x0FFF0000L
++//LB5_LB_BUFFER_URGENCY_STATUS
++#define LB5_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0
++#define LB5_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10
++#define LB5_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0x00000FFFL
++#define LB5_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x00010000L
++//LB5_LB_BUFFER_STATUS
++#define LB5_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0
++#define LB5_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4
++#define LB5_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8
++#define LB5_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc
++#define LB5_LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10
++#define LB5_LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14
++#define LB5_LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18
++#define LB5_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0x0000000FL
++#define LB5_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x00000010L
++#define LB5_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x00000100L
++#define LB5_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x00001000L
++#define LB5_LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x00010000L
++#define LB5_LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x00100000L
++#define LB5_LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x01000000L
++//LB5_LB_NO_OUTSTANDING_REQ_STATUS
++#define LB5_LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0
++#define LB5_LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x00000001L
++//LB5_MVP_AFR_FLIP_MODE
++#define LB5_MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT 0x0
++#define LB5_MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK 0x00000003L
++//LB5_MVP_AFR_FLIP_FIFO_CNTL
++#define LB5_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT 0x0
++#define LB5_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT 0x4
++#define LB5_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT 0x8
++#define LB5_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT 0xc
++#define LB5_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK 0x0000000FL
++#define LB5_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK 0x00000010L
++#define LB5_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK 0x00000100L
++#define LB5_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK 0x00001000L
++//LB5_MVP_FLIP_LINE_NUM_INSERT
++#define LB5_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT 0x0
++#define LB5_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT 0x8
++#define LB5_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT 0x18
++#define LB5_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT 0x1e
++#define LB5_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK 0x00000003L
++#define LB5_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK 0x007FFF00L
++#define LB5_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK 0x3F000000L
++#define LB5_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK 0x40000000L
++//LB5_DC_MVP_LB_CONTROL
++#define LB5_DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT 0x0
++#define LB5_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT 0x8
++#define LB5_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT 0xc
++#define LB5_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT 0x10
++#define LB5_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT 0x14
++#define LB5_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT 0x1c
++#define LB5_DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT 0x1f
++#define LB5_DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK 0x00000003L
++#define LB5_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK 0x00000100L
++#define LB5_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK 0x00001000L
++#define LB5_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK 0x00010000L
++#define LB5_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK 0x00100000L
++#define LB5_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK 0x10000000L
++#define LB5_DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK 0x80000000L
++
++
++// addressBlock: dce_dc_dcfe5_dispdec
++//DCFE5_DCFE_CLOCK_CONTROL
++#define DCFE5_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x4
++#define DCFE5_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x8
++#define DCFE5_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0xc
++#define DCFE5_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE__SHIFT 0xf
++#define DCFE5_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE__SHIFT 0x11
++#define DCFE5_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL__SHIFT 0x18
++#define DCFE5_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE__SHIFT 0x1f
++#define DCFE5_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x00000010L
++#define DCFE5_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE_MASK 0x00000100L
++#define DCFE5_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE_MASK 0x00001000L
++#define DCFE5_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE_MASK 0x00008000L
++#define DCFE5_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE_MASK 0x00020000L
++#define DCFE5_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL_MASK 0x1F000000L
++#define DCFE5_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE_MASK 0x80000000L
++//DCFE5_DCFE_SOFT_RESET
++#define DCFE5_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET__SHIFT 0x0
++#define DCFE5_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET__SHIFT 0x1
++#define DCFE5_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET__SHIFT 0x2
++#define DCFE5_DCFE_SOFT_RESET__SCL_SOFT_RESET__SHIFT 0x3
++#define DCFE5_DCFE_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4
++#define DCFE5_DCFE_SOFT_RESET__PSCL_SOFT_RESET__SHIFT 0x5
++#define DCFE5_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET_MASK 0x00000001L
++#define DCFE5_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET_MASK 0x00000002L
++#define DCFE5_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET_MASK 0x00000004L
++#define DCFE5_DCFE_SOFT_RESET__SCL_SOFT_RESET_MASK 0x00000008L
++#define DCFE5_DCFE_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x00000010L
++#define DCFE5_DCFE_SOFT_RESET__PSCL_SOFT_RESET_MASK 0x00000020L
++//DCFE5_DCFE_MEM_PWR_CTRL
++#define DCFE5_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE__SHIFT 0x0
++#define DCFE5_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS__SHIFT 0x2
++#define DCFE5_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE__SHIFT 0x3
++#define DCFE5_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS__SHIFT 0x5
++#define DCFE5_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE__SHIFT 0x6
++#define DCFE5_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS__SHIFT 0x8
++#define DCFE5_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE__SHIFT 0x9
++#define DCFE5_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS__SHIFT 0xb
++#define DCFE5_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE__SHIFT 0xc
++#define DCFE5_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS__SHIFT 0xe
++#define DCFE5_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE__SHIFT 0xf
++#define DCFE5_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS__SHIFT 0x11
++#define DCFE5_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE__SHIFT 0x12
++#define DCFE5_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS__SHIFT 0x14
++#define DCFE5_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE__SHIFT 0x15
++#define DCFE5_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS__SHIFT 0x17
++#define DCFE5_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE__SHIFT 0x18
++#define DCFE5_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS__SHIFT 0x1a
++#define DCFE5_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE__SHIFT 0x1b
++#define DCFE5_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS__SHIFT 0x1d
++#define DCFE5_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE_MASK 0x00000003L
++#define DCFE5_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS_MASK 0x00000004L
++#define DCFE5_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE_MASK 0x00000018L
++#define DCFE5_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS_MASK 0x00000020L
++#define DCFE5_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE_MASK 0x000000C0L
++#define DCFE5_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS_MASK 0x00000100L
++#define DCFE5_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE_MASK 0x00000600L
++#define DCFE5_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS_MASK 0x00000800L
++#define DCFE5_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE_MASK 0x00003000L
++#define DCFE5_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS_MASK 0x00004000L
++#define DCFE5_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE_MASK 0x00018000L
++#define DCFE5_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK 0x00020000L
++#define DCFE5_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE_MASK 0x000C0000L
++#define DCFE5_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS_MASK 0x00100000L
++#define DCFE5_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE_MASK 0x00600000L
++#define DCFE5_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS_MASK 0x00800000L
++#define DCFE5_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE_MASK 0x03000000L
++#define DCFE5_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS_MASK 0x04000000L
++#define DCFE5_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE_MASK 0x18000000L
++#define DCFE5_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS_MASK 0x20000000L
++//DCFE5_DCFE_MEM_PWR_CTRL2
++#define DCFE5_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL__SHIFT 0x0
++#define DCFE5_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2
++#define DCFE5_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4
++#define DCFE5_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL__SHIFT 0x6
++#define DCFE5_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL__SHIFT 0x8
++#define DCFE5_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL__SHIFT 0xa
++#define DCFE5_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL__SHIFT 0xc
++#define DCFE5_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL__SHIFT 0xe
++#define DCFE5_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE__SHIFT 0x10
++#define DCFE5_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS__SHIFT 0x12
++#define DCFE5_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE__SHIFT 0x15
++#define DCFE5_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS__SHIFT 0x17
++#define DCFE5_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL_MASK 0x00000003L
++#define DCFE5_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL_MASK 0x0000000CL
++#define DCFE5_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL_MASK 0x00000030L
++#define DCFE5_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL_MASK 0x000000C0L
++#define DCFE5_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL_MASK 0x00000300L
++#define DCFE5_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL_MASK 0x00000C00L
++#define DCFE5_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL_MASK 0x00003000L
++#define DCFE5_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL_MASK 0x0000C000L
++#define DCFE5_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE_MASK 0x00030000L
++#define DCFE5_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS_MASK 0x00040000L
++#define DCFE5_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE_MASK 0x00600000L
++#define DCFE5_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS_MASK 0x00800000L
++//DCFE5_DCFE_MEM_PWR_STATUS
++#define DCFE5_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE__SHIFT 0x0
++#define DCFE5_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE__SHIFT 0x2
++#define DCFE5_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE__SHIFT 0x4
++#define DCFE5_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x6
++#define DCFE5_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE__SHIFT 0x8
++#define DCFE5_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE__SHIFT 0xa
++#define DCFE5_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE__SHIFT 0xc
++#define DCFE5_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE__SHIFT 0xe
++#define DCFE5_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT 0x10
++#define DCFE5_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE__SHIFT 0x12
++#define DCFE5_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE__SHIFT 0x14
++#define DCFE5_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE__SHIFT 0x16
++#define DCFE5_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK 0x00000003L
++#define DCFE5_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE_MASK 0x0000000CL
++#define DCFE5_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE_MASK 0x00000030L
++#define DCFE5_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE_MASK 0x000000C0L
++#define DCFE5_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE_MASK 0x00000300L
++#define DCFE5_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE_MASK 0x00000C00L
++#define DCFE5_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE_MASK 0x00003000L
++#define DCFE5_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE_MASK 0x0000C000L
++#define DCFE5_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE_MASK 0x00030000L
++#define DCFE5_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK 0x000C0000L
++#define DCFE5_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE_MASK 0x00300000L
++#define DCFE5_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE_MASK 0x00C00000L
++//DCFE5_DCFE_MISC
++#define DCFE5_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN__SHIFT 0x0
++#define DCFE5_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN_MASK 0x00000001L
++//DCFE5_DCFE_FLUSH
++#define DCFE5_DCFE_FLUSH__FLUSH_OCCURED__SHIFT 0x0
++#define DCFE5_DCFE_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT 0x1
++#define DCFE5_DCFE_FLUSH__FLUSH_DEEP__SHIFT 0x2
++#define DCFE5_DCFE_FLUSH__CLEAR_FLUSH_DEEP__SHIFT 0x3
++#define DCFE5_DCFE_FLUSH__ALL_MC_REQ_RET__SHIFT 0x4
++#define DCFE5_DCFE_FLUSH__FLUSH_OCCURED_MASK 0x00000001L
++#define DCFE5_DCFE_FLUSH__CLEAR_FLUSH_OCCURED_MASK 0x00000002L
++#define DCFE5_DCFE_FLUSH__FLUSH_DEEP_MASK 0x00000004L
++#define DCFE5_DCFE_FLUSH__CLEAR_FLUSH_DEEP_MASK 0x00000008L
++#define DCFE5_DCFE_FLUSH__ALL_MC_REQ_RET_MASK 0x00000010L
++
++
++// addressBlock: dce_dc_dc_perfmon8_dispdec
++//DC_PERFMON8_PERFCOUNTER_CNTL
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
++//DC_PERFMON8_PERFCOUNTER_CNTL2
++#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
++#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
++#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
++#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
++#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
++#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
++#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
++#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
++//DC_PERFMON8_PERFCOUNTER_STATE
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
++//DC_PERFMON8_PERFMON_CNTL
++#define DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
++#define DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
++#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
++#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
++#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
++#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
++#define DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
++#define DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
++#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
++#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
++#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
++#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
++//DC_PERFMON8_PERFMON_CNTL2
++#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
++#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
++#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
++#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
++#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
++#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
++#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
++#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
++//DC_PERFMON8_PERFMON_CVALUE_INT_MISC
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
++//DC_PERFMON8_PERFMON_CVALUE_LOW
++#define DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
++#define DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
++//DC_PERFMON8_PERFMON_HI
++#define DC_PERFMON8_PERFMON_HI__PERFMON_HI__SHIFT 0x0
++#define DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
++#define DC_PERFMON8_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
++#define DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
++//DC_PERFMON8_PERFMON_LOW
++#define DC_PERFMON8_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
++#define DC_PERFMON8_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dmif_pg5_dispdec
++//DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1
++#define DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
++#define DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
++#define DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0x0000FFFFL
++#define DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xFFFF0000L
++//DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2
++#define DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
++#define DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
++#define DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0x0000FFFFL
++#define DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xFFFF0000L
++//DMIF_PG5_DPG_WATERMARK_MASK_CONTROL
++#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
++#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x4
++#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
++#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK__SHIFT 0xc
++#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0xf
++#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x12
++#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL__SHIFT 0x13
++#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL__SHIFT 0x14
++#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000007L
++#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000070L
++#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x00000700L
++#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK_MASK 0x00007000L
++#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00038000L
++#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x00040000L
++#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL_MASK 0x00080000L
++#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL_MASK 0x3FF00000L
++//DMIF_PG5_DPG_PIPE_URGENCY_CONTROL
++#define DMIF_PG5_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
++#define DMIF_PG5_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
++#define DMIF_PG5_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0x0000FFFFL
++#define DMIF_PG5_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xFFFF0000L
++//DMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL
++#define DMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK__SHIFT 0x0
++#define DMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK__SHIFT 0x10
++#define DMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK_MASK 0x0000FFFFL
++#define DMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK_MASK 0xFFFF0000L
++//DMIF_PG5_DPG_PIPE_STUTTER_CONTROL
++#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
++#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
++#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
++#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
++#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
++#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
++#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
++#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH__SHIFT 0x10
++#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x14
++#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x15
++#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x16
++#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x17
++#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0x1a
++#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0x1b
++#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L
++#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L
++#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x00000020L
++#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x00000040L
++#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x00000080L
++#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x00000400L
++#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x00000800L
++#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH_MASK 0x00010000L
++#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x00100000L
++#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x00200000L
++#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x00400000L
++#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x00800000L
++#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x04000000L
++#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x08000000L
++//DMIF_PG5_DPG_PIPE_STUTTER_CONTROL2
++#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x0
++#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK__SHIFT 0x10
++#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0x0000FFFFL
++#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK 0xFFFF0000L
++//DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL
++#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE__SHIFT 0x0
++#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE__SHIFT 0x1
++#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
++#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
++#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
++#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
++#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK__SHIFT 0xf
++#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE_MASK 0x00000001L
++#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE_MASK 0x00000002L
++#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L
++#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x00000100L
++#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON_MASK 0x00000200L
++#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT_MASK 0x00000400L
++#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK_MASK 0xFFFF8000L
++//DMIF_PG5_DPG_REPEATER_PROGRAM
++#define DMIF_PG5_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
++#define DMIF_PG5_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
++#define DMIF_PG5_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x00000007L
++#define DMIF_PG5_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x00000070L
++//DMIF_PG5_DPG_CHK_PRE_PROC_CNTL
++#define DMIF_PG5_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0
++#define DMIF_PG5_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x00000001L
++//DMIF_PG5_DPG_DVMM_STATUS
++#define DMIF_PG5_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED__SHIFT 0x0
++#define DMIF_PG5_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED__SHIFT 0x1
++#define DMIF_PG5_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR__SHIFT 0x4
++#define DMIF_PG5_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR__SHIFT 0x5
++#define DMIF_PG5_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_MASK 0x00000001L
++#define DMIF_PG5_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_MASK 0x00000002L
++#define DMIF_PG5_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR_MASK 0x00000010L
++#define DMIF_PG5_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR_MASK 0x00000020L
++
++
++// addressBlock: dce_dc_scl5_dispdec
++//SCL5_SCL_COEF_RAM_SELECT
++#define SCL5_SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0
++#define SCL5_SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8
++#define SCL5_SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10
++#define SCL5_SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x0000000FL
++#define SCL5_SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x00000F00L
++#define SCL5_SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x00070000L
++//SCL5_SCL_COEF_RAM_TAP_DATA
++#define SCL5_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0
++#define SCL5_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
++#define SCL5_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10
++#define SCL5_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
++#define SCL5_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL
++#define SCL5_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L
++#define SCL5_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L
++#define SCL5_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L
++//SCL5_SCL_MODE
++#define SCL5_SCL_MODE__SCL_MODE__SHIFT 0x0
++#define SCL5_SCL_MODE__SCL_PSCL_EN__SHIFT 0x4
++#define SCL5_SCL_MODE__SCL_MODE_MASK 0x00000003L
++#define SCL5_SCL_MODE__SCL_PSCL_EN_MASK 0x00000010L
++//SCL5_SCL_TAP_CONTROL
++#define SCL5_SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0
++#define SCL5_SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x8
++#define SCL5_SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x00000007L
++#define SCL5_SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0x00000F00L
++//SCL5_SCL_CONTROL
++#define SCL5_SCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
++#define SCL5_SCL_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4
++#define SCL5_SCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L
++#define SCL5_SCL_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x00000010L
++//SCL5_SCL_BYPASS_CONTROL
++#define SCL5_SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT 0x0
++#define SCL5_SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x00000003L
++//SCL5_SCL_MANUAL_REPLICATE_CONTROL
++#define SCL5_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
++#define SCL5_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
++#define SCL5_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL
++#define SCL5_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L
++//SCL5_SCL_AUTOMATIC_MODE_CONTROL
++#define SCL5_SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0
++#define SCL5_SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10
++#define SCL5_SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x00000001L
++#define SCL5_SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x00010000L
++//SCL5_SCL_HORZ_FILTER_CONTROL
++#define SCL5_SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT 0x0
++#define SCL5_SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
++#define SCL5_SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK 0x00000001L
++#define SCL5_SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
++//SCL5_SCL_HORZ_FILTER_SCALE_RATIO
++#define SCL5_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
++#define SCL5_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL
++//SCL5_SCL_HORZ_FILTER_INIT
++#define SCL5_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
++#define SCL5_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
++#define SCL5_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL
++#define SCL5_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L
++//SCL5_SCL_VERT_FILTER_CONTROL
++#define SCL5_SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT 0x0
++#define SCL5_SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
++#define SCL5_SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK 0x00000001L
++#define SCL5_SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
++//SCL5_SCL_VERT_FILTER_SCALE_RATIO
++#define SCL5_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
++#define SCL5_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL
++//SCL5_SCL_VERT_FILTER_INIT
++#define SCL5_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
++#define SCL5_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
++#define SCL5_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL
++#define SCL5_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x07000000L
++//SCL5_SCL_VERT_FILTER_INIT_BOT
++#define SCL5_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
++#define SCL5_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
++#define SCL5_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL
++#define SCL5_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x07000000L
++//SCL5_SCL_ROUND_OFFSET
++#define SCL5_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0
++#define SCL5_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10
++#define SCL5_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0x0000FFFFL
++#define SCL5_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xFFFF0000L
++//SCL5_SCL_UPDATE
++#define SCL5_SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
++#define SCL5_SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8
++#define SCL5_SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10
++#define SCL5_SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18
++#define SCL5_SCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L
++#define SCL5_SCL_UPDATE__SCL_UPDATE_TAKEN_MASK 0x00000100L
++#define SCL5_SCL_UPDATE__SCL_UPDATE_LOCK_MASK 0x00010000L
++#define SCL5_SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x01000000L
++//SCL5_SCL_F_SHARP_CONTROL
++#define SCL5_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT 0x0
++#define SCL5_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT 0x4
++#define SCL5_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT 0x8
++#define SCL5_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT 0xc
++#define SCL5_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK 0x00000007L
++#define SCL5_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK 0x00000010L
++#define SCL5_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK 0x00000700L
++#define SCL5_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK 0x00001000L
++//SCL5_SCL_ALU_CONTROL
++#define SCL5_SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0
++#define SCL5_SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x00000001L
++//SCL5_SCL_COEF_RAM_CONFLICT_STATUS
++#define SCL5_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT 0x0
++#define SCL5_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT 0x8
++#define SCL5_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT 0xc
++#define SCL5_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10
++#define SCL5_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK 0x00000001L
++#define SCL5_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK 0x00000100L
++#define SCL5_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK 0x00001000L
++#define SCL5_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK 0x00010000L
++//SCL5_VIEWPORT_START_SECONDARY
++#define SCL5_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0
++#define SCL5_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10
++#define SCL5_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x00003FFFL
++#define SCL5_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3FFF0000L
++//SCL5_VIEWPORT_START
++#define SCL5_VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0
++#define SCL5_VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10
++#define SCL5_VIEWPORT_START__VIEWPORT_Y_START_MASK 0x00003FFFL
++#define SCL5_VIEWPORT_START__VIEWPORT_X_START_MASK 0x3FFF0000L
++//SCL5_VIEWPORT_SIZE
++#define SCL5_VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0
++#define SCL5_VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10
++#define SCL5_VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x00003FFFL
++#define SCL5_VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x3FFF0000L
++//SCL5_EXT_OVERSCAN_LEFT_RIGHT
++#define SCL5_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
++#define SCL5_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
++#define SCL5_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL
++#define SCL5_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L
++//SCL5_EXT_OVERSCAN_TOP_BOTTOM
++#define SCL5_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
++#define SCL5_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
++#define SCL5_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL
++#define SCL5_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L
++//SCL5_SCL_MODE_CHANGE_DET1
++#define SCL5_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0
++#define SCL5_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4
++#define SCL5_SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7
++#define SCL5_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x00000001L
++#define SCL5_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x00000010L
++#define SCL5_SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0x0FFFFF80L
++//SCL5_SCL_MODE_CHANGE_DET2
++#define SCL5_SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0
++#define SCL5_SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x001FFFFFL
++//SCL5_SCL_MODE_CHANGE_DET3
++#define SCL5_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0
++#define SCL5_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10
++#define SCL5_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x00003FFFL
++#define SCL5_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3FFF0000L
++//SCL5_SCL_MODE_CHANGE_MASK
++#define SCL5_SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0
++#define SCL5_SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x00000001L
++
++
++// addressBlock: dce_dc_blnd5_dispdec
++//BLND5_BLND_CONTROL
++#define BLND5_BLND_CONTROL__BLND_GLOBAL_GAIN__SHIFT 0x0
++#define BLND5_BLND_CONTROL__BLND_MODE__SHIFT 0x8
++#define BLND5_BLND_CONTROL__BLND_STEREO_TYPE__SHIFT 0xa
++#define BLND5_BLND_CONTROL__BLND_STEREO_POLARITY__SHIFT 0xc
++#define BLND5_BLND_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT 0xd
++#define BLND5_BLND_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10
++#define BLND5_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x12
++#define BLND5_BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14
++#define BLND5_BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18
++#define BLND5_BLND_CONTROL__BLND_GLOBAL_GAIN_MASK 0x000000FFL
++#define BLND5_BLND_CONTROL__BLND_MODE_MASK 0x00000300L
++#define BLND5_BLND_CONTROL__BLND_STEREO_TYPE_MASK 0x00000C00L
++#define BLND5_BLND_CONTROL__BLND_STEREO_POLARITY_MASK 0x00001000L
++#define BLND5_BLND_CONTROL__BLND_FEEDTHROUGH_EN_MASK 0x00002000L
++#define BLND5_BLND_CONTROL__BLND_ALPHA_MODE_MASK 0x00030000L
++#define BLND5_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00040000L
++#define BLND5_BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x00100000L
++#define BLND5_BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xFF000000L
++//BLND5_BLND_SM_CONTROL2
++#define BLND5_BLND_SM_CONTROL2__SM_MODE__SHIFT 0x0
++#define BLND5_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4
++#define BLND5_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5
++#define BLND5_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
++#define BLND5_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
++#define BLND5_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18
++#define BLND5_BLND_SM_CONTROL2__SM_MODE_MASK 0x00000007L
++#define BLND5_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x00000010L
++#define BLND5_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x00000020L
++#define BLND5_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L
++#define BLND5_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L
++#define BLND5_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x01000000L
++//BLND5_BLND_CONTROL2
++#define BLND5_BLND_CONTROL2__PTI_ENABLE__SHIFT 0x0
++#define BLND5_BLND_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT 0x4
++#define BLND5_BLND_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT 0x6
++#define BLND5_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT 0x7
++#define BLND5_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT 0x8
++#define BLND5_BLND_CONTROL2__PTI_ENABLE_MASK 0x00000001L
++#define BLND5_BLND_CONTROL2__PTI_NEW_PIXEL_GAP_MASK 0x00000030L
++#define BLND5_BLND_CONTROL2__BLND_NEW_PIXEL_MODE_MASK 0x00000040L
++#define BLND5_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK 0x00000080L
++#define BLND5_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK 0x00000100L
++//BLND5_BLND_UPDATE
++#define BLND5_BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0
++#define BLND5_BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8
++#define BLND5_BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10
++#define BLND5_BLND_UPDATE__BLND_UPDATE_PENDING_MASK 0x00000001L
++#define BLND5_BLND_UPDATE__BLND_UPDATE_TAKEN_MASK 0x00000100L
++#define BLND5_BLND_UPDATE__BLND_UPDATE_LOCK_MASK 0x00010000L
++//BLND5_BLND_UNDERFLOW_INTERRUPT
++#define BLND5_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0
++#define BLND5_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8
++#define BLND5_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc
++#define BLND5_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10
++#define BLND5_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x00000001L
++#define BLND5_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x00000100L
++#define BLND5_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x00001000L
++#define BLND5_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x00030000L
++//BLND5_BLND_V_UPDATE_LOCK
++#define BLND5_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0
++#define BLND5_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1
++#define BLND5_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10
++#define BLND5_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c
++#define BLND5_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT 0x1d
++#define BLND5_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT 0x1f
++#define BLND5_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x00000001L
++#define BLND5_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x00000002L
++#define BLND5_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x00010000L
++#define BLND5_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000L
++#define BLND5_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK 0x20000000L
++#define BLND5_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK 0x80000000L
++//BLND5_BLND_REG_UPDATE_STATUS
++#define BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT 0x0
++#define BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT 0x1
++#define BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2
++#define BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3
++#define BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT 0x6
++#define BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT 0x7
++#define BLND5_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT 0x8
++#define BLND5_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT 0x9
++#define BLND5_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT 0xa
++#define BLND5_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT 0xb
++#define BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK 0x00000001L
++#define BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK 0x00000002L
++#define BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK 0x00000004L
++#define BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK 0x00000008L
++#define BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK 0x00000040L
++#define BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK 0x00000080L
++#define BLND5_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK 0x00000100L
++#define BLND5_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK 0x00000200L
++#define BLND5_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK 0x00000400L
++#define BLND5_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK 0x00000800L
++
++
++// addressBlock: dce_dc_crtc5_dispdec
++//CRTC5_CRTC_H_BLANK_EARLY_NUM
++#define CRTC5_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0
++#define CRTC5_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10
++#define CRTC5_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x000003FFL
++#define CRTC5_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x00010000L
++//CRTC5_CRTC_H_TOTAL
++#define CRTC5_CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0
++#define CRTC5_CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x00003FFFL
++//CRTC5_CRTC_H_BLANK_START_END
++#define CRTC5_CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0
++#define CRTC5_CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10
++#define CRTC5_CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x00003FFFL
++#define CRTC5_CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3FFF0000L
++//CRTC5_CRTC_H_SYNC_A
++#define CRTC5_CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0
++#define CRTC5_CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10
++#define CRTC5_CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x00003FFFL
++#define CRTC5_CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3FFF0000L
++//CRTC5_CRTC_H_SYNC_A_CNTL
++#define CRTC5_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0
++#define CRTC5_CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10
++#define CRTC5_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11
++#define CRTC5_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x00000001L
++#define CRTC5_CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x00010000L
++#define CRTC5_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x00020000L
++//CRTC5_CRTC_H_SYNC_B
++#define CRTC5_CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0
++#define CRTC5_CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10
++#define CRTC5_CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x00003FFFL
++#define CRTC5_CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x3FFF0000L
++//CRTC5_CRTC_H_SYNC_B_CNTL
++#define CRTC5_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0
++#define CRTC5_CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10
++#define CRTC5_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11
++#define CRTC5_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x00000001L
++#define CRTC5_CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x00010000L
++#define CRTC5_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x00020000L
++//CRTC5_CRTC_VBI_END
++#define CRTC5_CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x0
++#define CRTC5_CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x10
++#define CRTC5_CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x00003FFFL
++#define CRTC5_CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x3FFF0000L
++//CRTC5_CRTC_V_TOTAL
++#define CRTC5_CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0
++#define CRTC5_CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x00003FFFL
++//CRTC5_CRTC_V_TOTAL_MIN
++#define CRTC5_CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0
++#define CRTC5_CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x00003FFFL
++//CRTC5_CRTC_V_TOTAL_MAX
++#define CRTC5_CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0
++#define CRTC5_CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10
++#define CRTC5_CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x00003FFFL
++#define CRTC5_CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x00010000L
++//CRTC5_CRTC_V_TOTAL_CONTROL
++#define CRTC5_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0
++#define CRTC5_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4
++#define CRTC5_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8
++#define CRTC5_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc
++#define CRTC5_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf
++#define CRTC5_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10
++#define CRTC5_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x00000001L
++#define CRTC5_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x00000010L
++#define CRTC5_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x00000100L
++#define CRTC5_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x00001000L
++#define CRTC5_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00008000L
++#define CRTC5_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L
++//CRTC5_CRTC_V_TOTAL_INT_STATUS
++#define CRTC5_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0
++#define CRTC5_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4
++#define CRTC5_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8
++#define CRTC5_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc
++#define CRTC5_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L
++#define CRTC5_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L
++#define CRTC5_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L
++#define CRTC5_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L
++//CRTC5_CRTC_VSYNC_NOM_INT_STATUS
++#define CRTC5_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0
++#define CRTC5_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4
++#define CRTC5_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x00000001L
++#define CRTC5_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L
++//CRTC5_CRTC_V_BLANK_START_END
++#define CRTC5_CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0
++#define CRTC5_CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10
++#define CRTC5_CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x00003FFFL
++#define CRTC5_CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3FFF0000L
++//CRTC5_CRTC_V_SYNC_A
++#define CRTC5_CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0
++#define CRTC5_CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10
++#define CRTC5_CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x00003FFFL
++#define CRTC5_CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3FFF0000L
++//CRTC5_CRTC_V_SYNC_A_CNTL
++#define CRTC5_CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0
++#define CRTC5_CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x00000001L
++//CRTC5_CRTC_V_SYNC_B
++#define CRTC5_CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0
++#define CRTC5_CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10
++#define CRTC5_CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x00003FFFL
++#define CRTC5_CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x3FFF0000L
++//CRTC5_CRTC_V_SYNC_B_CNTL
++#define CRTC5_CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0
++#define CRTC5_CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x00000001L
++//CRTC5_CRTC_DTMTEST_CNTL
++#define CRTC5_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0
++#define CRTC5_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1
++#define CRTC5_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x00000001L
++#define CRTC5_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x0000001EL
++//CRTC5_CRTC_DTMTEST_STATUS_POSITION
++#define CRTC5_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0
++#define CRTC5_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10
++#define CRTC5_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x00003FFFL
++#define CRTC5_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x3FFF0000L
++//CRTC5_CRTC_TRIGA_CNTL
++#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0
++#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5
++#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8
++#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9
++#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa
++#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb
++#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
++#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
++#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14
++#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18
++#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f
++#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x0000001FL
++#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0x000000E0L
++#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000100L
++#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x00000200L
++#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x00000400L
++#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x00000800L
++#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
++#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
++#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L
++#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1F000000L
++#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000L
++//CRTC5_CRTC_TRIGA_MANUAL_TRIG
++#define CRTC5_CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0
++#define CRTC5_CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x00000001L
++//CRTC5_CRTC_TRIGB_CNTL
++#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0
++#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5
++#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8
++#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9
++#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa
++#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb
++#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
++#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
++#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14
++#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18
++#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f
++#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x0000001FL
++#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0x000000E0L
++#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000100L
++#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x00000200L
++#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x00000400L
++#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x00000800L
++#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
++#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
++#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L
++#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1F000000L
++#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000L
++//CRTC5_CRTC_TRIGB_MANUAL_TRIG
++#define CRTC5_CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0
++#define CRTC5_CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x00000001L
++//CRTC5_CRTC_FORCE_COUNT_NOW_CNTL
++#define CRTC5_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0
++#define CRTC5_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4
++#define CRTC5_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8
++#define CRTC5_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10
++#define CRTC5_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18
++#define CRTC5_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x00000003L
++#define CRTC5_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L
++#define CRTC5_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L
++#define CRTC5_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L
++#define CRTC5_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L
++//CRTC5_CRTC_FLOW_CONTROL
++#define CRTC5_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0
++#define CRTC5_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8
++#define CRTC5_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10
++#define CRTC5_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18
++#define CRTC5_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL
++#define CRTC5_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x00000100L
++#define CRTC5_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L
++#define CRTC5_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L
++//CRTC5_CRTC_STEREO_FORCE_NEXT_EYE
++#define CRTC5_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0
++#define CRTC5_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER__SHIFT 0x8
++#define CRTC5_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER__SHIFT 0x10
++#define CRTC5_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L
++#define CRTC5_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L
++#define CRTC5_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L
++//CRTC5_CRTC_AVSYNC_COUNTER
++#define CRTC5_CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER__SHIFT 0x0
++#define CRTC5_CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER_MASK 0xFFFFFFFFL
++//CRTC5_CRTC_CONTROL
++#define CRTC5_CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x0
++#define CRTC5_CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4
++#define CRTC5_CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8
++#define CRTC5_CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc
++#define CRTC5_CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd
++#define CRTC5_CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe
++#define CRTC5_CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10
++#define CRTC5_CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14
++#define CRTC5_CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d
++#define CRTC5_CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e
++#define CRTC5_CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f
++#define CRTC5_CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x00000001L
++#define CRTC5_CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x00000010L
++#define CRTC5_CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x00000300L
++#define CRTC5_CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x00001000L
++#define CRTC5_CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x00002000L
++#define CRTC5_CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x00004000L
++#define CRTC5_CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x00010000L
++#define CRTC5_CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x00700000L
++#define CRTC5_CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000L
++#define CRTC5_CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L
++#define CRTC5_CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L
++//CRTC5_CRTC_BLANK_CONTROL
++#define CRTC5_CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0
++#define CRTC5_CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8
++#define CRTC5_CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10
++#define CRTC5_CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x00000001L
++#define CRTC5_CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x00000100L
++#define CRTC5_CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x00010000L
++//CRTC5_CRTC_INTERLACE_CONTROL
++#define CRTC5_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0
++#define CRTC5_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10
++#define CRTC5_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x00000001L
++#define CRTC5_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L
++//CRTC5_CRTC_INTERLACE_STATUS
++#define CRTC5_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0
++#define CRTC5_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1
++#define CRTC5_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x00000001L
++#define CRTC5_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x00000002L
++//CRTC5_CRTC_FIELD_INDICATION_CONTROL
++#define CRTC5_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0
++#define CRTC5_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1
++#define CRTC5_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x00000001L
++#define CRTC5_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x00000002L
++//CRTC5_CRTC_PIXEL_DATA_READBACK0
++#define CRTC5_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0
++#define CRTC5_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10
++#define CRTC5_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0x00000FFFL
++#define CRTC5_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0x0FFF0000L
++//CRTC5_CRTC_PIXEL_DATA_READBACK1
++#define CRTC5_CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0
++#define CRTC5_CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0x00000FFFL
++//CRTC5_CRTC_STATUS
++#define CRTC5_CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x0
++#define CRTC5_CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1
++#define CRTC5_CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x2
++#define CRTC5_CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x3
++#define CRTC5_CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x4
++#define CRTC5_CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5
++#define CRTC5_CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x10
++#define CRTC5_CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11
++#define CRTC5_CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x12
++#define CRTC5_CRTC_STATUS__CRTC_V_BLANK_MASK 0x00000001L
++#define CRTC5_CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x00000002L
++#define CRTC5_CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x00000004L
++#define CRTC5_CRTC_STATUS__CRTC_V_UPDATE_MASK 0x00000008L
++#define CRTC5_CRTC_STATUS__CRTC_V_START_LINE_MASK 0x00000010L
++#define CRTC5_CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x00000020L
++#define CRTC5_CRTC_STATUS__CRTC_H_BLANK_MASK 0x00010000L
++#define CRTC5_CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x00020000L
++#define CRTC5_CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x00040000L
++//CRTC5_CRTC_STATUS_POSITION
++#define CRTC5_CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0
++#define CRTC5_CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10
++#define CRTC5_CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x00003FFFL
++#define CRTC5_CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x3FFF0000L
++//CRTC5_CRTC_NOM_VERT_POSITION
++#define CRTC5_CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0
++#define CRTC5_CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x00003FFFL
++//CRTC5_CRTC_STATUS_FRAME_COUNT
++#define CRTC5_CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0
++#define CRTC5_CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0x00FFFFFFL
++//CRTC5_CRTC_STATUS_VF_COUNT
++#define CRTC5_CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0
++#define CRTC5_CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x3FFFFFFFL
++//CRTC5_CRTC_STATUS_HV_COUNT
++#define CRTC5_CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0
++#define CRTC5_CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x3FFFFFFFL
++//CRTC5_CRTC_COUNT_CONTROL
++#define CRTC5_CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0
++#define CRTC5_CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1
++#define CRTC5_CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x00000001L
++#define CRTC5_CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x0000001EL
++//CRTC5_CRTC_COUNT_RESET
++#define CRTC5_CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0
++#define CRTC5_CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x00000001L
++//CRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE
++#define CRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0
++#define CRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L
++//CRTC5_CRTC_VERT_SYNC_CONTROL
++#define CRTC5_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0
++#define CRTC5_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8
++#define CRTC5_CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10
++#define CRTC5_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L
++#define CRTC5_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L
++#define CRTC5_CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L
++//CRTC5_CRTC_STEREO_STATUS
++#define CRTC5_CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0
++#define CRTC5_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8
++#define CRTC5_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10
++#define CRTC5_CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG__SHIFT 0x14
++#define CRTC5_CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18
++#define CRTC5_CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x00000001L
++#define CRTC5_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x00000100L
++#define CRTC5_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x00010000L
++#define CRTC5_CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG_MASK 0x00100000L
++#define CRTC5_CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L
++//CRTC5_CRTC_STEREO_CONTROL
++#define CRTC5_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0
++#define CRTC5_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf
++#define CRTC5_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10
++#define CRTC5_CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11
++#define CRTC5_CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12
++#define CRTC5_CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM__SHIFT 0x13
++#define CRTC5_CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14
++#define CRTC5_CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18
++#define CRTC5_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00003FFFL
++#define CRTC5_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L
++#define CRTC5_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x00010000L
++#define CRTC5_CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L
++#define CRTC5_CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L
++#define CRTC5_CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM_MASK 0x00080000L
++#define CRTC5_CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L
++#define CRTC5_CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x01000000L
++//CRTC5_CRTC_SNAPSHOT_STATUS
++#define CRTC5_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0
++#define CRTC5_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1
++#define CRTC5_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2
++#define CRTC5_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x00000001L
++#define CRTC5_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x00000002L
++#define CRTC5_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L
++//CRTC5_CRTC_SNAPSHOT_CONTROL
++#define CRTC5_CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0
++#define CRTC5_CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L
++//CRTC5_CRTC_SNAPSHOT_POSITION
++#define CRTC5_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0
++#define CRTC5_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10
++#define CRTC5_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x00003FFFL
++#define CRTC5_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x3FFF0000L
++//CRTC5_CRTC_SNAPSHOT_FRAME
++#define CRTC5_CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0
++#define CRTC5_CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL
++//CRTC5_CRTC_START_LINE_CONTROL
++#define CRTC5_CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0
++#define CRTC5_CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x1
++#define CRTC5_CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x2
++#define CRTC5_CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x8
++#define CRTC5_CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc
++#define CRTC5_CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x00000001L
++#define CRTC5_CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x00000002L
++#define CRTC5_CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x00000004L
++#define CRTC5_CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x00000100L
++#define CRTC5_CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0x000FF000L
++//CRTC5_CRTC_INTERRUPT_CONTROL
++#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0
++#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1
++#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4
++#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5
++#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8
++#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9
++#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10
++#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11
++#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18
++#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19
++#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a
++#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b
++#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c
++#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d
++#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e
++#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f
++#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x00000001L
++#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x00000002L
++#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x00000010L
++#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x00000020L
++#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L
++#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L
++#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L
++#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L
++#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x01000000L
++#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x02000000L
++#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x04000000L
++#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x08000000L
++#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000L
++#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000L
++#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L
++#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L
++//CRTC5_CRTC_UPDATE_LOCK
++#define CRTC5_CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0
++#define CRTC5_CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x00000001L
++//CRTC5_CRTC_DOUBLE_BUFFER_CONTROL
++#define CRTC5_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0
++#define CRTC5_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8
++#define CRTC5_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10
++#define CRTC5_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18
++#define CRTC5_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x19
++#define CRTC5_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x00000001L
++#define CRTC5_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x00000100L
++#define CRTC5_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L
++#define CRTC5_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x01000000L
++#define CRTC5_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x02000000L
++//CRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE
++#define CRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0
++#define CRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x00000001L
++//CRTC5_CRTC_TEST_PATTERN_CONTROL
++#define CRTC5_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0
++#define CRTC5_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8
++#define CRTC5_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10
++#define CRTC5_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18
++#define CRTC5_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x00000001L
++#define CRTC5_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x00000700L
++#define CRTC5_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L
++#define CRTC5_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xFF000000L
++//CRTC5_CRTC_TEST_PATTERN_PARAMETERS
++#define CRTC5_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0
++#define CRTC5_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4
++#define CRTC5_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8
++#define CRTC5_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc
++#define CRTC5_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10
++#define CRTC5_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0x0000000FL
++#define CRTC5_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0x000000F0L
++#define CRTC5_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0x00000F00L
++#define CRTC5_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0x0000F000L
++#define CRTC5_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xFFFF0000L
++//CRTC5_CRTC_TEST_PATTERN_COLOR
++#define CRTC5_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0
++#define CRTC5_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10
++#define CRTC5_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0x0000FFFFL
++#define CRTC5_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x003F0000L
++//CRTC5_CRTC_MASTER_UPDATE_LOCK
++#define CRTC5_CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0
++#define CRTC5_CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8
++#define CRTC5_CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK__SHIFT 0x10
++#define CRTC5_CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x00000001L
++#define CRTC5_CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x00000100L
++#define CRTC5_CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK_MASK 0x00010000L
++//CRTC5_CRTC_MASTER_UPDATE_MODE
++#define CRTC5_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0
++#define CRTC5_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10
++#define CRTC5_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x00000007L
++#define CRTC5_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00030000L
++//CRTC5_CRTC_MVP_INBAND_CNTL_INSERT
++#define CRTC5_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0
++#define CRTC5_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8
++#define CRTC5_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x00000003L
++#define CRTC5_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xFFFFFF00L
++//CRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER
++#define CRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0
++#define CRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0x000000FFL
++//CRTC5_CRTC_MVP_STATUS
++#define CRTC5_CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0
++#define CRTC5_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4
++#define CRTC5_CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10
++#define CRTC5_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14
++#define CRTC5_CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x00000001L
++#define CRTC5_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x00000010L
++#define CRTC5_CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x00010000L
++#define CRTC5_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x00100000L
++//CRTC5_CRTC_MASTER_EN
++#define CRTC5_CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0
++#define CRTC5_CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x00000001L
++//CRTC5_CRTC_ALLOW_STOP_OFF_V_CNT
++#define CRTC5_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0
++#define CRTC5_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10
++#define CRTC5_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0x000000FFL
++#define CRTC5_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x00010000L
++//CRTC5_CRTC_V_UPDATE_INT_STATUS
++#define CRTC5_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0
++#define CRTC5_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8
++#define CRTC5_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x00000001L
++#define CRTC5_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x00000100L
++//CRTC5_CRTC_OVERSCAN_COLOR
++#define CRTC5_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0
++#define CRTC5_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa
++#define CRTC5_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14
++#define CRTC5_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x000003FFL
++#define CRTC5_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0x000FFC00L
++#define CRTC5_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3FF00000L
++//CRTC5_CRTC_OVERSCAN_COLOR_EXT
++#define CRTC5_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0
++#define CRTC5_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8
++#define CRTC5_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10
++#define CRTC5_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x00000003L
++#define CRTC5_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x00000300L
++#define CRTC5_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x00030000L
++//CRTC5_CRTC_BLANK_DATA_COLOR
++#define CRTC5_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0
++#define CRTC5_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa
++#define CRTC5_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14
++#define CRTC5_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL
++#define CRTC5_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L
++#define CRTC5_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L
++//CRTC5_CRTC_BLANK_DATA_COLOR_EXT
++#define CRTC5_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0
++#define CRTC5_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8
++#define CRTC5_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10
++#define CRTC5_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x00000003L
++#define CRTC5_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00000300L
++#define CRTC5_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x00030000L
++//CRTC5_CRTC_BLACK_COLOR
++#define CRTC5_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0
++#define CRTC5_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa
++#define CRTC5_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14
++#define CRTC5_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x000003FFL
++#define CRTC5_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0x000FFC00L
++#define CRTC5_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3FF00000L
++//CRTC5_CRTC_BLACK_COLOR_EXT
++#define CRTC5_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0
++#define CRTC5_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8
++#define CRTC5_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10
++#define CRTC5_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x00000003L
++#define CRTC5_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x00000300L
++#define CRTC5_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x00030000L
++//CRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION
++#define CRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0
++#define CRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10
++#define CRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00003FFFL
++#define CRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x3FFF0000L
++//CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL
++#define CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4
++#define CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8
++#define CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc
++#define CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10
++#define CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14
++#define CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18
++#define CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L
++#define CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L
++#define CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L
++#define CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L
++#define CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L
++#define CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L
++//CRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION
++#define CRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0
++#define CRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00003FFFL
++//CRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL
++#define CRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8
++#define CRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc
++#define CRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10
++#define CRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14
++#define CRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18
++#define CRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L
++#define CRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L
++#define CRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L
++#define CRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L
++#define CRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L
++//CRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION
++#define CRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0
++#define CRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00003FFFL
++//CRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL
++#define CRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8
++#define CRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc
++#define CRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10
++#define CRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14
++#define CRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18
++#define CRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L
++#define CRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L
++#define CRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L
++#define CRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L
++#define CRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L
++//CRTC5_CRTC_CRC_CNTL
++#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0
++#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4
++#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8
++#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc
++#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
++#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14
++#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18
++#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC_EN_MASK 0x00000001L
++#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x00000010L
++#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x00000300L
++#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x00003000L
++#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
++#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x00700000L
++#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x07000000L
++//CRTC5_CRTC_CRC0_WINDOWA_X_CONTROL
++#define CRTC5_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0
++#define CRTC5_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10
++#define CRTC5_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x00003FFFL
++#define CRTC5_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3FFF0000L
++//CRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL
++#define CRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0
++#define CRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10
++#define CRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x00003FFFL
++#define CRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3FFF0000L
++//CRTC5_CRTC_CRC0_WINDOWB_X_CONTROL
++#define CRTC5_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0
++#define CRTC5_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10
++#define CRTC5_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x00003FFFL
++#define CRTC5_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3FFF0000L
++//CRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL
++#define CRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0
++#define CRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10
++#define CRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x00003FFFL
++#define CRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3FFF0000L
++//CRTC5_CRTC_CRC0_DATA_RG
++#define CRTC5_CRTC_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0
++#define CRTC5_CRTC_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10
++#define CRTC5_CRTC_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL
++#define CRTC5_CRTC_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L
++//CRTC5_CRTC_CRC0_DATA_B
++#define CRTC5_CRTC_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0
++#define CRTC5_CRTC_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL
++//CRTC5_CRTC_CRC1_WINDOWA_X_CONTROL
++#define CRTC5_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0
++#define CRTC5_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10
++#define CRTC5_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x00003FFFL
++#define CRTC5_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3FFF0000L
++//CRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL
++#define CRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0
++#define CRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10
++#define CRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x00003FFFL
++#define CRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3FFF0000L
++//CRTC5_CRTC_CRC1_WINDOWB_X_CONTROL
++#define CRTC5_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0
++#define CRTC5_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10
++#define CRTC5_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x00003FFFL
++#define CRTC5_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3FFF0000L
++//CRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL
++#define CRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0
++#define CRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10
++#define CRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x00003FFFL
++#define CRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3FFF0000L
++//CRTC5_CRTC_CRC1_DATA_RG
++#define CRTC5_CRTC_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0
++#define CRTC5_CRTC_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10
++#define CRTC5_CRTC_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL
++#define CRTC5_CRTC_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L
++//CRTC5_CRTC_CRC1_DATA_B
++#define CRTC5_CRTC_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0
++#define CRTC5_CRTC_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL
++//CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL
++#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE__SHIFT 0x0
++#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__SHIFT 0x3
++#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__SHIFT 0x4
++#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__SHIFT 0x5
++#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__SHIFT 0x8
++#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__SHIFT 0x9
++#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__SHIFT 0xc
++#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__SHIFT 0xd
++#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__SHIFT 0xe
++#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE__SHIFT 0x18
++#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE__SHIFT 0x1c
++#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE_MASK 0x00000003L
++#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_MASK 0x00000008L
++#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_MASK 0x00000010L
++#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_MASK 0x00000060L
++#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_MASK 0x00000100L
++#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_MASK 0x00000200L
++#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_MASK 0x00001000L
++#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_MASK 0x00002000L
++#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_MASK 0x00004000L
++#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE_MASK 0x07000000L
++#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE_MASK 0x70000000L
++//CRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START
++#define CRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X__SHIFT 0x0
++#define CRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y__SHIFT 0x10
++#define CRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X_MASK 0x00003FFFL
++#define CRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y_MASK 0x3FFF0000L
++//CRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END
++#define CRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X__SHIFT 0x0
++#define CRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y__SHIFT 0x10
++#define CRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X_MASK 0x00003FFFL
++#define CRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y_MASK 0x3FFF0000L
++//CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL
++#define CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__SHIFT 0x0
++#define CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS__SHIFT 0x4
++#define CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS__SHIFT 0x8
++#define CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__SHIFT 0x10
++#define CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__SHIFT 0x14
++#define CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__SHIFT 0x1d
++#define CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_MASK 0x00000001L
++#define CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS_MASK 0x00000010L
++#define CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS_MASK 0x00000100L
++#define CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_MASK 0x00010000L
++#define CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_MASK 0x00100000L
++#define CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_MASK 0xE0000000L
++//CRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL
++#define CRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE__SHIFT 0x0
++#define CRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS__SHIFT 0x4
++#define CRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS__SHIFT 0x8
++#define CRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR__SHIFT 0x10
++#define CRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE__SHIFT 0x14
++#define CRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE_MASK 0x00000001L
++#define CRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS_MASK 0x00000010L
++#define CRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS_MASK 0x00000100L
++#define CRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR_MASK 0x00010000L
++#define CRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE_MASK 0x00100000L
++//CRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL
++#define CRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__SHIFT 0x0
++#define CRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS__SHIFT 0x4
++#define CRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS__SHIFT 0x8
++#define CRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__SHIFT 0x10
++#define CRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__SHIFT 0x14
++#define CRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_MASK 0x00000001L
++#define CRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS_MASK 0x00000010L
++#define CRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS_MASK 0x00000100L
++#define CRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_MASK 0x00010000L
++#define CRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_MASK 0x00100000L
++//CRTC5_CRTC_STATIC_SCREEN_CONTROL
++#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0
++#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10
++#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18
++#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19
++#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a
++#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b
++#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c
++#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e
++#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f
++#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL
++#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L
++#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x01000000L
++#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x02000000L
++#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x04000000L
++#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x08000000L
++#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000L
++#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L
++#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L
++//CRTC5_CRTC_3D_STRUCTURE_CONTROL
++#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0
++#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4
++#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8
++#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc
++#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10
++#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11
++#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12
++#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x00000001L
++#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x00000010L
++#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L
++#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L
++#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L
++#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L
++#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L
++//CRTC5_CRTC_GSL_VSYNC_GAP
++#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0
++#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8
++#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10
++#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11
++#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13
++#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14
++#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17
++#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18
++#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL
++#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L
++#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L
++#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x00060000L
++#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L
++#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L
++#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L
++#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xFF000000L
++//CRTC5_CRTC_GSL_WINDOW
++#define CRTC5_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0
++#define CRTC5_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10
++#define CRTC5_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x00003FFFL
++#define CRTC5_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x3FFF0000L
++//CRTC5_CRTC_GSL_CONTROL
++#define CRTC5_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0
++#define CRTC5_CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10
++#define CRTC5_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c
++#define CRTC5_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x00003FFFL
++#define CRTC5_CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x001F0000L
++#define CRTC5_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L
++//CRTC5_CRTC_RANGE_TIMING_INT_STATUS
++#define CRTC5_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0
++#define CRTC5_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4
++#define CRTC5_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8
++#define CRTC5_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc
++#define CRTC5_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10
++#define CRTC5_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L
++#define CRTC5_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L
++#define CRTC5_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L
++#define CRTC5_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L
++#define CRTC5_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L
++//CRTC5_CRTC_DRR_CONTROL
++#define CRTC5_CRTC_DRR_CONTROL__CRTC_XDMA_PREFETCH_DELAY__SHIFT 0x0
++#define CRTC5_CRTC_DRR_CONTROL__CRTC_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0xe
++#define CRTC5_CRTC_DRR_CONTROL__CRTC_SET_V_TOTAL_MIN_AUTO_DIS__SHIFT 0x1c
++#define CRTC5_CRTC_DRR_CONTROL__CRTC_DRR_MODE_DBUF_UPDATE_MODE__SHIFT 0x1d
++#define CRTC5_CRTC_DRR_CONTROL__CRTC_XDMA_PREFETCH_DELAY_MASK 0x00003FFFL
++#define CRTC5_CRTC_DRR_CONTROL__CRTC_V_TOTAL_LAST_USED_BY_DRR_MASK 0x0FFFC000L
++#define CRTC5_CRTC_DRR_CONTROL__CRTC_SET_V_TOTAL_MIN_AUTO_DIS_MASK 0x10000000L
++#define CRTC5_CRTC_DRR_CONTROL__CRTC_DRR_MODE_DBUF_UPDATE_MODE_MASK 0x60000000L
++
++
++// addressBlock: dce_dc_fmt5_dispdec
++//FMT5_FMT_CLAMP_COMPONENT_R
++#define FMT5_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0
++#define FMT5_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10
++#define FMT5_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL
++#define FMT5_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L
++//FMT5_FMT_CLAMP_COMPONENT_G
++#define FMT5_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0
++#define FMT5_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10
++#define FMT5_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL
++#define FMT5_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L
++//FMT5_FMT_CLAMP_COMPONENT_B
++#define FMT5_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0
++#define FMT5_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10
++#define FMT5_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL
++#define FMT5_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L
++//FMT5_FMT_DYNAMIC_EXP_CNTL
++#define FMT5_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0
++#define FMT5_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4
++#define FMT5_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L
++#define FMT5_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L
++//FMT5_FMT_CONTROL
++#define FMT5_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0
++#define FMT5_FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT 0x4
++#define FMT5_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8
++#define FMT5_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc
++#define FMT5_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10
++#define FMT5_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12
++#define FMT5_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14
++#define FMT5_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15
++#define FMT5_FMT_CONTROL__FMT_SRC_SELECT__SHIFT 0x18
++#define FMT5_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED__SHIFT 0x1e
++#define FMT5_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_CLEAR__SHIFT 0x1f
++#define FMT5_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L
++#define FMT5_FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK 0x00000010L
++#define FMT5_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L
++#define FMT5_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L
++#define FMT5_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L
++#define FMT5_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L
++#define FMT5_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L
++#define FMT5_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L
++#define FMT5_FMT_CONTROL__FMT_SRC_SELECT_MASK 0x07000000L
++#define FMT5_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_MASK 0x40000000L
++#define FMT5_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_CLEAR_MASK 0x80000000L
++//FMT5_FMT_BIT_DEPTH_CONTROL
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L
++//FMT5_FMT_DITHER_RAND_R_SEED
++#define FMT5_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0
++#define FMT5_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10
++#define FMT5_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL
++#define FMT5_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L
++//FMT5_FMT_DITHER_RAND_G_SEED
++#define FMT5_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0
++#define FMT5_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10
++#define FMT5_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL
++#define FMT5_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L
++//FMT5_FMT_DITHER_RAND_B_SEED
++#define FMT5_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0
++#define FMT5_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10
++#define FMT5_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL
++#define FMT5_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L
++//FMT5_FMT_CLAMP_CNTL
++#define FMT5_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0
++#define FMT5_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10
++#define FMT5_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L
++#define FMT5_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L
++//FMT5_FMT_CRC_CNTL
++#define FMT5_FMT_CRC_CNTL__FMT_CRC_EN__SHIFT 0x0
++#define FMT5_FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN__SHIFT 0x1
++#define FMT5_FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT 0x4
++#define FMT5_FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING__SHIFT 0x5
++#define FMT5_FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN__SHIFT 0x6
++#define FMT5_FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB__SHIFT 0x8
++#define FMT5_FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE__SHIFT 0x9
++#define FMT5_FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT 0xc
++#define FMT5_FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
++#define FMT5_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT 0x14
++#define FMT5_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT 0x18
++#define FMT5_FMT_CRC_CNTL__FMT_CRC_EN_MASK 0x00000001L
++#define FMT5_FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN_MASK 0x00000002L
++#define FMT5_FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK 0x00000010L
++#define FMT5_FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING_MASK 0x00000020L
++#define FMT5_FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN_MASK 0x00000040L
++#define FMT5_FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB_MASK 0x00000100L
++#define FMT5_FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE_MASK 0x00000200L
++#define FMT5_FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK 0x00003000L
++#define FMT5_FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
++#define FMT5_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK 0x00100000L
++#define FMT5_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK 0x01000000L
++//FMT5_FMT_CRC_SIG_RED_GREEN_MASK
++#define FMT5_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT 0x0
++#define FMT5_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT 0x10
++#define FMT5_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK 0x0000FFFFL
++#define FMT5_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L
++//FMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK
++#define FMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT 0x0
++#define FMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT 0x10
++#define FMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL
++#define FMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L
++//FMT5_FMT_CRC_SIG_RED_GREEN
++#define FMT5_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT 0x0
++#define FMT5_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT 0x10
++#define FMT5_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK 0x0000FFFFL
++#define FMT5_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK 0xFFFF0000L
++//FMT5_FMT_CRC_SIG_BLUE_CONTROL
++#define FMT5_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT 0x0
++#define FMT5_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT 0x10
++#define FMT5_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK 0x0000FFFFL
++#define FMT5_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK 0xFFFF0000L
++//FMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL
++#define FMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0
++#define FMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL
++//FMT5_FMT_420_HBLANK_EARLY_START
++#define FMT5_FMT_420_HBLANK_EARLY_START__FMT_420_HBLANK_EARLY_START__SHIFT 0x0
++#define FMT5_FMT_420_HBLANK_EARLY_START__FMT_420_HBLANK_EARLY_START_MASK 0x00000FFFL
++
++
++// addressBlock: dce_dc_unp0_dispdec
++//UNP0_UNP_GRPH_ENABLE
++#define UNP0_UNP_GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0
++#define UNP0_UNP_GRPH_ENABLE__GRPH_ENABLE_MASK 0x00000001L
++//UNP0_UNP_GRPH_CONTROL
++#define UNP0_UNP_GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0
++#define UNP0_UNP_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x2
++#define UNP0_UNP_GRPH_CONTROL__GRPH_Z__SHIFT 0x4
++#define UNP0_UNP_GRPH_CONTROL__GRPH_BANK_WIDTH_L__SHIFT 0x6
++#define UNP0_UNP_GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8
++#define UNP0_UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT_L__SHIFT 0xb
++#define UNP0_UNP_GRPH_CONTROL__GRPH_TILE_SPLIT_L__SHIFT 0xd
++#define UNP0_UNP_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10
++#define UNP0_UNP_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11
++#define UNP0_UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_L__SHIFT 0x12
++#define UNP0_UNP_GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x14
++#define UNP0_UNP_GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT 0x18
++#define UNP0_UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE_L__SHIFT 0x1d
++#define UNP0_UNP_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f
++#define UNP0_UNP_GRPH_CONTROL__GRPH_DEPTH_MASK 0x00000003L
++#define UNP0_UNP_GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0x0000000CL
++#define UNP0_UNP_GRPH_CONTROL__GRPH_Z_MASK 0x00000030L
++#define UNP0_UNP_GRPH_CONTROL__GRPH_BANK_WIDTH_L_MASK 0x000000C0L
++#define UNP0_UNP_GRPH_CONTROL__GRPH_FORMAT_MASK 0x00000700L
++#define UNP0_UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT_L_MASK 0x00001800L
++#define UNP0_UNP_GRPH_CONTROL__GRPH_TILE_SPLIT_L_MASK 0x0000E000L
++#define UNP0_UNP_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x00010000L
++#define UNP0_UNP_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x00020000L
++#define UNP0_UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_L_MASK 0x000C0000L
++#define UNP0_UNP_GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0x00F00000L
++#define UNP0_UNP_GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1F000000L
++#define UNP0_UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE_L_MASK 0x60000000L
++#define UNP0_UNP_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000L
++//UNP0_UNP_GRPH_CONTROL_C
++#define UNP0_UNP_GRPH_CONTROL_C__GRPH_BANK_WIDTH_C__SHIFT 0x6
++#define UNP0_UNP_GRPH_CONTROL_C__GRPH_BANK_HEIGHT_C__SHIFT 0xb
++#define UNP0_UNP_GRPH_CONTROL_C__GRPH_TILE_SPLIT_C__SHIFT 0xd
++#define UNP0_UNP_GRPH_CONTROL_C__GRPH_MACRO_TILE_ASPECT_C__SHIFT 0x12
++#define UNP0_UNP_GRPH_CONTROL_C__GRPH_MICRO_TILE_MODE_C__SHIFT 0x1d
++#define UNP0_UNP_GRPH_CONTROL_C__GRPH_BANK_WIDTH_C_MASK 0x000000C0L
++#define UNP0_UNP_GRPH_CONTROL_C__GRPH_BANK_HEIGHT_C_MASK 0x00001800L
++#define UNP0_UNP_GRPH_CONTROL_C__GRPH_TILE_SPLIT_C_MASK 0x0000E000L
++#define UNP0_UNP_GRPH_CONTROL_C__GRPH_MACRO_TILE_ASPECT_C_MASK 0x000C0000L
++#define UNP0_UNP_GRPH_CONTROL_C__GRPH_MICRO_TILE_MODE_C_MASK 0x60000000L
++//UNP0_UNP_GRPH_CONTROL_EXP
++#define UNP0_UNP_GRPH_CONTROL_EXP__VIDEO_FORMAT__SHIFT 0x0
++#define UNP0_UNP_GRPH_CONTROL_EXP__VIDEO_FORMAT_MASK 0x00000007L
++//UNP0_UNP_GRPH_SWAP_CNTL
++#define UNP0_UNP_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0
++#define UNP0_UNP_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4
++#define UNP0_UNP_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6
++#define UNP0_UNP_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8
++#define UNP0_UNP_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x00000003L
++#define UNP0_UNP_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x00000030L
++#define UNP0_UNP_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0x000000C0L
++#define UNP0_UNP_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x00000300L
++//UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L
++#define UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L__SHIFT 0x8
++#define UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L_MASK 0xFFFFFF00L
++//UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C
++#define UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x8
++#define UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFF00L
++//UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L
++#define UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
++#define UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_MASK 0x000000FFL
++//UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C
++#define UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
++#define UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x000000FFL
++//UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L
++#define UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__SHIFT 0x8
++#define UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_MASK 0xFFFFFF00L
++//UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C
++#define UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__SHIFT 0x8
++#define UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_MASK 0xFFFFFF00L
++//UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L
++#define UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
++#define UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_MASK 0x000000FFL
++//UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C
++#define UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
++#define UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_MASK 0x000000FFL
++//UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L
++#define UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_SURFACE_ADDRESS_L__SHIFT 0x8
++#define UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_SURFACE_ADDRESS_L_MASK 0xFFFFFF00L
++//UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C
++#define UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x8
++#define UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFF00L
++//UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L
++#define UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
++#define UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_MASK 0x000000FFL
++//UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C
++#define UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
++#define UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x000000FFL
++//UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L
++#define UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__SHIFT 0x8
++#define UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_MASK 0xFFFFFF00L
++//UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C
++#define UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__SHIFT 0x8
++#define UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_MASK 0xFFFFFF00L
++//UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L
++#define UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
++#define UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_MASK 0x000000FFL
++//UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C
++#define UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
++#define UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_MASK 0x000000FFL
++//UNP0_UNP_GRPH_PITCH_L
++#define UNP0_UNP_GRPH_PITCH_L__GRPH_PITCH_L__SHIFT 0x0
++#define UNP0_UNP_GRPH_PITCH_L__GRPH_PITCH_L_MASK 0x00007FFFL
++//UNP0_UNP_GRPH_PITCH_C
++#define UNP0_UNP_GRPH_PITCH_C__GRPH_PITCH_C__SHIFT 0x0
++#define UNP0_UNP_GRPH_PITCH_C__GRPH_PITCH_C_MASK 0x00007FFFL
++//UNP0_UNP_GRPH_SURFACE_OFFSET_X_L
++#define UNP0_UNP_GRPH_SURFACE_OFFSET_X_L__GRPH_SURFACE_OFFSET_X_L__SHIFT 0x0
++#define UNP0_UNP_GRPH_SURFACE_OFFSET_X_L__GRPH_SURFACE_OFFSET_X_L_MASK 0x00003FFFL
++//UNP0_UNP_GRPH_SURFACE_OFFSET_X_C
++#define UNP0_UNP_GRPH_SURFACE_OFFSET_X_C__GRPH_SURFACE_OFFSET_X_C__SHIFT 0x0
++#define UNP0_UNP_GRPH_SURFACE_OFFSET_X_C__GRPH_SURFACE_OFFSET_X_C_MASK 0x00003FFFL
++//UNP0_UNP_GRPH_SURFACE_OFFSET_Y_L
++#define UNP0_UNP_GRPH_SURFACE_OFFSET_Y_L__GRPH_SURFACE_OFFSET_Y_L__SHIFT 0x0
++#define UNP0_UNP_GRPH_SURFACE_OFFSET_Y_L__GRPH_SURFACE_OFFSET_Y_L_MASK 0x00003FFFL
++//UNP0_UNP_GRPH_SURFACE_OFFSET_Y_C
++#define UNP0_UNP_GRPH_SURFACE_OFFSET_Y_C__GRPH_SURFACE_OFFSET_Y_C__SHIFT 0x0
++#define UNP0_UNP_GRPH_SURFACE_OFFSET_Y_C__GRPH_SURFACE_OFFSET_Y_C_MASK 0x00003FFFL
++//UNP0_UNP_GRPH_X_START_L
++#define UNP0_UNP_GRPH_X_START_L__GRPH_X_START_L__SHIFT 0x0
++#define UNP0_UNP_GRPH_X_START_L__GRPH_X_START_L_MASK 0x00003FFFL
++//UNP0_UNP_GRPH_X_START_C
++#define UNP0_UNP_GRPH_X_START_C__GRPH_X_START_C__SHIFT 0x0
++#define UNP0_UNP_GRPH_X_START_C__GRPH_X_START_C_MASK 0x00003FFFL
++//UNP0_UNP_GRPH_Y_START_L
++#define UNP0_UNP_GRPH_Y_START_L__GRPH_Y_START_L__SHIFT 0x0
++#define UNP0_UNP_GRPH_Y_START_L__GRPH_Y_START_L_MASK 0x00003FFFL
++//UNP0_UNP_GRPH_Y_START_C
++#define UNP0_UNP_GRPH_Y_START_C__GRPH_Y_START_C__SHIFT 0x0
++#define UNP0_UNP_GRPH_Y_START_C__GRPH_Y_START_C_MASK 0x00003FFFL
++//UNP0_UNP_GRPH_X_END_L
++#define UNP0_UNP_GRPH_X_END_L__GRPH_X_END_L__SHIFT 0x0
++#define UNP0_UNP_GRPH_X_END_L__GRPH_X_END_L_MASK 0x00007FFFL
++//UNP0_UNP_GRPH_X_END_C
++#define UNP0_UNP_GRPH_X_END_C__GRPH_X_END_C__SHIFT 0x0
++#define UNP0_UNP_GRPH_X_END_C__GRPH_X_END_C_MASK 0x00007FFFL
++//UNP0_UNP_GRPH_Y_END_L
++#define UNP0_UNP_GRPH_Y_END_L__GRPH_Y_END_L__SHIFT 0x0
++#define UNP0_UNP_GRPH_Y_END_L__GRPH_Y_END_L_MASK 0x00007FFFL
++//UNP0_UNP_GRPH_Y_END_C
++#define UNP0_UNP_GRPH_Y_END_C__GRPH_Y_END_C__SHIFT 0x0
++#define UNP0_UNP_GRPH_Y_END_C__GRPH_Y_END_C_MASK 0x00007FFFL
++//UNP0_UNP_GRPH_UPDATE
++#define UNP0_UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0
++#define UNP0_UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1
++#define UNP0_UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2
++#define UNP0_UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3
++#define UNP0_UNP_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10
++#define UNP0_UNP_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14
++#define UNP0_UNP_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
++#define UNP0_UNP_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c
++#define UNP0_UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x00000001L
++#define UNP0_UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x00000002L
++#define UNP0_UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x00000004L
++#define UNP0_UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x00000008L
++#define UNP0_UNP_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x00010000L
++#define UNP0_UNP_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x00100000L
++#define UNP0_UNP_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
++#define UNP0_UNP_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000L
++//UNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT
++#define UNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L__SHIFT 0x0
++#define UNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C__SHIFT 0x8
++#define UNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L_MASK 0x000000FFL
++#define UNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C_MASK 0x0000FF00L
++//UNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L
++#define UNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L__GRPH_SURFACE_ADDRESS_INUSE_L__SHIFT 0x8
++#define UNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L__GRPH_SURFACE_ADDRESS_INUSE_L_MASK 0xFFFFFF00L
++//UNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C
++#define UNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C__GRPH_SURFACE_ADDRESS_INUSE_C__SHIFT 0x8
++#define UNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C__GRPH_SURFACE_ADDRESS_INUSE_C_MASK 0xFFFFFF00L
++//UNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L
++#define UNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__SHIFT 0x0
++#define UNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_MASK 0x000000FFL
++//UNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C
++#define UNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__SHIFT 0x0
++#define UNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_MASK 0x000000FFL
++//UNP0_UNP_DVMM_PTE_CONTROL
++#define UNP0_UNP_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT 0x0
++#define UNP0_UNP_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT 0x1
++#define UNP0_UNP_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT 0x5
++#define UNP0_UNP_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT 0x9
++#define UNP0_UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT 0x14
++#define UNP0_UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT 0x15
++#define UNP0_UNP_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK 0x00000001L
++#define UNP0_UNP_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK 0x0000001EL
++#define UNP0_UNP_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK 0x000001E0L
++#define UNP0_UNP_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK 0x0007FE00L
++#define UNP0_UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK 0x00100000L
++#define UNP0_UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK 0x00200000L
++//UNP0_UNP_DVMM_PTE_CONTROL_C
++#define UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_USE_SINGLE_PTE_C__SHIFT 0x0
++#define UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_WIDTH_C__SHIFT 0x1
++#define UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_HEIGHT_C__SHIFT 0x5
++#define UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_MIN_PTE_BEFORE_FLIP_C__SHIFT 0x9
++#define UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE0_C__SHIFT 0x14
++#define UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE1_C__SHIFT 0x15
++#define UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_USE_SINGLE_PTE_C_MASK 0x00000001L
++#define UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_WIDTH_C_MASK 0x0000001EL
++#define UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_HEIGHT_C_MASK 0x000001E0L
++#define UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_MIN_PTE_BEFORE_FLIP_C_MASK 0x0007FE00L
++#define UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE0_C_MASK 0x00100000L
++#define UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE1_C_MASK 0x00200000L
++//UNP0_UNP_DVMM_PTE_ARB_CONTROL
++#define UNP0_UNP_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT 0x0
++#define UNP0_UNP_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT 0x8
++#define UNP0_UNP_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK 0x0000003FL
++#define UNP0_UNP_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK 0x0000FF00L
++//UNP0_UNP_DVMM_PTE_ARB_CONTROL_C
++#define UNP0_UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_PTE_REQ_PER_CHUNK_C__SHIFT 0x0
++#define UNP0_UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_MAX_PTE_REQ_OUTSTANDING_C__SHIFT 0x8
++#define UNP0_UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_PTE_REQ_PER_CHUNK_C_MASK 0x0000003FL
++#define UNP0_UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_MAX_PTE_REQ_OUTSTANDING_C_MASK 0x0000FF00L
++//UNP0_UNP_GRPH_INTERRUPT_STATUS
++#define UNP0_UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0
++#define UNP0_UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8
++#define UNP0_UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x00000001L
++#define UNP0_UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x00000100L
++//UNP0_UNP_GRPH_INTERRUPT_CONTROL
++#define UNP0_UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0
++#define UNP0_UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8
++#define UNP0_UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x00000001L
++#define UNP0_UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x00000100L
++//UNP0_UNP_GRPH_STEREOSYNC_FLIP
++#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0
++#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x4
++#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_EN__SHIFT 0x8
++#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_MODE__SHIFT 0xc
++#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10
++#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11
++#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_BOTTOM_SURFACE_PENDING__SHIFT 0x12
++#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_BOTTOM_SURFACE_PENDING__SHIFT 0x13
++#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c
++#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x00000001L
++#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x00000030L
++#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_EN_MASK 0x00000100L
++#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_MODE_MASK 0x00003000L
++#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x00010000L
++#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x00020000L
++#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_BOTTOM_SURFACE_PENDING_MASK 0x00040000L
++#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_BOTTOM_SURFACE_PENDING_MASK 0x00080000L
++#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000L
++//UNP0_UNP_FLIP_CONTROL
++#define UNP0_UNP_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT 0x0
++#define UNP0_UNP_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK 0x00000001L
++//UNP0_UNP_CRC_CONTROL
++#define UNP0_UNP_CRC_CONTROL__UNP_CRC_ENABLE__SHIFT 0x0
++#define UNP0_UNP_CRC_CONTROL__UNP_CRC_SOURCE_SEL__SHIFT 0x2
++#define UNP0_UNP_CRC_CONTROL__UNP_CRC_LINE_SEL__SHIFT 0x8
++#define UNP0_UNP_CRC_CONTROL__UNP_CRC_ENABLE_MASK 0x00000001L
++#define UNP0_UNP_CRC_CONTROL__UNP_CRC_SOURCE_SEL_MASK 0x0000001CL
++#define UNP0_UNP_CRC_CONTROL__UNP_CRC_LINE_SEL_MASK 0x00000300L
++//UNP0_UNP_CRC_MASK
++#define UNP0_UNP_CRC_MASK__UNP_CRC_MASK__SHIFT 0x0
++#define UNP0_UNP_CRC_MASK__UNP_CRC_MASK_MASK 0xFFFFFFFFL
++//UNP0_UNP_CRC_CURRENT
++#define UNP0_UNP_CRC_CURRENT__UNP_CRC_CURRENT__SHIFT 0x0
++#define UNP0_UNP_CRC_CURRENT__UNP_CRC_CURRENT_MASK 0xFFFFFFFFL
++//UNP0_UNP_CRC_LAST
++#define UNP0_UNP_CRC_LAST__UNP_CRC_LAST__SHIFT 0x0
++#define UNP0_UNP_CRC_LAST__UNP_CRC_LAST_MASK 0xFFFFFFFFL
++//UNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK
++#define UNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK__UNP_LB_GAP_BETWEEN_CHUNK__SHIFT 0x4
++#define UNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK__UNP_LB_GAP_BETWEEN_CHUNK_MASK 0x000001F0L
++//UNP0_UNP_HW_ROTATION
++#define UNP0_UNP_HW_ROTATION__ROTATION_ANGLE__SHIFT 0x0
++#define UNP0_UNP_HW_ROTATION__PIXEL_DROP__SHIFT 0x4
++#define UNP0_UNP_HW_ROTATION__BUFFER_MODE__SHIFT 0x8
++#define UNP0_UNP_HW_ROTATION__ROTATION_ANGLE_MASK 0x00000007L
++#define UNP0_UNP_HW_ROTATION__PIXEL_DROP_MASK 0x00000010L
++#define UNP0_UNP_HW_ROTATION__BUFFER_MODE_MASK 0x00000100L
++
++
++// addressBlock: dce_dc_lbv0_dispdec
++//LBV0_LBV_DATA_FORMAT
++#define LBV0_LBV_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0
++#define LBV0_LBV_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2
++#define LBV0_LBV_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3
++#define LBV0_LBV_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4
++#define LBV0_LBV_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5
++#define LBV0_LBV_DATA_FORMAT__DITHER_EN__SHIFT 0x6
++#define LBV0_LBV_DATA_FORMAT__DOWNSCALE_PREFETCH_EN__SHIFT 0x7
++#define LBV0_LBV_DATA_FORMAT__PREFETCH__SHIFT 0xc
++#define LBV0_LBV_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18
++#define LBV0_LBV_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f
++#define LBV0_LBV_DATA_FORMAT__PIXEL_DEPTH_MASK 0x00000003L
++#define LBV0_LBV_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x00000004L
++#define LBV0_LBV_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000008L
++#define LBV0_LBV_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x00000010L
++#define LBV0_LBV_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x00000020L
++#define LBV0_LBV_DATA_FORMAT__DITHER_EN_MASK 0x00000040L
++#define LBV0_LBV_DATA_FORMAT__DOWNSCALE_PREFETCH_EN_MASK 0x00000080L
++#define LBV0_LBV_DATA_FORMAT__PREFETCH_MASK 0x00001000L
++#define LBV0_LBV_DATA_FORMAT__REQUEST_MODE_MASK 0x01000000L
++#define LBV0_LBV_DATA_FORMAT__ALPHA_EN_MASK 0x80000000L
++//LBV0_LBV_MEMORY_CTRL
++#define LBV0_LBV_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0
++#define LBV0_LBV_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
++#define LBV0_LBV_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14
++#define LBV0_LBV_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0x00000FFFL
++#define LBV0_LBV_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x000F0000L
++#define LBV0_LBV_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x00300000L
++//LBV0_LBV_MEMORY_SIZE_STATUS
++#define LBV0_LBV_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0
++#define LBV0_LBV_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0x00000FFFL
++//LBV0_LBV_DESKTOP_HEIGHT
++#define LBV0_LBV_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0
++#define LBV0_LBV_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x00007FFFL
++//LBV0_LBV_VLINE_START_END
++#define LBV0_LBV_VLINE_START_END__VLINE_START__SHIFT 0x0
++#define LBV0_LBV_VLINE_START_END__VLINE_END__SHIFT 0x10
++#define LBV0_LBV_VLINE_START_END__VLINE_INV__SHIFT 0x1f
++#define LBV0_LBV_VLINE_START_END__VLINE_START_MASK 0x00003FFFL
++#define LBV0_LBV_VLINE_START_END__VLINE_END_MASK 0x7FFF0000L
++#define LBV0_LBV_VLINE_START_END__VLINE_INV_MASK 0x80000000L
++//LBV0_LBV_VLINE2_START_END
++#define LBV0_LBV_VLINE2_START_END__VLINE2_START__SHIFT 0x0
++#define LBV0_LBV_VLINE2_START_END__VLINE2_END__SHIFT 0x10
++#define LBV0_LBV_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f
++#define LBV0_LBV_VLINE2_START_END__VLINE2_START_MASK 0x00003FFFL
++#define LBV0_LBV_VLINE2_START_END__VLINE2_END_MASK 0x7FFF0000L
++#define LBV0_LBV_VLINE2_START_END__VLINE2_INV_MASK 0x80000000L
++//LBV0_LBV_V_COUNTER
++#define LBV0_LBV_V_COUNTER__V_COUNTER__SHIFT 0x0
++#define LBV0_LBV_V_COUNTER__V_COUNTER_MASK 0x00007FFFL
++//LBV0_LBV_SNAPSHOT_V_COUNTER
++#define LBV0_LBV_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0
++#define LBV0_LBV_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x00007FFFL
++//LBV0_LBV_V_COUNTER_CHROMA
++#define LBV0_LBV_V_COUNTER_CHROMA__V_COUNTER_CHROMA__SHIFT 0x0
++#define LBV0_LBV_V_COUNTER_CHROMA__V_COUNTER_CHROMA_MASK 0x00007FFFL
++//LBV0_LBV_SNAPSHOT_V_COUNTER_CHROMA
++#define LBV0_LBV_SNAPSHOT_V_COUNTER_CHROMA__SNAPSHOT_V_COUNTER_CHROMA__SHIFT 0x0
++#define LBV0_LBV_SNAPSHOT_V_COUNTER_CHROMA__SNAPSHOT_V_COUNTER_CHROMA_MASK 0x00007FFFL
++//LBV0_LBV_INTERRUPT_MASK
++#define LBV0_LBV_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0
++#define LBV0_LBV_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4
++#define LBV0_LBV_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8
++#define LBV0_LBV_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x00000001L
++#define LBV0_LBV_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x00000010L
++#define LBV0_LBV_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x00000100L
++//LBV0_LBV_VLINE_STATUS
++#define LBV0_LBV_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0
++#define LBV0_LBV_VLINE_STATUS__VLINE_ACK__SHIFT 0x4
++#define LBV0_LBV_VLINE_STATUS__VLINE_STAT__SHIFT 0xc
++#define LBV0_LBV_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10
++#define LBV0_LBV_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11
++#define LBV0_LBV_VLINE_STATUS__VLINE_OCCURRED_MASK 0x00000001L
++#define LBV0_LBV_VLINE_STATUS__VLINE_ACK_MASK 0x00000010L
++#define LBV0_LBV_VLINE_STATUS__VLINE_STAT_MASK 0x00001000L
++#define LBV0_LBV_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x00010000L
++#define LBV0_LBV_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x00020000L
++//LBV0_LBV_VLINE2_STATUS
++#define LBV0_LBV_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0
++#define LBV0_LBV_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4
++#define LBV0_LBV_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc
++#define LBV0_LBV_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10
++#define LBV0_LBV_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11
++#define LBV0_LBV_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x00000001L
++#define LBV0_LBV_VLINE2_STATUS__VLINE2_ACK_MASK 0x00000010L
++#define LBV0_LBV_VLINE2_STATUS__VLINE2_STAT_MASK 0x00001000L
++#define LBV0_LBV_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x00010000L
++#define LBV0_LBV_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x00020000L
++//LBV0_LBV_VBLANK_STATUS
++#define LBV0_LBV_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0
++#define LBV0_LBV_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4
++#define LBV0_LBV_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc
++#define LBV0_LBV_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10
++#define LBV0_LBV_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11
++#define LBV0_LBV_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x00000001L
++#define LBV0_LBV_VBLANK_STATUS__VBLANK_ACK_MASK 0x00000010L
++#define LBV0_LBV_VBLANK_STATUS__VBLANK_STAT_MASK 0x00001000L
++#define LBV0_LBV_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x00010000L
++#define LBV0_LBV_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x00020000L
++//LBV0_LBV_SYNC_RESET_SEL
++#define LBV0_LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0
++#define LBV0_LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4
++#define LBV0_LBV_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8
++#define LBV0_LBV_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16
++#define LBV0_LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x00000003L
++#define LBV0_LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x00000010L
++#define LBV0_LBV_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0x0000FF00L
++#define LBV0_LBV_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0x00C00000L
++//LBV0_LBV_BLACK_KEYER_R_CR
++#define LBV0_LBV_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4
++#define LBV0_LBV_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0x0000FFF0L
++//LBV0_LBV_BLACK_KEYER_G_Y
++#define LBV0_LBV_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4
++#define LBV0_LBV_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0x0000FFF0L
++//LBV0_LBV_BLACK_KEYER_B_CB
++#define LBV0_LBV_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4
++#define LBV0_LBV_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0x0000FFF0L
++//LBV0_LBV_KEYER_COLOR_CTRL
++#define LBV0_LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0
++#define LBV0_LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8
++#define LBV0_LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x00000001L
++#define LBV0_LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x00000100L
++//LBV0_LBV_KEYER_COLOR_R_CR
++#define LBV0_LBV_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4
++#define LBV0_LBV_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0x0000FFF0L
++//LBV0_LBV_KEYER_COLOR_G_Y
++#define LBV0_LBV_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4
++#define LBV0_LBV_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0x0000FFF0L
++//LBV0_LBV_KEYER_COLOR_B_CB
++#define LBV0_LBV_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4
++#define LBV0_LBV_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0x0000FFF0L
++//LBV0_LBV_KEYER_COLOR_REP_R_CR
++#define LBV0_LBV_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4
++#define LBV0_LBV_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0x0000FFF0L
++//LBV0_LBV_KEYER_COLOR_REP_G_Y
++#define LBV0_LBV_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4
++#define LBV0_LBV_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0x0000FFF0L
++//LBV0_LBV_KEYER_COLOR_REP_B_CB
++#define LBV0_LBV_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4
++#define LBV0_LBV_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0x0000FFF0L
++//LBV0_LBV_BUFFER_LEVEL_STATUS
++#define LBV0_LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0
++#define LBV0_LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa
++#define LBV0_LBV_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10
++#define LBV0_LBV_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c
++#define LBV0_LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x0000003FL
++#define LBV0_LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0x0000FC00L
++#define LBV0_LBV_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0x0FFF0000L
++#define LBV0_LBV_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xF0000000L
++//LBV0_LBV_BUFFER_URGENCY_CTRL
++#define LBV0_LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0
++#define LBV0_LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10
++#define LBV0_LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0x00000FFFL
++#define LBV0_LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0x0FFF0000L
++//LBV0_LBV_BUFFER_URGENCY_STATUS
++#define LBV0_LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0
++#define LBV0_LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10
++#define LBV0_LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0x00000FFFL
++#define LBV0_LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x00010000L
++//LBV0_LBV_BUFFER_STATUS
++#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0
++#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4
++#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8
++#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc
++#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10
++#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14
++#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18
++#define LBV0_LBV_BUFFER_STATUS__LB_ENABLE_HIGH_THROUGHPUT__SHIFT 0x19
++#define LBV0_LBV_BUFFER_STATUS__LB_HIGH_THROUGHPUT_CNTL__SHIFT 0x1a
++#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0x0000000FL
++#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x00000010L
++#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x00000100L
++#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x00001000L
++#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x00010000L
++#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x00100000L
++#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x01000000L
++#define LBV0_LBV_BUFFER_STATUS__LB_ENABLE_HIGH_THROUGHPUT_MASK 0x02000000L
++#define LBV0_LBV_BUFFER_STATUS__LB_HIGH_THROUGHPUT_CNTL_MASK 0x1C000000L
++//LBV0_LBV_NO_OUTSTANDING_REQ_STATUS
++#define LBV0_LBV_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0
++#define LBV0_LBV_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x00000001L
++
++
++// addressBlock: dce_dc_sclv0_dispdec
++//SCLV0_SCLV_COEF_RAM_SELECT
++#define SCLV0_SCLV_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0
++#define SCLV0_SCLV_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8
++#define SCLV0_SCLV_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10
++#define SCLV0_SCLV_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x00000003L
++#define SCLV0_SCLV_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x00007F00L
++#define SCLV0_SCLV_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x00030000L
++//SCLV0_SCLV_COEF_RAM_TAP_DATA
++#define SCLV0_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0
++#define SCLV0_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
++#define SCLV0_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10
++#define SCLV0_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
++#define SCLV0_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL
++#define SCLV0_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L
++#define SCLV0_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L
++#define SCLV0_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L
++//SCLV0_SCLV_MODE
++#define SCLV0_SCLV_MODE__SCL_MODE__SHIFT 0x0
++#define SCLV0_SCLV_MODE__SCL_MODE_C__SHIFT 0x2
++#define SCLV0_SCLV_MODE__SCL_PSCL_EN__SHIFT 0x4
++#define SCLV0_SCLV_MODE__SCL_PSCL_EN_C__SHIFT 0x5
++#define SCLV0_SCLV_MODE__SCL_INTERLACE_SOURCE__SHIFT 0x8
++#define SCLV0_SCLV_MODE__SCL_MODE_MASK 0x00000003L
++#define SCLV0_SCLV_MODE__SCL_MODE_C_MASK 0x0000000CL
++#define SCLV0_SCLV_MODE__SCL_PSCL_EN_MASK 0x00000010L
++#define SCLV0_SCLV_MODE__SCL_PSCL_EN_C_MASK 0x00000020L
++#define SCLV0_SCLV_MODE__SCL_INTERLACE_SOURCE_MASK 0x00000300L
++//SCLV0_SCLV_TAP_CONTROL
++#define SCLV0_SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0
++#define SCLV0_SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x4
++#define SCLV0_SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_C__SHIFT 0x8
++#define SCLV0_SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_C__SHIFT 0xc
++#define SCLV0_SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x00000007L
++#define SCLV0_SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0x00000070L
++#define SCLV0_SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_C_MASK 0x00000700L
++#define SCLV0_SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_C_MASK 0x00007000L
++//SCLV0_SCLV_CONTROL
++#define SCLV0_SCLV_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
++#define SCLV0_SCLV_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4
++#define SCLV0_SCLV_CONTROL__SCL_TOTAL_PHASE__SHIFT 0x8
++#define SCLV0_SCLV_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L
++#define SCLV0_SCLV_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x00000010L
++#define SCLV0_SCLV_CONTROL__SCL_TOTAL_PHASE_MASK 0x00000100L
++//SCLV0_SCLV_MANUAL_REPLICATE_CONTROL
++#define SCLV0_SCLV_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
++#define SCLV0_SCLV_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
++#define SCLV0_SCLV_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL
++#define SCLV0_SCLV_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L
++//SCLV0_SCLV_AUTOMATIC_MODE_CONTROL
++#define SCLV0_SCLV_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0
++#define SCLV0_SCLV_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10
++#define SCLV0_SCLV_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x00000001L
++#define SCLV0_SCLV_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x00010000L
++//SCLV0_SCLV_HORZ_FILTER_CONTROL
++#define SCLV0_SCLV_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
++#define SCLV0_SCLV_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
++//SCLV0_SCLV_HORZ_FILTER_SCALE_RATIO
++#define SCLV0_SCLV_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
++#define SCLV0_SCLV_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL
++//SCLV0_SCLV_HORZ_FILTER_INIT
++#define SCLV0_SCLV_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
++#define SCLV0_SCLV_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
++#define SCLV0_SCLV_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL
++#define SCLV0_SCLV_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L
++//SCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_C
++#define SCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0
++#define SCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x03FFFFFFL
++//SCLV0_SCLV_HORZ_FILTER_INIT_C
++#define SCLV0_SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0
++#define SCLV0_SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18
++#define SCLV0_SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL
++#define SCLV0_SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L
++//SCLV0_SCLV_VERT_FILTER_CONTROL
++#define SCLV0_SCLV_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
++#define SCLV0_SCLV_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
++//SCLV0_SCLV_VERT_FILTER_SCALE_RATIO
++#define SCLV0_SCLV_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
++#define SCLV0_SCLV_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL
++//SCLV0_SCLV_VERT_FILTER_INIT
++#define SCLV0_SCLV_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
++#define SCLV0_SCLV_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
++#define SCLV0_SCLV_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL
++#define SCLV0_SCLV_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x07000000L
++//SCLV0_SCLV_VERT_FILTER_INIT_BOT
++#define SCLV0_SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
++#define SCLV0_SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
++#define SCLV0_SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL
++#define SCLV0_SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x07000000L
++//SCLV0_SCLV_VERT_FILTER_SCALE_RATIO_C
++#define SCLV0_SCLV_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0
++#define SCLV0_SCLV_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x03FFFFFFL
++//SCLV0_SCLV_VERT_FILTER_INIT_C
++#define SCLV0_SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0
++#define SCLV0_SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18
++#define SCLV0_SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL
++#define SCLV0_SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x07000000L
++//SCLV0_SCLV_VERT_FILTER_INIT_BOT_C
++#define SCLV0_SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0
++#define SCLV0_SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18
++#define SCLV0_SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL
++#define SCLV0_SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x07000000L
++//SCLV0_SCLV_ROUND_OFFSET
++#define SCLV0_SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0
++#define SCLV0_SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10
++#define SCLV0_SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0x0000FFFFL
++#define SCLV0_SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xFFFF0000L
++//SCLV0_SCLV_UPDATE
++#define SCLV0_SCLV_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
++#define SCLV0_SCLV_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8
++#define SCLV0_SCLV_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10
++#define SCLV0_SCLV_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18
++#define SCLV0_SCLV_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L
++#define SCLV0_SCLV_UPDATE__SCL_UPDATE_TAKEN_MASK 0x00000100L
++#define SCLV0_SCLV_UPDATE__SCL_UPDATE_LOCK_MASK 0x00010000L
++#define SCLV0_SCLV_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x01000000L
++//SCLV0_SCLV_ALU_CONTROL
++#define SCLV0_SCLV_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0
++#define SCLV0_SCLV_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x00000001L
++//SCLV0_SCLV_VIEWPORT_START
++#define SCLV0_SCLV_VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0
++#define SCLV0_SCLV_VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10
++#define SCLV0_SCLV_VIEWPORT_START__VIEWPORT_Y_START_MASK 0x00003FFFL
++#define SCLV0_SCLV_VIEWPORT_START__VIEWPORT_X_START_MASK 0x3FFF0000L
++//SCLV0_SCLV_VIEWPORT_START_SECONDARY
++#define SCLV0_SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0
++#define SCLV0_SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10
++#define SCLV0_SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x00003FFFL
++#define SCLV0_SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3FFF0000L
++//SCLV0_SCLV_VIEWPORT_SIZE
++#define SCLV0_SCLV_VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0
++#define SCLV0_SCLV_VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10
++#define SCLV0_SCLV_VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x00001FFFL
++#define SCLV0_SCLV_VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x1FFF0000L
++//SCLV0_SCLV_VIEWPORT_START_C
++#define SCLV0_SCLV_VIEWPORT_START_C__VIEWPORT_Y_START_C__SHIFT 0x0
++#define SCLV0_SCLV_VIEWPORT_START_C__VIEWPORT_X_START_C__SHIFT 0x10
++#define SCLV0_SCLV_VIEWPORT_START_C__VIEWPORT_Y_START_C_MASK 0x00003FFFL
++#define SCLV0_SCLV_VIEWPORT_START_C__VIEWPORT_X_START_C_MASK 0x3FFF0000L
++//SCLV0_SCLV_VIEWPORT_START_SECONDARY_C
++#define SCLV0_SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_Y_START_SECONDARY_C__SHIFT 0x0
++#define SCLV0_SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_X_START_SECONDARY_C__SHIFT 0x10
++#define SCLV0_SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_Y_START_SECONDARY_C_MASK 0x00003FFFL
++#define SCLV0_SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_X_START_SECONDARY_C_MASK 0x3FFF0000L
++//SCLV0_SCLV_VIEWPORT_SIZE_C
++#define SCLV0_SCLV_VIEWPORT_SIZE_C__VIEWPORT_HEIGHT_C__SHIFT 0x0
++#define SCLV0_SCLV_VIEWPORT_SIZE_C__VIEWPORT_WIDTH_C__SHIFT 0x10
++#define SCLV0_SCLV_VIEWPORT_SIZE_C__VIEWPORT_HEIGHT_C_MASK 0x00001FFFL
++#define SCLV0_SCLV_VIEWPORT_SIZE_C__VIEWPORT_WIDTH_C_MASK 0x1FFF0000L
++//SCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT
++#define SCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
++#define SCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
++#define SCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL
++#define SCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L
++//SCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM
++#define SCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
++#define SCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
++#define SCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL
++#define SCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L
++//SCLV0_SCLV_MODE_CHANGE_DET1
++#define SCLV0_SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0
++#define SCLV0_SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4
++#define SCLV0_SCLV_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7
++#define SCLV0_SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x00000001L
++#define SCLV0_SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x00000010L
++#define SCLV0_SCLV_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0x0FFFFF80L
++//SCLV0_SCLV_MODE_CHANGE_DET2
++#define SCLV0_SCLV_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0
++#define SCLV0_SCLV_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x001FFFFFL
++//SCLV0_SCLV_MODE_CHANGE_DET3
++#define SCLV0_SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0
++#define SCLV0_SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10
++#define SCLV0_SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x00003FFFL
++#define SCLV0_SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3FFF0000L
++//SCLV0_SCLV_MODE_CHANGE_MASK
++#define SCLV0_SCLV_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0
++#define SCLV0_SCLV_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x00000001L
++//SCLV0_SCLV_HORZ_FILTER_INIT_BOT
++#define SCLV0_SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_FRAC_BOT__SHIFT 0x0
++#define SCLV0_SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_INT_BOT__SHIFT 0x18
++#define SCLV0_SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_FRAC_BOT_MASK 0x00FFFFFFL
++#define SCLV0_SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_INT_BOT_MASK 0x0F000000L
++//SCLV0_SCLV_HORZ_FILTER_INIT_BOT_C
++#define SCLV0_SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_FRAC_BOT_C__SHIFT 0x0
++#define SCLV0_SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_INT_BOT_C__SHIFT 0x18
++#define SCLV0_SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL
++#define SCLV0_SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_INT_BOT_C_MASK 0x0F000000L
++
++
++// addressBlock: dce_dc_col_man0_dispdec
++//COL_MAN0_COL_MAN_UPDATE
++#define COL_MAN0_COL_MAN_UPDATE__COL_MAN_UPDATE_PENDING__SHIFT 0x0
++#define COL_MAN0_COL_MAN_UPDATE__COL_MAN_UPDATE_TAKEN__SHIFT 0x1
++#define COL_MAN0_COL_MAN_UPDATE__COL_MAN_UPDATE_LOCK__SHIFT 0x10
++#define COL_MAN0_COL_MAN_UPDATE__COL_MAN_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
++#define COL_MAN0_COL_MAN_UPDATE__COL_MAN_UPDATE_PENDING_MASK 0x00000001L
++#define COL_MAN0_COL_MAN_UPDATE__COL_MAN_UPDATE_TAKEN_MASK 0x00000002L
++#define COL_MAN0_COL_MAN_UPDATE__COL_MAN_UPDATE_LOCK_MASK 0x00010000L
++#define COL_MAN0_COL_MAN_UPDATE__COL_MAN_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
++//COL_MAN0_COL_MAN_INPUT_CSC_CONTROL
++#define COL_MAN0_COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_MODE__SHIFT 0x0
++#define COL_MAN0_COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_INPUT_TYPE__SHIFT 0x8
++#define COL_MAN0_COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_CONVERSION_MODE__SHIFT 0x10
++#define COL_MAN0_COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_MODE_MASK 0x00000003L
++#define COL_MAN0_COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_INPUT_TYPE_MASK 0x00000300L
++#define COL_MAN0_COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_CONVERSION_MODE_MASK 0x00010000L
++//COL_MAN0_INPUT_CSC_C11_C12_A
++#define COL_MAN0_INPUT_CSC_C11_C12_A__INPUT_CSC_C11_A__SHIFT 0x0
++#define COL_MAN0_INPUT_CSC_C11_C12_A__INPUT_CSC_C12_A__SHIFT 0x10
++#define COL_MAN0_INPUT_CSC_C11_C12_A__INPUT_CSC_C11_A_MASK 0x0000FFFFL
++#define COL_MAN0_INPUT_CSC_C11_C12_A__INPUT_CSC_C12_A_MASK 0xFFFF0000L
++//COL_MAN0_INPUT_CSC_C13_C14_A
++#define COL_MAN0_INPUT_CSC_C13_C14_A__INPUT_CSC_C13_A__SHIFT 0x0
++#define COL_MAN0_INPUT_CSC_C13_C14_A__INPUT_CSC_C14_A__SHIFT 0x10
++#define COL_MAN0_INPUT_CSC_C13_C14_A__INPUT_CSC_C13_A_MASK 0x0000FFFFL
++#define COL_MAN0_INPUT_CSC_C13_C14_A__INPUT_CSC_C14_A_MASK 0xFFFF0000L
++//COL_MAN0_INPUT_CSC_C21_C22_A
++#define COL_MAN0_INPUT_CSC_C21_C22_A__INPUT_CSC_C21_A__SHIFT 0x0
++#define COL_MAN0_INPUT_CSC_C21_C22_A__INPUT_CSC_C22_A__SHIFT 0x10
++#define COL_MAN0_INPUT_CSC_C21_C22_A__INPUT_CSC_C21_A_MASK 0x0000FFFFL
++#define COL_MAN0_INPUT_CSC_C21_C22_A__INPUT_CSC_C22_A_MASK 0xFFFF0000L
++//COL_MAN0_INPUT_CSC_C23_C24_A
++#define COL_MAN0_INPUT_CSC_C23_C24_A__INPUT_CSC_C23_A__SHIFT 0x0
++#define COL_MAN0_INPUT_CSC_C23_C24_A__INPUT_CSC_C24_A__SHIFT 0x10
++#define COL_MAN0_INPUT_CSC_C23_C24_A__INPUT_CSC_C23_A_MASK 0x0000FFFFL
++#define COL_MAN0_INPUT_CSC_C23_C24_A__INPUT_CSC_C24_A_MASK 0xFFFF0000L
++//COL_MAN0_INPUT_CSC_C31_C32_A
++#define COL_MAN0_INPUT_CSC_C31_C32_A__INPUT_CSC_C31_A__SHIFT 0x0
++#define COL_MAN0_INPUT_CSC_C31_C32_A__INPUT_CSC_C32_A__SHIFT 0x10
++#define COL_MAN0_INPUT_CSC_C31_C32_A__INPUT_CSC_C31_A_MASK 0x0000FFFFL
++#define COL_MAN0_INPUT_CSC_C31_C32_A__INPUT_CSC_C32_A_MASK 0xFFFF0000L
++//COL_MAN0_INPUT_CSC_C33_C34_A
++#define COL_MAN0_INPUT_CSC_C33_C34_A__INPUT_CSC_C33_A__SHIFT 0x0
++#define COL_MAN0_INPUT_CSC_C33_C34_A__INPUT_CSC_C34_A__SHIFT 0x10
++#define COL_MAN0_INPUT_CSC_C33_C34_A__INPUT_CSC_C33_A_MASK 0x0000FFFFL
++#define COL_MAN0_INPUT_CSC_C33_C34_A__INPUT_CSC_C34_A_MASK 0xFFFF0000L
++//COL_MAN0_INPUT_CSC_C11_C12_B
++#define COL_MAN0_INPUT_CSC_C11_C12_B__INPUT_CSC_C11_B__SHIFT 0x0
++#define COL_MAN0_INPUT_CSC_C11_C12_B__INPUT_CSC_C12_B__SHIFT 0x10
++#define COL_MAN0_INPUT_CSC_C11_C12_B__INPUT_CSC_C11_B_MASK 0x0000FFFFL
++#define COL_MAN0_INPUT_CSC_C11_C12_B__INPUT_CSC_C12_B_MASK 0xFFFF0000L
++//COL_MAN0_INPUT_CSC_C13_C14_B
++#define COL_MAN0_INPUT_CSC_C13_C14_B__INPUT_CSC_C13_B__SHIFT 0x0
++#define COL_MAN0_INPUT_CSC_C13_C14_B__INPUT_CSC_C14_B__SHIFT 0x10
++#define COL_MAN0_INPUT_CSC_C13_C14_B__INPUT_CSC_C13_B_MASK 0x0000FFFFL
++#define COL_MAN0_INPUT_CSC_C13_C14_B__INPUT_CSC_C14_B_MASK 0xFFFF0000L
++//COL_MAN0_INPUT_CSC_C21_C22_B
++#define COL_MAN0_INPUT_CSC_C21_C22_B__INPUT_CSC_C21_B__SHIFT 0x0
++#define COL_MAN0_INPUT_CSC_C21_C22_B__INPUT_CSC_C22_B__SHIFT 0x10
++#define COL_MAN0_INPUT_CSC_C21_C22_B__INPUT_CSC_C21_B_MASK 0x0000FFFFL
++#define COL_MAN0_INPUT_CSC_C21_C22_B__INPUT_CSC_C22_B_MASK 0xFFFF0000L
++//COL_MAN0_INPUT_CSC_C23_C24_B
++#define COL_MAN0_INPUT_CSC_C23_C24_B__INPUT_CSC_C23_B__SHIFT 0x0
++#define COL_MAN0_INPUT_CSC_C23_C24_B__INPUT_CSC_C24_B__SHIFT 0x10
++#define COL_MAN0_INPUT_CSC_C23_C24_B__INPUT_CSC_C23_B_MASK 0x0000FFFFL
++#define COL_MAN0_INPUT_CSC_C23_C24_B__INPUT_CSC_C24_B_MASK 0xFFFF0000L
++//COL_MAN0_INPUT_CSC_C31_C32_B
++#define COL_MAN0_INPUT_CSC_C31_C32_B__INPUT_CSC_C31_B__SHIFT 0x0
++#define COL_MAN0_INPUT_CSC_C31_C32_B__INPUT_CSC_C32_B__SHIFT 0x10
++#define COL_MAN0_INPUT_CSC_C31_C32_B__INPUT_CSC_C31_B_MASK 0x0000FFFFL
++#define COL_MAN0_INPUT_CSC_C31_C32_B__INPUT_CSC_C32_B_MASK 0xFFFF0000L
++//COL_MAN0_INPUT_CSC_C33_C34_B
++#define COL_MAN0_INPUT_CSC_C33_C34_B__INPUT_CSC_C33_B__SHIFT 0x0
++#define COL_MAN0_INPUT_CSC_C33_C34_B__INPUT_CSC_C34_B__SHIFT 0x10
++#define COL_MAN0_INPUT_CSC_C33_C34_B__INPUT_CSC_C33_B_MASK 0x0000FFFFL
++#define COL_MAN0_INPUT_CSC_C33_C34_B__INPUT_CSC_C34_B_MASK 0xFFFF0000L
++//COL_MAN0_PRESCALE_CONTROL
++#define COL_MAN0_PRESCALE_CONTROL__PRESCALE_MODE__SHIFT 0x0
++#define COL_MAN0_PRESCALE_CONTROL__PRESCALE_MODE_MASK 0x00000003L
++//COL_MAN0_PRESCALE_VALUES_R
++#define COL_MAN0_PRESCALE_VALUES_R__PRESCALE_BIAS_R__SHIFT 0x0
++#define COL_MAN0_PRESCALE_VALUES_R__PRESCALE_SCALE_R__SHIFT 0x10
++#define COL_MAN0_PRESCALE_VALUES_R__PRESCALE_BIAS_R_MASK 0x0000FFFFL
++#define COL_MAN0_PRESCALE_VALUES_R__PRESCALE_SCALE_R_MASK 0xFFFF0000L
++//COL_MAN0_PRESCALE_VALUES_G
++#define COL_MAN0_PRESCALE_VALUES_G__PRESCALE_BIAS_G__SHIFT 0x0
++#define COL_MAN0_PRESCALE_VALUES_G__PRESCALE_SCALE_G__SHIFT 0x10
++#define COL_MAN0_PRESCALE_VALUES_G__PRESCALE_BIAS_G_MASK 0x0000FFFFL
++#define COL_MAN0_PRESCALE_VALUES_G__PRESCALE_SCALE_G_MASK 0xFFFF0000L
++//COL_MAN0_PRESCALE_VALUES_B
++#define COL_MAN0_PRESCALE_VALUES_B__PRESCALE_BIAS_B__SHIFT 0x0
++#define COL_MAN0_PRESCALE_VALUES_B__PRESCALE_SCALE_B__SHIFT 0x10
++#define COL_MAN0_PRESCALE_VALUES_B__PRESCALE_BIAS_B_MASK 0x0000FFFFL
++#define COL_MAN0_PRESCALE_VALUES_B__PRESCALE_SCALE_B_MASK 0xFFFF0000L
++//COL_MAN0_COL_MAN_OUTPUT_CSC_CONTROL
++#define COL_MAN0_COL_MAN_OUTPUT_CSC_CONTROL__OUTPUT_CSC_MODE__SHIFT 0x0
++#define COL_MAN0_COL_MAN_OUTPUT_CSC_CONTROL__OUTPUT_CSC_MODE_MASK 0x00000007L
++//COL_MAN0_OUTPUT_CSC_C11_C12_A
++#define COL_MAN0_OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C11_A__SHIFT 0x0
++#define COL_MAN0_OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C12_A__SHIFT 0x10
++#define COL_MAN0_OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C11_A_MASK 0x0000FFFFL
++#define COL_MAN0_OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C12_A_MASK 0xFFFF0000L
++//COL_MAN0_OUTPUT_CSC_C13_C14_A
++#define COL_MAN0_OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C13_A__SHIFT 0x0
++#define COL_MAN0_OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C14_A__SHIFT 0x10
++#define COL_MAN0_OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C13_A_MASK 0x0000FFFFL
++#define COL_MAN0_OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C14_A_MASK 0xFFFF0000L
++//COL_MAN0_OUTPUT_CSC_C21_C22_A
++#define COL_MAN0_OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C21_A__SHIFT 0x0
++#define COL_MAN0_OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C22_A__SHIFT 0x10
++#define COL_MAN0_OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C21_A_MASK 0x0000FFFFL
++#define COL_MAN0_OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C22_A_MASK 0xFFFF0000L
++//COL_MAN0_OUTPUT_CSC_C23_C24_A
++#define COL_MAN0_OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C23_A__SHIFT 0x0
++#define COL_MAN0_OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C24_A__SHIFT 0x10
++#define COL_MAN0_OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C23_A_MASK 0x0000FFFFL
++#define COL_MAN0_OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C24_A_MASK 0xFFFF0000L
++//COL_MAN0_OUTPUT_CSC_C31_C32_A
++#define COL_MAN0_OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C31_A__SHIFT 0x0
++#define COL_MAN0_OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C32_A__SHIFT 0x10
++#define COL_MAN0_OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C31_A_MASK 0x0000FFFFL
++#define COL_MAN0_OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C32_A_MASK 0xFFFF0000L
++//COL_MAN0_OUTPUT_CSC_C33_C34_A
++#define COL_MAN0_OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C33_A__SHIFT 0x0
++#define COL_MAN0_OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C34_A__SHIFT 0x10
++#define COL_MAN0_OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C33_A_MASK 0x0000FFFFL
++#define COL_MAN0_OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C34_A_MASK 0xFFFF0000L
++//COL_MAN0_OUTPUT_CSC_C11_C12_B
++#define COL_MAN0_OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C11_B__SHIFT 0x0
++#define COL_MAN0_OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C12_B__SHIFT 0x10
++#define COL_MAN0_OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C11_B_MASK 0x0000FFFFL
++#define COL_MAN0_OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C12_B_MASK 0xFFFF0000L
++//COL_MAN0_OUTPUT_CSC_C13_C14_B
++#define COL_MAN0_OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C13_B__SHIFT 0x0
++#define COL_MAN0_OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C14_B__SHIFT 0x10
++#define COL_MAN0_OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C13_B_MASK 0x0000FFFFL
++#define COL_MAN0_OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C14_B_MASK 0xFFFF0000L
++//COL_MAN0_OUTPUT_CSC_C21_C22_B
++#define COL_MAN0_OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C21_B__SHIFT 0x0
++#define COL_MAN0_OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C22_B__SHIFT 0x10
++#define COL_MAN0_OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C21_B_MASK 0x0000FFFFL
++#define COL_MAN0_OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C22_B_MASK 0xFFFF0000L
++//COL_MAN0_OUTPUT_CSC_C23_C24_B
++#define COL_MAN0_OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C23_B__SHIFT 0x0
++#define COL_MAN0_OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C24_B__SHIFT 0x10
++#define COL_MAN0_OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C23_B_MASK 0x0000FFFFL
++#define COL_MAN0_OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C24_B_MASK 0xFFFF0000L
++//COL_MAN0_OUTPUT_CSC_C31_C32_B
++#define COL_MAN0_OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C31_B__SHIFT 0x0
++#define COL_MAN0_OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C32_B__SHIFT 0x10
++#define COL_MAN0_OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C31_B_MASK 0x0000FFFFL
++#define COL_MAN0_OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C32_B_MASK 0xFFFF0000L
++//COL_MAN0_OUTPUT_CSC_C33_C34_B
++#define COL_MAN0_OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C33_B__SHIFT 0x0
++#define COL_MAN0_OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C34_B__SHIFT 0x10
++#define COL_MAN0_OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C33_B_MASK 0x0000FFFFL
++#define COL_MAN0_OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C34_B_MASK 0xFFFF0000L
++//COL_MAN0_DENORM_CLAMP_CONTROL
++#define COL_MAN0_DENORM_CLAMP_CONTROL__DENORM_MODE__SHIFT 0x0
++#define COL_MAN0_DENORM_CLAMP_CONTROL__DENORM_10BIT_OUT__SHIFT 0x8
++#define COL_MAN0_DENORM_CLAMP_CONTROL__DENORM_MODE_MASK 0x00000003L
++#define COL_MAN0_DENORM_CLAMP_CONTROL__DENORM_10BIT_OUT_MASK 0x00000100L
++//COL_MAN0_DENORM_CLAMP_RANGE_R_CR
++#define COL_MAN0_DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MAX_R_CR__SHIFT 0x0
++#define COL_MAN0_DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MIN_R_CR__SHIFT 0xc
++#define COL_MAN0_DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MAX_R_CR_MASK 0x00000FFFL
++#define COL_MAN0_DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MIN_R_CR_MASK 0x00FFF000L
++//COL_MAN0_DENORM_CLAMP_RANGE_G_Y
++#define COL_MAN0_DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MAX_G_Y__SHIFT 0x0
++#define COL_MAN0_DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MIN_G_Y__SHIFT 0xc
++#define COL_MAN0_DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MAX_G_Y_MASK 0x00000FFFL
++#define COL_MAN0_DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MIN_G_Y_MASK 0x00FFF000L
++//COL_MAN0_DENORM_CLAMP_RANGE_B_CB
++#define COL_MAN0_DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MAX_B_CB__SHIFT 0x0
++#define COL_MAN0_DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MIN_B_CB__SHIFT 0xc
++#define COL_MAN0_DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MAX_B_CB_MASK 0x00000FFFL
++#define COL_MAN0_DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MIN_B_CB_MASK 0x00FFF000L
++//COL_MAN0_COL_MAN_FP_CONVERTED_FIELD
++#define COL_MAN0_COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_DATA__SHIFT 0x0
++#define COL_MAN0_COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14
++#define COL_MAN0_COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_DATA_MASK 0x0003FFFFL
++#define COL_MAN0_COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_INDEX_MASK 0x07F00000L
++//COL_MAN0_COL_MAN_REGAMMA_CONTROL
++#define COL_MAN0_COL_MAN_REGAMMA_CONTROL__COL_MAN_REGAMMA_MODE__SHIFT 0x0
++#define COL_MAN0_COL_MAN_REGAMMA_CONTROL__COL_MAN_REGAMMA_MODE_MASK 0x00000007L
++//COL_MAN0_COL_MAN_REGAMMA_LUT_INDEX
++#define COL_MAN0_COL_MAN_REGAMMA_LUT_INDEX__COL_MAN_REGAMMA_LUT_INDEX__SHIFT 0x0
++#define COL_MAN0_COL_MAN_REGAMMA_LUT_INDEX__COL_MAN_REGAMMA_LUT_INDEX_MASK 0x000001FFL
++//COL_MAN0_COL_MAN_REGAMMA_LUT_DATA
++#define COL_MAN0_COL_MAN_REGAMMA_LUT_DATA__COL_MAN_REGAMMA_LUT_DATA__SHIFT 0x0
++#define COL_MAN0_COL_MAN_REGAMMA_LUT_DATA__COL_MAN_REGAMMA_LUT_DATA_MASK 0x0007FFFFL
++//COL_MAN0_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK
++#define COL_MAN0_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK__COL_MAN_REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x0
++#define COL_MAN0_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK__COL_MAN_REGAMMA_LUT_WRITE_EN_MASK_MASK 0x00000007L
++//COL_MAN0_COL_MAN_REGAMMA_CNTLA_START_CNTL
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_START_CNTL__COL_MAN_REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x0
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_START_CNTL__COL_MAN_REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_START_CNTL__COL_MAN_REGAMMA_CNTLA_EXP_REGION_START_MASK 0x0003FFFFL
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_START_CNTL__COL_MAN_REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
++//COL_MAN0_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL__COL_MAN_REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL__COL_MAN_REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
++//COL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL1
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL1__COL_MAN_REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x0
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL1__COL_MAN_REGAMMA_CNTLA_EXP_REGION_END_MASK 0x0000FFFFL
++//COL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL2
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL2__COL_MAN_REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL2__COL_MAN_REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL2__COL_MAN_REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL2__COL_MAN_REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xFFFF0000L
++//COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xb
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0xf
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1b
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00003800L
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x00FF8000L
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x38000000L
++//COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xb
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0xf
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1b
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00003800L
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x00FF8000L
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x38000000L
++//COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xb
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0xf
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1b
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00003800L
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x00FF8000L
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x38000000L
++//COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xb
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0xf
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1b
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00003800L
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x00FF8000L
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x38000000L
++//COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xb
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0xf
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1b
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00003800L
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x00FF8000L
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x38000000L
++//COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xb
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0xf
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1b
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00003800L
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x00FF8000L
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x38000000L
++//COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xb
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0xf
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1b
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00003800L
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x00FF8000L
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x38000000L
++//COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xb
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0xf
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1b
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00003800L
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x00FF8000L
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x38000000L
++//COL_MAN0_COL_MAN_REGAMMA_CNTLB_START_CNTL
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_START_CNTL__COL_MAN_REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x0
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_START_CNTL__COL_MAN_REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_START_CNTL__COL_MAN_REGAMMA_CNTLB_EXP_REGION_START_MASK 0x0003FFFFL
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_START_CNTL__COL_MAN_REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
++//COL_MAN0_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL__COL_MAN_REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL__COL_MAN_REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
++//COL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL1
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL1__COL_MAN_REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x0
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL1__COL_MAN_REGAMMA_CNTLB_EXP_REGION_END_MASK 0x0000FFFFL
++//COL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL2
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL2__COL_MAN_REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL2__COL_MAN_REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL2__COL_MAN_REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL2__COL_MAN_REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xFFFF0000L
++//COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xb
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0xf
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1b
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00003800L
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x00FF8000L
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x38000000L
++//COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xb
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0xf
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1b
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00003800L
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x00FF8000L
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x38000000L
++//COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xb
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0xf
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1b
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00003800L
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x00FF8000L
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x38000000L
++//COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xb
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0xf
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1b
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00003800L
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x00FF8000L
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x38000000L
++//COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xb
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0xf
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1b
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00003800L
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x00FF8000L
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x38000000L
++//COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xb
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0xf
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1b
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00003800L
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x00FF8000L
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x38000000L
++//COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xb
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0xf
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1b
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00003800L
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x00FF8000L
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x38000000L
++//COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xb
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0xf
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1b
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00003800L
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x00FF8000L
++#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x38000000L
++//COL_MAN0_PACK_FIFO_ERROR
++#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_OCCURED__SHIFT 0x0
++#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_ACK__SHIFT 0x1
++#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_OCCURED__SHIFT 0x8
++#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_ACK__SHIFT 0x9
++#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_OCCURED__SHIFT 0x10
++#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_ACK__SHIFT 0x11
++#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_OCCURED__SHIFT 0x18
++#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_ACK__SHIFT 0x19
++#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_OCCURED_MASK 0x00000001L
++#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_ACK_MASK 0x00000002L
++#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_OCCURED_MASK 0x00000100L
++#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_ACK_MASK 0x00000200L
++#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_OCCURED_MASK 0x00010000L
++#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_ACK_MASK 0x00020000L
++#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_OCCURED_MASK 0x01000000L
++#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_ACK_MASK 0x02000000L
++//COL_MAN0_OUTPUT_FIFO_ERROR
++#define COL_MAN0_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_OCCURED__SHIFT 0x0
++#define COL_MAN0_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_ACK__SHIFT 0x1
++#define COL_MAN0_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_OCCURED__SHIFT 0x8
++#define COL_MAN0_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_ACK__SHIFT 0x9
++#define COL_MAN0_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_OCCURED_MASK 0x00000001L
++#define COL_MAN0_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_ACK_MASK 0x00000002L
++#define COL_MAN0_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_OCCURED_MASK 0x00000100L
++#define COL_MAN0_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_ACK_MASK 0x00000200L
++//COL_MAN0_INPUT_GAMMA_LUT_AUTOFILL
++#define COL_MAN0_INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL__SHIFT 0x0
++#define COL_MAN0_INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL_DONE__SHIFT 0x1
++#define COL_MAN0_INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL_MASK 0x00000001L
++#define COL_MAN0_INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL_DONE_MASK 0x00000002L
++//COL_MAN0_INPUT_GAMMA_LUT_RW_INDEX
++#define COL_MAN0_INPUT_GAMMA_LUT_RW_INDEX__INPUT_GAMMA_LUT_RW_INDEX__SHIFT 0x0
++#define COL_MAN0_INPUT_GAMMA_LUT_RW_INDEX__INPUT_GAMMA_LUT_RW_INDEX_MASK 0x000000FFL
++//COL_MAN0_INPUT_GAMMA_LUT_SEQ_COLOR
++#define COL_MAN0_INPUT_GAMMA_LUT_SEQ_COLOR__INPUT_GAMMA_LUT_SEQ_COLOR__SHIFT 0x0
++#define COL_MAN0_INPUT_GAMMA_LUT_SEQ_COLOR__INPUT_GAMMA_LUT_SEQ_COLOR_MASK 0x0000FFFFL
++//COL_MAN0_INPUT_GAMMA_LUT_PWL_DATA
++#define COL_MAN0_INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_BASE__SHIFT 0x0
++#define COL_MAN0_INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_DELTA__SHIFT 0x10
++#define COL_MAN0_INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_BASE_MASK 0x0000FFFFL
++#define COL_MAN0_INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_DELTA_MASK 0xFFFF0000L
++//COL_MAN0_INPUT_GAMMA_LUT_30_COLOR
++#define COL_MAN0_INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_BLUE__SHIFT 0x0
++#define COL_MAN0_INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_GREEN__SHIFT 0xa
++#define COL_MAN0_INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_RED__SHIFT 0x14
++#define COL_MAN0_INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_BLUE_MASK 0x000003FFL
++#define COL_MAN0_INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_GREEN_MASK 0x000FFC00L
++#define COL_MAN0_INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_RED_MASK 0x3FF00000L
++//COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1
++#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_MODE__SHIFT 0x0
++#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_LUT_10BIT_BYPASS_EN__SHIFT 0x1a
++#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_MODE_MASK 0x00000003L
++#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_LUT_10BIT_BYPASS_EN_MASK 0x04000000L
++//COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2
++#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_B__SHIFT 0x1
++#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_SIGNED_EN__SHIFT 0x5
++#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_FORMAT__SHIFT 0x6
++#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_G__SHIFT 0x8
++#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_SIGNED_EN__SHIFT 0xc
++#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_FORMAT__SHIFT 0xd
++#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_R__SHIFT 0xf
++#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_SIGNED_EN__SHIFT 0x13
++#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_FORMAT__SHIFT 0x14
++#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_RW_MODE__SHIFT 0x16
++#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_WRITE_EN_MASK__SHIFT 0x17
++#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_VGA_ACCESS_ENABLE__SHIFT 0x1a
++#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x1b
++#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_B_MASK 0x0000001EL
++#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_SIGNED_EN_MASK 0x00000020L
++#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_FORMAT_MASK 0x000000C0L
++#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_G_MASK 0x00000F00L
++#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_SIGNED_EN_MASK 0x00001000L
++#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_FORMAT_MASK 0x00006000L
++#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_R_MASK 0x00078000L
++#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_SIGNED_EN_MASK 0x00080000L
++#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_FORMAT_MASK 0x00300000L
++#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_RW_MODE_MASK 0x00400000L
++#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_WRITE_EN_MASK_MASK 0x03800000L
++#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_VGA_ACCESS_ENABLE_MASK 0x04000000L
++#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x08000000L
++//COL_MAN0_INPUT_GAMMA_BW_OFFSETS_B
++#define COL_MAN0_INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_BLACK_OFFSET_B__SHIFT 0x0
++#define COL_MAN0_INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_WHITE_OFFSET_B__SHIFT 0x10
++#define COL_MAN0_INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_BLACK_OFFSET_B_MASK 0x0000FFFFL
++#define COL_MAN0_INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_WHITE_OFFSET_B_MASK 0xFFFF0000L
++//COL_MAN0_INPUT_GAMMA_BW_OFFSETS_G
++#define COL_MAN0_INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_BLACK_OFFSET_G__SHIFT 0x0
++#define COL_MAN0_INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_WHITE_OFFSET_G__SHIFT 0x10
++#define COL_MAN0_INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_BLACK_OFFSET_G_MASK 0x0000FFFFL
++#define COL_MAN0_INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_WHITE_OFFSET_G_MASK 0xFFFF0000L
++//COL_MAN0_INPUT_GAMMA_BW_OFFSETS_R
++#define COL_MAN0_INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_BLACK_OFFSET_R__SHIFT 0x0
++#define COL_MAN0_INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_WHITE_OFFSET_R__SHIFT 0x10
++#define COL_MAN0_INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_BLACK_OFFSET_R_MASK 0x0000FFFFL
++#define COL_MAN0_INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_WHITE_OFFSET_R_MASK 0xFFFF0000L
++//COL_MAN0_COL_MAN_DEGAMMA_CONTROL
++#define COL_MAN0_COL_MAN_DEGAMMA_CONTROL__COL_MAN_DEGAMMA_MODE__SHIFT 0x0
++#define COL_MAN0_COL_MAN_DEGAMMA_CONTROL__COL_MAN_DEGAMMA_MODE_MASK 0x00000003L
++//COL_MAN0_COL_MAN_GAMUT_REMAP_CONTROL
++#define COL_MAN0_COL_MAN_GAMUT_REMAP_CONTROL__COL_MAN_GAMUT_REMAP_MODE__SHIFT 0x0
++#define COL_MAN0_COL_MAN_GAMUT_REMAP_CONTROL__COL_MAN_GAMUT_REMAP_MODE_MASK 0x00000003L
++//COL_MAN0_COL_MAN_GAMUT_REMAP_C11_C12
++#define COL_MAN0_COL_MAN_GAMUT_REMAP_C11_C12__COL_MAN_GAMUT_REMAP_C11__SHIFT 0x0
++#define COL_MAN0_COL_MAN_GAMUT_REMAP_C11_C12__COL_MAN_GAMUT_REMAP_C12__SHIFT 0x10
++#define COL_MAN0_COL_MAN_GAMUT_REMAP_C11_C12__COL_MAN_GAMUT_REMAP_C11_MASK 0x0000FFFFL
++#define COL_MAN0_COL_MAN_GAMUT_REMAP_C11_C12__COL_MAN_GAMUT_REMAP_C12_MASK 0xFFFF0000L
++//COL_MAN0_COL_MAN_GAMUT_REMAP_C13_C14
++#define COL_MAN0_COL_MAN_GAMUT_REMAP_C13_C14__COL_MAN_GAMUT_REMAP_C13__SHIFT 0x0
++#define COL_MAN0_COL_MAN_GAMUT_REMAP_C13_C14__COL_MAN_GAMUT_REMAP_C14__SHIFT 0x10
++#define COL_MAN0_COL_MAN_GAMUT_REMAP_C13_C14__COL_MAN_GAMUT_REMAP_C13_MASK 0x0000FFFFL
++#define COL_MAN0_COL_MAN_GAMUT_REMAP_C13_C14__COL_MAN_GAMUT_REMAP_C14_MASK 0xFFFF0000L
++//COL_MAN0_COL_MAN_GAMUT_REMAP_C21_C22
++#define COL_MAN0_COL_MAN_GAMUT_REMAP_C21_C22__COL_MAN_GAMUT_REMAP_C21__SHIFT 0x0
++#define COL_MAN0_COL_MAN_GAMUT_REMAP_C21_C22__COL_MAN_GAMUT_REMAP_C22__SHIFT 0x10
++#define COL_MAN0_COL_MAN_GAMUT_REMAP_C21_C22__COL_MAN_GAMUT_REMAP_C21_MASK 0x0000FFFFL
++#define COL_MAN0_COL_MAN_GAMUT_REMAP_C21_C22__COL_MAN_GAMUT_REMAP_C22_MASK 0xFFFF0000L
++//COL_MAN0_COL_MAN_GAMUT_REMAP_C23_C24
++#define COL_MAN0_COL_MAN_GAMUT_REMAP_C23_C24__COL_MAN_GAMUT_REMAP_C23__SHIFT 0x0
++#define COL_MAN0_COL_MAN_GAMUT_REMAP_C23_C24__COL_MAN_GAMUT_REMAP_C24__SHIFT 0x10
++#define COL_MAN0_COL_MAN_GAMUT_REMAP_C23_C24__COL_MAN_GAMUT_REMAP_C23_MASK 0x0000FFFFL
++#define COL_MAN0_COL_MAN_GAMUT_REMAP_C23_C24__COL_MAN_GAMUT_REMAP_C24_MASK 0xFFFF0000L
++//COL_MAN0_COL_MAN_GAMUT_REMAP_C31_C32
++#define COL_MAN0_COL_MAN_GAMUT_REMAP_C31_C32__COL_MAN_GAMUT_REMAP_C31__SHIFT 0x0
++#define COL_MAN0_COL_MAN_GAMUT_REMAP_C31_C32__COL_MAN_GAMUT_REMAP_C32__SHIFT 0x10
++#define COL_MAN0_COL_MAN_GAMUT_REMAP_C31_C32__COL_MAN_GAMUT_REMAP_C31_MASK 0x0000FFFFL
++#define COL_MAN0_COL_MAN_GAMUT_REMAP_C31_C32__COL_MAN_GAMUT_REMAP_C32_MASK 0xFFFF0000L
++//COL_MAN0_COL_MAN_GAMUT_REMAP_C33_C34
++#define COL_MAN0_COL_MAN_GAMUT_REMAP_C33_C34__COL_MAN_GAMUT_REMAP_C33__SHIFT 0x0
++#define COL_MAN0_COL_MAN_GAMUT_REMAP_C33_C34__COL_MAN_GAMUT_REMAP_C34__SHIFT 0x10
++#define COL_MAN0_COL_MAN_GAMUT_REMAP_C33_C34__COL_MAN_GAMUT_REMAP_C33_MASK 0x0000FFFFL
++#define COL_MAN0_COL_MAN_GAMUT_REMAP_C33_C34__COL_MAN_GAMUT_REMAP_C34_MASK 0xFFFF0000L
++
++
++// addressBlock: dce_dc_dcfev0_dispdec
++//DCFEV0_DCFEV_CLOCK_CONTROL
++#define DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_R_DCFEV_GATE_DISABLE__SHIFT 0x3
++#define DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_G_UNP_GATE_DISABLE__SHIFT 0x7
++#define DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_G_SCLV_GATE_DISABLE__SHIFT 0x9
++#define DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_G_COL_MAN_GATE_DISABLE__SHIFT 0xb
++#define DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_G_PSCLV_GATE_DISABLE__SHIFT 0xd
++#define DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_G_CRTC_GATE_DISABLE__SHIFT 0xf
++#define DCFEV0_DCFEV_CLOCK_CONTROL__DCFEV_TEST_CLK_SEL__SHIFT 0x18
++#define DCFEV0_DCFEV_CLOCK_CONTROL__DCFEV_CLOCK_ENABLE__SHIFT 0x1f
++#define DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_R_DCFEV_GATE_DISABLE_MASK 0x00000008L
++#define DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_G_UNP_GATE_DISABLE_MASK 0x00000080L
++#define DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_G_SCLV_GATE_DISABLE_MASK 0x00000200L
++#define DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_G_COL_MAN_GATE_DISABLE_MASK 0x00000800L
++#define DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_G_PSCLV_GATE_DISABLE_MASK 0x00002000L
++#define DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_G_CRTC_GATE_DISABLE_MASK 0x00008000L
++#define DCFEV0_DCFEV_CLOCK_CONTROL__DCFEV_TEST_CLK_SEL_MASK 0x1F000000L
++#define DCFEV0_DCFEV_CLOCK_CONTROL__DCFEV_CLOCK_ENABLE_MASK 0x80000000L
++//DCFEV0_DCFEV_SOFT_RESET
++#define DCFEV0_DCFEV_SOFT_RESET__UNP_PIXPIPE_SOFT_RESET__SHIFT 0x0
++#define DCFEV0_DCFEV_SOFT_RESET__UNP_REQ_SOFT_RESET__SHIFT 0x1
++#define DCFEV0_DCFEV_SOFT_RESET__SCLV_ALU_SOFT_RESET__SHIFT 0x2
++#define DCFEV0_DCFEV_SOFT_RESET__SCLV_SOFT_RESET__SHIFT 0x3
++#define DCFEV0_DCFEV_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4
++#define DCFEV0_DCFEV_SOFT_RESET__PSCLV_SOFT_RESET__SHIFT 0x5
++#define DCFEV0_DCFEV_SOFT_RESET__COL_MAN_SOFT_RESET__SHIFT 0x6
++#define DCFEV0_DCFEV_SOFT_RESET__UNP_PIXPIPE_SOFT_RESET_MASK 0x00000001L
++#define DCFEV0_DCFEV_SOFT_RESET__UNP_REQ_SOFT_RESET_MASK 0x00000002L
++#define DCFEV0_DCFEV_SOFT_RESET__SCLV_ALU_SOFT_RESET_MASK 0x00000004L
++#define DCFEV0_DCFEV_SOFT_RESET__SCLV_SOFT_RESET_MASK 0x00000008L
++#define DCFEV0_DCFEV_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x00000010L
++#define DCFEV0_DCFEV_SOFT_RESET__PSCLV_SOFT_RESET_MASK 0x00000020L
++#define DCFEV0_DCFEV_SOFT_RESET__COL_MAN_SOFT_RESET_MASK 0x00000040L
++//DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL
++#define DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x3
++#define DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVL_GATE_DIS__SHIFT 0x4
++#define DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVC_GATE_DIS__SHIFT 0x5
++#define DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SOFT_RESET__SHIFT 0x6
++#define DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_TEST_CLK_SEL__SHIFT 0x18
++#define DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_BUFFER_MODE__SHIFT 0x1f
++#define DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SCLK_G_DMIFTRK_GATE_DIS_MASK 0x00000008L
++#define DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVL_GATE_DIS_MASK 0x00000010L
++#define DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVC_GATE_DIS_MASK 0x00000020L
++#define DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SOFT_RESET_MASK 0x00000040L
++#define DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_TEST_CLK_SEL_MASK 0x1F000000L
++#define DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_BUFFER_MODE_MASK 0x80000000L
++//DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_SEL__SHIFT 0x0
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_0_FORCE__SHIFT 0x2
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_1_FORCE__SHIFT 0x3
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_2_FORCE__SHIFT 0x4
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_3_FORCE__SHIFT 0x5
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_4_FORCE__SHIFT 0x6
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_0_FORCE__SHIFT 0x7
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_1_FORCE__SHIFT 0x8
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_2_FORCE__SHIFT 0x9
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_3_FORCE__SHIFT 0xa
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_4_FORCE__SHIFT 0xb
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_SEL_MASK 0x00000003L
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_0_FORCE_MASK 0x00000004L
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_1_FORCE_MASK 0x00000008L
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_2_FORCE_MASK 0x00000010L
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_3_FORCE_MASK 0x00000020L
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_4_FORCE_MASK 0x00000040L
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_0_FORCE_MASK 0x00000080L
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_1_FORCE_MASK 0x00000100L
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_2_FORCE_MASK 0x00000200L
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_3_FORCE_MASK 0x00000400L
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_4_FORCE_MASK 0x00000800L
++//DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_0_STATE__SHIFT 0x0
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_1_STATE__SHIFT 0x2
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_2_STATE__SHIFT 0x4
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_3_STATE__SHIFT 0x6
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_4_STATE__SHIFT 0x8
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_0_STATE__SHIFT 0xa
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_1_STATE__SHIFT 0xc
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_2_STATE__SHIFT 0xe
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_3_STATE__SHIFT 0x10
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_4_STATE__SHIFT 0x12
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_0_STATE_MASK 0x00000003L
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_1_STATE_MASK 0x0000000CL
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_2_STATE_MASK 0x00000030L
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_3_STATE_MASK 0x000000C0L
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_4_STATE_MASK 0x00000300L
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_0_STATE_MASK 0x00000C00L
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_1_STATE_MASK 0x00003000L
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_2_STATE_MASK 0x0000C000L
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_3_STATE_MASK 0x00030000L
++#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_4_STATE_MASK 0x000C0000L
++//DCFEV0_DCFEV_MEM_PWR_CTRL
++#define DCFEV0_DCFEV_MEM_PWR_CTRL__COL_MAN_REGAMMA_MEM_PWR_FORCE__SHIFT 0x0
++#define DCFEV0_DCFEV_MEM_PWR_CTRL__COL_MAN_REGAMMA_MEM_PWR_DIS__SHIFT 0x2
++#define DCFEV0_DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_FORCE__SHIFT 0x3
++#define DCFEV0_DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_DIS__SHIFT 0x5
++#define DCFEV0_DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_FORCE__SHIFT 0x6
++#define DCFEV0_DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_DIS__SHIFT 0x8
++#define DCFEV0_DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_FORCE__SHIFT 0x9
++#define DCFEV0_DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_DIS__SHIFT 0xb
++#define DCFEV0_DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_FORCE__SHIFT 0xc
++#define DCFEV0_DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_DIS__SHIFT 0xe
++#define DCFEV0_DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_FORCE__SHIFT 0xf
++#define DCFEV0_DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_DIS__SHIFT 0x11
++#define DCFEV0_DCFEV_MEM_PWR_CTRL__COL_MAN_REGAMMA_MEM_PWR_FORCE_MASK 0x00000003L
++#define DCFEV0_DCFEV_MEM_PWR_CTRL__COL_MAN_REGAMMA_MEM_PWR_DIS_MASK 0x00000004L
++#define DCFEV0_DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_FORCE_MASK 0x00000018L
++#define DCFEV0_DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_DIS_MASK 0x00000020L
++#define DCFEV0_DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_FORCE_MASK 0x000000C0L
++#define DCFEV0_DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_DIS_MASK 0x00000100L
++#define DCFEV0_DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_FORCE_MASK 0x00000600L
++#define DCFEV0_DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_DIS_MASK 0x00000800L
++#define DCFEV0_DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_FORCE_MASK 0x00003000L
++#define DCFEV0_DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_DIS_MASK 0x00004000L
++#define DCFEV0_DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_FORCE_MASK 0x00018000L
++#define DCFEV0_DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_DIS_MASK 0x00020000L
++//DCFEV0_DCFEV_MEM_PWR_CTRL2
++#define DCFEV0_DCFEV_MEM_PWR_CTRL2__COL_MAN_REGAMMA_MEM_PWR_MODE_SEL__SHIFT 0x0
++#define DCFEV0_DCFEV_MEM_PWR_CTRL2__COL_MAN_INPUT_GAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2
++#define DCFEV0_DCFEV_MEM_PWR_CTRL2__SCLV_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4
++#define DCFEV0_DCFEV_MEM_PWR_CTRL2__LBV_MEM_PWR_MODE_SEL__SHIFT 0x6
++#define DCFEV0_DCFEV_MEM_PWR_CTRL2__COL_MAN_REGAMMA_MEM_PWR_MODE_SEL_MASK 0x00000003L
++#define DCFEV0_DCFEV_MEM_PWR_CTRL2__COL_MAN_INPUT_GAMMA_MEM_PWR_MODE_SEL_MASK 0x0000000CL
++#define DCFEV0_DCFEV_MEM_PWR_CTRL2__SCLV_COEFF_MEM_PWR_MODE_SEL_MASK 0x00000030L
++#define DCFEV0_DCFEV_MEM_PWR_CTRL2__LBV_MEM_PWR_MODE_SEL_MASK 0x000000C0L
++//DCFEV0_DCFEV_MEM_PWR_STATUS
++#define DCFEV0_DCFEV_MEM_PWR_STATUS__COL_MAN_REGAMMA_MEM_PWR_STATE__SHIFT 0x0
++#define DCFEV0_DCFEV_MEM_PWR_STATUS__COL_MAN_INPUT_GAMMA_MEM_PWR_STATE__SHIFT 0x2
++#define DCFEV0_DCFEV_MEM_PWR_STATUS__SCLV_COEFF_MEM_PWR_STATE__SHIFT 0x4
++#define DCFEV0_DCFEV_MEM_PWR_STATUS__LBV0_MEM_PWR_STATE__SHIFT 0x6
++#define DCFEV0_DCFEV_MEM_PWR_STATUS__LBV1_MEM_PWR_STATE__SHIFT 0x8
++#define DCFEV0_DCFEV_MEM_PWR_STATUS__LBV2_MEM_PWR_STATE__SHIFT 0xa
++#define DCFEV0_DCFEV_MEM_PWR_STATUS__LBV3_MEM_PWR_STATE__SHIFT 0xc
++#define DCFEV0_DCFEV_MEM_PWR_STATUS__COL_MAN_REGAMMA_MEM_PWR_STATE_MASK 0x00000003L
++#define DCFEV0_DCFEV_MEM_PWR_STATUS__COL_MAN_INPUT_GAMMA_MEM_PWR_STATE_MASK 0x0000000CL
++#define DCFEV0_DCFEV_MEM_PWR_STATUS__SCLV_COEFF_MEM_PWR_STATE_MASK 0x00000030L
++#define DCFEV0_DCFEV_MEM_PWR_STATUS__LBV0_MEM_PWR_STATE_MASK 0x000000C0L
++#define DCFEV0_DCFEV_MEM_PWR_STATUS__LBV1_MEM_PWR_STATE_MASK 0x00000300L
++#define DCFEV0_DCFEV_MEM_PWR_STATUS__LBV2_MEM_PWR_STATE_MASK 0x00000C00L
++#define DCFEV0_DCFEV_MEM_PWR_STATUS__LBV3_MEM_PWR_STATE_MASK 0x00003000L
++//DCFEV0_DCFEV_L_FLUSH
++#define DCFEV0_DCFEV_L_FLUSH__FLUSH_OCCURED__SHIFT 0x0
++#define DCFEV0_DCFEV_L_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT 0x1
++#define DCFEV0_DCFEV_L_FLUSH__FLUSH_DEEP__SHIFT 0x2
++#define DCFEV0_DCFEV_L_FLUSH__CLEAR_FLUSH_DEEP__SHIFT 0x3
++#define DCFEV0_DCFEV_L_FLUSH__ALL_MC_REQ_RET__SHIFT 0x4
++#define DCFEV0_DCFEV_L_FLUSH__FLUSH_OCCURED_MASK 0x00000001L
++#define DCFEV0_DCFEV_L_FLUSH__CLEAR_FLUSH_OCCURED_MASK 0x00000002L
++#define DCFEV0_DCFEV_L_FLUSH__FLUSH_DEEP_MASK 0x00000004L
++#define DCFEV0_DCFEV_L_FLUSH__CLEAR_FLUSH_DEEP_MASK 0x00000008L
++#define DCFEV0_DCFEV_L_FLUSH__ALL_MC_REQ_RET_MASK 0x00000010L
++//DCFEV0_DCFEV_C_FLUSH
++#define DCFEV0_DCFEV_C_FLUSH__FLUSH_OCCURED__SHIFT 0x0
++#define DCFEV0_DCFEV_C_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT 0x1
++#define DCFEV0_DCFEV_C_FLUSH__FLUSH_DEEP__SHIFT 0x2
++#define DCFEV0_DCFEV_C_FLUSH__CLEAR_FLUSH_DEEP__SHIFT 0x3
++#define DCFEV0_DCFEV_C_FLUSH__ALL_MC_REQ_RET__SHIFT 0x4
++#define DCFEV0_DCFEV_C_FLUSH__FLUSH_OCCURED_MASK 0x00000001L
++#define DCFEV0_DCFEV_C_FLUSH__CLEAR_FLUSH_OCCURED_MASK 0x00000002L
++#define DCFEV0_DCFEV_C_FLUSH__FLUSH_DEEP_MASK 0x00000004L
++#define DCFEV0_DCFEV_C_FLUSH__CLEAR_FLUSH_DEEP_MASK 0x00000008L
++#define DCFEV0_DCFEV_C_FLUSH__ALL_MC_REQ_RET_MASK 0x00000010L
++//DCFEV0_DCFEV_MISC
++#define DCFEV0_DCFEV_MISC__DCFEV_DPG_ALLOW_SR_ECO_EN__SHIFT 0x0
++#define DCFEV0_DCFEV_MISC__DCFEV_DPG_ALLOW_SR_ECO_EN_MASK 0x00000001L
++
++
++// addressBlock: dce_dc_dc_perfmon11_dispdec
++//DC_PERFMON11_PERFCOUNTER_CNTL
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
++//DC_PERFMON11_PERFCOUNTER_CNTL2
++#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
++#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
++#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
++#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
++#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
++#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
++#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
++#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
++//DC_PERFMON11_PERFCOUNTER_STATE
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
++//DC_PERFMON11_PERFMON_CNTL
++#define DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
++#define DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
++#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
++#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
++#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
++#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
++#define DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
++#define DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
++#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
++#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
++#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
++#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
++//DC_PERFMON11_PERFMON_CNTL2
++#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
++#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
++#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
++#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
++#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
++#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
++#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
++#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
++//DC_PERFMON11_PERFMON_CVALUE_INT_MISC
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
++//DC_PERFMON11_PERFMON_CVALUE_LOW
++#define DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
++#define DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
++//DC_PERFMON11_PERFMON_HI
++#define DC_PERFMON11_PERFMON_HI__PERFMON_HI__SHIFT 0x0
++#define DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
++#define DC_PERFMON11_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
++#define DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
++//DC_PERFMON11_PERFMON_LOW
++#define DC_PERFMON11_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
++#define DC_PERFMON11_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dmifv_pg0_dispdec
++//DMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1
++#define DMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
++#define DMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
++#define DMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0x0000FFFFL
++#define DMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xFFFF0000L
++//DMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2
++#define DMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
++#define DMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
++#define DMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0x0000FFFFL
++#define DMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xFFFF0000L
++//DMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL
++#define DMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
++#define DMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
++#define DMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x10
++#define DMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x18
++#define DMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000003L
++#define DMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x00000300L
++#define DMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00030000L
++#define DMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x01000000L
++//DMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL
++#define DMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
++#define DMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
++#define DMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0x0000FFFFL
++#define DMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xFFFF0000L
++//DMIFV_PG0_DPGV0_PIPE_DPM_CONTROL
++#define DMIFV_PG0_DPGV0_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x0
++#define DMIFV_PG0_DPGV0_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x00000001L
++//DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL
++#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
++#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
++#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
++#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
++#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
++#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x8
++#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x9
++#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
++#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
++#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x10
++#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L
++#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L
++#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x00000020L
++#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x00000040L
++#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x00000080L
++#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x00000100L
++#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x00000200L
++#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x00000400L
++#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x00000800L
++#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xFFFF0000L
++//DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL
++#define DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x0
++#define DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
++#define DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
++#define DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
++#define DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
++#define DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x10
++#define DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x00000001L
++#define DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L
++#define DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x00000100L
++#define DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000200L
++#define DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000400L
++#define DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xFFFF0000L
++//DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH
++#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x0
++#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x4
++#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x5
++#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x6
++#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x7
++#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x8
++#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x9
++#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0xa
++#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0xb
++#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x00000001L
++#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x00000010L
++#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x00000020L
++#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x00000040L
++#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x00000080L
++#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x00000100L
++#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x00000200L
++#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x00000400L
++#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x00000800L
++//DMIFV_PG0_DPGV0_REPEATER_PROGRAM
++#define DMIFV_PG0_DPGV0_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
++#define DMIFV_PG0_DPGV0_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
++#define DMIFV_PG0_DPGV0_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x00000007L
++#define DMIFV_PG0_DPGV0_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x00000070L
++//DMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL
++#define DMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0
++#define DMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x00000001L
++//DMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1
++#define DMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
++#define DMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
++#define DMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0x0000FFFFL
++#define DMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xFFFF0000L
++//DMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2
++#define DMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
++#define DMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
++#define DMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0x0000FFFFL
++#define DMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xFFFF0000L
++//DMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL
++#define DMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
++#define DMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
++#define DMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x10
++#define DMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x18
++#define DMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000003L
++#define DMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x00000300L
++#define DMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00030000L
++#define DMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x01000000L
++//DMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL
++#define DMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
++#define DMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
++#define DMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0x0000FFFFL
++#define DMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xFFFF0000L
++//DMIFV_PG0_DPGV1_PIPE_DPM_CONTROL
++#define DMIFV_PG0_DPGV1_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x0
++#define DMIFV_PG0_DPGV1_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x00000001L
++//DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL
++#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
++#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
++#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
++#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
++#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
++#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x8
++#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x9
++#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
++#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
++#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x10
++#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L
++#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L
++#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x00000020L
++#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x00000040L
++#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x00000080L
++#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x00000100L
++#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x00000200L
++#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x00000400L
++#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x00000800L
++#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xFFFF0000L
++//DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL
++#define DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x0
++#define DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
++#define DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
++#define DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
++#define DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
++#define DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x10
++#define DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x00000001L
++#define DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L
++#define DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x00000100L
++#define DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000200L
++#define DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000400L
++#define DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xFFFF0000L
++//DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH
++#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x0
++#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x4
++#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x5
++#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x6
++#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x7
++#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x8
++#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x9
++#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0xa
++#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0xb
++#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x00000001L
++#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x00000010L
++#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x00000020L
++#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x00000040L
++#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x00000080L
++#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x00000100L
++#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x00000200L
++#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x00000400L
++#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x00000800L
++//DMIFV_PG0_DPGV1_REPEATER_PROGRAM
++#define DMIFV_PG0_DPGV1_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
++#define DMIFV_PG0_DPGV1_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
++#define DMIFV_PG0_DPGV1_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x00000007L
++#define DMIFV_PG0_DPGV1_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x00000070L
++//DMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL
++#define DMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0
++#define DMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x00000001L
++
++
++// addressBlock: dce_dc_blndv0_dispdec
++//BLNDV0_BLNDV_CONTROL
++#define BLNDV0_BLNDV_CONTROL__BLND_GLOBAL_GAIN__SHIFT 0x0
++#define BLNDV0_BLNDV_CONTROL__BLND_MODE__SHIFT 0x8
++#define BLNDV0_BLNDV_CONTROL__BLND_STEREO_TYPE__SHIFT 0xa
++#define BLNDV0_BLNDV_CONTROL__BLND_STEREO_POLARITY__SHIFT 0xc
++#define BLNDV0_BLNDV_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT 0xd
++#define BLNDV0_BLNDV_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10
++#define BLNDV0_BLNDV_CONTROL__BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x12
++#define BLNDV0_BLNDV_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14
++#define BLNDV0_BLNDV_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18
++#define BLNDV0_BLNDV_CONTROL__BLND_GLOBAL_GAIN_MASK 0x000000FFL
++#define BLNDV0_BLNDV_CONTROL__BLND_MODE_MASK 0x00000300L
++#define BLNDV0_BLNDV_CONTROL__BLND_STEREO_TYPE_MASK 0x00000C00L
++#define BLNDV0_BLNDV_CONTROL__BLND_STEREO_POLARITY_MASK 0x00001000L
++#define BLNDV0_BLNDV_CONTROL__BLND_FEEDTHROUGH_EN_MASK 0x00002000L
++#define BLNDV0_BLNDV_CONTROL__BLND_ALPHA_MODE_MASK 0x00030000L
++#define BLNDV0_BLNDV_CONTROL__BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00040000L
++#define BLNDV0_BLNDV_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x00100000L
++#define BLNDV0_BLNDV_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xFF000000L
++//BLNDV0_BLNDV_SM_CONTROL2
++#define BLNDV0_BLNDV_SM_CONTROL2__SM_MODE__SHIFT 0x0
++#define BLNDV0_BLNDV_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4
++#define BLNDV0_BLNDV_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5
++#define BLNDV0_BLNDV_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
++#define BLNDV0_BLNDV_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
++#define BLNDV0_BLNDV_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18
++#define BLNDV0_BLNDV_SM_CONTROL2__SM_MODE_MASK 0x00000007L
++#define BLNDV0_BLNDV_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x00000010L
++#define BLNDV0_BLNDV_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x00000020L
++#define BLNDV0_BLNDV_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L
++#define BLNDV0_BLNDV_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L
++#define BLNDV0_BLNDV_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x01000000L
++//BLNDV0_BLNDV_CONTROL2
++#define BLNDV0_BLNDV_CONTROL2__PTI_ENABLE__SHIFT 0x0
++#define BLNDV0_BLNDV_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT 0x4
++#define BLNDV0_BLNDV_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT 0x6
++#define BLNDV0_BLNDV_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT 0x7
++#define BLNDV0_BLNDV_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT 0x8
++#define BLNDV0_BLNDV_CONTROL2__PTI_ENABLE_MASK 0x00000001L
++#define BLNDV0_BLNDV_CONTROL2__PTI_NEW_PIXEL_GAP_MASK 0x00000030L
++#define BLNDV0_BLNDV_CONTROL2__BLND_NEW_PIXEL_MODE_MASK 0x00000040L
++#define BLNDV0_BLNDV_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK 0x00000080L
++#define BLNDV0_BLNDV_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK 0x00000100L
++//BLNDV0_BLNDV_UPDATE
++#define BLNDV0_BLNDV_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0
++#define BLNDV0_BLNDV_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8
++#define BLNDV0_BLNDV_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10
++#define BLNDV0_BLNDV_UPDATE__BLND_UPDATE_PENDING_MASK 0x00000001L
++#define BLNDV0_BLNDV_UPDATE__BLND_UPDATE_TAKEN_MASK 0x00000100L
++#define BLNDV0_BLNDV_UPDATE__BLND_UPDATE_LOCK_MASK 0x00010000L
++//BLNDV0_BLNDV_UNDERFLOW_INTERRUPT
++#define BLNDV0_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0
++#define BLNDV0_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8
++#define BLNDV0_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc
++#define BLNDV0_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10
++#define BLNDV0_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x00000001L
++#define BLNDV0_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x00000100L
++#define BLNDV0_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x00001000L
++#define BLNDV0_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x00030000L
++//BLNDV0_BLNDV_V_UPDATE_LOCK
++#define BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0
++#define BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1
++#define BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10
++#define BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c
++#define BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT 0x1d
++#define BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT 0x1f
++#define BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x00000001L
++#define BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x00000002L
++#define BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x00010000L
++#define BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000L
++#define BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK 0x20000000L
++#define BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK 0x80000000L
++//BLNDV0_BLNDV_REG_UPDATE_STATUS
++#define BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT 0x0
++#define BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT 0x1
++#define BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2
++#define BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3
++#define BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT 0x6
++#define BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT 0x7
++#define BLNDV0_BLNDV_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT 0x8
++#define BLNDV0_BLNDV_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT 0x9
++#define BLNDV0_BLNDV_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT 0xa
++#define BLNDV0_BLNDV_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT 0xb
++#define BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK 0x00000001L
++#define BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK 0x00000002L
++#define BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK 0x00000004L
++#define BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK 0x00000008L
++#define BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK 0x00000040L
++#define BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK 0x00000080L
++#define BLNDV0_BLNDV_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK 0x00000100L
++#define BLNDV0_BLNDV_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK 0x00000200L
++#define BLNDV0_BLNDV_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK 0x00000400L
++#define BLNDV0_BLNDV_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK 0x00000800L
++
++
++// addressBlock: dce_dc_crtcv0_dispdec
++//CRTCV0_CRTCV_H_BLANK_EARLY_NUM
++#define CRTCV0_CRTCV_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0
++#define CRTCV0_CRTCV_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10
++#define CRTCV0_CRTCV_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x000003FFL
++#define CRTCV0_CRTCV_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x00010000L
++//CRTCV0_CRTCV_H_TOTAL
++#define CRTCV0_CRTCV_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0
++#define CRTCV0_CRTCV_H_TOTAL__CRTC_H_TOTAL_MASK 0x00003FFFL
++//CRTCV0_CRTCV_H_BLANK_START_END
++#define CRTCV0_CRTCV_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0
++#define CRTCV0_CRTCV_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10
++#define CRTCV0_CRTCV_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x00003FFFL
++#define CRTCV0_CRTCV_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3FFF0000L
++//CRTCV0_CRTCV_H_SYNC_A
++#define CRTCV0_CRTCV_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0
++#define CRTCV0_CRTCV_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10
++#define CRTCV0_CRTCV_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x00003FFFL
++#define CRTCV0_CRTCV_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3FFF0000L
++//CRTCV0_CRTCV_H_SYNC_A_CNTL
++#define CRTCV0_CRTCV_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0
++#define CRTCV0_CRTCV_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10
++#define CRTCV0_CRTCV_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11
++#define CRTCV0_CRTCV_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x00000001L
++#define CRTCV0_CRTCV_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x00010000L
++#define CRTCV0_CRTCV_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x00020000L
++//CRTCV0_CRTCV_H_SYNC_B
++#define CRTCV0_CRTCV_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0
++#define CRTCV0_CRTCV_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10
++#define CRTCV0_CRTCV_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x00003FFFL
++#define CRTCV0_CRTCV_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x3FFF0000L
++//CRTCV0_CRTCV_H_SYNC_B_CNTL
++#define CRTCV0_CRTCV_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0
++#define CRTCV0_CRTCV_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10
++#define CRTCV0_CRTCV_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11
++#define CRTCV0_CRTCV_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x00000001L
++#define CRTCV0_CRTCV_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x00010000L
++#define CRTCV0_CRTCV_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x00020000L
++//CRTCV0_CRTCV_VBI_END
++#define CRTCV0_CRTCV_VBI_END__CRTC_VBI_V_END__SHIFT 0x0
++#define CRTCV0_CRTCV_VBI_END__CRTC_VBI_H_END__SHIFT 0x10
++#define CRTCV0_CRTCV_VBI_END__CRTC_VBI_V_END_MASK 0x00003FFFL
++#define CRTCV0_CRTCV_VBI_END__CRTC_VBI_H_END_MASK 0x3FFF0000L
++//CRTCV0_CRTCV_V_TOTAL
++#define CRTCV0_CRTCV_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0
++#define CRTCV0_CRTCV_V_TOTAL__CRTC_V_TOTAL_MASK 0x00003FFFL
++//CRTCV0_CRTCV_V_TOTAL_MIN
++#define CRTCV0_CRTCV_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0
++#define CRTCV0_CRTCV_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x00003FFFL
++//CRTCV0_CRTCV_V_TOTAL_MAX
++#define CRTCV0_CRTCV_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0
++#define CRTCV0_CRTCV_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10
++#define CRTCV0_CRTCV_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x00003FFFL
++#define CRTCV0_CRTCV_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x00010000L
++//CRTCV0_CRTCV_V_TOTAL_CONTROL
++#define CRTCV0_CRTCV_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0
++#define CRTCV0_CRTCV_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4
++#define CRTCV0_CRTCV_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8
++#define CRTCV0_CRTCV_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc
++#define CRTCV0_CRTCV_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf
++#define CRTCV0_CRTCV_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10
++#define CRTCV0_CRTCV_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x00000001L
++#define CRTCV0_CRTCV_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x00000010L
++#define CRTCV0_CRTCV_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x00000100L
++#define CRTCV0_CRTCV_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x00001000L
++#define CRTCV0_CRTCV_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00008000L
++#define CRTCV0_CRTCV_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L
++//CRTCV0_CRTCV_V_TOTAL_INT_STATUS
++#define CRTCV0_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0
++#define CRTCV0_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4
++#define CRTCV0_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8
++#define CRTCV0_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc
++#define CRTCV0_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L
++#define CRTCV0_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L
++#define CRTCV0_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L
++#define CRTCV0_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L
++//CRTCV0_CRTCV_VSYNC_NOM_INT_STATUS
++#define CRTCV0_CRTCV_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0
++#define CRTCV0_CRTCV_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4
++#define CRTCV0_CRTCV_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x00000001L
++#define CRTCV0_CRTCV_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L
++//CRTCV0_CRTCV_V_BLANK_START_END
++#define CRTCV0_CRTCV_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0
++#define CRTCV0_CRTCV_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10
++#define CRTCV0_CRTCV_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x00003FFFL
++#define CRTCV0_CRTCV_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3FFF0000L
++//CRTCV0_CRTCV_V_SYNC_A
++#define CRTCV0_CRTCV_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0
++#define CRTCV0_CRTCV_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10
++#define CRTCV0_CRTCV_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x00003FFFL
++#define CRTCV0_CRTCV_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3FFF0000L
++//CRTCV0_CRTCV_V_SYNC_A_CNTL
++#define CRTCV0_CRTCV_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0
++#define CRTCV0_CRTCV_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x00000001L
++//CRTCV0_CRTCV_V_SYNC_B
++#define CRTCV0_CRTCV_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0
++#define CRTCV0_CRTCV_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10
++#define CRTCV0_CRTCV_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x00003FFFL
++#define CRTCV0_CRTCV_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x3FFF0000L
++//CRTCV0_CRTCV_V_SYNC_B_CNTL
++#define CRTCV0_CRTCV_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0
++#define CRTCV0_CRTCV_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x00000001L
++//CRTCV0_CRTCV_DTMTEST_CNTL
++#define CRTCV0_CRTCV_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0
++#define CRTCV0_CRTCV_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1
++#define CRTCV0_CRTCV_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x00000001L
++#define CRTCV0_CRTCV_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x0000001EL
++//CRTCV0_CRTCV_DTMTEST_STATUS_POSITION
++#define CRTCV0_CRTCV_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0
++#define CRTCV0_CRTCV_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10
++#define CRTCV0_CRTCV_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x00003FFFL
++#define CRTCV0_CRTCV_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x3FFF0000L
++//CRTCV0_CRTCV_TRIGA_CNTL
++#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0
++#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5
++#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8
++#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9
++#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa
++#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb
++#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
++#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
++#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14
++#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18
++#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f
++#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x0000001FL
++#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0x000000E0L
++#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000100L
++#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x00000200L
++#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x00000400L
++#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x00000800L
++#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
++#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
++#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L
++#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1F000000L
++#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000L
++//CRTCV0_CRTCV_TRIGA_MANUAL_TRIG
++#define CRTCV0_CRTCV_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0
++#define CRTCV0_CRTCV_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x00000001L
++//CRTCV0_CRTCV_TRIGB_CNTL
++#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0
++#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5
++#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8
++#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9
++#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa
++#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb
++#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
++#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
++#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14
++#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18
++#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f
++#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x0000001FL
++#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0x000000E0L
++#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000100L
++#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x00000200L
++#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x00000400L
++#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x00000800L
++#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
++#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
++#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L
++#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1F000000L
++#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000L
++//CRTCV0_CRTCV_TRIGB_MANUAL_TRIG
++#define CRTCV0_CRTCV_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0
++#define CRTCV0_CRTCV_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x00000001L
++//CRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL
++#define CRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0
++#define CRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4
++#define CRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8
++#define CRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10
++#define CRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18
++#define CRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x00000003L
++#define CRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L
++#define CRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L
++#define CRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L
++#define CRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L
++//CRTCV0_CRTCV_FLOW_CONTROL
++#define CRTCV0_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0
++#define CRTCV0_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8
++#define CRTCV0_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10
++#define CRTCV0_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18
++#define CRTCV0_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL
++#define CRTCV0_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x00000100L
++#define CRTCV0_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L
++#define CRTCV0_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L
++//CRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE
++#define CRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0
++#define CRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER__SHIFT 0x8
++#define CRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER__SHIFT 0x10
++#define CRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L
++#define CRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L
++#define CRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L
++//CRTCV0_CRTCV_AVSYNC_COUNTER
++#define CRTCV0_CRTCV_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER__SHIFT 0x0
++#define CRTCV0_CRTCV_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER_MASK 0xFFFFFFFFL
++//CRTCV0_CRTCV_CONTROL
++#define CRTCV0_CRTCV_CONTROL__CRTC_MASTER_EN__SHIFT 0x0
++#define CRTCV0_CRTCV_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4
++#define CRTCV0_CRTCV_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8
++#define CRTCV0_CRTCV_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc
++#define CRTCV0_CRTCV_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd
++#define CRTCV0_CRTCV_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe
++#define CRTCV0_CRTCV_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10
++#define CRTCV0_CRTCV_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14
++#define CRTCV0_CRTCV_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d
++#define CRTCV0_CRTCV_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e
++#define CRTCV0_CRTCV_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f
++#define CRTCV0_CRTCV_CONTROL__CRTC_MASTER_EN_MASK 0x00000001L
++#define CRTCV0_CRTCV_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x00000010L
++#define CRTCV0_CRTCV_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x00000300L
++#define CRTCV0_CRTCV_CONTROL__CRTC_START_POINT_CNTL_MASK 0x00001000L
++#define CRTCV0_CRTCV_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x00002000L
++#define CRTCV0_CRTCV_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x00004000L
++#define CRTCV0_CRTCV_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x00010000L
++#define CRTCV0_CRTCV_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x00700000L
++#define CRTCV0_CRTCV_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000L
++#define CRTCV0_CRTCV_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L
++#define CRTCV0_CRTCV_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L
++//CRTCV0_CRTCV_BLANK_CONTROL
++#define CRTCV0_CRTCV_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0
++#define CRTCV0_CRTCV_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8
++#define CRTCV0_CRTCV_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10
++#define CRTCV0_CRTCV_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x00000001L
++#define CRTCV0_CRTCV_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x00000100L
++#define CRTCV0_CRTCV_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x00010000L
++//CRTCV0_CRTCV_INTERLACE_CONTROL
++#define CRTCV0_CRTCV_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0
++#define CRTCV0_CRTCV_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10
++#define CRTCV0_CRTCV_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x00000001L
++#define CRTCV0_CRTCV_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L
++//CRTCV0_CRTCV_INTERLACE_STATUS
++#define CRTCV0_CRTCV_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0
++#define CRTCV0_CRTCV_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1
++#define CRTCV0_CRTCV_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x00000001L
++#define CRTCV0_CRTCV_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x00000002L
++//CRTCV0_CRTCV_FIELD_INDICATION_CONTROL
++#define CRTCV0_CRTCV_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0
++#define CRTCV0_CRTCV_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1
++#define CRTCV0_CRTCV_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x00000001L
++#define CRTCV0_CRTCV_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x00000002L
++//CRTCV0_CRTCV_PIXEL_DATA_READBACK0
++#define CRTCV0_CRTCV_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0
++#define CRTCV0_CRTCV_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10
++#define CRTCV0_CRTCV_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0x00000FFFL
++#define CRTCV0_CRTCV_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0x0FFF0000L
++//CRTCV0_CRTCV_PIXEL_DATA_READBACK1
++#define CRTCV0_CRTCV_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0
++#define CRTCV0_CRTCV_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0x00000FFFL
++//CRTCV0_CRTCV_STATUS
++#define CRTCV0_CRTCV_STATUS__CRTC_V_BLANK__SHIFT 0x0
++#define CRTCV0_CRTCV_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1
++#define CRTCV0_CRTCV_STATUS__CRTC_V_SYNC_A__SHIFT 0x2
++#define CRTCV0_CRTCV_STATUS__CRTC_V_UPDATE__SHIFT 0x3
++#define CRTCV0_CRTCV_STATUS__CRTC_V_START_LINE__SHIFT 0x4
++#define CRTCV0_CRTCV_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5
++#define CRTCV0_CRTCV_STATUS__CRTC_H_BLANK__SHIFT 0x10
++#define CRTCV0_CRTCV_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11
++#define CRTCV0_CRTCV_STATUS__CRTC_H_SYNC_A__SHIFT 0x12
++#define CRTCV0_CRTCV_STATUS__CRTC_V_BLANK_MASK 0x00000001L
++#define CRTCV0_CRTCV_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x00000002L
++#define CRTCV0_CRTCV_STATUS__CRTC_V_SYNC_A_MASK 0x00000004L
++#define CRTCV0_CRTCV_STATUS__CRTC_V_UPDATE_MASK 0x00000008L
++#define CRTCV0_CRTCV_STATUS__CRTC_V_START_LINE_MASK 0x00000010L
++#define CRTCV0_CRTCV_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x00000020L
++#define CRTCV0_CRTCV_STATUS__CRTC_H_BLANK_MASK 0x00010000L
++#define CRTCV0_CRTCV_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x00020000L
++#define CRTCV0_CRTCV_STATUS__CRTC_H_SYNC_A_MASK 0x00040000L
++//CRTCV0_CRTCV_STATUS_POSITION
++#define CRTCV0_CRTCV_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0
++#define CRTCV0_CRTCV_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10
++#define CRTCV0_CRTCV_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x00003FFFL
++#define CRTCV0_CRTCV_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x3FFF0000L
++//CRTCV0_CRTCV_NOM_VERT_POSITION
++#define CRTCV0_CRTCV_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0
++#define CRTCV0_CRTCV_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x00003FFFL
++//CRTCV0_CRTCV_STATUS_FRAME_COUNT
++#define CRTCV0_CRTCV_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0
++#define CRTCV0_CRTCV_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0x00FFFFFFL
++//CRTCV0_CRTCV_STATUS_VF_COUNT
++#define CRTCV0_CRTCV_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0
++#define CRTCV0_CRTCV_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x3FFFFFFFL
++//CRTCV0_CRTCV_STATUS_HV_COUNT
++#define CRTCV0_CRTCV_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0
++#define CRTCV0_CRTCV_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x3FFFFFFFL
++//CRTCV0_CRTCV_COUNT_CONTROL
++#define CRTCV0_CRTCV_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0
++#define CRTCV0_CRTCV_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1
++#define CRTCV0_CRTCV_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x00000001L
++#define CRTCV0_CRTCV_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x0000001EL
++//CRTCV0_CRTCV_COUNT_RESET
++#define CRTCV0_CRTCV_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0
++#define CRTCV0_CRTCV_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x00000001L
++//CRTCV0_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE
++#define CRTCV0_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0
++#define CRTCV0_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L
++//CRTCV0_CRTCV_VERT_SYNC_CONTROL
++#define CRTCV0_CRTCV_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0
++#define CRTCV0_CRTCV_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8
++#define CRTCV0_CRTCV_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10
++#define CRTCV0_CRTCV_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L
++#define CRTCV0_CRTCV_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L
++#define CRTCV0_CRTCV_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L
++//CRTCV0_CRTCV_STEREO_STATUS
++#define CRTCV0_CRTCV_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0
++#define CRTCV0_CRTCV_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8
++#define CRTCV0_CRTCV_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10
++#define CRTCV0_CRTCV_STEREO_STATUS__CRTC_STEREO_EYE_FLAG__SHIFT 0x14
++#define CRTCV0_CRTCV_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18
++#define CRTCV0_CRTCV_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x00000001L
++#define CRTCV0_CRTCV_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x00000100L
++#define CRTCV0_CRTCV_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x00010000L
++#define CRTCV0_CRTCV_STEREO_STATUS__CRTC_STEREO_EYE_FLAG_MASK 0x00100000L
++#define CRTCV0_CRTCV_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L
++//CRTCV0_CRTCV_STEREO_CONTROL
++#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0
++#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf
++#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10
++#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11
++#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12
++#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM__SHIFT 0x13
++#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14
++#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18
++#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00003FFFL
++#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L
++#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x00010000L
++#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L
++#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L
++#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM_MASK 0x00080000L
++#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L
++#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x01000000L
++//CRTCV0_CRTCV_SNAPSHOT_STATUS
++#define CRTCV0_CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0
++#define CRTCV0_CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1
++#define CRTCV0_CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2
++#define CRTCV0_CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x00000001L
++#define CRTCV0_CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x00000002L
++#define CRTCV0_CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L
++//CRTCV0_CRTCV_SNAPSHOT_CONTROL
++#define CRTCV0_CRTCV_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0
++#define CRTCV0_CRTCV_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L
++//CRTCV0_CRTCV_SNAPSHOT_POSITION
++#define CRTCV0_CRTCV_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0
++#define CRTCV0_CRTCV_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10
++#define CRTCV0_CRTCV_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x00003FFFL
++#define CRTCV0_CRTCV_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x3FFF0000L
++//CRTCV0_CRTCV_SNAPSHOT_FRAME
++#define CRTCV0_CRTCV_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0
++#define CRTCV0_CRTCV_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL
++//CRTCV0_CRTCV_START_LINE_CONTROL
++#define CRTCV0_CRTCV_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0
++#define CRTCV0_CRTCV_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x1
++#define CRTCV0_CRTCV_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x2
++#define CRTCV0_CRTCV_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x8
++#define CRTCV0_CRTCV_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc
++#define CRTCV0_CRTCV_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x00000001L
++#define CRTCV0_CRTCV_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x00000002L
++#define CRTCV0_CRTCV_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x00000004L
++#define CRTCV0_CRTCV_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x00000100L
++#define CRTCV0_CRTCV_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0x000FF000L
++//CRTCV0_CRTCV_INTERRUPT_CONTROL
++#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0
++#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1
++#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4
++#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5
++#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8
++#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9
++#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10
++#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11
++#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18
++#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19
++#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a
++#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b
++#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c
++#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d
++#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e
++#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f
++#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x00000001L
++#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x00000002L
++#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x00000010L
++#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x00000020L
++#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L
++#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L
++#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L
++#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L
++#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x01000000L
++#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x02000000L
++#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x04000000L
++#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x08000000L
++#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000L
++#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000L
++#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L
++#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L
++//CRTCV0_CRTCV_UPDATE_LOCK
++#define CRTCV0_CRTCV_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0
++#define CRTCV0_CRTCV_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x00000001L
++//CRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL
++#define CRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0
++#define CRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8
++#define CRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10
++#define CRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18
++#define CRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x19
++#define CRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x00000001L
++#define CRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x00000100L
++#define CRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L
++#define CRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x01000000L
++#define CRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x02000000L
++//CRTCV0_CRTCV_VGA_PARAMETER_CAPTURE_MODE
++#define CRTCV0_CRTCV_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0
++#define CRTCV0_CRTCV_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x00000001L
++//CRTCV0_CRTCV_TEST_PATTERN_CONTROL
++#define CRTCV0_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0
++#define CRTCV0_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8
++#define CRTCV0_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10
++#define CRTCV0_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18
++#define CRTCV0_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x00000001L
++#define CRTCV0_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x00000700L
++#define CRTCV0_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L
++#define CRTCV0_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xFF000000L
++//CRTCV0_CRTCV_TEST_PATTERN_PARAMETERS
++#define CRTCV0_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0
++#define CRTCV0_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4
++#define CRTCV0_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8
++#define CRTCV0_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc
++#define CRTCV0_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10
++#define CRTCV0_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0x0000000FL
++#define CRTCV0_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0x000000F0L
++#define CRTCV0_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0x00000F00L
++#define CRTCV0_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0x0000F000L
++#define CRTCV0_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xFFFF0000L
++//CRTCV0_CRTCV_TEST_PATTERN_COLOR
++#define CRTCV0_CRTCV_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0
++#define CRTCV0_CRTCV_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10
++#define CRTCV0_CRTCV_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0x0000FFFFL
++#define CRTCV0_CRTCV_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x003F0000L
++//CRTCV0_CRTCV_MASTER_UPDATE_LOCK
++#define CRTCV0_CRTCV_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0
++#define CRTCV0_CRTCV_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8
++#define CRTCV0_CRTCV_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK__SHIFT 0x10
++#define CRTCV0_CRTCV_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x00000001L
++#define CRTCV0_CRTCV_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x00000100L
++#define CRTCV0_CRTCV_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK_MASK 0x00010000L
++//CRTCV0_CRTCV_MASTER_UPDATE_MODE
++#define CRTCV0_CRTCV_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0
++#define CRTCV0_CRTCV_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10
++#define CRTCV0_CRTCV_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x00000007L
++#define CRTCV0_CRTCV_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00030000L
++//CRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT
++#define CRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0
++#define CRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8
++#define CRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x00000003L
++#define CRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xFFFFFF00L
++//CRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER
++#define CRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0
++#define CRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0x000000FFL
++//CRTCV0_CRTCV_MVP_STATUS
++#define CRTCV0_CRTCV_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0
++#define CRTCV0_CRTCV_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4
++#define CRTCV0_CRTCV_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10
++#define CRTCV0_CRTCV_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14
++#define CRTCV0_CRTCV_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x00000001L
++#define CRTCV0_CRTCV_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x00000010L
++#define CRTCV0_CRTCV_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x00010000L
++#define CRTCV0_CRTCV_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x00100000L
++//CRTCV0_CRTCV_MASTER_EN
++#define CRTCV0_CRTCV_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0
++#define CRTCV0_CRTCV_MASTER_EN__CRTC_MASTER_EN_MASK 0x00000001L
++//CRTCV0_CRTCV_ALLOW_STOP_OFF_V_CNT
++#define CRTCV0_CRTCV_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0
++#define CRTCV0_CRTCV_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10
++#define CRTCV0_CRTCV_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0x000000FFL
++#define CRTCV0_CRTCV_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x00010000L
++//CRTCV0_CRTCV_V_UPDATE_INT_STATUS
++#define CRTCV0_CRTCV_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0
++#define CRTCV0_CRTCV_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8
++#define CRTCV0_CRTCV_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x00000001L
++#define CRTCV0_CRTCV_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x00000100L
++//CRTCV0_CRTCV_OVERSCAN_COLOR
++#define CRTCV0_CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0
++#define CRTCV0_CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa
++#define CRTCV0_CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14
++#define CRTCV0_CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x000003FFL
++#define CRTCV0_CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0x000FFC00L
++#define CRTCV0_CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3FF00000L
++//CRTCV0_CRTCV_OVERSCAN_COLOR_EXT
++#define CRTCV0_CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0
++#define CRTCV0_CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8
++#define CRTCV0_CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10
++#define CRTCV0_CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x00000003L
++#define CRTCV0_CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x00000300L
++#define CRTCV0_CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x00030000L
++//CRTCV0_CRTCV_BLANK_DATA_COLOR
++#define CRTCV0_CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0
++#define CRTCV0_CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa
++#define CRTCV0_CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14
++#define CRTCV0_CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL
++#define CRTCV0_CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L
++#define CRTCV0_CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L
++//CRTCV0_CRTCV_BLANK_DATA_COLOR_EXT
++#define CRTCV0_CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0
++#define CRTCV0_CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8
++#define CRTCV0_CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10
++#define CRTCV0_CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x00000003L
++#define CRTCV0_CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00000300L
++#define CRTCV0_CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x00030000L
++//CRTCV0_CRTCV_BLACK_COLOR
++#define CRTCV0_CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0
++#define CRTCV0_CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa
++#define CRTCV0_CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14
++#define CRTCV0_CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x000003FFL
++#define CRTCV0_CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0x000FFC00L
++#define CRTCV0_CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3FF00000L
++//CRTCV0_CRTCV_BLACK_COLOR_EXT
++#define CRTCV0_CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0
++#define CRTCV0_CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8
++#define CRTCV0_CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10
++#define CRTCV0_CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x00000003L
++#define CRTCV0_CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x00000300L
++#define CRTCV0_CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x00030000L
++//CRTCV0_CRTCV_VERTICAL_INTERRUPT0_POSITION
++#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0
++#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10
++#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00003FFFL
++#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x3FFF0000L
++//CRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL
++#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4
++#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8
++#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc
++#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10
++#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14
++#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18
++#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L
++#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L
++#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L
++#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L
++#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L
++#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L
++//CRTCV0_CRTCV_VERTICAL_INTERRUPT1_POSITION
++#define CRTCV0_CRTCV_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0
++#define CRTCV0_CRTCV_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00003FFFL
++//CRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL
++#define CRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8
++#define CRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc
++#define CRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10
++#define CRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14
++#define CRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18
++#define CRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L
++#define CRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L
++#define CRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L
++#define CRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L
++#define CRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L
++//CRTCV0_CRTCV_VERTICAL_INTERRUPT2_POSITION
++#define CRTCV0_CRTCV_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0
++#define CRTCV0_CRTCV_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00003FFFL
++//CRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL
++#define CRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8
++#define CRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc
++#define CRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10
++#define CRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14
++#define CRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18
++#define CRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L
++#define CRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L
++#define CRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L
++#define CRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L
++#define CRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L
++//CRTCV0_CRTCV_CRC_CNTL
++#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0
++#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4
++#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8
++#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc
++#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
++#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14
++#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18
++#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC_EN_MASK 0x00000001L
++#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x00000010L
++#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x00000300L
++#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x00003000L
++#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
++#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x00700000L
++#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x07000000L
++//CRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL
++#define CRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0
++#define CRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10
++#define CRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x00003FFFL
++#define CRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3FFF0000L
++//CRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL
++#define CRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0
++#define CRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10
++#define CRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x00003FFFL
++#define CRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3FFF0000L
++//CRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL
++#define CRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0
++#define CRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10
++#define CRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x00003FFFL
++#define CRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3FFF0000L
++//CRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL
++#define CRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0
++#define CRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10
++#define CRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x00003FFFL
++#define CRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3FFF0000L
++//CRTCV0_CRTCV_CRC0_DATA_RG
++#define CRTCV0_CRTCV_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0
++#define CRTCV0_CRTCV_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10
++#define CRTCV0_CRTCV_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL
++#define CRTCV0_CRTCV_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L
++//CRTCV0_CRTCV_CRC0_DATA_B
++#define CRTCV0_CRTCV_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0
++#define CRTCV0_CRTCV_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL
++//CRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL
++#define CRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0
++#define CRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10
++#define CRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x00003FFFL
++#define CRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3FFF0000L
++//CRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL
++#define CRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0
++#define CRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10
++#define CRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x00003FFFL
++#define CRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3FFF0000L
++//CRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL
++#define CRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0
++#define CRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10
++#define CRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x00003FFFL
++#define CRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3FFF0000L
++//CRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL
++#define CRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0
++#define CRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10
++#define CRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x00003FFFL
++#define CRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3FFF0000L
++//CRTCV0_CRTCV_CRC1_DATA_RG
++#define CRTCV0_CRTCV_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0
++#define CRTCV0_CRTCV_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10
++#define CRTCV0_CRTCV_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL
++#define CRTCV0_CRTCV_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L
++//CRTCV0_CRTCV_CRC1_DATA_B
++#define CRTCV0_CRTCV_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0
++#define CRTCV0_CRTCV_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL
++//CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE__SHIFT 0x0
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__SHIFT 0x3
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__SHIFT 0x4
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__SHIFT 0x5
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__SHIFT 0x8
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__SHIFT 0x9
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__SHIFT 0xc
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__SHIFT 0xd
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__SHIFT 0xe
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE__SHIFT 0x18
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE__SHIFT 0x1c
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE_MASK 0x00000003L
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_MASK 0x00000008L
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_MASK 0x00000010L
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_MASK 0x00000060L
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_MASK 0x00000100L
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_MASK 0x00000200L
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_MASK 0x00001000L
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_MASK 0x00002000L
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_MASK 0x00004000L
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE_MASK 0x07000000L
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE_MASK 0x70000000L
++//CRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_START
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X__SHIFT 0x0
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y__SHIFT 0x10
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X_MASK 0x00003FFFL
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y_MASK 0x3FFF0000L
++//CRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_END
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X__SHIFT 0x0
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y__SHIFT 0x10
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X_MASK 0x00003FFFL
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y_MASK 0x3FFF0000L
++//CRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__SHIFT 0x0
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS__SHIFT 0x4
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS__SHIFT 0x8
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__SHIFT 0x10
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__SHIFT 0x14
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__SHIFT 0x1d
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_MASK 0x00000001L
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS_MASK 0x00000010L
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS_MASK 0x00000100L
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_MASK 0x00010000L
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_MASK 0x00100000L
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_MASK 0xE0000000L
++//CRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE__SHIFT 0x0
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS__SHIFT 0x4
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS__SHIFT 0x8
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR__SHIFT 0x10
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE__SHIFT 0x14
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE_MASK 0x00000001L
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS_MASK 0x00000010L
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS_MASK 0x00000100L
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR_MASK 0x00010000L
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE_MASK 0x00100000L
++//CRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__SHIFT 0x0
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS__SHIFT 0x4
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS__SHIFT 0x8
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__SHIFT 0x10
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__SHIFT 0x14
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_MASK 0x00000001L
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS_MASK 0x00000010L
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS_MASK 0x00000100L
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_MASK 0x00010000L
++#define CRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_MASK 0x00100000L
++//CRTCV0_CRTCV_STATIC_SCREEN_CONTROL
++#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0
++#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10
++#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18
++#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19
++#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a
++#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b
++#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c
++#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL
++#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L
++#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x01000000L
++#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x02000000L
++#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x04000000L
++#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x08000000L
++#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000L
++//CRTCV0_CRTCV_3D_STRUCTURE_CONTROL
++#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0
++#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4
++#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8
++#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc
++#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10
++#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11
++#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12
++#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x00000001L
++#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x00000010L
++#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L
++#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L
++#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L
++#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L
++#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L
++//CRTCV0_CRTCV_GSL_VSYNC_GAP
++#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0
++#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8
++#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10
++#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11
++#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13
++#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14
++#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17
++#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18
++#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL
++#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L
++#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L
++#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x00060000L
++#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L
++#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L
++#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L
++#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xFF000000L
++//CRTCV0_CRTCV_GSL_WINDOW
++#define CRTCV0_CRTCV_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0
++#define CRTCV0_CRTCV_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10
++#define CRTCV0_CRTCV_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x00003FFFL
++#define CRTCV0_CRTCV_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x3FFF0000L
++//CRTCV0_CRTCV_GSL_CONTROL
++#define CRTCV0_CRTCV_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0
++#define CRTCV0_CRTCV_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10
++#define CRTCV0_CRTCV_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c
++#define CRTCV0_CRTCV_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x00003FFFL
++#define CRTCV0_CRTCV_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x001F0000L
++#define CRTCV0_CRTCV_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L
++
++
++// addressBlock: dce_dc_unp1_dispdec
++//UNP1_UNP_GRPH_ENABLE
++#define UNP1_UNP_GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0
++#define UNP1_UNP_GRPH_ENABLE__GRPH_ENABLE_MASK 0x00000001L
++//UNP1_UNP_GRPH_CONTROL
++#define UNP1_UNP_GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0
++#define UNP1_UNP_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x2
++#define UNP1_UNP_GRPH_CONTROL__GRPH_Z__SHIFT 0x4
++#define UNP1_UNP_GRPH_CONTROL__GRPH_BANK_WIDTH_L__SHIFT 0x6
++#define UNP1_UNP_GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8
++#define UNP1_UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT_L__SHIFT 0xb
++#define UNP1_UNP_GRPH_CONTROL__GRPH_TILE_SPLIT_L__SHIFT 0xd
++#define UNP1_UNP_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10
++#define UNP1_UNP_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11
++#define UNP1_UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_L__SHIFT 0x12
++#define UNP1_UNP_GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x14
++#define UNP1_UNP_GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT 0x18
++#define UNP1_UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE_L__SHIFT 0x1d
++#define UNP1_UNP_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f
++#define UNP1_UNP_GRPH_CONTROL__GRPH_DEPTH_MASK 0x00000003L
++#define UNP1_UNP_GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0x0000000CL
++#define UNP1_UNP_GRPH_CONTROL__GRPH_Z_MASK 0x00000030L
++#define UNP1_UNP_GRPH_CONTROL__GRPH_BANK_WIDTH_L_MASK 0x000000C0L
++#define UNP1_UNP_GRPH_CONTROL__GRPH_FORMAT_MASK 0x00000700L
++#define UNP1_UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT_L_MASK 0x00001800L
++#define UNP1_UNP_GRPH_CONTROL__GRPH_TILE_SPLIT_L_MASK 0x0000E000L
++#define UNP1_UNP_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x00010000L
++#define UNP1_UNP_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x00020000L
++#define UNP1_UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_L_MASK 0x000C0000L
++#define UNP1_UNP_GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0x00F00000L
++#define UNP1_UNP_GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1F000000L
++#define UNP1_UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE_L_MASK 0x60000000L
++#define UNP1_UNP_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000L
++//UNP1_UNP_GRPH_CONTROL_C
++#define UNP1_UNP_GRPH_CONTROL_C__GRPH_BANK_WIDTH_C__SHIFT 0x6
++#define UNP1_UNP_GRPH_CONTROL_C__GRPH_BANK_HEIGHT_C__SHIFT 0xb
++#define UNP1_UNP_GRPH_CONTROL_C__GRPH_TILE_SPLIT_C__SHIFT 0xd
++#define UNP1_UNP_GRPH_CONTROL_C__GRPH_MACRO_TILE_ASPECT_C__SHIFT 0x12
++#define UNP1_UNP_GRPH_CONTROL_C__GRPH_MICRO_TILE_MODE_C__SHIFT 0x1d
++#define UNP1_UNP_GRPH_CONTROL_C__GRPH_BANK_WIDTH_C_MASK 0x000000C0L
++#define UNP1_UNP_GRPH_CONTROL_C__GRPH_BANK_HEIGHT_C_MASK 0x00001800L
++#define UNP1_UNP_GRPH_CONTROL_C__GRPH_TILE_SPLIT_C_MASK 0x0000E000L
++#define UNP1_UNP_GRPH_CONTROL_C__GRPH_MACRO_TILE_ASPECT_C_MASK 0x000C0000L
++#define UNP1_UNP_GRPH_CONTROL_C__GRPH_MICRO_TILE_MODE_C_MASK 0x60000000L
++//UNP1_UNP_GRPH_CONTROL_EXP
++#define UNP1_UNP_GRPH_CONTROL_EXP__VIDEO_FORMAT__SHIFT 0x0
++#define UNP1_UNP_GRPH_CONTROL_EXP__VIDEO_FORMAT_MASK 0x00000007L
++//UNP1_UNP_GRPH_SWAP_CNTL
++#define UNP1_UNP_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0
++#define UNP1_UNP_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4
++#define UNP1_UNP_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6
++#define UNP1_UNP_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8
++#define UNP1_UNP_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x00000003L
++#define UNP1_UNP_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x00000030L
++#define UNP1_UNP_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0x000000C0L
++#define UNP1_UNP_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x00000300L
++//UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L
++#define UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L__SHIFT 0x8
++#define UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L_MASK 0xFFFFFF00L
++//UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C
++#define UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x8
++#define UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFF00L
++//UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L
++#define UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
++#define UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_MASK 0x000000FFL
++//UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C
++#define UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
++#define UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x000000FFL
++//UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L
++#define UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__SHIFT 0x8
++#define UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_MASK 0xFFFFFF00L
++//UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C
++#define UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__SHIFT 0x8
++#define UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_MASK 0xFFFFFF00L
++//UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L
++#define UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
++#define UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_MASK 0x000000FFL
++//UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C
++#define UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
++#define UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_MASK 0x000000FFL
++//UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L
++#define UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_SURFACE_ADDRESS_L__SHIFT 0x8
++#define UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_SURFACE_ADDRESS_L_MASK 0xFFFFFF00L
++//UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C
++#define UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x8
++#define UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFF00L
++//UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L
++#define UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
++#define UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_MASK 0x000000FFL
++//UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C
++#define UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
++#define UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x000000FFL
++//UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L
++#define UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__SHIFT 0x8
++#define UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_MASK 0xFFFFFF00L
++//UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C
++#define UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__SHIFT 0x8
++#define UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_MASK 0xFFFFFF00L
++//UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L
++#define UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
++#define UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_MASK 0x000000FFL
++//UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C
++#define UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
++#define UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_MASK 0x000000FFL
++//UNP1_UNP_GRPH_PITCH_L
++#define UNP1_UNP_GRPH_PITCH_L__GRPH_PITCH_L__SHIFT 0x0
++#define UNP1_UNP_GRPH_PITCH_L__GRPH_PITCH_L_MASK 0x00007FFFL
++//UNP1_UNP_GRPH_PITCH_C
++#define UNP1_UNP_GRPH_PITCH_C__GRPH_PITCH_C__SHIFT 0x0
++#define UNP1_UNP_GRPH_PITCH_C__GRPH_PITCH_C_MASK 0x00007FFFL
++//UNP1_UNP_GRPH_SURFACE_OFFSET_X_L
++#define UNP1_UNP_GRPH_SURFACE_OFFSET_X_L__GRPH_SURFACE_OFFSET_X_L__SHIFT 0x0
++#define UNP1_UNP_GRPH_SURFACE_OFFSET_X_L__GRPH_SURFACE_OFFSET_X_L_MASK 0x00003FFFL
++//UNP1_UNP_GRPH_SURFACE_OFFSET_X_C
++#define UNP1_UNP_GRPH_SURFACE_OFFSET_X_C__GRPH_SURFACE_OFFSET_X_C__SHIFT 0x0
++#define UNP1_UNP_GRPH_SURFACE_OFFSET_X_C__GRPH_SURFACE_OFFSET_X_C_MASK 0x00003FFFL
++//UNP1_UNP_GRPH_SURFACE_OFFSET_Y_L
++#define UNP1_UNP_GRPH_SURFACE_OFFSET_Y_L__GRPH_SURFACE_OFFSET_Y_L__SHIFT 0x0
++#define UNP1_UNP_GRPH_SURFACE_OFFSET_Y_L__GRPH_SURFACE_OFFSET_Y_L_MASK 0x00003FFFL
++//UNP1_UNP_GRPH_SURFACE_OFFSET_Y_C
++#define UNP1_UNP_GRPH_SURFACE_OFFSET_Y_C__GRPH_SURFACE_OFFSET_Y_C__SHIFT 0x0
++#define UNP1_UNP_GRPH_SURFACE_OFFSET_Y_C__GRPH_SURFACE_OFFSET_Y_C_MASK 0x00003FFFL
++//UNP1_UNP_GRPH_X_START_L
++#define UNP1_UNP_GRPH_X_START_L__GRPH_X_START_L__SHIFT 0x0
++#define UNP1_UNP_GRPH_X_START_L__GRPH_X_START_L_MASK 0x00003FFFL
++//UNP1_UNP_GRPH_X_START_C
++#define UNP1_UNP_GRPH_X_START_C__GRPH_X_START_C__SHIFT 0x0
++#define UNP1_UNP_GRPH_X_START_C__GRPH_X_START_C_MASK 0x00003FFFL
++//UNP1_UNP_GRPH_Y_START_L
++#define UNP1_UNP_GRPH_Y_START_L__GRPH_Y_START_L__SHIFT 0x0
++#define UNP1_UNP_GRPH_Y_START_L__GRPH_Y_START_L_MASK 0x00003FFFL
++//UNP1_UNP_GRPH_Y_START_C
++#define UNP1_UNP_GRPH_Y_START_C__GRPH_Y_START_C__SHIFT 0x0
++#define UNP1_UNP_GRPH_Y_START_C__GRPH_Y_START_C_MASK 0x00003FFFL
++//UNP1_UNP_GRPH_X_END_L
++#define UNP1_UNP_GRPH_X_END_L__GRPH_X_END_L__SHIFT 0x0
++#define UNP1_UNP_GRPH_X_END_L__GRPH_X_END_L_MASK 0x00007FFFL
++//UNP1_UNP_GRPH_X_END_C
++#define UNP1_UNP_GRPH_X_END_C__GRPH_X_END_C__SHIFT 0x0
++#define UNP1_UNP_GRPH_X_END_C__GRPH_X_END_C_MASK 0x00007FFFL
++//UNP1_UNP_GRPH_Y_END_L
++#define UNP1_UNP_GRPH_Y_END_L__GRPH_Y_END_L__SHIFT 0x0
++#define UNP1_UNP_GRPH_Y_END_L__GRPH_Y_END_L_MASK 0x00007FFFL
++//UNP1_UNP_GRPH_Y_END_C
++#define UNP1_UNP_GRPH_Y_END_C__GRPH_Y_END_C__SHIFT 0x0
++#define UNP1_UNP_GRPH_Y_END_C__GRPH_Y_END_C_MASK 0x00007FFFL
++//UNP1_UNP_GRPH_UPDATE
++#define UNP1_UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0
++#define UNP1_UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1
++#define UNP1_UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2
++#define UNP1_UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3
++#define UNP1_UNP_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10
++#define UNP1_UNP_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14
++#define UNP1_UNP_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
++#define UNP1_UNP_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c
++#define UNP1_UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x00000001L
++#define UNP1_UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x00000002L
++#define UNP1_UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x00000004L
++#define UNP1_UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x00000008L
++#define UNP1_UNP_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x00010000L
++#define UNP1_UNP_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x00100000L
++#define UNP1_UNP_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
++#define UNP1_UNP_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000L
++//UNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT
++#define UNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L__SHIFT 0x0
++#define UNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C__SHIFT 0x8
++#define UNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L_MASK 0x000000FFL
++#define UNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C_MASK 0x0000FF00L
++//UNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L
++#define UNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L__GRPH_SURFACE_ADDRESS_INUSE_L__SHIFT 0x8
++#define UNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L__GRPH_SURFACE_ADDRESS_INUSE_L_MASK 0xFFFFFF00L
++//UNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C
++#define UNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C__GRPH_SURFACE_ADDRESS_INUSE_C__SHIFT 0x8
++#define UNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C__GRPH_SURFACE_ADDRESS_INUSE_C_MASK 0xFFFFFF00L
++//UNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L
++#define UNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__SHIFT 0x0
++#define UNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_MASK 0x000000FFL
++//UNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C
++#define UNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__SHIFT 0x0
++#define UNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_MASK 0x000000FFL
++//UNP1_UNP_DVMM_PTE_CONTROL
++#define UNP1_UNP_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT 0x0
++#define UNP1_UNP_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT 0x1
++#define UNP1_UNP_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT 0x5
++#define UNP1_UNP_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT 0x9
++#define UNP1_UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT 0x14
++#define UNP1_UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT 0x15
++#define UNP1_UNP_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK 0x00000001L
++#define UNP1_UNP_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK 0x0000001EL
++#define UNP1_UNP_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK 0x000001E0L
++#define UNP1_UNP_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK 0x0007FE00L
++#define UNP1_UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK 0x00100000L
++#define UNP1_UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK 0x00200000L
++//UNP1_UNP_DVMM_PTE_CONTROL_C
++#define UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_USE_SINGLE_PTE_C__SHIFT 0x0
++#define UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_WIDTH_C__SHIFT 0x1
++#define UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_HEIGHT_C__SHIFT 0x5
++#define UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_MIN_PTE_BEFORE_FLIP_C__SHIFT 0x9
++#define UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE0_C__SHIFT 0x14
++#define UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE1_C__SHIFT 0x15
++#define UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_USE_SINGLE_PTE_C_MASK 0x00000001L
++#define UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_WIDTH_C_MASK 0x0000001EL
++#define UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_HEIGHT_C_MASK 0x000001E0L
++#define UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_MIN_PTE_BEFORE_FLIP_C_MASK 0x0007FE00L
++#define UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE0_C_MASK 0x00100000L
++#define UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE1_C_MASK 0x00200000L
++//UNP1_UNP_DVMM_PTE_ARB_CONTROL
++#define UNP1_UNP_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT 0x0
++#define UNP1_UNP_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT 0x8
++#define UNP1_UNP_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK 0x0000003FL
++#define UNP1_UNP_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK 0x0000FF00L
++//UNP1_UNP_DVMM_PTE_ARB_CONTROL_C
++#define UNP1_UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_PTE_REQ_PER_CHUNK_C__SHIFT 0x0
++#define UNP1_UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_MAX_PTE_REQ_OUTSTANDING_C__SHIFT 0x8
++#define UNP1_UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_PTE_REQ_PER_CHUNK_C_MASK 0x0000003FL
++#define UNP1_UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_MAX_PTE_REQ_OUTSTANDING_C_MASK 0x0000FF00L
++//UNP1_UNP_GRPH_INTERRUPT_STATUS
++#define UNP1_UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0
++#define UNP1_UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8
++#define UNP1_UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x00000001L
++#define UNP1_UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x00000100L
++//UNP1_UNP_GRPH_INTERRUPT_CONTROL
++#define UNP1_UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0
++#define UNP1_UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8
++#define UNP1_UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x00000001L
++#define UNP1_UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x00000100L
++//UNP1_UNP_GRPH_STEREOSYNC_FLIP
++#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0
++#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x4
++#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_EN__SHIFT 0x8
++#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_MODE__SHIFT 0xc
++#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10
++#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11
++#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_BOTTOM_SURFACE_PENDING__SHIFT 0x12
++#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_BOTTOM_SURFACE_PENDING__SHIFT 0x13
++#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c
++#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x00000001L
++#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x00000030L
++#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_EN_MASK 0x00000100L
++#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_MODE_MASK 0x00003000L
++#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x00010000L
++#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x00020000L
++#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_BOTTOM_SURFACE_PENDING_MASK 0x00040000L
++#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_BOTTOM_SURFACE_PENDING_MASK 0x00080000L
++#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000L
++//UNP1_UNP_FLIP_CONTROL
++#define UNP1_UNP_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT 0x0
++#define UNP1_UNP_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK 0x00000001L
++//UNP1_UNP_CRC_CONTROL
++#define UNP1_UNP_CRC_CONTROL__UNP_CRC_ENABLE__SHIFT 0x0
++#define UNP1_UNP_CRC_CONTROL__UNP_CRC_SOURCE_SEL__SHIFT 0x2
++#define UNP1_UNP_CRC_CONTROL__UNP_CRC_LINE_SEL__SHIFT 0x8
++#define UNP1_UNP_CRC_CONTROL__UNP_CRC_ENABLE_MASK 0x00000001L
++#define UNP1_UNP_CRC_CONTROL__UNP_CRC_SOURCE_SEL_MASK 0x0000001CL
++#define UNP1_UNP_CRC_CONTROL__UNP_CRC_LINE_SEL_MASK 0x00000300L
++//UNP1_UNP_CRC_MASK
++#define UNP1_UNP_CRC_MASK__UNP_CRC_MASK__SHIFT 0x0
++#define UNP1_UNP_CRC_MASK__UNP_CRC_MASK_MASK 0xFFFFFFFFL
++//UNP1_UNP_CRC_CURRENT
++#define UNP1_UNP_CRC_CURRENT__UNP_CRC_CURRENT__SHIFT 0x0
++#define UNP1_UNP_CRC_CURRENT__UNP_CRC_CURRENT_MASK 0xFFFFFFFFL
++//UNP1_UNP_CRC_LAST
++#define UNP1_UNP_CRC_LAST__UNP_CRC_LAST__SHIFT 0x0
++#define UNP1_UNP_CRC_LAST__UNP_CRC_LAST_MASK 0xFFFFFFFFL
++//UNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK
++#define UNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK__UNP_LB_GAP_BETWEEN_CHUNK__SHIFT 0x4
++#define UNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK__UNP_LB_GAP_BETWEEN_CHUNK_MASK 0x000001F0L
++//UNP1_UNP_HW_ROTATION
++#define UNP1_UNP_HW_ROTATION__ROTATION_ANGLE__SHIFT 0x0
++#define UNP1_UNP_HW_ROTATION__PIXEL_DROP__SHIFT 0x4
++#define UNP1_UNP_HW_ROTATION__BUFFER_MODE__SHIFT 0x8
++#define UNP1_UNP_HW_ROTATION__ROTATION_ANGLE_MASK 0x00000007L
++#define UNP1_UNP_HW_ROTATION__PIXEL_DROP_MASK 0x00000010L
++#define UNP1_UNP_HW_ROTATION__BUFFER_MODE_MASK 0x00000100L
++
++
++// addressBlock: dce_dc_lbv1_dispdec
++//LBV1_LBV_DATA_FORMAT
++#define LBV1_LBV_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0
++#define LBV1_LBV_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2
++#define LBV1_LBV_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3
++#define LBV1_LBV_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4
++#define LBV1_LBV_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5
++#define LBV1_LBV_DATA_FORMAT__DITHER_EN__SHIFT 0x6
++#define LBV1_LBV_DATA_FORMAT__DOWNSCALE_PREFETCH_EN__SHIFT 0x7
++#define LBV1_LBV_DATA_FORMAT__PREFETCH__SHIFT 0xc
++#define LBV1_LBV_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18
++#define LBV1_LBV_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f
++#define LBV1_LBV_DATA_FORMAT__PIXEL_DEPTH_MASK 0x00000003L
++#define LBV1_LBV_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x00000004L
++#define LBV1_LBV_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000008L
++#define LBV1_LBV_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x00000010L
++#define LBV1_LBV_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x00000020L
++#define LBV1_LBV_DATA_FORMAT__DITHER_EN_MASK 0x00000040L
++#define LBV1_LBV_DATA_FORMAT__DOWNSCALE_PREFETCH_EN_MASK 0x00000080L
++#define LBV1_LBV_DATA_FORMAT__PREFETCH_MASK 0x00001000L
++#define LBV1_LBV_DATA_FORMAT__REQUEST_MODE_MASK 0x01000000L
++#define LBV1_LBV_DATA_FORMAT__ALPHA_EN_MASK 0x80000000L
++//LBV1_LBV_MEMORY_CTRL
++#define LBV1_LBV_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0
++#define LBV1_LBV_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
++#define LBV1_LBV_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14
++#define LBV1_LBV_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0x00000FFFL
++#define LBV1_LBV_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x000F0000L
++#define LBV1_LBV_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x00300000L
++//LBV1_LBV_MEMORY_SIZE_STATUS
++#define LBV1_LBV_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0
++#define LBV1_LBV_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0x00000FFFL
++//LBV1_LBV_DESKTOP_HEIGHT
++#define LBV1_LBV_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0
++#define LBV1_LBV_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x00007FFFL
++//LBV1_LBV_VLINE_START_END
++#define LBV1_LBV_VLINE_START_END__VLINE_START__SHIFT 0x0
++#define LBV1_LBV_VLINE_START_END__VLINE_END__SHIFT 0x10
++#define LBV1_LBV_VLINE_START_END__VLINE_INV__SHIFT 0x1f
++#define LBV1_LBV_VLINE_START_END__VLINE_START_MASK 0x00003FFFL
++#define LBV1_LBV_VLINE_START_END__VLINE_END_MASK 0x7FFF0000L
++#define LBV1_LBV_VLINE_START_END__VLINE_INV_MASK 0x80000000L
++//LBV1_LBV_VLINE2_START_END
++#define LBV1_LBV_VLINE2_START_END__VLINE2_START__SHIFT 0x0
++#define LBV1_LBV_VLINE2_START_END__VLINE2_END__SHIFT 0x10
++#define LBV1_LBV_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f
++#define LBV1_LBV_VLINE2_START_END__VLINE2_START_MASK 0x00003FFFL
++#define LBV1_LBV_VLINE2_START_END__VLINE2_END_MASK 0x7FFF0000L
++#define LBV1_LBV_VLINE2_START_END__VLINE2_INV_MASK 0x80000000L
++//LBV1_LBV_V_COUNTER
++#define LBV1_LBV_V_COUNTER__V_COUNTER__SHIFT 0x0
++#define LBV1_LBV_V_COUNTER__V_COUNTER_MASK 0x00007FFFL
++//LBV1_LBV_SNAPSHOT_V_COUNTER
++#define LBV1_LBV_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0
++#define LBV1_LBV_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x00007FFFL
++//LBV1_LBV_V_COUNTER_CHROMA
++#define LBV1_LBV_V_COUNTER_CHROMA__V_COUNTER_CHROMA__SHIFT 0x0
++#define LBV1_LBV_V_COUNTER_CHROMA__V_COUNTER_CHROMA_MASK 0x00007FFFL
++//LBV1_LBV_SNAPSHOT_V_COUNTER_CHROMA
++#define LBV1_LBV_SNAPSHOT_V_COUNTER_CHROMA__SNAPSHOT_V_COUNTER_CHROMA__SHIFT 0x0
++#define LBV1_LBV_SNAPSHOT_V_COUNTER_CHROMA__SNAPSHOT_V_COUNTER_CHROMA_MASK 0x00007FFFL
++//LBV1_LBV_INTERRUPT_MASK
++#define LBV1_LBV_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0
++#define LBV1_LBV_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4
++#define LBV1_LBV_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8
++#define LBV1_LBV_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x00000001L
++#define LBV1_LBV_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x00000010L
++#define LBV1_LBV_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x00000100L
++//LBV1_LBV_VLINE_STATUS
++#define LBV1_LBV_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0
++#define LBV1_LBV_VLINE_STATUS__VLINE_ACK__SHIFT 0x4
++#define LBV1_LBV_VLINE_STATUS__VLINE_STAT__SHIFT 0xc
++#define LBV1_LBV_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10
++#define LBV1_LBV_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11
++#define LBV1_LBV_VLINE_STATUS__VLINE_OCCURRED_MASK 0x00000001L
++#define LBV1_LBV_VLINE_STATUS__VLINE_ACK_MASK 0x00000010L
++#define LBV1_LBV_VLINE_STATUS__VLINE_STAT_MASK 0x00001000L
++#define LBV1_LBV_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x00010000L
++#define LBV1_LBV_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x00020000L
++//LBV1_LBV_VLINE2_STATUS
++#define LBV1_LBV_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0
++#define LBV1_LBV_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4
++#define LBV1_LBV_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc
++#define LBV1_LBV_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10
++#define LBV1_LBV_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11
++#define LBV1_LBV_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x00000001L
++#define LBV1_LBV_VLINE2_STATUS__VLINE2_ACK_MASK 0x00000010L
++#define LBV1_LBV_VLINE2_STATUS__VLINE2_STAT_MASK 0x00001000L
++#define LBV1_LBV_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x00010000L
++#define LBV1_LBV_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x00020000L
++//LBV1_LBV_VBLANK_STATUS
++#define LBV1_LBV_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0
++#define LBV1_LBV_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4
++#define LBV1_LBV_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc
++#define LBV1_LBV_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10
++#define LBV1_LBV_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11
++#define LBV1_LBV_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x00000001L
++#define LBV1_LBV_VBLANK_STATUS__VBLANK_ACK_MASK 0x00000010L
++#define LBV1_LBV_VBLANK_STATUS__VBLANK_STAT_MASK 0x00001000L
++#define LBV1_LBV_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x00010000L
++#define LBV1_LBV_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x00020000L
++//LBV1_LBV_SYNC_RESET_SEL
++#define LBV1_LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0
++#define LBV1_LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4
++#define LBV1_LBV_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8
++#define LBV1_LBV_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16
++#define LBV1_LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x00000003L
++#define LBV1_LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x00000010L
++#define LBV1_LBV_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0x0000FF00L
++#define LBV1_LBV_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0x00C00000L
++//LBV1_LBV_BLACK_KEYER_R_CR
++#define LBV1_LBV_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4
++#define LBV1_LBV_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0x0000FFF0L
++//LBV1_LBV_BLACK_KEYER_G_Y
++#define LBV1_LBV_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4
++#define LBV1_LBV_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0x0000FFF0L
++//LBV1_LBV_BLACK_KEYER_B_CB
++#define LBV1_LBV_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4
++#define LBV1_LBV_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0x0000FFF0L
++//LBV1_LBV_KEYER_COLOR_CTRL
++#define LBV1_LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0
++#define LBV1_LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8
++#define LBV1_LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x00000001L
++#define LBV1_LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x00000100L
++//LBV1_LBV_KEYER_COLOR_R_CR
++#define LBV1_LBV_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4
++#define LBV1_LBV_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0x0000FFF0L
++//LBV1_LBV_KEYER_COLOR_G_Y
++#define LBV1_LBV_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4
++#define LBV1_LBV_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0x0000FFF0L
++//LBV1_LBV_KEYER_COLOR_B_CB
++#define LBV1_LBV_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4
++#define LBV1_LBV_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0x0000FFF0L
++//LBV1_LBV_KEYER_COLOR_REP_R_CR
++#define LBV1_LBV_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4
++#define LBV1_LBV_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0x0000FFF0L
++//LBV1_LBV_KEYER_COLOR_REP_G_Y
++#define LBV1_LBV_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4
++#define LBV1_LBV_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0x0000FFF0L
++//LBV1_LBV_KEYER_COLOR_REP_B_CB
++#define LBV1_LBV_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4
++#define LBV1_LBV_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0x0000FFF0L
++//LBV1_LBV_BUFFER_LEVEL_STATUS
++#define LBV1_LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0
++#define LBV1_LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa
++#define LBV1_LBV_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10
++#define LBV1_LBV_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c
++#define LBV1_LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x0000003FL
++#define LBV1_LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0x0000FC00L
++#define LBV1_LBV_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0x0FFF0000L
++#define LBV1_LBV_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xF0000000L
++//LBV1_LBV_BUFFER_URGENCY_CTRL
++#define LBV1_LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0
++#define LBV1_LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10
++#define LBV1_LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0x00000FFFL
++#define LBV1_LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0x0FFF0000L
++//LBV1_LBV_BUFFER_URGENCY_STATUS
++#define LBV1_LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0
++#define LBV1_LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10
++#define LBV1_LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0x00000FFFL
++#define LBV1_LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x00010000L
++//LBV1_LBV_BUFFER_STATUS
++#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0
++#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4
++#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8
++#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc
++#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10
++#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14
++#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18
++#define LBV1_LBV_BUFFER_STATUS__LB_ENABLE_HIGH_THROUGHPUT__SHIFT 0x19
++#define LBV1_LBV_BUFFER_STATUS__LB_HIGH_THROUGHPUT_CNTL__SHIFT 0x1a
++#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0x0000000FL
++#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x00000010L
++#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x00000100L
++#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x00001000L
++#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x00010000L
++#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x00100000L
++#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x01000000L
++#define LBV1_LBV_BUFFER_STATUS__LB_ENABLE_HIGH_THROUGHPUT_MASK 0x02000000L
++#define LBV1_LBV_BUFFER_STATUS__LB_HIGH_THROUGHPUT_CNTL_MASK 0x1C000000L
++//LBV1_LBV_NO_OUTSTANDING_REQ_STATUS
++#define LBV1_LBV_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0
++#define LBV1_LBV_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x00000001L
++
++
++// addressBlock: dce_dc_sclv1_dispdec
++//SCLV1_SCLV_COEF_RAM_SELECT
++#define SCLV1_SCLV_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0
++#define SCLV1_SCLV_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8
++#define SCLV1_SCLV_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10
++#define SCLV1_SCLV_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x00000003L
++#define SCLV1_SCLV_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x00007F00L
++#define SCLV1_SCLV_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x00030000L
++//SCLV1_SCLV_COEF_RAM_TAP_DATA
++#define SCLV1_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0
++#define SCLV1_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
++#define SCLV1_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10
++#define SCLV1_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
++#define SCLV1_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL
++#define SCLV1_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L
++#define SCLV1_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L
++#define SCLV1_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L
++//SCLV1_SCLV_MODE
++#define SCLV1_SCLV_MODE__SCL_MODE__SHIFT 0x0
++#define SCLV1_SCLV_MODE__SCL_MODE_C__SHIFT 0x2
++#define SCLV1_SCLV_MODE__SCL_PSCL_EN__SHIFT 0x4
++#define SCLV1_SCLV_MODE__SCL_PSCL_EN_C__SHIFT 0x5
++#define SCLV1_SCLV_MODE__SCL_INTERLACE_SOURCE__SHIFT 0x8
++#define SCLV1_SCLV_MODE__SCL_MODE_MASK 0x00000003L
++#define SCLV1_SCLV_MODE__SCL_MODE_C_MASK 0x0000000CL
++#define SCLV1_SCLV_MODE__SCL_PSCL_EN_MASK 0x00000010L
++#define SCLV1_SCLV_MODE__SCL_PSCL_EN_C_MASK 0x00000020L
++#define SCLV1_SCLV_MODE__SCL_INTERLACE_SOURCE_MASK 0x00000300L
++//SCLV1_SCLV_TAP_CONTROL
++#define SCLV1_SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0
++#define SCLV1_SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x4
++#define SCLV1_SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_C__SHIFT 0x8
++#define SCLV1_SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_C__SHIFT 0xc
++#define SCLV1_SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x00000007L
++#define SCLV1_SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0x00000070L
++#define SCLV1_SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_C_MASK 0x00000700L
++#define SCLV1_SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_C_MASK 0x00007000L
++//SCLV1_SCLV_CONTROL
++#define SCLV1_SCLV_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
++#define SCLV1_SCLV_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4
++#define SCLV1_SCLV_CONTROL__SCL_TOTAL_PHASE__SHIFT 0x8
++#define SCLV1_SCLV_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L
++#define SCLV1_SCLV_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x00000010L
++#define SCLV1_SCLV_CONTROL__SCL_TOTAL_PHASE_MASK 0x00000100L
++//SCLV1_SCLV_MANUAL_REPLICATE_CONTROL
++#define SCLV1_SCLV_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
++#define SCLV1_SCLV_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
++#define SCLV1_SCLV_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL
++#define SCLV1_SCLV_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L
++//SCLV1_SCLV_AUTOMATIC_MODE_CONTROL
++#define SCLV1_SCLV_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0
++#define SCLV1_SCLV_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10
++#define SCLV1_SCLV_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x00000001L
++#define SCLV1_SCLV_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x00010000L
++//SCLV1_SCLV_HORZ_FILTER_CONTROL
++#define SCLV1_SCLV_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
++#define SCLV1_SCLV_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
++//SCLV1_SCLV_HORZ_FILTER_SCALE_RATIO
++#define SCLV1_SCLV_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
++#define SCLV1_SCLV_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL
++//SCLV1_SCLV_HORZ_FILTER_INIT
++#define SCLV1_SCLV_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
++#define SCLV1_SCLV_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
++#define SCLV1_SCLV_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL
++#define SCLV1_SCLV_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L
++//SCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_C
++#define SCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0
++#define SCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x03FFFFFFL
++//SCLV1_SCLV_HORZ_FILTER_INIT_C
++#define SCLV1_SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0
++#define SCLV1_SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18
++#define SCLV1_SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL
++#define SCLV1_SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L
++//SCLV1_SCLV_VERT_FILTER_CONTROL
++#define SCLV1_SCLV_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
++#define SCLV1_SCLV_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
++//SCLV1_SCLV_VERT_FILTER_SCALE_RATIO
++#define SCLV1_SCLV_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
++#define SCLV1_SCLV_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL
++//SCLV1_SCLV_VERT_FILTER_INIT
++#define SCLV1_SCLV_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
++#define SCLV1_SCLV_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
++#define SCLV1_SCLV_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL
++#define SCLV1_SCLV_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x07000000L
++//SCLV1_SCLV_VERT_FILTER_INIT_BOT
++#define SCLV1_SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
++#define SCLV1_SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
++#define SCLV1_SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL
++#define SCLV1_SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x07000000L
++//SCLV1_SCLV_VERT_FILTER_SCALE_RATIO_C
++#define SCLV1_SCLV_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0
++#define SCLV1_SCLV_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x03FFFFFFL
++//SCLV1_SCLV_VERT_FILTER_INIT_C
++#define SCLV1_SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0
++#define SCLV1_SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18
++#define SCLV1_SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL
++#define SCLV1_SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x07000000L
++//SCLV1_SCLV_VERT_FILTER_INIT_BOT_C
++#define SCLV1_SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0
++#define SCLV1_SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18
++#define SCLV1_SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL
++#define SCLV1_SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x07000000L
++//SCLV1_SCLV_ROUND_OFFSET
++#define SCLV1_SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0
++#define SCLV1_SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10
++#define SCLV1_SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0x0000FFFFL
++#define SCLV1_SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xFFFF0000L
++//SCLV1_SCLV_UPDATE
++#define SCLV1_SCLV_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
++#define SCLV1_SCLV_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8
++#define SCLV1_SCLV_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10
++#define SCLV1_SCLV_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18
++#define SCLV1_SCLV_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L
++#define SCLV1_SCLV_UPDATE__SCL_UPDATE_TAKEN_MASK 0x00000100L
++#define SCLV1_SCLV_UPDATE__SCL_UPDATE_LOCK_MASK 0x00010000L
++#define SCLV1_SCLV_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x01000000L
++//SCLV1_SCLV_ALU_CONTROL
++#define SCLV1_SCLV_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0
++#define SCLV1_SCLV_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x00000001L
++//SCLV1_SCLV_VIEWPORT_START
++#define SCLV1_SCLV_VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0
++#define SCLV1_SCLV_VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10
++#define SCLV1_SCLV_VIEWPORT_START__VIEWPORT_Y_START_MASK 0x00003FFFL
++#define SCLV1_SCLV_VIEWPORT_START__VIEWPORT_X_START_MASK 0x3FFF0000L
++//SCLV1_SCLV_VIEWPORT_START_SECONDARY
++#define SCLV1_SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0
++#define SCLV1_SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10
++#define SCLV1_SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x00003FFFL
++#define SCLV1_SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3FFF0000L
++//SCLV1_SCLV_VIEWPORT_SIZE
++#define SCLV1_SCLV_VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0
++#define SCLV1_SCLV_VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10
++#define SCLV1_SCLV_VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x00001FFFL
++#define SCLV1_SCLV_VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x1FFF0000L
++//SCLV1_SCLV_VIEWPORT_START_C
++#define SCLV1_SCLV_VIEWPORT_START_C__VIEWPORT_Y_START_C__SHIFT 0x0
++#define SCLV1_SCLV_VIEWPORT_START_C__VIEWPORT_X_START_C__SHIFT 0x10
++#define SCLV1_SCLV_VIEWPORT_START_C__VIEWPORT_Y_START_C_MASK 0x00003FFFL
++#define SCLV1_SCLV_VIEWPORT_START_C__VIEWPORT_X_START_C_MASK 0x3FFF0000L
++//SCLV1_SCLV_VIEWPORT_START_SECONDARY_C
++#define SCLV1_SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_Y_START_SECONDARY_C__SHIFT 0x0
++#define SCLV1_SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_X_START_SECONDARY_C__SHIFT 0x10
++#define SCLV1_SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_Y_START_SECONDARY_C_MASK 0x00003FFFL
++#define SCLV1_SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_X_START_SECONDARY_C_MASK 0x3FFF0000L
++//SCLV1_SCLV_VIEWPORT_SIZE_C
++#define SCLV1_SCLV_VIEWPORT_SIZE_C__VIEWPORT_HEIGHT_C__SHIFT 0x0
++#define SCLV1_SCLV_VIEWPORT_SIZE_C__VIEWPORT_WIDTH_C__SHIFT 0x10
++#define SCLV1_SCLV_VIEWPORT_SIZE_C__VIEWPORT_HEIGHT_C_MASK 0x00001FFFL
++#define SCLV1_SCLV_VIEWPORT_SIZE_C__VIEWPORT_WIDTH_C_MASK 0x1FFF0000L
++//SCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT
++#define SCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
++#define SCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
++#define SCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL
++#define SCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L
++//SCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM
++#define SCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
++#define SCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
++#define SCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL
++#define SCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L
++//SCLV1_SCLV_MODE_CHANGE_DET1
++#define SCLV1_SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0
++#define SCLV1_SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4
++#define SCLV1_SCLV_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7
++#define SCLV1_SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x00000001L
++#define SCLV1_SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x00000010L
++#define SCLV1_SCLV_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0x0FFFFF80L
++//SCLV1_SCLV_MODE_CHANGE_DET2
++#define SCLV1_SCLV_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0
++#define SCLV1_SCLV_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x001FFFFFL
++//SCLV1_SCLV_MODE_CHANGE_DET3
++#define SCLV1_SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0
++#define SCLV1_SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10
++#define SCLV1_SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x00003FFFL
++#define SCLV1_SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3FFF0000L
++//SCLV1_SCLV_MODE_CHANGE_MASK
++#define SCLV1_SCLV_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0
++#define SCLV1_SCLV_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x00000001L
++//SCLV1_SCLV_HORZ_FILTER_INIT_BOT
++#define SCLV1_SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_FRAC_BOT__SHIFT 0x0
++#define SCLV1_SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_INT_BOT__SHIFT 0x18
++#define SCLV1_SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_FRAC_BOT_MASK 0x00FFFFFFL
++#define SCLV1_SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_INT_BOT_MASK 0x0F000000L
++//SCLV1_SCLV_HORZ_FILTER_INIT_BOT_C
++#define SCLV1_SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_FRAC_BOT_C__SHIFT 0x0
++#define SCLV1_SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_INT_BOT_C__SHIFT 0x18
++#define SCLV1_SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL
++#define SCLV1_SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_INT_BOT_C_MASK 0x0F000000L
++
++
++// addressBlock: dce_dc_col_man1_dispdec
++//COL_MAN1_COL_MAN_UPDATE
++#define COL_MAN1_COL_MAN_UPDATE__COL_MAN_UPDATE_PENDING__SHIFT 0x0
++#define COL_MAN1_COL_MAN_UPDATE__COL_MAN_UPDATE_TAKEN__SHIFT 0x1
++#define COL_MAN1_COL_MAN_UPDATE__COL_MAN_UPDATE_LOCK__SHIFT 0x10
++#define COL_MAN1_COL_MAN_UPDATE__COL_MAN_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
++#define COL_MAN1_COL_MAN_UPDATE__COL_MAN_UPDATE_PENDING_MASK 0x00000001L
++#define COL_MAN1_COL_MAN_UPDATE__COL_MAN_UPDATE_TAKEN_MASK 0x00000002L
++#define COL_MAN1_COL_MAN_UPDATE__COL_MAN_UPDATE_LOCK_MASK 0x00010000L
++#define COL_MAN1_COL_MAN_UPDATE__COL_MAN_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
++//COL_MAN1_COL_MAN_INPUT_CSC_CONTROL
++#define COL_MAN1_COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_MODE__SHIFT 0x0
++#define COL_MAN1_COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_INPUT_TYPE__SHIFT 0x8
++#define COL_MAN1_COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_CONVERSION_MODE__SHIFT 0x10
++#define COL_MAN1_COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_MODE_MASK 0x00000003L
++#define COL_MAN1_COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_INPUT_TYPE_MASK 0x00000300L
++#define COL_MAN1_COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_CONVERSION_MODE_MASK 0x00010000L
++//COL_MAN1_INPUT_CSC_C11_C12_A
++#define COL_MAN1_INPUT_CSC_C11_C12_A__INPUT_CSC_C11_A__SHIFT 0x0
++#define COL_MAN1_INPUT_CSC_C11_C12_A__INPUT_CSC_C12_A__SHIFT 0x10
++#define COL_MAN1_INPUT_CSC_C11_C12_A__INPUT_CSC_C11_A_MASK 0x0000FFFFL
++#define COL_MAN1_INPUT_CSC_C11_C12_A__INPUT_CSC_C12_A_MASK 0xFFFF0000L
++//COL_MAN1_INPUT_CSC_C13_C14_A
++#define COL_MAN1_INPUT_CSC_C13_C14_A__INPUT_CSC_C13_A__SHIFT 0x0
++#define COL_MAN1_INPUT_CSC_C13_C14_A__INPUT_CSC_C14_A__SHIFT 0x10
++#define COL_MAN1_INPUT_CSC_C13_C14_A__INPUT_CSC_C13_A_MASK 0x0000FFFFL
++#define COL_MAN1_INPUT_CSC_C13_C14_A__INPUT_CSC_C14_A_MASK 0xFFFF0000L
++//COL_MAN1_INPUT_CSC_C21_C22_A
++#define COL_MAN1_INPUT_CSC_C21_C22_A__INPUT_CSC_C21_A__SHIFT 0x0
++#define COL_MAN1_INPUT_CSC_C21_C22_A__INPUT_CSC_C22_A__SHIFT 0x10
++#define COL_MAN1_INPUT_CSC_C21_C22_A__INPUT_CSC_C21_A_MASK 0x0000FFFFL
++#define COL_MAN1_INPUT_CSC_C21_C22_A__INPUT_CSC_C22_A_MASK 0xFFFF0000L
++//COL_MAN1_INPUT_CSC_C23_C24_A
++#define COL_MAN1_INPUT_CSC_C23_C24_A__INPUT_CSC_C23_A__SHIFT 0x0
++#define COL_MAN1_INPUT_CSC_C23_C24_A__INPUT_CSC_C24_A__SHIFT 0x10
++#define COL_MAN1_INPUT_CSC_C23_C24_A__INPUT_CSC_C23_A_MASK 0x0000FFFFL
++#define COL_MAN1_INPUT_CSC_C23_C24_A__INPUT_CSC_C24_A_MASK 0xFFFF0000L
++//COL_MAN1_INPUT_CSC_C31_C32_A
++#define COL_MAN1_INPUT_CSC_C31_C32_A__INPUT_CSC_C31_A__SHIFT 0x0
++#define COL_MAN1_INPUT_CSC_C31_C32_A__INPUT_CSC_C32_A__SHIFT 0x10
++#define COL_MAN1_INPUT_CSC_C31_C32_A__INPUT_CSC_C31_A_MASK 0x0000FFFFL
++#define COL_MAN1_INPUT_CSC_C31_C32_A__INPUT_CSC_C32_A_MASK 0xFFFF0000L
++//COL_MAN1_INPUT_CSC_C33_C34_A
++#define COL_MAN1_INPUT_CSC_C33_C34_A__INPUT_CSC_C33_A__SHIFT 0x0
++#define COL_MAN1_INPUT_CSC_C33_C34_A__INPUT_CSC_C34_A__SHIFT 0x10
++#define COL_MAN1_INPUT_CSC_C33_C34_A__INPUT_CSC_C33_A_MASK 0x0000FFFFL
++#define COL_MAN1_INPUT_CSC_C33_C34_A__INPUT_CSC_C34_A_MASK 0xFFFF0000L
++//COL_MAN1_INPUT_CSC_C11_C12_B
++#define COL_MAN1_INPUT_CSC_C11_C12_B__INPUT_CSC_C11_B__SHIFT 0x0
++#define COL_MAN1_INPUT_CSC_C11_C12_B__INPUT_CSC_C12_B__SHIFT 0x10
++#define COL_MAN1_INPUT_CSC_C11_C12_B__INPUT_CSC_C11_B_MASK 0x0000FFFFL
++#define COL_MAN1_INPUT_CSC_C11_C12_B__INPUT_CSC_C12_B_MASK 0xFFFF0000L
++//COL_MAN1_INPUT_CSC_C13_C14_B
++#define COL_MAN1_INPUT_CSC_C13_C14_B__INPUT_CSC_C13_B__SHIFT 0x0
++#define COL_MAN1_INPUT_CSC_C13_C14_B__INPUT_CSC_C14_B__SHIFT 0x10
++#define COL_MAN1_INPUT_CSC_C13_C14_B__INPUT_CSC_C13_B_MASK 0x0000FFFFL
++#define COL_MAN1_INPUT_CSC_C13_C14_B__INPUT_CSC_C14_B_MASK 0xFFFF0000L
++//COL_MAN1_INPUT_CSC_C21_C22_B
++#define COL_MAN1_INPUT_CSC_C21_C22_B__INPUT_CSC_C21_B__SHIFT 0x0
++#define COL_MAN1_INPUT_CSC_C21_C22_B__INPUT_CSC_C22_B__SHIFT 0x10
++#define COL_MAN1_INPUT_CSC_C21_C22_B__INPUT_CSC_C21_B_MASK 0x0000FFFFL
++#define COL_MAN1_INPUT_CSC_C21_C22_B__INPUT_CSC_C22_B_MASK 0xFFFF0000L
++//COL_MAN1_INPUT_CSC_C23_C24_B
++#define COL_MAN1_INPUT_CSC_C23_C24_B__INPUT_CSC_C23_B__SHIFT 0x0
++#define COL_MAN1_INPUT_CSC_C23_C24_B__INPUT_CSC_C24_B__SHIFT 0x10
++#define COL_MAN1_INPUT_CSC_C23_C24_B__INPUT_CSC_C23_B_MASK 0x0000FFFFL
++#define COL_MAN1_INPUT_CSC_C23_C24_B__INPUT_CSC_C24_B_MASK 0xFFFF0000L
++//COL_MAN1_INPUT_CSC_C31_C32_B
++#define COL_MAN1_INPUT_CSC_C31_C32_B__INPUT_CSC_C31_B__SHIFT 0x0
++#define COL_MAN1_INPUT_CSC_C31_C32_B__INPUT_CSC_C32_B__SHIFT 0x10
++#define COL_MAN1_INPUT_CSC_C31_C32_B__INPUT_CSC_C31_B_MASK 0x0000FFFFL
++#define COL_MAN1_INPUT_CSC_C31_C32_B__INPUT_CSC_C32_B_MASK 0xFFFF0000L
++//COL_MAN1_INPUT_CSC_C33_C34_B
++#define COL_MAN1_INPUT_CSC_C33_C34_B__INPUT_CSC_C33_B__SHIFT 0x0
++#define COL_MAN1_INPUT_CSC_C33_C34_B__INPUT_CSC_C34_B__SHIFT 0x10
++#define COL_MAN1_INPUT_CSC_C33_C34_B__INPUT_CSC_C33_B_MASK 0x0000FFFFL
++#define COL_MAN1_INPUT_CSC_C33_C34_B__INPUT_CSC_C34_B_MASK 0xFFFF0000L
++//COL_MAN1_PRESCALE_CONTROL
++#define COL_MAN1_PRESCALE_CONTROL__PRESCALE_MODE__SHIFT 0x0
++#define COL_MAN1_PRESCALE_CONTROL__PRESCALE_MODE_MASK 0x00000003L
++//COL_MAN1_PRESCALE_VALUES_R
++#define COL_MAN1_PRESCALE_VALUES_R__PRESCALE_BIAS_R__SHIFT 0x0
++#define COL_MAN1_PRESCALE_VALUES_R__PRESCALE_SCALE_R__SHIFT 0x10
++#define COL_MAN1_PRESCALE_VALUES_R__PRESCALE_BIAS_R_MASK 0x0000FFFFL
++#define COL_MAN1_PRESCALE_VALUES_R__PRESCALE_SCALE_R_MASK 0xFFFF0000L
++//COL_MAN1_PRESCALE_VALUES_G
++#define COL_MAN1_PRESCALE_VALUES_G__PRESCALE_BIAS_G__SHIFT 0x0
++#define COL_MAN1_PRESCALE_VALUES_G__PRESCALE_SCALE_G__SHIFT 0x10
++#define COL_MAN1_PRESCALE_VALUES_G__PRESCALE_BIAS_G_MASK 0x0000FFFFL
++#define COL_MAN1_PRESCALE_VALUES_G__PRESCALE_SCALE_G_MASK 0xFFFF0000L
++//COL_MAN1_PRESCALE_VALUES_B
++#define COL_MAN1_PRESCALE_VALUES_B__PRESCALE_BIAS_B__SHIFT 0x0
++#define COL_MAN1_PRESCALE_VALUES_B__PRESCALE_SCALE_B__SHIFT 0x10
++#define COL_MAN1_PRESCALE_VALUES_B__PRESCALE_BIAS_B_MASK 0x0000FFFFL
++#define COL_MAN1_PRESCALE_VALUES_B__PRESCALE_SCALE_B_MASK 0xFFFF0000L
++//COL_MAN1_COL_MAN_OUTPUT_CSC_CONTROL
++#define COL_MAN1_COL_MAN_OUTPUT_CSC_CONTROL__OUTPUT_CSC_MODE__SHIFT 0x0
++#define COL_MAN1_COL_MAN_OUTPUT_CSC_CONTROL__OUTPUT_CSC_MODE_MASK 0x00000007L
++//COL_MAN1_OUTPUT_CSC_C11_C12_A
++#define COL_MAN1_OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C11_A__SHIFT 0x0
++#define COL_MAN1_OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C12_A__SHIFT 0x10
++#define COL_MAN1_OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C11_A_MASK 0x0000FFFFL
++#define COL_MAN1_OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C12_A_MASK 0xFFFF0000L
++//COL_MAN1_OUTPUT_CSC_C13_C14_A
++#define COL_MAN1_OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C13_A__SHIFT 0x0
++#define COL_MAN1_OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C14_A__SHIFT 0x10
++#define COL_MAN1_OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C13_A_MASK 0x0000FFFFL
++#define COL_MAN1_OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C14_A_MASK 0xFFFF0000L
++//COL_MAN1_OUTPUT_CSC_C21_C22_A
++#define COL_MAN1_OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C21_A__SHIFT 0x0
++#define COL_MAN1_OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C22_A__SHIFT 0x10
++#define COL_MAN1_OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C21_A_MASK 0x0000FFFFL
++#define COL_MAN1_OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C22_A_MASK 0xFFFF0000L
++//COL_MAN1_OUTPUT_CSC_C23_C24_A
++#define COL_MAN1_OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C23_A__SHIFT 0x0
++#define COL_MAN1_OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C24_A__SHIFT 0x10
++#define COL_MAN1_OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C23_A_MASK 0x0000FFFFL
++#define COL_MAN1_OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C24_A_MASK 0xFFFF0000L
++//COL_MAN1_OUTPUT_CSC_C31_C32_A
++#define COL_MAN1_OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C31_A__SHIFT 0x0
++#define COL_MAN1_OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C32_A__SHIFT 0x10
++#define COL_MAN1_OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C31_A_MASK 0x0000FFFFL
++#define COL_MAN1_OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C32_A_MASK 0xFFFF0000L
++//COL_MAN1_OUTPUT_CSC_C33_C34_A
++#define COL_MAN1_OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C33_A__SHIFT 0x0
++#define COL_MAN1_OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C34_A__SHIFT 0x10
++#define COL_MAN1_OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C33_A_MASK 0x0000FFFFL
++#define COL_MAN1_OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C34_A_MASK 0xFFFF0000L
++//COL_MAN1_OUTPUT_CSC_C11_C12_B
++#define COL_MAN1_OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C11_B__SHIFT 0x0
++#define COL_MAN1_OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C12_B__SHIFT 0x10
++#define COL_MAN1_OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C11_B_MASK 0x0000FFFFL
++#define COL_MAN1_OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C12_B_MASK 0xFFFF0000L
++//COL_MAN1_OUTPUT_CSC_C13_C14_B
++#define COL_MAN1_OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C13_B__SHIFT 0x0
++#define COL_MAN1_OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C14_B__SHIFT 0x10
++#define COL_MAN1_OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C13_B_MASK 0x0000FFFFL
++#define COL_MAN1_OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C14_B_MASK 0xFFFF0000L
++//COL_MAN1_OUTPUT_CSC_C21_C22_B
++#define COL_MAN1_OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C21_B__SHIFT 0x0
++#define COL_MAN1_OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C22_B__SHIFT 0x10
++#define COL_MAN1_OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C21_B_MASK 0x0000FFFFL
++#define COL_MAN1_OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C22_B_MASK 0xFFFF0000L
++//COL_MAN1_OUTPUT_CSC_C23_C24_B
++#define COL_MAN1_OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C23_B__SHIFT 0x0
++#define COL_MAN1_OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C24_B__SHIFT 0x10
++#define COL_MAN1_OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C23_B_MASK 0x0000FFFFL
++#define COL_MAN1_OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C24_B_MASK 0xFFFF0000L
++//COL_MAN1_OUTPUT_CSC_C31_C32_B
++#define COL_MAN1_OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C31_B__SHIFT 0x0
++#define COL_MAN1_OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C32_B__SHIFT 0x10
++#define COL_MAN1_OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C31_B_MASK 0x0000FFFFL
++#define COL_MAN1_OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C32_B_MASK 0xFFFF0000L
++//COL_MAN1_OUTPUT_CSC_C33_C34_B
++#define COL_MAN1_OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C33_B__SHIFT 0x0
++#define COL_MAN1_OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C34_B__SHIFT 0x10
++#define COL_MAN1_OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C33_B_MASK 0x0000FFFFL
++#define COL_MAN1_OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C34_B_MASK 0xFFFF0000L
++//COL_MAN1_DENORM_CLAMP_CONTROL
++#define COL_MAN1_DENORM_CLAMP_CONTROL__DENORM_MODE__SHIFT 0x0
++#define COL_MAN1_DENORM_CLAMP_CONTROL__DENORM_10BIT_OUT__SHIFT 0x8
++#define COL_MAN1_DENORM_CLAMP_CONTROL__DENORM_MODE_MASK 0x00000003L
++#define COL_MAN1_DENORM_CLAMP_CONTROL__DENORM_10BIT_OUT_MASK 0x00000100L
++//COL_MAN1_DENORM_CLAMP_RANGE_R_CR
++#define COL_MAN1_DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MAX_R_CR__SHIFT 0x0
++#define COL_MAN1_DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MIN_R_CR__SHIFT 0xc
++#define COL_MAN1_DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MAX_R_CR_MASK 0x00000FFFL
++#define COL_MAN1_DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MIN_R_CR_MASK 0x00FFF000L
++//COL_MAN1_DENORM_CLAMP_RANGE_G_Y
++#define COL_MAN1_DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MAX_G_Y__SHIFT 0x0
++#define COL_MAN1_DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MIN_G_Y__SHIFT 0xc
++#define COL_MAN1_DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MAX_G_Y_MASK 0x00000FFFL
++#define COL_MAN1_DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MIN_G_Y_MASK 0x00FFF000L
++//COL_MAN1_DENORM_CLAMP_RANGE_B_CB
++#define COL_MAN1_DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MAX_B_CB__SHIFT 0x0
++#define COL_MAN1_DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MIN_B_CB__SHIFT 0xc
++#define COL_MAN1_DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MAX_B_CB_MASK 0x00000FFFL
++#define COL_MAN1_DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MIN_B_CB_MASK 0x00FFF000L
++//COL_MAN1_COL_MAN_FP_CONVERTED_FIELD
++#define COL_MAN1_COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_DATA__SHIFT 0x0
++#define COL_MAN1_COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14
++#define COL_MAN1_COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_DATA_MASK 0x0003FFFFL
++#define COL_MAN1_COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_INDEX_MASK 0x07F00000L
++//COL_MAN1_COL_MAN_REGAMMA_CONTROL
++#define COL_MAN1_COL_MAN_REGAMMA_CONTROL__COL_MAN_REGAMMA_MODE__SHIFT 0x0
++#define COL_MAN1_COL_MAN_REGAMMA_CONTROL__COL_MAN_REGAMMA_MODE_MASK 0x00000007L
++//COL_MAN1_COL_MAN_REGAMMA_LUT_INDEX
++#define COL_MAN1_COL_MAN_REGAMMA_LUT_INDEX__COL_MAN_REGAMMA_LUT_INDEX__SHIFT 0x0
++#define COL_MAN1_COL_MAN_REGAMMA_LUT_INDEX__COL_MAN_REGAMMA_LUT_INDEX_MASK 0x000001FFL
++//COL_MAN1_COL_MAN_REGAMMA_LUT_DATA
++#define COL_MAN1_COL_MAN_REGAMMA_LUT_DATA__COL_MAN_REGAMMA_LUT_DATA__SHIFT 0x0
++#define COL_MAN1_COL_MAN_REGAMMA_LUT_DATA__COL_MAN_REGAMMA_LUT_DATA_MASK 0x0007FFFFL
++//COL_MAN1_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK
++#define COL_MAN1_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK__COL_MAN_REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x0
++#define COL_MAN1_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK__COL_MAN_REGAMMA_LUT_WRITE_EN_MASK_MASK 0x00000007L
++//COL_MAN1_COL_MAN_REGAMMA_CNTLA_START_CNTL
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_START_CNTL__COL_MAN_REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x0
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_START_CNTL__COL_MAN_REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_START_CNTL__COL_MAN_REGAMMA_CNTLA_EXP_REGION_START_MASK 0x0003FFFFL
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_START_CNTL__COL_MAN_REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
++//COL_MAN1_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL__COL_MAN_REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL__COL_MAN_REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
++//COL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL1
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL1__COL_MAN_REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x0
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL1__COL_MAN_REGAMMA_CNTLA_EXP_REGION_END_MASK 0x0000FFFFL
++//COL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL2
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL2__COL_MAN_REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL2__COL_MAN_REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL2__COL_MAN_REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL2__COL_MAN_REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xFFFF0000L
++//COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xb
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0xf
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1b
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00003800L
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x00FF8000L
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x38000000L
++//COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xb
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0xf
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1b
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00003800L
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x00FF8000L
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x38000000L
++//COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xb
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0xf
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1b
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00003800L
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x00FF8000L
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x38000000L
++//COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xb
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0xf
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1b
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00003800L
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x00FF8000L
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x38000000L
++//COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xb
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0xf
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1b
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00003800L
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x00FF8000L
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x38000000L
++//COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xb
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0xf
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1b
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00003800L
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x00FF8000L
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x38000000L
++//COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xb
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0xf
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1b
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00003800L
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x00FF8000L
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x38000000L
++//COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xb
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0xf
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1b
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00003800L
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x00FF8000L
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x38000000L
++//COL_MAN1_COL_MAN_REGAMMA_CNTLB_START_CNTL
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_START_CNTL__COL_MAN_REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x0
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_START_CNTL__COL_MAN_REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_START_CNTL__COL_MAN_REGAMMA_CNTLB_EXP_REGION_START_MASK 0x0003FFFFL
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_START_CNTL__COL_MAN_REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
++//COL_MAN1_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL__COL_MAN_REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL__COL_MAN_REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
++//COL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL1
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL1__COL_MAN_REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x0
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL1__COL_MAN_REGAMMA_CNTLB_EXP_REGION_END_MASK 0x0000FFFFL
++//COL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL2
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL2__COL_MAN_REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL2__COL_MAN_REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL2__COL_MAN_REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL2__COL_MAN_REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xFFFF0000L
++//COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xb
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0xf
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1b
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00003800L
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x00FF8000L
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x38000000L
++//COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xb
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0xf
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1b
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00003800L
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x00FF8000L
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x38000000L
++//COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xb
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0xf
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1b
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00003800L
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x00FF8000L
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x38000000L
++//COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xb
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0xf
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1b
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00003800L
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x00FF8000L
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x38000000L
++//COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xb
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0xf
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1b
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00003800L
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x00FF8000L
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x38000000L
++//COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xb
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0xf
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1b
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00003800L
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x00FF8000L
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x38000000L
++//COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xb
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0xf
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1b
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00003800L
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x00FF8000L
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x38000000L
++//COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xb
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0xf
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1b
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00003800L
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x00FF8000L
++#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x38000000L
++//COL_MAN1_PACK_FIFO_ERROR
++#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_OCCURED__SHIFT 0x0
++#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_ACK__SHIFT 0x1
++#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_OCCURED__SHIFT 0x8
++#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_ACK__SHIFT 0x9
++#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_OCCURED__SHIFT 0x10
++#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_ACK__SHIFT 0x11
++#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_OCCURED__SHIFT 0x18
++#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_ACK__SHIFT 0x19
++#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_OCCURED_MASK 0x00000001L
++#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_ACK_MASK 0x00000002L
++#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_OCCURED_MASK 0x00000100L
++#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_ACK_MASK 0x00000200L
++#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_OCCURED_MASK 0x00010000L
++#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_ACK_MASK 0x00020000L
++#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_OCCURED_MASK 0x01000000L
++#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_ACK_MASK 0x02000000L
++//COL_MAN1_OUTPUT_FIFO_ERROR
++#define COL_MAN1_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_OCCURED__SHIFT 0x0
++#define COL_MAN1_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_ACK__SHIFT 0x1
++#define COL_MAN1_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_OCCURED__SHIFT 0x8
++#define COL_MAN1_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_ACK__SHIFT 0x9
++#define COL_MAN1_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_OCCURED_MASK 0x00000001L
++#define COL_MAN1_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_ACK_MASK 0x00000002L
++#define COL_MAN1_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_OCCURED_MASK 0x00000100L
++#define COL_MAN1_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_ACK_MASK 0x00000200L
++//COL_MAN1_INPUT_GAMMA_LUT_AUTOFILL
++#define COL_MAN1_INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL__SHIFT 0x0
++#define COL_MAN1_INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL_DONE__SHIFT 0x1
++#define COL_MAN1_INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL_MASK 0x00000001L
++#define COL_MAN1_INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL_DONE_MASK 0x00000002L
++//COL_MAN1_INPUT_GAMMA_LUT_RW_INDEX
++#define COL_MAN1_INPUT_GAMMA_LUT_RW_INDEX__INPUT_GAMMA_LUT_RW_INDEX__SHIFT 0x0
++#define COL_MAN1_INPUT_GAMMA_LUT_RW_INDEX__INPUT_GAMMA_LUT_RW_INDEX_MASK 0x000000FFL
++//COL_MAN1_INPUT_GAMMA_LUT_SEQ_COLOR
++#define COL_MAN1_INPUT_GAMMA_LUT_SEQ_COLOR__INPUT_GAMMA_LUT_SEQ_COLOR__SHIFT 0x0
++#define COL_MAN1_INPUT_GAMMA_LUT_SEQ_COLOR__INPUT_GAMMA_LUT_SEQ_COLOR_MASK 0x0000FFFFL
++//COL_MAN1_INPUT_GAMMA_LUT_PWL_DATA
++#define COL_MAN1_INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_BASE__SHIFT 0x0
++#define COL_MAN1_INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_DELTA__SHIFT 0x10
++#define COL_MAN1_INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_BASE_MASK 0x0000FFFFL
++#define COL_MAN1_INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_DELTA_MASK 0xFFFF0000L
++//COL_MAN1_INPUT_GAMMA_LUT_30_COLOR
++#define COL_MAN1_INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_BLUE__SHIFT 0x0
++#define COL_MAN1_INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_GREEN__SHIFT 0xa
++#define COL_MAN1_INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_RED__SHIFT 0x14
++#define COL_MAN1_INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_BLUE_MASK 0x000003FFL
++#define COL_MAN1_INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_GREEN_MASK 0x000FFC00L
++#define COL_MAN1_INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_RED_MASK 0x3FF00000L
++//COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1
++#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_MODE__SHIFT 0x0
++#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_LUT_10BIT_BYPASS_EN__SHIFT 0x1a
++#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_MODE_MASK 0x00000003L
++#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_LUT_10BIT_BYPASS_EN_MASK 0x04000000L
++//COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2
++#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_B__SHIFT 0x1
++#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_SIGNED_EN__SHIFT 0x5
++#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_FORMAT__SHIFT 0x6
++#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_G__SHIFT 0x8
++#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_SIGNED_EN__SHIFT 0xc
++#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_FORMAT__SHIFT 0xd
++#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_R__SHIFT 0xf
++#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_SIGNED_EN__SHIFT 0x13
++#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_FORMAT__SHIFT 0x14
++#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_RW_MODE__SHIFT 0x16
++#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_WRITE_EN_MASK__SHIFT 0x17
++#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_VGA_ACCESS_ENABLE__SHIFT 0x1a
++#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x1b
++#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_B_MASK 0x0000001EL
++#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_SIGNED_EN_MASK 0x00000020L
++#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_FORMAT_MASK 0x000000C0L
++#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_G_MASK 0x00000F00L
++#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_SIGNED_EN_MASK 0x00001000L
++#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_FORMAT_MASK 0x00006000L
++#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_R_MASK 0x00078000L
++#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_SIGNED_EN_MASK 0x00080000L
++#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_FORMAT_MASK 0x00300000L
++#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_RW_MODE_MASK 0x00400000L
++#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_WRITE_EN_MASK_MASK 0x03800000L
++#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_VGA_ACCESS_ENABLE_MASK 0x04000000L
++#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x08000000L
++//COL_MAN1_INPUT_GAMMA_BW_OFFSETS_B
++#define COL_MAN1_INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_BLACK_OFFSET_B__SHIFT 0x0
++#define COL_MAN1_INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_WHITE_OFFSET_B__SHIFT 0x10
++#define COL_MAN1_INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_BLACK_OFFSET_B_MASK 0x0000FFFFL
++#define COL_MAN1_INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_WHITE_OFFSET_B_MASK 0xFFFF0000L
++//COL_MAN1_INPUT_GAMMA_BW_OFFSETS_G
++#define COL_MAN1_INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_BLACK_OFFSET_G__SHIFT 0x0
++#define COL_MAN1_INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_WHITE_OFFSET_G__SHIFT 0x10
++#define COL_MAN1_INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_BLACK_OFFSET_G_MASK 0x0000FFFFL
++#define COL_MAN1_INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_WHITE_OFFSET_G_MASK 0xFFFF0000L
++//COL_MAN1_INPUT_GAMMA_BW_OFFSETS_R
++#define COL_MAN1_INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_BLACK_OFFSET_R__SHIFT 0x0
++#define COL_MAN1_INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_WHITE_OFFSET_R__SHIFT 0x10
++#define COL_MAN1_INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_BLACK_OFFSET_R_MASK 0x0000FFFFL
++#define COL_MAN1_INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_WHITE_OFFSET_R_MASK 0xFFFF0000L
++//COL_MAN1_COL_MAN_DEGAMMA_CONTROL
++#define COL_MAN1_COL_MAN_DEGAMMA_CONTROL__COL_MAN_DEGAMMA_MODE__SHIFT 0x0
++#define COL_MAN1_COL_MAN_DEGAMMA_CONTROL__COL_MAN_DEGAMMA_MODE_MASK 0x00000003L
++//COL_MAN1_COL_MAN_GAMUT_REMAP_CONTROL
++#define COL_MAN1_COL_MAN_GAMUT_REMAP_CONTROL__COL_MAN_GAMUT_REMAP_MODE__SHIFT 0x0
++#define COL_MAN1_COL_MAN_GAMUT_REMAP_CONTROL__COL_MAN_GAMUT_REMAP_MODE_MASK 0x00000003L
++//COL_MAN1_COL_MAN_GAMUT_REMAP_C11_C12
++#define COL_MAN1_COL_MAN_GAMUT_REMAP_C11_C12__COL_MAN_GAMUT_REMAP_C11__SHIFT 0x0
++#define COL_MAN1_COL_MAN_GAMUT_REMAP_C11_C12__COL_MAN_GAMUT_REMAP_C12__SHIFT 0x10
++#define COL_MAN1_COL_MAN_GAMUT_REMAP_C11_C12__COL_MAN_GAMUT_REMAP_C11_MASK 0x0000FFFFL
++#define COL_MAN1_COL_MAN_GAMUT_REMAP_C11_C12__COL_MAN_GAMUT_REMAP_C12_MASK 0xFFFF0000L
++//COL_MAN1_COL_MAN_GAMUT_REMAP_C13_C14
++#define COL_MAN1_COL_MAN_GAMUT_REMAP_C13_C14__COL_MAN_GAMUT_REMAP_C13__SHIFT 0x0
++#define COL_MAN1_COL_MAN_GAMUT_REMAP_C13_C14__COL_MAN_GAMUT_REMAP_C14__SHIFT 0x10
++#define COL_MAN1_COL_MAN_GAMUT_REMAP_C13_C14__COL_MAN_GAMUT_REMAP_C13_MASK 0x0000FFFFL
++#define COL_MAN1_COL_MAN_GAMUT_REMAP_C13_C14__COL_MAN_GAMUT_REMAP_C14_MASK 0xFFFF0000L
++//COL_MAN1_COL_MAN_GAMUT_REMAP_C21_C22
++#define COL_MAN1_COL_MAN_GAMUT_REMAP_C21_C22__COL_MAN_GAMUT_REMAP_C21__SHIFT 0x0
++#define COL_MAN1_COL_MAN_GAMUT_REMAP_C21_C22__COL_MAN_GAMUT_REMAP_C22__SHIFT 0x10
++#define COL_MAN1_COL_MAN_GAMUT_REMAP_C21_C22__COL_MAN_GAMUT_REMAP_C21_MASK 0x0000FFFFL
++#define COL_MAN1_COL_MAN_GAMUT_REMAP_C21_C22__COL_MAN_GAMUT_REMAP_C22_MASK 0xFFFF0000L
++//COL_MAN1_COL_MAN_GAMUT_REMAP_C23_C24
++#define COL_MAN1_COL_MAN_GAMUT_REMAP_C23_C24__COL_MAN_GAMUT_REMAP_C23__SHIFT 0x0
++#define COL_MAN1_COL_MAN_GAMUT_REMAP_C23_C24__COL_MAN_GAMUT_REMAP_C24__SHIFT 0x10
++#define COL_MAN1_COL_MAN_GAMUT_REMAP_C23_C24__COL_MAN_GAMUT_REMAP_C23_MASK 0x0000FFFFL
++#define COL_MAN1_COL_MAN_GAMUT_REMAP_C23_C24__COL_MAN_GAMUT_REMAP_C24_MASK 0xFFFF0000L
++//COL_MAN1_COL_MAN_GAMUT_REMAP_C31_C32
++#define COL_MAN1_COL_MAN_GAMUT_REMAP_C31_C32__COL_MAN_GAMUT_REMAP_C31__SHIFT 0x0
++#define COL_MAN1_COL_MAN_GAMUT_REMAP_C31_C32__COL_MAN_GAMUT_REMAP_C32__SHIFT 0x10
++#define COL_MAN1_COL_MAN_GAMUT_REMAP_C31_C32__COL_MAN_GAMUT_REMAP_C31_MASK 0x0000FFFFL
++#define COL_MAN1_COL_MAN_GAMUT_REMAP_C31_C32__COL_MAN_GAMUT_REMAP_C32_MASK 0xFFFF0000L
++//COL_MAN1_COL_MAN_GAMUT_REMAP_C33_C34
++#define COL_MAN1_COL_MAN_GAMUT_REMAP_C33_C34__COL_MAN_GAMUT_REMAP_C33__SHIFT 0x0
++#define COL_MAN1_COL_MAN_GAMUT_REMAP_C33_C34__COL_MAN_GAMUT_REMAP_C34__SHIFT 0x10
++#define COL_MAN1_COL_MAN_GAMUT_REMAP_C33_C34__COL_MAN_GAMUT_REMAP_C33_MASK 0x0000FFFFL
++#define COL_MAN1_COL_MAN_GAMUT_REMAP_C33_C34__COL_MAN_GAMUT_REMAP_C34_MASK 0xFFFF0000L
++
++
++// addressBlock: dce_dc_dcfev1_dispdec
++//DCFEV1_DCFEV_CLOCK_CONTROL
++#define DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_R_DCFEV_GATE_DISABLE__SHIFT 0x3
++#define DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_G_UNP_GATE_DISABLE__SHIFT 0x7
++#define DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_G_SCLV_GATE_DISABLE__SHIFT 0x9
++#define DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_G_COL_MAN_GATE_DISABLE__SHIFT 0xb
++#define DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_G_PSCLV_GATE_DISABLE__SHIFT 0xd
++#define DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_G_CRTC_GATE_DISABLE__SHIFT 0xf
++#define DCFEV1_DCFEV_CLOCK_CONTROL__DCFEV_TEST_CLK_SEL__SHIFT 0x18
++#define DCFEV1_DCFEV_CLOCK_CONTROL__DCFEV_CLOCK_ENABLE__SHIFT 0x1f
++#define DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_R_DCFEV_GATE_DISABLE_MASK 0x00000008L
++#define DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_G_UNP_GATE_DISABLE_MASK 0x00000080L
++#define DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_G_SCLV_GATE_DISABLE_MASK 0x00000200L
++#define DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_G_COL_MAN_GATE_DISABLE_MASK 0x00000800L
++#define DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_G_PSCLV_GATE_DISABLE_MASK 0x00002000L
++#define DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_G_CRTC_GATE_DISABLE_MASK 0x00008000L
++#define DCFEV1_DCFEV_CLOCK_CONTROL__DCFEV_TEST_CLK_SEL_MASK 0x1F000000L
++#define DCFEV1_DCFEV_CLOCK_CONTROL__DCFEV_CLOCK_ENABLE_MASK 0x80000000L
++//DCFEV1_DCFEV_SOFT_RESET
++#define DCFEV1_DCFEV_SOFT_RESET__UNP_PIXPIPE_SOFT_RESET__SHIFT 0x0
++#define DCFEV1_DCFEV_SOFT_RESET__UNP_REQ_SOFT_RESET__SHIFT 0x1
++#define DCFEV1_DCFEV_SOFT_RESET__SCLV_ALU_SOFT_RESET__SHIFT 0x2
++#define DCFEV1_DCFEV_SOFT_RESET__SCLV_SOFT_RESET__SHIFT 0x3
++#define DCFEV1_DCFEV_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4
++#define DCFEV1_DCFEV_SOFT_RESET__PSCLV_SOFT_RESET__SHIFT 0x5
++#define DCFEV1_DCFEV_SOFT_RESET__COL_MAN_SOFT_RESET__SHIFT 0x6
++#define DCFEV1_DCFEV_SOFT_RESET__UNP_PIXPIPE_SOFT_RESET_MASK 0x00000001L
++#define DCFEV1_DCFEV_SOFT_RESET__UNP_REQ_SOFT_RESET_MASK 0x00000002L
++#define DCFEV1_DCFEV_SOFT_RESET__SCLV_ALU_SOFT_RESET_MASK 0x00000004L
++#define DCFEV1_DCFEV_SOFT_RESET__SCLV_SOFT_RESET_MASK 0x00000008L
++#define DCFEV1_DCFEV_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x00000010L
++#define DCFEV1_DCFEV_SOFT_RESET__PSCLV_SOFT_RESET_MASK 0x00000020L
++#define DCFEV1_DCFEV_SOFT_RESET__COL_MAN_SOFT_RESET_MASK 0x00000040L
++//DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL
++#define DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x3
++#define DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVL_GATE_DIS__SHIFT 0x4
++#define DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVC_GATE_DIS__SHIFT 0x5
++#define DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SOFT_RESET__SHIFT 0x6
++#define DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_TEST_CLK_SEL__SHIFT 0x18
++#define DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_BUFFER_MODE__SHIFT 0x1f
++#define DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SCLK_G_DMIFTRK_GATE_DIS_MASK 0x00000008L
++#define DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVL_GATE_DIS_MASK 0x00000010L
++#define DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVC_GATE_DIS_MASK 0x00000020L
++#define DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SOFT_RESET_MASK 0x00000040L
++#define DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_TEST_CLK_SEL_MASK 0x1F000000L
++#define DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_BUFFER_MODE_MASK 0x80000000L
++//DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_SEL__SHIFT 0x0
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_0_FORCE__SHIFT 0x2
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_1_FORCE__SHIFT 0x3
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_2_FORCE__SHIFT 0x4
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_3_FORCE__SHIFT 0x5
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_4_FORCE__SHIFT 0x6
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_0_FORCE__SHIFT 0x7
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_1_FORCE__SHIFT 0x8
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_2_FORCE__SHIFT 0x9
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_3_FORCE__SHIFT 0xa
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_4_FORCE__SHIFT 0xb
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_SEL_MASK 0x00000003L
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_0_FORCE_MASK 0x00000004L
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_1_FORCE_MASK 0x00000008L
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_2_FORCE_MASK 0x00000010L
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_3_FORCE_MASK 0x00000020L
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_4_FORCE_MASK 0x00000040L
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_0_FORCE_MASK 0x00000080L
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_1_FORCE_MASK 0x00000100L
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_2_FORCE_MASK 0x00000200L
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_3_FORCE_MASK 0x00000400L
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_4_FORCE_MASK 0x00000800L
++//DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_0_STATE__SHIFT 0x0
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_1_STATE__SHIFT 0x2
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_2_STATE__SHIFT 0x4
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_3_STATE__SHIFT 0x6
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_4_STATE__SHIFT 0x8
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_0_STATE__SHIFT 0xa
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_1_STATE__SHIFT 0xc
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_2_STATE__SHIFT 0xe
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_3_STATE__SHIFT 0x10
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_4_STATE__SHIFT 0x12
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_0_STATE_MASK 0x00000003L
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_1_STATE_MASK 0x0000000CL
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_2_STATE_MASK 0x00000030L
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_3_STATE_MASK 0x000000C0L
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_4_STATE_MASK 0x00000300L
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_0_STATE_MASK 0x00000C00L
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_1_STATE_MASK 0x00003000L
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_2_STATE_MASK 0x0000C000L
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_3_STATE_MASK 0x00030000L
++#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_4_STATE_MASK 0x000C0000L
++//DCFEV1_DCFEV_MEM_PWR_CTRL
++#define DCFEV1_DCFEV_MEM_PWR_CTRL__COL_MAN_REGAMMA_MEM_PWR_FORCE__SHIFT 0x0
++#define DCFEV1_DCFEV_MEM_PWR_CTRL__COL_MAN_REGAMMA_MEM_PWR_DIS__SHIFT 0x2
++#define DCFEV1_DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_FORCE__SHIFT 0x3
++#define DCFEV1_DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_DIS__SHIFT 0x5
++#define DCFEV1_DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_FORCE__SHIFT 0x6
++#define DCFEV1_DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_DIS__SHIFT 0x8
++#define DCFEV1_DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_FORCE__SHIFT 0x9
++#define DCFEV1_DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_DIS__SHIFT 0xb
++#define DCFEV1_DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_FORCE__SHIFT 0xc
++#define DCFEV1_DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_DIS__SHIFT 0xe
++#define DCFEV1_DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_FORCE__SHIFT 0xf
++#define DCFEV1_DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_DIS__SHIFT 0x11
++#define DCFEV1_DCFEV_MEM_PWR_CTRL__COL_MAN_REGAMMA_MEM_PWR_FORCE_MASK 0x00000003L
++#define DCFEV1_DCFEV_MEM_PWR_CTRL__COL_MAN_REGAMMA_MEM_PWR_DIS_MASK 0x00000004L
++#define DCFEV1_DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_FORCE_MASK 0x00000018L
++#define DCFEV1_DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_DIS_MASK 0x00000020L
++#define DCFEV1_DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_FORCE_MASK 0x000000C0L
++#define DCFEV1_DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_DIS_MASK 0x00000100L
++#define DCFEV1_DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_FORCE_MASK 0x00000600L
++#define DCFEV1_DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_DIS_MASK 0x00000800L
++#define DCFEV1_DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_FORCE_MASK 0x00003000L
++#define DCFEV1_DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_DIS_MASK 0x00004000L
++#define DCFEV1_DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_FORCE_MASK 0x00018000L
++#define DCFEV1_DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_DIS_MASK 0x00020000L
++//DCFEV1_DCFEV_MEM_PWR_CTRL2
++#define DCFEV1_DCFEV_MEM_PWR_CTRL2__COL_MAN_REGAMMA_MEM_PWR_MODE_SEL__SHIFT 0x0
++#define DCFEV1_DCFEV_MEM_PWR_CTRL2__COL_MAN_INPUT_GAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2
++#define DCFEV1_DCFEV_MEM_PWR_CTRL2__SCLV_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4
++#define DCFEV1_DCFEV_MEM_PWR_CTRL2__LBV_MEM_PWR_MODE_SEL__SHIFT 0x6
++#define DCFEV1_DCFEV_MEM_PWR_CTRL2__COL_MAN_REGAMMA_MEM_PWR_MODE_SEL_MASK 0x00000003L
++#define DCFEV1_DCFEV_MEM_PWR_CTRL2__COL_MAN_INPUT_GAMMA_MEM_PWR_MODE_SEL_MASK 0x0000000CL
++#define DCFEV1_DCFEV_MEM_PWR_CTRL2__SCLV_COEFF_MEM_PWR_MODE_SEL_MASK 0x00000030L
++#define DCFEV1_DCFEV_MEM_PWR_CTRL2__LBV_MEM_PWR_MODE_SEL_MASK 0x000000C0L
++//DCFEV1_DCFEV_MEM_PWR_STATUS
++#define DCFEV1_DCFEV_MEM_PWR_STATUS__COL_MAN_REGAMMA_MEM_PWR_STATE__SHIFT 0x0
++#define DCFEV1_DCFEV_MEM_PWR_STATUS__COL_MAN_INPUT_GAMMA_MEM_PWR_STATE__SHIFT 0x2
++#define DCFEV1_DCFEV_MEM_PWR_STATUS__SCLV_COEFF_MEM_PWR_STATE__SHIFT 0x4
++#define DCFEV1_DCFEV_MEM_PWR_STATUS__LBV0_MEM_PWR_STATE__SHIFT 0x6
++#define DCFEV1_DCFEV_MEM_PWR_STATUS__LBV1_MEM_PWR_STATE__SHIFT 0x8
++#define DCFEV1_DCFEV_MEM_PWR_STATUS__LBV2_MEM_PWR_STATE__SHIFT 0xa
++#define DCFEV1_DCFEV_MEM_PWR_STATUS__LBV3_MEM_PWR_STATE__SHIFT 0xc
++#define DCFEV1_DCFEV_MEM_PWR_STATUS__COL_MAN_REGAMMA_MEM_PWR_STATE_MASK 0x00000003L
++#define DCFEV1_DCFEV_MEM_PWR_STATUS__COL_MAN_INPUT_GAMMA_MEM_PWR_STATE_MASK 0x0000000CL
++#define DCFEV1_DCFEV_MEM_PWR_STATUS__SCLV_COEFF_MEM_PWR_STATE_MASK 0x00000030L
++#define DCFEV1_DCFEV_MEM_PWR_STATUS__LBV0_MEM_PWR_STATE_MASK 0x000000C0L
++#define DCFEV1_DCFEV_MEM_PWR_STATUS__LBV1_MEM_PWR_STATE_MASK 0x00000300L
++#define DCFEV1_DCFEV_MEM_PWR_STATUS__LBV2_MEM_PWR_STATE_MASK 0x00000C00L
++#define DCFEV1_DCFEV_MEM_PWR_STATUS__LBV3_MEM_PWR_STATE_MASK 0x00003000L
++//DCFEV1_DCFEV_L_FLUSH
++#define DCFEV1_DCFEV_L_FLUSH__FLUSH_OCCURED__SHIFT 0x0
++#define DCFEV1_DCFEV_L_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT 0x1
++#define DCFEV1_DCFEV_L_FLUSH__FLUSH_DEEP__SHIFT 0x2
++#define DCFEV1_DCFEV_L_FLUSH__CLEAR_FLUSH_DEEP__SHIFT 0x3
++#define DCFEV1_DCFEV_L_FLUSH__ALL_MC_REQ_RET__SHIFT 0x4
++#define DCFEV1_DCFEV_L_FLUSH__FLUSH_OCCURED_MASK 0x00000001L
++#define DCFEV1_DCFEV_L_FLUSH__CLEAR_FLUSH_OCCURED_MASK 0x00000002L
++#define DCFEV1_DCFEV_L_FLUSH__FLUSH_DEEP_MASK 0x00000004L
++#define DCFEV1_DCFEV_L_FLUSH__CLEAR_FLUSH_DEEP_MASK 0x00000008L
++#define DCFEV1_DCFEV_L_FLUSH__ALL_MC_REQ_RET_MASK 0x00000010L
++//DCFEV1_DCFEV_C_FLUSH
++#define DCFEV1_DCFEV_C_FLUSH__FLUSH_OCCURED__SHIFT 0x0
++#define DCFEV1_DCFEV_C_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT 0x1
++#define DCFEV1_DCFEV_C_FLUSH__FLUSH_DEEP__SHIFT 0x2
++#define DCFEV1_DCFEV_C_FLUSH__CLEAR_FLUSH_DEEP__SHIFT 0x3
++#define DCFEV1_DCFEV_C_FLUSH__ALL_MC_REQ_RET__SHIFT 0x4
++#define DCFEV1_DCFEV_C_FLUSH__FLUSH_OCCURED_MASK 0x00000001L
++#define DCFEV1_DCFEV_C_FLUSH__CLEAR_FLUSH_OCCURED_MASK 0x00000002L
++#define DCFEV1_DCFEV_C_FLUSH__FLUSH_DEEP_MASK 0x00000004L
++#define DCFEV1_DCFEV_C_FLUSH__CLEAR_FLUSH_DEEP_MASK 0x00000008L
++#define DCFEV1_DCFEV_C_FLUSH__ALL_MC_REQ_RET_MASK 0x00000010L
++//DCFEV1_DCFEV_MISC
++#define DCFEV1_DCFEV_MISC__DCFEV_DPG_ALLOW_SR_ECO_EN__SHIFT 0x0
++#define DCFEV1_DCFEV_MISC__DCFEV_DPG_ALLOW_SR_ECO_EN_MASK 0x00000001L
++
++
++// addressBlock: dce_dc_dc_perfmon12_dispdec
++//DC_PERFMON12_PERFCOUNTER_CNTL
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
++//DC_PERFMON12_PERFCOUNTER_CNTL2
++#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
++#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
++#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
++#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
++#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
++#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
++#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
++#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
++//DC_PERFMON12_PERFCOUNTER_STATE
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
++//DC_PERFMON12_PERFMON_CNTL
++#define DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
++#define DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
++#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
++#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
++#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
++#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
++#define DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
++#define DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
++#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
++#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
++#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
++#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
++//DC_PERFMON12_PERFMON_CNTL2
++#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
++#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
++#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
++#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
++#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
++#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
++#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
++#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
++//DC_PERFMON12_PERFMON_CVALUE_INT_MISC
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
++//DC_PERFMON12_PERFMON_CVALUE_LOW
++#define DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
++#define DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
++//DC_PERFMON12_PERFMON_HI
++#define DC_PERFMON12_PERFMON_HI__PERFMON_HI__SHIFT 0x0
++#define DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
++#define DC_PERFMON12_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
++#define DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
++//DC_PERFMON12_PERFMON_LOW
++#define DC_PERFMON12_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
++#define DC_PERFMON12_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dmifv_pg1_dispdec
++//DMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1
++#define DMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
++#define DMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
++#define DMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0x0000FFFFL
++#define DMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xFFFF0000L
++//DMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2
++#define DMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
++#define DMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
++#define DMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0x0000FFFFL
++#define DMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xFFFF0000L
++//DMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL
++#define DMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
++#define DMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
++#define DMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x10
++#define DMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x18
++#define DMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000003L
++#define DMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x00000300L
++#define DMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00030000L
++#define DMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x01000000L
++//DMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL
++#define DMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
++#define DMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
++#define DMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0x0000FFFFL
++#define DMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xFFFF0000L
++//DMIFV_PG1_DPGV0_PIPE_DPM_CONTROL
++#define DMIFV_PG1_DPGV0_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x0
++#define DMIFV_PG1_DPGV0_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x00000001L
++//DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL
++#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
++#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
++#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
++#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
++#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
++#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x8
++#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x9
++#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
++#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
++#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x10
++#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L
++#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L
++#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x00000020L
++#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x00000040L
++#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x00000080L
++#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x00000100L
++#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x00000200L
++#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x00000400L
++#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x00000800L
++#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xFFFF0000L
++//DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL
++#define DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x0
++#define DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
++#define DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
++#define DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
++#define DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
++#define DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x10
++#define DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x00000001L
++#define DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L
++#define DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x00000100L
++#define DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000200L
++#define DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000400L
++#define DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xFFFF0000L
++//DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH
++#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x0
++#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x4
++#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x5
++#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x6
++#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x7
++#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x8
++#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x9
++#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0xa
++#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0xb
++#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x00000001L
++#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x00000010L
++#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x00000020L
++#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x00000040L
++#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x00000080L
++#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x00000100L
++#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x00000200L
++#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x00000400L
++#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x00000800L
++//DMIFV_PG1_DPGV0_REPEATER_PROGRAM
++#define DMIFV_PG1_DPGV0_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
++#define DMIFV_PG1_DPGV0_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
++#define DMIFV_PG1_DPGV0_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x00000007L
++#define DMIFV_PG1_DPGV0_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x00000070L
++//DMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL
++#define DMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0
++#define DMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x00000001L
++//DMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1
++#define DMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
++#define DMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
++#define DMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0x0000FFFFL
++#define DMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xFFFF0000L
++//DMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2
++#define DMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
++#define DMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
++#define DMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0x0000FFFFL
++#define DMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xFFFF0000L
++//DMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL
++#define DMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
++#define DMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
++#define DMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x10
++#define DMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x18
++#define DMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000003L
++#define DMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x00000300L
++#define DMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00030000L
++#define DMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x01000000L
++//DMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL
++#define DMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
++#define DMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
++#define DMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0x0000FFFFL
++#define DMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xFFFF0000L
++//DMIFV_PG1_DPGV1_PIPE_DPM_CONTROL
++#define DMIFV_PG1_DPGV1_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x0
++#define DMIFV_PG1_DPGV1_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x00000001L
++//DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL
++#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
++#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
++#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
++#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
++#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
++#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x8
++#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x9
++#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
++#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
++#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x10
++#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L
++#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L
++#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x00000020L
++#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x00000040L
++#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x00000080L
++#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x00000100L
++#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x00000200L
++#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x00000400L
++#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x00000800L
++#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xFFFF0000L
++//DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL
++#define DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x0
++#define DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
++#define DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
++#define DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
++#define DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
++#define DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x10
++#define DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x00000001L
++#define DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L
++#define DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x00000100L
++#define DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000200L
++#define DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000400L
++#define DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xFFFF0000L
++//DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH
++#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x0
++#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x4
++#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x5
++#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x6
++#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x7
++#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x8
++#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x9
++#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0xa
++#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0xb
++#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x00000001L
++#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x00000010L
++#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x00000020L
++#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x00000040L
++#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x00000080L
++#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x00000100L
++#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x00000200L
++#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x00000400L
++#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x00000800L
++//DMIFV_PG1_DPGV1_REPEATER_PROGRAM
++#define DMIFV_PG1_DPGV1_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
++#define DMIFV_PG1_DPGV1_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
++#define DMIFV_PG1_DPGV1_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x00000007L
++#define DMIFV_PG1_DPGV1_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x00000070L
++//DMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL
++#define DMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0
++#define DMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x00000001L
++
++
++// addressBlock: dce_dc_blndv1_dispdec
++//BLNDV1_BLNDV_CONTROL
++#define BLNDV1_BLNDV_CONTROL__BLND_GLOBAL_GAIN__SHIFT 0x0
++#define BLNDV1_BLNDV_CONTROL__BLND_MODE__SHIFT 0x8
++#define BLNDV1_BLNDV_CONTROL__BLND_STEREO_TYPE__SHIFT 0xa
++#define BLNDV1_BLNDV_CONTROL__BLND_STEREO_POLARITY__SHIFT 0xc
++#define BLNDV1_BLNDV_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT 0xd
++#define BLNDV1_BLNDV_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10
++#define BLNDV1_BLNDV_CONTROL__BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x12
++#define BLNDV1_BLNDV_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14
++#define BLNDV1_BLNDV_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18
++#define BLNDV1_BLNDV_CONTROL__BLND_GLOBAL_GAIN_MASK 0x000000FFL
++#define BLNDV1_BLNDV_CONTROL__BLND_MODE_MASK 0x00000300L
++#define BLNDV1_BLNDV_CONTROL__BLND_STEREO_TYPE_MASK 0x00000C00L
++#define BLNDV1_BLNDV_CONTROL__BLND_STEREO_POLARITY_MASK 0x00001000L
++#define BLNDV1_BLNDV_CONTROL__BLND_FEEDTHROUGH_EN_MASK 0x00002000L
++#define BLNDV1_BLNDV_CONTROL__BLND_ALPHA_MODE_MASK 0x00030000L
++#define BLNDV1_BLNDV_CONTROL__BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00040000L
++#define BLNDV1_BLNDV_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x00100000L
++#define BLNDV1_BLNDV_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xFF000000L
++//BLNDV1_BLNDV_SM_CONTROL2
++#define BLNDV1_BLNDV_SM_CONTROL2__SM_MODE__SHIFT 0x0
++#define BLNDV1_BLNDV_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4
++#define BLNDV1_BLNDV_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5
++#define BLNDV1_BLNDV_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
++#define BLNDV1_BLNDV_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
++#define BLNDV1_BLNDV_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18
++#define BLNDV1_BLNDV_SM_CONTROL2__SM_MODE_MASK 0x00000007L
++#define BLNDV1_BLNDV_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x00000010L
++#define BLNDV1_BLNDV_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x00000020L
++#define BLNDV1_BLNDV_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L
++#define BLNDV1_BLNDV_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L
++#define BLNDV1_BLNDV_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x01000000L
++//BLNDV1_BLNDV_CONTROL2
++#define BLNDV1_BLNDV_CONTROL2__PTI_ENABLE__SHIFT 0x0
++#define BLNDV1_BLNDV_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT 0x4
++#define BLNDV1_BLNDV_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT 0x6
++#define BLNDV1_BLNDV_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT 0x7
++#define BLNDV1_BLNDV_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT 0x8
++#define BLNDV1_BLNDV_CONTROL2__PTI_ENABLE_MASK 0x00000001L
++#define BLNDV1_BLNDV_CONTROL2__PTI_NEW_PIXEL_GAP_MASK 0x00000030L
++#define BLNDV1_BLNDV_CONTROL2__BLND_NEW_PIXEL_MODE_MASK 0x00000040L
++#define BLNDV1_BLNDV_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK 0x00000080L
++#define BLNDV1_BLNDV_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK 0x00000100L
++//BLNDV1_BLNDV_UPDATE
++#define BLNDV1_BLNDV_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0
++#define BLNDV1_BLNDV_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8
++#define BLNDV1_BLNDV_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10
++#define BLNDV1_BLNDV_UPDATE__BLND_UPDATE_PENDING_MASK 0x00000001L
++#define BLNDV1_BLNDV_UPDATE__BLND_UPDATE_TAKEN_MASK 0x00000100L
++#define BLNDV1_BLNDV_UPDATE__BLND_UPDATE_LOCK_MASK 0x00010000L
++//BLNDV1_BLNDV_UNDERFLOW_INTERRUPT
++#define BLNDV1_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0
++#define BLNDV1_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8
++#define BLNDV1_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc
++#define BLNDV1_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10
++#define BLNDV1_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x00000001L
++#define BLNDV1_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x00000100L
++#define BLNDV1_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x00001000L
++#define BLNDV1_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x00030000L
++//BLNDV1_BLNDV_V_UPDATE_LOCK
++#define BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0
++#define BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1
++#define BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10
++#define BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c
++#define BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT 0x1d
++#define BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT 0x1f
++#define BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x00000001L
++#define BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x00000002L
++#define BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x00010000L
++#define BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000L
++#define BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK 0x20000000L
++#define BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK 0x80000000L
++//BLNDV1_BLNDV_REG_UPDATE_STATUS
++#define BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT 0x0
++#define BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT 0x1
++#define BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2
++#define BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3
++#define BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT 0x6
++#define BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT 0x7
++#define BLNDV1_BLNDV_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT 0x8
++#define BLNDV1_BLNDV_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT 0x9
++#define BLNDV1_BLNDV_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT 0xa
++#define BLNDV1_BLNDV_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT 0xb
++#define BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK 0x00000001L
++#define BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK 0x00000002L
++#define BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK 0x00000004L
++#define BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK 0x00000008L
++#define BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK 0x00000040L
++#define BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK 0x00000080L
++#define BLNDV1_BLNDV_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK 0x00000100L
++#define BLNDV1_BLNDV_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK 0x00000200L
++#define BLNDV1_BLNDV_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK 0x00000400L
++#define BLNDV1_BLNDV_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK 0x00000800L
++
++
++// addressBlock: dce_dc_crtcv1_dispdec
++//CRTCV1_CRTCV_H_BLANK_EARLY_NUM
++#define CRTCV1_CRTCV_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0
++#define CRTCV1_CRTCV_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10
++#define CRTCV1_CRTCV_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x000003FFL
++#define CRTCV1_CRTCV_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x00010000L
++//CRTCV1_CRTCV_H_TOTAL
++#define CRTCV1_CRTCV_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0
++#define CRTCV1_CRTCV_H_TOTAL__CRTC_H_TOTAL_MASK 0x00003FFFL
++//CRTCV1_CRTCV_H_BLANK_START_END
++#define CRTCV1_CRTCV_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0
++#define CRTCV1_CRTCV_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10
++#define CRTCV1_CRTCV_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x00003FFFL
++#define CRTCV1_CRTCV_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3FFF0000L
++//CRTCV1_CRTCV_H_SYNC_A
++#define CRTCV1_CRTCV_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0
++#define CRTCV1_CRTCV_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10
++#define CRTCV1_CRTCV_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x00003FFFL
++#define CRTCV1_CRTCV_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3FFF0000L
++//CRTCV1_CRTCV_H_SYNC_A_CNTL
++#define CRTCV1_CRTCV_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0
++#define CRTCV1_CRTCV_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10
++#define CRTCV1_CRTCV_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11
++#define CRTCV1_CRTCV_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x00000001L
++#define CRTCV1_CRTCV_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x00010000L
++#define CRTCV1_CRTCV_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x00020000L
++//CRTCV1_CRTCV_H_SYNC_B
++#define CRTCV1_CRTCV_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0
++#define CRTCV1_CRTCV_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10
++#define CRTCV1_CRTCV_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x00003FFFL
++#define CRTCV1_CRTCV_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x3FFF0000L
++//CRTCV1_CRTCV_H_SYNC_B_CNTL
++#define CRTCV1_CRTCV_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0
++#define CRTCV1_CRTCV_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10
++#define CRTCV1_CRTCV_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11
++#define CRTCV1_CRTCV_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x00000001L
++#define CRTCV1_CRTCV_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x00010000L
++#define CRTCV1_CRTCV_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x00020000L
++//CRTCV1_CRTCV_VBI_END
++#define CRTCV1_CRTCV_VBI_END__CRTC_VBI_V_END__SHIFT 0x0
++#define CRTCV1_CRTCV_VBI_END__CRTC_VBI_H_END__SHIFT 0x10
++#define CRTCV1_CRTCV_VBI_END__CRTC_VBI_V_END_MASK 0x00003FFFL
++#define CRTCV1_CRTCV_VBI_END__CRTC_VBI_H_END_MASK 0x3FFF0000L
++//CRTCV1_CRTCV_V_TOTAL
++#define CRTCV1_CRTCV_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0
++#define CRTCV1_CRTCV_V_TOTAL__CRTC_V_TOTAL_MASK 0x00003FFFL
++//CRTCV1_CRTCV_V_TOTAL_MIN
++#define CRTCV1_CRTCV_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0
++#define CRTCV1_CRTCV_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x00003FFFL
++//CRTCV1_CRTCV_V_TOTAL_MAX
++#define CRTCV1_CRTCV_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0
++#define CRTCV1_CRTCV_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10
++#define CRTCV1_CRTCV_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x00003FFFL
++#define CRTCV1_CRTCV_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x00010000L
++//CRTCV1_CRTCV_V_TOTAL_CONTROL
++#define CRTCV1_CRTCV_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0
++#define CRTCV1_CRTCV_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4
++#define CRTCV1_CRTCV_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8
++#define CRTCV1_CRTCV_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc
++#define CRTCV1_CRTCV_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf
++#define CRTCV1_CRTCV_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10
++#define CRTCV1_CRTCV_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x00000001L
++#define CRTCV1_CRTCV_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x00000010L
++#define CRTCV1_CRTCV_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x00000100L
++#define CRTCV1_CRTCV_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x00001000L
++#define CRTCV1_CRTCV_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00008000L
++#define CRTCV1_CRTCV_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L
++//CRTCV1_CRTCV_V_TOTAL_INT_STATUS
++#define CRTCV1_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0
++#define CRTCV1_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4
++#define CRTCV1_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8
++#define CRTCV1_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc
++#define CRTCV1_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L
++#define CRTCV1_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L
++#define CRTCV1_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L
++#define CRTCV1_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L
++//CRTCV1_CRTCV_VSYNC_NOM_INT_STATUS
++#define CRTCV1_CRTCV_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0
++#define CRTCV1_CRTCV_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4
++#define CRTCV1_CRTCV_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x00000001L
++#define CRTCV1_CRTCV_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L
++//CRTCV1_CRTCV_V_BLANK_START_END
++#define CRTCV1_CRTCV_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0
++#define CRTCV1_CRTCV_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10
++#define CRTCV1_CRTCV_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x00003FFFL
++#define CRTCV1_CRTCV_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3FFF0000L
++//CRTCV1_CRTCV_V_SYNC_A
++#define CRTCV1_CRTCV_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0
++#define CRTCV1_CRTCV_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10
++#define CRTCV1_CRTCV_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x00003FFFL
++#define CRTCV1_CRTCV_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3FFF0000L
++//CRTCV1_CRTCV_V_SYNC_A_CNTL
++#define CRTCV1_CRTCV_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0
++#define CRTCV1_CRTCV_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x00000001L
++//CRTCV1_CRTCV_V_SYNC_B
++#define CRTCV1_CRTCV_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0
++#define CRTCV1_CRTCV_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10
++#define CRTCV1_CRTCV_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x00003FFFL
++#define CRTCV1_CRTCV_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x3FFF0000L
++//CRTCV1_CRTCV_V_SYNC_B_CNTL
++#define CRTCV1_CRTCV_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0
++#define CRTCV1_CRTCV_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x00000001L
++//CRTCV1_CRTCV_DTMTEST_CNTL
++#define CRTCV1_CRTCV_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0
++#define CRTCV1_CRTCV_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1
++#define CRTCV1_CRTCV_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x00000001L
++#define CRTCV1_CRTCV_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x0000001EL
++//CRTCV1_CRTCV_DTMTEST_STATUS_POSITION
++#define CRTCV1_CRTCV_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0
++#define CRTCV1_CRTCV_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10
++#define CRTCV1_CRTCV_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x00003FFFL
++#define CRTCV1_CRTCV_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x3FFF0000L
++//CRTCV1_CRTCV_TRIGA_CNTL
++#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0
++#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5
++#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8
++#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9
++#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa
++#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb
++#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
++#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
++#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14
++#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18
++#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f
++#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x0000001FL
++#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0x000000E0L
++#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000100L
++#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x00000200L
++#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x00000400L
++#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x00000800L
++#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
++#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
++#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L
++#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1F000000L
++#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000L
++//CRTCV1_CRTCV_TRIGA_MANUAL_TRIG
++#define CRTCV1_CRTCV_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0
++#define CRTCV1_CRTCV_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x00000001L
++//CRTCV1_CRTCV_TRIGB_CNTL
++#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0
++#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5
++#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8
++#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9
++#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa
++#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb
++#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
++#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
++#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14
++#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18
++#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f
++#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x0000001FL
++#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0x000000E0L
++#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000100L
++#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x00000200L
++#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x00000400L
++#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x00000800L
++#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
++#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
++#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L
++#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1F000000L
++#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000L
++//CRTCV1_CRTCV_TRIGB_MANUAL_TRIG
++#define CRTCV1_CRTCV_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0
++#define CRTCV1_CRTCV_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x00000001L
++//CRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL
++#define CRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0
++#define CRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4
++#define CRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8
++#define CRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10
++#define CRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18
++#define CRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x00000003L
++#define CRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L
++#define CRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L
++#define CRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L
++#define CRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L
++//CRTCV1_CRTCV_FLOW_CONTROL
++#define CRTCV1_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0
++#define CRTCV1_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8
++#define CRTCV1_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10
++#define CRTCV1_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18
++#define CRTCV1_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL
++#define CRTCV1_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x00000100L
++#define CRTCV1_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L
++#define CRTCV1_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L
++//CRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE
++#define CRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0
++#define CRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER__SHIFT 0x8
++#define CRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER__SHIFT 0x10
++#define CRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L
++#define CRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L
++#define CRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L
++//CRTCV1_CRTCV_AVSYNC_COUNTER
++#define CRTCV1_CRTCV_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER__SHIFT 0x0
++#define CRTCV1_CRTCV_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER_MASK 0xFFFFFFFFL
++//CRTCV1_CRTCV_CONTROL
++#define CRTCV1_CRTCV_CONTROL__CRTC_MASTER_EN__SHIFT 0x0
++#define CRTCV1_CRTCV_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4
++#define CRTCV1_CRTCV_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8
++#define CRTCV1_CRTCV_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc
++#define CRTCV1_CRTCV_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd
++#define CRTCV1_CRTCV_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe
++#define CRTCV1_CRTCV_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10
++#define CRTCV1_CRTCV_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14
++#define CRTCV1_CRTCV_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d
++#define CRTCV1_CRTCV_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e
++#define CRTCV1_CRTCV_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f
++#define CRTCV1_CRTCV_CONTROL__CRTC_MASTER_EN_MASK 0x00000001L
++#define CRTCV1_CRTCV_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x00000010L
++#define CRTCV1_CRTCV_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x00000300L
++#define CRTCV1_CRTCV_CONTROL__CRTC_START_POINT_CNTL_MASK 0x00001000L
++#define CRTCV1_CRTCV_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x00002000L
++#define CRTCV1_CRTCV_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x00004000L
++#define CRTCV1_CRTCV_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x00010000L
++#define CRTCV1_CRTCV_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x00700000L
++#define CRTCV1_CRTCV_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000L
++#define CRTCV1_CRTCV_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L
++#define CRTCV1_CRTCV_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L
++//CRTCV1_CRTCV_BLANK_CONTROL
++#define CRTCV1_CRTCV_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0
++#define CRTCV1_CRTCV_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8
++#define CRTCV1_CRTCV_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10
++#define CRTCV1_CRTCV_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x00000001L
++#define CRTCV1_CRTCV_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x00000100L
++#define CRTCV1_CRTCV_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x00010000L
++//CRTCV1_CRTCV_INTERLACE_CONTROL
++#define CRTCV1_CRTCV_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0
++#define CRTCV1_CRTCV_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10
++#define CRTCV1_CRTCV_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x00000001L
++#define CRTCV1_CRTCV_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L
++//CRTCV1_CRTCV_INTERLACE_STATUS
++#define CRTCV1_CRTCV_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0
++#define CRTCV1_CRTCV_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1
++#define CRTCV1_CRTCV_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x00000001L
++#define CRTCV1_CRTCV_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x00000002L
++//CRTCV1_CRTCV_FIELD_INDICATION_CONTROL
++#define CRTCV1_CRTCV_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0
++#define CRTCV1_CRTCV_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1
++#define CRTCV1_CRTCV_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x00000001L
++#define CRTCV1_CRTCV_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x00000002L
++//CRTCV1_CRTCV_PIXEL_DATA_READBACK0
++#define CRTCV1_CRTCV_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0
++#define CRTCV1_CRTCV_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10
++#define CRTCV1_CRTCV_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0x00000FFFL
++#define CRTCV1_CRTCV_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0x0FFF0000L
++//CRTCV1_CRTCV_PIXEL_DATA_READBACK1
++#define CRTCV1_CRTCV_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0
++#define CRTCV1_CRTCV_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0x00000FFFL
++//CRTCV1_CRTCV_STATUS
++#define CRTCV1_CRTCV_STATUS__CRTC_V_BLANK__SHIFT 0x0
++#define CRTCV1_CRTCV_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1
++#define CRTCV1_CRTCV_STATUS__CRTC_V_SYNC_A__SHIFT 0x2
++#define CRTCV1_CRTCV_STATUS__CRTC_V_UPDATE__SHIFT 0x3
++#define CRTCV1_CRTCV_STATUS__CRTC_V_START_LINE__SHIFT 0x4
++#define CRTCV1_CRTCV_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5
++#define CRTCV1_CRTCV_STATUS__CRTC_H_BLANK__SHIFT 0x10
++#define CRTCV1_CRTCV_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11
++#define CRTCV1_CRTCV_STATUS__CRTC_H_SYNC_A__SHIFT 0x12
++#define CRTCV1_CRTCV_STATUS__CRTC_V_BLANK_MASK 0x00000001L
++#define CRTCV1_CRTCV_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x00000002L
++#define CRTCV1_CRTCV_STATUS__CRTC_V_SYNC_A_MASK 0x00000004L
++#define CRTCV1_CRTCV_STATUS__CRTC_V_UPDATE_MASK 0x00000008L
++#define CRTCV1_CRTCV_STATUS__CRTC_V_START_LINE_MASK 0x00000010L
++#define CRTCV1_CRTCV_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x00000020L
++#define CRTCV1_CRTCV_STATUS__CRTC_H_BLANK_MASK 0x00010000L
++#define CRTCV1_CRTCV_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x00020000L
++#define CRTCV1_CRTCV_STATUS__CRTC_H_SYNC_A_MASK 0x00040000L
++//CRTCV1_CRTCV_STATUS_POSITION
++#define CRTCV1_CRTCV_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0
++#define CRTCV1_CRTCV_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10
++#define CRTCV1_CRTCV_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x00003FFFL
++#define CRTCV1_CRTCV_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x3FFF0000L
++//CRTCV1_CRTCV_NOM_VERT_POSITION
++#define CRTCV1_CRTCV_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0
++#define CRTCV1_CRTCV_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x00003FFFL
++//CRTCV1_CRTCV_STATUS_FRAME_COUNT
++#define CRTCV1_CRTCV_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0
++#define CRTCV1_CRTCV_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0x00FFFFFFL
++//CRTCV1_CRTCV_STATUS_VF_COUNT
++#define CRTCV1_CRTCV_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0
++#define CRTCV1_CRTCV_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x3FFFFFFFL
++//CRTCV1_CRTCV_STATUS_HV_COUNT
++#define CRTCV1_CRTCV_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0
++#define CRTCV1_CRTCV_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x3FFFFFFFL
++//CRTCV1_CRTCV_COUNT_CONTROL
++#define CRTCV1_CRTCV_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0
++#define CRTCV1_CRTCV_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1
++#define CRTCV1_CRTCV_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x00000001L
++#define CRTCV1_CRTCV_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x0000001EL
++//CRTCV1_CRTCV_COUNT_RESET
++#define CRTCV1_CRTCV_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0
++#define CRTCV1_CRTCV_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x00000001L
++//CRTCV1_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE
++#define CRTCV1_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0
++#define CRTCV1_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L
++//CRTCV1_CRTCV_VERT_SYNC_CONTROL
++#define CRTCV1_CRTCV_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0
++#define CRTCV1_CRTCV_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8
++#define CRTCV1_CRTCV_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10
++#define CRTCV1_CRTCV_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L
++#define CRTCV1_CRTCV_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L
++#define CRTCV1_CRTCV_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L
++//CRTCV1_CRTCV_STEREO_STATUS
++#define CRTCV1_CRTCV_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0
++#define CRTCV1_CRTCV_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8
++#define CRTCV1_CRTCV_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10
++#define CRTCV1_CRTCV_STEREO_STATUS__CRTC_STEREO_EYE_FLAG__SHIFT 0x14
++#define CRTCV1_CRTCV_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18
++#define CRTCV1_CRTCV_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x00000001L
++#define CRTCV1_CRTCV_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x00000100L
++#define CRTCV1_CRTCV_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x00010000L
++#define CRTCV1_CRTCV_STEREO_STATUS__CRTC_STEREO_EYE_FLAG_MASK 0x00100000L
++#define CRTCV1_CRTCV_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L
++//CRTCV1_CRTCV_STEREO_CONTROL
++#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0
++#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf
++#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10
++#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11
++#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12
++#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM__SHIFT 0x13
++#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14
++#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18
++#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00003FFFL
++#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L
++#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x00010000L
++#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L
++#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L
++#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM_MASK 0x00080000L
++#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L
++#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x01000000L
++//CRTCV1_CRTCV_SNAPSHOT_STATUS
++#define CRTCV1_CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0
++#define CRTCV1_CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1
++#define CRTCV1_CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2
++#define CRTCV1_CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x00000001L
++#define CRTCV1_CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x00000002L
++#define CRTCV1_CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L
++//CRTCV1_CRTCV_SNAPSHOT_CONTROL
++#define CRTCV1_CRTCV_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0
++#define CRTCV1_CRTCV_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L
++//CRTCV1_CRTCV_SNAPSHOT_POSITION
++#define CRTCV1_CRTCV_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0
++#define CRTCV1_CRTCV_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10
++#define CRTCV1_CRTCV_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x00003FFFL
++#define CRTCV1_CRTCV_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x3FFF0000L
++//CRTCV1_CRTCV_SNAPSHOT_FRAME
++#define CRTCV1_CRTCV_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0
++#define CRTCV1_CRTCV_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL
++//CRTCV1_CRTCV_START_LINE_CONTROL
++#define CRTCV1_CRTCV_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0
++#define CRTCV1_CRTCV_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x1
++#define CRTCV1_CRTCV_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x2
++#define CRTCV1_CRTCV_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x8
++#define CRTCV1_CRTCV_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc
++#define CRTCV1_CRTCV_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x00000001L
++#define CRTCV1_CRTCV_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x00000002L
++#define CRTCV1_CRTCV_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x00000004L
++#define CRTCV1_CRTCV_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x00000100L
++#define CRTCV1_CRTCV_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0x000FF000L
++//CRTCV1_CRTCV_INTERRUPT_CONTROL
++#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0
++#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1
++#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4
++#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5
++#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8
++#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9
++#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10
++#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11
++#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18
++#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19
++#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a
++#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b
++#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c
++#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d
++#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e
++#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f
++#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x00000001L
++#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x00000002L
++#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x00000010L
++#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x00000020L
++#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L
++#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L
++#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L
++#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L
++#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x01000000L
++#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x02000000L
++#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x04000000L
++#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x08000000L
++#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000L
++#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000L
++#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L
++#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L
++//CRTCV1_CRTCV_UPDATE_LOCK
++#define CRTCV1_CRTCV_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0
++#define CRTCV1_CRTCV_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x00000001L
++//CRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL
++#define CRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0
++#define CRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8
++#define CRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10
++#define CRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18
++#define CRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x19
++#define CRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x00000001L
++#define CRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x00000100L
++#define CRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L
++#define CRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x01000000L
++#define CRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x02000000L
++//CRTCV1_CRTCV_VGA_PARAMETER_CAPTURE_MODE
++#define CRTCV1_CRTCV_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0
++#define CRTCV1_CRTCV_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x00000001L
++//CRTCV1_CRTCV_TEST_PATTERN_CONTROL
++#define CRTCV1_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0
++#define CRTCV1_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8
++#define CRTCV1_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10
++#define CRTCV1_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18
++#define CRTCV1_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x00000001L
++#define CRTCV1_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x00000700L
++#define CRTCV1_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L
++#define CRTCV1_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xFF000000L
++//CRTCV1_CRTCV_TEST_PATTERN_PARAMETERS
++#define CRTCV1_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0
++#define CRTCV1_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4
++#define CRTCV1_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8
++#define CRTCV1_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc
++#define CRTCV1_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10
++#define CRTCV1_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0x0000000FL
++#define CRTCV1_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0x000000F0L
++#define CRTCV1_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0x00000F00L
++#define CRTCV1_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0x0000F000L
++#define CRTCV1_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xFFFF0000L
++//CRTCV1_CRTCV_TEST_PATTERN_COLOR
++#define CRTCV1_CRTCV_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0
++#define CRTCV1_CRTCV_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10
++#define CRTCV1_CRTCV_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0x0000FFFFL
++#define CRTCV1_CRTCV_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x003F0000L
++//CRTCV1_CRTCV_MASTER_UPDATE_LOCK
++#define CRTCV1_CRTCV_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0
++#define CRTCV1_CRTCV_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8
++#define CRTCV1_CRTCV_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK__SHIFT 0x10
++#define CRTCV1_CRTCV_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x00000001L
++#define CRTCV1_CRTCV_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x00000100L
++#define CRTCV1_CRTCV_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK_MASK 0x00010000L
++//CRTCV1_CRTCV_MASTER_UPDATE_MODE
++#define CRTCV1_CRTCV_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0
++#define CRTCV1_CRTCV_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10
++#define CRTCV1_CRTCV_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x00000007L
++#define CRTCV1_CRTCV_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00030000L
++//CRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT
++#define CRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0
++#define CRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8
++#define CRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x00000003L
++#define CRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xFFFFFF00L
++//CRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER
++#define CRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0
++#define CRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0x000000FFL
++//CRTCV1_CRTCV_MVP_STATUS
++#define CRTCV1_CRTCV_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0
++#define CRTCV1_CRTCV_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4
++#define CRTCV1_CRTCV_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10
++#define CRTCV1_CRTCV_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14
++#define CRTCV1_CRTCV_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x00000001L
++#define CRTCV1_CRTCV_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x00000010L
++#define CRTCV1_CRTCV_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x00010000L
++#define CRTCV1_CRTCV_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x00100000L
++//CRTCV1_CRTCV_MASTER_EN
++#define CRTCV1_CRTCV_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0
++#define CRTCV1_CRTCV_MASTER_EN__CRTC_MASTER_EN_MASK 0x00000001L
++//CRTCV1_CRTCV_ALLOW_STOP_OFF_V_CNT
++#define CRTCV1_CRTCV_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0
++#define CRTCV1_CRTCV_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10
++#define CRTCV1_CRTCV_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0x000000FFL
++#define CRTCV1_CRTCV_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x00010000L
++//CRTCV1_CRTCV_V_UPDATE_INT_STATUS
++#define CRTCV1_CRTCV_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0
++#define CRTCV1_CRTCV_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8
++#define CRTCV1_CRTCV_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x00000001L
++#define CRTCV1_CRTCV_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x00000100L
++//CRTCV1_CRTCV_OVERSCAN_COLOR
++#define CRTCV1_CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0
++#define CRTCV1_CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa
++#define CRTCV1_CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14
++#define CRTCV1_CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x000003FFL
++#define CRTCV1_CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0x000FFC00L
++#define CRTCV1_CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3FF00000L
++//CRTCV1_CRTCV_OVERSCAN_COLOR_EXT
++#define CRTCV1_CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0
++#define CRTCV1_CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8
++#define CRTCV1_CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10
++#define CRTCV1_CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x00000003L
++#define CRTCV1_CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x00000300L
++#define CRTCV1_CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x00030000L
++//CRTCV1_CRTCV_BLANK_DATA_COLOR
++#define CRTCV1_CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0
++#define CRTCV1_CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa
++#define CRTCV1_CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14
++#define CRTCV1_CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL
++#define CRTCV1_CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L
++#define CRTCV1_CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L
++//CRTCV1_CRTCV_BLANK_DATA_COLOR_EXT
++#define CRTCV1_CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0
++#define CRTCV1_CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8
++#define CRTCV1_CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10
++#define CRTCV1_CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x00000003L
++#define CRTCV1_CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00000300L
++#define CRTCV1_CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x00030000L
++//CRTCV1_CRTCV_BLACK_COLOR
++#define CRTCV1_CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0
++#define CRTCV1_CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa
++#define CRTCV1_CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14
++#define CRTCV1_CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x000003FFL
++#define CRTCV1_CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0x000FFC00L
++#define CRTCV1_CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3FF00000L
++//CRTCV1_CRTCV_BLACK_COLOR_EXT
++#define CRTCV1_CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0
++#define CRTCV1_CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8
++#define CRTCV1_CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10
++#define CRTCV1_CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x00000003L
++#define CRTCV1_CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x00000300L
++#define CRTCV1_CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x00030000L
++//CRTCV1_CRTCV_VERTICAL_INTERRUPT0_POSITION
++#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0
++#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10
++#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00003FFFL
++#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x3FFF0000L
++//CRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL
++#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4
++#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8
++#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc
++#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10
++#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14
++#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18
++#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L
++#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L
++#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L
++#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L
++#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L
++#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L
++//CRTCV1_CRTCV_VERTICAL_INTERRUPT1_POSITION
++#define CRTCV1_CRTCV_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0
++#define CRTCV1_CRTCV_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00003FFFL
++//CRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL
++#define CRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8
++#define CRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc
++#define CRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10
++#define CRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14
++#define CRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18
++#define CRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L
++#define CRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L
++#define CRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L
++#define CRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L
++#define CRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L
++//CRTCV1_CRTCV_VERTICAL_INTERRUPT2_POSITION
++#define CRTCV1_CRTCV_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0
++#define CRTCV1_CRTCV_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00003FFFL
++//CRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL
++#define CRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8
++#define CRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc
++#define CRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10
++#define CRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14
++#define CRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18
++#define CRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L
++#define CRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L
++#define CRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L
++#define CRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L
++#define CRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L
++//CRTCV1_CRTCV_CRC_CNTL
++#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0
++#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4
++#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8
++#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc
++#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
++#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14
++#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18
++#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC_EN_MASK 0x00000001L
++#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x00000010L
++#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x00000300L
++#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x00003000L
++#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
++#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x00700000L
++#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x07000000L
++//CRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL
++#define CRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0
++#define CRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10
++#define CRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x00003FFFL
++#define CRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3FFF0000L
++//CRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL
++#define CRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0
++#define CRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10
++#define CRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x00003FFFL
++#define CRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3FFF0000L
++//CRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL
++#define CRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0
++#define CRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10
++#define CRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x00003FFFL
++#define CRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3FFF0000L
++//CRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL
++#define CRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0
++#define CRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10
++#define CRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x00003FFFL
++#define CRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3FFF0000L
++//CRTCV1_CRTCV_CRC0_DATA_RG
++#define CRTCV1_CRTCV_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0
++#define CRTCV1_CRTCV_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10
++#define CRTCV1_CRTCV_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL
++#define CRTCV1_CRTCV_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L
++//CRTCV1_CRTCV_CRC0_DATA_B
++#define CRTCV1_CRTCV_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0
++#define CRTCV1_CRTCV_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL
++//CRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL
++#define CRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0
++#define CRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10
++#define CRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x00003FFFL
++#define CRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3FFF0000L
++//CRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL
++#define CRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0
++#define CRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10
++#define CRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x00003FFFL
++#define CRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3FFF0000L
++//CRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL
++#define CRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0
++#define CRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10
++#define CRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x00003FFFL
++#define CRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3FFF0000L
++//CRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL
++#define CRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0
++#define CRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10
++#define CRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x00003FFFL
++#define CRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3FFF0000L
++//CRTCV1_CRTCV_CRC1_DATA_RG
++#define CRTCV1_CRTCV_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0
++#define CRTCV1_CRTCV_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10
++#define CRTCV1_CRTCV_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL
++#define CRTCV1_CRTCV_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L
++//CRTCV1_CRTCV_CRC1_DATA_B
++#define CRTCV1_CRTCV_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0
++#define CRTCV1_CRTCV_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL
++//CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE__SHIFT 0x0
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__SHIFT 0x3
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__SHIFT 0x4
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__SHIFT 0x5
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__SHIFT 0x8
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__SHIFT 0x9
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__SHIFT 0xc
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__SHIFT 0xd
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__SHIFT 0xe
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE__SHIFT 0x18
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE__SHIFT 0x1c
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE_MASK 0x00000003L
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_MASK 0x00000008L
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_MASK 0x00000010L
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_MASK 0x00000060L
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_MASK 0x00000100L
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_MASK 0x00000200L
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_MASK 0x00001000L
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_MASK 0x00002000L
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_MASK 0x00004000L
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE_MASK 0x07000000L
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE_MASK 0x70000000L
++//CRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_START
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X__SHIFT 0x0
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y__SHIFT 0x10
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X_MASK 0x00003FFFL
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y_MASK 0x3FFF0000L
++//CRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_END
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X__SHIFT 0x0
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y__SHIFT 0x10
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X_MASK 0x00003FFFL
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y_MASK 0x3FFF0000L
++//CRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__SHIFT 0x0
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS__SHIFT 0x4
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS__SHIFT 0x8
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__SHIFT 0x10
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__SHIFT 0x14
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__SHIFT 0x1d
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_MASK 0x00000001L
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS_MASK 0x00000010L
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS_MASK 0x00000100L
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_MASK 0x00010000L
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_MASK 0x00100000L
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_MASK 0xE0000000L
++//CRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE__SHIFT 0x0
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS__SHIFT 0x4
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS__SHIFT 0x8
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR__SHIFT 0x10
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE__SHIFT 0x14
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE_MASK 0x00000001L
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS_MASK 0x00000010L
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS_MASK 0x00000100L
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR_MASK 0x00010000L
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE_MASK 0x00100000L
++//CRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__SHIFT 0x0
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS__SHIFT 0x4
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS__SHIFT 0x8
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__SHIFT 0x10
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__SHIFT 0x14
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_MASK 0x00000001L
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS_MASK 0x00000010L
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS_MASK 0x00000100L
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_MASK 0x00010000L
++#define CRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_MASK 0x00100000L
++//CRTCV1_CRTCV_STATIC_SCREEN_CONTROL
++#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0
++#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10
++#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18
++#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19
++#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a
++#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b
++#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c
++#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL
++#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L
++#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x01000000L
++#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x02000000L
++#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x04000000L
++#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x08000000L
++#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000L
++//CRTCV1_CRTCV_3D_STRUCTURE_CONTROL
++#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0
++#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4
++#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8
++#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc
++#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10
++#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11
++#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12
++#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x00000001L
++#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x00000010L
++#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L
++#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L
++#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L
++#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L
++#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L
++//CRTCV1_CRTCV_GSL_VSYNC_GAP
++#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0
++#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8
++#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10
++#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11
++#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13
++#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14
++#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17
++#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18
++#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL
++#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L
++#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L
++#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x00060000L
++#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L
++#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L
++#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L
++#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xFF000000L
++//CRTCV1_CRTCV_GSL_WINDOW
++#define CRTCV1_CRTCV_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0
++#define CRTCV1_CRTCV_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10
++#define CRTCV1_CRTCV_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x00003FFFL
++#define CRTCV1_CRTCV_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x3FFF0000L
++//CRTCV1_CRTCV_GSL_CONTROL
++#define CRTCV1_CRTCV_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0
++#define CRTCV1_CRTCV_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10
++#define CRTCV1_CRTCV_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c
++#define CRTCV1_CRTCV_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x00003FFFL
++#define CRTCV1_CRTCV_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x001F0000L
++#define CRTCV1_CRTCV_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L
++
++
++// addressBlock: dce_dc_hpd0_dispdec
++//HPD0_DC_HPD_INT_STATUS
++#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0
++#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1
++#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4
++#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8
++#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
++#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
++#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L
++#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L
++#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L
++#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L
++#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L
++#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L
++//HPD0_DC_HPD_INT_CONTROL
++#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0
++#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8
++#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10
++#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14
++#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18
++#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L
++#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L
++#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L
++#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L
++#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L
++//HPD0_DC_HPD_CONTROL
++#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0
++#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10
++#define HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c
++#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL
++#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L
++#define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L
++//HPD0_DC_HPD_FAST_TRAIN_CNTL
++#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0
++#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
++#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18
++#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
++#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL
++#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L
++#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L
++#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L
++//HPD0_DC_HPD_TOGGLE_FILT_CNTL
++#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0
++#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14
++#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL
++#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L
++
++
++// addressBlock: dce_dc_hpd1_dispdec
++//HPD1_DC_HPD_INT_STATUS
++#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0
++#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1
++#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4
++#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8
++#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
++#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
++#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L
++#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L
++#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L
++#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L
++#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L
++#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L
++//HPD1_DC_HPD_INT_CONTROL
++#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0
++#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8
++#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10
++#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14
++#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18
++#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L
++#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L
++#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L
++#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L
++#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L
++//HPD1_DC_HPD_CONTROL
++#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0
++#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10
++#define HPD1_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c
++#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL
++#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L
++#define HPD1_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L
++//HPD1_DC_HPD_FAST_TRAIN_CNTL
++#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0
++#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
++#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18
++#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
++#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL
++#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L
++#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L
++#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L
++//HPD1_DC_HPD_TOGGLE_FILT_CNTL
++#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0
++#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14
++#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL
++#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L
++
++
++// addressBlock: dce_dc_hpd2_dispdec
++//HPD2_DC_HPD_INT_STATUS
++#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0
++#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1
++#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4
++#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8
++#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
++#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
++#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L
++#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L
++#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L
++#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L
++#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L
++#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L
++//HPD2_DC_HPD_INT_CONTROL
++#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0
++#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8
++#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10
++#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14
++#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18
++#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L
++#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L
++#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L
++#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L
++#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L
++//HPD2_DC_HPD_CONTROL
++#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0
++#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10
++#define HPD2_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c
++#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL
++#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L
++#define HPD2_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L
++//HPD2_DC_HPD_FAST_TRAIN_CNTL
++#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0
++#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
++#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18
++#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
++#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL
++#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L
++#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L
++#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L
++//HPD2_DC_HPD_TOGGLE_FILT_CNTL
++#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0
++#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14
++#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL
++#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L
++
++
++// addressBlock: dce_dc_hpd3_dispdec
++//HPD3_DC_HPD_INT_STATUS
++#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0
++#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1
++#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4
++#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8
++#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
++#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
++#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L
++#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L
++#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L
++#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L
++#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L
++#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L
++//HPD3_DC_HPD_INT_CONTROL
++#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0
++#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8
++#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10
++#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14
++#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18
++#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L
++#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L
++#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L
++#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L
++#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L
++//HPD3_DC_HPD_CONTROL
++#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0
++#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10
++#define HPD3_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c
++#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL
++#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L
++#define HPD3_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L
++//HPD3_DC_HPD_FAST_TRAIN_CNTL
++#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0
++#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
++#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18
++#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
++#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL
++#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L
++#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L
++#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L
++//HPD3_DC_HPD_TOGGLE_FILT_CNTL
++#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0
++#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14
++#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL
++#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L
++
++
++// addressBlock: dce_dc_hpd4_dispdec
++//HPD4_DC_HPD_INT_STATUS
++#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0
++#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1
++#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4
++#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8
++#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
++#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
++#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L
++#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L
++#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L
++#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L
++#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L
++#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L
++//HPD4_DC_HPD_INT_CONTROL
++#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0
++#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8
++#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10
++#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14
++#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18
++#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L
++#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L
++#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L
++#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L
++#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L
++//HPD4_DC_HPD_CONTROL
++#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0
++#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10
++#define HPD4_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c
++#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL
++#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L
++#define HPD4_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L
++//HPD4_DC_HPD_FAST_TRAIN_CNTL
++#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0
++#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
++#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18
++#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
++#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL
++#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L
++#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L
++#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L
++//HPD4_DC_HPD_TOGGLE_FILT_CNTL
++#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0
++#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14
++#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL
++#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L
++
++
++// addressBlock: dce_dc_hpd5_dispdec
++//HPD5_DC_HPD_INT_STATUS
++#define HPD5_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0
++#define HPD5_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1
++#define HPD5_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4
++#define HPD5_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8
++#define HPD5_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
++#define HPD5_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
++#define HPD5_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L
++#define HPD5_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L
++#define HPD5_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L
++#define HPD5_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L
++#define HPD5_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L
++#define HPD5_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L
++//HPD5_DC_HPD_INT_CONTROL
++#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0
++#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8
++#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10
++#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14
++#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18
++#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L
++#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L
++#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L
++#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L
++#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L
++//HPD5_DC_HPD_CONTROL
++#define HPD5_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0
++#define HPD5_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10
++#define HPD5_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c
++#define HPD5_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL
++#define HPD5_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L
++#define HPD5_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L
++//HPD5_DC_HPD_FAST_TRAIN_CNTL
++#define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0
++#define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
++#define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18
++#define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
++#define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL
++#define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L
++#define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L
++#define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L
++//HPD5_DC_HPD_TOGGLE_FILT_CNTL
++#define HPD5_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0
++#define HPD5_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14
++#define HPD5_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL
++#define HPD5_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L
++
++
++// addressBlock: dce_dc_dc_perfmon2_dispdec
++//DC_PERFMON2_PERFCOUNTER_CNTL
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
++//DC_PERFMON2_PERFCOUNTER_CNTL2
++#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
++#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
++#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
++#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
++#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
++#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
++#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
++#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
++//DC_PERFMON2_PERFCOUNTER_STATE
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
++//DC_PERFMON2_PERFMON_CNTL
++#define DC_PERFMON2_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
++#define DC_PERFMON2_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
++#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
++#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
++#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
++#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
++#define DC_PERFMON2_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
++#define DC_PERFMON2_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
++#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
++#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
++#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
++#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
++//DC_PERFMON2_PERFMON_CNTL2
++#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
++#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
++#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
++#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
++#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
++#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
++#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
++#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
++//DC_PERFMON2_PERFMON_CVALUE_INT_MISC
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
++//DC_PERFMON2_PERFMON_CVALUE_LOW
++#define DC_PERFMON2_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
++#define DC_PERFMON2_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
++//DC_PERFMON2_PERFMON_HI
++#define DC_PERFMON2_PERFMON_HI__PERFMON_HI__SHIFT 0x0
++#define DC_PERFMON2_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
++#define DC_PERFMON2_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
++#define DC_PERFMON2_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
++//DC_PERFMON2_PERFMON_LOW
++#define DC_PERFMON2_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
++#define DC_PERFMON2_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dp_aux0_dispdec
++//DP_AUX0_AUX_CONTROL
++#define DP_AUX0_AUX_CONTROL__AUX_EN__SHIFT 0x0
++#define DP_AUX0_AUX_CONTROL__AUX_RESET__SHIFT 0x4
++#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5
++#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8
++#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc
++#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10
++#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12
++#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14
++#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18
++#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c
++#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d
++#define DP_AUX0_AUX_CONTROL__SPARE_0__SHIFT 0x1e
++#define DP_AUX0_AUX_CONTROL__SPARE_1__SHIFT 0x1f
++#define DP_AUX0_AUX_CONTROL__AUX_EN_MASK 0x00000001L
++#define DP_AUX0_AUX_CONTROL__AUX_RESET_MASK 0x00000010L
++#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L
++#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L
++#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L
++#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L
++#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L
++#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L
++#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L
++#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L
++#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L
++#define DP_AUX0_AUX_CONTROL__SPARE_0_MASK 0x40000000L
++#define DP_AUX0_AUX_CONTROL__SPARE_1_MASK 0x80000000L
++//DP_AUX0_AUX_SW_CONTROL
++#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0
++#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2
++#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4
++#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10
++#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L
++#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L
++#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L
++#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L
++//DP_AUX0_AUX_ARB_CONTROL
++#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0
++#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2
++#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8
++#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa
++#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10
++#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10
++#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11
++#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18
++#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18
++#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19
++#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L
++#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL
++#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L
++#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L
++#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L
++#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L
++#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L
++#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L
++#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L
++#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L
++//DP_AUX0_AUX_INTERRUPT_CONTROL
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L
++//DP_AUX0_AUX_SW_STATUS
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18
++#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L
++#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xC0000000L
++//DP_AUX0_AUX_LS_STATUS
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L
++//DP_AUX0_AUX_SW_DATA
++#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0
++#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8
++#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10
++#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f
++#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L
++#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L
++#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L
++#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L
++//DP_AUX0_AUX_LS_DATA
++#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8
++#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10
++#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L
++#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L
++//DP_AUX0_AUX_DPHY_TX_REF_CONTROL
++#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0
++#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4
++#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10
++#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L
++#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L
++#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L
++//DP_AUX0_AUX_DPHY_TX_CONTROL
++#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0
++#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8
++#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10
++#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x00000007L
++#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L
++#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L
++//DP_AUX0_AUX_DPHY_RX_CONTROL0
++#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4
++#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8
++#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc
++#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10
++#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11
++#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12
++#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13
++#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14
++#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18
++#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c
++#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L
++#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L
++#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L
++#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L
++#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L
++#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L
++#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L
++#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L
++#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x07000000L
++#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L
++//DP_AUX0_AUX_DPHY_RX_CONTROL1
++#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0
++#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL
++//DP_AUX0_AUX_DPHY_TX_STATUS
++#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0
++#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4
++#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10
++#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L
++#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L
++#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L
++//DP_AUX0_AUX_DPHY_RX_STATUS
++#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0
++#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8
++#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10
++#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15
++#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L
++#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L
++#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L
++#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L
++//DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL
++#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0
++#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8
++#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10
++#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14
++#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL
++#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L
++#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L
++#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L
++//DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L
++//DP_AUX0_AUX_GTC_SYNC_STATUS
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L
++
++
++// addressBlock: dce_dc_dp_aux1_dispdec
++//DP_AUX1_AUX_CONTROL
++#define DP_AUX1_AUX_CONTROL__AUX_EN__SHIFT 0x0
++#define DP_AUX1_AUX_CONTROL__AUX_RESET__SHIFT 0x4
++#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5
++#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8
++#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc
++#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10
++#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12
++#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14
++#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18
++#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c
++#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d
++#define DP_AUX1_AUX_CONTROL__SPARE_0__SHIFT 0x1e
++#define DP_AUX1_AUX_CONTROL__SPARE_1__SHIFT 0x1f
++#define DP_AUX1_AUX_CONTROL__AUX_EN_MASK 0x00000001L
++#define DP_AUX1_AUX_CONTROL__AUX_RESET_MASK 0x00000010L
++#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L
++#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L
++#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L
++#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L
++#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L
++#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L
++#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L
++#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L
++#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L
++#define DP_AUX1_AUX_CONTROL__SPARE_0_MASK 0x40000000L
++#define DP_AUX1_AUX_CONTROL__SPARE_1_MASK 0x80000000L
++//DP_AUX1_AUX_SW_CONTROL
++#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0
++#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2
++#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4
++#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10
++#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L
++#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L
++#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L
++#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L
++//DP_AUX1_AUX_ARB_CONTROL
++#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0
++#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2
++#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8
++#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa
++#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10
++#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10
++#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11
++#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18
++#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18
++#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19
++#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L
++#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL
++#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L
++#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L
++#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L
++#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L
++#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L
++#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L
++#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L
++#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L
++//DP_AUX1_AUX_INTERRUPT_CONTROL
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L
++//DP_AUX1_AUX_SW_STATUS
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18
++#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L
++#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xC0000000L
++//DP_AUX1_AUX_LS_STATUS
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L
++//DP_AUX1_AUX_SW_DATA
++#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0
++#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8
++#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10
++#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f
++#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L
++#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L
++#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L
++#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L
++//DP_AUX1_AUX_LS_DATA
++#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8
++#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10
++#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L
++#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L
++//DP_AUX1_AUX_DPHY_TX_REF_CONTROL
++#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0
++#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4
++#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10
++#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L
++#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L
++#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L
++//DP_AUX1_AUX_DPHY_TX_CONTROL
++#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0
++#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8
++#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10
++#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x00000007L
++#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L
++#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L
++//DP_AUX1_AUX_DPHY_RX_CONTROL0
++#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4
++#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8
++#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc
++#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10
++#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11
++#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12
++#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13
++#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14
++#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18
++#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c
++#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L
++#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L
++#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L
++#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L
++#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L
++#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L
++#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L
++#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L
++#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x07000000L
++#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L
++//DP_AUX1_AUX_DPHY_RX_CONTROL1
++#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0
++#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL
++//DP_AUX1_AUX_DPHY_TX_STATUS
++#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0
++#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4
++#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10
++#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L
++#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L
++#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L
++//DP_AUX1_AUX_DPHY_RX_STATUS
++#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0
++#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8
++#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10
++#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15
++#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L
++#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L
++#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L
++#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L
++//DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL
++#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0
++#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8
++#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10
++#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14
++#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL
++#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L
++#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L
++#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L
++//DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L
++//DP_AUX1_AUX_GTC_SYNC_STATUS
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L
++
++
++// addressBlock: dce_dc_dp_aux2_dispdec
++//DP_AUX2_AUX_CONTROL
++#define DP_AUX2_AUX_CONTROL__AUX_EN__SHIFT 0x0
++#define DP_AUX2_AUX_CONTROL__AUX_RESET__SHIFT 0x4
++#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5
++#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8
++#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc
++#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10
++#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12
++#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14
++#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18
++#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c
++#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d
++#define DP_AUX2_AUX_CONTROL__SPARE_0__SHIFT 0x1e
++#define DP_AUX2_AUX_CONTROL__SPARE_1__SHIFT 0x1f
++#define DP_AUX2_AUX_CONTROL__AUX_EN_MASK 0x00000001L
++#define DP_AUX2_AUX_CONTROL__AUX_RESET_MASK 0x00000010L
++#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L
++#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L
++#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L
++#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L
++#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L
++#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L
++#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L
++#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L
++#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L
++#define DP_AUX2_AUX_CONTROL__SPARE_0_MASK 0x40000000L
++#define DP_AUX2_AUX_CONTROL__SPARE_1_MASK 0x80000000L
++//DP_AUX2_AUX_SW_CONTROL
++#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0
++#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2
++#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4
++#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10
++#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L
++#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L
++#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L
++#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L
++//DP_AUX2_AUX_ARB_CONTROL
++#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0
++#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2
++#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8
++#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa
++#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10
++#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10
++#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11
++#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18
++#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18
++#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19
++#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L
++#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL
++#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L
++#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L
++#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L
++#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L
++#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L
++#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L
++#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L
++#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L
++//DP_AUX2_AUX_INTERRUPT_CONTROL
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L
++//DP_AUX2_AUX_SW_STATUS
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18
++#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L
++#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xC0000000L
++//DP_AUX2_AUX_LS_STATUS
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L
++//DP_AUX2_AUX_SW_DATA
++#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0
++#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8
++#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10
++#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f
++#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L
++#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L
++#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L
++#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L
++//DP_AUX2_AUX_LS_DATA
++#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8
++#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10
++#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L
++#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L
++//DP_AUX2_AUX_DPHY_TX_REF_CONTROL
++#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0
++#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4
++#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10
++#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L
++#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L
++#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L
++//DP_AUX2_AUX_DPHY_TX_CONTROL
++#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0
++#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8
++#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10
++#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x00000007L
++#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L
++#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L
++//DP_AUX2_AUX_DPHY_RX_CONTROL0
++#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4
++#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8
++#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc
++#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10
++#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11
++#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12
++#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13
++#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14
++#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18
++#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c
++#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L
++#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L
++#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L
++#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L
++#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L
++#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L
++#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L
++#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L
++#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x07000000L
++#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L
++//DP_AUX2_AUX_DPHY_RX_CONTROL1
++#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0
++#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL
++//DP_AUX2_AUX_DPHY_TX_STATUS
++#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0
++#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4
++#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10
++#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L
++#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L
++#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L
++//DP_AUX2_AUX_DPHY_RX_STATUS
++#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0
++#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8
++#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10
++#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15
++#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L
++#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L
++#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L
++#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L
++//DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL
++#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0
++#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8
++#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10
++#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14
++#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL
++#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L
++#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L
++#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L
++//DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L
++//DP_AUX2_AUX_GTC_SYNC_STATUS
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L
++
++
++// addressBlock: dce_dc_dp_aux3_dispdec
++//DP_AUX3_AUX_CONTROL
++#define DP_AUX3_AUX_CONTROL__AUX_EN__SHIFT 0x0
++#define DP_AUX3_AUX_CONTROL__AUX_RESET__SHIFT 0x4
++#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5
++#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8
++#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc
++#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10
++#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12
++#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14
++#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18
++#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c
++#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d
++#define DP_AUX3_AUX_CONTROL__SPARE_0__SHIFT 0x1e
++#define DP_AUX3_AUX_CONTROL__SPARE_1__SHIFT 0x1f
++#define DP_AUX3_AUX_CONTROL__AUX_EN_MASK 0x00000001L
++#define DP_AUX3_AUX_CONTROL__AUX_RESET_MASK 0x00000010L
++#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L
++#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L
++#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L
++#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L
++#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L
++#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L
++#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L
++#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L
++#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L
++#define DP_AUX3_AUX_CONTROL__SPARE_0_MASK 0x40000000L
++#define DP_AUX3_AUX_CONTROL__SPARE_1_MASK 0x80000000L
++//DP_AUX3_AUX_SW_CONTROL
++#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0
++#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2
++#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4
++#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10
++#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L
++#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L
++#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L
++#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L
++//DP_AUX3_AUX_ARB_CONTROL
++#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0
++#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2
++#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8
++#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa
++#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10
++#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10
++#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11
++#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18
++#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18
++#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19
++#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L
++#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL
++#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L
++#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L
++#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L
++#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L
++#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L
++#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L
++#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L
++#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L
++//DP_AUX3_AUX_INTERRUPT_CONTROL
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L
++//DP_AUX3_AUX_SW_STATUS
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18
++#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L
++#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xC0000000L
++//DP_AUX3_AUX_LS_STATUS
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L
++//DP_AUX3_AUX_SW_DATA
++#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0
++#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8
++#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10
++#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f
++#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L
++#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L
++#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L
++#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L
++//DP_AUX3_AUX_LS_DATA
++#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8
++#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10
++#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L
++#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L
++//DP_AUX3_AUX_DPHY_TX_REF_CONTROL
++#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0
++#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4
++#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10
++#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L
++#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L
++#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L
++//DP_AUX3_AUX_DPHY_TX_CONTROL
++#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0
++#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8
++#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10
++#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x00000007L
++#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L
++#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L
++//DP_AUX3_AUX_DPHY_RX_CONTROL0
++#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4
++#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8
++#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc
++#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10
++#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11
++#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12
++#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13
++#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14
++#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18
++#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c
++#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L
++#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L
++#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L
++#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L
++#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L
++#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L
++#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L
++#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L
++#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x07000000L
++#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L
++//DP_AUX3_AUX_DPHY_RX_CONTROL1
++#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0
++#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL
++//DP_AUX3_AUX_DPHY_TX_STATUS
++#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0
++#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4
++#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10
++#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L
++#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L
++#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L
++//DP_AUX3_AUX_DPHY_RX_STATUS
++#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0
++#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8
++#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10
++#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15
++#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L
++#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L
++#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L
++#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L
++//DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL
++#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0
++#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8
++#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10
++#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14
++#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL
++#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L
++#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L
++#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L
++//DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L
++//DP_AUX3_AUX_GTC_SYNC_STATUS
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L
++
++
++// addressBlock: dce_dc_dp_aux4_dispdec
++//DP_AUX4_AUX_CONTROL
++#define DP_AUX4_AUX_CONTROL__AUX_EN__SHIFT 0x0
++#define DP_AUX4_AUX_CONTROL__AUX_RESET__SHIFT 0x4
++#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5
++#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8
++#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc
++#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10
++#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12
++#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14
++#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18
++#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c
++#define DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d
++#define DP_AUX4_AUX_CONTROL__SPARE_0__SHIFT 0x1e
++#define DP_AUX4_AUX_CONTROL__SPARE_1__SHIFT 0x1f
++#define DP_AUX4_AUX_CONTROL__AUX_EN_MASK 0x00000001L
++#define DP_AUX4_AUX_CONTROL__AUX_RESET_MASK 0x00000010L
++#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L
++#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L
++#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L
++#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L
++#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L
++#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L
++#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L
++#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L
++#define DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L
++#define DP_AUX4_AUX_CONTROL__SPARE_0_MASK 0x40000000L
++#define DP_AUX4_AUX_CONTROL__SPARE_1_MASK 0x80000000L
++//DP_AUX4_AUX_SW_CONTROL
++#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0
++#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2
++#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4
++#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10
++#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L
++#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L
++#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L
++#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L
++//DP_AUX4_AUX_ARB_CONTROL
++#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0
++#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2
++#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8
++#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa
++#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10
++#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10
++#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11
++#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18
++#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18
++#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19
++#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L
++#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL
++#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L
++#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L
++#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L
++#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L
++#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L
++#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L
++#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L
++#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L
++//DP_AUX4_AUX_INTERRUPT_CONTROL
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L
++//DP_AUX4_AUX_SW_STATUS
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18
++#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L
++#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xC0000000L
++//DP_AUX4_AUX_LS_STATUS
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L
++//DP_AUX4_AUX_SW_DATA
++#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0
++#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8
++#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10
++#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f
++#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L
++#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L
++#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L
++#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L
++//DP_AUX4_AUX_LS_DATA
++#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8
++#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10
++#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L
++#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L
++//DP_AUX4_AUX_DPHY_TX_REF_CONTROL
++#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0
++#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4
++#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10
++#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L
++#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L
++#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L
++//DP_AUX4_AUX_DPHY_TX_CONTROL
++#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0
++#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8
++#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10
++#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x00000007L
++#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L
++#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L
++//DP_AUX4_AUX_DPHY_RX_CONTROL0
++#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4
++#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8
++#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc
++#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10
++#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11
++#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12
++#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13
++#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14
++#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18
++#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c
++#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L
++#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L
++#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L
++#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L
++#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L
++#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L
++#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L
++#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L
++#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x07000000L
++#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L
++//DP_AUX4_AUX_DPHY_RX_CONTROL1
++#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0
++#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL
++//DP_AUX4_AUX_DPHY_TX_STATUS
++#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0
++#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4
++#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10
++#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L
++#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L
++#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L
++//DP_AUX4_AUX_DPHY_RX_STATUS
++#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0
++#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8
++#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10
++#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15
++#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L
++#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L
++#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L
++#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L
++//DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL
++#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0
++#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8
++#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10
++#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14
++#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL
++#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L
++#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L
++#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L
++//DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L
++//DP_AUX4_AUX_GTC_SYNC_STATUS
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L
++
++
++// addressBlock: dce_dc_dp_aux5_dispdec
++//DP_AUX5_AUX_CONTROL
++#define DP_AUX5_AUX_CONTROL__AUX_EN__SHIFT 0x0
++#define DP_AUX5_AUX_CONTROL__AUX_RESET__SHIFT 0x4
++#define DP_AUX5_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5
++#define DP_AUX5_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8
++#define DP_AUX5_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc
++#define DP_AUX5_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10
++#define DP_AUX5_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12
++#define DP_AUX5_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14
++#define DP_AUX5_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18
++#define DP_AUX5_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c
++#define DP_AUX5_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d
++#define DP_AUX5_AUX_CONTROL__SPARE_0__SHIFT 0x1e
++#define DP_AUX5_AUX_CONTROL__SPARE_1__SHIFT 0x1f
++#define DP_AUX5_AUX_CONTROL__AUX_EN_MASK 0x00000001L
++#define DP_AUX5_AUX_CONTROL__AUX_RESET_MASK 0x00000010L
++#define DP_AUX5_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L
++#define DP_AUX5_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L
++#define DP_AUX5_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L
++#define DP_AUX5_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L
++#define DP_AUX5_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L
++#define DP_AUX5_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L
++#define DP_AUX5_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L
++#define DP_AUX5_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L
++#define DP_AUX5_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L
++#define DP_AUX5_AUX_CONTROL__SPARE_0_MASK 0x40000000L
++#define DP_AUX5_AUX_CONTROL__SPARE_1_MASK 0x80000000L
++//DP_AUX5_AUX_SW_CONTROL
++#define DP_AUX5_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0
++#define DP_AUX5_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2
++#define DP_AUX5_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4
++#define DP_AUX5_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10
++#define DP_AUX5_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L
++#define DP_AUX5_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L
++#define DP_AUX5_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L
++#define DP_AUX5_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L
++//DP_AUX5_AUX_ARB_CONTROL
++#define DP_AUX5_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0
++#define DP_AUX5_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2
++#define DP_AUX5_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8
++#define DP_AUX5_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa
++#define DP_AUX5_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10
++#define DP_AUX5_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10
++#define DP_AUX5_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11
++#define DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18
++#define DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18
++#define DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19
++#define DP_AUX5_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L
++#define DP_AUX5_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL
++#define DP_AUX5_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L
++#define DP_AUX5_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L
++#define DP_AUX5_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L
++#define DP_AUX5_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L
++#define DP_AUX5_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L
++#define DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L
++#define DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L
++#define DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L
++//DP_AUX5_AUX_INTERRUPT_CONTROL
++#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0
++#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1
++#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2
++#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4
++#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5
++#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6
++#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8
++#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9
++#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa
++#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc
++#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd
++#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe
++#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L
++#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L
++#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L
++#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L
++#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L
++#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L
++#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L
++#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L
++#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L
++#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L
++#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L
++#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L
++//DP_AUX5_AUX_SW_STATUS
++#define DP_AUX5_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0
++#define DP_AUX5_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1
++#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4
++#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7
++#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8
++#define DP_AUX5_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9
++#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa
++#define DP_AUX5_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb
++#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc
++#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe
++#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11
++#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12
++#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13
++#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14
++#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16
++#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17
++#define DP_AUX5_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18
++#define DP_AUX5_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e
++#define DP_AUX5_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L
++#define DP_AUX5_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L
++#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L
++#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L
++#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L
++#define DP_AUX5_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L
++#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L
++#define DP_AUX5_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L
++#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L
++#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L
++#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L
++#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L
++#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L
++#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L
++#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L
++#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L
++#define DP_AUX5_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L
++#define DP_AUX5_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xC0000000L
++//DP_AUX5_AUX_LS_STATUS
++#define DP_AUX5_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0
++#define DP_AUX5_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1
++#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4
++#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7
++#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8
++#define DP_AUX5_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9
++#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa
++#define DP_AUX5_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb
++#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc
++#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe
++#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11
++#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12
++#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13
++#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14
++#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16
++#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17
++#define DP_AUX5_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18
++#define DP_AUX5_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d
++#define DP_AUX5_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e
++#define DP_AUX5_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f
++#define DP_AUX5_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L
++#define DP_AUX5_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L
++#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L
++#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L
++#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L
++#define DP_AUX5_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L
++#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L
++#define DP_AUX5_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L
++#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L
++#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L
++#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L
++#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L
++#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L
++#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L
++#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L
++#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L
++#define DP_AUX5_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L
++#define DP_AUX5_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L
++#define DP_AUX5_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L
++#define DP_AUX5_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L
++//DP_AUX5_AUX_SW_DATA
++#define DP_AUX5_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0
++#define DP_AUX5_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8
++#define DP_AUX5_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10
++#define DP_AUX5_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f
++#define DP_AUX5_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L
++#define DP_AUX5_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L
++#define DP_AUX5_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L
++#define DP_AUX5_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L
++//DP_AUX5_AUX_LS_DATA
++#define DP_AUX5_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8
++#define DP_AUX5_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10
++#define DP_AUX5_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L
++#define DP_AUX5_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L
++//DP_AUX5_AUX_DPHY_TX_REF_CONTROL
++#define DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0
++#define DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4
++#define DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10
++#define DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L
++#define DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L
++#define DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L
++//DP_AUX5_AUX_DPHY_TX_CONTROL
++#define DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0
++#define DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8
++#define DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10
++#define DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x00000007L
++#define DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L
++#define DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L
++//DP_AUX5_AUX_DPHY_RX_CONTROL0
++#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4
++#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8
++#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc
++#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10
++#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11
++#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12
++#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13
++#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14
++#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18
++#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c
++#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L
++#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L
++#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L
++#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L
++#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L
++#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L
++#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L
++#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L
++#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x07000000L
++#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L
++//DP_AUX5_AUX_DPHY_RX_CONTROL1
++#define DP_AUX5_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0
++#define DP_AUX5_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL
++//DP_AUX5_AUX_DPHY_TX_STATUS
++#define DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0
++#define DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4
++#define DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10
++#define DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L
++#define DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L
++#define DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L
++//DP_AUX5_AUX_DPHY_RX_STATUS
++#define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0
++#define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8
++#define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10
++#define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15
++#define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L
++#define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L
++#define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L
++#define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L
++//DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL
++#define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0
++#define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8
++#define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10
++#define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14
++#define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL
++#define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L
++#define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L
++#define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L
++//DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS
++#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0
++#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4
++#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8
++#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9
++#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10
++#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14
++#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15
++#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16
++#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17
++#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18
++#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19
++#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c
++#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L
++#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L
++#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L
++#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L
++#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L
++#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L
++#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L
++#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L
++#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L
++#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L
++#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L
++#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L
++//DP_AUX5_AUX_GTC_SYNC_STATUS
++#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0
++#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1
++#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4
++#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7
++#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8
++#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9
++#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa
++#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb
++#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc
++#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe
++#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11
++#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12
++#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13
++#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14
++#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16
++#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17
++#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18
++#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d
++#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e
++#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L
++#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L
++#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L
++#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L
++#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L
++#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L
++#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L
++#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L
++#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L
++#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L
++#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L
++#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L
++#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L
++#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L
++#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L
++#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L
++#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L
++#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L
++#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L
++
++
++// addressBlock: dce_dc_dig0_dispdec
++//DIG0_DIG_FE_CNTL
++#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0
++#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4
++#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8
++#define DIG0_DIG_FE_CNTL__DIG_START__SHIFT 0xa
++#define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18
++#define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c
++#define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e
++#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L
++#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L
++#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L
++#define DIG0_DIG_FE_CNTL__DIG_START_MASK 0x00000400L
++#define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L
++#define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L
++#define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L
++//DIG0_DIG_OUTPUT_CRC_CNTL
++#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0
++#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4
++#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8
++#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L
++#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L
++#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L
++//DIG0_DIG_OUTPUT_CRC_RESULT
++#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0
++#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL
++//DIG0_DIG_CLOCK_PATTERN
++#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0
++#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL
++//DIG0_DIG_TEST_PATTERN
++#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0
++#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1
++#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4
++#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5
++#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6
++#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10
++#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L
++#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L
++#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L
++#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L
++#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L
++#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L
++//DIG0_DIG_RANDOM_PATTERN_SEED
++#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0
++#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18
++#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL
++#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L
++//DIG0_DIG_FIFO_STATUS
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L
++//DIG0_HDMI_CONTROL
++#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0
++#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1
++#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2
++#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3
++#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4
++#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8
++#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9
++#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18
++#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c
++#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L
++#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L
++#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L
++#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L
++#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L
++#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L
++#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L
++#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L
++#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L
++//DIG0_HDMI_STATUS
++#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0
++#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10
++#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14
++#define DIG0_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b
++#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L
++#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L
++#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L
++#define DIG0_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L
++//DIG0_HDMI_AUDIO_PACKET_CONTROL
++#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4
++#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10
++#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L
++#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L
++//DIG0_HDMI_ACR_PACKET_CONTROL
++#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0
++#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1
++#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4
++#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8
++#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc
++#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10
++#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f
++#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L
++#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L
++#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L
++#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L
++#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L
++#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L
++#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L
++//DIG0_HDMI_VBI_PACKET_CONTROL
++#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0
++#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4
++#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5
++#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8
++#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9
++#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10
++#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L
++#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L
++#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L
++#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L
++#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L
++#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L
++//DIG0_HDMI_INFOFRAME_CONTROL0
++#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x0
++#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x1
++#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4
++#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5
++#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8
++#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9
++#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x00000001L
++#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x00000002L
++#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L
++#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L
++#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L
++#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L
++//DIG0_HDMI_INFOFRAME_CONTROL1
++#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x0
++#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8
++#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10
++#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x0000003FL
++#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L
++#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L
++//DIG0_HDMI_GENERIC_PACKET_CONTROL0
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003F0000L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3F000000L
++//DIG0_AFMT_INTERRUPT_STATUS
++//DIG0_HDMI_GC
++#define DIG0_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0
++#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2
++#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4
++#define DIG0_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8
++#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc
++#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L
++#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L
++#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L
++#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L
++#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L
++//DIG0_AFMT_AUDIO_PACKET_CONTROL2
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L
++//DIG0_AFMT_ISRC1_0
++#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0
++#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6
++#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7
++#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L
++#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L
++#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L
++//DIG0_AFMT_ISRC1_1
++#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0
++#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8
++#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10
++#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18
++#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL
++#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L
++#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L
++#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L
++//DIG0_AFMT_ISRC1_2
++#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0
++#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8
++#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10
++#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18
++#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL
++#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L
++#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L
++#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L
++//DIG0_AFMT_ISRC1_3
++#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0
++#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8
++#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10
++#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18
++#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL
++#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L
++#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L
++#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L
++//DIG0_AFMT_ISRC1_4
++#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0
++#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8
++#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10
++#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18
++#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL
++#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L
++#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L
++#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L
++//DIG0_AFMT_ISRC2_0
++#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0
++#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8
++#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10
++#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18
++#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL
++#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L
++#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L
++#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L
++//DIG0_AFMT_ISRC2_1
++#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0
++#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8
++#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10
++#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18
++#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL
++#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L
++#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L
++#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L
++//DIG0_AFMT_ISRC2_2
++#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0
++#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8
++#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10
++#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18
++#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL
++#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L
++#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L
++#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L
++//DIG0_AFMT_ISRC2_3
++#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0
++#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8
++#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10
++#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18
++#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL
++#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L
++#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L
++#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L
++//DIG0_AFMT_AVI_INFO0
++#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x0
++#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x8
++#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0xa
++#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0xc
++#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0xd
++#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x10
++#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x14
++#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x16
++#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x18
++#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x1a
++#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x1c
++#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x1f
++#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0x000000FFL
++#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x00000300L
++#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0x00000C00L
++#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x00001000L
++#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x0000E000L
++#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0x000F0000L
++#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x00300000L
++#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0x00C00000L
++#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x03000000L
++#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0x0C000000L
++#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000L
++#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000L
++//DIG0_AFMT_AVI_INFO1
++#define DIG0_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x0
++#define DIG0_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x8
++#define DIG0_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0xc
++#define DIG0_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0xe
++#define DIG0_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x10
++#define DIG0_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x000000FFL
++#define DIG0_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0x00000F00L
++#define DIG0_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x00003000L
++#define DIG0_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0x0000C000L
++#define DIG0_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xFFFF0000L
++//DIG0_AFMT_AVI_INFO2
++#define DIG0_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x0
++#define DIG0_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x10
++#define DIG0_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0x0000FFFFL
++#define DIG0_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xFFFF0000L
++//DIG0_AFMT_AVI_INFO3
++#define DIG0_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x0
++#define DIG0_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x18
++#define DIG0_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0x0000FFFFL
++#define DIG0_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xFF000000L
++//DIG0_AFMT_MPEG_INFO0
++#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0
++#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8
++#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10
++#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18
++#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL
++#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L
++#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L
++#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L
++//DIG0_AFMT_MPEG_INFO1
++#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0
++#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8
++#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc
++#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL
++#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L
++#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L
++//DIG0_AFMT_GENERIC_HDR
++#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0
++#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8
++#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10
++#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18
++#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL
++#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L
++#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L
++#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L
++//DIG0_AFMT_GENERIC_0
++#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0
++#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8
++#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10
++#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18
++#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL
++#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L
++#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L
++#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L
++//DIG0_AFMT_GENERIC_1
++#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0
++#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8
++#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10
++#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18
++#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL
++#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L
++#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L
++#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L
++//DIG0_AFMT_GENERIC_2
++#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0
++#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8
++#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10
++#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18
++#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL
++#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L
++#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L
++#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L
++//DIG0_AFMT_GENERIC_3
++#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0
++#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8
++#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10
++#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18
++#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL
++#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L
++#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L
++#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L
++//DIG0_AFMT_GENERIC_4
++#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0
++#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8
++#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10
++#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18
++#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL
++#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L
++#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L
++#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L
++//DIG0_AFMT_GENERIC_5
++#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0
++#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8
++#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10
++#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18
++#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL
++#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L
++#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L
++#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L
++//DIG0_AFMT_GENERIC_6
++#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0
++#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8
++#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10
++#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18
++#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL
++#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L
++#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L
++#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L
++//DIG0_AFMT_GENERIC_7
++#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0
++#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8
++#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10
++#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18
++#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL
++#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L
++#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L
++#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L
++//DIG0_HDMI_GENERIC_PACKET_CONTROL1
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003F0000L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3F000000L
++//DIG0_HDMI_ACR_32_0
++#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc
++#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L
++//DIG0_HDMI_ACR_32_1
++#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0
++#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL
++//DIG0_HDMI_ACR_44_0
++#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc
++#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L
++//DIG0_HDMI_ACR_44_1
++#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0
++#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL
++//DIG0_HDMI_ACR_48_0
++#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc
++#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L
++//DIG0_HDMI_ACR_48_1
++#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0
++#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL
++//DIG0_HDMI_ACR_STATUS_0
++#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc
++#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L
++//DIG0_HDMI_ACR_STATUS_1
++#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0
++#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL
++//DIG0_AFMT_AUDIO_INFO0
++#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0
++#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8
++#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb
++#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10
++#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18
++#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL
++#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L
++#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L
++#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L
++#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L
++//DIG0_AFMT_AUDIO_INFO1
++#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0
++#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb
++#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf
++#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10
++#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL
++#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L
++#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L
++#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L
++//DIG0_AFMT_60958_0
++#define DIG0_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0
++#define DIG0_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1
++#define DIG0_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2
++#define DIG0_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3
++#define DIG0_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6
++#define DIG0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8
++#define DIG0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10
++#define DIG0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14
++#define DIG0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18
++#define DIG0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c
++#define DIG0_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
++#define DIG0_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
++#define DIG0_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L
++#define DIG0_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L
++#define DIG0_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L
++#define DIG0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L
++#define DIG0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L
++#define DIG0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L
++#define DIG0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L
++#define DIG0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L
++//DIG0_AFMT_60958_1
++#define DIG0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0
++#define DIG0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4
++#define DIG0_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10
++#define DIG0_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12
++#define DIG0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14
++#define DIG0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL
++#define DIG0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L
++#define DIG0_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L
++#define DIG0_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L
++#define DIG0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L
++//DIG0_AFMT_AUDIO_CRC_CONTROL
++#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0
++#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4
++#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8
++#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc
++#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10
++#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L
++#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L
++#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L
++#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L
++#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L
++//DIG0_AFMT_RAMP_CONTROL0
++#define DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0
++#define DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f
++#define DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL
++#define DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L
++//DIG0_AFMT_RAMP_CONTROL1
++#define DIG0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0
++#define DIG0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18
++#define DIG0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL
++#define DIG0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L
++//DIG0_AFMT_RAMP_CONTROL2
++#define DIG0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0
++#define DIG0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL
++//DIG0_AFMT_RAMP_CONTROL3
++#define DIG0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0
++#define DIG0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL
++//DIG0_AFMT_60958_2
++#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
++#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
++#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8
++#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc
++#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10
++#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14
++#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
++#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
++#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L
++#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L
++#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L
++#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L
++//DIG0_AFMT_AUDIO_CRC_RESULT
++#define DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0
++#define DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8
++#define DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L
++#define DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L
++//DIG0_AFMT_STATUS
++#define DIG0_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4
++#define DIG0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8
++#define DIG0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18
++#define DIG0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e
++#define DIG0_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L
++#define DIG0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L
++#define DIG0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L
++#define DIG0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L
++//DIG0_AFMT_AUDIO_PACKET_CONTROL
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L
++//DIG0_AFMT_VBI_PACKET_CONTROL
++#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x2
++#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x3
++#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1e
++#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x00000004L
++#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x00000008L
++#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xC0000000L
++//DIG0_AFMT_INFOFRAME_CONTROL0
++#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6
++#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7
++#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa
++#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L
++#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L
++#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L
++//DIG0_AFMT_AUDIO_SRC_CONTROL
++#define DIG0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0
++#define DIG0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L
++//DIG0_DIG_BE_CNTL
++#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0
++#define DIG0_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1
++#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8
++#define DIG0_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10
++#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c
++#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L
++#define DIG0_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L
++#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L
++#define DIG0_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L
++#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L
++//DIG0_DIG_BE_EN_CNTL
++#define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0
++#define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8
++#define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L
++#define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L
++//DIG0_TMDS_CNTL
++#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0
++#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L
++//DIG0_TMDS_CONTROL_CHAR
++#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0
++#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1
++#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2
++#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3
++#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L
++#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L
++#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L
++#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L
++//DIG0_TMDS_CONTROL0_FEEDBACK
++#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0
++#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8
++#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L
++#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L
++//DIG0_TMDS_STEREOSYNC_CTL_SEL
++#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0
++#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L
++//DIG0_TMDS_SYNC_CHAR_PATTERN_0_1
++#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0
++#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10
++#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL
++#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L
++//DIG0_TMDS_SYNC_CHAR_PATTERN_2_3
++#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0
++#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10
++#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL
++#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L
++//DIG0_TMDS_CTL_BITS
++#define DIG0_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0
++#define DIG0_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8
++#define DIG0_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10
++#define DIG0_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18
++#define DIG0_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L
++#define DIG0_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L
++#define DIG0_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L
++#define DIG0_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L
++//DIG0_TMDS_DCBALANCER_CONTROL
++#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0
++#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8
++#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10
++#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18
++#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L
++#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L
++#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L
++#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L
++//DIG0_TMDS_CTL0_1_GEN_CNTL
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L
++//DIG0_TMDS_CTL2_3_GEN_CNTL
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L
++//DIG0_DIG_VERSION
++#define DIG0_DIG_VERSION__DIG_TYPE__SHIFT 0x0
++#define DIG0_DIG_VERSION__DIG_TYPE_MASK 0x00000001L
++//DIG0_DIG_LANE_ENABLE
++#define DIG0_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0
++#define DIG0_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1
++#define DIG0_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2
++#define DIG0_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3
++#define DIG0_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8
++#define DIG0_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L
++#define DIG0_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L
++#define DIG0_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L
++#define DIG0_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L
++#define DIG0_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L
++//DIG0_AFMT_CNTL
++#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0
++#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8
++#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L
++#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L
++
++
++// addressBlock: dce_dc_dp0_dispdec
++//DP0_DP_LINK_CNTL
++#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4
++#define DP0_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8
++#define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11
++#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L
++#define DP0_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L
++#define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L
++//DP0_DP_PIXEL_FORMAT
++#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0
++#define DP0_DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x8
++#define DP0_DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x10
++#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18
++#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L
++#define DP0_DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x00000100L
++#define DP0_DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x00010000L
++#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L
++//DP0_DP_MSA_COLORIMETRY
++#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x0
++#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x8
++#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE__SHIFT 0x9
++#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE__SHIFT 0x11
++#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0x000000FFL
++#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x00000100L
++#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_MASK 0x00000200L
++#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE_MASK 0x00020000L
++//DP0_DP_CONFIG
++#define DP0_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0
++#define DP0_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L
++//DP0_DP_VID_STREAM_CNTL
++#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0
++#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8
++#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10
++#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14
++#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L
++#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L
++#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L
++#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L
++//DP0_DP_STEER_FIFO
++#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0
++#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4
++#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5
++#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6
++#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7
++#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8
++#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc
++#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L
++#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L
++#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L
++#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L
++#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L
++#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L
++#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L
++//DP0_DP_MSA_MISC
++#define DP0_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x3
++#define DP0_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8
++#define DP0_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10
++#define DP0_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18
++#define DP0_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x00000078L
++#define DP0_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L
++#define DP0_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L
++#define DP0_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L
++//DP0_DP_VID_TIMING
++#define DP0_DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x0
++#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4
++#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8
++#define DP0_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN__SHIFT 0x9
++#define DP0_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18
++#define DP0_DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x00000001L
++#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L
++#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L
++#define DP0_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN_MASK 0x00000200L
++#define DP0_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L
++//DP0_DP_VID_N
++#define DP0_DP_VID_N__DP_VID_N__SHIFT 0x0
++#define DP0_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL
++//DP0_DP_VID_M
++#define DP0_DP_VID_M__DP_VID_M__SHIFT 0x0
++#define DP0_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL
++//DP0_DP_LINK_FRAMING_CNTL
++#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0
++#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18
++#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c
++#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL
++#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L
++#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L
++//DP0_DP_HBR2_EYE_PATTERN
++#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0
++#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L
++//DP0_DP_VID_MSA_VBID
++#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0
++#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x10
++#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18
++#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL
++#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x00010000L
++#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L
++//DP0_DP_VID_INTERRUPT_CNTL
++#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0
++#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1
++#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2
++#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L
++#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L
++#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L
++//DP0_DP_DPHY_CNTL
++#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0
++#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1
++#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2
++#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3
++#define DP0_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10
++#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18
++#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L
++#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L
++#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L
++#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L
++#define DP0_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L
++#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L
++//DP0_DP_DPHY_TRAINING_PATTERN_SEL
++#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0
++#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L
++//DP0_DP_DPHY_SYM0
++#define DP0_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0
++#define DP0_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa
++#define DP0_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14
++#define DP0_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL
++#define DP0_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L
++#define DP0_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L
++//DP0_DP_DPHY_SYM1
++#define DP0_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0
++#define DP0_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa
++#define DP0_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14
++#define DP0_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL
++#define DP0_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L
++#define DP0_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L
++//DP0_DP_DPHY_SYM2
++#define DP0_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0
++#define DP0_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa
++#define DP0_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL
++#define DP0_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L
++//DP0_DP_DPHY_8B10B_CNTL
++#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8
++#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10
++#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18
++#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L
++#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L
++#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L
++//DP0_DP_DPHY_PRBS_CNTL
++#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0
++#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4
++#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8
++#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L
++#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L
++#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L
++//DP0_DP_DPHY_SCRAM_CNTL
++#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0
++#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4
++#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8
++#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18
++#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L
++#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L
++#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L
++#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L
++//DP0_DP_DPHY_CRC_EN
++#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0
++#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4
++#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8
++#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L
++#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L
++#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L
++//DP0_DP_DPHY_CRC_CNTL
++#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0
++#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4
++#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10
++#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L
++#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L
++#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L
++//DP0_DP_DPHY_CRC_RESULT
++#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0
++#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8
++#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10
++#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18
++#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL
++#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L
++#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L
++#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L
++//DP0_DP_DPHY_CRC_MST_CNTL
++#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0
++#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8
++#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL
++#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L
++//DP0_DP_DPHY_CRC_MST_STATUS
++#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0
++#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8
++#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10
++#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L
++#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L
++#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L
++//DP0_DP_DPHY_FAST_TRAINING
++#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0
++#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1
++#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2
++#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8
++#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14
++#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L
++#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L
++#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L
++#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L
++#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L
++//DP0_DP_DPHY_FAST_TRAINING_STATUS
++#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0
++#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4
++#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8
++#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc
++#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L
++#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L
++#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L
++#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L
++//DP0_DP_MSA_V_TIMING_OVERRIDE1
++#define DP0_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x0
++#define DP0_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x4
++#define DP0_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x00000001L
++#define DP0_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x0003FFF0L
++//DP0_DP_MSA_V_TIMING_OVERRIDE2
++#define DP0_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x0
++#define DP0_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x10
++#define DP0_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x00003FFFL
++#define DP0_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x3FFF0000L
++//DP0_DP_SEC_CNTL
++#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0
++#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4
++#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8
++#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc
++#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10
++#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14
++#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15
++#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16
++#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17
++#define DP0_DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x18
++#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c
++#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L
++#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L
++#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L
++#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L
++#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L
++#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L
++#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L
++#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L
++#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L
++#define DP0_DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x01000000L
++#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L
++//DP0_DP_SEC_CNTL1
++#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0
++#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4
++#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5
++#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6
++#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7
++#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10
++#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L
++#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L
++#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L
++#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L
++#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L
++#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L
++//DP0_DP_SEC_FRAMING1
++#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0
++#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10
++#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL
++#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
++//DP0_DP_SEC_FRAMING2
++#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0
++#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10
++#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL
++#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
++//DP0_DP_SEC_FRAMING3
++#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0
++#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10
++#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL
++#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L
++//DP0_DP_SEC_FRAMING4
++#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14
++#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18
++#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c
++#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d
++#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L
++#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L
++#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L
++#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L
++//DP0_DP_SEC_AUD_N
++#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0
++#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL
++//DP0_DP_SEC_AUD_N_READBACK
++#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0
++#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL
++//DP0_DP_SEC_AUD_M
++#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0
++#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL
++//DP0_DP_SEC_AUD_M_READBACK
++#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0
++#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL
++//DP0_DP_SEC_TIMESTAMP
++#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0
++#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L
++//DP0_DP_SEC_PACKET_CNTL
++#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1
++#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4
++#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8
++#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10
++#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL
++#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L
++#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L
++#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L
++//DP0_DP_MSE_RATE_CNTL
++#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0
++#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a
++#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL
++#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L
++//DP0_DP_MSE_RATE_UPDATE
++#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0
++#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L
++//DP0_DP_MSE_SAT0
++#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0
++#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8
++#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10
++#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18
++#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L
++#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L
++#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L
++#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L
++//DP0_DP_MSE_SAT1
++#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0
++#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8
++#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10
++#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18
++#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L
++#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L
++#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L
++#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L
++//DP0_DP_MSE_SAT2
++#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0
++#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8
++#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10
++#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18
++#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L
++#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L
++#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L
++#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L
++//DP0_DP_MSE_SAT_UPDATE
++#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0
++#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8
++#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L
++#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L
++//DP0_DP_MSE_LINK_TIMING
++#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0
++#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10
++#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL
++#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L
++//DP0_DP_MSE_MISC_CNTL
++#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0
++#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4
++#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8
++#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L
++#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L
++#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L
++//DP0_DP_DPHY_BS_SR_SWAP_CNTL
++#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0
++#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf
++#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10
++#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL
++#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L
++#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L
++//DP0_DP_DPHY_HBR2_PATTERN_CONTROL
++#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0
++#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L
++//DP0_DP_MSE_SAT0_STATUS
++#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0
++#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8
++#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10
++#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18
++#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L
++#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L
++#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L
++#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L
++//DP0_DP_MSE_SAT1_STATUS
++#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0
++#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8
++#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10
++#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18
++#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L
++#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L
++#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L
++#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L
++//DP0_DP_MSE_SAT2_STATUS
++#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0
++#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8
++#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10
++#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18
++#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L
++#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L
++#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L
++#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L
++
++
++// addressBlock: dce_dc_dig1_dispdec
++//DIG1_DIG_FE_CNTL
++#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0
++#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4
++#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8
++#define DIG1_DIG_FE_CNTL__DIG_START__SHIFT 0xa
++#define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18
++#define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c
++#define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e
++#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L
++#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L
++#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L
++#define DIG1_DIG_FE_CNTL__DIG_START_MASK 0x00000400L
++#define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L
++#define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L
++#define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L
++//DIG1_DIG_OUTPUT_CRC_CNTL
++#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0
++#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4
++#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8
++#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L
++#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L
++#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L
++//DIG1_DIG_OUTPUT_CRC_RESULT
++#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0
++#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL
++//DIG1_DIG_CLOCK_PATTERN
++#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0
++#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL
++//DIG1_DIG_TEST_PATTERN
++#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0
++#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1
++#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4
++#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5
++#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6
++#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10
++#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L
++#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L
++#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L
++#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L
++#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L
++#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L
++//DIG1_DIG_RANDOM_PATTERN_SEED
++#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0
++#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18
++#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL
++#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L
++//DIG1_DIG_FIFO_STATUS
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L
++//DIG1_HDMI_CONTROL
++#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0
++#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1
++#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2
++#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3
++#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4
++#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8
++#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9
++#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18
++#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c
++#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L
++#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L
++#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L
++#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L
++#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L
++#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L
++#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L
++#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L
++#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L
++//DIG1_HDMI_STATUS
++#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0
++#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10
++#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14
++#define DIG1_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b
++#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L
++#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L
++#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L
++#define DIG1_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L
++//DIG1_HDMI_AUDIO_PACKET_CONTROL
++#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4
++#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10
++#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L
++#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L
++//DIG1_HDMI_ACR_PACKET_CONTROL
++#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0
++#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1
++#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4
++#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8
++#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc
++#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10
++#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f
++#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L
++#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L
++#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L
++#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L
++#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L
++#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L
++#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L
++//DIG1_HDMI_VBI_PACKET_CONTROL
++#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0
++#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4
++#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5
++#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8
++#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9
++#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10
++#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L
++#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L
++#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L
++#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L
++#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L
++#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L
++//DIG1_HDMI_INFOFRAME_CONTROL0
++#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x0
++#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x1
++#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4
++#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5
++#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8
++#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9
++#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x00000001L
++#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x00000002L
++#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L
++#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L
++#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L
++#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L
++//DIG1_HDMI_INFOFRAME_CONTROL1
++#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x0
++#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8
++#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10
++#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x0000003FL
++#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L
++#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L
++//DIG1_HDMI_GENERIC_PACKET_CONTROL0
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003F0000L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3F000000L
++//DIG1_AFMT_INTERRUPT_STATUS
++//DIG1_HDMI_GC
++#define DIG1_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0
++#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2
++#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4
++#define DIG1_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8
++#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc
++#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L
++#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L
++#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L
++#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L
++#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L
++//DIG1_AFMT_AUDIO_PACKET_CONTROL2
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L
++//DIG1_AFMT_ISRC1_0
++#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0
++#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6
++#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7
++#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L
++#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L
++#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L
++//DIG1_AFMT_ISRC1_1
++#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0
++#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8
++#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10
++#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18
++#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL
++#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L
++#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L
++#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L
++//DIG1_AFMT_ISRC1_2
++#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0
++#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8
++#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10
++#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18
++#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL
++#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L
++#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L
++#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L
++//DIG1_AFMT_ISRC1_3
++#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0
++#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8
++#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10
++#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18
++#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL
++#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L
++#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L
++#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L
++//DIG1_AFMT_ISRC1_4
++#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0
++#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8
++#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10
++#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18
++#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL
++#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L
++#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L
++#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L
++//DIG1_AFMT_ISRC2_0
++#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0
++#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8
++#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10
++#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18
++#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL
++#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L
++#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L
++#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L
++//DIG1_AFMT_ISRC2_1
++#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0
++#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8
++#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10
++#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18
++#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL
++#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L
++#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L
++#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L
++//DIG1_AFMT_ISRC2_2
++#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0
++#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8
++#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10
++#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18
++#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL
++#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L
++#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L
++#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L
++//DIG1_AFMT_ISRC2_3
++#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0
++#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8
++#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10
++#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18
++#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL
++#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L
++#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L
++#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L
++//DIG1_AFMT_AVI_INFO0
++#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x0
++#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x8
++#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0xa
++#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0xc
++#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0xd
++#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x10
++#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x14
++#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x16
++#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x18
++#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x1a
++#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x1c
++#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x1f
++#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0x000000FFL
++#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x00000300L
++#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0x00000C00L
++#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x00001000L
++#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x0000E000L
++#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0x000F0000L
++#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x00300000L
++#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0x00C00000L
++#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x03000000L
++#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0x0C000000L
++#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000L
++#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000L
++//DIG1_AFMT_AVI_INFO1
++#define DIG1_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x0
++#define DIG1_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x8
++#define DIG1_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0xc
++#define DIG1_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0xe
++#define DIG1_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x10
++#define DIG1_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x000000FFL
++#define DIG1_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0x00000F00L
++#define DIG1_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x00003000L
++#define DIG1_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0x0000C000L
++#define DIG1_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xFFFF0000L
++//DIG1_AFMT_AVI_INFO2
++#define DIG1_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x0
++#define DIG1_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x10
++#define DIG1_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0x0000FFFFL
++#define DIG1_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xFFFF0000L
++//DIG1_AFMT_AVI_INFO3
++#define DIG1_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x0
++#define DIG1_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x18
++#define DIG1_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0x0000FFFFL
++#define DIG1_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xFF000000L
++//DIG1_AFMT_MPEG_INFO0
++#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0
++#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8
++#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10
++#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18
++#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL
++#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L
++#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L
++#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L
++//DIG1_AFMT_MPEG_INFO1
++#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0
++#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8
++#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc
++#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL
++#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L
++#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L
++//DIG1_AFMT_GENERIC_HDR
++#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0
++#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8
++#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10
++#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18
++#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL
++#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L
++#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L
++#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L
++//DIG1_AFMT_GENERIC_0
++#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0
++#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8
++#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10
++#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18
++#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL
++#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L
++#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L
++#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L
++//DIG1_AFMT_GENERIC_1
++#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0
++#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8
++#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10
++#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18
++#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL
++#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L
++#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L
++#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L
++//DIG1_AFMT_GENERIC_2
++#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0
++#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8
++#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10
++#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18
++#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL
++#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L
++#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L
++#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L
++//DIG1_AFMT_GENERIC_3
++#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0
++#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8
++#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10
++#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18
++#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL
++#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L
++#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L
++#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L
++//DIG1_AFMT_GENERIC_4
++#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0
++#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8
++#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10
++#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18
++#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL
++#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L
++#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L
++#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L
++//DIG1_AFMT_GENERIC_5
++#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0
++#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8
++#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10
++#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18
++#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL
++#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L
++#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L
++#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L
++//DIG1_AFMT_GENERIC_6
++#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0
++#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8
++#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10
++#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18
++#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL
++#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L
++#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L
++#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L
++//DIG1_AFMT_GENERIC_7
++#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0
++#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8
++#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10
++#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18
++#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL
++#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L
++#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L
++#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L
++//DIG1_HDMI_GENERIC_PACKET_CONTROL1
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003F0000L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3F000000L
++//DIG1_HDMI_ACR_32_0
++#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc
++#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L
++//DIG1_HDMI_ACR_32_1
++#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0
++#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL
++//DIG1_HDMI_ACR_44_0
++#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc
++#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L
++//DIG1_HDMI_ACR_44_1
++#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0
++#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL
++//DIG1_HDMI_ACR_48_0
++#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc
++#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L
++//DIG1_HDMI_ACR_48_1
++#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0
++#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL
++//DIG1_HDMI_ACR_STATUS_0
++#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc
++#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L
++//DIG1_HDMI_ACR_STATUS_1
++#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0
++#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL
++//DIG1_AFMT_AUDIO_INFO0
++#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0
++#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8
++#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb
++#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10
++#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18
++#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL
++#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L
++#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L
++#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L
++#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L
++//DIG1_AFMT_AUDIO_INFO1
++#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0
++#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb
++#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf
++#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10
++#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL
++#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L
++#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L
++#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L
++//DIG1_AFMT_60958_0
++#define DIG1_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0
++#define DIG1_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1
++#define DIG1_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2
++#define DIG1_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3
++#define DIG1_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6
++#define DIG1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8
++#define DIG1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10
++#define DIG1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14
++#define DIG1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18
++#define DIG1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c
++#define DIG1_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
++#define DIG1_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
++#define DIG1_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L
++#define DIG1_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L
++#define DIG1_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L
++#define DIG1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L
++#define DIG1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L
++#define DIG1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L
++#define DIG1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L
++#define DIG1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L
++//DIG1_AFMT_60958_1
++#define DIG1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0
++#define DIG1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4
++#define DIG1_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10
++#define DIG1_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12
++#define DIG1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14
++#define DIG1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL
++#define DIG1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L
++#define DIG1_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L
++#define DIG1_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L
++#define DIG1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L
++//DIG1_AFMT_AUDIO_CRC_CONTROL
++#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0
++#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4
++#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8
++#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc
++#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10
++#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L
++#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L
++#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L
++#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L
++#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L
++//DIG1_AFMT_RAMP_CONTROL0
++#define DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0
++#define DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f
++#define DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL
++#define DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L
++//DIG1_AFMT_RAMP_CONTROL1
++#define DIG1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0
++#define DIG1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18
++#define DIG1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL
++#define DIG1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L
++//DIG1_AFMT_RAMP_CONTROL2
++#define DIG1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0
++#define DIG1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL
++//DIG1_AFMT_RAMP_CONTROL3
++#define DIG1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0
++#define DIG1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL
++//DIG1_AFMT_60958_2
++#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
++#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
++#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8
++#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc
++#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10
++#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14
++#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
++#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
++#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L
++#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L
++#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L
++#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L
++//DIG1_AFMT_AUDIO_CRC_RESULT
++#define DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0
++#define DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8
++#define DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L
++#define DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L
++//DIG1_AFMT_STATUS
++#define DIG1_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4
++#define DIG1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8
++#define DIG1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18
++#define DIG1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e
++#define DIG1_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L
++#define DIG1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L
++#define DIG1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L
++#define DIG1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L
++//DIG1_AFMT_AUDIO_PACKET_CONTROL
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L
++//DIG1_AFMT_VBI_PACKET_CONTROL
++#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x2
++#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x3
++#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1e
++#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x00000004L
++#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x00000008L
++#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xC0000000L
++//DIG1_AFMT_INFOFRAME_CONTROL0
++#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6
++#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7
++#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa
++#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L
++#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L
++#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L
++//DIG1_AFMT_AUDIO_SRC_CONTROL
++#define DIG1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0
++#define DIG1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L
++//DIG1_DIG_BE_CNTL
++#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0
++#define DIG1_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1
++#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8
++#define DIG1_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10
++#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c
++#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L
++#define DIG1_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L
++#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L
++#define DIG1_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L
++#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L
++//DIG1_DIG_BE_EN_CNTL
++#define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0
++#define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8
++#define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L
++#define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L
++//DIG1_TMDS_CNTL
++#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0
++#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L
++//DIG1_TMDS_CONTROL_CHAR
++#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0
++#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1
++#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2
++#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3
++#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L
++#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L
++#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L
++#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L
++//DIG1_TMDS_CONTROL0_FEEDBACK
++#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0
++#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8
++#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L
++#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L
++//DIG1_TMDS_STEREOSYNC_CTL_SEL
++#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0
++#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L
++//DIG1_TMDS_SYNC_CHAR_PATTERN_0_1
++#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0
++#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10
++#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL
++#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L
++//DIG1_TMDS_SYNC_CHAR_PATTERN_2_3
++#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0
++#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10
++#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL
++#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L
++//DIG1_TMDS_CTL_BITS
++#define DIG1_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0
++#define DIG1_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8
++#define DIG1_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10
++#define DIG1_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18
++#define DIG1_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L
++#define DIG1_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L
++#define DIG1_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L
++#define DIG1_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L
++//DIG1_TMDS_DCBALANCER_CONTROL
++#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0
++#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8
++#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10
++#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18
++#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L
++#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L
++#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L
++#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L
++//DIG1_TMDS_CTL0_1_GEN_CNTL
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L
++//DIG1_TMDS_CTL2_3_GEN_CNTL
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L
++//DIG1_DIG_VERSION
++#define DIG1_DIG_VERSION__DIG_TYPE__SHIFT 0x0
++#define DIG1_DIG_VERSION__DIG_TYPE_MASK 0x00000001L
++//DIG1_DIG_LANE_ENABLE
++#define DIG1_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0
++#define DIG1_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1
++#define DIG1_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2
++#define DIG1_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3
++#define DIG1_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8
++#define DIG1_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L
++#define DIG1_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L
++#define DIG1_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L
++#define DIG1_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L
++#define DIG1_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L
++//DIG1_AFMT_CNTL
++#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0
++#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8
++#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L
++#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L
++
++
++// addressBlock: dce_dc_dp1_dispdec
++//DP1_DP_LINK_CNTL
++#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4
++#define DP1_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8
++#define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11
++#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L
++#define DP1_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L
++#define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L
++//DP1_DP_PIXEL_FORMAT
++#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0
++#define DP1_DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x8
++#define DP1_DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x10
++#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18
++#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L
++#define DP1_DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x00000100L
++#define DP1_DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x00010000L
++#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L
++//DP1_DP_MSA_COLORIMETRY
++#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x0
++#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x8
++#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE__SHIFT 0x9
++#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE__SHIFT 0x11
++#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0x000000FFL
++#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x00000100L
++#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_MASK 0x00000200L
++#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE_MASK 0x00020000L
++//DP1_DP_CONFIG
++#define DP1_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0
++#define DP1_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L
++//DP1_DP_VID_STREAM_CNTL
++#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0
++#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8
++#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10
++#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14
++#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L
++#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L
++#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L
++#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L
++//DP1_DP_STEER_FIFO
++#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0
++#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4
++#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5
++#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6
++#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7
++#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8
++#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc
++#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L
++#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L
++#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L
++#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L
++#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L
++#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L
++#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L
++//DP1_DP_MSA_MISC
++#define DP1_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x3
++#define DP1_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8
++#define DP1_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10
++#define DP1_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18
++#define DP1_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x00000078L
++#define DP1_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L
++#define DP1_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L
++#define DP1_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L
++//DP1_DP_VID_TIMING
++#define DP1_DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x0
++#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4
++#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8
++#define DP1_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN__SHIFT 0x9
++#define DP1_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18
++#define DP1_DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x00000001L
++#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L
++#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L
++#define DP1_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN_MASK 0x00000200L
++#define DP1_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L
++//DP1_DP_VID_N
++#define DP1_DP_VID_N__DP_VID_N__SHIFT 0x0
++#define DP1_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL
++//DP1_DP_VID_M
++#define DP1_DP_VID_M__DP_VID_M__SHIFT 0x0
++#define DP1_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL
++//DP1_DP_LINK_FRAMING_CNTL
++#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0
++#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18
++#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c
++#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL
++#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L
++#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L
++//DP1_DP_HBR2_EYE_PATTERN
++#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0
++#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L
++//DP1_DP_VID_MSA_VBID
++#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0
++#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x10
++#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18
++#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL
++#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x00010000L
++#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L
++//DP1_DP_VID_INTERRUPT_CNTL
++#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0
++#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1
++#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2
++#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L
++#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L
++#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L
++//DP1_DP_DPHY_CNTL
++#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0
++#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1
++#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2
++#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3
++#define DP1_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10
++#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18
++#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L
++#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L
++#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L
++#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L
++#define DP1_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L
++#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L
++//DP1_DP_DPHY_TRAINING_PATTERN_SEL
++#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0
++#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L
++//DP1_DP_DPHY_SYM0
++#define DP1_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0
++#define DP1_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa
++#define DP1_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14
++#define DP1_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL
++#define DP1_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L
++#define DP1_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L
++//DP1_DP_DPHY_SYM1
++#define DP1_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0
++#define DP1_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa
++#define DP1_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14
++#define DP1_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL
++#define DP1_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L
++#define DP1_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L
++//DP1_DP_DPHY_SYM2
++#define DP1_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0
++#define DP1_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa
++#define DP1_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL
++#define DP1_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L
++//DP1_DP_DPHY_8B10B_CNTL
++#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8
++#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10
++#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18
++#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L
++#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L
++#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L
++//DP1_DP_DPHY_PRBS_CNTL
++#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0
++#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4
++#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8
++#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L
++#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L
++#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L
++//DP1_DP_DPHY_SCRAM_CNTL
++#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0
++#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4
++#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8
++#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18
++#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L
++#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L
++#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L
++#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L
++//DP1_DP_DPHY_CRC_EN
++#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0
++#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4
++#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8
++#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L
++#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L
++#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L
++//DP1_DP_DPHY_CRC_CNTL
++#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0
++#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4
++#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10
++#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L
++#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L
++#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L
++//DP1_DP_DPHY_CRC_RESULT
++#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0
++#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8
++#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10
++#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18
++#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL
++#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L
++#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L
++#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L
++//DP1_DP_DPHY_CRC_MST_CNTL
++#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0
++#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8
++#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL
++#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L
++//DP1_DP_DPHY_CRC_MST_STATUS
++#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0
++#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8
++#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10
++#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L
++#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L
++#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L
++//DP1_DP_DPHY_FAST_TRAINING
++#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0
++#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1
++#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2
++#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8
++#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14
++#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L
++#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L
++#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L
++#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L
++#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L
++//DP1_DP_DPHY_FAST_TRAINING_STATUS
++#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0
++#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4
++#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8
++#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc
++#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L
++#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L
++#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L
++#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L
++//DP1_DP_MSA_V_TIMING_OVERRIDE1
++#define DP1_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x0
++#define DP1_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x4
++#define DP1_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x00000001L
++#define DP1_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x0003FFF0L
++//DP1_DP_MSA_V_TIMING_OVERRIDE2
++#define DP1_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x0
++#define DP1_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x10
++#define DP1_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x00003FFFL
++#define DP1_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x3FFF0000L
++//DP1_DP_SEC_CNTL
++#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0
++#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4
++#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8
++#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc
++#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10
++#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14
++#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15
++#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16
++#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17
++#define DP1_DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x18
++#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c
++#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L
++#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L
++#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L
++#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L
++#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L
++#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L
++#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L
++#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L
++#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L
++#define DP1_DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x01000000L
++#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L
++//DP1_DP_SEC_CNTL1
++#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0
++#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4
++#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5
++#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6
++#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7
++#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10
++#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L
++#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L
++#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L
++#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L
++#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L
++#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L
++//DP1_DP_SEC_FRAMING1
++#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0
++#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10
++#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL
++#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
++//DP1_DP_SEC_FRAMING2
++#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0
++#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10
++#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL
++#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
++//DP1_DP_SEC_FRAMING3
++#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0
++#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10
++#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL
++#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L
++//DP1_DP_SEC_FRAMING4
++#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14
++#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18
++#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c
++#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d
++#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L
++#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L
++#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L
++#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L
++//DP1_DP_SEC_AUD_N
++#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0
++#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL
++//DP1_DP_SEC_AUD_N_READBACK
++#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0
++#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL
++//DP1_DP_SEC_AUD_M
++#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0
++#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL
++//DP1_DP_SEC_AUD_M_READBACK
++#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0
++#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL
++//DP1_DP_SEC_TIMESTAMP
++#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0
++#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L
++//DP1_DP_SEC_PACKET_CNTL
++#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1
++#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4
++#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8
++#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10
++#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL
++#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L
++#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L
++#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L
++//DP1_DP_MSE_RATE_CNTL
++#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0
++#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a
++#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL
++#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L
++//DP1_DP_MSE_RATE_UPDATE
++#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0
++#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L
++//DP1_DP_MSE_SAT0
++#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0
++#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8
++#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10
++#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18
++#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L
++#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L
++#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L
++#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L
++//DP1_DP_MSE_SAT1
++#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0
++#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8
++#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10
++#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18
++#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L
++#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L
++#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L
++#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L
++//DP1_DP_MSE_SAT2
++#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0
++#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8
++#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10
++#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18
++#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L
++#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L
++#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L
++#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L
++//DP1_DP_MSE_SAT_UPDATE
++#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0
++#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8
++#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L
++#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L
++//DP1_DP_MSE_LINK_TIMING
++#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0
++#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10
++#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL
++#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L
++//DP1_DP_MSE_MISC_CNTL
++#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0
++#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4
++#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8
++#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L
++#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L
++#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L
++//DP1_DP_DPHY_BS_SR_SWAP_CNTL
++#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0
++#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf
++#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10
++#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL
++#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L
++#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L
++//DP1_DP_DPHY_HBR2_PATTERN_CONTROL
++#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0
++#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L
++//DP1_DP_MSE_SAT0_STATUS
++#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0
++#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8
++#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10
++#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18
++#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L
++#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L
++#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L
++#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L
++//DP1_DP_MSE_SAT1_STATUS
++#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0
++#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8
++#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10
++#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18
++#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L
++#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L
++#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L
++#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L
++//DP1_DP_MSE_SAT2_STATUS
++#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0
++#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8
++#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10
++#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18
++#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L
++#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L
++#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L
++#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L
++
++
++// addressBlock: dce_dc_dig2_dispdec
++//DIG2_DIG_FE_CNTL
++#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0
++#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4
++#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8
++#define DIG2_DIG_FE_CNTL__DIG_START__SHIFT 0xa
++#define DIG2_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18
++#define DIG2_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c
++#define DIG2_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e
++#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L
++#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L
++#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L
++#define DIG2_DIG_FE_CNTL__DIG_START_MASK 0x00000400L
++#define DIG2_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L
++#define DIG2_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L
++#define DIG2_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L
++//DIG2_DIG_OUTPUT_CRC_CNTL
++#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0
++#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4
++#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8
++#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L
++#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L
++#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L
++//DIG2_DIG_OUTPUT_CRC_RESULT
++#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0
++#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL
++//DIG2_DIG_CLOCK_PATTERN
++#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0
++#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL
++//DIG2_DIG_TEST_PATTERN
++#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0
++#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1
++#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4
++#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5
++#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6
++#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10
++#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L
++#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L
++#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L
++#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L
++#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L
++#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L
++//DIG2_DIG_RANDOM_PATTERN_SEED
++#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0
++#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18
++#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL
++#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L
++//DIG2_DIG_FIFO_STATUS
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L
++//DIG2_HDMI_CONTROL
++#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0
++#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1
++#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2
++#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3
++#define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4
++#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8
++#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9
++#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18
++#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c
++#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L
++#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L
++#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L
++#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L
++#define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L
++#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L
++#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L
++#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L
++#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L
++//DIG2_HDMI_STATUS
++#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0
++#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10
++#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14
++#define DIG2_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b
++#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L
++#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L
++#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L
++#define DIG2_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L
++//DIG2_HDMI_AUDIO_PACKET_CONTROL
++#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4
++#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10
++#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L
++#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L
++//DIG2_HDMI_ACR_PACKET_CONTROL
++#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0
++#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1
++#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4
++#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8
++#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc
++#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10
++#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f
++#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L
++#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L
++#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L
++#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L
++#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L
++#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L
++#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L
++//DIG2_HDMI_VBI_PACKET_CONTROL
++#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0
++#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4
++#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5
++#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8
++#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9
++#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10
++#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L
++#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L
++#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L
++#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L
++#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L
++#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L
++//DIG2_HDMI_INFOFRAME_CONTROL0
++#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x0
++#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x1
++#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4
++#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5
++#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8
++#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9
++#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x00000001L
++#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x00000002L
++#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L
++#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L
++#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L
++#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L
++//DIG2_HDMI_INFOFRAME_CONTROL1
++#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x0
++#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8
++#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10
++#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x0000003FL
++#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L
++#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L
++//DIG2_HDMI_GENERIC_PACKET_CONTROL0
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003F0000L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3F000000L
++//DIG2_AFMT_INTERRUPT_STATUS
++//DIG2_HDMI_GC
++#define DIG2_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0
++#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2
++#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4
++#define DIG2_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8
++#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc
++#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L
++#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L
++#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L
++#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L
++#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L
++//DIG2_AFMT_AUDIO_PACKET_CONTROL2
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L
++//DIG2_AFMT_ISRC1_0
++#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0
++#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6
++#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7
++#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L
++#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L
++#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L
++//DIG2_AFMT_ISRC1_1
++#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0
++#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8
++#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10
++#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18
++#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL
++#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L
++#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L
++#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L
++//DIG2_AFMT_ISRC1_2
++#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0
++#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8
++#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10
++#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18
++#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL
++#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L
++#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L
++#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L
++//DIG2_AFMT_ISRC1_3
++#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0
++#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8
++#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10
++#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18
++#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL
++#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L
++#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L
++#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L
++//DIG2_AFMT_ISRC1_4
++#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0
++#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8
++#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10
++#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18
++#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL
++#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L
++#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L
++#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L
++//DIG2_AFMT_ISRC2_0
++#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0
++#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8
++#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10
++#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18
++#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL
++#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L
++#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L
++#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L
++//DIG2_AFMT_ISRC2_1
++#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0
++#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8
++#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10
++#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18
++#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL
++#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L
++#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L
++#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L
++//DIG2_AFMT_ISRC2_2
++#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0
++#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8
++#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10
++#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18
++#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL
++#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L
++#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L
++#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L
++//DIG2_AFMT_ISRC2_3
++#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0
++#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8
++#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10
++#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18
++#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL
++#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L
++#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L
++#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L
++//DIG2_AFMT_AVI_INFO0
++#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x0
++#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x8
++#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0xa
++#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0xc
++#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0xd
++#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x10
++#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x14
++#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x16
++#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x18
++#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x1a
++#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x1c
++#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x1f
++#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0x000000FFL
++#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x00000300L
++#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0x00000C00L
++#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x00001000L
++#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x0000E000L
++#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0x000F0000L
++#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x00300000L
++#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0x00C00000L
++#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x03000000L
++#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0x0C000000L
++#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000L
++#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000L
++//DIG2_AFMT_AVI_INFO1
++#define DIG2_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x0
++#define DIG2_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x8
++#define DIG2_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0xc
++#define DIG2_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0xe
++#define DIG2_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x10
++#define DIG2_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x000000FFL
++#define DIG2_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0x00000F00L
++#define DIG2_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x00003000L
++#define DIG2_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0x0000C000L
++#define DIG2_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xFFFF0000L
++//DIG2_AFMT_AVI_INFO2
++#define DIG2_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x0
++#define DIG2_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x10
++#define DIG2_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0x0000FFFFL
++#define DIG2_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xFFFF0000L
++//DIG2_AFMT_AVI_INFO3
++#define DIG2_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x0
++#define DIG2_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x18
++#define DIG2_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0x0000FFFFL
++#define DIG2_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xFF000000L
++//DIG2_AFMT_MPEG_INFO0
++#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0
++#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8
++#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10
++#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18
++#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL
++#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L
++#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L
++#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L
++//DIG2_AFMT_MPEG_INFO1
++#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0
++#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8
++#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc
++#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL
++#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L
++#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L
++//DIG2_AFMT_GENERIC_HDR
++#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0
++#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8
++#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10
++#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18
++#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL
++#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L
++#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L
++#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L
++//DIG2_AFMT_GENERIC_0
++#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0
++#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8
++#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10
++#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18
++#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL
++#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L
++#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L
++#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L
++//DIG2_AFMT_GENERIC_1
++#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0
++#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8
++#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10
++#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18
++#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL
++#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L
++#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L
++#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L
++//DIG2_AFMT_GENERIC_2
++#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0
++#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8
++#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10
++#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18
++#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL
++#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L
++#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L
++#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L
++//DIG2_AFMT_GENERIC_3
++#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0
++#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8
++#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10
++#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18
++#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL
++#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L
++#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L
++#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L
++//DIG2_AFMT_GENERIC_4
++#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0
++#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8
++#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10
++#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18
++#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL
++#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L
++#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L
++#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L
++//DIG2_AFMT_GENERIC_5
++#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0
++#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8
++#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10
++#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18
++#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL
++#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L
++#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L
++#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L
++//DIG2_AFMT_GENERIC_6
++#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0
++#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8
++#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10
++#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18
++#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL
++#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L
++#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L
++#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L
++//DIG2_AFMT_GENERIC_7
++#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0
++#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8
++#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10
++#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18
++#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL
++#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L
++#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L
++#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L
++//DIG2_HDMI_GENERIC_PACKET_CONTROL1
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003F0000L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3F000000L
++//DIG2_HDMI_ACR_32_0
++#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc
++#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L
++//DIG2_HDMI_ACR_32_1
++#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0
++#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL
++//DIG2_HDMI_ACR_44_0
++#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc
++#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L
++//DIG2_HDMI_ACR_44_1
++#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0
++#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL
++//DIG2_HDMI_ACR_48_0
++#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc
++#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L
++//DIG2_HDMI_ACR_48_1
++#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0
++#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL
++//DIG2_HDMI_ACR_STATUS_0
++#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc
++#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L
++//DIG2_HDMI_ACR_STATUS_1
++#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0
++#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL
++//DIG2_AFMT_AUDIO_INFO0
++#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0
++#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8
++#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb
++#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10
++#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18
++#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL
++#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L
++#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L
++#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L
++#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L
++//DIG2_AFMT_AUDIO_INFO1
++#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0
++#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb
++#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf
++#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10
++#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL
++#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L
++#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L
++#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L
++//DIG2_AFMT_60958_0
++#define DIG2_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0
++#define DIG2_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1
++#define DIG2_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2
++#define DIG2_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3
++#define DIG2_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6
++#define DIG2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8
++#define DIG2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10
++#define DIG2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14
++#define DIG2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18
++#define DIG2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c
++#define DIG2_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
++#define DIG2_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
++#define DIG2_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L
++#define DIG2_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L
++#define DIG2_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L
++#define DIG2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L
++#define DIG2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L
++#define DIG2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L
++#define DIG2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L
++#define DIG2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L
++//DIG2_AFMT_60958_1
++#define DIG2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0
++#define DIG2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4
++#define DIG2_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10
++#define DIG2_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12
++#define DIG2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14
++#define DIG2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL
++#define DIG2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L
++#define DIG2_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L
++#define DIG2_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L
++#define DIG2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L
++//DIG2_AFMT_AUDIO_CRC_CONTROL
++#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0
++#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4
++#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8
++#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc
++#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10
++#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L
++#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L
++#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L
++#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L
++#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L
++//DIG2_AFMT_RAMP_CONTROL0
++#define DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0
++#define DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f
++#define DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL
++#define DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L
++//DIG2_AFMT_RAMP_CONTROL1
++#define DIG2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0
++#define DIG2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18
++#define DIG2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL
++#define DIG2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L
++//DIG2_AFMT_RAMP_CONTROL2
++#define DIG2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0
++#define DIG2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL
++//DIG2_AFMT_RAMP_CONTROL3
++#define DIG2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0
++#define DIG2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL
++//DIG2_AFMT_60958_2
++#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
++#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
++#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8
++#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc
++#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10
++#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14
++#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
++#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
++#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L
++#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L
++#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L
++#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L
++//DIG2_AFMT_AUDIO_CRC_RESULT
++#define DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0
++#define DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8
++#define DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L
++#define DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L
++//DIG2_AFMT_STATUS
++#define DIG2_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4
++#define DIG2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8
++#define DIG2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18
++#define DIG2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e
++#define DIG2_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L
++#define DIG2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L
++#define DIG2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L
++#define DIG2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L
++//DIG2_AFMT_AUDIO_PACKET_CONTROL
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L
++//DIG2_AFMT_VBI_PACKET_CONTROL
++#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x2
++#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x3
++#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1e
++#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x00000004L
++#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x00000008L
++#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xC0000000L
++//DIG2_AFMT_INFOFRAME_CONTROL0
++#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6
++#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7
++#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa
++#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L
++#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L
++#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L
++//DIG2_AFMT_AUDIO_SRC_CONTROL
++#define DIG2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0
++#define DIG2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L
++//DIG2_DIG_BE_CNTL
++#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0
++#define DIG2_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1
++#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8
++#define DIG2_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10
++#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c
++#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L
++#define DIG2_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L
++#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L
++#define DIG2_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L
++#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L
++//DIG2_DIG_BE_EN_CNTL
++#define DIG2_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0
++#define DIG2_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8
++#define DIG2_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L
++#define DIG2_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L
++//DIG2_TMDS_CNTL
++#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0
++#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L
++//DIG2_TMDS_CONTROL_CHAR
++#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0
++#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1
++#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2
++#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3
++#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L
++#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L
++#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L
++#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L
++//DIG2_TMDS_CONTROL0_FEEDBACK
++#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0
++#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8
++#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L
++#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L
++//DIG2_TMDS_STEREOSYNC_CTL_SEL
++#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0
++#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L
++//DIG2_TMDS_SYNC_CHAR_PATTERN_0_1
++#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0
++#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10
++#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL
++#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L
++//DIG2_TMDS_SYNC_CHAR_PATTERN_2_3
++#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0
++#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10
++#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL
++#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L
++//DIG2_TMDS_CTL_BITS
++#define DIG2_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0
++#define DIG2_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8
++#define DIG2_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10
++#define DIG2_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18
++#define DIG2_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L
++#define DIG2_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L
++#define DIG2_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L
++#define DIG2_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L
++//DIG2_TMDS_DCBALANCER_CONTROL
++#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0
++#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8
++#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10
++#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18
++#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L
++#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L
++#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L
++#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L
++//DIG2_TMDS_CTL0_1_GEN_CNTL
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L
++//DIG2_TMDS_CTL2_3_GEN_CNTL
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L
++//DIG2_DIG_VERSION
++#define DIG2_DIG_VERSION__DIG_TYPE__SHIFT 0x0
++#define DIG2_DIG_VERSION__DIG_TYPE_MASK 0x00000001L
++//DIG2_DIG_LANE_ENABLE
++#define DIG2_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0
++#define DIG2_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1
++#define DIG2_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2
++#define DIG2_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3
++#define DIG2_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8
++#define DIG2_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L
++#define DIG2_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L
++#define DIG2_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L
++#define DIG2_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L
++#define DIG2_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L
++//DIG2_AFMT_CNTL
++#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0
++#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8
++#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L
++#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L
++
++
++// addressBlock: dce_dc_dp2_dispdec
++//DP2_DP_LINK_CNTL
++#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4
++#define DP2_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8
++#define DP2_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11
++#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L
++#define DP2_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L
++#define DP2_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L
++//DP2_DP_PIXEL_FORMAT
++#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0
++#define DP2_DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x8
++#define DP2_DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x10
++#define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18
++#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L
++#define DP2_DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x00000100L
++#define DP2_DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x00010000L
++#define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L
++//DP2_DP_MSA_COLORIMETRY
++#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x0
++#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x8
++#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE__SHIFT 0x9
++#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE__SHIFT 0x11
++#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0x000000FFL
++#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x00000100L
++#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_MASK 0x00000200L
++#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE_MASK 0x00020000L
++//DP2_DP_CONFIG
++#define DP2_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0
++#define DP2_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L
++//DP2_DP_VID_STREAM_CNTL
++#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0
++#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8
++#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10
++#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14
++#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L
++#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L
++#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L
++#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L
++//DP2_DP_STEER_FIFO
++#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0
++#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4
++#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5
++#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6
++#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7
++#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8
++#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc
++#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L
++#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L
++#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L
++#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L
++#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L
++#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L
++#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L
++//DP2_DP_MSA_MISC
++#define DP2_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x3
++#define DP2_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8
++#define DP2_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10
++#define DP2_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18
++#define DP2_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x00000078L
++#define DP2_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L
++#define DP2_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L
++#define DP2_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L
++//DP2_DP_VID_TIMING
++#define DP2_DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x0
++#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4
++#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8
++#define DP2_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN__SHIFT 0x9
++#define DP2_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18
++#define DP2_DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x00000001L
++#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L
++#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L
++#define DP2_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN_MASK 0x00000200L
++#define DP2_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L
++//DP2_DP_VID_N
++#define DP2_DP_VID_N__DP_VID_N__SHIFT 0x0
++#define DP2_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL
++//DP2_DP_VID_M
++#define DP2_DP_VID_M__DP_VID_M__SHIFT 0x0
++#define DP2_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL
++//DP2_DP_LINK_FRAMING_CNTL
++#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0
++#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18
++#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c
++#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL
++#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L
++#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L
++//DP2_DP_HBR2_EYE_PATTERN
++#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0
++#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L
++//DP2_DP_VID_MSA_VBID
++#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0
++#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x10
++#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18
++#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL
++#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x00010000L
++#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L
++//DP2_DP_VID_INTERRUPT_CNTL
++#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0
++#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1
++#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2
++#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L
++#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L
++#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L
++//DP2_DP_DPHY_CNTL
++#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0
++#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1
++#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2
++#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3
++#define DP2_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10
++#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18
++#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L
++#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L
++#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L
++#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L
++#define DP2_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L
++#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L
++//DP2_DP_DPHY_TRAINING_PATTERN_SEL
++#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0
++#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L
++//DP2_DP_DPHY_SYM0
++#define DP2_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0
++#define DP2_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa
++#define DP2_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14
++#define DP2_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL
++#define DP2_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L
++#define DP2_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L
++//DP2_DP_DPHY_SYM1
++#define DP2_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0
++#define DP2_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa
++#define DP2_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14
++#define DP2_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL
++#define DP2_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L
++#define DP2_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L
++//DP2_DP_DPHY_SYM2
++#define DP2_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0
++#define DP2_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa
++#define DP2_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL
++#define DP2_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L
++//DP2_DP_DPHY_8B10B_CNTL
++#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8
++#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10
++#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18
++#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L
++#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L
++#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L
++//DP2_DP_DPHY_PRBS_CNTL
++#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0
++#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4
++#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8
++#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L
++#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L
++#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L
++//DP2_DP_DPHY_SCRAM_CNTL
++#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0
++#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4
++#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8
++#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18
++#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L
++#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L
++#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L
++#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L
++//DP2_DP_DPHY_CRC_EN
++#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0
++#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4
++#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8
++#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L
++#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L
++#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L
++//DP2_DP_DPHY_CRC_CNTL
++#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0
++#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4
++#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10
++#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L
++#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L
++#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L
++//DP2_DP_DPHY_CRC_RESULT
++#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0
++#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8
++#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10
++#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18
++#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL
++#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L
++#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L
++#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L
++//DP2_DP_DPHY_CRC_MST_CNTL
++#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0
++#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8
++#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL
++#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L
++//DP2_DP_DPHY_CRC_MST_STATUS
++#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0
++#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8
++#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10
++#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L
++#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L
++#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L
++//DP2_DP_DPHY_FAST_TRAINING
++#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0
++#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1
++#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2
++#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8
++#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14
++#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L
++#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L
++#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L
++#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L
++#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L
++//DP2_DP_DPHY_FAST_TRAINING_STATUS
++#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0
++#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4
++#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8
++#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc
++#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L
++#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L
++#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L
++#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L
++//DP2_DP_MSA_V_TIMING_OVERRIDE1
++#define DP2_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x0
++#define DP2_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x4
++#define DP2_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x00000001L
++#define DP2_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x0003FFF0L
++//DP2_DP_MSA_V_TIMING_OVERRIDE2
++#define DP2_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x0
++#define DP2_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x10
++#define DP2_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x00003FFFL
++#define DP2_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x3FFF0000L
++//DP2_DP_SEC_CNTL
++#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0
++#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4
++#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8
++#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc
++#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10
++#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14
++#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15
++#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16
++#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17
++#define DP2_DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x18
++#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c
++#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L
++#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L
++#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L
++#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L
++#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L
++#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L
++#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L
++#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L
++#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L
++#define DP2_DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x01000000L
++#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L
++//DP2_DP_SEC_CNTL1
++#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0
++#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4
++#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5
++#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6
++#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7
++#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10
++#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L
++#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L
++#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L
++#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L
++#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L
++#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L
++//DP2_DP_SEC_FRAMING1
++#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0
++#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10
++#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL
++#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
++//DP2_DP_SEC_FRAMING2
++#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0
++#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10
++#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL
++#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
++//DP2_DP_SEC_FRAMING3
++#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0
++#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10
++#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL
++#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L
++//DP2_DP_SEC_FRAMING4
++#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14
++#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18
++#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c
++#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d
++#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L
++#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L
++#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L
++#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L
++//DP2_DP_SEC_AUD_N
++#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0
++#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL
++//DP2_DP_SEC_AUD_N_READBACK
++#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0
++#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL
++//DP2_DP_SEC_AUD_M
++#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0
++#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL
++//DP2_DP_SEC_AUD_M_READBACK
++#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0
++#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL
++//DP2_DP_SEC_TIMESTAMP
++#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0
++#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L
++//DP2_DP_SEC_PACKET_CNTL
++#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1
++#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4
++#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8
++#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10
++#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL
++#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L
++#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L
++#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L
++//DP2_DP_MSE_RATE_CNTL
++#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0
++#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a
++#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL
++#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L
++//DP2_DP_MSE_RATE_UPDATE
++#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0
++#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L
++//DP2_DP_MSE_SAT0
++#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0
++#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8
++#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10
++#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18
++#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L
++#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L
++#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L
++#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L
++//DP2_DP_MSE_SAT1
++#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0
++#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8
++#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10
++#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18
++#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L
++#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L
++#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L
++#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L
++//DP2_DP_MSE_SAT2
++#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0
++#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8
++#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10
++#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18
++#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L
++#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L
++#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L
++#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L
++//DP2_DP_MSE_SAT_UPDATE
++#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0
++#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8
++#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L
++#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L
++//DP2_DP_MSE_LINK_TIMING
++#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0
++#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10
++#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL
++#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L
++//DP2_DP_MSE_MISC_CNTL
++#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0
++#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4
++#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8
++#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L
++#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L
++#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L
++//DP2_DP_DPHY_BS_SR_SWAP_CNTL
++#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0
++#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf
++#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10
++#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL
++#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L
++#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L
++//DP2_DP_DPHY_HBR2_PATTERN_CONTROL
++#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0
++#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L
++//DP2_DP_MSE_SAT0_STATUS
++#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0
++#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8
++#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10
++#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18
++#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L
++#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L
++#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L
++#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L
++//DP2_DP_MSE_SAT1_STATUS
++#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0
++#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8
++#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10
++#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18
++#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L
++#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L
++#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L
++#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L
++//DP2_DP_MSE_SAT2_STATUS
++#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0
++#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8
++#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10
++#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18
++#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L
++#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L
++#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L
++#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L
++
++
++// addressBlock: dce_dc_dig3_dispdec
++//DIG3_DIG_FE_CNTL
++#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0
++#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4
++#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8
++#define DIG3_DIG_FE_CNTL__DIG_START__SHIFT 0xa
++#define DIG3_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18
++#define DIG3_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c
++#define DIG3_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e
++#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L
++#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L
++#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L
++#define DIG3_DIG_FE_CNTL__DIG_START_MASK 0x00000400L
++#define DIG3_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L
++#define DIG3_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L
++#define DIG3_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L
++//DIG3_DIG_OUTPUT_CRC_CNTL
++#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0
++#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4
++#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8
++#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L
++#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L
++#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L
++//DIG3_DIG_OUTPUT_CRC_RESULT
++#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0
++#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL
++//DIG3_DIG_CLOCK_PATTERN
++#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0
++#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL
++//DIG3_DIG_TEST_PATTERN
++#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0
++#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1
++#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4
++#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5
++#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6
++#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10
++#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L
++#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L
++#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L
++#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L
++#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L
++#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L
++//DIG3_DIG_RANDOM_PATTERN_SEED
++#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0
++#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18
++#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL
++#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L
++//DIG3_DIG_FIFO_STATUS
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L
++//DIG3_HDMI_CONTROL
++#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0
++#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1
++#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2
++#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3
++#define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4
++#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8
++#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9
++#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18
++#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c
++#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L
++#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L
++#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L
++#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L
++#define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L
++#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L
++#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L
++#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L
++#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L
++//DIG3_HDMI_STATUS
++#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0
++#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10
++#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14
++#define DIG3_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b
++#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L
++#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L
++#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L
++#define DIG3_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L
++//DIG3_HDMI_AUDIO_PACKET_CONTROL
++#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4
++#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10
++#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L
++#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L
++//DIG3_HDMI_ACR_PACKET_CONTROL
++#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0
++#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1
++#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4
++#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8
++#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc
++#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10
++#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f
++#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L
++#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L
++#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L
++#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L
++#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L
++#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L
++#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L
++//DIG3_HDMI_VBI_PACKET_CONTROL
++#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0
++#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4
++#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5
++#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8
++#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9
++#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10
++#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L
++#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L
++#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L
++#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L
++#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L
++#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L
++//DIG3_HDMI_INFOFRAME_CONTROL0
++#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x0
++#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x1
++#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4
++#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5
++#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8
++#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9
++#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x00000001L
++#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x00000002L
++#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L
++#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L
++#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L
++#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L
++//DIG3_HDMI_INFOFRAME_CONTROL1
++#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x0
++#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8
++#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10
++#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x0000003FL
++#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L
++#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L
++//DIG3_HDMI_GENERIC_PACKET_CONTROL0
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003F0000L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3F000000L
++//DIG3_AFMT_INTERRUPT_STATUS
++//DIG3_HDMI_GC
++#define DIG3_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0
++#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2
++#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4
++#define DIG3_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8
++#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc
++#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L
++#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L
++#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L
++#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L
++#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L
++//DIG3_AFMT_AUDIO_PACKET_CONTROL2
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L
++//DIG3_AFMT_ISRC1_0
++#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0
++#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6
++#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7
++#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L
++#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L
++#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L
++//DIG3_AFMT_ISRC1_1
++#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0
++#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8
++#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10
++#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18
++#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL
++#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L
++#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L
++#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L
++//DIG3_AFMT_ISRC1_2
++#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0
++#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8
++#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10
++#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18
++#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL
++#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L
++#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L
++#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L
++//DIG3_AFMT_ISRC1_3
++#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0
++#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8
++#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10
++#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18
++#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL
++#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L
++#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L
++#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L
++//DIG3_AFMT_ISRC1_4
++#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0
++#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8
++#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10
++#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18
++#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL
++#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L
++#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L
++#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L
++//DIG3_AFMT_ISRC2_0
++#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0
++#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8
++#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10
++#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18
++#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL
++#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L
++#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L
++#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L
++//DIG3_AFMT_ISRC2_1
++#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0
++#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8
++#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10
++#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18
++#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL
++#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L
++#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L
++#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L
++//DIG3_AFMT_ISRC2_2
++#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0
++#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8
++#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10
++#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18
++#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL
++#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L
++#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L
++#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L
++//DIG3_AFMT_ISRC2_3
++#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0
++#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8
++#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10
++#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18
++#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL
++#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L
++#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L
++#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L
++//DIG3_AFMT_AVI_INFO0
++#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x0
++#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x8
++#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0xa
++#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0xc
++#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0xd
++#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x10
++#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x14
++#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x16
++#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x18
++#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x1a
++#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x1c
++#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x1f
++#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0x000000FFL
++#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x00000300L
++#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0x00000C00L
++#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x00001000L
++#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x0000E000L
++#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0x000F0000L
++#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x00300000L
++#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0x00C00000L
++#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x03000000L
++#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0x0C000000L
++#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000L
++#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000L
++//DIG3_AFMT_AVI_INFO1
++#define DIG3_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x0
++#define DIG3_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x8
++#define DIG3_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0xc
++#define DIG3_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0xe
++#define DIG3_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x10
++#define DIG3_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x000000FFL
++#define DIG3_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0x00000F00L
++#define DIG3_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x00003000L
++#define DIG3_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0x0000C000L
++#define DIG3_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xFFFF0000L
++//DIG3_AFMT_AVI_INFO2
++#define DIG3_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x0
++#define DIG3_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x10
++#define DIG3_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0x0000FFFFL
++#define DIG3_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xFFFF0000L
++//DIG3_AFMT_AVI_INFO3
++#define DIG3_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x0
++#define DIG3_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x18
++#define DIG3_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0x0000FFFFL
++#define DIG3_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xFF000000L
++//DIG3_AFMT_MPEG_INFO0
++#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0
++#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8
++#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10
++#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18
++#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL
++#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L
++#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L
++#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L
++//DIG3_AFMT_MPEG_INFO1
++#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0
++#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8
++#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc
++#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL
++#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L
++#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L
++//DIG3_AFMT_GENERIC_HDR
++#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0
++#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8
++#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10
++#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18
++#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL
++#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L
++#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L
++#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L
++//DIG3_AFMT_GENERIC_0
++#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0
++#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8
++#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10
++#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18
++#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL
++#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L
++#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L
++#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L
++//DIG3_AFMT_GENERIC_1
++#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0
++#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8
++#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10
++#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18
++#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL
++#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L
++#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L
++#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L
++//DIG3_AFMT_GENERIC_2
++#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0
++#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8
++#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10
++#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18
++#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL
++#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L
++#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L
++#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L
++//DIG3_AFMT_GENERIC_3
++#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0
++#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8
++#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10
++#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18
++#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL
++#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L
++#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L
++#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L
++//DIG3_AFMT_GENERIC_4
++#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0
++#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8
++#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10
++#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18
++#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL
++#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L
++#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L
++#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L
++//DIG3_AFMT_GENERIC_5
++#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0
++#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8
++#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10
++#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18
++#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL
++#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L
++#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L
++#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L
++//DIG3_AFMT_GENERIC_6
++#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0
++#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8
++#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10
++#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18
++#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL
++#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L
++#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L
++#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L
++//DIG3_AFMT_GENERIC_7
++#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0
++#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8
++#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10
++#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18
++#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL
++#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L
++#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L
++#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L
++//DIG3_HDMI_GENERIC_PACKET_CONTROL1
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003F0000L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3F000000L
++//DIG3_HDMI_ACR_32_0
++#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc
++#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L
++//DIG3_HDMI_ACR_32_1
++#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0
++#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL
++//DIG3_HDMI_ACR_44_0
++#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc
++#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L
++//DIG3_HDMI_ACR_44_1
++#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0
++#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL
++//DIG3_HDMI_ACR_48_0
++#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc
++#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L
++//DIG3_HDMI_ACR_48_1
++#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0
++#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL
++//DIG3_HDMI_ACR_STATUS_0
++#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc
++#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L
++//DIG3_HDMI_ACR_STATUS_1
++#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0
++#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL
++//DIG3_AFMT_AUDIO_INFO0
++#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0
++#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8
++#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb
++#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10
++#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18
++#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL
++#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L
++#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L
++#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L
++#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L
++//DIG3_AFMT_AUDIO_INFO1
++#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0
++#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb
++#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf
++#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10
++#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL
++#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L
++#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L
++#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L
++//DIG3_AFMT_60958_0
++#define DIG3_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0
++#define DIG3_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1
++#define DIG3_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2
++#define DIG3_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3
++#define DIG3_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6
++#define DIG3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8
++#define DIG3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10
++#define DIG3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14
++#define DIG3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18
++#define DIG3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c
++#define DIG3_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
++#define DIG3_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
++#define DIG3_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L
++#define DIG3_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L
++#define DIG3_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L
++#define DIG3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L
++#define DIG3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L
++#define DIG3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L
++#define DIG3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L
++#define DIG3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L
++//DIG3_AFMT_60958_1
++#define DIG3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0
++#define DIG3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4
++#define DIG3_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10
++#define DIG3_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12
++#define DIG3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14
++#define DIG3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL
++#define DIG3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L
++#define DIG3_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L
++#define DIG3_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L
++#define DIG3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L
++//DIG3_AFMT_AUDIO_CRC_CONTROL
++#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0
++#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4
++#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8
++#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc
++#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10
++#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L
++#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L
++#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L
++#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L
++#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L
++//DIG3_AFMT_RAMP_CONTROL0
++#define DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0
++#define DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f
++#define DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL
++#define DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L
++//DIG3_AFMT_RAMP_CONTROL1
++#define DIG3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0
++#define DIG3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18
++#define DIG3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL
++#define DIG3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L
++//DIG3_AFMT_RAMP_CONTROL2
++#define DIG3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0
++#define DIG3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL
++//DIG3_AFMT_RAMP_CONTROL3
++#define DIG3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0
++#define DIG3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL
++//DIG3_AFMT_60958_2
++#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
++#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
++#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8
++#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc
++#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10
++#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14
++#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
++#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
++#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L
++#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L
++#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L
++#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L
++//DIG3_AFMT_AUDIO_CRC_RESULT
++#define DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0
++#define DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8
++#define DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L
++#define DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L
++//DIG3_AFMT_STATUS
++#define DIG3_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4
++#define DIG3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8
++#define DIG3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18
++#define DIG3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e
++#define DIG3_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L
++#define DIG3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L
++#define DIG3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L
++#define DIG3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L
++//DIG3_AFMT_AUDIO_PACKET_CONTROL
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L
++//DIG3_AFMT_VBI_PACKET_CONTROL
++#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x2
++#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x3
++#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1e
++#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x00000004L
++#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x00000008L
++#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xC0000000L
++//DIG3_AFMT_INFOFRAME_CONTROL0
++#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6
++#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7
++#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa
++#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L
++#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L
++#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L
++//DIG3_AFMT_AUDIO_SRC_CONTROL
++#define DIG3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0
++#define DIG3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L
++//DIG3_DIG_BE_CNTL
++#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0
++#define DIG3_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1
++#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8
++#define DIG3_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10
++#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c
++#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L
++#define DIG3_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L
++#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L
++#define DIG3_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L
++#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L
++//DIG3_DIG_BE_EN_CNTL
++#define DIG3_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0
++#define DIG3_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8
++#define DIG3_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L
++#define DIG3_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L
++//DIG3_TMDS_CNTL
++#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0
++#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L
++//DIG3_TMDS_CONTROL_CHAR
++#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0
++#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1
++#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2
++#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3
++#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L
++#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L
++#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L
++#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L
++//DIG3_TMDS_CONTROL0_FEEDBACK
++#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0
++#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8
++#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L
++#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L
++//DIG3_TMDS_STEREOSYNC_CTL_SEL
++#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0
++#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L
++//DIG3_TMDS_SYNC_CHAR_PATTERN_0_1
++#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0
++#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10
++#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL
++#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L
++//DIG3_TMDS_SYNC_CHAR_PATTERN_2_3
++#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0
++#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10
++#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL
++#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L
++//DIG3_TMDS_CTL_BITS
++#define DIG3_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0
++#define DIG3_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8
++#define DIG3_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10
++#define DIG3_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18
++#define DIG3_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L
++#define DIG3_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L
++#define DIG3_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L
++#define DIG3_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L
++//DIG3_TMDS_DCBALANCER_CONTROL
++#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0
++#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8
++#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10
++#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18
++#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L
++#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L
++#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L
++#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L
++//DIG3_TMDS_CTL0_1_GEN_CNTL
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L
++//DIG3_TMDS_CTL2_3_GEN_CNTL
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L
++//DIG3_DIG_VERSION
++#define DIG3_DIG_VERSION__DIG_TYPE__SHIFT 0x0
++#define DIG3_DIG_VERSION__DIG_TYPE_MASK 0x00000001L
++//DIG3_DIG_LANE_ENABLE
++#define DIG3_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0
++#define DIG3_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1
++#define DIG3_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2
++#define DIG3_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3
++#define DIG3_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8
++#define DIG3_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L
++#define DIG3_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L
++#define DIG3_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L
++#define DIG3_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L
++#define DIG3_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L
++//DIG3_AFMT_CNTL
++#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0
++#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8
++#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L
++#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L
++
++
++// addressBlock: dce_dc_dp3_dispdec
++//DP3_DP_LINK_CNTL
++#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4
++#define DP3_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8
++#define DP3_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11
++#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L
++#define DP3_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L
++#define DP3_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L
++//DP3_DP_PIXEL_FORMAT
++#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0
++#define DP3_DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x8
++#define DP3_DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x10
++#define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18
++#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L
++#define DP3_DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x00000100L
++#define DP3_DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x00010000L
++#define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L
++//DP3_DP_MSA_COLORIMETRY
++#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x0
++#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x8
++#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE__SHIFT 0x9
++#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE__SHIFT 0x11
++#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0x000000FFL
++#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x00000100L
++#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_MASK 0x00000200L
++#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE_MASK 0x00020000L
++//DP3_DP_CONFIG
++#define DP3_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0
++#define DP3_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L
++//DP3_DP_VID_STREAM_CNTL
++#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0
++#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8
++#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10
++#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14
++#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L
++#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L
++#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L
++#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L
++//DP3_DP_STEER_FIFO
++#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0
++#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4
++#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5
++#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6
++#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7
++#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8
++#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc
++#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L
++#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L
++#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L
++#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L
++#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L
++#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L
++#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L
++//DP3_DP_MSA_MISC
++#define DP3_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x3
++#define DP3_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8
++#define DP3_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10
++#define DP3_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18
++#define DP3_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x00000078L
++#define DP3_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L
++#define DP3_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L
++#define DP3_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L
++//DP3_DP_VID_TIMING
++#define DP3_DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x0
++#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4
++#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8
++#define DP3_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN__SHIFT 0x9
++#define DP3_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18
++#define DP3_DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x00000001L
++#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L
++#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L
++#define DP3_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN_MASK 0x00000200L
++#define DP3_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L
++//DP3_DP_VID_N
++#define DP3_DP_VID_N__DP_VID_N__SHIFT 0x0
++#define DP3_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL
++//DP3_DP_VID_M
++#define DP3_DP_VID_M__DP_VID_M__SHIFT 0x0
++#define DP3_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL
++//DP3_DP_LINK_FRAMING_CNTL
++#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0
++#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18
++#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c
++#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL
++#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L
++#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L
++//DP3_DP_HBR2_EYE_PATTERN
++#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0
++#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L
++//DP3_DP_VID_MSA_VBID
++#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0
++#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x10
++#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18
++#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL
++#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x00010000L
++#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L
++//DP3_DP_VID_INTERRUPT_CNTL
++#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0
++#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1
++#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2
++#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L
++#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L
++#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L
++//DP3_DP_DPHY_CNTL
++#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0
++#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1
++#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2
++#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3
++#define DP3_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10
++#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18
++#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L
++#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L
++#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L
++#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L
++#define DP3_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L
++#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L
++//DP3_DP_DPHY_TRAINING_PATTERN_SEL
++#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0
++#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L
++//DP3_DP_DPHY_SYM0
++#define DP3_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0
++#define DP3_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa
++#define DP3_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14
++#define DP3_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL
++#define DP3_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L
++#define DP3_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L
++//DP3_DP_DPHY_SYM1
++#define DP3_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0
++#define DP3_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa
++#define DP3_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14
++#define DP3_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL
++#define DP3_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L
++#define DP3_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L
++//DP3_DP_DPHY_SYM2
++#define DP3_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0
++#define DP3_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa
++#define DP3_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL
++#define DP3_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L
++//DP3_DP_DPHY_8B10B_CNTL
++#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8
++#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10
++#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18
++#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L
++#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L
++#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L
++//DP3_DP_DPHY_PRBS_CNTL
++#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0
++#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4
++#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8
++#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L
++#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L
++#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L
++//DP3_DP_DPHY_SCRAM_CNTL
++#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0
++#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4
++#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8
++#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18
++#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L
++#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L
++#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L
++#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L
++//DP3_DP_DPHY_CRC_EN
++#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0
++#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4
++#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8
++#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L
++#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L
++#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L
++//DP3_DP_DPHY_CRC_CNTL
++#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0
++#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4
++#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10
++#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L
++#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L
++#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L
++//DP3_DP_DPHY_CRC_RESULT
++#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0
++#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8
++#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10
++#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18
++#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL
++#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L
++#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L
++#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L
++//DP3_DP_DPHY_CRC_MST_CNTL
++#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0
++#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8
++#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL
++#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L
++//DP3_DP_DPHY_CRC_MST_STATUS
++#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0
++#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8
++#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10
++#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L
++#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L
++#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L
++//DP3_DP_DPHY_FAST_TRAINING
++#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0
++#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1
++#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2
++#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8
++#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14
++#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L
++#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L
++#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L
++#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L
++#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L
++//DP3_DP_DPHY_FAST_TRAINING_STATUS
++#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0
++#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4
++#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8
++#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc
++#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L
++#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L
++#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L
++#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L
++//DP3_DP_MSA_V_TIMING_OVERRIDE1
++#define DP3_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x0
++#define DP3_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x4
++#define DP3_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x00000001L
++#define DP3_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x0003FFF0L
++//DP3_DP_MSA_V_TIMING_OVERRIDE2
++#define DP3_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x0
++#define DP3_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x10
++#define DP3_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x00003FFFL
++#define DP3_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x3FFF0000L
++//DP3_DP_SEC_CNTL
++#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0
++#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4
++#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8
++#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc
++#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10
++#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14
++#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15
++#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16
++#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17
++#define DP3_DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x18
++#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c
++#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L
++#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L
++#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L
++#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L
++#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L
++#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L
++#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L
++#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L
++#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L
++#define DP3_DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x01000000L
++#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L
++//DP3_DP_SEC_CNTL1
++#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0
++#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4
++#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5
++#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6
++#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7
++#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10
++#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L
++#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L
++#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L
++#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L
++#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L
++#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L
++//DP3_DP_SEC_FRAMING1
++#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0
++#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10
++#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL
++#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
++//DP3_DP_SEC_FRAMING2
++#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0
++#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10
++#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL
++#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
++//DP3_DP_SEC_FRAMING3
++#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0
++#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10
++#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL
++#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L
++//DP3_DP_SEC_FRAMING4
++#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14
++#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18
++#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c
++#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d
++#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L
++#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L
++#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L
++#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L
++//DP3_DP_SEC_AUD_N
++#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0
++#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL
++//DP3_DP_SEC_AUD_N_READBACK
++#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0
++#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL
++//DP3_DP_SEC_AUD_M
++#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0
++#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL
++//DP3_DP_SEC_AUD_M_READBACK
++#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0
++#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL
++//DP3_DP_SEC_TIMESTAMP
++#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0
++#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L
++//DP3_DP_SEC_PACKET_CNTL
++#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1
++#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4
++#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8
++#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10
++#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL
++#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L
++#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L
++#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L
++//DP3_DP_MSE_RATE_CNTL
++#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0
++#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a
++#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL
++#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L
++//DP3_DP_MSE_RATE_UPDATE
++#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0
++#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L
++//DP3_DP_MSE_SAT0
++#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0
++#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8
++#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10
++#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18
++#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L
++#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L
++#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L
++#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L
++//DP3_DP_MSE_SAT1
++#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0
++#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8
++#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10
++#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18
++#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L
++#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L
++#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L
++#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L
++//DP3_DP_MSE_SAT2
++#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0
++#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8
++#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10
++#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18
++#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L
++#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L
++#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L
++#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L
++//DP3_DP_MSE_SAT_UPDATE
++#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0
++#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8
++#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L
++#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L
++//DP3_DP_MSE_LINK_TIMING
++#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0
++#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10
++#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL
++#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L
++//DP3_DP_MSE_MISC_CNTL
++#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0
++#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4
++#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8
++#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L
++#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L
++#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L
++//DP3_DP_DPHY_BS_SR_SWAP_CNTL
++#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0
++#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf
++#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10
++#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL
++#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L
++#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L
++//DP3_DP_DPHY_HBR2_PATTERN_CONTROL
++#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0
++#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L
++//DP3_DP_MSE_SAT0_STATUS
++#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0
++#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8
++#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10
++#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18
++#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L
++#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L
++#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L
++#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L
++//DP3_DP_MSE_SAT1_STATUS
++#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0
++#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8
++#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10
++#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18
++#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L
++#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L
++#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L
++#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L
++//DP3_DP_MSE_SAT2_STATUS
++#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0
++#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8
++#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10
++#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18
++#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L
++#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L
++#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L
++#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L
++
++
++// addressBlock: dce_dc_dig4_dispdec
++//DIG4_DIG_FE_CNTL
++#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0
++#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4
++#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8
++#define DIG4_DIG_FE_CNTL__DIG_START__SHIFT 0xa
++#define DIG4_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18
++#define DIG4_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c
++#define DIG4_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e
++#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L
++#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L
++#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L
++#define DIG4_DIG_FE_CNTL__DIG_START_MASK 0x00000400L
++#define DIG4_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L
++#define DIG4_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L
++#define DIG4_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L
++//DIG4_DIG_OUTPUT_CRC_CNTL
++#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0
++#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4
++#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8
++#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L
++#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L
++#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L
++//DIG4_DIG_OUTPUT_CRC_RESULT
++#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0
++#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL
++//DIG4_DIG_CLOCK_PATTERN
++#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0
++#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL
++//DIG4_DIG_TEST_PATTERN
++#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0
++#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1
++#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4
++#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5
++#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6
++#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10
++#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L
++#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L
++#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L
++#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L
++#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L
++#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L
++//DIG4_DIG_RANDOM_PATTERN_SEED
++#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0
++#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18
++#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL
++#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L
++//DIG4_DIG_FIFO_STATUS
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L
++//DIG4_HDMI_CONTROL
++#define DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0
++#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1
++#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2
++#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3
++#define DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4
++#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8
++#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9
++#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18
++#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c
++#define DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L
++#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L
++#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L
++#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L
++#define DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L
++#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L
++#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L
++#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L
++#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L
++//DIG4_HDMI_STATUS
++#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0
++#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10
++#define DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14
++#define DIG4_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b
++#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L
++#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L
++#define DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L
++#define DIG4_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L
++//DIG4_HDMI_AUDIO_PACKET_CONTROL
++#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4
++#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10
++#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L
++#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L
++//DIG4_HDMI_ACR_PACKET_CONTROL
++#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0
++#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1
++#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4
++#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8
++#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc
++#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10
++#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f
++#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L
++#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L
++#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L
++#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L
++#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L
++#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L
++#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L
++//DIG4_HDMI_VBI_PACKET_CONTROL
++#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0
++#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4
++#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5
++#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8
++#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9
++#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10
++#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L
++#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L
++#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L
++#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L
++#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L
++#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L
++//DIG4_HDMI_INFOFRAME_CONTROL0
++#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x0
++#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x1
++#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4
++#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5
++#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8
++#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9
++#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x00000001L
++#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x00000002L
++#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L
++#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L
++#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L
++#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L
++//DIG4_HDMI_INFOFRAME_CONTROL1
++#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x0
++#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8
++#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10
++#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x0000003FL
++#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L
++#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L
++//DIG4_HDMI_GENERIC_PACKET_CONTROL0
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003F0000L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3F000000L
++//DIG4_AFMT_INTERRUPT_STATUS
++//DIG4_HDMI_GC
++#define DIG4_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0
++#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2
++#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4
++#define DIG4_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8
++#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc
++#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L
++#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L
++#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L
++#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L
++#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L
++//DIG4_AFMT_AUDIO_PACKET_CONTROL2
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L
++//DIG4_AFMT_ISRC1_0
++#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0
++#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6
++#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7
++#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L
++#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L
++#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L
++//DIG4_AFMT_ISRC1_1
++#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0
++#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8
++#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10
++#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18
++#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL
++#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L
++#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L
++#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L
++//DIG4_AFMT_ISRC1_2
++#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0
++#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8
++#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10
++#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18
++#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL
++#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L
++#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L
++#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L
++//DIG4_AFMT_ISRC1_3
++#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0
++#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8
++#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10
++#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18
++#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL
++#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L
++#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L
++#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L
++//DIG4_AFMT_ISRC1_4
++#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0
++#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8
++#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10
++#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18
++#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL
++#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L
++#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L
++#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L
++//DIG4_AFMT_ISRC2_0
++#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0
++#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8
++#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10
++#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18
++#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL
++#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L
++#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L
++#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L
++//DIG4_AFMT_ISRC2_1
++#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0
++#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8
++#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10
++#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18
++#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL
++#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L
++#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L
++#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L
++//DIG4_AFMT_ISRC2_2
++#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0
++#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8
++#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10
++#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18
++#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL
++#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L
++#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L
++#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L
++//DIG4_AFMT_ISRC2_3
++#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0
++#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8
++#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10
++#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18
++#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL
++#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L
++#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L
++#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L
++//DIG4_AFMT_AVI_INFO0
++#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x0
++#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x8
++#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0xa
++#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0xc
++#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0xd
++#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x10
++#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x14
++#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x16
++#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x18
++#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x1a
++#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x1c
++#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x1f
++#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0x000000FFL
++#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x00000300L
++#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0x00000C00L
++#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x00001000L
++#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x0000E000L
++#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0x000F0000L
++#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x00300000L
++#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0x00C00000L
++#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x03000000L
++#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0x0C000000L
++#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000L
++#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000L
++//DIG4_AFMT_AVI_INFO1
++#define DIG4_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x0
++#define DIG4_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x8
++#define DIG4_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0xc
++#define DIG4_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0xe
++#define DIG4_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x10
++#define DIG4_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x000000FFL
++#define DIG4_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0x00000F00L
++#define DIG4_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x00003000L
++#define DIG4_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0x0000C000L
++#define DIG4_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xFFFF0000L
++//DIG4_AFMT_AVI_INFO2
++#define DIG4_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x0
++#define DIG4_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x10
++#define DIG4_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0x0000FFFFL
++#define DIG4_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xFFFF0000L
++//DIG4_AFMT_AVI_INFO3
++#define DIG4_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x0
++#define DIG4_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x18
++#define DIG4_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0x0000FFFFL
++#define DIG4_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xFF000000L
++//DIG4_AFMT_MPEG_INFO0
++#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0
++#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8
++#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10
++#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18
++#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL
++#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L
++#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L
++#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L
++//DIG4_AFMT_MPEG_INFO1
++#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0
++#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8
++#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc
++#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL
++#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L
++#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L
++//DIG4_AFMT_GENERIC_HDR
++#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0
++#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8
++#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10
++#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18
++#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL
++#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L
++#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L
++#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L
++//DIG4_AFMT_GENERIC_0
++#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0
++#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8
++#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10
++#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18
++#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL
++#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L
++#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L
++#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L
++//DIG4_AFMT_GENERIC_1
++#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0
++#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8
++#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10
++#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18
++#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL
++#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L
++#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L
++#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L
++//DIG4_AFMT_GENERIC_2
++#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0
++#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8
++#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10
++#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18
++#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL
++#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L
++#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L
++#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L
++//DIG4_AFMT_GENERIC_3
++#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0
++#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8
++#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10
++#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18
++#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL
++#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L
++#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L
++#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L
++//DIG4_AFMT_GENERIC_4
++#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0
++#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8
++#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10
++#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18
++#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL
++#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L
++#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L
++#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L
++//DIG4_AFMT_GENERIC_5
++#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0
++#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8
++#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10
++#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18
++#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL
++#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L
++#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L
++#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L
++//DIG4_AFMT_GENERIC_6
++#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0
++#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8
++#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10
++#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18
++#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL
++#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L
++#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L
++#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L
++//DIG4_AFMT_GENERIC_7
++#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0
++#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8
++#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10
++#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18
++#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL
++#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L
++#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L
++#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L
++//DIG4_HDMI_GENERIC_PACKET_CONTROL1
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003F0000L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3F000000L
++//DIG4_HDMI_ACR_32_0
++#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc
++#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L
++//DIG4_HDMI_ACR_32_1
++#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0
++#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL
++//DIG4_HDMI_ACR_44_0
++#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc
++#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L
++//DIG4_HDMI_ACR_44_1
++#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0
++#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL
++//DIG4_HDMI_ACR_48_0
++#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc
++#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L
++//DIG4_HDMI_ACR_48_1
++#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0
++#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL
++//DIG4_HDMI_ACR_STATUS_0
++#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc
++#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L
++//DIG4_HDMI_ACR_STATUS_1
++#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0
++#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL
++//DIG4_AFMT_AUDIO_INFO0
++#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0
++#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8
++#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb
++#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10
++#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18
++#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL
++#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L
++#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L
++#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L
++#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L
++//DIG4_AFMT_AUDIO_INFO1
++#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0
++#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb
++#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf
++#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10
++#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL
++#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L
++#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L
++#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L
++//DIG4_AFMT_60958_0
++#define DIG4_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0
++#define DIG4_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1
++#define DIG4_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2
++#define DIG4_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3
++#define DIG4_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6
++#define DIG4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8
++#define DIG4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10
++#define DIG4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14
++#define DIG4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18
++#define DIG4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c
++#define DIG4_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
++#define DIG4_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
++#define DIG4_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L
++#define DIG4_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L
++#define DIG4_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L
++#define DIG4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L
++#define DIG4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L
++#define DIG4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L
++#define DIG4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L
++#define DIG4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L
++//DIG4_AFMT_60958_1
++#define DIG4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0
++#define DIG4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4
++#define DIG4_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10
++#define DIG4_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12
++#define DIG4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14
++#define DIG4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL
++#define DIG4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L
++#define DIG4_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L
++#define DIG4_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L
++#define DIG4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L
++//DIG4_AFMT_AUDIO_CRC_CONTROL
++#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0
++#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4
++#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8
++#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc
++#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10
++#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L
++#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L
++#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L
++#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L
++#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L
++//DIG4_AFMT_RAMP_CONTROL0
++#define DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0
++#define DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f
++#define DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL
++#define DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L
++//DIG4_AFMT_RAMP_CONTROL1
++#define DIG4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0
++#define DIG4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18
++#define DIG4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL
++#define DIG4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L
++//DIG4_AFMT_RAMP_CONTROL2
++#define DIG4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0
++#define DIG4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL
++//DIG4_AFMT_RAMP_CONTROL3
++#define DIG4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0
++#define DIG4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL
++//DIG4_AFMT_60958_2
++#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
++#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
++#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8
++#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc
++#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10
++#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14
++#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
++#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
++#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L
++#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L
++#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L
++#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L
++//DIG4_AFMT_AUDIO_CRC_RESULT
++#define DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0
++#define DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8
++#define DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L
++#define DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L
++//DIG4_AFMT_STATUS
++#define DIG4_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4
++#define DIG4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8
++#define DIG4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18
++#define DIG4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e
++#define DIG4_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L
++#define DIG4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L
++#define DIG4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L
++#define DIG4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L
++//DIG4_AFMT_AUDIO_PACKET_CONTROL
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L
++//DIG4_AFMT_VBI_PACKET_CONTROL
++#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x2
++#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x3
++#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1e
++#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x00000004L
++#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x00000008L
++#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xC0000000L
++//DIG4_AFMT_INFOFRAME_CONTROL0
++#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6
++#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7
++#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa
++#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L
++#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L
++#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L
++//DIG4_AFMT_AUDIO_SRC_CONTROL
++#define DIG4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0
++#define DIG4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L
++//DIG4_DIG_BE_CNTL
++#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0
++#define DIG4_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1
++#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8
++#define DIG4_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10
++#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c
++#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L
++#define DIG4_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L
++#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L
++#define DIG4_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L
++#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L
++//DIG4_DIG_BE_EN_CNTL
++#define DIG4_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0
++#define DIG4_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8
++#define DIG4_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L
++#define DIG4_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L
++//DIG4_TMDS_CNTL
++#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0
++#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L
++//DIG4_TMDS_CONTROL_CHAR
++#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0
++#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1
++#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2
++#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3
++#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L
++#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L
++#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L
++#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L
++//DIG4_TMDS_CONTROL0_FEEDBACK
++#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0
++#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8
++#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L
++#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L
++//DIG4_TMDS_STEREOSYNC_CTL_SEL
++#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0
++#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L
++//DIG4_TMDS_SYNC_CHAR_PATTERN_0_1
++#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0
++#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10
++#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL
++#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L
++//DIG4_TMDS_SYNC_CHAR_PATTERN_2_3
++#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0
++#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10
++#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL
++#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L
++//DIG4_TMDS_CTL_BITS
++#define DIG4_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0
++#define DIG4_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8
++#define DIG4_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10
++#define DIG4_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18
++#define DIG4_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L
++#define DIG4_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L
++#define DIG4_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L
++#define DIG4_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L
++//DIG4_TMDS_DCBALANCER_CONTROL
++#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0
++#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8
++#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10
++#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18
++#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L
++#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L
++#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L
++#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L
++//DIG4_TMDS_CTL0_1_GEN_CNTL
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L
++//DIG4_TMDS_CTL2_3_GEN_CNTL
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L
++//DIG4_DIG_VERSION
++#define DIG4_DIG_VERSION__DIG_TYPE__SHIFT 0x0
++#define DIG4_DIG_VERSION__DIG_TYPE_MASK 0x00000001L
++//DIG4_DIG_LANE_ENABLE
++#define DIG4_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0
++#define DIG4_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1
++#define DIG4_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2
++#define DIG4_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3
++#define DIG4_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8
++#define DIG4_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L
++#define DIG4_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L
++#define DIG4_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L
++#define DIG4_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L
++#define DIG4_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L
++//DIG4_AFMT_CNTL
++#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0
++#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8
++#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L
++#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L
++
++
++// addressBlock: dce_dc_dp4_dispdec
++//DP4_DP_LINK_CNTL
++#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4
++#define DP4_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8
++#define DP4_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11
++#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L
++#define DP4_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L
++#define DP4_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L
++//DP4_DP_PIXEL_FORMAT
++#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0
++#define DP4_DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x8
++#define DP4_DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x10
++#define DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18
++#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L
++#define DP4_DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x00000100L
++#define DP4_DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x00010000L
++#define DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L
++//DP4_DP_MSA_COLORIMETRY
++#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x0
++#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x8
++#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE__SHIFT 0x9
++#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE__SHIFT 0x11
++#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0x000000FFL
++#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x00000100L
++#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_MASK 0x00000200L
++#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE_MASK 0x00020000L
++//DP4_DP_CONFIG
++#define DP4_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0
++#define DP4_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L
++//DP4_DP_VID_STREAM_CNTL
++#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0
++#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8
++#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10
++#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14
++#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L
++#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L
++#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L
++#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L
++//DP4_DP_STEER_FIFO
++#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0
++#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4
++#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5
++#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6
++#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7
++#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8
++#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc
++#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L
++#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L
++#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L
++#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L
++#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L
++#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L
++#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L
++//DP4_DP_MSA_MISC
++#define DP4_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x3
++#define DP4_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8
++#define DP4_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10
++#define DP4_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18
++#define DP4_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x00000078L
++#define DP4_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L
++#define DP4_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L
++#define DP4_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L
++//DP4_DP_VID_TIMING
++#define DP4_DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x0
++#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4
++#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8
++#define DP4_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN__SHIFT 0x9
++#define DP4_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18
++#define DP4_DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x00000001L
++#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L
++#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L
++#define DP4_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN_MASK 0x00000200L
++#define DP4_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L
++//DP4_DP_VID_N
++#define DP4_DP_VID_N__DP_VID_N__SHIFT 0x0
++#define DP4_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL
++//DP4_DP_VID_M
++#define DP4_DP_VID_M__DP_VID_M__SHIFT 0x0
++#define DP4_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL
++//DP4_DP_LINK_FRAMING_CNTL
++#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0
++#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18
++#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c
++#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL
++#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L
++#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L
++//DP4_DP_HBR2_EYE_PATTERN
++#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0
++#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L
++//DP4_DP_VID_MSA_VBID
++#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0
++#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x10
++#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18
++#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL
++#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x00010000L
++#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L
++//DP4_DP_VID_INTERRUPT_CNTL
++#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0
++#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1
++#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2
++#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L
++#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L
++#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L
++//DP4_DP_DPHY_CNTL
++#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0
++#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1
++#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2
++#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3
++#define DP4_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10
++#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18
++#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L
++#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L
++#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L
++#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L
++#define DP4_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L
++#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L
++//DP4_DP_DPHY_TRAINING_PATTERN_SEL
++#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0
++#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L
++//DP4_DP_DPHY_SYM0
++#define DP4_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0
++#define DP4_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa
++#define DP4_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14
++#define DP4_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL
++#define DP4_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L
++#define DP4_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L
++//DP4_DP_DPHY_SYM1
++#define DP4_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0
++#define DP4_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa
++#define DP4_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14
++#define DP4_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL
++#define DP4_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L
++#define DP4_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L
++//DP4_DP_DPHY_SYM2
++#define DP4_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0
++#define DP4_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa
++#define DP4_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL
++#define DP4_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L
++//DP4_DP_DPHY_8B10B_CNTL
++#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8
++#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10
++#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18
++#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L
++#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L
++#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L
++//DP4_DP_DPHY_PRBS_CNTL
++#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0
++#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4
++#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8
++#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L
++#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L
++#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L
++//DP4_DP_DPHY_SCRAM_CNTL
++#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0
++#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4
++#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8
++#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18
++#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L
++#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L
++#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L
++#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L
++//DP4_DP_DPHY_CRC_EN
++#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0
++#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4
++#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8
++#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L
++#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L
++#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L
++//DP4_DP_DPHY_CRC_CNTL
++#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0
++#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4
++#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10
++#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L
++#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L
++#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L
++//DP4_DP_DPHY_CRC_RESULT
++#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0
++#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8
++#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10
++#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18
++#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL
++#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L
++#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L
++#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L
++//DP4_DP_DPHY_CRC_MST_CNTL
++#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0
++#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8
++#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL
++#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L
++//DP4_DP_DPHY_CRC_MST_STATUS
++#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0
++#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8
++#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10
++#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L
++#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L
++#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L
++//DP4_DP_DPHY_FAST_TRAINING
++#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0
++#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1
++#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2
++#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8
++#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14
++#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L
++#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L
++#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L
++#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L
++#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L
++//DP4_DP_DPHY_FAST_TRAINING_STATUS
++#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0
++#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4
++#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8
++#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc
++#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L
++#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L
++#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L
++#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L
++//DP4_DP_MSA_V_TIMING_OVERRIDE1
++#define DP4_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x0
++#define DP4_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x4
++#define DP4_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x00000001L
++#define DP4_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x0003FFF0L
++//DP4_DP_MSA_V_TIMING_OVERRIDE2
++#define DP4_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x0
++#define DP4_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x10
++#define DP4_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x00003FFFL
++#define DP4_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x3FFF0000L
++//DP4_DP_SEC_CNTL
++#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0
++#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4
++#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8
++#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc
++#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10
++#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14
++#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15
++#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16
++#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17
++#define DP4_DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x18
++#define DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c
++#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L
++#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L
++#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L
++#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L
++#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L
++#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L
++#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L
++#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L
++#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L
++#define DP4_DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x01000000L
++#define DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L
++//DP4_DP_SEC_CNTL1
++#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0
++#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4
++#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5
++#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6
++#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7
++#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10
++#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L
++#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L
++#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L
++#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L
++#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L
++#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L
++//DP4_DP_SEC_FRAMING1
++#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0
++#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10
++#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL
++#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
++//DP4_DP_SEC_FRAMING2
++#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0
++#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10
++#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL
++#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
++//DP4_DP_SEC_FRAMING3
++#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0
++#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10
++#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL
++#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L
++//DP4_DP_SEC_FRAMING4
++#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14
++#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18
++#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c
++#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d
++#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L
++#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L
++#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L
++#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L
++//DP4_DP_SEC_AUD_N
++#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0
++#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL
++//DP4_DP_SEC_AUD_N_READBACK
++#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0
++#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL
++//DP4_DP_SEC_AUD_M
++#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0
++#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL
++//DP4_DP_SEC_AUD_M_READBACK
++#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0
++#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL
++//DP4_DP_SEC_TIMESTAMP
++#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0
++#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L
++//DP4_DP_SEC_PACKET_CNTL
++#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1
++#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4
++#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8
++#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10
++#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL
++#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L
++#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L
++#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L
++//DP4_DP_MSE_RATE_CNTL
++#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0
++#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a
++#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL
++#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L
++//DP4_DP_MSE_RATE_UPDATE
++#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0
++#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L
++//DP4_DP_MSE_SAT0
++#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0
++#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8
++#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10
++#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18
++#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L
++#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L
++#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L
++#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L
++//DP4_DP_MSE_SAT1
++#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0
++#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8
++#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10
++#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18
++#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L
++#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L
++#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L
++#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L
++//DP4_DP_MSE_SAT2
++#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0
++#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8
++#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10
++#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18
++#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L
++#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L
++#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L
++#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L
++//DP4_DP_MSE_SAT_UPDATE
++#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0
++#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8
++#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L
++#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L
++//DP4_DP_MSE_LINK_TIMING
++#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0
++#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10
++#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL
++#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L
++//DP4_DP_MSE_MISC_CNTL
++#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0
++#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4
++#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8
++#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L
++#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L
++#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L
++//DP4_DP_DPHY_BS_SR_SWAP_CNTL
++#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0
++#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf
++#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10
++#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL
++#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L
++#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L
++//DP4_DP_DPHY_HBR2_PATTERN_CONTROL
++#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0
++#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L
++//DP4_DP_MSE_SAT0_STATUS
++#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0
++#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8
++#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10
++#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18
++#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L
++#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L
++#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L
++#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L
++//DP4_DP_MSE_SAT1_STATUS
++#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0
++#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8
++#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10
++#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18
++#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L
++#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L
++#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L
++#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L
++//DP4_DP_MSE_SAT2_STATUS
++#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0
++#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8
++#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10
++#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18
++#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L
++#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L
++#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L
++#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L
++
++
++// addressBlock: dce_dc_dig5_dispdec
++//DIG5_DIG_FE_CNTL
++#define DIG5_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0
++#define DIG5_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4
++#define DIG5_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8
++#define DIG5_DIG_FE_CNTL__DIG_START__SHIFT 0xa
++#define DIG5_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18
++#define DIG5_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c
++#define DIG5_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e
++#define DIG5_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L
++#define DIG5_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L
++#define DIG5_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L
++#define DIG5_DIG_FE_CNTL__DIG_START_MASK 0x00000400L
++#define DIG5_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L
++#define DIG5_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L
++#define DIG5_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L
++//DIG5_DIG_OUTPUT_CRC_CNTL
++#define DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0
++#define DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4
++#define DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8
++#define DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L
++#define DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L
++#define DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L
++//DIG5_DIG_OUTPUT_CRC_RESULT
++#define DIG5_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0
++#define DIG5_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL
++//DIG5_DIG_CLOCK_PATTERN
++#define DIG5_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0
++#define DIG5_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL
++//DIG5_DIG_TEST_PATTERN
++#define DIG5_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0
++#define DIG5_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1
++#define DIG5_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4
++#define DIG5_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5
++#define DIG5_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6
++#define DIG5_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10
++#define DIG5_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L
++#define DIG5_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L
++#define DIG5_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L
++#define DIG5_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L
++#define DIG5_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L
++#define DIG5_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L
++//DIG5_DIG_RANDOM_PATTERN_SEED
++#define DIG5_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0
++#define DIG5_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18
++#define DIG5_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL
++#define DIG5_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L
++//DIG5_DIG_FIFO_STATUS
++#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0
++#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
++#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
++#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8
++#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
++#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
++#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16
++#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a
++#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d
++#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
++#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
++#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L
++#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L
++#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL
++#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L
++#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L
++#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L
++#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L
++#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L
++#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L
++#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L
++#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L
++//DIG5_HDMI_CONTROL
++#define DIG5_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0
++#define DIG5_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1
++#define DIG5_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2
++#define DIG5_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3
++#define DIG5_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4
++#define DIG5_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8
++#define DIG5_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9
++#define DIG5_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18
++#define DIG5_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c
++#define DIG5_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L
++#define DIG5_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L
++#define DIG5_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L
++#define DIG5_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L
++#define DIG5_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L
++#define DIG5_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L
++#define DIG5_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L
++#define DIG5_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L
++#define DIG5_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L
++//DIG5_HDMI_STATUS
++#define DIG5_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0
++#define DIG5_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10
++#define DIG5_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14
++#define DIG5_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b
++#define DIG5_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L
++#define DIG5_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L
++#define DIG5_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L
++#define DIG5_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L
++//DIG5_HDMI_AUDIO_PACKET_CONTROL
++#define DIG5_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4
++#define DIG5_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10
++#define DIG5_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L
++#define DIG5_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L
++//DIG5_HDMI_ACR_PACKET_CONTROL
++#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0
++#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1
++#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4
++#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8
++#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc
++#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10
++#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f
++#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L
++#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L
++#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L
++#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L
++#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L
++#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L
++#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L
++//DIG5_HDMI_VBI_PACKET_CONTROL
++#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0
++#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4
++#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5
++#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8
++#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9
++#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10
++#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L
++#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L
++#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L
++#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L
++#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L
++#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L
++//DIG5_HDMI_INFOFRAME_CONTROL0
++#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x0
++#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x1
++#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4
++#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5
++#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8
++#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9
++#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x00000001L
++#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x00000002L
++#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L
++#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L
++#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L
++#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L
++//DIG5_HDMI_INFOFRAME_CONTROL1
++#define DIG5_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x0
++#define DIG5_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8
++#define DIG5_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10
++#define DIG5_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x0000003FL
++#define DIG5_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L
++#define DIG5_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L
++//DIG5_HDMI_GENERIC_PACKET_CONTROL0
++#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0
++#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1
++#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4
++#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5
++#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10
++#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18
++#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L
++#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L
++#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L
++#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L
++#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003F0000L
++#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3F000000L
++//DIG5_AFMT_INTERRUPT_STATUS
++//DIG5_HDMI_GC
++#define DIG5_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0
++#define DIG5_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2
++#define DIG5_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4
++#define DIG5_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8
++#define DIG5_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc
++#define DIG5_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L
++#define DIG5_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L
++#define DIG5_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L
++#define DIG5_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L
++#define DIG5_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L
++//DIG5_AFMT_AUDIO_PACKET_CONTROL2
++#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0
++#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1
++#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8
++#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10
++#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18
++#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c
++#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L
++#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L
++#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L
++#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L
++#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L
++#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L
++//DIG5_AFMT_ISRC1_0
++#define DIG5_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0
++#define DIG5_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6
++#define DIG5_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7
++#define DIG5_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L
++#define DIG5_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L
++#define DIG5_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L
++//DIG5_AFMT_ISRC1_1
++#define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0
++#define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8
++#define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10
++#define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18
++#define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL
++#define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L
++#define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L
++#define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L
++//DIG5_AFMT_ISRC1_2
++#define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0
++#define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8
++#define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10
++#define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18
++#define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL
++#define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L
++#define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L
++#define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L
++//DIG5_AFMT_ISRC1_3
++#define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0
++#define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8
++#define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10
++#define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18
++#define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL
++#define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L
++#define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L
++#define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L
++//DIG5_AFMT_ISRC1_4
++#define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0
++#define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8
++#define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10
++#define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18
++#define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL
++#define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L
++#define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L
++#define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L
++//DIG5_AFMT_ISRC2_0
++#define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0
++#define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8
++#define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10
++#define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18
++#define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL
++#define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L
++#define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L
++#define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L
++//DIG5_AFMT_ISRC2_1
++#define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0
++#define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8
++#define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10
++#define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18
++#define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL
++#define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L
++#define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L
++#define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L
++//DIG5_AFMT_ISRC2_2
++#define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0
++#define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8
++#define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10
++#define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18
++#define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL
++#define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L
++#define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L
++#define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L
++//DIG5_AFMT_ISRC2_3
++#define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0
++#define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8
++#define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10
++#define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18
++#define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL
++#define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L
++#define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L
++#define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L
++//DIG5_AFMT_AVI_INFO0
++#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x0
++#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x8
++#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0xa
++#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0xc
++#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0xd
++#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x10
++#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x14
++#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x16
++#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x18
++#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x1a
++#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x1c
++#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x1f
++#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0x000000FFL
++#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x00000300L
++#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0x00000C00L
++#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x00001000L
++#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x0000E000L
++#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0x000F0000L
++#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x00300000L
++#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0x00C00000L
++#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x03000000L
++#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0x0C000000L
++#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000L
++#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000L
++//DIG5_AFMT_AVI_INFO1
++#define DIG5_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x0
++#define DIG5_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x8
++#define DIG5_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0xc
++#define DIG5_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0xe
++#define DIG5_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x10
++#define DIG5_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x000000FFL
++#define DIG5_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0x00000F00L
++#define DIG5_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x00003000L
++#define DIG5_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0x0000C000L
++#define DIG5_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xFFFF0000L
++//DIG5_AFMT_AVI_INFO2
++#define DIG5_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x0
++#define DIG5_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x10
++#define DIG5_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0x0000FFFFL
++#define DIG5_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xFFFF0000L
++//DIG5_AFMT_AVI_INFO3
++#define DIG5_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x0
++#define DIG5_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x18
++#define DIG5_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0x0000FFFFL
++#define DIG5_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xFF000000L
++//DIG5_AFMT_MPEG_INFO0
++#define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0
++#define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8
++#define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10
++#define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18
++#define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL
++#define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L
++#define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L
++#define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L
++//DIG5_AFMT_MPEG_INFO1
++#define DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0
++#define DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8
++#define DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc
++#define DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL
++#define DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L
++#define DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L
++//DIG5_AFMT_GENERIC_HDR
++#define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0
++#define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8
++#define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10
++#define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18
++#define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL
++#define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L
++#define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L
++#define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L
++//DIG5_AFMT_GENERIC_0
++#define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0
++#define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8
++#define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10
++#define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18
++#define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL
++#define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L
++#define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L
++#define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L
++//DIG5_AFMT_GENERIC_1
++#define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0
++#define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8
++#define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10
++#define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18
++#define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL
++#define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L
++#define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L
++#define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L
++//DIG5_AFMT_GENERIC_2
++#define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0
++#define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8
++#define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10
++#define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18
++#define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL
++#define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L
++#define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L
++#define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L
++//DIG5_AFMT_GENERIC_3
++#define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0
++#define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8
++#define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10
++#define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18
++#define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL
++#define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L
++#define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L
++#define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L
++//DIG5_AFMT_GENERIC_4
++#define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0
++#define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8
++#define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10
++#define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18
++#define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL
++#define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L
++#define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L
++#define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L
++//DIG5_AFMT_GENERIC_5
++#define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0
++#define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8
++#define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10
++#define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18
++#define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL
++#define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L
++#define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L
++#define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L
++//DIG5_AFMT_GENERIC_6
++#define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0
++#define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8
++#define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10
++#define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18
++#define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL
++#define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L
++#define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L
++#define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L
++//DIG5_AFMT_GENERIC_7
++#define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0
++#define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8
++#define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10
++#define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18
++#define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL
++#define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L
++#define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L
++#define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L
++//DIG5_HDMI_GENERIC_PACKET_CONTROL1
++#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0
++#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1
++#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4
++#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5
++#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10
++#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18
++#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L
++#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L
++#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L
++#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L
++#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003F0000L
++#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3F000000L
++//DIG5_HDMI_ACR_32_0
++#define DIG5_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc
++#define DIG5_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L
++//DIG5_HDMI_ACR_32_1
++#define DIG5_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0
++#define DIG5_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL
++//DIG5_HDMI_ACR_44_0
++#define DIG5_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc
++#define DIG5_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L
++//DIG5_HDMI_ACR_44_1
++#define DIG5_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0
++#define DIG5_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL
++//DIG5_HDMI_ACR_48_0
++#define DIG5_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc
++#define DIG5_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L
++//DIG5_HDMI_ACR_48_1
++#define DIG5_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0
++#define DIG5_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL
++//DIG5_HDMI_ACR_STATUS_0
++#define DIG5_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc
++#define DIG5_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L
++//DIG5_HDMI_ACR_STATUS_1
++#define DIG5_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0
++#define DIG5_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL
++//DIG5_AFMT_AUDIO_INFO0
++#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0
++#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8
++#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb
++#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10
++#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18
++#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL
++#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L
++#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L
++#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L
++#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L
++//DIG5_AFMT_AUDIO_INFO1
++#define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0
++#define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb
++#define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf
++#define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10
++#define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL
++#define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L
++#define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L
++#define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L
++//DIG5_AFMT_60958_0
++#define DIG5_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0
++#define DIG5_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1
++#define DIG5_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2
++#define DIG5_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3
++#define DIG5_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6
++#define DIG5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8
++#define DIG5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10
++#define DIG5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14
++#define DIG5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18
++#define DIG5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c
++#define DIG5_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
++#define DIG5_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
++#define DIG5_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L
++#define DIG5_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L
++#define DIG5_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L
++#define DIG5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L
++#define DIG5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L
++#define DIG5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L
++#define DIG5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L
++#define DIG5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L
++//DIG5_AFMT_60958_1
++#define DIG5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0
++#define DIG5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4
++#define DIG5_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10
++#define DIG5_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12
++#define DIG5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14
++#define DIG5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL
++#define DIG5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L
++#define DIG5_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L
++#define DIG5_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L
++#define DIG5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L
++//DIG5_AFMT_AUDIO_CRC_CONTROL
++#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0
++#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4
++#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8
++#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc
++#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10
++#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L
++#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L
++#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L
++#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L
++#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L
++//DIG5_AFMT_RAMP_CONTROL0
++#define DIG5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0
++#define DIG5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f
++#define DIG5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL
++#define DIG5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L
++//DIG5_AFMT_RAMP_CONTROL1
++#define DIG5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0
++#define DIG5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18
++#define DIG5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL
++#define DIG5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L
++//DIG5_AFMT_RAMP_CONTROL2
++#define DIG5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0
++#define DIG5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL
++//DIG5_AFMT_RAMP_CONTROL3
++#define DIG5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0
++#define DIG5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL
++//DIG5_AFMT_60958_2
++#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
++#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
++#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8
++#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc
++#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10
++#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14
++#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
++#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
++#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L
++#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L
++#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L
++#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L
++//DIG5_AFMT_AUDIO_CRC_RESULT
++#define DIG5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0
++#define DIG5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8
++#define DIG5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L
++#define DIG5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L
++//DIG5_AFMT_STATUS
++#define DIG5_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4
++#define DIG5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8
++#define DIG5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18
++#define DIG5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e
++#define DIG5_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L
++#define DIG5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L
++#define DIG5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L
++#define DIG5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L
++//DIG5_AFMT_AUDIO_PACKET_CONTROL
++#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0
++#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb
++#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc
++#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe
++#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17
++#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18
++#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a
++#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e
++#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L
++#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L
++#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L
++#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L
++#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L
++#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L
++#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L
++#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L
++//DIG5_AFMT_VBI_PACKET_CONTROL
++#define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x2
++#define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x3
++#define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1e
++#define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x00000004L
++#define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x00000008L
++#define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xC0000000L
++//DIG5_AFMT_INFOFRAME_CONTROL0
++#define DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6
++#define DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7
++#define DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa
++#define DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L
++#define DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L
++#define DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L
++//DIG5_AFMT_AUDIO_SRC_CONTROL
++#define DIG5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0
++#define DIG5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L
++//DIG5_DIG_BE_CNTL
++#define DIG5_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0
++#define DIG5_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1
++#define DIG5_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8
++#define DIG5_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10
++#define DIG5_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c
++#define DIG5_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L
++#define DIG5_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L
++#define DIG5_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L
++#define DIG5_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L
++#define DIG5_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L
++//DIG5_DIG_BE_EN_CNTL
++#define DIG5_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0
++#define DIG5_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8
++#define DIG5_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L
++#define DIG5_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L
++//DIG5_TMDS_CNTL
++#define DIG5_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0
++#define DIG5_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L
++//DIG5_TMDS_CONTROL_CHAR
++#define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0
++#define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1
++#define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2
++#define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3
++#define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L
++#define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L
++#define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L
++#define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L
++//DIG5_TMDS_CONTROL0_FEEDBACK
++#define DIG5_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0
++#define DIG5_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8
++#define DIG5_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L
++#define DIG5_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L
++//DIG5_TMDS_STEREOSYNC_CTL_SEL
++#define DIG5_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0
++#define DIG5_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L
++//DIG5_TMDS_SYNC_CHAR_PATTERN_0_1
++#define DIG5_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0
++#define DIG5_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10
++#define DIG5_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL
++#define DIG5_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L
++//DIG5_TMDS_SYNC_CHAR_PATTERN_2_3
++#define DIG5_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0
++#define DIG5_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10
++#define DIG5_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL
++#define DIG5_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L
++//DIG5_TMDS_CTL_BITS
++#define DIG5_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0
++#define DIG5_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8
++#define DIG5_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10
++#define DIG5_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18
++#define DIG5_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L
++#define DIG5_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L
++#define DIG5_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L
++#define DIG5_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L
++//DIG5_TMDS_DCBALANCER_CONTROL
++#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0
++#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8
++#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10
++#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18
++#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L
++#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L
++#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L
++#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L
++//DIG5_TMDS_CTL0_1_GEN_CNTL
++#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0
++#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4
++#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7
++#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8
++#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa
++#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb
++#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc
++#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10
++#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14
++#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17
++#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18
++#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a
++#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b
++#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c
++#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f
++#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL
++#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L
++#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L
++#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L
++#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L
++#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L
++#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L
++#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L
++#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L
++#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L
++#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L
++#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L
++#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L
++#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L
++#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L
++//DIG5_TMDS_CTL2_3_GEN_CNTL
++#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0
++#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4
++#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7
++#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8
++#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa
++#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb
++#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc
++#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10
++#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14
++#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17
++#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18
++#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a
++#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b
++#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c
++#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL
++#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L
++#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L
++#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L
++#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L
++#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L
++#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L
++#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L
++#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L
++#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L
++#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L
++#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L
++#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L
++#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L
++//DIG5_DIG_VERSION
++#define DIG5_DIG_VERSION__DIG_TYPE__SHIFT 0x0
++#define DIG5_DIG_VERSION__DIG_TYPE_MASK 0x00000001L
++//DIG5_DIG_LANE_ENABLE
++#define DIG5_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0
++#define DIG5_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1
++#define DIG5_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2
++#define DIG5_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3
++#define DIG5_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8
++#define DIG5_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L
++#define DIG5_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L
++#define DIG5_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L
++#define DIG5_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L
++#define DIG5_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L
++//DIG5_AFMT_CNTL
++#define DIG5_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0
++#define DIG5_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8
++#define DIG5_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L
++#define DIG5_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L
++
++
++// addressBlock: dce_dc_dp5_dispdec
++//DP5_DP_LINK_CNTL
++#define DP5_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4
++#define DP5_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8
++#define DP5_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11
++#define DP5_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L
++#define DP5_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L
++#define DP5_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L
++//DP5_DP_PIXEL_FORMAT
++#define DP5_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0
++#define DP5_DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x8
++#define DP5_DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x10
++#define DP5_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18
++#define DP5_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L
++#define DP5_DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x00000100L
++#define DP5_DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x00010000L
++#define DP5_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L
++//DP5_DP_MSA_COLORIMETRY
++#define DP5_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x0
++#define DP5_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x8
++#define DP5_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE__SHIFT 0x9
++#define DP5_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE__SHIFT 0x11
++#define DP5_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0x000000FFL
++#define DP5_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x00000100L
++#define DP5_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_MASK 0x00000200L
++#define DP5_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE_MASK 0x00020000L
++//DP5_DP_CONFIG
++#define DP5_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0
++#define DP5_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L
++//DP5_DP_VID_STREAM_CNTL
++#define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0
++#define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8
++#define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10
++#define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14
++#define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L
++#define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L
++#define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L
++#define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L
++//DP5_DP_STEER_FIFO
++#define DP5_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0
++#define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4
++#define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5
++#define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6
++#define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7
++#define DP5_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8
++#define DP5_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc
++#define DP5_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L
++#define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L
++#define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L
++#define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L
++#define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L
++#define DP5_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L
++#define DP5_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L
++//DP5_DP_MSA_MISC
++#define DP5_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x3
++#define DP5_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8
++#define DP5_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10
++#define DP5_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18
++#define DP5_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x00000078L
++#define DP5_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L
++#define DP5_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L
++#define DP5_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L
++//DP5_DP_VID_TIMING
++#define DP5_DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x0
++#define DP5_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4
++#define DP5_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8
++#define DP5_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN__SHIFT 0x9
++#define DP5_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18
++#define DP5_DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x00000001L
++#define DP5_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L
++#define DP5_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L
++#define DP5_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN_MASK 0x00000200L
++#define DP5_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L
++//DP5_DP_VID_N
++#define DP5_DP_VID_N__DP_VID_N__SHIFT 0x0
++#define DP5_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL
++//DP5_DP_VID_M
++#define DP5_DP_VID_M__DP_VID_M__SHIFT 0x0
++#define DP5_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL
++//DP5_DP_LINK_FRAMING_CNTL
++#define DP5_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0
++#define DP5_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18
++#define DP5_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c
++#define DP5_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL
++#define DP5_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L
++#define DP5_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L
++//DP5_DP_HBR2_EYE_PATTERN
++#define DP5_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0
++#define DP5_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L
++//DP5_DP_VID_MSA_VBID
++#define DP5_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0
++#define DP5_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x10
++#define DP5_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18
++#define DP5_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL
++#define DP5_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x00010000L
++#define DP5_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L
++//DP5_DP_VID_INTERRUPT_CNTL
++#define DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0
++#define DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1
++#define DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2
++#define DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L
++#define DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L
++#define DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L
++//DP5_DP_DPHY_CNTL
++#define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0
++#define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1
++#define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2
++#define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3
++#define DP5_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10
++#define DP5_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18
++#define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L
++#define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L
++#define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L
++#define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L
++#define DP5_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L
++#define DP5_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L
++//DP5_DP_DPHY_TRAINING_PATTERN_SEL
++#define DP5_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0
++#define DP5_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L
++//DP5_DP_DPHY_SYM0
++#define DP5_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0
++#define DP5_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa
++#define DP5_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14
++#define DP5_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL
++#define DP5_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L
++#define DP5_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L
++//DP5_DP_DPHY_SYM1
++#define DP5_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0
++#define DP5_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa
++#define DP5_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14
++#define DP5_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL
++#define DP5_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L
++#define DP5_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L
++//DP5_DP_DPHY_SYM2
++#define DP5_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0
++#define DP5_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa
++#define DP5_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL
++#define DP5_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L
++//DP5_DP_DPHY_8B10B_CNTL
++#define DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8
++#define DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10
++#define DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18
++#define DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L
++#define DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L
++#define DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L
++//DP5_DP_DPHY_PRBS_CNTL
++#define DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0
++#define DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4
++#define DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8
++#define DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L
++#define DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L
++#define DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L
++//DP5_DP_DPHY_SCRAM_CNTL
++#define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0
++#define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4
++#define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8
++#define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18
++#define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L
++#define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L
++#define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L
++#define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L
++//DP5_DP_DPHY_CRC_EN
++#define DP5_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0
++#define DP5_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4
++#define DP5_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8
++#define DP5_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L
++#define DP5_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L
++#define DP5_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L
++//DP5_DP_DPHY_CRC_CNTL
++#define DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0
++#define DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4
++#define DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10
++#define DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L
++#define DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L
++#define DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L
++//DP5_DP_DPHY_CRC_RESULT
++#define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0
++#define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8
++#define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10
++#define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18
++#define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL
++#define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L
++#define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L
++#define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L
++//DP5_DP_DPHY_CRC_MST_CNTL
++#define DP5_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0
++#define DP5_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8
++#define DP5_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL
++#define DP5_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L
++//DP5_DP_DPHY_CRC_MST_STATUS
++#define DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0
++#define DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8
++#define DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10
++#define DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L
++#define DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L
++#define DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L
++//DP5_DP_DPHY_FAST_TRAINING
++#define DP5_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0
++#define DP5_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1
++#define DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2
++#define DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8
++#define DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14
++#define DP5_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L
++#define DP5_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L
++#define DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L
++#define DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L
++#define DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L
++//DP5_DP_DPHY_FAST_TRAINING_STATUS
++#define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0
++#define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4
++#define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8
++#define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc
++#define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L
++#define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L
++#define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L
++#define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L
++//DP5_DP_MSA_V_TIMING_OVERRIDE1
++#define DP5_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x0
++#define DP5_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x4
++#define DP5_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x00000001L
++#define DP5_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x0003FFF0L
++//DP5_DP_MSA_V_TIMING_OVERRIDE2
++#define DP5_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x0
++#define DP5_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x10
++#define DP5_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x00003FFFL
++#define DP5_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x3FFF0000L
++//DP5_DP_SEC_CNTL
++#define DP5_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0
++#define DP5_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4
++#define DP5_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8
++#define DP5_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc
++#define DP5_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10
++#define DP5_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14
++#define DP5_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15
++#define DP5_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16
++#define DP5_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17
++#define DP5_DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x18
++#define DP5_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c
++#define DP5_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L
++#define DP5_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L
++#define DP5_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L
++#define DP5_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L
++#define DP5_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L
++#define DP5_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L
++#define DP5_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L
++#define DP5_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L
++#define DP5_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L
++#define DP5_DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x01000000L
++#define DP5_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L
++//DP5_DP_SEC_CNTL1
++#define DP5_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0
++#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4
++#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5
++#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6
++#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7
++#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10
++#define DP5_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L
++#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L
++#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L
++#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L
++#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L
++#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L
++//DP5_DP_SEC_FRAMING1
++#define DP5_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0
++#define DP5_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10
++#define DP5_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL
++#define DP5_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
++//DP5_DP_SEC_FRAMING2
++#define DP5_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0
++#define DP5_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10
++#define DP5_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL
++#define DP5_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
++//DP5_DP_SEC_FRAMING3
++#define DP5_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0
++#define DP5_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10
++#define DP5_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL
++#define DP5_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L
++//DP5_DP_SEC_FRAMING4
++#define DP5_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14
++#define DP5_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18
++#define DP5_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c
++#define DP5_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d
++#define DP5_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L
++#define DP5_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L
++#define DP5_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L
++#define DP5_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L
++//DP5_DP_SEC_AUD_N
++#define DP5_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0
++#define DP5_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL
++//DP5_DP_SEC_AUD_N_READBACK
++#define DP5_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0
++#define DP5_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL
++//DP5_DP_SEC_AUD_M
++#define DP5_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0
++#define DP5_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL
++//DP5_DP_SEC_AUD_M_READBACK
++#define DP5_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0
++#define DP5_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL
++//DP5_DP_SEC_TIMESTAMP
++#define DP5_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0
++#define DP5_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L
++//DP5_DP_SEC_PACKET_CNTL
++#define DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1
++#define DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4
++#define DP5_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8
++#define DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10
++#define DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL
++#define DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L
++#define DP5_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L
++#define DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L
++//DP5_DP_MSE_RATE_CNTL
++#define DP5_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0
++#define DP5_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a
++#define DP5_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL
++#define DP5_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L
++//DP5_DP_MSE_RATE_UPDATE
++#define DP5_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0
++#define DP5_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L
++//DP5_DP_MSE_SAT0
++#define DP5_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0
++#define DP5_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8
++#define DP5_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10
++#define DP5_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18
++#define DP5_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L
++#define DP5_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L
++#define DP5_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L
++#define DP5_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L
++//DP5_DP_MSE_SAT1
++#define DP5_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0
++#define DP5_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8
++#define DP5_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10
++#define DP5_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18
++#define DP5_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L
++#define DP5_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L
++#define DP5_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L
++#define DP5_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L
++//DP5_DP_MSE_SAT2
++#define DP5_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0
++#define DP5_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8
++#define DP5_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10
++#define DP5_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18
++#define DP5_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L
++#define DP5_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L
++#define DP5_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L
++#define DP5_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L
++//DP5_DP_MSE_SAT_UPDATE
++#define DP5_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0
++#define DP5_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8
++#define DP5_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L
++#define DP5_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L
++//DP5_DP_MSE_LINK_TIMING
++#define DP5_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0
++#define DP5_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10
++#define DP5_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL
++#define DP5_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L
++//DP5_DP_MSE_MISC_CNTL
++#define DP5_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0
++#define DP5_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4
++#define DP5_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8
++#define DP5_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L
++#define DP5_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L
++#define DP5_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L
++//DP5_DP_DPHY_BS_SR_SWAP_CNTL
++#define DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0
++#define DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf
++#define DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10
++#define DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL
++#define DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L
++#define DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L
++//DP5_DP_DPHY_HBR2_PATTERN_CONTROL
++#define DP5_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0
++#define DP5_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L
++//DP5_DP_MSE_SAT0_STATUS
++#define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0
++#define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8
++#define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10
++#define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18
++#define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L
++#define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L
++#define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L
++#define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L
++//DP5_DP_MSE_SAT1_STATUS
++#define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0
++#define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8
++#define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10
++#define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18
++#define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L
++#define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L
++#define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L
++#define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L
++//DP5_DP_MSE_SAT2_STATUS
++#define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0
++#define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8
++#define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10
++#define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18
++#define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L
++#define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L
++#define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L
++#define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L
++
++
++// addressBlock: dce_dc_dig6_dispdec
++//DIG6_DIG_FE_CNTL
++#define DIG6_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0
++#define DIG6_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4
++#define DIG6_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8
++#define DIG6_DIG_FE_CNTL__DIG_START__SHIFT 0xa
++#define DIG6_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18
++#define DIG6_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c
++#define DIG6_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e
++#define DIG6_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L
++#define DIG6_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L
++#define DIG6_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L
++#define DIG6_DIG_FE_CNTL__DIG_START_MASK 0x00000400L
++#define DIG6_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L
++#define DIG6_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L
++#define DIG6_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L
++//DIG6_DIG_OUTPUT_CRC_CNTL
++#define DIG6_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0
++#define DIG6_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4
++#define DIG6_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8
++#define DIG6_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L
++#define DIG6_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L
++#define DIG6_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L
++//DIG6_DIG_OUTPUT_CRC_RESULT
++#define DIG6_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0
++#define DIG6_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL
++//DIG6_DIG_CLOCK_PATTERN
++#define DIG6_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0
++#define DIG6_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL
++//DIG6_DIG_TEST_PATTERN
++#define DIG6_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0
++#define DIG6_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1
++#define DIG6_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4
++#define DIG6_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5
++#define DIG6_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6
++#define DIG6_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10
++#define DIG6_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L
++#define DIG6_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L
++#define DIG6_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L
++#define DIG6_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L
++#define DIG6_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L
++#define DIG6_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L
++//DIG6_DIG_RANDOM_PATTERN_SEED
++#define DIG6_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0
++#define DIG6_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18
++#define DIG6_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL
++#define DIG6_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L
++//DIG6_DIG_FIFO_STATUS
++#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0
++#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
++#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
++#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8
++#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
++#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
++#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16
++#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a
++#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d
++#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
++#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
++#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L
++#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L
++#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL
++#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L
++#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L
++#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L
++#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L
++#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L
++#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L
++#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L
++#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L
++//DIG6_HDMI_CONTROL
++#define DIG6_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0
++#define DIG6_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1
++#define DIG6_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2
++#define DIG6_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3
++#define DIG6_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4
++#define DIG6_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8
++#define DIG6_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9
++#define DIG6_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18
++#define DIG6_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c
++#define DIG6_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L
++#define DIG6_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L
++#define DIG6_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L
++#define DIG6_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L
++#define DIG6_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L
++#define DIG6_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L
++#define DIG6_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L
++#define DIG6_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L
++#define DIG6_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L
++//DIG6_HDMI_STATUS
++#define DIG6_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0
++#define DIG6_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10
++#define DIG6_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14
++#define DIG6_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b
++#define DIG6_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L
++#define DIG6_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L
++#define DIG6_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L
++#define DIG6_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L
++//DIG6_HDMI_AUDIO_PACKET_CONTROL
++#define DIG6_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4
++#define DIG6_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10
++#define DIG6_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L
++#define DIG6_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L
++//DIG6_HDMI_ACR_PACKET_CONTROL
++#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0
++#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1
++#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4
++#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8
++#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc
++#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10
++#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f
++#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L
++#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L
++#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L
++#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L
++#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L
++#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L
++#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L
++//DIG6_HDMI_VBI_PACKET_CONTROL
++#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0
++#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4
++#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5
++#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8
++#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9
++#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10
++#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L
++#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L
++#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L
++#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L
++#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L
++#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L
++//DIG6_HDMI_INFOFRAME_CONTROL0
++#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x0
++#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x1
++#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4
++#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5
++#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8
++#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9
++#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x00000001L
++#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x00000002L
++#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L
++#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L
++#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L
++#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L
++//DIG6_HDMI_INFOFRAME_CONTROL1
++#define DIG6_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x0
++#define DIG6_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8
++#define DIG6_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10
++#define DIG6_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x0000003FL
++#define DIG6_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L
++#define DIG6_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L
++//DIG6_HDMI_GENERIC_PACKET_CONTROL0
++#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0
++#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1
++#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4
++#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5
++#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10
++#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18
++#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L
++#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L
++#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L
++#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L
++#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003F0000L
++#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3F000000L
++//DIG6_AFMT_INTERRUPT_STATUS
++//DIG6_HDMI_GC
++#define DIG6_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0
++#define DIG6_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2
++#define DIG6_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4
++#define DIG6_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8
++#define DIG6_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc
++#define DIG6_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L
++#define DIG6_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L
++#define DIG6_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L
++#define DIG6_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L
++#define DIG6_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L
++//DIG6_AFMT_AUDIO_PACKET_CONTROL2
++#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0
++#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1
++#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8
++#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10
++#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18
++#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c
++#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L
++#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L
++#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L
++#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L
++#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L
++#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L
++//DIG6_AFMT_ISRC1_0
++#define DIG6_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0
++#define DIG6_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6
++#define DIG6_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7
++#define DIG6_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L
++#define DIG6_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L
++#define DIG6_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L
++//DIG6_AFMT_ISRC1_1
++#define DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0
++#define DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8
++#define DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10
++#define DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18
++#define DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL
++#define DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L
++#define DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L
++#define DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L
++//DIG6_AFMT_ISRC1_2
++#define DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0
++#define DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8
++#define DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10
++#define DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18
++#define DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL
++#define DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L
++#define DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L
++#define DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L
++//DIG6_AFMT_ISRC1_3
++#define DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0
++#define DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8
++#define DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10
++#define DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18
++#define DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL
++#define DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L
++#define DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L
++#define DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L
++//DIG6_AFMT_ISRC1_4
++#define DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0
++#define DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8
++#define DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10
++#define DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18
++#define DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL
++#define DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L
++#define DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L
++#define DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L
++//DIG6_AFMT_ISRC2_0
++#define DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0
++#define DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8
++#define DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10
++#define DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18
++#define DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL
++#define DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L
++#define DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L
++#define DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L
++//DIG6_AFMT_ISRC2_1
++#define DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0
++#define DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8
++#define DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10
++#define DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18
++#define DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL
++#define DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L
++#define DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L
++#define DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L
++//DIG6_AFMT_ISRC2_2
++#define DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0
++#define DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8
++#define DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10
++#define DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18
++#define DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL
++#define DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L
++#define DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L
++#define DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L
++//DIG6_AFMT_ISRC2_3
++#define DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0
++#define DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8
++#define DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10
++#define DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18
++#define DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL
++#define DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L
++#define DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L
++#define DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L
++//DIG6_AFMT_AVI_INFO0
++#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x0
++#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x8
++#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0xa
++#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0xc
++#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0xd
++#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x10
++#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x14
++#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x16
++#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x18
++#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x1a
++#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x1c
++#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x1f
++#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0x000000FFL
++#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x00000300L
++#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0x00000C00L
++#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x00001000L
++#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x0000E000L
++#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0x000F0000L
++#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x00300000L
++#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0x00C00000L
++#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x03000000L
++#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0x0C000000L
++#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000L
++#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000L
++//DIG6_AFMT_AVI_INFO1
++#define DIG6_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x0
++#define DIG6_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x8
++#define DIG6_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0xc
++#define DIG6_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0xe
++#define DIG6_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x10
++#define DIG6_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x000000FFL
++#define DIG6_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0x00000F00L
++#define DIG6_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x00003000L
++#define DIG6_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0x0000C000L
++#define DIG6_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xFFFF0000L
++//DIG6_AFMT_AVI_INFO2
++#define DIG6_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x0
++#define DIG6_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x10
++#define DIG6_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0x0000FFFFL
++#define DIG6_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xFFFF0000L
++//DIG6_AFMT_AVI_INFO3
++#define DIG6_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x0
++#define DIG6_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x18
++#define DIG6_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0x0000FFFFL
++#define DIG6_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xFF000000L
++//DIG6_AFMT_MPEG_INFO0
++#define DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0
++#define DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8
++#define DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10
++#define DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18
++#define DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL
++#define DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L
++#define DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L
++#define DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L
++//DIG6_AFMT_MPEG_INFO1
++#define DIG6_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0
++#define DIG6_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8
++#define DIG6_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc
++#define DIG6_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL
++#define DIG6_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L
++#define DIG6_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L
++//DIG6_AFMT_GENERIC_HDR
++#define DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0
++#define DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8
++#define DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10
++#define DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18
++#define DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL
++#define DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L
++#define DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L
++#define DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L
++//DIG6_AFMT_GENERIC_0
++#define DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0
++#define DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8
++#define DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10
++#define DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18
++#define DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL
++#define DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L
++#define DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L
++#define DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L
++//DIG6_AFMT_GENERIC_1
++#define DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0
++#define DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8
++#define DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10
++#define DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18
++#define DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL
++#define DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L
++#define DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L
++#define DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L
++//DIG6_AFMT_GENERIC_2
++#define DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0
++#define DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8
++#define DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10
++#define DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18
++#define DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL
++#define DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L
++#define DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L
++#define DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L
++//DIG6_AFMT_GENERIC_3
++#define DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0
++#define DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8
++#define DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10
++#define DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18
++#define DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL
++#define DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L
++#define DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L
++#define DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L
++//DIG6_AFMT_GENERIC_4
++#define DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0
++#define DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8
++#define DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10
++#define DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18
++#define DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL
++#define DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L
++#define DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L
++#define DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L
++//DIG6_AFMT_GENERIC_5
++#define DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0
++#define DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8
++#define DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10
++#define DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18
++#define DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL
++#define DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L
++#define DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L
++#define DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L
++//DIG6_AFMT_GENERIC_6
++#define DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0
++#define DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8
++#define DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10
++#define DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18
++#define DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL
++#define DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L
++#define DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L
++#define DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L
++//DIG6_AFMT_GENERIC_7
++#define DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0
++#define DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8
++#define DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10
++#define DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18
++#define DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL
++#define DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L
++#define DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L
++#define DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L
++//DIG6_HDMI_GENERIC_PACKET_CONTROL1
++#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0
++#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1
++#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4
++#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5
++#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10
++#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18
++#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L
++#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L
++#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L
++#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L
++#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003F0000L
++#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3F000000L
++//DIG6_HDMI_ACR_32_0
++#define DIG6_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc
++#define DIG6_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L
++//DIG6_HDMI_ACR_32_1
++#define DIG6_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0
++#define DIG6_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL
++//DIG6_HDMI_ACR_44_0
++#define DIG6_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc
++#define DIG6_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L
++//DIG6_HDMI_ACR_44_1
++#define DIG6_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0
++#define DIG6_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL
++//DIG6_HDMI_ACR_48_0
++#define DIG6_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc
++#define DIG6_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L
++//DIG6_HDMI_ACR_48_1
++#define DIG6_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0
++#define DIG6_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL
++//DIG6_HDMI_ACR_STATUS_0
++#define DIG6_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc
++#define DIG6_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L
++//DIG6_HDMI_ACR_STATUS_1
++#define DIG6_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0
++#define DIG6_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL
++//DIG6_AFMT_AUDIO_INFO0
++#define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0
++#define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8
++#define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb
++#define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10
++#define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18
++#define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL
++#define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L
++#define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L
++#define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L
++#define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L
++//DIG6_AFMT_AUDIO_INFO1
++#define DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0
++#define DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb
++#define DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf
++#define DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10
++#define DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL
++#define DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L
++#define DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L
++#define DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L
++//DIG6_AFMT_60958_0
++#define DIG6_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0
++#define DIG6_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1
++#define DIG6_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2
++#define DIG6_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3
++#define DIG6_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6
++#define DIG6_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8
++#define DIG6_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10
++#define DIG6_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14
++#define DIG6_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18
++#define DIG6_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c
++#define DIG6_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
++#define DIG6_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
++#define DIG6_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L
++#define DIG6_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L
++#define DIG6_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L
++#define DIG6_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L
++#define DIG6_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L
++#define DIG6_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L
++#define DIG6_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L
++#define DIG6_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L
++//DIG6_AFMT_60958_1
++#define DIG6_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0
++#define DIG6_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4
++#define DIG6_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10
++#define DIG6_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12
++#define DIG6_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14
++#define DIG6_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL
++#define DIG6_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L
++#define DIG6_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L
++#define DIG6_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L
++#define DIG6_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L
++//DIG6_AFMT_AUDIO_CRC_CONTROL
++#define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0
++#define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4
++#define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8
++#define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc
++#define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10
++#define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L
++#define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L
++#define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L
++#define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L
++#define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L
++//DIG6_AFMT_RAMP_CONTROL0
++#define DIG6_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0
++#define DIG6_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f
++#define DIG6_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL
++#define DIG6_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L
++//DIG6_AFMT_RAMP_CONTROL1
++#define DIG6_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0
++#define DIG6_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18
++#define DIG6_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL
++#define DIG6_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L
++//DIG6_AFMT_RAMP_CONTROL2
++#define DIG6_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0
++#define DIG6_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL
++//DIG6_AFMT_RAMP_CONTROL3
++#define DIG6_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0
++#define DIG6_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL
++//DIG6_AFMT_60958_2
++#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
++#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
++#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8
++#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc
++#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10
++#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14
++#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
++#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
++#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L
++#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L
++#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L
++#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L
++//DIG6_AFMT_AUDIO_CRC_RESULT
++#define DIG6_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0
++#define DIG6_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8
++#define DIG6_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L
++#define DIG6_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L
++//DIG6_AFMT_STATUS
++#define DIG6_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4
++#define DIG6_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8
++#define DIG6_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18
++#define DIG6_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e
++#define DIG6_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L
++#define DIG6_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L
++#define DIG6_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L
++#define DIG6_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L
++//DIG6_AFMT_AUDIO_PACKET_CONTROL
++#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0
++#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb
++#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc
++#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe
++#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17
++#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18
++#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a
++#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e
++#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L
++#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L
++#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L
++#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L
++#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L
++#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L
++#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L
++#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L
++//DIG6_AFMT_VBI_PACKET_CONTROL
++#define DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x2
++#define DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x3
++#define DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1e
++#define DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x00000004L
++#define DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x00000008L
++#define DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xC0000000L
++//DIG6_AFMT_INFOFRAME_CONTROL0
++#define DIG6_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6
++#define DIG6_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7
++#define DIG6_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa
++#define DIG6_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L
++#define DIG6_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L
++#define DIG6_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L
++//DIG6_AFMT_AUDIO_SRC_CONTROL
++#define DIG6_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0
++#define DIG6_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L
++//DIG6_DIG_BE_CNTL
++#define DIG6_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0
++#define DIG6_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1
++#define DIG6_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8
++#define DIG6_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10
++#define DIG6_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c
++#define DIG6_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L
++#define DIG6_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L
++#define DIG6_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L
++#define DIG6_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L
++#define DIG6_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L
++//DIG6_DIG_BE_EN_CNTL
++#define DIG6_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0
++#define DIG6_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8
++#define DIG6_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L
++#define DIG6_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L
++//DIG6_TMDS_CNTL
++#define DIG6_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0
++#define DIG6_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L
++//DIG6_TMDS_CONTROL_CHAR
++#define DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0
++#define DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1
++#define DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2
++#define DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3
++#define DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L
++#define DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L
++#define DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L
++#define DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L
++//DIG6_TMDS_CONTROL0_FEEDBACK
++#define DIG6_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0
++#define DIG6_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8
++#define DIG6_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L
++#define DIG6_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L
++//DIG6_TMDS_STEREOSYNC_CTL_SEL
++#define DIG6_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0
++#define DIG6_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L
++//DIG6_TMDS_SYNC_CHAR_PATTERN_0_1
++#define DIG6_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0
++#define DIG6_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10
++#define DIG6_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL
++#define DIG6_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L
++//DIG6_TMDS_SYNC_CHAR_PATTERN_2_3
++#define DIG6_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0
++#define DIG6_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10
++#define DIG6_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL
++#define DIG6_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L
++//DIG6_TMDS_CTL_BITS
++#define DIG6_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0
++#define DIG6_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8
++#define DIG6_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10
++#define DIG6_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18
++#define DIG6_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L
++#define DIG6_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L
++#define DIG6_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L
++#define DIG6_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L
++//DIG6_TMDS_DCBALANCER_CONTROL
++#define DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0
++#define DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8
++#define DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10
++#define DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18
++#define DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L
++#define DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L
++#define DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L
++#define DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L
++//DIG6_TMDS_CTL0_1_GEN_CNTL
++#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0
++#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4
++#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7
++#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8
++#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa
++#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb
++#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc
++#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10
++#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14
++#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17
++#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18
++#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a
++#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b
++#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c
++#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f
++#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL
++#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L
++#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L
++#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L
++#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L
++#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L
++#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L
++#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L
++#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L
++#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L
++#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L
++#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L
++#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L
++#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L
++#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L
++//DIG6_TMDS_CTL2_3_GEN_CNTL
++#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0
++#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4
++#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7
++#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8
++#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa
++#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb
++#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc
++#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10
++#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14
++#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17
++#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18
++#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a
++#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b
++#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c
++#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL
++#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L
++#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L
++#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L
++#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L
++#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L
++#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L
++#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L
++#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L
++#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L
++#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L
++#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L
++#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L
++#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L
++//DIG6_DIG_VERSION
++#define DIG6_DIG_VERSION__DIG_TYPE__SHIFT 0x0
++#define DIG6_DIG_VERSION__DIG_TYPE_MASK 0x00000001L
++//DIG6_DIG_LANE_ENABLE
++#define DIG6_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0
++#define DIG6_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1
++#define DIG6_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2
++#define DIG6_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3
++#define DIG6_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8
++#define DIG6_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L
++#define DIG6_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L
++#define DIG6_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L
++#define DIG6_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L
++#define DIG6_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L
++//DIG6_AFMT_CNTL
++#define DIG6_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0
++#define DIG6_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8
++#define DIG6_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L
++#define DIG6_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L
++
++
++// addressBlock: dce_dc_dp6_dispdec
++//DP6_DP_LINK_CNTL
++#define DP6_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4
++#define DP6_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8
++#define DP6_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11
++#define DP6_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L
++#define DP6_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L
++#define DP6_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L
++//DP6_DP_PIXEL_FORMAT
++#define DP6_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0
++#define DP6_DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x8
++#define DP6_DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x10
++#define DP6_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18
++#define DP6_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L
++#define DP6_DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x00000100L
++#define DP6_DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x00010000L
++#define DP6_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L
++//DP6_DP_MSA_COLORIMETRY
++#define DP6_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x0
++#define DP6_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x8
++#define DP6_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE__SHIFT 0x9
++#define DP6_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE__SHIFT 0x11
++#define DP6_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0x000000FFL
++#define DP6_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x00000100L
++#define DP6_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_MASK 0x00000200L
++#define DP6_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE_MASK 0x00020000L
++//DP6_DP_CONFIG
++#define DP6_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0
++#define DP6_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L
++//DP6_DP_VID_STREAM_CNTL
++#define DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0
++#define DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8
++#define DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10
++#define DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14
++#define DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L
++#define DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L
++#define DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L
++#define DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L
++//DP6_DP_STEER_FIFO
++#define DP6_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0
++#define DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4
++#define DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5
++#define DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6
++#define DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7
++#define DP6_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8
++#define DP6_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc
++#define DP6_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L
++#define DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L
++#define DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L
++#define DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L
++#define DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L
++#define DP6_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L
++#define DP6_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L
++//DP6_DP_MSA_MISC
++#define DP6_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x3
++#define DP6_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8
++#define DP6_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10
++#define DP6_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18
++#define DP6_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x00000078L
++#define DP6_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L
++#define DP6_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L
++#define DP6_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L
++//DP6_DP_VID_TIMING
++#define DP6_DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x0
++#define DP6_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4
++#define DP6_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8
++#define DP6_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN__SHIFT 0x9
++#define DP6_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18
++#define DP6_DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x00000001L
++#define DP6_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L
++#define DP6_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L
++#define DP6_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN_MASK 0x00000200L
++#define DP6_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L
++//DP6_DP_VID_N
++#define DP6_DP_VID_N__DP_VID_N__SHIFT 0x0
++#define DP6_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL
++//DP6_DP_VID_M
++#define DP6_DP_VID_M__DP_VID_M__SHIFT 0x0
++#define DP6_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL
++//DP6_DP_LINK_FRAMING_CNTL
++#define DP6_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0
++#define DP6_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18
++#define DP6_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c
++#define DP6_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL
++#define DP6_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L
++#define DP6_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L
++//DP6_DP_HBR2_EYE_PATTERN
++#define DP6_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0
++#define DP6_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L
++//DP6_DP_VID_MSA_VBID
++#define DP6_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0
++#define DP6_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x10
++#define DP6_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18
++#define DP6_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL
++#define DP6_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x00010000L
++#define DP6_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L
++//DP6_DP_VID_INTERRUPT_CNTL
++#define DP6_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0
++#define DP6_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1
++#define DP6_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2
++#define DP6_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L
++#define DP6_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L
++#define DP6_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L
++//DP6_DP_DPHY_CNTL
++#define DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0
++#define DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1
++#define DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2
++#define DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3
++#define DP6_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10
++#define DP6_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18
++#define DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L
++#define DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L
++#define DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L
++#define DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L
++#define DP6_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L
++#define DP6_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L
++//DP6_DP_DPHY_TRAINING_PATTERN_SEL
++#define DP6_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0
++#define DP6_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L
++//DP6_DP_DPHY_SYM0
++#define DP6_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0
++#define DP6_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa
++#define DP6_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14
++#define DP6_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL
++#define DP6_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L
++#define DP6_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L
++//DP6_DP_DPHY_SYM1
++#define DP6_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0
++#define DP6_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa
++#define DP6_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14
++#define DP6_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL
++#define DP6_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L
++#define DP6_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L
++//DP6_DP_DPHY_SYM2
++#define DP6_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0
++#define DP6_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa
++#define DP6_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL
++#define DP6_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L
++//DP6_DP_DPHY_8B10B_CNTL
++#define DP6_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8
++#define DP6_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10
++#define DP6_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18
++#define DP6_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L
++#define DP6_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L
++#define DP6_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L
++//DP6_DP_DPHY_PRBS_CNTL
++#define DP6_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0
++#define DP6_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4
++#define DP6_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8
++#define DP6_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L
++#define DP6_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L
++#define DP6_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L
++//DP6_DP_DPHY_SCRAM_CNTL
++#define DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0
++#define DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4
++#define DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8
++#define DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18
++#define DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L
++#define DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L
++#define DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L
++#define DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L
++//DP6_DP_DPHY_CRC_EN
++#define DP6_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0
++#define DP6_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4
++#define DP6_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8
++#define DP6_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L
++#define DP6_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L
++#define DP6_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L
++//DP6_DP_DPHY_CRC_CNTL
++#define DP6_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0
++#define DP6_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4
++#define DP6_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10
++#define DP6_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L
++#define DP6_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L
++#define DP6_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L
++//DP6_DP_DPHY_CRC_RESULT
++#define DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0
++#define DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8
++#define DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10
++#define DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18
++#define DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL
++#define DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L
++#define DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L
++#define DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L
++//DP6_DP_DPHY_CRC_MST_CNTL
++#define DP6_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0
++#define DP6_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8
++#define DP6_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL
++#define DP6_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L
++//DP6_DP_DPHY_CRC_MST_STATUS
++#define DP6_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0
++#define DP6_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8
++#define DP6_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10
++#define DP6_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L
++#define DP6_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L
++#define DP6_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L
++//DP6_DP_DPHY_FAST_TRAINING
++#define DP6_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0
++#define DP6_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1
++#define DP6_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2
++#define DP6_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8
++#define DP6_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14
++#define DP6_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L
++#define DP6_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L
++#define DP6_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L
++#define DP6_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L
++#define DP6_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L
++//DP6_DP_DPHY_FAST_TRAINING_STATUS
++#define DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0
++#define DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4
++#define DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8
++#define DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc
++#define DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L
++#define DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L
++#define DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L
++#define DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L
++//DP6_DP_MSA_V_TIMING_OVERRIDE1
++#define DP6_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x0
++#define DP6_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x4
++#define DP6_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x00000001L
++#define DP6_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x0003FFF0L
++//DP6_DP_MSA_V_TIMING_OVERRIDE2
++#define DP6_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x0
++#define DP6_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x10
++#define DP6_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x00003FFFL
++#define DP6_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x3FFF0000L
++//DP6_DP_SEC_CNTL
++#define DP6_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0
++#define DP6_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4
++#define DP6_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8
++#define DP6_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc
++#define DP6_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10
++#define DP6_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14
++#define DP6_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15
++#define DP6_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16
++#define DP6_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17
++#define DP6_DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x18
++#define DP6_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c
++#define DP6_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L
++#define DP6_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L
++#define DP6_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L
++#define DP6_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L
++#define DP6_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L
++#define DP6_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L
++#define DP6_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L
++#define DP6_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L
++#define DP6_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L
++#define DP6_DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x01000000L
++#define DP6_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L
++//DP6_DP_SEC_CNTL1
++#define DP6_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0
++#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4
++#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5
++#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6
++#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7
++#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10
++#define DP6_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L
++#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L
++#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L
++#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L
++#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L
++#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L
++//DP6_DP_SEC_FRAMING1
++#define DP6_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0
++#define DP6_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10
++#define DP6_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL
++#define DP6_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
++//DP6_DP_SEC_FRAMING2
++#define DP6_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0
++#define DP6_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10
++#define DP6_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL
++#define DP6_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
++//DP6_DP_SEC_FRAMING3
++#define DP6_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0
++#define DP6_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10
++#define DP6_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL
++#define DP6_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L
++//DP6_DP_SEC_FRAMING4
++#define DP6_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14
++#define DP6_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18
++#define DP6_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c
++#define DP6_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d
++#define DP6_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L
++#define DP6_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L
++#define DP6_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L
++#define DP6_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L
++//DP6_DP_SEC_AUD_N
++#define DP6_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0
++#define DP6_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL
++//DP6_DP_SEC_AUD_N_READBACK
++#define DP6_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0
++#define DP6_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL
++//DP6_DP_SEC_AUD_M
++#define DP6_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0
++#define DP6_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL
++//DP6_DP_SEC_AUD_M_READBACK
++#define DP6_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0
++#define DP6_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL
++//DP6_DP_SEC_TIMESTAMP
++#define DP6_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0
++#define DP6_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L
++//DP6_DP_SEC_PACKET_CNTL
++#define DP6_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1
++#define DP6_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4
++#define DP6_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8
++#define DP6_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10
++#define DP6_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL
++#define DP6_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L
++#define DP6_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L
++#define DP6_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L
++//DP6_DP_MSE_RATE_CNTL
++#define DP6_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0
++#define DP6_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a
++#define DP6_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL
++#define DP6_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L
++//DP6_DP_MSE_RATE_UPDATE
++#define DP6_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0
++#define DP6_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L
++//DP6_DP_MSE_SAT0
++#define DP6_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0
++#define DP6_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8
++#define DP6_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10
++#define DP6_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18
++#define DP6_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L
++#define DP6_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L
++#define DP6_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L
++#define DP6_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L
++//DP6_DP_MSE_SAT1
++#define DP6_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0
++#define DP6_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8
++#define DP6_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10
++#define DP6_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18
++#define DP6_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L
++#define DP6_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L
++#define DP6_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L
++#define DP6_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L
++//DP6_DP_MSE_SAT2
++#define DP6_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0
++#define DP6_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8
++#define DP6_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10
++#define DP6_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18
++#define DP6_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L
++#define DP6_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L
++#define DP6_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L
++#define DP6_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L
++//DP6_DP_MSE_SAT_UPDATE
++#define DP6_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0
++#define DP6_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8
++#define DP6_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L
++#define DP6_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L
++//DP6_DP_MSE_LINK_TIMING
++#define DP6_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0
++#define DP6_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10
++#define DP6_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL
++#define DP6_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L
++//DP6_DP_MSE_MISC_CNTL
++#define DP6_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0
++#define DP6_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4
++#define DP6_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8
++#define DP6_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L
++#define DP6_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L
++#define DP6_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L
++//DP6_DP_DPHY_BS_SR_SWAP_CNTL
++#define DP6_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0
++#define DP6_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf
++#define DP6_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10
++#define DP6_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL
++#define DP6_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L
++#define DP6_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L
++//DP6_DP_DPHY_HBR2_PATTERN_CONTROL
++#define DP6_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0
++#define DP6_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L
++//DP6_DP_MSE_SAT0_STATUS
++#define DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0
++#define DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8
++#define DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10
++#define DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18
++#define DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L
++#define DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L
++#define DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L
++#define DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L
++//DP6_DP_MSE_SAT1_STATUS
++#define DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0
++#define DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8
++#define DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10
++#define DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18
++#define DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L
++#define DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L
++#define DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L
++#define DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L
++//DP6_DP_MSE_SAT2_STATUS
++#define DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0
++#define DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8
++#define DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10
++#define DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18
++#define DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L
++#define DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L
++#define DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L
++#define DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L
++
++
++// addressBlock: dce_dc_dcio_uniphy0_dispdec
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dc_combophycmregs0_dispdec
++//DC_COMBOPHYCMREGS0_COMMON_FUSE1
++#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_valid__SHIFT 0x0
++#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated0__SHIFT 0x1
++#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_ron_override_val__SHIFT 0x3
++#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated1__SHIFT 0x9
++#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0xa
++#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated2__SHIFT 0xc
++#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_rtt_override_val__SHIFT 0xd
++#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated3__SHIFT 0x13
++#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0x14
++#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_refresh_cal_en__SHIFT 0x16
++#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_spare__SHIFT 0x17
++#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_valid_MASK 0x00000001L
++#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated0_MASK 0x00000006L
++#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_ron_override_val_MASK 0x000001F8L
++#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated1_MASK 0x00000200L
++#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x00000C00L
++#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated2_MASK 0x00001000L
++#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_rtt_override_val_MASK 0x0007E000L
++#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated3_MASK 0x00080000L
++#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x00300000L
++#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_refresh_cal_en_MASK 0x00400000L
++#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_spare_MASK 0xFF800000L
++//DC_COMBOPHYCMREGS0_COMMON_FUSE2
++#define DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_valid__SHIFT 0x0
++#define DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_unpopulated__SHIFT 0x1
++#define DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_tx_fifo_ptr__SHIFT 0x9
++#define DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_spare__SHIFT 0xe
++#define DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_valid_MASK 0x00000001L
++#define DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_unpopulated_MASK 0x000001FEL
++#define DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_tx_fifo_ptr_MASK 0x00003E00L
++#define DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_spare_MASK 0xFFFFC000L
++//DC_COMBOPHYCMREGS0_COMMON_FUSE3
++#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_valid__SHIFT 0x0
++#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_unpopulated__SHIFT 0x1
++#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_ei_det_thresh_sel__SHIFT 0xa
++#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d
++#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_valid_MASK 0x00000001L
++#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_unpopulated_MASK 0x000003FEL
++#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_ei_det_thresh_sel_MASK 0x00001C00L
++#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_spare_MASK 0xE0000000L
++//DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM
++#define DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0
++#define DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8
++#define DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10
++#define DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18
++#define DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0x000000FFL
++#define DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0x0000FF00L
++#define DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0x00FF0000L
++#define DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xFF000000L
++//DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT
++#define DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0
++#define DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4
++#define DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT__vprot_en__SHIFT 0xb
++#define DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT__pgdelay_MASK 0x0000000FL
++#define DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT__pgmask_MASK 0x000003F0L
++#define DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT__vprot_en_MASK 0x00000800L
++//DC_COMBOPHYCMREGS0_COMMON_TXCNTRL
++#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT 0x0
++#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__clkgate_dis__SHIFT 0x5
++#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT 0x6
++#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT 0x9
++#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT 0xc
++#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__dual_dvi_mstr_en__SHIFT 0xf
++#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__dual_dvi_en__SHIFT 0x10
++#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK 0x0000001FL
++#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__clkgate_dis_MASK 0x00000020L
++#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK 0x000001C0L
++#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK 0x00000E00L
++#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK 0x00007000L
++#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__dual_dvi_mstr_en_MASK 0x00008000L
++#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__dual_dvi_en_MASK 0x00010000L
++//DC_COMBOPHYCMREGS0_COMMON_TMDP
++#define DC_COMBOPHYCMREGS0_COMMON_TMDP__tmdp_spare__SHIFT 0x0
++#define DC_COMBOPHYCMREGS0_COMMON_TMDP__tmdp_spare_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS
++#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_0_reset_l__SHIFT 0x0
++#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_1_reset_l__SHIFT 0x1
++#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_2_reset_l__SHIFT 0x2
++#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_3_reset_l__SHIFT 0x3
++#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_4_reset_l__SHIFT 0x4
++#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_5_reset_l__SHIFT 0x5
++#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_6_reset_l__SHIFT 0x6
++#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_7_reset_l__SHIFT 0x7
++#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_0_reset_l_MASK 0x00000001L
++#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_1_reset_l_MASK 0x00000002L
++#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_2_reset_l_MASK 0x00000004L
++#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_3_reset_l_MASK 0x00000008L
++#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_4_reset_l_MASK 0x00000010L
++#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_5_reset_l_MASK 0x00000020L
++#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_6_reset_l_MASK 0x00000040L
++#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_7_reset_l_MASK 0x00000080L
++//DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL
++#define DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT 0x0
++#define DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT 0x1
++#define DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT 0x15
++#define DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__zcalcode_override_MASK 0x00000001L
++#define DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK 0x0000003EL
++#define DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK 0x00200000L
++//DC_COMBOPHYCMREGS0_COMMON_DISP_RFU1
++#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU1__rfu_value1__SHIFT 0x0
++#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU1__rfu_value1_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS0_COMMON_DISP_RFU2
++#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU2__rfu_value2__SHIFT 0x0
++#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU2__rfu_value2_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS0_COMMON_DISP_RFU3
++#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU3__rfu_value3__SHIFT 0x0
++#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU3__rfu_value3_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS0_COMMON_DISP_RFU4
++#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU4__rfu_value4__SHIFT 0x0
++#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU4__rfu_value4_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS0_COMMON_DISP_RFU5
++#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU5__rfu_value5__SHIFT 0x0
++#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU5__rfu_value5_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS0_COMMON_DISP_RFU6
++#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU6__rfu_value6__SHIFT 0x0
++#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU6__rfu_value6_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS0_COMMON_DISP_RFU7
++#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU7__rfu_value7__SHIFT 0x0
++#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU7__rfu_value7_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dc_combophytxregs0_dispdec
++//DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0
++#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3
++#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT 0x8
++#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK 0x00000100L
++//DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0
++#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT 0x3
++#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT 0x5
++#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0__txmarg_sel_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0__deemph_sel_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0__tx_margin_en_MASK 0x00000020L
++//DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x1
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x3
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT 0x8
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT 0xa
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT 0xc
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT 0xd
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT 0xe
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT 0xf
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT 0x10
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT 0x14
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT 0x16
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x00000006L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0x000000E0L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK 0x00000300L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK 0x00000C00L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK 0x00001000L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK 0x00002000L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK 0x00004000L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK 0x00008000L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK 0x000F0000L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK 0x00100000L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK 0x00C00000L
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0__rfu_value0__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0__rfu_value0_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0__rfu_value1__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0__rfu_value1_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0__rfu_value2__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0__rfu_value2_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0__rfu_value3__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0__rfu_value3_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0__rfu_value4__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0__rfu_value4_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0__rfu_value5__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0__rfu_value5_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0__rfu_value6__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0__rfu_value6_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0__rfu_value7__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0__rfu_value7_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0__rfu_value8__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0__rfu_value8_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0__rfu_value9__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0__rfu_value9_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0__rfu_value10__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0__rfu_value10_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0__rfu_value11__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0__rfu_value11_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0__rfu_value12__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0__rfu_value12_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1
++#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3
++#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT 0x8
++#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK 0x00000100L
++//DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1
++#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT 0x3
++#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT 0x5
++#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1__txmarg_sel_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1__deemph_sel_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1__tx_margin_en_MASK 0x00000020L
++//DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x1
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x3
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT 0x8
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT 0xa
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT 0xc
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT 0xd
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT 0xe
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT 0xf
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT 0x10
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT 0x14
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT 0x16
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x00000006L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0x000000E0L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK 0x00000300L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK 0x00000C00L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK 0x00001000L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK 0x00002000L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK 0x00004000L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK 0x00008000L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK 0x000F0000L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK 0x00100000L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK 0x00C00000L
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1__rfu_value0__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1__rfu_value0_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1__rfu_value1__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1__rfu_value1_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1__rfu_value2__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1__rfu_value2_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1__rfu_value3__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1__rfu_value3_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1__rfu_value4__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1__rfu_value4_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1__rfu_value5__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1__rfu_value5_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1__rfu_value6__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1__rfu_value6_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1__rfu_value7__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1__rfu_value7_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1__rfu_value8__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1__rfu_value8_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1__rfu_value9__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1__rfu_value9_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1__rfu_value10__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1__rfu_value10_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1__rfu_value11__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1__rfu_value11_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1__rfu_value12__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1__rfu_value12_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2
++#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3
++#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT 0x8
++#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK 0x00000100L
++//DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2
++#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT 0x3
++#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT 0x5
++#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2__txmarg_sel_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2__deemph_sel_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2__tx_margin_en_MASK 0x00000020L
++//DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x1
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x3
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT 0x8
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT 0xa
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT 0xc
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT 0xd
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT 0xe
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT 0xf
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT 0x10
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT 0x14
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT 0x16
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x00000006L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0x000000E0L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK 0x00000300L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK 0x00000C00L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK 0x00001000L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK 0x00002000L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK 0x00004000L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK 0x00008000L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK 0x000F0000L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK 0x00100000L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK 0x00C00000L
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2__rfu_value0__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2__rfu_value0_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2__rfu_value1__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2__rfu_value1_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2__rfu_value2__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2__rfu_value2_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2__rfu_value3__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2__rfu_value3_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2__rfu_value4__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2__rfu_value4_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2__rfu_value5__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2__rfu_value5_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2__rfu_value6__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2__rfu_value6_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2__rfu_value7__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2__rfu_value7_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2__rfu_value8__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2__rfu_value8_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2__rfu_value9__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2__rfu_value9_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2__rfu_value10__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2__rfu_value10_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2__rfu_value11__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2__rfu_value11_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2__rfu_value12__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2__rfu_value12_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3
++#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3
++#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT 0x8
++#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK 0x00000100L
++//DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3
++#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT 0x3
++#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT 0x5
++#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3__txmarg_sel_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3__deemph_sel_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3__tx_margin_en_MASK 0x00000020L
++//DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x1
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x3
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT 0x8
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT 0xa
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT 0xc
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT 0xd
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT 0xe
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT 0xf
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT 0x10
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT 0x14
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT 0x16
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x00000006L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0x000000E0L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK 0x00000300L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK 0x00000C00L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK 0x00001000L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK 0x00002000L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK 0x00004000L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK 0x00008000L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK 0x000F0000L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK 0x00100000L
++#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK 0x00C00000L
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3__rfu_value0__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3__rfu_value0_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3__rfu_value1__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3__rfu_value1_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3__rfu_value2__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3__rfu_value2_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3__rfu_value3__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3__rfu_value3_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3__rfu_value4__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3__rfu_value4_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3__rfu_value5__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3__rfu_value5_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3__rfu_value6__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3__rfu_value6_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3__rfu_value7__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3__rfu_value7_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3__rfu_value8__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3__rfu_value8_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3__rfu_value9__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3__rfu_value9_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3__rfu_value10__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3__rfu_value10_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3__rfu_value11__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3__rfu_value11_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3__rfu_value12__SHIFT 0x0
++#define DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3__rfu_value12_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dc_combophypllregs0_dispdec
++//DC_COMBOPHYPLLREGS0_FREQ_CTRL0
++#define DC_COMBOPHYPLLREGS0_FREQ_CTRL0__fcw0_frac__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS0_FREQ_CTRL0__fcw0_int__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS0_FREQ_CTRL0__fcw0_frac_MASK 0x0000FFFFL
++#define DC_COMBOPHYPLLREGS0_FREQ_CTRL0__fcw0_int_MASK 0x01FF0000L
++//DC_COMBOPHYPLLREGS0_FREQ_CTRL1
++#define DC_COMBOPHYPLLREGS0_FREQ_CTRL1__fcw1_frac__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS0_FREQ_CTRL1__fcw1_int__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS0_FREQ_CTRL1__fcw1_frac_MASK 0x0000FFFFL
++#define DC_COMBOPHYPLLREGS0_FREQ_CTRL1__fcw1_int_MASK 0x01FF0000L
++//DC_COMBOPHYPLLREGS0_FREQ_CTRL2
++#define DC_COMBOPHYPLLREGS0_FREQ_CTRL2__fcw_denom__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS0_FREQ_CTRL2__fcw_slew_frac__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS0_FREQ_CTRL2__fcw_denom_MASK 0x0000FFFFL
++#define DC_COMBOPHYPLLREGS0_FREQ_CTRL2__fcw_slew_frac_MASK 0xFFFF0000L
++//DC_COMBOPHYPLLREGS0_FREQ_CTRL3
++#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__refclk_div__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__vco_pre_div__SHIFT 0x3
++#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__fracn_en__SHIFT 0x6
++#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__ssc_en__SHIFT 0x8
++#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__fcw_sel__SHIFT 0xa
++#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__freq_jump_en__SHIFT 0xc
++#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__tdc_resolution__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__dpll_cfg_1__SHIFT 0x18
++#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__refclk_div_MASK 0x00000003L
++#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__vco_pre_div_MASK 0x00000018L
++#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__fracn_en_MASK 0x00000040L
++#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__ssc_en_MASK 0x00000100L
++#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__fcw_sel_MASK 0x00000400L
++#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__freq_jump_en_MASK 0x00001000L
++#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__tdc_resolution_MASK 0x00FF0000L
++#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__dpll_cfg_1_MASK 0xFF000000L
++//DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE
++#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gi_coarse_mant__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gi_coarse_exp__SHIFT 0x2
++#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gp_coarse_mant__SHIFT 0x7
++#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gp_coarse_exp__SHIFT 0xc
++#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__nctl_coarse_res__SHIFT 0x11
++#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT 0x18
++#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gi_coarse_mant_MASK 0x00000003L
++#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gi_coarse_exp_MASK 0x0000003CL
++#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gp_coarse_mant_MASK 0x00000780L
++#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gp_coarse_exp_MASK 0x0000F000L
++#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__nctl_coarse_res_MASK 0x007E0000L
++#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__nctl_coarse_frac_res_MASK 0x03000000L
++//DC_COMBOPHYPLLREGS0_BW_CTRL_FINE
++#define DC_COMBOPHYPLLREGS0_BW_CTRL_FINE__dpll_cfg_3__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS0_BW_CTRL_FINE__dpll_cfg_3_MASK 0x000003FFL
++//DC_COMBOPHYPLLREGS0_CAL_CTRL
++#define DC_COMBOPHYPLLREGS0_CAL_CTRL__bypass_freq_lock__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS0_CAL_CTRL__tdc_cal_en__SHIFT 0x1
++#define DC_COMBOPHYPLLREGS0_CAL_CTRL__tdc_cal_ctrl__SHIFT 0x3
++#define DC_COMBOPHYPLLREGS0_CAL_CTRL__meas_win_sel__SHIFT 0x9
++#define DC_COMBOPHYPLLREGS0_CAL_CTRL__kdco_cal_dis__SHIFT 0xb
++#define DC_COMBOPHYPLLREGS0_CAL_CTRL__kdco_ratio__SHIFT 0xd
++#define DC_COMBOPHYPLLREGS0_CAL_CTRL__kdco_incr_cal_dis__SHIFT 0x16
++#define DC_COMBOPHYPLLREGS0_CAL_CTRL__nctl_adj_dis__SHIFT 0x17
++#define DC_COMBOPHYPLLREGS0_CAL_CTRL__refclk_rate__SHIFT 0x18
++#define DC_COMBOPHYPLLREGS0_CAL_CTRL__bypass_freq_lock_MASK 0x00000001L
++#define DC_COMBOPHYPLLREGS0_CAL_CTRL__tdc_cal_en_MASK 0x00000002L
++#define DC_COMBOPHYPLLREGS0_CAL_CTRL__tdc_cal_ctrl_MASK 0x000001F8L
++#define DC_COMBOPHYPLLREGS0_CAL_CTRL__meas_win_sel_MASK 0x00000600L
++#define DC_COMBOPHYPLLREGS0_CAL_CTRL__kdco_cal_dis_MASK 0x00000800L
++#define DC_COMBOPHYPLLREGS0_CAL_CTRL__kdco_ratio_MASK 0x001FE000L
++#define DC_COMBOPHYPLLREGS0_CAL_CTRL__kdco_incr_cal_dis_MASK 0x00400000L
++#define DC_COMBOPHYPLLREGS0_CAL_CTRL__nctl_adj_dis_MASK 0x00800000L
++#define DC_COMBOPHYPLLREGS0_CAL_CTRL__refclk_rate_MASK 0xFF000000L
++//DC_COMBOPHYPLLREGS0_LOOP_CTRL
++#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__fbdiv_mask_en__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__fb_slip_dis__SHIFT 0x2
++#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__clk_tdc_sel__SHIFT 0x4
++#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__clk_nctl_sel__SHIFT 0x7
++#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__sig_del_patt_sel__SHIFT 0xa
++#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__nctl_sig_del_dis__SHIFT 0xc
++#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__fbclk_track_refclk__SHIFT 0xe
++#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__prbs_en__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__tdc_clk_gate_en__SHIFT 0x12
++#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__phase_offset__SHIFT 0x14
++#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__fbdiv_mask_en_MASK 0x00000001L
++#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__fb_slip_dis_MASK 0x00000004L
++#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__clk_tdc_sel_MASK 0x00000030L
++#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__clk_nctl_sel_MASK 0x00000180L
++#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__sig_del_patt_sel_MASK 0x00000400L
++#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__nctl_sig_del_dis_MASK 0x00001000L
++#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__fbclk_track_refclk_MASK 0x00004000L
++#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__prbs_en_MASK 0x00010000L
++#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__tdc_clk_gate_en_MASK 0x00040000L
++#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__phase_offset_MASK 0x07F00000L
++//DC_COMBOPHYPLLREGS0_VREG_CFG
++#define DC_COMBOPHYPLLREGS0_VREG_CFG__bleeder_ac__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS0_VREG_CFG__bleeder_en__SHIFT 0x1
++#define DC_COMBOPHYPLLREGS0_VREG_CFG__is_1p2__SHIFT 0x2
++#define DC_COMBOPHYPLLREGS0_VREG_CFG__reg_obs_sel__SHIFT 0x3
++#define DC_COMBOPHYPLLREGS0_VREG_CFG__reg_on_mode__SHIFT 0x5
++#define DC_COMBOPHYPLLREGS0_VREG_CFG__rlad_tap_sel__SHIFT 0x7
++#define DC_COMBOPHYPLLREGS0_VREG_CFG__reg_off_hi__SHIFT 0xb
++#define DC_COMBOPHYPLLREGS0_VREG_CFG__reg_off_lo__SHIFT 0xc
++#define DC_COMBOPHYPLLREGS0_VREG_CFG__scale_driver__SHIFT 0xd
++#define DC_COMBOPHYPLLREGS0_VREG_CFG__sel_bump__SHIFT 0xf
++#define DC_COMBOPHYPLLREGS0_VREG_CFG__sel_rladder_x__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS0_VREG_CFG__short_rc_filt_x__SHIFT 0x11
++#define DC_COMBOPHYPLLREGS0_VREG_CFG__vref_pwr_on__SHIFT 0x12
++#define DC_COMBOPHYPLLREGS0_VREG_CFG__dpll_cfg_2__SHIFT 0x14
++#define DC_COMBOPHYPLLREGS0_VREG_CFG__bleeder_ac_MASK 0x00000001L
++#define DC_COMBOPHYPLLREGS0_VREG_CFG__bleeder_en_MASK 0x00000002L
++#define DC_COMBOPHYPLLREGS0_VREG_CFG__is_1p2_MASK 0x00000004L
++#define DC_COMBOPHYPLLREGS0_VREG_CFG__reg_obs_sel_MASK 0x00000018L
++#define DC_COMBOPHYPLLREGS0_VREG_CFG__reg_on_mode_MASK 0x00000060L
++#define DC_COMBOPHYPLLREGS0_VREG_CFG__rlad_tap_sel_MASK 0x00000780L
++#define DC_COMBOPHYPLLREGS0_VREG_CFG__reg_off_hi_MASK 0x00000800L
++#define DC_COMBOPHYPLLREGS0_VREG_CFG__reg_off_lo_MASK 0x00001000L
++#define DC_COMBOPHYPLLREGS0_VREG_CFG__scale_driver_MASK 0x00006000L
++#define DC_COMBOPHYPLLREGS0_VREG_CFG__sel_bump_MASK 0x00008000L
++#define DC_COMBOPHYPLLREGS0_VREG_CFG__sel_rladder_x_MASK 0x00010000L
++#define DC_COMBOPHYPLLREGS0_VREG_CFG__short_rc_filt_x_MASK 0x00020000L
++#define DC_COMBOPHYPLLREGS0_VREG_CFG__vref_pwr_on_MASK 0x00040000L
++#define DC_COMBOPHYPLLREGS0_VREG_CFG__dpll_cfg_2_MASK 0x0FF00000L
++//DC_COMBOPHYPLLREGS0_OBSERVE0
++#define DC_COMBOPHYPLLREGS0_OBSERVE0__lock_det_tdc_steps__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS0_OBSERVE0__clear_sticky_lock__SHIFT 0x6
++#define DC_COMBOPHYPLLREGS0_OBSERVE0__lock_det_dis__SHIFT 0x8
++#define DC_COMBOPHYPLLREGS0_OBSERVE0__dco_cfg__SHIFT 0xa
++#define DC_COMBOPHYPLLREGS0_OBSERVE0__anaobs_sel__SHIFT 0x15
++#define DC_COMBOPHYPLLREGS0_OBSERVE0__lock_det_tdc_steps_MASK 0x0000001FL
++#define DC_COMBOPHYPLLREGS0_OBSERVE0__clear_sticky_lock_MASK 0x00000040L
++#define DC_COMBOPHYPLLREGS0_OBSERVE0__lock_det_dis_MASK 0x00000100L
++#define DC_COMBOPHYPLLREGS0_OBSERVE0__dco_cfg_MASK 0x0003FC00L
++#define DC_COMBOPHYPLLREGS0_OBSERVE0__anaobs_sel_MASK 0x00E00000L
++//DC_COMBOPHYPLLREGS0_OBSERVE1
++#define DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_sel__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_trig_sel__SHIFT 0x5
++#define DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_div__SHIFT 0xa
++#define DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_trig_div__SHIFT 0xd
++#define DC_COMBOPHYPLLREGS0_OBSERVE1__lock_timer__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_sel_MASK 0x0000000FL
++#define DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_trig_sel_MASK 0x000001E0L
++#define DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_div_MASK 0x00000C00L
++#define DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_trig_div_MASK 0x00006000L
++#define DC_COMBOPHYPLLREGS0_OBSERVE1__lock_timer_MASK 0x3FFF0000L
++//DC_COMBOPHYPLLREGS0_DFT_OUT
++#define DC_COMBOPHYPLLREGS0_DFT_OUT__dft_data__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS0_DFT_OUT__dft_data_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dcio_uniphy1_dispdec
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dc_combophycmregs1_dispdec
++//DC_COMBOPHYCMREGS1_COMMON_FUSE1
++#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_valid__SHIFT 0x0
++#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated0__SHIFT 0x1
++#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_ron_override_val__SHIFT 0x3
++#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated1__SHIFT 0x9
++#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0xa
++#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated2__SHIFT 0xc
++#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_rtt_override_val__SHIFT 0xd
++#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated3__SHIFT 0x13
++#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0x14
++#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_refresh_cal_en__SHIFT 0x16
++#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_spare__SHIFT 0x17
++#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_valid_MASK 0x00000001L
++#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated0_MASK 0x00000006L
++#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_ron_override_val_MASK 0x000001F8L
++#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated1_MASK 0x00000200L
++#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x00000C00L
++#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated2_MASK 0x00001000L
++#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_rtt_override_val_MASK 0x0007E000L
++#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated3_MASK 0x00080000L
++#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x00300000L
++#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_refresh_cal_en_MASK 0x00400000L
++#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_spare_MASK 0xFF800000L
++//DC_COMBOPHYCMREGS1_COMMON_FUSE2
++#define DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_valid__SHIFT 0x0
++#define DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_unpopulated__SHIFT 0x1
++#define DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_tx_fifo_ptr__SHIFT 0x9
++#define DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_spare__SHIFT 0xe
++#define DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_valid_MASK 0x00000001L
++#define DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_unpopulated_MASK 0x000001FEL
++#define DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_tx_fifo_ptr_MASK 0x00003E00L
++#define DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_spare_MASK 0xFFFFC000L
++//DC_COMBOPHYCMREGS1_COMMON_FUSE3
++#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_valid__SHIFT 0x0
++#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_unpopulated__SHIFT 0x1
++#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_ei_det_thresh_sel__SHIFT 0xa
++#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d
++#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_valid_MASK 0x00000001L
++#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_unpopulated_MASK 0x000003FEL
++#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_ei_det_thresh_sel_MASK 0x00001C00L
++#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_spare_MASK 0xE0000000L
++//DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM
++#define DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0
++#define DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8
++#define DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10
++#define DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18
++#define DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0x000000FFL
++#define DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0x0000FF00L
++#define DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0x00FF0000L
++#define DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xFF000000L
++//DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT
++#define DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0
++#define DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4
++#define DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT__vprot_en__SHIFT 0xb
++#define DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT__pgdelay_MASK 0x0000000FL
++#define DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT__pgmask_MASK 0x000003F0L
++#define DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT__vprot_en_MASK 0x00000800L
++//DC_COMBOPHYCMREGS1_COMMON_TXCNTRL
++#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT 0x0
++#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__clkgate_dis__SHIFT 0x5
++#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT 0x6
++#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT 0x9
++#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT 0xc
++#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__dual_dvi_mstr_en__SHIFT 0xf
++#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__dual_dvi_en__SHIFT 0x10
++#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK 0x0000001FL
++#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__clkgate_dis_MASK 0x00000020L
++#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK 0x000001C0L
++#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK 0x00000E00L
++#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK 0x00007000L
++#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__dual_dvi_mstr_en_MASK 0x00008000L
++#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__dual_dvi_en_MASK 0x00010000L
++//DC_COMBOPHYCMREGS1_COMMON_TMDP
++#define DC_COMBOPHYCMREGS1_COMMON_TMDP__tmdp_spare__SHIFT 0x0
++#define DC_COMBOPHYCMREGS1_COMMON_TMDP__tmdp_spare_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS
++#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_0_reset_l__SHIFT 0x0
++#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_1_reset_l__SHIFT 0x1
++#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_2_reset_l__SHIFT 0x2
++#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_3_reset_l__SHIFT 0x3
++#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_4_reset_l__SHIFT 0x4
++#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_5_reset_l__SHIFT 0x5
++#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_6_reset_l__SHIFT 0x6
++#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_7_reset_l__SHIFT 0x7
++#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_0_reset_l_MASK 0x00000001L
++#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_1_reset_l_MASK 0x00000002L
++#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_2_reset_l_MASK 0x00000004L
++#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_3_reset_l_MASK 0x00000008L
++#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_4_reset_l_MASK 0x00000010L
++#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_5_reset_l_MASK 0x00000020L
++#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_6_reset_l_MASK 0x00000040L
++#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_7_reset_l_MASK 0x00000080L
++//DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL
++#define DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT 0x0
++#define DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT 0x1
++#define DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT 0x15
++#define DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__zcalcode_override_MASK 0x00000001L
++#define DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK 0x0000003EL
++#define DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK 0x00200000L
++//DC_COMBOPHYCMREGS1_COMMON_DISP_RFU1
++#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU1__rfu_value1__SHIFT 0x0
++#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU1__rfu_value1_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS1_COMMON_DISP_RFU2
++#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU2__rfu_value2__SHIFT 0x0
++#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU2__rfu_value2_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS1_COMMON_DISP_RFU3
++#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU3__rfu_value3__SHIFT 0x0
++#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU3__rfu_value3_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS1_COMMON_DISP_RFU4
++#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU4__rfu_value4__SHIFT 0x0
++#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU4__rfu_value4_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS1_COMMON_DISP_RFU5
++#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU5__rfu_value5__SHIFT 0x0
++#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU5__rfu_value5_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS1_COMMON_DISP_RFU6
++#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU6__rfu_value6__SHIFT 0x0
++#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU6__rfu_value6_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS1_COMMON_DISP_RFU7
++#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU7__rfu_value7__SHIFT 0x0
++#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU7__rfu_value7_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dc_combophytxregs1_dispdec
++//DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0
++#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3
++#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT 0x8
++#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK 0x00000100L
++//DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0
++#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT 0x3
++#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT 0x5
++#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0__txmarg_sel_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0__deemph_sel_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0__tx_margin_en_MASK 0x00000020L
++//DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x1
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x3
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT 0x8
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT 0xa
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT 0xc
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT 0xd
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT 0xe
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT 0xf
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT 0x10
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT 0x14
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT 0x16
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x00000006L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0x000000E0L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK 0x00000300L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK 0x00000C00L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK 0x00001000L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK 0x00002000L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK 0x00004000L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK 0x00008000L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK 0x000F0000L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK 0x00100000L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK 0x00C00000L
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0__rfu_value0__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0__rfu_value0_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0__rfu_value1__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0__rfu_value1_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0__rfu_value2__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0__rfu_value2_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0__rfu_value3__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0__rfu_value3_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0__rfu_value4__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0__rfu_value4_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0__rfu_value5__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0__rfu_value5_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0__rfu_value6__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0__rfu_value6_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0__rfu_value7__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0__rfu_value7_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0__rfu_value8__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0__rfu_value8_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0__rfu_value9__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0__rfu_value9_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0__rfu_value10__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0__rfu_value10_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0__rfu_value11__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0__rfu_value11_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0__rfu_value12__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0__rfu_value12_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1
++#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3
++#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT 0x8
++#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK 0x00000100L
++//DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1
++#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT 0x3
++#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT 0x5
++#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1__txmarg_sel_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1__deemph_sel_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1__tx_margin_en_MASK 0x00000020L
++//DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x1
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x3
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT 0x8
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT 0xa
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT 0xc
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT 0xd
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT 0xe
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT 0xf
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT 0x10
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT 0x14
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT 0x16
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x00000006L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0x000000E0L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK 0x00000300L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK 0x00000C00L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK 0x00001000L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK 0x00002000L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK 0x00004000L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK 0x00008000L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK 0x000F0000L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK 0x00100000L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK 0x00C00000L
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1__rfu_value0__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1__rfu_value0_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1__rfu_value1__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1__rfu_value1_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1__rfu_value2__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1__rfu_value2_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1__rfu_value3__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1__rfu_value3_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1__rfu_value4__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1__rfu_value4_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1__rfu_value5__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1__rfu_value5_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1__rfu_value6__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1__rfu_value6_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1__rfu_value7__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1__rfu_value7_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1__rfu_value8__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1__rfu_value8_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1__rfu_value9__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1__rfu_value9_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1__rfu_value10__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1__rfu_value10_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1__rfu_value11__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1__rfu_value11_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1__rfu_value12__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1__rfu_value12_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2
++#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3
++#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT 0x8
++#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK 0x00000100L
++//DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2
++#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT 0x3
++#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT 0x5
++#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2__txmarg_sel_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2__deemph_sel_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2__tx_margin_en_MASK 0x00000020L
++//DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x1
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x3
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT 0x8
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT 0xa
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT 0xc
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT 0xd
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT 0xe
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT 0xf
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT 0x10
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT 0x14
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT 0x16
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x00000006L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0x000000E0L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK 0x00000300L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK 0x00000C00L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK 0x00001000L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK 0x00002000L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK 0x00004000L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK 0x00008000L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK 0x000F0000L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK 0x00100000L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK 0x00C00000L
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2__rfu_value0__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2__rfu_value0_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2__rfu_value1__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2__rfu_value1_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2__rfu_value2__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2__rfu_value2_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2__rfu_value3__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2__rfu_value3_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2__rfu_value4__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2__rfu_value4_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2__rfu_value5__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2__rfu_value5_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2__rfu_value6__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2__rfu_value6_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2__rfu_value7__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2__rfu_value7_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2__rfu_value8__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2__rfu_value8_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2__rfu_value9__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2__rfu_value9_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2__rfu_value10__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2__rfu_value10_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2__rfu_value11__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2__rfu_value11_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2__rfu_value12__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2__rfu_value12_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3
++#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3
++#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT 0x8
++#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK 0x00000100L
++//DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3
++#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT 0x3
++#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT 0x5
++#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3__txmarg_sel_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3__deemph_sel_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3__tx_margin_en_MASK 0x00000020L
++//DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x1
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x3
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT 0x8
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT 0xa
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT 0xc
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT 0xd
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT 0xe
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT 0xf
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT 0x10
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT 0x14
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT 0x16
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x00000006L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0x000000E0L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK 0x00000300L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK 0x00000C00L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK 0x00001000L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK 0x00002000L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK 0x00004000L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK 0x00008000L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK 0x000F0000L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK 0x00100000L
++#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK 0x00C00000L
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3__rfu_value0__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3__rfu_value0_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3__rfu_value1__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3__rfu_value1_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3__rfu_value2__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3__rfu_value2_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3__rfu_value3__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3__rfu_value3_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3__rfu_value4__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3__rfu_value4_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3__rfu_value5__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3__rfu_value5_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3__rfu_value6__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3__rfu_value6_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3__rfu_value7__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3__rfu_value7_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3__rfu_value8__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3__rfu_value8_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3__rfu_value9__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3__rfu_value9_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3__rfu_value10__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3__rfu_value10_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3__rfu_value11__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3__rfu_value11_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3__rfu_value12__SHIFT 0x0
++#define DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3__rfu_value12_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dc_combophypllregs1_dispdec
++//DC_COMBOPHYPLLREGS1_FREQ_CTRL0
++#define DC_COMBOPHYPLLREGS1_FREQ_CTRL0__fcw0_frac__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS1_FREQ_CTRL0__fcw0_int__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS1_FREQ_CTRL0__fcw0_frac_MASK 0x0000FFFFL
++#define DC_COMBOPHYPLLREGS1_FREQ_CTRL0__fcw0_int_MASK 0x01FF0000L
++//DC_COMBOPHYPLLREGS1_FREQ_CTRL1
++#define DC_COMBOPHYPLLREGS1_FREQ_CTRL1__fcw1_frac__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS1_FREQ_CTRL1__fcw1_int__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS1_FREQ_CTRL1__fcw1_frac_MASK 0x0000FFFFL
++#define DC_COMBOPHYPLLREGS1_FREQ_CTRL1__fcw1_int_MASK 0x01FF0000L
++//DC_COMBOPHYPLLREGS1_FREQ_CTRL2
++#define DC_COMBOPHYPLLREGS1_FREQ_CTRL2__fcw_denom__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS1_FREQ_CTRL2__fcw_slew_frac__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS1_FREQ_CTRL2__fcw_denom_MASK 0x0000FFFFL
++#define DC_COMBOPHYPLLREGS1_FREQ_CTRL2__fcw_slew_frac_MASK 0xFFFF0000L
++//DC_COMBOPHYPLLREGS1_FREQ_CTRL3
++#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__refclk_div__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__vco_pre_div__SHIFT 0x3
++#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__fracn_en__SHIFT 0x6
++#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__ssc_en__SHIFT 0x8
++#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__fcw_sel__SHIFT 0xa
++#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__freq_jump_en__SHIFT 0xc
++#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__tdc_resolution__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__dpll_cfg_1__SHIFT 0x18
++#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__refclk_div_MASK 0x00000003L
++#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__vco_pre_div_MASK 0x00000018L
++#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__fracn_en_MASK 0x00000040L
++#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__ssc_en_MASK 0x00000100L
++#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__fcw_sel_MASK 0x00000400L
++#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__freq_jump_en_MASK 0x00001000L
++#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__tdc_resolution_MASK 0x00FF0000L
++#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__dpll_cfg_1_MASK 0xFF000000L
++//DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE
++#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gi_coarse_mant__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gi_coarse_exp__SHIFT 0x2
++#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gp_coarse_mant__SHIFT 0x7
++#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gp_coarse_exp__SHIFT 0xc
++#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__nctl_coarse_res__SHIFT 0x11
++#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT 0x18
++#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gi_coarse_mant_MASK 0x00000003L
++#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gi_coarse_exp_MASK 0x0000003CL
++#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gp_coarse_mant_MASK 0x00000780L
++#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gp_coarse_exp_MASK 0x0000F000L
++#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__nctl_coarse_res_MASK 0x007E0000L
++#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__nctl_coarse_frac_res_MASK 0x03000000L
++//DC_COMBOPHYPLLREGS1_BW_CTRL_FINE
++#define DC_COMBOPHYPLLREGS1_BW_CTRL_FINE__dpll_cfg_3__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS1_BW_CTRL_FINE__dpll_cfg_3_MASK 0x000003FFL
++//DC_COMBOPHYPLLREGS1_CAL_CTRL
++#define DC_COMBOPHYPLLREGS1_CAL_CTRL__bypass_freq_lock__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS1_CAL_CTRL__tdc_cal_en__SHIFT 0x1
++#define DC_COMBOPHYPLLREGS1_CAL_CTRL__tdc_cal_ctrl__SHIFT 0x3
++#define DC_COMBOPHYPLLREGS1_CAL_CTRL__meas_win_sel__SHIFT 0x9
++#define DC_COMBOPHYPLLREGS1_CAL_CTRL__kdco_cal_dis__SHIFT 0xb
++#define DC_COMBOPHYPLLREGS1_CAL_CTRL__kdco_ratio__SHIFT 0xd
++#define DC_COMBOPHYPLLREGS1_CAL_CTRL__kdco_incr_cal_dis__SHIFT 0x16
++#define DC_COMBOPHYPLLREGS1_CAL_CTRL__nctl_adj_dis__SHIFT 0x17
++#define DC_COMBOPHYPLLREGS1_CAL_CTRL__refclk_rate__SHIFT 0x18
++#define DC_COMBOPHYPLLREGS1_CAL_CTRL__bypass_freq_lock_MASK 0x00000001L
++#define DC_COMBOPHYPLLREGS1_CAL_CTRL__tdc_cal_en_MASK 0x00000002L
++#define DC_COMBOPHYPLLREGS1_CAL_CTRL__tdc_cal_ctrl_MASK 0x000001F8L
++#define DC_COMBOPHYPLLREGS1_CAL_CTRL__meas_win_sel_MASK 0x00000600L
++#define DC_COMBOPHYPLLREGS1_CAL_CTRL__kdco_cal_dis_MASK 0x00000800L
++#define DC_COMBOPHYPLLREGS1_CAL_CTRL__kdco_ratio_MASK 0x001FE000L
++#define DC_COMBOPHYPLLREGS1_CAL_CTRL__kdco_incr_cal_dis_MASK 0x00400000L
++#define DC_COMBOPHYPLLREGS1_CAL_CTRL__nctl_adj_dis_MASK 0x00800000L
++#define DC_COMBOPHYPLLREGS1_CAL_CTRL__refclk_rate_MASK 0xFF000000L
++//DC_COMBOPHYPLLREGS1_LOOP_CTRL
++#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__fbdiv_mask_en__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__fb_slip_dis__SHIFT 0x2
++#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__clk_tdc_sel__SHIFT 0x4
++#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__clk_nctl_sel__SHIFT 0x7
++#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__sig_del_patt_sel__SHIFT 0xa
++#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__nctl_sig_del_dis__SHIFT 0xc
++#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__fbclk_track_refclk__SHIFT 0xe
++#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__prbs_en__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__tdc_clk_gate_en__SHIFT 0x12
++#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__phase_offset__SHIFT 0x14
++#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__fbdiv_mask_en_MASK 0x00000001L
++#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__fb_slip_dis_MASK 0x00000004L
++#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__clk_tdc_sel_MASK 0x00000030L
++#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__clk_nctl_sel_MASK 0x00000180L
++#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__sig_del_patt_sel_MASK 0x00000400L
++#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__nctl_sig_del_dis_MASK 0x00001000L
++#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__fbclk_track_refclk_MASK 0x00004000L
++#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__prbs_en_MASK 0x00010000L
++#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__tdc_clk_gate_en_MASK 0x00040000L
++#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__phase_offset_MASK 0x07F00000L
++//DC_COMBOPHYPLLREGS1_VREG_CFG
++#define DC_COMBOPHYPLLREGS1_VREG_CFG__bleeder_ac__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS1_VREG_CFG__bleeder_en__SHIFT 0x1
++#define DC_COMBOPHYPLLREGS1_VREG_CFG__is_1p2__SHIFT 0x2
++#define DC_COMBOPHYPLLREGS1_VREG_CFG__reg_obs_sel__SHIFT 0x3
++#define DC_COMBOPHYPLLREGS1_VREG_CFG__reg_on_mode__SHIFT 0x5
++#define DC_COMBOPHYPLLREGS1_VREG_CFG__rlad_tap_sel__SHIFT 0x7
++#define DC_COMBOPHYPLLREGS1_VREG_CFG__reg_off_hi__SHIFT 0xb
++#define DC_COMBOPHYPLLREGS1_VREG_CFG__reg_off_lo__SHIFT 0xc
++#define DC_COMBOPHYPLLREGS1_VREG_CFG__scale_driver__SHIFT 0xd
++#define DC_COMBOPHYPLLREGS1_VREG_CFG__sel_bump__SHIFT 0xf
++#define DC_COMBOPHYPLLREGS1_VREG_CFG__sel_rladder_x__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS1_VREG_CFG__short_rc_filt_x__SHIFT 0x11
++#define DC_COMBOPHYPLLREGS1_VREG_CFG__vref_pwr_on__SHIFT 0x12
++#define DC_COMBOPHYPLLREGS1_VREG_CFG__dpll_cfg_2__SHIFT 0x14
++#define DC_COMBOPHYPLLREGS1_VREG_CFG__bleeder_ac_MASK 0x00000001L
++#define DC_COMBOPHYPLLREGS1_VREG_CFG__bleeder_en_MASK 0x00000002L
++#define DC_COMBOPHYPLLREGS1_VREG_CFG__is_1p2_MASK 0x00000004L
++#define DC_COMBOPHYPLLREGS1_VREG_CFG__reg_obs_sel_MASK 0x00000018L
++#define DC_COMBOPHYPLLREGS1_VREG_CFG__reg_on_mode_MASK 0x00000060L
++#define DC_COMBOPHYPLLREGS1_VREG_CFG__rlad_tap_sel_MASK 0x00000780L
++#define DC_COMBOPHYPLLREGS1_VREG_CFG__reg_off_hi_MASK 0x00000800L
++#define DC_COMBOPHYPLLREGS1_VREG_CFG__reg_off_lo_MASK 0x00001000L
++#define DC_COMBOPHYPLLREGS1_VREG_CFG__scale_driver_MASK 0x00006000L
++#define DC_COMBOPHYPLLREGS1_VREG_CFG__sel_bump_MASK 0x00008000L
++#define DC_COMBOPHYPLLREGS1_VREG_CFG__sel_rladder_x_MASK 0x00010000L
++#define DC_COMBOPHYPLLREGS1_VREG_CFG__short_rc_filt_x_MASK 0x00020000L
++#define DC_COMBOPHYPLLREGS1_VREG_CFG__vref_pwr_on_MASK 0x00040000L
++#define DC_COMBOPHYPLLREGS1_VREG_CFG__dpll_cfg_2_MASK 0x0FF00000L
++//DC_COMBOPHYPLLREGS1_OBSERVE0
++#define DC_COMBOPHYPLLREGS1_OBSERVE0__lock_det_tdc_steps__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS1_OBSERVE0__clear_sticky_lock__SHIFT 0x6
++#define DC_COMBOPHYPLLREGS1_OBSERVE0__lock_det_dis__SHIFT 0x8
++#define DC_COMBOPHYPLLREGS1_OBSERVE0__dco_cfg__SHIFT 0xa
++#define DC_COMBOPHYPLLREGS1_OBSERVE0__anaobs_sel__SHIFT 0x15
++#define DC_COMBOPHYPLLREGS1_OBSERVE0__lock_det_tdc_steps_MASK 0x0000001FL
++#define DC_COMBOPHYPLLREGS1_OBSERVE0__clear_sticky_lock_MASK 0x00000040L
++#define DC_COMBOPHYPLLREGS1_OBSERVE0__lock_det_dis_MASK 0x00000100L
++#define DC_COMBOPHYPLLREGS1_OBSERVE0__dco_cfg_MASK 0x0003FC00L
++#define DC_COMBOPHYPLLREGS1_OBSERVE0__anaobs_sel_MASK 0x00E00000L
++//DC_COMBOPHYPLLREGS1_OBSERVE1
++#define DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_sel__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_trig_sel__SHIFT 0x5
++#define DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_div__SHIFT 0xa
++#define DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_trig_div__SHIFT 0xd
++#define DC_COMBOPHYPLLREGS1_OBSERVE1__lock_timer__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_sel_MASK 0x0000000FL
++#define DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_trig_sel_MASK 0x000001E0L
++#define DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_div_MASK 0x00000C00L
++#define DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_trig_div_MASK 0x00006000L
++#define DC_COMBOPHYPLLREGS1_OBSERVE1__lock_timer_MASK 0x3FFF0000L
++//DC_COMBOPHYPLLREGS1_DFT_OUT
++#define DC_COMBOPHYPLLREGS1_DFT_OUT__dft_data__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS1_DFT_OUT__dft_data_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dcio_uniphy2_dispdec
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dc_combophycmregs2_dispdec
++//DC_COMBOPHYCMREGS2_COMMON_FUSE1
++#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_valid__SHIFT 0x0
++#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated0__SHIFT 0x1
++#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_ron_override_val__SHIFT 0x3
++#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated1__SHIFT 0x9
++#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0xa
++#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated2__SHIFT 0xc
++#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_rtt_override_val__SHIFT 0xd
++#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated3__SHIFT 0x13
++#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0x14
++#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_refresh_cal_en__SHIFT 0x16
++#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_spare__SHIFT 0x17
++#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_valid_MASK 0x00000001L
++#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated0_MASK 0x00000006L
++#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_ron_override_val_MASK 0x000001F8L
++#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated1_MASK 0x00000200L
++#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x00000C00L
++#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated2_MASK 0x00001000L
++#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_rtt_override_val_MASK 0x0007E000L
++#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated3_MASK 0x00080000L
++#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x00300000L
++#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_refresh_cal_en_MASK 0x00400000L
++#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_spare_MASK 0xFF800000L
++//DC_COMBOPHYCMREGS2_COMMON_FUSE2
++#define DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_valid__SHIFT 0x0
++#define DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_unpopulated__SHIFT 0x1
++#define DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_tx_fifo_ptr__SHIFT 0x9
++#define DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_spare__SHIFT 0xe
++#define DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_valid_MASK 0x00000001L
++#define DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_unpopulated_MASK 0x000001FEL
++#define DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_tx_fifo_ptr_MASK 0x00003E00L
++#define DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_spare_MASK 0xFFFFC000L
++//DC_COMBOPHYCMREGS2_COMMON_FUSE3
++#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_valid__SHIFT 0x0
++#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_unpopulated__SHIFT 0x1
++#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_ei_det_thresh_sel__SHIFT 0xa
++#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d
++#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_valid_MASK 0x00000001L
++#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_unpopulated_MASK 0x000003FEL
++#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_ei_det_thresh_sel_MASK 0x00001C00L
++#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_spare_MASK 0xE0000000L
++//DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM
++#define DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0
++#define DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8
++#define DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10
++#define DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18
++#define DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0x000000FFL
++#define DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0x0000FF00L
++#define DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0x00FF0000L
++#define DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xFF000000L
++//DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT
++#define DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0
++#define DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4
++#define DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT__vprot_en__SHIFT 0xb
++#define DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT__pgdelay_MASK 0x0000000FL
++#define DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT__pgmask_MASK 0x000003F0L
++#define DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT__vprot_en_MASK 0x00000800L
++//DC_COMBOPHYCMREGS2_COMMON_TXCNTRL
++#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT 0x0
++#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__clkgate_dis__SHIFT 0x5
++#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT 0x6
++#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT 0x9
++#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT 0xc
++#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__dual_dvi_mstr_en__SHIFT 0xf
++#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__dual_dvi_en__SHIFT 0x10
++#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK 0x0000001FL
++#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__clkgate_dis_MASK 0x00000020L
++#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK 0x000001C0L
++#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK 0x00000E00L
++#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK 0x00007000L
++#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__dual_dvi_mstr_en_MASK 0x00008000L
++#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__dual_dvi_en_MASK 0x00010000L
++//DC_COMBOPHYCMREGS2_COMMON_TMDP
++#define DC_COMBOPHYCMREGS2_COMMON_TMDP__tmdp_spare__SHIFT 0x0
++#define DC_COMBOPHYCMREGS2_COMMON_TMDP__tmdp_spare_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS
++#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_0_reset_l__SHIFT 0x0
++#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_1_reset_l__SHIFT 0x1
++#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_2_reset_l__SHIFT 0x2
++#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_3_reset_l__SHIFT 0x3
++#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_4_reset_l__SHIFT 0x4
++#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_5_reset_l__SHIFT 0x5
++#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_6_reset_l__SHIFT 0x6
++#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_7_reset_l__SHIFT 0x7
++#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_0_reset_l_MASK 0x00000001L
++#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_1_reset_l_MASK 0x00000002L
++#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_2_reset_l_MASK 0x00000004L
++#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_3_reset_l_MASK 0x00000008L
++#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_4_reset_l_MASK 0x00000010L
++#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_5_reset_l_MASK 0x00000020L
++#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_6_reset_l_MASK 0x00000040L
++#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_7_reset_l_MASK 0x00000080L
++//DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL
++#define DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT 0x0
++#define DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT 0x1
++#define DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT 0x15
++#define DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__zcalcode_override_MASK 0x00000001L
++#define DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK 0x0000003EL
++#define DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK 0x00200000L
++//DC_COMBOPHYCMREGS2_COMMON_DISP_RFU1
++#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU1__rfu_value1__SHIFT 0x0
++#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU1__rfu_value1_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS2_COMMON_DISP_RFU2
++#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU2__rfu_value2__SHIFT 0x0
++#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU2__rfu_value2_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS2_COMMON_DISP_RFU3
++#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU3__rfu_value3__SHIFT 0x0
++#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU3__rfu_value3_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS2_COMMON_DISP_RFU4
++#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU4__rfu_value4__SHIFT 0x0
++#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU4__rfu_value4_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS2_COMMON_DISP_RFU5
++#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU5__rfu_value5__SHIFT 0x0
++#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU5__rfu_value5_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS2_COMMON_DISP_RFU6
++#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU6__rfu_value6__SHIFT 0x0
++#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU6__rfu_value6_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS2_COMMON_DISP_RFU7
++#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU7__rfu_value7__SHIFT 0x0
++#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU7__rfu_value7_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dc_combophytxregs2_dispdec
++//DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0
++#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3
++#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT 0x8
++#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK 0x00000100L
++//DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0
++#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT 0x3
++#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT 0x5
++#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0__txmarg_sel_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0__deemph_sel_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0__tx_margin_en_MASK 0x00000020L
++//DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x1
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x3
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT 0x8
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT 0xa
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT 0xc
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT 0xd
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT 0xe
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT 0xf
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT 0x10
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT 0x14
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT 0x16
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x00000006L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0x000000E0L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK 0x00000300L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK 0x00000C00L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK 0x00001000L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK 0x00002000L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK 0x00004000L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK 0x00008000L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK 0x000F0000L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK 0x00100000L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK 0x00C00000L
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0__rfu_value0__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0__rfu_value0_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0__rfu_value1__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0__rfu_value1_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0__rfu_value2__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0__rfu_value2_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0__rfu_value3__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0__rfu_value3_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0__rfu_value4__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0__rfu_value4_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0__rfu_value5__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0__rfu_value5_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0__rfu_value6__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0__rfu_value6_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0__rfu_value7__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0__rfu_value7_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0__rfu_value8__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0__rfu_value8_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0__rfu_value9__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0__rfu_value9_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0__rfu_value10__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0__rfu_value10_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0__rfu_value11__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0__rfu_value11_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0__rfu_value12__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0__rfu_value12_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1
++#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3
++#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT 0x8
++#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK 0x00000100L
++//DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1
++#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT 0x3
++#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT 0x5
++#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1__txmarg_sel_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1__deemph_sel_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1__tx_margin_en_MASK 0x00000020L
++//DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x1
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x3
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT 0x8
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT 0xa
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT 0xc
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT 0xd
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT 0xe
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT 0xf
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT 0x10
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT 0x14
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT 0x16
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x00000006L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0x000000E0L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK 0x00000300L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK 0x00000C00L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK 0x00001000L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK 0x00002000L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK 0x00004000L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK 0x00008000L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK 0x000F0000L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK 0x00100000L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK 0x00C00000L
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1__rfu_value0__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1__rfu_value0_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1__rfu_value1__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1__rfu_value1_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1__rfu_value2__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1__rfu_value2_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1__rfu_value3__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1__rfu_value3_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1__rfu_value4__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1__rfu_value4_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1__rfu_value5__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1__rfu_value5_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1__rfu_value6__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1__rfu_value6_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1__rfu_value7__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1__rfu_value7_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1__rfu_value8__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1__rfu_value8_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1__rfu_value9__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1__rfu_value9_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1__rfu_value10__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1__rfu_value10_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1__rfu_value11__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1__rfu_value11_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1__rfu_value12__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1__rfu_value12_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2
++#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3
++#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT 0x8
++#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK 0x00000100L
++//DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2
++#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT 0x3
++#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT 0x5
++#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2__txmarg_sel_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2__deemph_sel_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2__tx_margin_en_MASK 0x00000020L
++//DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x1
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x3
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT 0x8
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT 0xa
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT 0xc
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT 0xd
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT 0xe
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT 0xf
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT 0x10
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT 0x14
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT 0x16
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x00000006L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0x000000E0L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK 0x00000300L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK 0x00000C00L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK 0x00001000L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK 0x00002000L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK 0x00004000L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK 0x00008000L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK 0x000F0000L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK 0x00100000L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK 0x00C00000L
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2__rfu_value0__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2__rfu_value0_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2__rfu_value1__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2__rfu_value1_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2__rfu_value2__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2__rfu_value2_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2__rfu_value3__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2__rfu_value3_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2__rfu_value4__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2__rfu_value4_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2__rfu_value5__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2__rfu_value5_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2__rfu_value6__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2__rfu_value6_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2__rfu_value7__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2__rfu_value7_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2__rfu_value8__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2__rfu_value8_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2__rfu_value9__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2__rfu_value9_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2__rfu_value10__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2__rfu_value10_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2__rfu_value11__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2__rfu_value11_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2__rfu_value12__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2__rfu_value12_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3
++#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3
++#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT 0x8
++#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK 0x00000100L
++//DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3
++#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT 0x3
++#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT 0x5
++#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3__txmarg_sel_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3__deemph_sel_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3__tx_margin_en_MASK 0x00000020L
++//DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x1
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x3
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT 0x8
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT 0xa
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT 0xc
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT 0xd
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT 0xe
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT 0xf
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT 0x10
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT 0x14
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT 0x16
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x00000006L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0x000000E0L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK 0x00000300L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK 0x00000C00L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK 0x00001000L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK 0x00002000L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK 0x00004000L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK 0x00008000L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK 0x000F0000L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK 0x00100000L
++#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK 0x00C00000L
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3__rfu_value0__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3__rfu_value0_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3__rfu_value1__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3__rfu_value1_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3__rfu_value2__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3__rfu_value2_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3__rfu_value3__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3__rfu_value3_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3__rfu_value4__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3__rfu_value4_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3__rfu_value5__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3__rfu_value5_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3__rfu_value6__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3__rfu_value6_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3__rfu_value7__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3__rfu_value7_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3__rfu_value8__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3__rfu_value8_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3__rfu_value9__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3__rfu_value9_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3__rfu_value10__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3__rfu_value10_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3__rfu_value11__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3__rfu_value11_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3__rfu_value12__SHIFT 0x0
++#define DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3__rfu_value12_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dc_combophypllregs2_dispdec
++//DC_COMBOPHYPLLREGS2_FREQ_CTRL0
++#define DC_COMBOPHYPLLREGS2_FREQ_CTRL0__fcw0_frac__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS2_FREQ_CTRL0__fcw0_int__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS2_FREQ_CTRL0__fcw0_frac_MASK 0x0000FFFFL
++#define DC_COMBOPHYPLLREGS2_FREQ_CTRL0__fcw0_int_MASK 0x01FF0000L
++//DC_COMBOPHYPLLREGS2_FREQ_CTRL1
++#define DC_COMBOPHYPLLREGS2_FREQ_CTRL1__fcw1_frac__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS2_FREQ_CTRL1__fcw1_int__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS2_FREQ_CTRL1__fcw1_frac_MASK 0x0000FFFFL
++#define DC_COMBOPHYPLLREGS2_FREQ_CTRL1__fcw1_int_MASK 0x01FF0000L
++//DC_COMBOPHYPLLREGS2_FREQ_CTRL2
++#define DC_COMBOPHYPLLREGS2_FREQ_CTRL2__fcw_denom__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS2_FREQ_CTRL2__fcw_slew_frac__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS2_FREQ_CTRL2__fcw_denom_MASK 0x0000FFFFL
++#define DC_COMBOPHYPLLREGS2_FREQ_CTRL2__fcw_slew_frac_MASK 0xFFFF0000L
++//DC_COMBOPHYPLLREGS2_FREQ_CTRL3
++#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__refclk_div__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__vco_pre_div__SHIFT 0x3
++#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__fracn_en__SHIFT 0x6
++#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__ssc_en__SHIFT 0x8
++#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__fcw_sel__SHIFT 0xa
++#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__freq_jump_en__SHIFT 0xc
++#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__tdc_resolution__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__dpll_cfg_1__SHIFT 0x18
++#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__refclk_div_MASK 0x00000003L
++#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__vco_pre_div_MASK 0x00000018L
++#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__fracn_en_MASK 0x00000040L
++#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__ssc_en_MASK 0x00000100L
++#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__fcw_sel_MASK 0x00000400L
++#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__freq_jump_en_MASK 0x00001000L
++#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__tdc_resolution_MASK 0x00FF0000L
++#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__dpll_cfg_1_MASK 0xFF000000L
++//DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE
++#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gi_coarse_mant__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gi_coarse_exp__SHIFT 0x2
++#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gp_coarse_mant__SHIFT 0x7
++#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gp_coarse_exp__SHIFT 0xc
++#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__nctl_coarse_res__SHIFT 0x11
++#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT 0x18
++#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gi_coarse_mant_MASK 0x00000003L
++#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gi_coarse_exp_MASK 0x0000003CL
++#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gp_coarse_mant_MASK 0x00000780L
++#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gp_coarse_exp_MASK 0x0000F000L
++#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__nctl_coarse_res_MASK 0x007E0000L
++#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__nctl_coarse_frac_res_MASK 0x03000000L
++//DC_COMBOPHYPLLREGS2_BW_CTRL_FINE
++#define DC_COMBOPHYPLLREGS2_BW_CTRL_FINE__dpll_cfg_3__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS2_BW_CTRL_FINE__dpll_cfg_3_MASK 0x000003FFL
++//DC_COMBOPHYPLLREGS2_CAL_CTRL
++#define DC_COMBOPHYPLLREGS2_CAL_CTRL__bypass_freq_lock__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS2_CAL_CTRL__tdc_cal_en__SHIFT 0x1
++#define DC_COMBOPHYPLLREGS2_CAL_CTRL__tdc_cal_ctrl__SHIFT 0x3
++#define DC_COMBOPHYPLLREGS2_CAL_CTRL__meas_win_sel__SHIFT 0x9
++#define DC_COMBOPHYPLLREGS2_CAL_CTRL__kdco_cal_dis__SHIFT 0xb
++#define DC_COMBOPHYPLLREGS2_CAL_CTRL__kdco_ratio__SHIFT 0xd
++#define DC_COMBOPHYPLLREGS2_CAL_CTRL__kdco_incr_cal_dis__SHIFT 0x16
++#define DC_COMBOPHYPLLREGS2_CAL_CTRL__nctl_adj_dis__SHIFT 0x17
++#define DC_COMBOPHYPLLREGS2_CAL_CTRL__refclk_rate__SHIFT 0x18
++#define DC_COMBOPHYPLLREGS2_CAL_CTRL__bypass_freq_lock_MASK 0x00000001L
++#define DC_COMBOPHYPLLREGS2_CAL_CTRL__tdc_cal_en_MASK 0x00000002L
++#define DC_COMBOPHYPLLREGS2_CAL_CTRL__tdc_cal_ctrl_MASK 0x000001F8L
++#define DC_COMBOPHYPLLREGS2_CAL_CTRL__meas_win_sel_MASK 0x00000600L
++#define DC_COMBOPHYPLLREGS2_CAL_CTRL__kdco_cal_dis_MASK 0x00000800L
++#define DC_COMBOPHYPLLREGS2_CAL_CTRL__kdco_ratio_MASK 0x001FE000L
++#define DC_COMBOPHYPLLREGS2_CAL_CTRL__kdco_incr_cal_dis_MASK 0x00400000L
++#define DC_COMBOPHYPLLREGS2_CAL_CTRL__nctl_adj_dis_MASK 0x00800000L
++#define DC_COMBOPHYPLLREGS2_CAL_CTRL__refclk_rate_MASK 0xFF000000L
++//DC_COMBOPHYPLLREGS2_LOOP_CTRL
++#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__fbdiv_mask_en__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__fb_slip_dis__SHIFT 0x2
++#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__clk_tdc_sel__SHIFT 0x4
++#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__clk_nctl_sel__SHIFT 0x7
++#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__sig_del_patt_sel__SHIFT 0xa
++#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__nctl_sig_del_dis__SHIFT 0xc
++#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__fbclk_track_refclk__SHIFT 0xe
++#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__prbs_en__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__tdc_clk_gate_en__SHIFT 0x12
++#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__phase_offset__SHIFT 0x14
++#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__fbdiv_mask_en_MASK 0x00000001L
++#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__fb_slip_dis_MASK 0x00000004L
++#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__clk_tdc_sel_MASK 0x00000030L
++#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__clk_nctl_sel_MASK 0x00000180L
++#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__sig_del_patt_sel_MASK 0x00000400L
++#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__nctl_sig_del_dis_MASK 0x00001000L
++#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__fbclk_track_refclk_MASK 0x00004000L
++#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__prbs_en_MASK 0x00010000L
++#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__tdc_clk_gate_en_MASK 0x00040000L
++#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__phase_offset_MASK 0x07F00000L
++//DC_COMBOPHYPLLREGS2_VREG_CFG
++#define DC_COMBOPHYPLLREGS2_VREG_CFG__bleeder_ac__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS2_VREG_CFG__bleeder_en__SHIFT 0x1
++#define DC_COMBOPHYPLLREGS2_VREG_CFG__is_1p2__SHIFT 0x2
++#define DC_COMBOPHYPLLREGS2_VREG_CFG__reg_obs_sel__SHIFT 0x3
++#define DC_COMBOPHYPLLREGS2_VREG_CFG__reg_on_mode__SHIFT 0x5
++#define DC_COMBOPHYPLLREGS2_VREG_CFG__rlad_tap_sel__SHIFT 0x7
++#define DC_COMBOPHYPLLREGS2_VREG_CFG__reg_off_hi__SHIFT 0xb
++#define DC_COMBOPHYPLLREGS2_VREG_CFG__reg_off_lo__SHIFT 0xc
++#define DC_COMBOPHYPLLREGS2_VREG_CFG__scale_driver__SHIFT 0xd
++#define DC_COMBOPHYPLLREGS2_VREG_CFG__sel_bump__SHIFT 0xf
++#define DC_COMBOPHYPLLREGS2_VREG_CFG__sel_rladder_x__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS2_VREG_CFG__short_rc_filt_x__SHIFT 0x11
++#define DC_COMBOPHYPLLREGS2_VREG_CFG__vref_pwr_on__SHIFT 0x12
++#define DC_COMBOPHYPLLREGS2_VREG_CFG__dpll_cfg_2__SHIFT 0x14
++#define DC_COMBOPHYPLLREGS2_VREG_CFG__bleeder_ac_MASK 0x00000001L
++#define DC_COMBOPHYPLLREGS2_VREG_CFG__bleeder_en_MASK 0x00000002L
++#define DC_COMBOPHYPLLREGS2_VREG_CFG__is_1p2_MASK 0x00000004L
++#define DC_COMBOPHYPLLREGS2_VREG_CFG__reg_obs_sel_MASK 0x00000018L
++#define DC_COMBOPHYPLLREGS2_VREG_CFG__reg_on_mode_MASK 0x00000060L
++#define DC_COMBOPHYPLLREGS2_VREG_CFG__rlad_tap_sel_MASK 0x00000780L
++#define DC_COMBOPHYPLLREGS2_VREG_CFG__reg_off_hi_MASK 0x00000800L
++#define DC_COMBOPHYPLLREGS2_VREG_CFG__reg_off_lo_MASK 0x00001000L
++#define DC_COMBOPHYPLLREGS2_VREG_CFG__scale_driver_MASK 0x00006000L
++#define DC_COMBOPHYPLLREGS2_VREG_CFG__sel_bump_MASK 0x00008000L
++#define DC_COMBOPHYPLLREGS2_VREG_CFG__sel_rladder_x_MASK 0x00010000L
++#define DC_COMBOPHYPLLREGS2_VREG_CFG__short_rc_filt_x_MASK 0x00020000L
++#define DC_COMBOPHYPLLREGS2_VREG_CFG__vref_pwr_on_MASK 0x00040000L
++#define DC_COMBOPHYPLLREGS2_VREG_CFG__dpll_cfg_2_MASK 0x0FF00000L
++//DC_COMBOPHYPLLREGS2_OBSERVE0
++#define DC_COMBOPHYPLLREGS2_OBSERVE0__lock_det_tdc_steps__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS2_OBSERVE0__clear_sticky_lock__SHIFT 0x6
++#define DC_COMBOPHYPLLREGS2_OBSERVE0__lock_det_dis__SHIFT 0x8
++#define DC_COMBOPHYPLLREGS2_OBSERVE0__dco_cfg__SHIFT 0xa
++#define DC_COMBOPHYPLLREGS2_OBSERVE0__anaobs_sel__SHIFT 0x15
++#define DC_COMBOPHYPLLREGS2_OBSERVE0__lock_det_tdc_steps_MASK 0x0000001FL
++#define DC_COMBOPHYPLLREGS2_OBSERVE0__clear_sticky_lock_MASK 0x00000040L
++#define DC_COMBOPHYPLLREGS2_OBSERVE0__lock_det_dis_MASK 0x00000100L
++#define DC_COMBOPHYPLLREGS2_OBSERVE0__dco_cfg_MASK 0x0003FC00L
++#define DC_COMBOPHYPLLREGS2_OBSERVE0__anaobs_sel_MASK 0x00E00000L
++//DC_COMBOPHYPLLREGS2_OBSERVE1
++#define DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_sel__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_trig_sel__SHIFT 0x5
++#define DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_div__SHIFT 0xa
++#define DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_trig_div__SHIFT 0xd
++#define DC_COMBOPHYPLLREGS2_OBSERVE1__lock_timer__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_sel_MASK 0x0000000FL
++#define DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_trig_sel_MASK 0x000001E0L
++#define DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_div_MASK 0x00000C00L
++#define DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_trig_div_MASK 0x00006000L
++#define DC_COMBOPHYPLLREGS2_OBSERVE1__lock_timer_MASK 0x3FFF0000L
++//DC_COMBOPHYPLLREGS2_DFT_OUT
++#define DC_COMBOPHYPLLREGS2_DFT_OUT__dft_data__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS2_DFT_OUT__dft_data_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dcio_uniphy3_dispdec
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dc_combophycmregs3_dispdec
++//DC_COMBOPHYCMREGS3_COMMON_FUSE1
++#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_valid__SHIFT 0x0
++#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated0__SHIFT 0x1
++#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_ron_override_val__SHIFT 0x3
++#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated1__SHIFT 0x9
++#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0xa
++#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated2__SHIFT 0xc
++#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_rtt_override_val__SHIFT 0xd
++#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated3__SHIFT 0x13
++#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0x14
++#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_refresh_cal_en__SHIFT 0x16
++#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_spare__SHIFT 0x17
++#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_valid_MASK 0x00000001L
++#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated0_MASK 0x00000006L
++#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_ron_override_val_MASK 0x000001F8L
++#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated1_MASK 0x00000200L
++#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x00000C00L
++#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated2_MASK 0x00001000L
++#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_rtt_override_val_MASK 0x0007E000L
++#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated3_MASK 0x00080000L
++#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x00300000L
++#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_refresh_cal_en_MASK 0x00400000L
++#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_spare_MASK 0xFF800000L
++//DC_COMBOPHYCMREGS3_COMMON_FUSE2
++#define DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_valid__SHIFT 0x0
++#define DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_unpopulated__SHIFT 0x1
++#define DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_tx_fifo_ptr__SHIFT 0x9
++#define DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_spare__SHIFT 0xe
++#define DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_valid_MASK 0x00000001L
++#define DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_unpopulated_MASK 0x000001FEL
++#define DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_tx_fifo_ptr_MASK 0x00003E00L
++#define DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_spare_MASK 0xFFFFC000L
++//DC_COMBOPHYCMREGS3_COMMON_FUSE3
++#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_valid__SHIFT 0x0
++#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_unpopulated__SHIFT 0x1
++#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_ei_det_thresh_sel__SHIFT 0xa
++#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d
++#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_valid_MASK 0x00000001L
++#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_unpopulated_MASK 0x000003FEL
++#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_ei_det_thresh_sel_MASK 0x00001C00L
++#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_spare_MASK 0xE0000000L
++//DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM
++#define DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0
++#define DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8
++#define DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10
++#define DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18
++#define DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0x000000FFL
++#define DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0x0000FF00L
++#define DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0x00FF0000L
++#define DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xFF000000L
++//DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT
++#define DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0
++#define DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4
++#define DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT__vprot_en__SHIFT 0xb
++#define DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT__pgdelay_MASK 0x0000000FL
++#define DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT__pgmask_MASK 0x000003F0L
++#define DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT__vprot_en_MASK 0x00000800L
++//DC_COMBOPHYCMREGS3_COMMON_TXCNTRL
++#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT 0x0
++#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__clkgate_dis__SHIFT 0x5
++#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT 0x6
++#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT 0x9
++#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT 0xc
++#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__dual_dvi_mstr_en__SHIFT 0xf
++#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__dual_dvi_en__SHIFT 0x10
++#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK 0x0000001FL
++#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__clkgate_dis_MASK 0x00000020L
++#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK 0x000001C0L
++#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK 0x00000E00L
++#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK 0x00007000L
++#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__dual_dvi_mstr_en_MASK 0x00008000L
++#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__dual_dvi_en_MASK 0x00010000L
++//DC_COMBOPHYCMREGS3_COMMON_TMDP
++#define DC_COMBOPHYCMREGS3_COMMON_TMDP__tmdp_spare__SHIFT 0x0
++#define DC_COMBOPHYCMREGS3_COMMON_TMDP__tmdp_spare_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS
++#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_0_reset_l__SHIFT 0x0
++#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_1_reset_l__SHIFT 0x1
++#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_2_reset_l__SHIFT 0x2
++#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_3_reset_l__SHIFT 0x3
++#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_4_reset_l__SHIFT 0x4
++#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_5_reset_l__SHIFT 0x5
++#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_6_reset_l__SHIFT 0x6
++#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_7_reset_l__SHIFT 0x7
++#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_0_reset_l_MASK 0x00000001L
++#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_1_reset_l_MASK 0x00000002L
++#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_2_reset_l_MASK 0x00000004L
++#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_3_reset_l_MASK 0x00000008L
++#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_4_reset_l_MASK 0x00000010L
++#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_5_reset_l_MASK 0x00000020L
++#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_6_reset_l_MASK 0x00000040L
++#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_7_reset_l_MASK 0x00000080L
++//DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL
++#define DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT 0x0
++#define DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT 0x1
++#define DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT 0x15
++#define DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__zcalcode_override_MASK 0x00000001L
++#define DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK 0x0000003EL
++#define DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK 0x00200000L
++//DC_COMBOPHYCMREGS3_COMMON_DISP_RFU1
++#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU1__rfu_value1__SHIFT 0x0
++#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU1__rfu_value1_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS3_COMMON_DISP_RFU2
++#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU2__rfu_value2__SHIFT 0x0
++#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU2__rfu_value2_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS3_COMMON_DISP_RFU3
++#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU3__rfu_value3__SHIFT 0x0
++#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU3__rfu_value3_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS3_COMMON_DISP_RFU4
++#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU4__rfu_value4__SHIFT 0x0
++#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU4__rfu_value4_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS3_COMMON_DISP_RFU5
++#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU5__rfu_value5__SHIFT 0x0
++#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU5__rfu_value5_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS3_COMMON_DISP_RFU6
++#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU6__rfu_value6__SHIFT 0x0
++#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU6__rfu_value6_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS3_COMMON_DISP_RFU7
++#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU7__rfu_value7__SHIFT 0x0
++#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU7__rfu_value7_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dc_combophytxregs3_dispdec
++//DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0
++#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3
++#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT 0x8
++#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK 0x00000100L
++//DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0
++#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT 0x3
++#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT 0x5
++#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0__txmarg_sel_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0__deemph_sel_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0__tx_margin_en_MASK 0x00000020L
++//DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x1
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x3
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT 0x8
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT 0xa
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT 0xc
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT 0xd
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT 0xe
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT 0xf
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT 0x10
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT 0x14
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT 0x16
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x00000006L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0x000000E0L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK 0x00000300L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK 0x00000C00L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK 0x00001000L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK 0x00002000L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK 0x00004000L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK 0x00008000L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK 0x000F0000L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK 0x00100000L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK 0x00C00000L
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0__rfu_value0__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0__rfu_value0_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0__rfu_value1__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0__rfu_value1_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0__rfu_value2__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0__rfu_value2_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0__rfu_value3__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0__rfu_value3_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0__rfu_value4__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0__rfu_value4_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0__rfu_value5__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0__rfu_value5_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0__rfu_value6__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0__rfu_value6_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0__rfu_value7__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0__rfu_value7_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0__rfu_value8__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0__rfu_value8_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0__rfu_value9__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0__rfu_value9_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0__rfu_value10__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0__rfu_value10_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0__rfu_value11__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0__rfu_value11_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0__rfu_value12__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0__rfu_value12_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1
++#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3
++#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT 0x8
++#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK 0x00000100L
++//DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1
++#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT 0x3
++#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT 0x5
++#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1__txmarg_sel_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1__deemph_sel_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1__tx_margin_en_MASK 0x00000020L
++//DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x1
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x3
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT 0x8
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT 0xa
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT 0xc
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT 0xd
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT 0xe
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT 0xf
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT 0x10
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT 0x14
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT 0x16
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x00000006L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0x000000E0L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK 0x00000300L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK 0x00000C00L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK 0x00001000L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK 0x00002000L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK 0x00004000L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK 0x00008000L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK 0x000F0000L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK 0x00100000L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK 0x00C00000L
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1__rfu_value0__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1__rfu_value0_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1__rfu_value1__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1__rfu_value1_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1__rfu_value2__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1__rfu_value2_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1__rfu_value3__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1__rfu_value3_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1__rfu_value4__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1__rfu_value4_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1__rfu_value5__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1__rfu_value5_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1__rfu_value6__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1__rfu_value6_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1__rfu_value7__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1__rfu_value7_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1__rfu_value8__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1__rfu_value8_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1__rfu_value9__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1__rfu_value9_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1__rfu_value10__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1__rfu_value10_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1__rfu_value11__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1__rfu_value11_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1__rfu_value12__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1__rfu_value12_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2
++#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3
++#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT 0x8
++#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK 0x00000100L
++//DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2
++#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT 0x3
++#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT 0x5
++#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2__txmarg_sel_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2__deemph_sel_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2__tx_margin_en_MASK 0x00000020L
++//DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x1
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x3
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT 0x8
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT 0xa
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT 0xc
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT 0xd
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT 0xe
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT 0xf
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT 0x10
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT 0x14
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT 0x16
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x00000006L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0x000000E0L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK 0x00000300L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK 0x00000C00L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK 0x00001000L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK 0x00002000L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK 0x00004000L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK 0x00008000L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK 0x000F0000L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK 0x00100000L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK 0x00C00000L
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2__rfu_value0__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2__rfu_value0_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2__rfu_value1__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2__rfu_value1_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2__rfu_value2__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2__rfu_value2_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2__rfu_value3__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2__rfu_value3_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2__rfu_value4__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2__rfu_value4_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2__rfu_value5__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2__rfu_value5_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2__rfu_value6__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2__rfu_value6_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2__rfu_value7__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2__rfu_value7_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2__rfu_value8__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2__rfu_value8_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2__rfu_value9__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2__rfu_value9_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2__rfu_value10__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2__rfu_value10_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2__rfu_value11__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2__rfu_value11_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2__rfu_value12__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2__rfu_value12_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3
++#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3
++#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT 0x8
++#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK 0x00000100L
++//DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3
++#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT 0x3
++#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT 0x5
++#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3__txmarg_sel_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3__deemph_sel_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3__tx_margin_en_MASK 0x00000020L
++//DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x1
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x3
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT 0x8
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT 0xa
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT 0xc
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT 0xd
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT 0xe
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT 0xf
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT 0x10
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT 0x14
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT 0x16
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x00000006L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0x000000E0L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK 0x00000300L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK 0x00000C00L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK 0x00001000L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK 0x00002000L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK 0x00004000L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK 0x00008000L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK 0x000F0000L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK 0x00100000L
++#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK 0x00C00000L
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3__rfu_value0__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3__rfu_value0_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3__rfu_value1__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3__rfu_value1_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3__rfu_value2__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3__rfu_value2_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3__rfu_value3__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3__rfu_value3_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3__rfu_value4__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3__rfu_value4_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3__rfu_value5__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3__rfu_value5_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3__rfu_value6__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3__rfu_value6_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3__rfu_value7__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3__rfu_value7_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3__rfu_value8__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3__rfu_value8_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3__rfu_value9__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3__rfu_value9_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3__rfu_value10__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3__rfu_value10_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3__rfu_value11__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3__rfu_value11_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3__rfu_value12__SHIFT 0x0
++#define DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3__rfu_value12_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dc_combophypllregs3_dispdec
++//DC_COMBOPHYPLLREGS3_FREQ_CTRL0
++#define DC_COMBOPHYPLLREGS3_FREQ_CTRL0__fcw0_frac__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS3_FREQ_CTRL0__fcw0_int__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS3_FREQ_CTRL0__fcw0_frac_MASK 0x0000FFFFL
++#define DC_COMBOPHYPLLREGS3_FREQ_CTRL0__fcw0_int_MASK 0x01FF0000L
++//DC_COMBOPHYPLLREGS3_FREQ_CTRL1
++#define DC_COMBOPHYPLLREGS3_FREQ_CTRL1__fcw1_frac__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS3_FREQ_CTRL1__fcw1_int__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS3_FREQ_CTRL1__fcw1_frac_MASK 0x0000FFFFL
++#define DC_COMBOPHYPLLREGS3_FREQ_CTRL1__fcw1_int_MASK 0x01FF0000L
++//DC_COMBOPHYPLLREGS3_FREQ_CTRL2
++#define DC_COMBOPHYPLLREGS3_FREQ_CTRL2__fcw_denom__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS3_FREQ_CTRL2__fcw_slew_frac__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS3_FREQ_CTRL2__fcw_denom_MASK 0x0000FFFFL
++#define DC_COMBOPHYPLLREGS3_FREQ_CTRL2__fcw_slew_frac_MASK 0xFFFF0000L
++//DC_COMBOPHYPLLREGS3_FREQ_CTRL3
++#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__refclk_div__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__vco_pre_div__SHIFT 0x3
++#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__fracn_en__SHIFT 0x6
++#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__ssc_en__SHIFT 0x8
++#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__fcw_sel__SHIFT 0xa
++#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__freq_jump_en__SHIFT 0xc
++#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__tdc_resolution__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__dpll_cfg_1__SHIFT 0x18
++#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__refclk_div_MASK 0x00000003L
++#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__vco_pre_div_MASK 0x00000018L
++#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__fracn_en_MASK 0x00000040L
++#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__ssc_en_MASK 0x00000100L
++#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__fcw_sel_MASK 0x00000400L
++#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__freq_jump_en_MASK 0x00001000L
++#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__tdc_resolution_MASK 0x00FF0000L
++#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__dpll_cfg_1_MASK 0xFF000000L
++//DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE
++#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gi_coarse_mant__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gi_coarse_exp__SHIFT 0x2
++#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gp_coarse_mant__SHIFT 0x7
++#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gp_coarse_exp__SHIFT 0xc
++#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__nctl_coarse_res__SHIFT 0x11
++#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT 0x18
++#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gi_coarse_mant_MASK 0x00000003L
++#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gi_coarse_exp_MASK 0x0000003CL
++#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gp_coarse_mant_MASK 0x00000780L
++#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gp_coarse_exp_MASK 0x0000F000L
++#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__nctl_coarse_res_MASK 0x007E0000L
++#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__nctl_coarse_frac_res_MASK 0x03000000L
++//DC_COMBOPHYPLLREGS3_BW_CTRL_FINE
++#define DC_COMBOPHYPLLREGS3_BW_CTRL_FINE__dpll_cfg_3__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS3_BW_CTRL_FINE__dpll_cfg_3_MASK 0x000003FFL
++//DC_COMBOPHYPLLREGS3_CAL_CTRL
++#define DC_COMBOPHYPLLREGS3_CAL_CTRL__bypass_freq_lock__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS3_CAL_CTRL__tdc_cal_en__SHIFT 0x1
++#define DC_COMBOPHYPLLREGS3_CAL_CTRL__tdc_cal_ctrl__SHIFT 0x3
++#define DC_COMBOPHYPLLREGS3_CAL_CTRL__meas_win_sel__SHIFT 0x9
++#define DC_COMBOPHYPLLREGS3_CAL_CTRL__kdco_cal_dis__SHIFT 0xb
++#define DC_COMBOPHYPLLREGS3_CAL_CTRL__kdco_ratio__SHIFT 0xd
++#define DC_COMBOPHYPLLREGS3_CAL_CTRL__kdco_incr_cal_dis__SHIFT 0x16
++#define DC_COMBOPHYPLLREGS3_CAL_CTRL__nctl_adj_dis__SHIFT 0x17
++#define DC_COMBOPHYPLLREGS3_CAL_CTRL__refclk_rate__SHIFT 0x18
++#define DC_COMBOPHYPLLREGS3_CAL_CTRL__bypass_freq_lock_MASK 0x00000001L
++#define DC_COMBOPHYPLLREGS3_CAL_CTRL__tdc_cal_en_MASK 0x00000002L
++#define DC_COMBOPHYPLLREGS3_CAL_CTRL__tdc_cal_ctrl_MASK 0x000001F8L
++#define DC_COMBOPHYPLLREGS3_CAL_CTRL__meas_win_sel_MASK 0x00000600L
++#define DC_COMBOPHYPLLREGS3_CAL_CTRL__kdco_cal_dis_MASK 0x00000800L
++#define DC_COMBOPHYPLLREGS3_CAL_CTRL__kdco_ratio_MASK 0x001FE000L
++#define DC_COMBOPHYPLLREGS3_CAL_CTRL__kdco_incr_cal_dis_MASK 0x00400000L
++#define DC_COMBOPHYPLLREGS3_CAL_CTRL__nctl_adj_dis_MASK 0x00800000L
++#define DC_COMBOPHYPLLREGS3_CAL_CTRL__refclk_rate_MASK 0xFF000000L
++//DC_COMBOPHYPLLREGS3_LOOP_CTRL
++#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__fbdiv_mask_en__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__fb_slip_dis__SHIFT 0x2
++#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__clk_tdc_sel__SHIFT 0x4
++#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__clk_nctl_sel__SHIFT 0x7
++#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__sig_del_patt_sel__SHIFT 0xa
++#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__nctl_sig_del_dis__SHIFT 0xc
++#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__fbclk_track_refclk__SHIFT 0xe
++#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__prbs_en__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__tdc_clk_gate_en__SHIFT 0x12
++#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__phase_offset__SHIFT 0x14
++#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__fbdiv_mask_en_MASK 0x00000001L
++#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__fb_slip_dis_MASK 0x00000004L
++#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__clk_tdc_sel_MASK 0x00000030L
++#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__clk_nctl_sel_MASK 0x00000180L
++#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__sig_del_patt_sel_MASK 0x00000400L
++#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__nctl_sig_del_dis_MASK 0x00001000L
++#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__fbclk_track_refclk_MASK 0x00004000L
++#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__prbs_en_MASK 0x00010000L
++#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__tdc_clk_gate_en_MASK 0x00040000L
++#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__phase_offset_MASK 0x07F00000L
++//DC_COMBOPHYPLLREGS3_VREG_CFG
++#define DC_COMBOPHYPLLREGS3_VREG_CFG__bleeder_ac__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS3_VREG_CFG__bleeder_en__SHIFT 0x1
++#define DC_COMBOPHYPLLREGS3_VREG_CFG__is_1p2__SHIFT 0x2
++#define DC_COMBOPHYPLLREGS3_VREG_CFG__reg_obs_sel__SHIFT 0x3
++#define DC_COMBOPHYPLLREGS3_VREG_CFG__reg_on_mode__SHIFT 0x5
++#define DC_COMBOPHYPLLREGS3_VREG_CFG__rlad_tap_sel__SHIFT 0x7
++#define DC_COMBOPHYPLLREGS3_VREG_CFG__reg_off_hi__SHIFT 0xb
++#define DC_COMBOPHYPLLREGS3_VREG_CFG__reg_off_lo__SHIFT 0xc
++#define DC_COMBOPHYPLLREGS3_VREG_CFG__scale_driver__SHIFT 0xd
++#define DC_COMBOPHYPLLREGS3_VREG_CFG__sel_bump__SHIFT 0xf
++#define DC_COMBOPHYPLLREGS3_VREG_CFG__sel_rladder_x__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS3_VREG_CFG__short_rc_filt_x__SHIFT 0x11
++#define DC_COMBOPHYPLLREGS3_VREG_CFG__vref_pwr_on__SHIFT 0x12
++#define DC_COMBOPHYPLLREGS3_VREG_CFG__dpll_cfg_2__SHIFT 0x14
++#define DC_COMBOPHYPLLREGS3_VREG_CFG__bleeder_ac_MASK 0x00000001L
++#define DC_COMBOPHYPLLREGS3_VREG_CFG__bleeder_en_MASK 0x00000002L
++#define DC_COMBOPHYPLLREGS3_VREG_CFG__is_1p2_MASK 0x00000004L
++#define DC_COMBOPHYPLLREGS3_VREG_CFG__reg_obs_sel_MASK 0x00000018L
++#define DC_COMBOPHYPLLREGS3_VREG_CFG__reg_on_mode_MASK 0x00000060L
++#define DC_COMBOPHYPLLREGS3_VREG_CFG__rlad_tap_sel_MASK 0x00000780L
++#define DC_COMBOPHYPLLREGS3_VREG_CFG__reg_off_hi_MASK 0x00000800L
++#define DC_COMBOPHYPLLREGS3_VREG_CFG__reg_off_lo_MASK 0x00001000L
++#define DC_COMBOPHYPLLREGS3_VREG_CFG__scale_driver_MASK 0x00006000L
++#define DC_COMBOPHYPLLREGS3_VREG_CFG__sel_bump_MASK 0x00008000L
++#define DC_COMBOPHYPLLREGS3_VREG_CFG__sel_rladder_x_MASK 0x00010000L
++#define DC_COMBOPHYPLLREGS3_VREG_CFG__short_rc_filt_x_MASK 0x00020000L
++#define DC_COMBOPHYPLLREGS3_VREG_CFG__vref_pwr_on_MASK 0x00040000L
++#define DC_COMBOPHYPLLREGS3_VREG_CFG__dpll_cfg_2_MASK 0x0FF00000L
++//DC_COMBOPHYPLLREGS3_OBSERVE0
++#define DC_COMBOPHYPLLREGS3_OBSERVE0__lock_det_tdc_steps__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS3_OBSERVE0__clear_sticky_lock__SHIFT 0x6
++#define DC_COMBOPHYPLLREGS3_OBSERVE0__lock_det_dis__SHIFT 0x8
++#define DC_COMBOPHYPLLREGS3_OBSERVE0__dco_cfg__SHIFT 0xa
++#define DC_COMBOPHYPLLREGS3_OBSERVE0__anaobs_sel__SHIFT 0x15
++#define DC_COMBOPHYPLLREGS3_OBSERVE0__lock_det_tdc_steps_MASK 0x0000001FL
++#define DC_COMBOPHYPLLREGS3_OBSERVE0__clear_sticky_lock_MASK 0x00000040L
++#define DC_COMBOPHYPLLREGS3_OBSERVE0__lock_det_dis_MASK 0x00000100L
++#define DC_COMBOPHYPLLREGS3_OBSERVE0__dco_cfg_MASK 0x0003FC00L
++#define DC_COMBOPHYPLLREGS3_OBSERVE0__anaobs_sel_MASK 0x00E00000L
++//DC_COMBOPHYPLLREGS3_OBSERVE1
++#define DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_sel__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_trig_sel__SHIFT 0x5
++#define DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_div__SHIFT 0xa
++#define DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_trig_div__SHIFT 0xd
++#define DC_COMBOPHYPLLREGS3_OBSERVE1__lock_timer__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_sel_MASK 0x0000000FL
++#define DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_trig_sel_MASK 0x000001E0L
++#define DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_div_MASK 0x00000C00L
++#define DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_trig_div_MASK 0x00006000L
++#define DC_COMBOPHYPLLREGS3_OBSERVE1__lock_timer_MASK 0x3FFF0000L
++//DC_COMBOPHYPLLREGS3_DFT_OUT
++#define DC_COMBOPHYPLLREGS3_DFT_OUT__dft_data__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS3_DFT_OUT__dft_data_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dcio_uniphy4_dispdec
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dc_combophycmregs4_dispdec
++//DC_COMBOPHYCMREGS4_COMMON_FUSE1
++#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_valid__SHIFT 0x0
++#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_unpopulated0__SHIFT 0x1
++#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_ron_override_val__SHIFT 0x3
++#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_unpopulated1__SHIFT 0x9
++#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0xa
++#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_unpopulated2__SHIFT 0xc
++#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_rtt_override_val__SHIFT 0xd
++#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_unpopulated3__SHIFT 0x13
++#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0x14
++#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_refresh_cal_en__SHIFT 0x16
++#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_spare__SHIFT 0x17
++#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_valid_MASK 0x00000001L
++#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_unpopulated0_MASK 0x00000006L
++#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_ron_override_val_MASK 0x000001F8L
++#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_unpopulated1_MASK 0x00000200L
++#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x00000C00L
++#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_unpopulated2_MASK 0x00001000L
++#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_rtt_override_val_MASK 0x0007E000L
++#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_unpopulated3_MASK 0x00080000L
++#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x00300000L
++#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_refresh_cal_en_MASK 0x00400000L
++#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_spare_MASK 0xFF800000L
++//DC_COMBOPHYCMREGS4_COMMON_FUSE2
++#define DC_COMBOPHYCMREGS4_COMMON_FUSE2__fuse2_valid__SHIFT 0x0
++#define DC_COMBOPHYCMREGS4_COMMON_FUSE2__fuse2_unpopulated__SHIFT 0x1
++#define DC_COMBOPHYCMREGS4_COMMON_FUSE2__fuse2_tx_fifo_ptr__SHIFT 0x9
++#define DC_COMBOPHYCMREGS4_COMMON_FUSE2__fuse2_spare__SHIFT 0xe
++#define DC_COMBOPHYCMREGS4_COMMON_FUSE2__fuse2_valid_MASK 0x00000001L
++#define DC_COMBOPHYCMREGS4_COMMON_FUSE2__fuse2_unpopulated_MASK 0x000001FEL
++#define DC_COMBOPHYCMREGS4_COMMON_FUSE2__fuse2_tx_fifo_ptr_MASK 0x00003E00L
++#define DC_COMBOPHYCMREGS4_COMMON_FUSE2__fuse2_spare_MASK 0xFFFFC000L
++//DC_COMBOPHYCMREGS4_COMMON_FUSE3
++#define DC_COMBOPHYCMREGS4_COMMON_FUSE3__fuse3_valid__SHIFT 0x0
++#define DC_COMBOPHYCMREGS4_COMMON_FUSE3__fuse3_unpopulated__SHIFT 0x1
++#define DC_COMBOPHYCMREGS4_COMMON_FUSE3__fuse3_ei_det_thresh_sel__SHIFT 0xa
++#define DC_COMBOPHYCMREGS4_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d
++#define DC_COMBOPHYCMREGS4_COMMON_FUSE3__fuse3_valid_MASK 0x00000001L
++#define DC_COMBOPHYCMREGS4_COMMON_FUSE3__fuse3_unpopulated_MASK 0x000003FEL
++#define DC_COMBOPHYCMREGS4_COMMON_FUSE3__fuse3_ei_det_thresh_sel_MASK 0x00001C00L
++#define DC_COMBOPHYCMREGS4_COMMON_FUSE3__fuse3_spare_MASK 0xE0000000L
++//DC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM
++#define DC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0
++#define DC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8
++#define DC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10
++#define DC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18
++#define DC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0x000000FFL
++#define DC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0x0000FF00L
++#define DC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0x00FF0000L
++#define DC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xFF000000L
++//DC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT
++#define DC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0
++#define DC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4
++#define DC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT__vprot_en__SHIFT 0xb
++#define DC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT__pgdelay_MASK 0x0000000FL
++#define DC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT__pgmask_MASK 0x000003F0L
++#define DC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT__vprot_en_MASK 0x00000800L
++//DC_COMBOPHYCMREGS4_COMMON_TXCNTRL
++#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT 0x0
++#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__clkgate_dis__SHIFT 0x5
++#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT 0x6
++#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT 0x9
++#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT 0xc
++#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__dual_dvi_mstr_en__SHIFT 0xf
++#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__dual_dvi_en__SHIFT 0x10
++#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK 0x0000001FL
++#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__clkgate_dis_MASK 0x00000020L
++#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK 0x000001C0L
++#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK 0x00000E00L
++#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK 0x00007000L
++#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__dual_dvi_mstr_en_MASK 0x00008000L
++#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__dual_dvi_en_MASK 0x00010000L
++//DC_COMBOPHYCMREGS4_COMMON_TMDP
++#define DC_COMBOPHYCMREGS4_COMMON_TMDP__tmdp_spare__SHIFT 0x0
++#define DC_COMBOPHYCMREGS4_COMMON_TMDP__tmdp_spare_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS
++#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_0_reset_l__SHIFT 0x0
++#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_1_reset_l__SHIFT 0x1
++#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_2_reset_l__SHIFT 0x2
++#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_3_reset_l__SHIFT 0x3
++#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_4_reset_l__SHIFT 0x4
++#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_5_reset_l__SHIFT 0x5
++#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_6_reset_l__SHIFT 0x6
++#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_7_reset_l__SHIFT 0x7
++#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_0_reset_l_MASK 0x00000001L
++#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_1_reset_l_MASK 0x00000002L
++#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_2_reset_l_MASK 0x00000004L
++#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_3_reset_l_MASK 0x00000008L
++#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_4_reset_l_MASK 0x00000010L
++#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_5_reset_l_MASK 0x00000020L
++#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_6_reset_l_MASK 0x00000040L
++#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_7_reset_l_MASK 0x00000080L
++//DC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL
++#define DC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT 0x0
++#define DC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT 0x1
++#define DC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT 0x15
++#define DC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL__zcalcode_override_MASK 0x00000001L
++#define DC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK 0x0000003EL
++#define DC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK 0x00200000L
++//DC_COMBOPHYCMREGS4_COMMON_DISP_RFU1
++#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU1__rfu_value1__SHIFT 0x0
++#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU1__rfu_value1_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS4_COMMON_DISP_RFU2
++#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU2__rfu_value2__SHIFT 0x0
++#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU2__rfu_value2_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS4_COMMON_DISP_RFU3
++#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU3__rfu_value3__SHIFT 0x0
++#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU3__rfu_value3_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS4_COMMON_DISP_RFU4
++#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU4__rfu_value4__SHIFT 0x0
++#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU4__rfu_value4_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS4_COMMON_DISP_RFU5
++#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU5__rfu_value5__SHIFT 0x0
++#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU5__rfu_value5_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS4_COMMON_DISP_RFU6
++#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU6__rfu_value6__SHIFT 0x0
++#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU6__rfu_value6_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS4_COMMON_DISP_RFU7
++#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU7__rfu_value7__SHIFT 0x0
++#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU7__rfu_value7_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dc_combophytxregs4_dispdec
++//DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0
++#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3
++#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT 0x8
++#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK 0x00000100L
++//DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0
++#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT 0x3
++#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT 0x5
++#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0__txmarg_sel_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0__deemph_sel_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0__tx_margin_en_MASK 0x00000020L
++//DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x1
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x3
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT 0x8
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT 0xa
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT 0xc
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT 0xd
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT 0xe
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT 0xf
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT 0x10
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT 0x14
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT 0x16
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x00000006L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0x000000E0L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK 0x00000300L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK 0x00000C00L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK 0x00001000L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK 0x00002000L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK 0x00004000L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK 0x00008000L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK 0x000F0000L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK 0x00100000L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK 0x00C00000L
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0__rfu_value0__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0__rfu_value0_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0__rfu_value1__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0__rfu_value1_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0__rfu_value2__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0__rfu_value2_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0__rfu_value3__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0__rfu_value3_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0__rfu_value4__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0__rfu_value4_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0__rfu_value5__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0__rfu_value5_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0__rfu_value6__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0__rfu_value6_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0__rfu_value7__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0__rfu_value7_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0__rfu_value8__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0__rfu_value8_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0__rfu_value9__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0__rfu_value9_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0__rfu_value10__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0__rfu_value10_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0__rfu_value11__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0__rfu_value11_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0__rfu_value12__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0__rfu_value12_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1
++#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3
++#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT 0x8
++#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK 0x00000100L
++//DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1
++#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT 0x3
++#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT 0x5
++#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1__txmarg_sel_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1__deemph_sel_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1__tx_margin_en_MASK 0x00000020L
++//DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x1
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x3
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT 0x8
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT 0xa
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT 0xc
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT 0xd
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT 0xe
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT 0xf
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT 0x10
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT 0x14
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT 0x16
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x00000006L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0x000000E0L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK 0x00000300L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK 0x00000C00L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK 0x00001000L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK 0x00002000L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK 0x00004000L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK 0x00008000L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK 0x000F0000L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK 0x00100000L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK 0x00C00000L
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1__rfu_value0__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1__rfu_value0_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1__rfu_value1__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1__rfu_value1_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1__rfu_value2__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1__rfu_value2_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1__rfu_value3__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1__rfu_value3_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1__rfu_value4__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1__rfu_value4_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1__rfu_value5__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1__rfu_value5_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1__rfu_value6__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1__rfu_value6_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1__rfu_value7__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1__rfu_value7_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1__rfu_value8__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1__rfu_value8_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1__rfu_value9__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1__rfu_value9_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1__rfu_value10__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1__rfu_value10_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1__rfu_value11__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1__rfu_value11_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1__rfu_value12__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1__rfu_value12_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2
++#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3
++#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT 0x8
++#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK 0x00000100L
++//DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2
++#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT 0x3
++#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT 0x5
++#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2__txmarg_sel_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2__deemph_sel_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2__tx_margin_en_MASK 0x00000020L
++//DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x1
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x3
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT 0x8
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT 0xa
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT 0xc
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT 0xd
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT 0xe
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT 0xf
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT 0x10
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT 0x14
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT 0x16
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x00000006L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0x000000E0L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK 0x00000300L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK 0x00000C00L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK 0x00001000L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK 0x00002000L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK 0x00004000L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK 0x00008000L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK 0x000F0000L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK 0x00100000L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK 0x00C00000L
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2__rfu_value0__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2__rfu_value0_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2__rfu_value1__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2__rfu_value1_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2__rfu_value2__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2__rfu_value2_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2__rfu_value3__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2__rfu_value3_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2__rfu_value4__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2__rfu_value4_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2__rfu_value5__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2__rfu_value5_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2__rfu_value6__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2__rfu_value6_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2__rfu_value7__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2__rfu_value7_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2__rfu_value8__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2__rfu_value8_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2__rfu_value9__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2__rfu_value9_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2__rfu_value10__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2__rfu_value10_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2__rfu_value11__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2__rfu_value11_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2__rfu_value12__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2__rfu_value12_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3
++#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3
++#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT 0x8
++#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK 0x00000100L
++//DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3
++#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT 0x3
++#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT 0x5
++#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3__txmarg_sel_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3__deemph_sel_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3__tx_margin_en_MASK 0x00000020L
++//DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x1
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x3
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT 0x8
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT 0xa
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT 0xc
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT 0xd
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT 0xe
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT 0xf
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT 0x10
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT 0x14
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT 0x16
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x00000006L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0x000000E0L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK 0x00000300L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK 0x00000C00L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK 0x00001000L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK 0x00002000L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK 0x00004000L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK 0x00008000L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK 0x000F0000L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK 0x00100000L
++#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK 0x00C00000L
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3__rfu_value0__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3__rfu_value0_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3__rfu_value1__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3__rfu_value1_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3__rfu_value2__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3__rfu_value2_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3__rfu_value3__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3__rfu_value3_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3__rfu_value4__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3__rfu_value4_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3__rfu_value5__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3__rfu_value5_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3__rfu_value6__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3__rfu_value6_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3__rfu_value7__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3__rfu_value7_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3__rfu_value8__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3__rfu_value8_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3__rfu_value9__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3__rfu_value9_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3__rfu_value10__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3__rfu_value10_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3__rfu_value11__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3__rfu_value11_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3__rfu_value12__SHIFT 0x0
++#define DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3__rfu_value12_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dc_combophypllregs4_dispdec
++//DC_COMBOPHYPLLREGS4_FREQ_CTRL0
++#define DC_COMBOPHYPLLREGS4_FREQ_CTRL0__fcw0_frac__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS4_FREQ_CTRL0__fcw0_int__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS4_FREQ_CTRL0__fcw0_frac_MASK 0x0000FFFFL
++#define DC_COMBOPHYPLLREGS4_FREQ_CTRL0__fcw0_int_MASK 0x01FF0000L
++//DC_COMBOPHYPLLREGS4_FREQ_CTRL1
++#define DC_COMBOPHYPLLREGS4_FREQ_CTRL1__fcw1_frac__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS4_FREQ_CTRL1__fcw1_int__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS4_FREQ_CTRL1__fcw1_frac_MASK 0x0000FFFFL
++#define DC_COMBOPHYPLLREGS4_FREQ_CTRL1__fcw1_int_MASK 0x01FF0000L
++//DC_COMBOPHYPLLREGS4_FREQ_CTRL2
++#define DC_COMBOPHYPLLREGS4_FREQ_CTRL2__fcw_denom__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS4_FREQ_CTRL2__fcw_slew_frac__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS4_FREQ_CTRL2__fcw_denom_MASK 0x0000FFFFL
++#define DC_COMBOPHYPLLREGS4_FREQ_CTRL2__fcw_slew_frac_MASK 0xFFFF0000L
++//DC_COMBOPHYPLLREGS4_FREQ_CTRL3
++#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__refclk_div__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__vco_pre_div__SHIFT 0x3
++#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__fracn_en__SHIFT 0x6
++#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__ssc_en__SHIFT 0x8
++#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__fcw_sel__SHIFT 0xa
++#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__freq_jump_en__SHIFT 0xc
++#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__tdc_resolution__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__dpll_cfg_1__SHIFT 0x18
++#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__refclk_div_MASK 0x00000003L
++#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__vco_pre_div_MASK 0x00000018L
++#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__fracn_en_MASK 0x00000040L
++#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__ssc_en_MASK 0x00000100L
++#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__fcw_sel_MASK 0x00000400L
++#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__freq_jump_en_MASK 0x00001000L
++#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__tdc_resolution_MASK 0x00FF0000L
++#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__dpll_cfg_1_MASK 0xFF000000L
++//DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE
++#define DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__gi_coarse_mant__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__gi_coarse_exp__SHIFT 0x2
++#define DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__gp_coarse_mant__SHIFT 0x7
++#define DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__gp_coarse_exp__SHIFT 0xc
++#define DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__nctl_coarse_res__SHIFT 0x11
++#define DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT 0x18
++#define DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__gi_coarse_mant_MASK 0x00000003L
++#define DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__gi_coarse_exp_MASK 0x0000003CL
++#define DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__gp_coarse_mant_MASK 0x00000780L
++#define DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__gp_coarse_exp_MASK 0x0000F000L
++#define DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__nctl_coarse_res_MASK 0x007E0000L
++#define DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__nctl_coarse_frac_res_MASK 0x03000000L
++//DC_COMBOPHYPLLREGS4_BW_CTRL_FINE
++#define DC_COMBOPHYPLLREGS4_BW_CTRL_FINE__dpll_cfg_3__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS4_BW_CTRL_FINE__dpll_cfg_3_MASK 0x000003FFL
++//DC_COMBOPHYPLLREGS4_CAL_CTRL
++#define DC_COMBOPHYPLLREGS4_CAL_CTRL__bypass_freq_lock__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS4_CAL_CTRL__tdc_cal_en__SHIFT 0x1
++#define DC_COMBOPHYPLLREGS4_CAL_CTRL__tdc_cal_ctrl__SHIFT 0x3
++#define DC_COMBOPHYPLLREGS4_CAL_CTRL__meas_win_sel__SHIFT 0x9
++#define DC_COMBOPHYPLLREGS4_CAL_CTRL__kdco_cal_dis__SHIFT 0xb
++#define DC_COMBOPHYPLLREGS4_CAL_CTRL__kdco_ratio__SHIFT 0xd
++#define DC_COMBOPHYPLLREGS4_CAL_CTRL__kdco_incr_cal_dis__SHIFT 0x16
++#define DC_COMBOPHYPLLREGS4_CAL_CTRL__nctl_adj_dis__SHIFT 0x17
++#define DC_COMBOPHYPLLREGS4_CAL_CTRL__refclk_rate__SHIFT 0x18
++#define DC_COMBOPHYPLLREGS4_CAL_CTRL__bypass_freq_lock_MASK 0x00000001L
++#define DC_COMBOPHYPLLREGS4_CAL_CTRL__tdc_cal_en_MASK 0x00000002L
++#define DC_COMBOPHYPLLREGS4_CAL_CTRL__tdc_cal_ctrl_MASK 0x000001F8L
++#define DC_COMBOPHYPLLREGS4_CAL_CTRL__meas_win_sel_MASK 0x00000600L
++#define DC_COMBOPHYPLLREGS4_CAL_CTRL__kdco_cal_dis_MASK 0x00000800L
++#define DC_COMBOPHYPLLREGS4_CAL_CTRL__kdco_ratio_MASK 0x001FE000L
++#define DC_COMBOPHYPLLREGS4_CAL_CTRL__kdco_incr_cal_dis_MASK 0x00400000L
++#define DC_COMBOPHYPLLREGS4_CAL_CTRL__nctl_adj_dis_MASK 0x00800000L
++#define DC_COMBOPHYPLLREGS4_CAL_CTRL__refclk_rate_MASK 0xFF000000L
++//DC_COMBOPHYPLLREGS4_LOOP_CTRL
++#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__fbdiv_mask_en__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__fb_slip_dis__SHIFT 0x2
++#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__clk_tdc_sel__SHIFT 0x4
++#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__clk_nctl_sel__SHIFT 0x7
++#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__sig_del_patt_sel__SHIFT 0xa
++#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__nctl_sig_del_dis__SHIFT 0xc
++#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__fbclk_track_refclk__SHIFT 0xe
++#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__prbs_en__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__tdc_clk_gate_en__SHIFT 0x12
++#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__phase_offset__SHIFT 0x14
++#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__fbdiv_mask_en_MASK 0x00000001L
++#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__fb_slip_dis_MASK 0x00000004L
++#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__clk_tdc_sel_MASK 0x00000030L
++#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__clk_nctl_sel_MASK 0x00000180L
++#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__sig_del_patt_sel_MASK 0x00000400L
++#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__nctl_sig_del_dis_MASK 0x00001000L
++#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__fbclk_track_refclk_MASK 0x00004000L
++#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__prbs_en_MASK 0x00010000L
++#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__tdc_clk_gate_en_MASK 0x00040000L
++#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__phase_offset_MASK 0x07F00000L
++//DC_COMBOPHYPLLREGS4_VREG_CFG
++#define DC_COMBOPHYPLLREGS4_VREG_CFG__bleeder_ac__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS4_VREG_CFG__bleeder_en__SHIFT 0x1
++#define DC_COMBOPHYPLLREGS4_VREG_CFG__is_1p2__SHIFT 0x2
++#define DC_COMBOPHYPLLREGS4_VREG_CFG__reg_obs_sel__SHIFT 0x3
++#define DC_COMBOPHYPLLREGS4_VREG_CFG__reg_on_mode__SHIFT 0x5
++#define DC_COMBOPHYPLLREGS4_VREG_CFG__rlad_tap_sel__SHIFT 0x7
++#define DC_COMBOPHYPLLREGS4_VREG_CFG__reg_off_hi__SHIFT 0xb
++#define DC_COMBOPHYPLLREGS4_VREG_CFG__reg_off_lo__SHIFT 0xc
++#define DC_COMBOPHYPLLREGS4_VREG_CFG__scale_driver__SHIFT 0xd
++#define DC_COMBOPHYPLLREGS4_VREG_CFG__sel_bump__SHIFT 0xf
++#define DC_COMBOPHYPLLREGS4_VREG_CFG__sel_rladder_x__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS4_VREG_CFG__short_rc_filt_x__SHIFT 0x11
++#define DC_COMBOPHYPLLREGS4_VREG_CFG__vref_pwr_on__SHIFT 0x12
++#define DC_COMBOPHYPLLREGS4_VREG_CFG__dpll_cfg_2__SHIFT 0x14
++#define DC_COMBOPHYPLLREGS4_VREG_CFG__bleeder_ac_MASK 0x00000001L
++#define DC_COMBOPHYPLLREGS4_VREG_CFG__bleeder_en_MASK 0x00000002L
++#define DC_COMBOPHYPLLREGS4_VREG_CFG__is_1p2_MASK 0x00000004L
++#define DC_COMBOPHYPLLREGS4_VREG_CFG__reg_obs_sel_MASK 0x00000018L
++#define DC_COMBOPHYPLLREGS4_VREG_CFG__reg_on_mode_MASK 0x00000060L
++#define DC_COMBOPHYPLLREGS4_VREG_CFG__rlad_tap_sel_MASK 0x00000780L
++#define DC_COMBOPHYPLLREGS4_VREG_CFG__reg_off_hi_MASK 0x00000800L
++#define DC_COMBOPHYPLLREGS4_VREG_CFG__reg_off_lo_MASK 0x00001000L
++#define DC_COMBOPHYPLLREGS4_VREG_CFG__scale_driver_MASK 0x00006000L
++#define DC_COMBOPHYPLLREGS4_VREG_CFG__sel_bump_MASK 0x00008000L
++#define DC_COMBOPHYPLLREGS4_VREG_CFG__sel_rladder_x_MASK 0x00010000L
++#define DC_COMBOPHYPLLREGS4_VREG_CFG__short_rc_filt_x_MASK 0x00020000L
++#define DC_COMBOPHYPLLREGS4_VREG_CFG__vref_pwr_on_MASK 0x00040000L
++#define DC_COMBOPHYPLLREGS4_VREG_CFG__dpll_cfg_2_MASK 0x0FF00000L
++//DC_COMBOPHYPLLREGS4_OBSERVE0
++#define DC_COMBOPHYPLLREGS4_OBSERVE0__lock_det_tdc_steps__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS4_OBSERVE0__clear_sticky_lock__SHIFT 0x6
++#define DC_COMBOPHYPLLREGS4_OBSERVE0__lock_det_dis__SHIFT 0x8
++#define DC_COMBOPHYPLLREGS4_OBSERVE0__dco_cfg__SHIFT 0xa
++#define DC_COMBOPHYPLLREGS4_OBSERVE0__anaobs_sel__SHIFT 0x15
++#define DC_COMBOPHYPLLREGS4_OBSERVE0__lock_det_tdc_steps_MASK 0x0000001FL
++#define DC_COMBOPHYPLLREGS4_OBSERVE0__clear_sticky_lock_MASK 0x00000040L
++#define DC_COMBOPHYPLLREGS4_OBSERVE0__lock_det_dis_MASK 0x00000100L
++#define DC_COMBOPHYPLLREGS4_OBSERVE0__dco_cfg_MASK 0x0003FC00L
++#define DC_COMBOPHYPLLREGS4_OBSERVE0__anaobs_sel_MASK 0x00E00000L
++//DC_COMBOPHYPLLREGS4_OBSERVE1
++#define DC_COMBOPHYPLLREGS4_OBSERVE1__digobs_sel__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS4_OBSERVE1__digobs_trig_sel__SHIFT 0x5
++#define DC_COMBOPHYPLLREGS4_OBSERVE1__digobs_div__SHIFT 0xa
++#define DC_COMBOPHYPLLREGS4_OBSERVE1__digobs_trig_div__SHIFT 0xd
++#define DC_COMBOPHYPLLREGS4_OBSERVE1__lock_timer__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS4_OBSERVE1__digobs_sel_MASK 0x0000000FL
++#define DC_COMBOPHYPLLREGS4_OBSERVE1__digobs_trig_sel_MASK 0x000001E0L
++#define DC_COMBOPHYPLLREGS4_OBSERVE1__digobs_div_MASK 0x00000C00L
++#define DC_COMBOPHYPLLREGS4_OBSERVE1__digobs_trig_div_MASK 0x00006000L
++#define DC_COMBOPHYPLLREGS4_OBSERVE1__lock_timer_MASK 0x3FFF0000L
++//DC_COMBOPHYPLLREGS4_DFT_OUT
++#define DC_COMBOPHYPLLREGS4_DFT_OUT__dft_data__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS4_DFT_OUT__dft_data_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dcio_uniphy5_dispdec
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dc_combophycmregs5_dispdec
++//DC_COMBOPHYCMREGS5_COMMON_FUSE1
++#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_valid__SHIFT 0x0
++#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_unpopulated0__SHIFT 0x1
++#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_ron_override_val__SHIFT 0x3
++#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_unpopulated1__SHIFT 0x9
++#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0xa
++#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_unpopulated2__SHIFT 0xc
++#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_rtt_override_val__SHIFT 0xd
++#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_unpopulated3__SHIFT 0x13
++#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0x14
++#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_refresh_cal_en__SHIFT 0x16
++#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_spare__SHIFT 0x17
++#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_valid_MASK 0x00000001L
++#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_unpopulated0_MASK 0x00000006L
++#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_ron_override_val_MASK 0x000001F8L
++#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_unpopulated1_MASK 0x00000200L
++#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x00000C00L
++#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_unpopulated2_MASK 0x00001000L
++#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_rtt_override_val_MASK 0x0007E000L
++#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_unpopulated3_MASK 0x00080000L
++#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x00300000L
++#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_refresh_cal_en_MASK 0x00400000L
++#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_spare_MASK 0xFF800000L
++//DC_COMBOPHYCMREGS5_COMMON_FUSE2
++#define DC_COMBOPHYCMREGS5_COMMON_FUSE2__fuse2_valid__SHIFT 0x0
++#define DC_COMBOPHYCMREGS5_COMMON_FUSE2__fuse2_unpopulated__SHIFT 0x1
++#define DC_COMBOPHYCMREGS5_COMMON_FUSE2__fuse2_tx_fifo_ptr__SHIFT 0x9
++#define DC_COMBOPHYCMREGS5_COMMON_FUSE2__fuse2_spare__SHIFT 0xe
++#define DC_COMBOPHYCMREGS5_COMMON_FUSE2__fuse2_valid_MASK 0x00000001L
++#define DC_COMBOPHYCMREGS5_COMMON_FUSE2__fuse2_unpopulated_MASK 0x000001FEL
++#define DC_COMBOPHYCMREGS5_COMMON_FUSE2__fuse2_tx_fifo_ptr_MASK 0x00003E00L
++#define DC_COMBOPHYCMREGS5_COMMON_FUSE2__fuse2_spare_MASK 0xFFFFC000L
++//DC_COMBOPHYCMREGS5_COMMON_FUSE3
++#define DC_COMBOPHYCMREGS5_COMMON_FUSE3__fuse3_valid__SHIFT 0x0
++#define DC_COMBOPHYCMREGS5_COMMON_FUSE3__fuse3_unpopulated__SHIFT 0x1
++#define DC_COMBOPHYCMREGS5_COMMON_FUSE3__fuse3_ei_det_thresh_sel__SHIFT 0xa
++#define DC_COMBOPHYCMREGS5_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d
++#define DC_COMBOPHYCMREGS5_COMMON_FUSE3__fuse3_valid_MASK 0x00000001L
++#define DC_COMBOPHYCMREGS5_COMMON_FUSE3__fuse3_unpopulated_MASK 0x000003FEL
++#define DC_COMBOPHYCMREGS5_COMMON_FUSE3__fuse3_ei_det_thresh_sel_MASK 0x00001C00L
++#define DC_COMBOPHYCMREGS5_COMMON_FUSE3__fuse3_spare_MASK 0xE0000000L
++//DC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM
++#define DC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0
++#define DC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8
++#define DC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10
++#define DC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18
++#define DC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0x000000FFL
++#define DC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0x0000FF00L
++#define DC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0x00FF0000L
++#define DC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xFF000000L
++//DC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT
++#define DC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0
++#define DC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4
++#define DC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT__vprot_en__SHIFT 0xb
++#define DC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT__pgdelay_MASK 0x0000000FL
++#define DC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT__pgmask_MASK 0x000003F0L
++#define DC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT__vprot_en_MASK 0x00000800L
++//DC_COMBOPHYCMREGS5_COMMON_TXCNTRL
++#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT 0x0
++#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__clkgate_dis__SHIFT 0x5
++#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT 0x6
++#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT 0x9
++#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT 0xc
++#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__dual_dvi_mstr_en__SHIFT 0xf
++#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__dual_dvi_en__SHIFT 0x10
++#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK 0x0000001FL
++#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__clkgate_dis_MASK 0x00000020L
++#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK 0x000001C0L
++#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK 0x00000E00L
++#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK 0x00007000L
++#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__dual_dvi_mstr_en_MASK 0x00008000L
++#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__dual_dvi_en_MASK 0x00010000L
++//DC_COMBOPHYCMREGS5_COMMON_TMDP
++#define DC_COMBOPHYCMREGS5_COMMON_TMDP__tmdp_spare__SHIFT 0x0
++#define DC_COMBOPHYCMREGS5_COMMON_TMDP__tmdp_spare_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS
++#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_0_reset_l__SHIFT 0x0
++#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_1_reset_l__SHIFT 0x1
++#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_2_reset_l__SHIFT 0x2
++#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_3_reset_l__SHIFT 0x3
++#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_4_reset_l__SHIFT 0x4
++#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_5_reset_l__SHIFT 0x5
++#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_6_reset_l__SHIFT 0x6
++#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_7_reset_l__SHIFT 0x7
++#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_0_reset_l_MASK 0x00000001L
++#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_1_reset_l_MASK 0x00000002L
++#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_2_reset_l_MASK 0x00000004L
++#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_3_reset_l_MASK 0x00000008L
++#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_4_reset_l_MASK 0x00000010L
++#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_5_reset_l_MASK 0x00000020L
++#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_6_reset_l_MASK 0x00000040L
++#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_7_reset_l_MASK 0x00000080L
++//DC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL
++#define DC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT 0x0
++#define DC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT 0x1
++#define DC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT 0x15
++#define DC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL__zcalcode_override_MASK 0x00000001L
++#define DC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK 0x0000003EL
++#define DC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK 0x00200000L
++//DC_COMBOPHYCMREGS5_COMMON_DISP_RFU1
++#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU1__rfu_value1__SHIFT 0x0
++#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU1__rfu_value1_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS5_COMMON_DISP_RFU2
++#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU2__rfu_value2__SHIFT 0x0
++#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU2__rfu_value2_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS5_COMMON_DISP_RFU3
++#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU3__rfu_value3__SHIFT 0x0
++#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU3__rfu_value3_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS5_COMMON_DISP_RFU4
++#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU4__rfu_value4__SHIFT 0x0
++#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU4__rfu_value4_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS5_COMMON_DISP_RFU5
++#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU5__rfu_value5__SHIFT 0x0
++#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU5__rfu_value5_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS5_COMMON_DISP_RFU6
++#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU6__rfu_value6__SHIFT 0x0
++#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU6__rfu_value6_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS5_COMMON_DISP_RFU7
++#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU7__rfu_value7__SHIFT 0x0
++#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU7__rfu_value7_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dc_combophytxregs5_dispdec
++//DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0
++#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3
++#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT 0x8
++#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK 0x00000100L
++//DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0
++#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT 0x3
++#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT 0x5
++#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0__txmarg_sel_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0__deemph_sel_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0__tx_margin_en_MASK 0x00000020L
++//DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x1
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x3
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT 0x8
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT 0xa
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT 0xc
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT 0xd
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT 0xe
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT 0xf
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT 0x10
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT 0x14
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT 0x16
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x00000006L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0x000000E0L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK 0x00000300L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK 0x00000C00L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK 0x00001000L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK 0x00002000L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK 0x00004000L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK 0x00008000L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK 0x000F0000L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK 0x00100000L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK 0x00C00000L
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0__rfu_value0__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0__rfu_value0_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0__rfu_value1__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0__rfu_value1_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0__rfu_value2__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0__rfu_value2_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0__rfu_value3__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0__rfu_value3_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0__rfu_value4__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0__rfu_value4_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0__rfu_value5__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0__rfu_value5_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0__rfu_value6__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0__rfu_value6_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0__rfu_value7__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0__rfu_value7_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0__rfu_value8__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0__rfu_value8_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0__rfu_value9__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0__rfu_value9_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0__rfu_value10__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0__rfu_value10_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0__rfu_value11__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0__rfu_value11_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0__rfu_value12__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0__rfu_value12_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1
++#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3
++#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT 0x8
++#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK 0x00000100L
++//DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1
++#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT 0x3
++#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT 0x5
++#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1__txmarg_sel_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1__deemph_sel_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1__tx_margin_en_MASK 0x00000020L
++//DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x1
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x3
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT 0x8
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT 0xa
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT 0xc
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT 0xd
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT 0xe
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT 0xf
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT 0x10
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT 0x14
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT 0x16
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x00000006L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0x000000E0L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK 0x00000300L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK 0x00000C00L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK 0x00001000L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK 0x00002000L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK 0x00004000L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK 0x00008000L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK 0x000F0000L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK 0x00100000L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK 0x00C00000L
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1__rfu_value0__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1__rfu_value0_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1__rfu_value1__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1__rfu_value1_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1__rfu_value2__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1__rfu_value2_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1__rfu_value3__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1__rfu_value3_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1__rfu_value4__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1__rfu_value4_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1__rfu_value5__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1__rfu_value5_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1__rfu_value6__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1__rfu_value6_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1__rfu_value7__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1__rfu_value7_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1__rfu_value8__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1__rfu_value8_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1__rfu_value9__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1__rfu_value9_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1__rfu_value10__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1__rfu_value10_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1__rfu_value11__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1__rfu_value11_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1__rfu_value12__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1__rfu_value12_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2
++#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3
++#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT 0x8
++#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK 0x00000100L
++//DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2
++#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT 0x3
++#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT 0x5
++#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2__txmarg_sel_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2__deemph_sel_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2__tx_margin_en_MASK 0x00000020L
++//DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x1
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x3
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT 0x8
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT 0xa
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT 0xc
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT 0xd
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT 0xe
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT 0xf
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT 0x10
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT 0x14
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT 0x16
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x00000006L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0x000000E0L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK 0x00000300L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK 0x00000C00L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK 0x00001000L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK 0x00002000L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK 0x00004000L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK 0x00008000L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK 0x000F0000L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK 0x00100000L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK 0x00C00000L
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2__rfu_value0__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2__rfu_value0_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2__rfu_value1__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2__rfu_value1_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2__rfu_value2__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2__rfu_value2_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2__rfu_value3__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2__rfu_value3_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2__rfu_value4__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2__rfu_value4_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2__rfu_value5__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2__rfu_value5_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2__rfu_value6__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2__rfu_value6_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2__rfu_value7__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2__rfu_value7_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2__rfu_value8__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2__rfu_value8_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2__rfu_value9__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2__rfu_value9_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2__rfu_value10__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2__rfu_value10_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2__rfu_value11__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2__rfu_value11_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2__rfu_value12__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2__rfu_value12_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3
++#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3
++#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT 0x8
++#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK 0x00000100L
++//DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3
++#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT 0x3
++#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT 0x5
++#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3__txmarg_sel_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3__deemph_sel_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3__tx_margin_en_MASK 0x00000020L
++//DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x1
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x3
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT 0x8
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT 0xa
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT 0xc
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT 0xd
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT 0xe
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT 0xf
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT 0x10
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT 0x14
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT 0x16
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x00000006L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0x000000E0L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK 0x00000300L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK 0x00000C00L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK 0x00001000L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK 0x00002000L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK 0x00004000L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK 0x00008000L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK 0x000F0000L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK 0x00100000L
++#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK 0x00C00000L
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3__rfu_value0__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3__rfu_value0_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3__rfu_value1__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3__rfu_value1_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3__rfu_value2__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3__rfu_value2_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3__rfu_value3__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3__rfu_value3_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3__rfu_value4__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3__rfu_value4_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3__rfu_value5__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3__rfu_value5_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3__rfu_value6__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3__rfu_value6_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3__rfu_value7__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3__rfu_value7_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3__rfu_value8__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3__rfu_value8_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3__rfu_value9__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3__rfu_value9_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3__rfu_value10__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3__rfu_value10_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3__rfu_value11__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3__rfu_value11_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3__rfu_value12__SHIFT 0x0
++#define DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3__rfu_value12_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dc_combophypllregs5_dispdec
++//DC_COMBOPHYPLLREGS5_FREQ_CTRL0
++#define DC_COMBOPHYPLLREGS5_FREQ_CTRL0__fcw0_frac__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS5_FREQ_CTRL0__fcw0_int__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS5_FREQ_CTRL0__fcw0_frac_MASK 0x0000FFFFL
++#define DC_COMBOPHYPLLREGS5_FREQ_CTRL0__fcw0_int_MASK 0x01FF0000L
++//DC_COMBOPHYPLLREGS5_FREQ_CTRL1
++#define DC_COMBOPHYPLLREGS5_FREQ_CTRL1__fcw1_frac__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS5_FREQ_CTRL1__fcw1_int__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS5_FREQ_CTRL1__fcw1_frac_MASK 0x0000FFFFL
++#define DC_COMBOPHYPLLREGS5_FREQ_CTRL1__fcw1_int_MASK 0x01FF0000L
++//DC_COMBOPHYPLLREGS5_FREQ_CTRL2
++#define DC_COMBOPHYPLLREGS5_FREQ_CTRL2__fcw_denom__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS5_FREQ_CTRL2__fcw_slew_frac__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS5_FREQ_CTRL2__fcw_denom_MASK 0x0000FFFFL
++#define DC_COMBOPHYPLLREGS5_FREQ_CTRL2__fcw_slew_frac_MASK 0xFFFF0000L
++//DC_COMBOPHYPLLREGS5_FREQ_CTRL3
++#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__refclk_div__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__vco_pre_div__SHIFT 0x3
++#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__fracn_en__SHIFT 0x6
++#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__ssc_en__SHIFT 0x8
++#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__fcw_sel__SHIFT 0xa
++#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__freq_jump_en__SHIFT 0xc
++#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__tdc_resolution__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__dpll_cfg_1__SHIFT 0x18
++#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__refclk_div_MASK 0x00000003L
++#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__vco_pre_div_MASK 0x00000018L
++#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__fracn_en_MASK 0x00000040L
++#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__ssc_en_MASK 0x00000100L
++#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__fcw_sel_MASK 0x00000400L
++#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__freq_jump_en_MASK 0x00001000L
++#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__tdc_resolution_MASK 0x00FF0000L
++#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__dpll_cfg_1_MASK 0xFF000000L
++//DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE
++#define DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__gi_coarse_mant__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__gi_coarse_exp__SHIFT 0x2
++#define DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__gp_coarse_mant__SHIFT 0x7
++#define DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__gp_coarse_exp__SHIFT 0xc
++#define DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__nctl_coarse_res__SHIFT 0x11
++#define DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT 0x18
++#define DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__gi_coarse_mant_MASK 0x00000003L
++#define DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__gi_coarse_exp_MASK 0x0000003CL
++#define DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__gp_coarse_mant_MASK 0x00000780L
++#define DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__gp_coarse_exp_MASK 0x0000F000L
++#define DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__nctl_coarse_res_MASK 0x007E0000L
++#define DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__nctl_coarse_frac_res_MASK 0x03000000L
++//DC_COMBOPHYPLLREGS5_BW_CTRL_FINE
++#define DC_COMBOPHYPLLREGS5_BW_CTRL_FINE__dpll_cfg_3__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS5_BW_CTRL_FINE__dpll_cfg_3_MASK 0x000003FFL
++//DC_COMBOPHYPLLREGS5_CAL_CTRL
++#define DC_COMBOPHYPLLREGS5_CAL_CTRL__bypass_freq_lock__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS5_CAL_CTRL__tdc_cal_en__SHIFT 0x1
++#define DC_COMBOPHYPLLREGS5_CAL_CTRL__tdc_cal_ctrl__SHIFT 0x3
++#define DC_COMBOPHYPLLREGS5_CAL_CTRL__meas_win_sel__SHIFT 0x9
++#define DC_COMBOPHYPLLREGS5_CAL_CTRL__kdco_cal_dis__SHIFT 0xb
++#define DC_COMBOPHYPLLREGS5_CAL_CTRL__kdco_ratio__SHIFT 0xd
++#define DC_COMBOPHYPLLREGS5_CAL_CTRL__kdco_incr_cal_dis__SHIFT 0x16
++#define DC_COMBOPHYPLLREGS5_CAL_CTRL__nctl_adj_dis__SHIFT 0x17
++#define DC_COMBOPHYPLLREGS5_CAL_CTRL__refclk_rate__SHIFT 0x18
++#define DC_COMBOPHYPLLREGS5_CAL_CTRL__bypass_freq_lock_MASK 0x00000001L
++#define DC_COMBOPHYPLLREGS5_CAL_CTRL__tdc_cal_en_MASK 0x00000002L
++#define DC_COMBOPHYPLLREGS5_CAL_CTRL__tdc_cal_ctrl_MASK 0x000001F8L
++#define DC_COMBOPHYPLLREGS5_CAL_CTRL__meas_win_sel_MASK 0x00000600L
++#define DC_COMBOPHYPLLREGS5_CAL_CTRL__kdco_cal_dis_MASK 0x00000800L
++#define DC_COMBOPHYPLLREGS5_CAL_CTRL__kdco_ratio_MASK 0x001FE000L
++#define DC_COMBOPHYPLLREGS5_CAL_CTRL__kdco_incr_cal_dis_MASK 0x00400000L
++#define DC_COMBOPHYPLLREGS5_CAL_CTRL__nctl_adj_dis_MASK 0x00800000L
++#define DC_COMBOPHYPLLREGS5_CAL_CTRL__refclk_rate_MASK 0xFF000000L
++//DC_COMBOPHYPLLREGS5_LOOP_CTRL
++#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__fbdiv_mask_en__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__fb_slip_dis__SHIFT 0x2
++#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__clk_tdc_sel__SHIFT 0x4
++#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__clk_nctl_sel__SHIFT 0x7
++#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__sig_del_patt_sel__SHIFT 0xa
++#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__nctl_sig_del_dis__SHIFT 0xc
++#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__fbclk_track_refclk__SHIFT 0xe
++#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__prbs_en__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__tdc_clk_gate_en__SHIFT 0x12
++#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__phase_offset__SHIFT 0x14
++#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__fbdiv_mask_en_MASK 0x00000001L
++#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__fb_slip_dis_MASK 0x00000004L
++#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__clk_tdc_sel_MASK 0x00000030L
++#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__clk_nctl_sel_MASK 0x00000180L
++#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__sig_del_patt_sel_MASK 0x00000400L
++#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__nctl_sig_del_dis_MASK 0x00001000L
++#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__fbclk_track_refclk_MASK 0x00004000L
++#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__prbs_en_MASK 0x00010000L
++#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__tdc_clk_gate_en_MASK 0x00040000L
++#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__phase_offset_MASK 0x07F00000L
++//DC_COMBOPHYPLLREGS5_VREG_CFG
++#define DC_COMBOPHYPLLREGS5_VREG_CFG__bleeder_ac__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS5_VREG_CFG__bleeder_en__SHIFT 0x1
++#define DC_COMBOPHYPLLREGS5_VREG_CFG__is_1p2__SHIFT 0x2
++#define DC_COMBOPHYPLLREGS5_VREG_CFG__reg_obs_sel__SHIFT 0x3
++#define DC_COMBOPHYPLLREGS5_VREG_CFG__reg_on_mode__SHIFT 0x5
++#define DC_COMBOPHYPLLREGS5_VREG_CFG__rlad_tap_sel__SHIFT 0x7
++#define DC_COMBOPHYPLLREGS5_VREG_CFG__reg_off_hi__SHIFT 0xb
++#define DC_COMBOPHYPLLREGS5_VREG_CFG__reg_off_lo__SHIFT 0xc
++#define DC_COMBOPHYPLLREGS5_VREG_CFG__scale_driver__SHIFT 0xd
++#define DC_COMBOPHYPLLREGS5_VREG_CFG__sel_bump__SHIFT 0xf
++#define DC_COMBOPHYPLLREGS5_VREG_CFG__sel_rladder_x__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS5_VREG_CFG__short_rc_filt_x__SHIFT 0x11
++#define DC_COMBOPHYPLLREGS5_VREG_CFG__vref_pwr_on__SHIFT 0x12
++#define DC_COMBOPHYPLLREGS5_VREG_CFG__dpll_cfg_2__SHIFT 0x14
++#define DC_COMBOPHYPLLREGS5_VREG_CFG__bleeder_ac_MASK 0x00000001L
++#define DC_COMBOPHYPLLREGS5_VREG_CFG__bleeder_en_MASK 0x00000002L
++#define DC_COMBOPHYPLLREGS5_VREG_CFG__is_1p2_MASK 0x00000004L
++#define DC_COMBOPHYPLLREGS5_VREG_CFG__reg_obs_sel_MASK 0x00000018L
++#define DC_COMBOPHYPLLREGS5_VREG_CFG__reg_on_mode_MASK 0x00000060L
++#define DC_COMBOPHYPLLREGS5_VREG_CFG__rlad_tap_sel_MASK 0x00000780L
++#define DC_COMBOPHYPLLREGS5_VREG_CFG__reg_off_hi_MASK 0x00000800L
++#define DC_COMBOPHYPLLREGS5_VREG_CFG__reg_off_lo_MASK 0x00001000L
++#define DC_COMBOPHYPLLREGS5_VREG_CFG__scale_driver_MASK 0x00006000L
++#define DC_COMBOPHYPLLREGS5_VREG_CFG__sel_bump_MASK 0x00008000L
++#define DC_COMBOPHYPLLREGS5_VREG_CFG__sel_rladder_x_MASK 0x00010000L
++#define DC_COMBOPHYPLLREGS5_VREG_CFG__short_rc_filt_x_MASK 0x00020000L
++#define DC_COMBOPHYPLLREGS5_VREG_CFG__vref_pwr_on_MASK 0x00040000L
++#define DC_COMBOPHYPLLREGS5_VREG_CFG__dpll_cfg_2_MASK 0x0FF00000L
++//DC_COMBOPHYPLLREGS5_OBSERVE0
++#define DC_COMBOPHYPLLREGS5_OBSERVE0__lock_det_tdc_steps__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS5_OBSERVE0__clear_sticky_lock__SHIFT 0x6
++#define DC_COMBOPHYPLLREGS5_OBSERVE0__lock_det_dis__SHIFT 0x8
++#define DC_COMBOPHYPLLREGS5_OBSERVE0__dco_cfg__SHIFT 0xa
++#define DC_COMBOPHYPLLREGS5_OBSERVE0__anaobs_sel__SHIFT 0x15
++#define DC_COMBOPHYPLLREGS5_OBSERVE0__lock_det_tdc_steps_MASK 0x0000001FL
++#define DC_COMBOPHYPLLREGS5_OBSERVE0__clear_sticky_lock_MASK 0x00000040L
++#define DC_COMBOPHYPLLREGS5_OBSERVE0__lock_det_dis_MASK 0x00000100L
++#define DC_COMBOPHYPLLREGS5_OBSERVE0__dco_cfg_MASK 0x0003FC00L
++#define DC_COMBOPHYPLLREGS5_OBSERVE0__anaobs_sel_MASK 0x00E00000L
++//DC_COMBOPHYPLLREGS5_OBSERVE1
++#define DC_COMBOPHYPLLREGS5_OBSERVE1__digobs_sel__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS5_OBSERVE1__digobs_trig_sel__SHIFT 0x5
++#define DC_COMBOPHYPLLREGS5_OBSERVE1__digobs_div__SHIFT 0xa
++#define DC_COMBOPHYPLLREGS5_OBSERVE1__digobs_trig_div__SHIFT 0xd
++#define DC_COMBOPHYPLLREGS5_OBSERVE1__lock_timer__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS5_OBSERVE1__digobs_sel_MASK 0x0000000FL
++#define DC_COMBOPHYPLLREGS5_OBSERVE1__digobs_trig_sel_MASK 0x000001E0L
++#define DC_COMBOPHYPLLREGS5_OBSERVE1__digobs_div_MASK 0x00000C00L
++#define DC_COMBOPHYPLLREGS5_OBSERVE1__digobs_trig_div_MASK 0x00006000L
++#define DC_COMBOPHYPLLREGS5_OBSERVE1__lock_timer_MASK 0x3FFF0000L
++//DC_COMBOPHYPLLREGS5_DFT_OUT
++#define DC_COMBOPHYPLLREGS5_DFT_OUT__dft_data__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS5_DFT_OUT__dft_data_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dcio_uniphy6_dispdec
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED58
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED59
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED60
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED61
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED62
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED63
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED64
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED65
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED66
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED67
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED68
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED69
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED70
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED71
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED72
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED73
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED74
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED75
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED76
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED77
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED78
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED79
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED80
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED81
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED82
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED83
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED84
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED85
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED86
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED87
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED88
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED89
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED90
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED91
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED92
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED93
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED94
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED95
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED96
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED97
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED98
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED99
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED100
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED101
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED102
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED103
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED104
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED105
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED106
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED107
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED108
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED109
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED110
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED111
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED112
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED113
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED114
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED115
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED116
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED117
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED118
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED119
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED120
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED121
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED122
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED123
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED124
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED125
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED126
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED127
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED128
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED129
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED130
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED131
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED132
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED133
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED134
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED135
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED136
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED137
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED138
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED139
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED140
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED141
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED142
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED143
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED144
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED145
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED146
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED147
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED148
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED149
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED150
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED151
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED152
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED153
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED154
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED155
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED156
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED157
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED158
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED159
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dc_combophycmregs6_dispdec
++//DC_COMBOPHYCMREGS6_COMMON_FUSE1
++#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_valid__SHIFT 0x0
++#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_unpopulated0__SHIFT 0x1
++#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_ron_override_val__SHIFT 0x3
++#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_unpopulated1__SHIFT 0x9
++#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0xa
++#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_unpopulated2__SHIFT 0xc
++#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_rtt_override_val__SHIFT 0xd
++#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_unpopulated3__SHIFT 0x13
++#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0x14
++#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_refresh_cal_en__SHIFT 0x16
++#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_spare__SHIFT 0x17
++#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_valid_MASK 0x00000001L
++#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_unpopulated0_MASK 0x00000006L
++#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_ron_override_val_MASK 0x000001F8L
++#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_unpopulated1_MASK 0x00000200L
++#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x00000C00L
++#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_unpopulated2_MASK 0x00001000L
++#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_rtt_override_val_MASK 0x0007E000L
++#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_unpopulated3_MASK 0x00080000L
++#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x00300000L
++#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_refresh_cal_en_MASK 0x00400000L
++#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_spare_MASK 0xFF800000L
++//DC_COMBOPHYCMREGS6_COMMON_FUSE2
++#define DC_COMBOPHYCMREGS6_COMMON_FUSE2__fuse2_valid__SHIFT 0x0
++#define DC_COMBOPHYCMREGS6_COMMON_FUSE2__fuse2_unpopulated__SHIFT 0x1
++#define DC_COMBOPHYCMREGS6_COMMON_FUSE2__fuse2_tx_fifo_ptr__SHIFT 0x9
++#define DC_COMBOPHYCMREGS6_COMMON_FUSE2__fuse2_spare__SHIFT 0xe
++#define DC_COMBOPHYCMREGS6_COMMON_FUSE2__fuse2_valid_MASK 0x00000001L
++#define DC_COMBOPHYCMREGS6_COMMON_FUSE2__fuse2_unpopulated_MASK 0x000001FEL
++#define DC_COMBOPHYCMREGS6_COMMON_FUSE2__fuse2_tx_fifo_ptr_MASK 0x00003E00L
++#define DC_COMBOPHYCMREGS6_COMMON_FUSE2__fuse2_spare_MASK 0xFFFFC000L
++//DC_COMBOPHYCMREGS6_COMMON_FUSE3
++#define DC_COMBOPHYCMREGS6_COMMON_FUSE3__fuse3_valid__SHIFT 0x0
++#define DC_COMBOPHYCMREGS6_COMMON_FUSE3__fuse3_unpopulated__SHIFT 0x1
++#define DC_COMBOPHYCMREGS6_COMMON_FUSE3__fuse3_ei_det_thresh_sel__SHIFT 0xa
++#define DC_COMBOPHYCMREGS6_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d
++#define DC_COMBOPHYCMREGS6_COMMON_FUSE3__fuse3_valid_MASK 0x00000001L
++#define DC_COMBOPHYCMREGS6_COMMON_FUSE3__fuse3_unpopulated_MASK 0x000003FEL
++#define DC_COMBOPHYCMREGS6_COMMON_FUSE3__fuse3_ei_det_thresh_sel_MASK 0x00001C00L
++#define DC_COMBOPHYCMREGS6_COMMON_FUSE3__fuse3_spare_MASK 0xE0000000L
++//DC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM
++#define DC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0
++#define DC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8
++#define DC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10
++#define DC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18
++#define DC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0x000000FFL
++#define DC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0x0000FF00L
++#define DC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0x00FF0000L
++#define DC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xFF000000L
++//DC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT
++#define DC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0
++#define DC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4
++#define DC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT__vprot_en__SHIFT 0xb
++#define DC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT__pgdelay_MASK 0x0000000FL
++#define DC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT__pgmask_MASK 0x000003F0L
++#define DC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT__vprot_en_MASK 0x00000800L
++//DC_COMBOPHYCMREGS6_COMMON_TXCNTRL
++#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT 0x0
++#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__clkgate_dis__SHIFT 0x5
++#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT 0x6
++#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT 0x9
++#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT 0xc
++#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__dual_dvi_mstr_en__SHIFT 0xf
++#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__dual_dvi_en__SHIFT 0x10
++#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK 0x0000001FL
++#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__clkgate_dis_MASK 0x00000020L
++#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK 0x000001C0L
++#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK 0x00000E00L
++#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK 0x00007000L
++#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__dual_dvi_mstr_en_MASK 0x00008000L
++#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__dual_dvi_en_MASK 0x00010000L
++//DC_COMBOPHYCMREGS6_COMMON_TMDP
++#define DC_COMBOPHYCMREGS6_COMMON_TMDP__tmdp_spare__SHIFT 0x0
++#define DC_COMBOPHYCMREGS6_COMMON_TMDP__tmdp_spare_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS
++#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_0_reset_l__SHIFT 0x0
++#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_1_reset_l__SHIFT 0x1
++#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_2_reset_l__SHIFT 0x2
++#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_3_reset_l__SHIFT 0x3
++#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_4_reset_l__SHIFT 0x4
++#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_5_reset_l__SHIFT 0x5
++#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_6_reset_l__SHIFT 0x6
++#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_7_reset_l__SHIFT 0x7
++#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_0_reset_l_MASK 0x00000001L
++#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_1_reset_l_MASK 0x00000002L
++#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_2_reset_l_MASK 0x00000004L
++#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_3_reset_l_MASK 0x00000008L
++#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_4_reset_l_MASK 0x00000010L
++#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_5_reset_l_MASK 0x00000020L
++#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_6_reset_l_MASK 0x00000040L
++#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_7_reset_l_MASK 0x00000080L
++//DC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL
++#define DC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT 0x0
++#define DC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT 0x1
++#define DC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT 0x15
++#define DC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL__zcalcode_override_MASK 0x00000001L
++#define DC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK 0x0000003EL
++#define DC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK 0x00200000L
++//DC_COMBOPHYCMREGS6_COMMON_DISP_RFU1
++#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU1__rfu_value1__SHIFT 0x0
++#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU1__rfu_value1_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS6_COMMON_DISP_RFU2
++#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU2__rfu_value2__SHIFT 0x0
++#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU2__rfu_value2_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS6_COMMON_DISP_RFU3
++#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU3__rfu_value3__SHIFT 0x0
++#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU3__rfu_value3_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS6_COMMON_DISP_RFU4
++#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU4__rfu_value4__SHIFT 0x0
++#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU4__rfu_value4_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS6_COMMON_DISP_RFU5
++#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU5__rfu_value5__SHIFT 0x0
++#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU5__rfu_value5_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS6_COMMON_DISP_RFU6
++#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU6__rfu_value6__SHIFT 0x0
++#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU6__rfu_value6_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS6_COMMON_DISP_RFU7
++#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU7__rfu_value7__SHIFT 0x0
++#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU7__rfu_value7_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dc_combophytxregs6_dispdec
++//DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0
++#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3
++#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT 0x8
++#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK 0x00000100L
++//DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0
++#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT 0x3
++#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT 0x5
++#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0__txmarg_sel_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0__deemph_sel_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0__tx_margin_en_MASK 0x00000020L
++//DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x1
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x3
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT 0x8
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT 0xa
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT 0xc
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT 0xd
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT 0xe
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT 0xf
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT 0x10
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT 0x14
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT 0x16
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x00000006L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0x000000E0L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK 0x00000300L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK 0x00000C00L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK 0x00001000L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK 0x00002000L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK 0x00004000L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK 0x00008000L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK 0x000F0000L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK 0x00100000L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK 0x00C00000L
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE0__rfu_value0__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE0__rfu_value0_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE0__rfu_value1__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE0__rfu_value1_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE0__rfu_value2__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE0__rfu_value2_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE0__rfu_value3__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE0__rfu_value3_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE0__rfu_value4__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE0__rfu_value4_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE0__rfu_value5__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE0__rfu_value5_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE0__rfu_value6__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE0__rfu_value6_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE0__rfu_value7__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE0__rfu_value7_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE0__rfu_value8__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE0__rfu_value8_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE0__rfu_value9__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE0__rfu_value9_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE0__rfu_value10__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE0__rfu_value10_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE0__rfu_value11__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE0__rfu_value11_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE0__rfu_value12__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE0__rfu_value12_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1
++#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3
++#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT 0x8
++#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK 0x00000100L
++//DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1
++#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT 0x3
++#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT 0x5
++#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1__txmarg_sel_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1__deemph_sel_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1__tx_margin_en_MASK 0x00000020L
++//DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x1
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x3
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT 0x8
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT 0xa
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT 0xc
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT 0xd
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT 0xe
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT 0xf
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT 0x10
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT 0x14
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT 0x16
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x00000006L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0x000000E0L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK 0x00000300L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK 0x00000C00L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK 0x00001000L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK 0x00002000L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK 0x00004000L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK 0x00008000L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK 0x000F0000L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK 0x00100000L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK 0x00C00000L
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE1
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE1__rfu_value0__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE1__rfu_value0_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE1
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE1__rfu_value1__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE1__rfu_value1_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE1
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE1__rfu_value2__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE1__rfu_value2_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE1
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE1__rfu_value3__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE1__rfu_value3_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE1
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE1__rfu_value4__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE1__rfu_value4_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE1
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE1__rfu_value5__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE1__rfu_value5_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE1
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE1__rfu_value6__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE1__rfu_value6_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE1
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE1__rfu_value7__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE1__rfu_value7_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE1
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE1__rfu_value8__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE1__rfu_value8_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE1
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE1__rfu_value9__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE1__rfu_value9_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE1
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE1__rfu_value10__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE1__rfu_value10_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE1
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE1__rfu_value11__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE1__rfu_value11_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE1
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE1__rfu_value12__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE1__rfu_value12_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2
++#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3
++#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT 0x8
++#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK 0x00000100L
++//DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2
++#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT 0x3
++#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT 0x5
++#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2__txmarg_sel_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2__deemph_sel_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2__tx_margin_en_MASK 0x00000020L
++//DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x1
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x3
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT 0x8
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT 0xa
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT 0xc
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT 0xd
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT 0xe
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT 0xf
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT 0x10
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT 0x14
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT 0x16
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x00000006L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0x000000E0L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK 0x00000300L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK 0x00000C00L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK 0x00001000L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK 0x00002000L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK 0x00004000L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK 0x00008000L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK 0x000F0000L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK 0x00100000L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK 0x00C00000L
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE2
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE2__rfu_value0__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE2__rfu_value0_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE2
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE2__rfu_value1__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE2__rfu_value1_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE2
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE2__rfu_value2__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE2__rfu_value2_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE2
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE2__rfu_value3__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE2__rfu_value3_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE2
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE2__rfu_value4__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE2__rfu_value4_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE2
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE2__rfu_value5__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE2__rfu_value5_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE2
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE2__rfu_value6__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE2__rfu_value6_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE2
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE2__rfu_value7__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE2__rfu_value7_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE2
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE2__rfu_value8__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE2__rfu_value8_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE2
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE2__rfu_value9__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE2__rfu_value9_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE2
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE2__rfu_value10__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE2__rfu_value10_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE2
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE2__rfu_value11__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE2__rfu_value11_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE2
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE2__rfu_value12__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE2__rfu_value12_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3
++#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3
++#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT 0x8
++#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK 0x00000100L
++//DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3
++#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT 0x3
++#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT 0x5
++#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3__txmarg_sel_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3__deemph_sel_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3__tx_margin_en_MASK 0x00000020L
++//DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x1
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x3
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT 0x8
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT 0xa
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT 0xc
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT 0xd
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT 0xe
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT 0xf
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT 0x10
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT 0x14
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT 0x16
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x00000006L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0x000000E0L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK 0x00000300L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK 0x00000C00L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK 0x00001000L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK 0x00002000L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK 0x00004000L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK 0x00008000L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK 0x000F0000L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK 0x00100000L
++#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK 0x00C00000L
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE3
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE3__rfu_value0__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE3__rfu_value0_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE3
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE3__rfu_value1__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE3__rfu_value1_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE3
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE3__rfu_value2__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE3__rfu_value2_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE3
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE3__rfu_value3__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE3__rfu_value3_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE3
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE3__rfu_value4__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE3__rfu_value4_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE3
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE3__rfu_value5__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE3__rfu_value5_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE3
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE3__rfu_value6__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE3__rfu_value6_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE3
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE3__rfu_value7__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE3__rfu_value7_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE3
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE3__rfu_value8__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE3__rfu_value8_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE3
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE3__rfu_value9__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE3__rfu_value9_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE3
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE3__rfu_value10__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE3__rfu_value10_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE3
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE3__rfu_value11__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE3__rfu_value11_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE3
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE3__rfu_value12__SHIFT 0x0
++#define DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE3__rfu_value12_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dc_combophypllregs6_dispdec
++//DC_COMBOPHYPLLREGS6_FREQ_CTRL0
++#define DC_COMBOPHYPLLREGS6_FREQ_CTRL0__fcw0_frac__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS6_FREQ_CTRL0__fcw0_int__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS6_FREQ_CTRL0__fcw0_frac_MASK 0x0000FFFFL
++#define DC_COMBOPHYPLLREGS6_FREQ_CTRL0__fcw0_int_MASK 0x01FF0000L
++//DC_COMBOPHYPLLREGS6_FREQ_CTRL1
++#define DC_COMBOPHYPLLREGS6_FREQ_CTRL1__fcw1_frac__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS6_FREQ_CTRL1__fcw1_int__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS6_FREQ_CTRL1__fcw1_frac_MASK 0x0000FFFFL
++#define DC_COMBOPHYPLLREGS6_FREQ_CTRL1__fcw1_int_MASK 0x01FF0000L
++//DC_COMBOPHYPLLREGS6_FREQ_CTRL2
++#define DC_COMBOPHYPLLREGS6_FREQ_CTRL2__fcw_denom__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS6_FREQ_CTRL2__fcw_slew_frac__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS6_FREQ_CTRL2__fcw_denom_MASK 0x0000FFFFL
++#define DC_COMBOPHYPLLREGS6_FREQ_CTRL2__fcw_slew_frac_MASK 0xFFFF0000L
++//DC_COMBOPHYPLLREGS6_FREQ_CTRL3
++#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__refclk_div__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__vco_pre_div__SHIFT 0x3
++#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__fracn_en__SHIFT 0x6
++#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__ssc_en__SHIFT 0x8
++#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__fcw_sel__SHIFT 0xa
++#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__freq_jump_en__SHIFT 0xc
++#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__tdc_resolution__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__dpll_cfg_1__SHIFT 0x18
++#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__refclk_div_MASK 0x00000003L
++#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__vco_pre_div_MASK 0x00000018L
++#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__fracn_en_MASK 0x00000040L
++#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__ssc_en_MASK 0x00000100L
++#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__fcw_sel_MASK 0x00000400L
++#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__freq_jump_en_MASK 0x00001000L
++#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__tdc_resolution_MASK 0x00FF0000L
++#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__dpll_cfg_1_MASK 0xFF000000L
++//DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE
++#define DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__gi_coarse_mant__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__gi_coarse_exp__SHIFT 0x2
++#define DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__gp_coarse_mant__SHIFT 0x7
++#define DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__gp_coarse_exp__SHIFT 0xc
++#define DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__nctl_coarse_res__SHIFT 0x11
++#define DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT 0x18
++#define DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__gi_coarse_mant_MASK 0x00000003L
++#define DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__gi_coarse_exp_MASK 0x0000003CL
++#define DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__gp_coarse_mant_MASK 0x00000780L
++#define DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__gp_coarse_exp_MASK 0x0000F000L
++#define DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__nctl_coarse_res_MASK 0x007E0000L
++#define DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__nctl_coarse_frac_res_MASK 0x03000000L
++//DC_COMBOPHYPLLREGS6_BW_CTRL_FINE
++#define DC_COMBOPHYPLLREGS6_BW_CTRL_FINE__dpll_cfg_3__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS6_BW_CTRL_FINE__dpll_cfg_3_MASK 0x000003FFL
++//DC_COMBOPHYPLLREGS6_CAL_CTRL
++#define DC_COMBOPHYPLLREGS6_CAL_CTRL__bypass_freq_lock__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS6_CAL_CTRL__tdc_cal_en__SHIFT 0x1
++#define DC_COMBOPHYPLLREGS6_CAL_CTRL__tdc_cal_ctrl__SHIFT 0x3
++#define DC_COMBOPHYPLLREGS6_CAL_CTRL__meas_win_sel__SHIFT 0x9
++#define DC_COMBOPHYPLLREGS6_CAL_CTRL__kdco_cal_dis__SHIFT 0xb
++#define DC_COMBOPHYPLLREGS6_CAL_CTRL__kdco_ratio__SHIFT 0xd
++#define DC_COMBOPHYPLLREGS6_CAL_CTRL__kdco_incr_cal_dis__SHIFT 0x16
++#define DC_COMBOPHYPLLREGS6_CAL_CTRL__nctl_adj_dis__SHIFT 0x17
++#define DC_COMBOPHYPLLREGS6_CAL_CTRL__refclk_rate__SHIFT 0x18
++#define DC_COMBOPHYPLLREGS6_CAL_CTRL__bypass_freq_lock_MASK 0x00000001L
++#define DC_COMBOPHYPLLREGS6_CAL_CTRL__tdc_cal_en_MASK 0x00000002L
++#define DC_COMBOPHYPLLREGS6_CAL_CTRL__tdc_cal_ctrl_MASK 0x000001F8L
++#define DC_COMBOPHYPLLREGS6_CAL_CTRL__meas_win_sel_MASK 0x00000600L
++#define DC_COMBOPHYPLLREGS6_CAL_CTRL__kdco_cal_dis_MASK 0x00000800L
++#define DC_COMBOPHYPLLREGS6_CAL_CTRL__kdco_ratio_MASK 0x001FE000L
++#define DC_COMBOPHYPLLREGS6_CAL_CTRL__kdco_incr_cal_dis_MASK 0x00400000L
++#define DC_COMBOPHYPLLREGS6_CAL_CTRL__nctl_adj_dis_MASK 0x00800000L
++#define DC_COMBOPHYPLLREGS6_CAL_CTRL__refclk_rate_MASK 0xFF000000L
++//DC_COMBOPHYPLLREGS6_LOOP_CTRL
++#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__fbdiv_mask_en__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__fb_slip_dis__SHIFT 0x2
++#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__clk_tdc_sel__SHIFT 0x4
++#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__clk_nctl_sel__SHIFT 0x7
++#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__sig_del_patt_sel__SHIFT 0xa
++#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__nctl_sig_del_dis__SHIFT 0xc
++#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__fbclk_track_refclk__SHIFT 0xe
++#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__prbs_en__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__tdc_clk_gate_en__SHIFT 0x12
++#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__phase_offset__SHIFT 0x14
++#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__fbdiv_mask_en_MASK 0x00000001L
++#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__fb_slip_dis_MASK 0x00000004L
++#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__clk_tdc_sel_MASK 0x00000030L
++#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__clk_nctl_sel_MASK 0x00000180L
++#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__sig_del_patt_sel_MASK 0x00000400L
++#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__nctl_sig_del_dis_MASK 0x00001000L
++#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__fbclk_track_refclk_MASK 0x00004000L
++#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__prbs_en_MASK 0x00010000L
++#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__tdc_clk_gate_en_MASK 0x00040000L
++#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__phase_offset_MASK 0x07F00000L
++//DC_COMBOPHYPLLREGS6_VREG_CFG
++#define DC_COMBOPHYPLLREGS6_VREG_CFG__bleeder_ac__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS6_VREG_CFG__bleeder_en__SHIFT 0x1
++#define DC_COMBOPHYPLLREGS6_VREG_CFG__is_1p2__SHIFT 0x2
++#define DC_COMBOPHYPLLREGS6_VREG_CFG__reg_obs_sel__SHIFT 0x3
++#define DC_COMBOPHYPLLREGS6_VREG_CFG__reg_on_mode__SHIFT 0x5
++#define DC_COMBOPHYPLLREGS6_VREG_CFG__rlad_tap_sel__SHIFT 0x7
++#define DC_COMBOPHYPLLREGS6_VREG_CFG__reg_off_hi__SHIFT 0xb
++#define DC_COMBOPHYPLLREGS6_VREG_CFG__reg_off_lo__SHIFT 0xc
++#define DC_COMBOPHYPLLREGS6_VREG_CFG__scale_driver__SHIFT 0xd
++#define DC_COMBOPHYPLLREGS6_VREG_CFG__sel_bump__SHIFT 0xf
++#define DC_COMBOPHYPLLREGS6_VREG_CFG__sel_rladder_x__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS6_VREG_CFG__short_rc_filt_x__SHIFT 0x11
++#define DC_COMBOPHYPLLREGS6_VREG_CFG__vref_pwr_on__SHIFT 0x12
++#define DC_COMBOPHYPLLREGS6_VREG_CFG__dpll_cfg_2__SHIFT 0x14
++#define DC_COMBOPHYPLLREGS6_VREG_CFG__bleeder_ac_MASK 0x00000001L
++#define DC_COMBOPHYPLLREGS6_VREG_CFG__bleeder_en_MASK 0x00000002L
++#define DC_COMBOPHYPLLREGS6_VREG_CFG__is_1p2_MASK 0x00000004L
++#define DC_COMBOPHYPLLREGS6_VREG_CFG__reg_obs_sel_MASK 0x00000018L
++#define DC_COMBOPHYPLLREGS6_VREG_CFG__reg_on_mode_MASK 0x00000060L
++#define DC_COMBOPHYPLLREGS6_VREG_CFG__rlad_tap_sel_MASK 0x00000780L
++#define DC_COMBOPHYPLLREGS6_VREG_CFG__reg_off_hi_MASK 0x00000800L
++#define DC_COMBOPHYPLLREGS6_VREG_CFG__reg_off_lo_MASK 0x00001000L
++#define DC_COMBOPHYPLLREGS6_VREG_CFG__scale_driver_MASK 0x00006000L
++#define DC_COMBOPHYPLLREGS6_VREG_CFG__sel_bump_MASK 0x00008000L
++#define DC_COMBOPHYPLLREGS6_VREG_CFG__sel_rladder_x_MASK 0x00010000L
++#define DC_COMBOPHYPLLREGS6_VREG_CFG__short_rc_filt_x_MASK 0x00020000L
++#define DC_COMBOPHYPLLREGS6_VREG_CFG__vref_pwr_on_MASK 0x00040000L
++#define DC_COMBOPHYPLLREGS6_VREG_CFG__dpll_cfg_2_MASK 0x0FF00000L
++//DC_COMBOPHYPLLREGS6_OBSERVE0
++#define DC_COMBOPHYPLLREGS6_OBSERVE0__lock_det_tdc_steps__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS6_OBSERVE0__clear_sticky_lock__SHIFT 0x6
++#define DC_COMBOPHYPLLREGS6_OBSERVE0__lock_det_dis__SHIFT 0x8
++#define DC_COMBOPHYPLLREGS6_OBSERVE0__dco_cfg__SHIFT 0xa
++#define DC_COMBOPHYPLLREGS6_OBSERVE0__anaobs_sel__SHIFT 0x15
++#define DC_COMBOPHYPLLREGS6_OBSERVE0__lock_det_tdc_steps_MASK 0x0000001FL
++#define DC_COMBOPHYPLLREGS6_OBSERVE0__clear_sticky_lock_MASK 0x00000040L
++#define DC_COMBOPHYPLLREGS6_OBSERVE0__lock_det_dis_MASK 0x00000100L
++#define DC_COMBOPHYPLLREGS6_OBSERVE0__dco_cfg_MASK 0x0003FC00L
++#define DC_COMBOPHYPLLREGS6_OBSERVE0__anaobs_sel_MASK 0x00E00000L
++//DC_COMBOPHYPLLREGS6_OBSERVE1
++#define DC_COMBOPHYPLLREGS6_OBSERVE1__digobs_sel__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS6_OBSERVE1__digobs_trig_sel__SHIFT 0x5
++#define DC_COMBOPHYPLLREGS6_OBSERVE1__digobs_div__SHIFT 0xa
++#define DC_COMBOPHYPLLREGS6_OBSERVE1__digobs_trig_div__SHIFT 0xd
++#define DC_COMBOPHYPLLREGS6_OBSERVE1__lock_timer__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS6_OBSERVE1__digobs_sel_MASK 0x0000000FL
++#define DC_COMBOPHYPLLREGS6_OBSERVE1__digobs_trig_sel_MASK 0x000001E0L
++#define DC_COMBOPHYPLLREGS6_OBSERVE1__digobs_div_MASK 0x00000C00L
++#define DC_COMBOPHYPLLREGS6_OBSERVE1__digobs_trig_div_MASK 0x00006000L
++#define DC_COMBOPHYPLLREGS6_OBSERVE1__lock_timer_MASK 0x3FFF0000L
++//DC_COMBOPHYPLLREGS6_DFT_OUT
++#define DC_COMBOPHYPLLREGS6_DFT_OUT__dft_data__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS6_DFT_OUT__dft_data_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dcio_uniphy8_dispdec
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED32
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED33
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED34
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED35
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED36
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED37
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED38
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED39
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED40
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED41
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED42
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED43
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED44
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED45
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED46
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED47
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED48
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED49
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED50
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED51
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED52
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED53
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED54
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED55
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED56
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED57
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED58
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED59
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED60
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED61
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED62
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED63
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED64
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED65
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED66
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED67
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED68
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED69
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED70
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED71
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED72
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED73
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED74
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED75
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED76
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED77
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED78
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED79
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED80
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED81
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED82
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED83
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED84
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED85
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED86
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED87
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED88
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED89
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED90
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED91
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED92
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED93
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED94
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED95
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED96
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED97
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED98
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED99
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED100
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED101
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED102
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED103
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED104
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED105
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED106
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED107
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED108
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED109
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED110
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED111
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED112
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED113
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED114
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED115
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED116
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED117
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED118
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED119
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED120
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED121
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED122
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED123
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED124
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED125
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED126
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED127
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED128
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED129
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED130
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED131
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED132
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED133
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED134
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED135
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED136
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED137
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED138
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED139
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED140
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED141
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED142
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED143
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED144
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED145
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED146
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED147
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED148
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED149
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED150
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED151
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED152
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED153
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED154
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED155
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED156
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED157
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED158
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED159
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dc_combophycmregs8_dispdec
++//DC_COMBOPHYCMREGS8_COMMON_FUSE1
++#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_valid__SHIFT 0x0
++#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_unpopulated0__SHIFT 0x1
++#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_ron_override_val__SHIFT 0x3
++#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_unpopulated1__SHIFT 0x9
++#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0xa
++#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_unpopulated2__SHIFT 0xc
++#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_rtt_override_val__SHIFT 0xd
++#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_unpopulated3__SHIFT 0x13
++#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0x14
++#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_refresh_cal_en__SHIFT 0x16
++#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_spare__SHIFT 0x17
++#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_valid_MASK 0x00000001L
++#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_unpopulated0_MASK 0x00000006L
++#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_ron_override_val_MASK 0x000001F8L
++#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_unpopulated1_MASK 0x00000200L
++#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x00000C00L
++#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_unpopulated2_MASK 0x00001000L
++#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_rtt_override_val_MASK 0x0007E000L
++#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_unpopulated3_MASK 0x00080000L
++#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x00300000L
++#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_refresh_cal_en_MASK 0x00400000L
++#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_spare_MASK 0xFF800000L
++//DC_COMBOPHYCMREGS8_COMMON_FUSE2
++#define DC_COMBOPHYCMREGS8_COMMON_FUSE2__fuse2_valid__SHIFT 0x0
++#define DC_COMBOPHYCMREGS8_COMMON_FUSE2__fuse2_unpopulated__SHIFT 0x1
++#define DC_COMBOPHYCMREGS8_COMMON_FUSE2__fuse2_tx_fifo_ptr__SHIFT 0x9
++#define DC_COMBOPHYCMREGS8_COMMON_FUSE2__fuse2_spare__SHIFT 0xe
++#define DC_COMBOPHYCMREGS8_COMMON_FUSE2__fuse2_valid_MASK 0x00000001L
++#define DC_COMBOPHYCMREGS8_COMMON_FUSE2__fuse2_unpopulated_MASK 0x000001FEL
++#define DC_COMBOPHYCMREGS8_COMMON_FUSE2__fuse2_tx_fifo_ptr_MASK 0x00003E00L
++#define DC_COMBOPHYCMREGS8_COMMON_FUSE2__fuse2_spare_MASK 0xFFFFC000L
++//DC_COMBOPHYCMREGS8_COMMON_FUSE3
++#define DC_COMBOPHYCMREGS8_COMMON_FUSE3__fuse3_valid__SHIFT 0x0
++#define DC_COMBOPHYCMREGS8_COMMON_FUSE3__fuse3_unpopulated__SHIFT 0x1
++#define DC_COMBOPHYCMREGS8_COMMON_FUSE3__fuse3_ei_det_thresh_sel__SHIFT 0xa
++#define DC_COMBOPHYCMREGS8_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d
++#define DC_COMBOPHYCMREGS8_COMMON_FUSE3__fuse3_valid_MASK 0x00000001L
++#define DC_COMBOPHYCMREGS8_COMMON_FUSE3__fuse3_unpopulated_MASK 0x000003FEL
++#define DC_COMBOPHYCMREGS8_COMMON_FUSE3__fuse3_ei_det_thresh_sel_MASK 0x00001C00L
++#define DC_COMBOPHYCMREGS8_COMMON_FUSE3__fuse3_spare_MASK 0xE0000000L
++//DC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM
++#define DC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0
++#define DC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8
++#define DC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10
++#define DC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18
++#define DC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0x000000FFL
++#define DC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0x0000FF00L
++#define DC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0x00FF0000L
++#define DC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xFF000000L
++//DC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT
++#define DC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0
++#define DC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4
++#define DC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT__vprot_en__SHIFT 0xb
++#define DC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT__pgdelay_MASK 0x0000000FL
++#define DC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT__pgmask_MASK 0x000003F0L
++#define DC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT__vprot_en_MASK 0x00000800L
++//DC_COMBOPHYCMREGS8_COMMON_TXCNTRL
++#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT 0x0
++#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__clkgate_dis__SHIFT 0x5
++#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT 0x6
++#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT 0x9
++#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT 0xc
++#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__dual_dvi_mstr_en__SHIFT 0xf
++#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__dual_dvi_en__SHIFT 0x10
++#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK 0x0000001FL
++#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__clkgate_dis_MASK 0x00000020L
++#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK 0x000001C0L
++#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK 0x00000E00L
++#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK 0x00007000L
++#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__dual_dvi_mstr_en_MASK 0x00008000L
++#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__dual_dvi_en_MASK 0x00010000L
++//DC_COMBOPHYCMREGS8_COMMON_TMDP
++#define DC_COMBOPHYCMREGS8_COMMON_TMDP__tmdp_spare__SHIFT 0x0
++#define DC_COMBOPHYCMREGS8_COMMON_TMDP__tmdp_spare_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS
++#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_0_reset_l__SHIFT 0x0
++#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_1_reset_l__SHIFT 0x1
++#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_2_reset_l__SHIFT 0x2
++#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_3_reset_l__SHIFT 0x3
++#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_4_reset_l__SHIFT 0x4
++#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_5_reset_l__SHIFT 0x5
++#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_6_reset_l__SHIFT 0x6
++#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_7_reset_l__SHIFT 0x7
++#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_0_reset_l_MASK 0x00000001L
++#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_1_reset_l_MASK 0x00000002L
++#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_2_reset_l_MASK 0x00000004L
++#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_3_reset_l_MASK 0x00000008L
++#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_4_reset_l_MASK 0x00000010L
++#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_5_reset_l_MASK 0x00000020L
++#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_6_reset_l_MASK 0x00000040L
++#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_7_reset_l_MASK 0x00000080L
++//DC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL
++#define DC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT 0x0
++#define DC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT 0x1
++#define DC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT 0x15
++#define DC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL__zcalcode_override_MASK 0x00000001L
++#define DC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK 0x0000003EL
++#define DC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK 0x00200000L
++//DC_COMBOPHYCMREGS8_COMMON_DISP_RFU1
++#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU1__rfu_value1__SHIFT 0x0
++#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU1__rfu_value1_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS8_COMMON_DISP_RFU2
++#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU2__rfu_value2__SHIFT 0x0
++#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU2__rfu_value2_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS8_COMMON_DISP_RFU3
++#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU3__rfu_value3__SHIFT 0x0
++#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU3__rfu_value3_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS8_COMMON_DISP_RFU4
++#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU4__rfu_value4__SHIFT 0x0
++#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU4__rfu_value4_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS8_COMMON_DISP_RFU5
++#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU5__rfu_value5__SHIFT 0x0
++#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU5__rfu_value5_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS8_COMMON_DISP_RFU6
++#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU6__rfu_value6__SHIFT 0x0
++#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU6__rfu_value6_MASK 0xFFFFFFFFL
++//DC_COMBOPHYCMREGS8_COMMON_DISP_RFU7
++#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU7__rfu_value7__SHIFT 0x0
++#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU7__rfu_value7_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dc_combophytxregs8_dispdec
++//DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0
++#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3
++#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT 0x8
++#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK 0x00000100L
++//DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0
++#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT 0x3
++#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT 0x5
++#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0__txmarg_sel_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0__deemph_sel_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0__tx_margin_en_MASK 0x00000020L
++//DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x1
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x3
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT 0x8
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT 0xa
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT 0xc
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT 0xd
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT 0xe
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT 0xf
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT 0x10
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT 0x14
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT 0x16
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x00000006L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0x000000E0L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK 0x00000300L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK 0x00000C00L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK 0x00001000L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK 0x00002000L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK 0x00004000L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK 0x00008000L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK 0x000F0000L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK 0x00100000L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK 0x00C00000L
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE0__rfu_value0__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE0__rfu_value0_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE0__rfu_value1__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE0__rfu_value1_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE0__rfu_value2__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE0__rfu_value2_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE0__rfu_value3__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE0__rfu_value3_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE0__rfu_value4__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE0__rfu_value4_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE0__rfu_value5__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE0__rfu_value5_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE0__rfu_value6__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE0__rfu_value6_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE0__rfu_value7__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE0__rfu_value7_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE0__rfu_value8__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE0__rfu_value8_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE0__rfu_value9__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE0__rfu_value9_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE0__rfu_value10__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE0__rfu_value10_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE0__rfu_value11__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE0__rfu_value11_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE0__rfu_value12__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE0__rfu_value12_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1
++#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3
++#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT 0x8
++#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK 0x00000100L
++//DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1
++#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT 0x3
++#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT 0x5
++#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1__txmarg_sel_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1__deemph_sel_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1__tx_margin_en_MASK 0x00000020L
++//DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x1
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x3
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT 0x8
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT 0xa
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT 0xc
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT 0xd
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT 0xe
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT 0xf
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT 0x10
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT 0x14
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT 0x16
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x00000006L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0x000000E0L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK 0x00000300L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK 0x00000C00L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK 0x00001000L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK 0x00002000L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK 0x00004000L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK 0x00008000L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK 0x000F0000L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK 0x00100000L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK 0x00C00000L
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE1
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE1__rfu_value0__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE1__rfu_value0_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE1
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE1__rfu_value1__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE1__rfu_value1_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE1
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE1__rfu_value2__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE1__rfu_value2_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE1
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE1__rfu_value3__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE1__rfu_value3_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE1
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE1__rfu_value4__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE1__rfu_value4_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE1
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE1__rfu_value5__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE1__rfu_value5_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE1
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE1__rfu_value6__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE1__rfu_value6_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE1
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE1__rfu_value7__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE1__rfu_value7_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE1
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE1__rfu_value8__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE1__rfu_value8_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE1
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE1__rfu_value9__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE1__rfu_value9_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE1
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE1__rfu_value10__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE1__rfu_value10_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE1
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE1__rfu_value11__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE1__rfu_value11_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE1
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE1__rfu_value12__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE1__rfu_value12_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2
++#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3
++#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT 0x8
++#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK 0x00000100L
++//DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2
++#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT 0x3
++#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT 0x5
++#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2__txmarg_sel_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2__deemph_sel_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2__tx_margin_en_MASK 0x00000020L
++//DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x1
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x3
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT 0x8
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT 0xa
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT 0xc
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT 0xd
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT 0xe
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT 0xf
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT 0x10
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT 0x14
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT 0x16
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x00000006L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0x000000E0L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK 0x00000300L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK 0x00000C00L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK 0x00001000L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK 0x00002000L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK 0x00004000L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK 0x00008000L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK 0x000F0000L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK 0x00100000L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK 0x00C00000L
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE2
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE2__rfu_value0__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE2__rfu_value0_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE2
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE2__rfu_value1__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE2__rfu_value1_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE2
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE2__rfu_value2__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE2__rfu_value2_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE2
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE2__rfu_value3__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE2__rfu_value3_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE2
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE2__rfu_value4__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE2__rfu_value4_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE2
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE2__rfu_value5__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE2__rfu_value5_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE2
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE2__rfu_value6__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE2__rfu_value6_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE2
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE2__rfu_value7__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE2__rfu_value7_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE2
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE2__rfu_value8__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE2__rfu_value8_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE2
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE2__rfu_value9__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE2__rfu_value9_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE2
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE2__rfu_value10__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE2__rfu_value10_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE2
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE2__rfu_value11__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE2__rfu_value11_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE2
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE2__rfu_value12__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE2__rfu_value12_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3
++#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3
++#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT 0x8
++#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK 0x00000100L
++//DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3
++#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT 0x3
++#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT 0x5
++#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3__txmarg_sel_MASK 0x00000007L
++#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3__deemph_sel_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3__tx_margin_en_MASK 0x00000020L
++//DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x1
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x3
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT 0x8
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT 0xa
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT 0xc
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT 0xd
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT 0xe
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT 0xf
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT 0x10
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT 0x14
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT 0x16
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x00000006L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x00000018L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0x000000E0L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK 0x00000300L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK 0x00000C00L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK 0x00001000L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK 0x00002000L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK 0x00004000L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK 0x00008000L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK 0x000F0000L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK 0x00100000L
++#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK 0x00C00000L
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE3
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE3__rfu_value0__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE3__rfu_value0_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE3
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE3__rfu_value1__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE3__rfu_value1_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE3
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE3__rfu_value2__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE3__rfu_value2_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE3
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE3__rfu_value3__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE3__rfu_value3_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE3
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE3__rfu_value4__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE3__rfu_value4_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE3
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE3__rfu_value5__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE3__rfu_value5_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE3
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE3__rfu_value6__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE3__rfu_value6_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE3
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE3__rfu_value7__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE3__rfu_value7_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE3
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE3__rfu_value8__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE3__rfu_value8_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE3
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE3__rfu_value9__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE3__rfu_value9_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE3
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE3__rfu_value10__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE3__rfu_value10_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE3
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE3__rfu_value11__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE3__rfu_value11_MASK 0xFFFFFFFFL
++//DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE3
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE3__rfu_value12__SHIFT 0x0
++#define DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE3__rfu_value12_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dc_combophypllregs8_dispdec
++//DC_COMBOPHYPLLREGS8_FREQ_CTRL0
++#define DC_COMBOPHYPLLREGS8_FREQ_CTRL0__fcw0_frac__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS8_FREQ_CTRL0__fcw0_int__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS8_FREQ_CTRL0__fcw0_frac_MASK 0x0000FFFFL
++#define DC_COMBOPHYPLLREGS8_FREQ_CTRL0__fcw0_int_MASK 0x01FF0000L
++//DC_COMBOPHYPLLREGS8_FREQ_CTRL1
++#define DC_COMBOPHYPLLREGS8_FREQ_CTRL1__fcw1_frac__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS8_FREQ_CTRL1__fcw1_int__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS8_FREQ_CTRL1__fcw1_frac_MASK 0x0000FFFFL
++#define DC_COMBOPHYPLLREGS8_FREQ_CTRL1__fcw1_int_MASK 0x01FF0000L
++//DC_COMBOPHYPLLREGS8_FREQ_CTRL2
++#define DC_COMBOPHYPLLREGS8_FREQ_CTRL2__fcw_denom__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS8_FREQ_CTRL2__fcw_slew_frac__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS8_FREQ_CTRL2__fcw_denom_MASK 0x0000FFFFL
++#define DC_COMBOPHYPLLREGS8_FREQ_CTRL2__fcw_slew_frac_MASK 0xFFFF0000L
++//DC_COMBOPHYPLLREGS8_FREQ_CTRL3
++#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__refclk_div__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__vco_pre_div__SHIFT 0x3
++#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__fracn_en__SHIFT 0x6
++#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__ssc_en__SHIFT 0x8
++#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__fcw_sel__SHIFT 0xa
++#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__freq_jump_en__SHIFT 0xc
++#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__tdc_resolution__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__dpll_cfg_1__SHIFT 0x18
++#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__refclk_div_MASK 0x00000003L
++#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__vco_pre_div_MASK 0x00000018L
++#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__fracn_en_MASK 0x00000040L
++#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__ssc_en_MASK 0x00000100L
++#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__fcw_sel_MASK 0x00000400L
++#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__freq_jump_en_MASK 0x00001000L
++#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__tdc_resolution_MASK 0x00FF0000L
++#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__dpll_cfg_1_MASK 0xFF000000L
++//DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE
++#define DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__gi_coarse_mant__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__gi_coarse_exp__SHIFT 0x2
++#define DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__gp_coarse_mant__SHIFT 0x7
++#define DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__gp_coarse_exp__SHIFT 0xc
++#define DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__nctl_coarse_res__SHIFT 0x11
++#define DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT 0x18
++#define DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__gi_coarse_mant_MASK 0x00000003L
++#define DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__gi_coarse_exp_MASK 0x0000003CL
++#define DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__gp_coarse_mant_MASK 0x00000780L
++#define DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__gp_coarse_exp_MASK 0x0000F000L
++#define DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__nctl_coarse_res_MASK 0x007E0000L
++#define DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__nctl_coarse_frac_res_MASK 0x03000000L
++//DC_COMBOPHYPLLREGS8_BW_CTRL_FINE
++#define DC_COMBOPHYPLLREGS8_BW_CTRL_FINE__dpll_cfg_3__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS8_BW_CTRL_FINE__dpll_cfg_3_MASK 0x000003FFL
++//DC_COMBOPHYPLLREGS8_CAL_CTRL
++#define DC_COMBOPHYPLLREGS8_CAL_CTRL__bypass_freq_lock__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS8_CAL_CTRL__tdc_cal_en__SHIFT 0x1
++#define DC_COMBOPHYPLLREGS8_CAL_CTRL__tdc_cal_ctrl__SHIFT 0x3
++#define DC_COMBOPHYPLLREGS8_CAL_CTRL__meas_win_sel__SHIFT 0x9
++#define DC_COMBOPHYPLLREGS8_CAL_CTRL__kdco_cal_dis__SHIFT 0xb
++#define DC_COMBOPHYPLLREGS8_CAL_CTRL__kdco_ratio__SHIFT 0xd
++#define DC_COMBOPHYPLLREGS8_CAL_CTRL__kdco_incr_cal_dis__SHIFT 0x16
++#define DC_COMBOPHYPLLREGS8_CAL_CTRL__nctl_adj_dis__SHIFT 0x17
++#define DC_COMBOPHYPLLREGS8_CAL_CTRL__refclk_rate__SHIFT 0x18
++#define DC_COMBOPHYPLLREGS8_CAL_CTRL__bypass_freq_lock_MASK 0x00000001L
++#define DC_COMBOPHYPLLREGS8_CAL_CTRL__tdc_cal_en_MASK 0x00000002L
++#define DC_COMBOPHYPLLREGS8_CAL_CTRL__tdc_cal_ctrl_MASK 0x000001F8L
++#define DC_COMBOPHYPLLREGS8_CAL_CTRL__meas_win_sel_MASK 0x00000600L
++#define DC_COMBOPHYPLLREGS8_CAL_CTRL__kdco_cal_dis_MASK 0x00000800L
++#define DC_COMBOPHYPLLREGS8_CAL_CTRL__kdco_ratio_MASK 0x001FE000L
++#define DC_COMBOPHYPLLREGS8_CAL_CTRL__kdco_incr_cal_dis_MASK 0x00400000L
++#define DC_COMBOPHYPLLREGS8_CAL_CTRL__nctl_adj_dis_MASK 0x00800000L
++#define DC_COMBOPHYPLLREGS8_CAL_CTRL__refclk_rate_MASK 0xFF000000L
++//DC_COMBOPHYPLLREGS8_LOOP_CTRL
++#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__fbdiv_mask_en__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__fb_slip_dis__SHIFT 0x2
++#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__clk_tdc_sel__SHIFT 0x4
++#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__clk_nctl_sel__SHIFT 0x7
++#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__sig_del_patt_sel__SHIFT 0xa
++#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__nctl_sig_del_dis__SHIFT 0xc
++#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__fbclk_track_refclk__SHIFT 0xe
++#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__prbs_en__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__tdc_clk_gate_en__SHIFT 0x12
++#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__phase_offset__SHIFT 0x14
++#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__fbdiv_mask_en_MASK 0x00000001L
++#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__fb_slip_dis_MASK 0x00000004L
++#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__clk_tdc_sel_MASK 0x00000030L
++#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__clk_nctl_sel_MASK 0x00000180L
++#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__sig_del_patt_sel_MASK 0x00000400L
++#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__nctl_sig_del_dis_MASK 0x00001000L
++#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__fbclk_track_refclk_MASK 0x00004000L
++#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__prbs_en_MASK 0x00010000L
++#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__tdc_clk_gate_en_MASK 0x00040000L
++#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__phase_offset_MASK 0x07F00000L
++//DC_COMBOPHYPLLREGS8_VREG_CFG
++#define DC_COMBOPHYPLLREGS8_VREG_CFG__bleeder_ac__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS8_VREG_CFG__bleeder_en__SHIFT 0x1
++#define DC_COMBOPHYPLLREGS8_VREG_CFG__is_1p2__SHIFT 0x2
++#define DC_COMBOPHYPLLREGS8_VREG_CFG__reg_obs_sel__SHIFT 0x3
++#define DC_COMBOPHYPLLREGS8_VREG_CFG__reg_on_mode__SHIFT 0x5
++#define DC_COMBOPHYPLLREGS8_VREG_CFG__rlad_tap_sel__SHIFT 0x7
++#define DC_COMBOPHYPLLREGS8_VREG_CFG__reg_off_hi__SHIFT 0xb
++#define DC_COMBOPHYPLLREGS8_VREG_CFG__reg_off_lo__SHIFT 0xc
++#define DC_COMBOPHYPLLREGS8_VREG_CFG__scale_driver__SHIFT 0xd
++#define DC_COMBOPHYPLLREGS8_VREG_CFG__sel_bump__SHIFT 0xf
++#define DC_COMBOPHYPLLREGS8_VREG_CFG__sel_rladder_x__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS8_VREG_CFG__short_rc_filt_x__SHIFT 0x11
++#define DC_COMBOPHYPLLREGS8_VREG_CFG__vref_pwr_on__SHIFT 0x12
++#define DC_COMBOPHYPLLREGS8_VREG_CFG__dpll_cfg_2__SHIFT 0x14
++#define DC_COMBOPHYPLLREGS8_VREG_CFG__bleeder_ac_MASK 0x00000001L
++#define DC_COMBOPHYPLLREGS8_VREG_CFG__bleeder_en_MASK 0x00000002L
++#define DC_COMBOPHYPLLREGS8_VREG_CFG__is_1p2_MASK 0x00000004L
++#define DC_COMBOPHYPLLREGS8_VREG_CFG__reg_obs_sel_MASK 0x00000018L
++#define DC_COMBOPHYPLLREGS8_VREG_CFG__reg_on_mode_MASK 0x00000060L
++#define DC_COMBOPHYPLLREGS8_VREG_CFG__rlad_tap_sel_MASK 0x00000780L
++#define DC_COMBOPHYPLLREGS8_VREG_CFG__reg_off_hi_MASK 0x00000800L
++#define DC_COMBOPHYPLLREGS8_VREG_CFG__reg_off_lo_MASK 0x00001000L
++#define DC_COMBOPHYPLLREGS8_VREG_CFG__scale_driver_MASK 0x00006000L
++#define DC_COMBOPHYPLLREGS8_VREG_CFG__sel_bump_MASK 0x00008000L
++#define DC_COMBOPHYPLLREGS8_VREG_CFG__sel_rladder_x_MASK 0x00010000L
++#define DC_COMBOPHYPLLREGS8_VREG_CFG__short_rc_filt_x_MASK 0x00020000L
++#define DC_COMBOPHYPLLREGS8_VREG_CFG__vref_pwr_on_MASK 0x00040000L
++#define DC_COMBOPHYPLLREGS8_VREG_CFG__dpll_cfg_2_MASK 0x0FF00000L
++//DC_COMBOPHYPLLREGS8_OBSERVE0
++#define DC_COMBOPHYPLLREGS8_OBSERVE0__lock_det_tdc_steps__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS8_OBSERVE0__clear_sticky_lock__SHIFT 0x6
++#define DC_COMBOPHYPLLREGS8_OBSERVE0__lock_det_dis__SHIFT 0x8
++#define DC_COMBOPHYPLLREGS8_OBSERVE0__dco_cfg__SHIFT 0xa
++#define DC_COMBOPHYPLLREGS8_OBSERVE0__anaobs_sel__SHIFT 0x15
++#define DC_COMBOPHYPLLREGS8_OBSERVE0__lock_det_tdc_steps_MASK 0x0000001FL
++#define DC_COMBOPHYPLLREGS8_OBSERVE0__clear_sticky_lock_MASK 0x00000040L
++#define DC_COMBOPHYPLLREGS8_OBSERVE0__lock_det_dis_MASK 0x00000100L
++#define DC_COMBOPHYPLLREGS8_OBSERVE0__dco_cfg_MASK 0x0003FC00L
++#define DC_COMBOPHYPLLREGS8_OBSERVE0__anaobs_sel_MASK 0x00E00000L
++//DC_COMBOPHYPLLREGS8_OBSERVE1
++#define DC_COMBOPHYPLLREGS8_OBSERVE1__digobs_sel__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS8_OBSERVE1__digobs_trig_sel__SHIFT 0x5
++#define DC_COMBOPHYPLLREGS8_OBSERVE1__digobs_div__SHIFT 0xa
++#define DC_COMBOPHYPLLREGS8_OBSERVE1__digobs_trig_div__SHIFT 0xd
++#define DC_COMBOPHYPLLREGS8_OBSERVE1__lock_timer__SHIFT 0x10
++#define DC_COMBOPHYPLLREGS8_OBSERVE1__digobs_sel_MASK 0x0000000FL
++#define DC_COMBOPHYPLLREGS8_OBSERVE1__digobs_trig_sel_MASK 0x000001E0L
++#define DC_COMBOPHYPLLREGS8_OBSERVE1__digobs_div_MASK 0x00000C00L
++#define DC_COMBOPHYPLLREGS8_OBSERVE1__digobs_trig_div_MASK 0x00006000L
++#define DC_COMBOPHYPLLREGS8_OBSERVE1__lock_timer_MASK 0x3FFF0000L
++//DC_COMBOPHYPLLREGS8_DFT_OUT
++#define DC_COMBOPHYPLLREGS8_DFT_OUT__dft_data__SHIFT 0x0
++#define DC_COMBOPHYPLLREGS8_DFT_OUT__dft_data_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dsi0_dispdec
++//DSI0_DISP_DSI_CTRL
++#define DSI0_DISP_DSI_CTRL__DSI_EN__SHIFT 0x0
++#define DSI0_DISP_DSI_CTRL__VIDEO_MODE_EN__SHIFT 0x1
++#define DSI0_DISP_DSI_CTRL__CMD_MODE_EN__SHIFT 0x2
++#define DSI0_DISP_DSI_CTRL__DLN0_EN__SHIFT 0x4
++#define DSI0_DISP_DSI_CTRL__DLN1_EN__SHIFT 0x5
++#define DSI0_DISP_DSI_CTRL__DLN2_EN__SHIFT 0x6
++#define DSI0_DISP_DSI_CTRL__DLN3_EN__SHIFT 0x7
++#define DSI0_DISP_DSI_CTRL__CLKLN_EN__SHIFT 0x8
++#define DSI0_DISP_DSI_CTRL__DLN0_PHY_EN__SHIFT 0xc
++#define DSI0_DISP_DSI_CTRL__DLN1_PHY_EN__SHIFT 0xd
++#define DSI0_DISP_DSI_CTRL__DLN2_PHY_EN__SHIFT 0xe
++#define DSI0_DISP_DSI_CTRL__DLN3_PHY_EN__SHIFT 0xf
++#define DSI0_DISP_DSI_CTRL__RESET_DISPCLK__SHIFT 0x10
++#define DSI0_DISP_DSI_CTRL__RESET_DSICLK__SHIFT 0x11
++#define DSI0_DISP_DSI_CTRL__RESET_BYTECLK__SHIFT 0x12
++#define DSI0_DISP_DSI_CTRL__RESET_ESCCLK__SHIFT 0x13
++#define DSI0_DISP_DSI_CTRL__CRTC_SEL__SHIFT 0x14
++#define DSI0_DISP_DSI_CTRL__ECC_CHK_EN__SHIFT 0x18
++#define DSI0_DISP_DSI_CTRL__CRC_CHK_EN__SHIFT 0x19
++#define DSI0_DISP_DSI_CTRL__PACKET_BYTE_MSB_LSB_FLIP__SHIFT 0x1c
++#define DSI0_DISP_DSI_CTRL__PRE_TRIGGER_EN__SHIFT 0x1d
++#define DSI0_DISP_DSI_CTRL__NEW_INTERLEAVE_MODE_EN__SHIFT 0x1e
++#define DSI0_DISP_DSI_CTRL__DSI_EN_MASK 0x00000001L
++#define DSI0_DISP_DSI_CTRL__VIDEO_MODE_EN_MASK 0x00000002L
++#define DSI0_DISP_DSI_CTRL__CMD_MODE_EN_MASK 0x00000004L
++#define DSI0_DISP_DSI_CTRL__DLN0_EN_MASK 0x00000010L
++#define DSI0_DISP_DSI_CTRL__DLN1_EN_MASK 0x00000020L
++#define DSI0_DISP_DSI_CTRL__DLN2_EN_MASK 0x00000040L
++#define DSI0_DISP_DSI_CTRL__DLN3_EN_MASK 0x00000080L
++#define DSI0_DISP_DSI_CTRL__CLKLN_EN_MASK 0x00000100L
++#define DSI0_DISP_DSI_CTRL__DLN0_PHY_EN_MASK 0x00001000L
++#define DSI0_DISP_DSI_CTRL__DLN1_PHY_EN_MASK 0x00002000L
++#define DSI0_DISP_DSI_CTRL__DLN2_PHY_EN_MASK 0x00004000L
++#define DSI0_DISP_DSI_CTRL__DLN3_PHY_EN_MASK 0x00008000L
++#define DSI0_DISP_DSI_CTRL__RESET_DISPCLK_MASK 0x00010000L
++#define DSI0_DISP_DSI_CTRL__RESET_DSICLK_MASK 0x00020000L
++#define DSI0_DISP_DSI_CTRL__RESET_BYTECLK_MASK 0x00040000L
++#define DSI0_DISP_DSI_CTRL__RESET_ESCCLK_MASK 0x00080000L
++#define DSI0_DISP_DSI_CTRL__CRTC_SEL_MASK 0x00700000L
++#define DSI0_DISP_DSI_CTRL__ECC_CHK_EN_MASK 0x01000000L
++#define DSI0_DISP_DSI_CTRL__CRC_CHK_EN_MASK 0x02000000L
++#define DSI0_DISP_DSI_CTRL__PACKET_BYTE_MSB_LSB_FLIP_MASK 0x10000000L
++#define DSI0_DISP_DSI_CTRL__PRE_TRIGGER_EN_MASK 0x20000000L
++#define DSI0_DISP_DSI_CTRL__NEW_INTERLEAVE_MODE_EN_MASK 0x40000000L
++//DSI0_DISP_DSI_STATUS
++#define DSI0_DISP_DSI_STATUS__CMD_MODE_ENGINE_BUSY__SHIFT 0x0
++#define DSI0_DISP_DSI_STATUS__CMD_MODE_DMA_BUSY__SHIFT 0x1
++#define DSI0_DISP_DSI_STATUS__CMD_MODE_DENG_BUSY__SHIFT 0x2
++#define DSI0_DISP_DSI_STATUS__VIDEO_MODE_ENGINE_BUSY__SHIFT 0x3
++#define DSI0_DISP_DSI_STATUS__BTA_BUSY__SHIFT 0x4
++#define DSI0_DISP_DSI_STATUS__GENERIC_TRIGGER_BUSY__SHIFT 0x5
++#define DSI0_DISP_DSI_STATUS__PHY_RESET_BUSY__SHIFT 0x6
++#define DSI0_DISP_DSI_STATUS__DLN0_HS_FIFO_EMPTY__SHIFT 0x8
++#define DSI0_DISP_DSI_STATUS__DLN0_HS_FIFO_FULL__SHIFT 0x9
++#define DSI0_DISP_DSI_STATUS__DLN1_HS_FIFO_EMPTY__SHIFT 0xa
++#define DSI0_DISP_DSI_STATUS__DLN1_HS_FIFO_FULL__SHIFT 0xb
++#define DSI0_DISP_DSI_STATUS__DLN2_HS_FIFO_EMPTY__SHIFT 0xc
++#define DSI0_DISP_DSI_STATUS__DLN2_HS_FIFO_FULL__SHIFT 0xd
++#define DSI0_DISP_DSI_STATUS__DLN3_HS_FIFO_EMPTY__SHIFT 0xe
++#define DSI0_DISP_DSI_STATUS__DLN3_HS_FIFO_FULL__SHIFT 0xf
++#define DSI0_DISP_DSI_STATUS__DLN0_HS_FIFO_OVERFLOW__SHIFT 0x10
++#define DSI0_DISP_DSI_STATUS__DLN0_HS_FIFO_OVERFLOW_CLR__SHIFT 0x10
++#define DSI0_DISP_DSI_STATUS__DLN1_HS_FIFO_OVERFLOW__SHIFT 0x11
++#define DSI0_DISP_DSI_STATUS__DLN1_HS_FIFO_OVERFLOW_CLR__SHIFT 0x11
++#define DSI0_DISP_DSI_STATUS__DLN2_HS_FIFO_OVERFLOW__SHIFT 0x12
++#define DSI0_DISP_DSI_STATUS__DLN2_HS_FIFO_OVERFLOW_CLR__SHIFT 0x12
++#define DSI0_DISP_DSI_STATUS__DLN3_HS_FIFO_OVERFLOW__SHIFT 0x13
++#define DSI0_DISP_DSI_STATUS__DLN3_HS_FIFO_OVERFLOW_CLR__SHIFT 0x13
++#define DSI0_DISP_DSI_STATUS__DLN0_LP_FIFO_EMPTY__SHIFT 0x14
++#define DSI0_DISP_DSI_STATUS__DLN0_LP_FIFO_FULL__SHIFT 0x15
++#define DSI0_DISP_DSI_STATUS__DLN0_LP_FIFO_OVERFLOW__SHIFT 0x16
++#define DSI0_DISP_DSI_STATUS__DLN0_LP_FIFO_OVERFLOW_CLR__SHIFT 0x16
++#define DSI0_DISP_DSI_STATUS__CMDFIFO_UNDERFLOW__SHIFT 0x17
++#define DSI0_DISP_DSI_STATUS__CMDFIFO_UNDERFLOW_CLR__SHIFT 0x17
++#define DSI0_DISP_DSI_STATUS__INTERLEAVE_PACKET_BLOCK__SHIFT 0x18
++#define DSI0_DISP_DSI_STATUS__INTERLEAVE_PACKET_BLOCK_CLR__SHIFT 0x18
++#define DSI0_DISP_DSI_STATUS__TE_ABORT__SHIFT 0x19
++#define DSI0_DISP_DSI_STATUS__TE_ABORT_CLR__SHIFT 0x19
++#define DSI0_DISP_DSI_STATUS__DMAFIFO_RD_WATERMARK_REACH__SHIFT 0x1c
++#define DSI0_DISP_DSI_STATUS__DMAFIFO_RD_WATERMARK_REACH_CLR__SHIFT 0x1c
++#define DSI0_DISP_DSI_STATUS__DMAFIFO_WR_WATERMARK_REACH__SHIFT 0x1d
++#define DSI0_DISP_DSI_STATUS__DMAFIFO_WR_WATERMARK_REACH_CLR__SHIFT 0x1d
++#define DSI0_DISP_DSI_STATUS__DMAFIFO_UNDERFLOW__SHIFT 0x1e
++#define DSI0_DISP_DSI_STATUS__DMAFIFO_UNDERFLOW_CLR__SHIFT 0x1e
++#define DSI0_DISP_DSI_STATUS__INTERLEAVE_OP_CONTENTION__SHIFT 0x1f
++#define DSI0_DISP_DSI_STATUS__INTERLEAVE_OP_CONTENTION_CLR__SHIFT 0x1f
++#define DSI0_DISP_DSI_STATUS__CMD_MODE_ENGINE_BUSY_MASK 0x00000001L
++#define DSI0_DISP_DSI_STATUS__CMD_MODE_DMA_BUSY_MASK 0x00000002L
++#define DSI0_DISP_DSI_STATUS__CMD_MODE_DENG_BUSY_MASK 0x00000004L
++#define DSI0_DISP_DSI_STATUS__VIDEO_MODE_ENGINE_BUSY_MASK 0x00000008L
++#define DSI0_DISP_DSI_STATUS__BTA_BUSY_MASK 0x00000010L
++#define DSI0_DISP_DSI_STATUS__GENERIC_TRIGGER_BUSY_MASK 0x00000020L
++#define DSI0_DISP_DSI_STATUS__PHY_RESET_BUSY_MASK 0x00000040L
++#define DSI0_DISP_DSI_STATUS__DLN0_HS_FIFO_EMPTY_MASK 0x00000100L
++#define DSI0_DISP_DSI_STATUS__DLN0_HS_FIFO_FULL_MASK 0x00000200L
++#define DSI0_DISP_DSI_STATUS__DLN1_HS_FIFO_EMPTY_MASK 0x00000400L
++#define DSI0_DISP_DSI_STATUS__DLN1_HS_FIFO_FULL_MASK 0x00000800L
++#define DSI0_DISP_DSI_STATUS__DLN2_HS_FIFO_EMPTY_MASK 0x00001000L
++#define DSI0_DISP_DSI_STATUS__DLN2_HS_FIFO_FULL_MASK 0x00002000L
++#define DSI0_DISP_DSI_STATUS__DLN3_HS_FIFO_EMPTY_MASK 0x00004000L
++#define DSI0_DISP_DSI_STATUS__DLN3_HS_FIFO_FULL_MASK 0x00008000L
++#define DSI0_DISP_DSI_STATUS__DLN0_HS_FIFO_OVERFLOW_MASK 0x00010000L
++#define DSI0_DISP_DSI_STATUS__DLN0_HS_FIFO_OVERFLOW_CLR_MASK 0x00010000L
++#define DSI0_DISP_DSI_STATUS__DLN1_HS_FIFO_OVERFLOW_MASK 0x00020000L
++#define DSI0_DISP_DSI_STATUS__DLN1_HS_FIFO_OVERFLOW_CLR_MASK 0x00020000L
++#define DSI0_DISP_DSI_STATUS__DLN2_HS_FIFO_OVERFLOW_MASK 0x00040000L
++#define DSI0_DISP_DSI_STATUS__DLN2_HS_FIFO_OVERFLOW_CLR_MASK 0x00040000L
++#define DSI0_DISP_DSI_STATUS__DLN3_HS_FIFO_OVERFLOW_MASK 0x00080000L
++#define DSI0_DISP_DSI_STATUS__DLN3_HS_FIFO_OVERFLOW_CLR_MASK 0x00080000L
++#define DSI0_DISP_DSI_STATUS__DLN0_LP_FIFO_EMPTY_MASK 0x00100000L
++#define DSI0_DISP_DSI_STATUS__DLN0_LP_FIFO_FULL_MASK 0x00200000L
++#define DSI0_DISP_DSI_STATUS__DLN0_LP_FIFO_OVERFLOW_MASK 0x00400000L
++#define DSI0_DISP_DSI_STATUS__DLN0_LP_FIFO_OVERFLOW_CLR_MASK 0x00400000L
++#define DSI0_DISP_DSI_STATUS__CMDFIFO_UNDERFLOW_MASK 0x00800000L
++#define DSI0_DISP_DSI_STATUS__CMDFIFO_UNDERFLOW_CLR_MASK 0x00800000L
++#define DSI0_DISP_DSI_STATUS__INTERLEAVE_PACKET_BLOCK_MASK 0x01000000L
++#define DSI0_DISP_DSI_STATUS__INTERLEAVE_PACKET_BLOCK_CLR_MASK 0x01000000L
++#define DSI0_DISP_DSI_STATUS__TE_ABORT_MASK 0x02000000L
++#define DSI0_DISP_DSI_STATUS__TE_ABORT_CLR_MASK 0x02000000L
++#define DSI0_DISP_DSI_STATUS__DMAFIFO_RD_WATERMARK_REACH_MASK 0x10000000L
++#define DSI0_DISP_DSI_STATUS__DMAFIFO_RD_WATERMARK_REACH_CLR_MASK 0x10000000L
++#define DSI0_DISP_DSI_STATUS__DMAFIFO_WR_WATERMARK_REACH_MASK 0x20000000L
++#define DSI0_DISP_DSI_STATUS__DMAFIFO_WR_WATERMARK_REACH_CLR_MASK 0x20000000L
++#define DSI0_DISP_DSI_STATUS__DMAFIFO_UNDERFLOW_MASK 0x40000000L
++#define DSI0_DISP_DSI_STATUS__DMAFIFO_UNDERFLOW_CLR_MASK 0x40000000L
++#define DSI0_DISP_DSI_STATUS__INTERLEAVE_OP_CONTENTION_MASK 0x80000000L
++#define DSI0_DISP_DSI_STATUS__INTERLEAVE_OP_CONTENTION_CLR_MASK 0x80000000L
++//DSI0_DISP_DSI_VIDEO_MODE_CTRL
++#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__VC__SHIFT 0x0
++#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__DST_FORMAT__SHIFT 0x4
++#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__TRAFFIC_MODE__SHIFT 0x8
++#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__BLLP_PWR_MODE__SHIFT 0xc
++#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__EOF_BLLP_PWR_MODE__SHIFT 0xf
++#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__HSA_PWR_MODE__SHIFT 0x10
++#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__HBP_PWR_MODE__SHIFT 0x14
++#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__HFP_PWR_MODE__SHIFT 0x18
++#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__PULSE_MODE_OPT__SHIFT 0x1c
++#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__VC_MASK 0x00000003L
++#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__DST_FORMAT_MASK 0x00000030L
++#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__TRAFFIC_MODE_MASK 0x00000300L
++#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__BLLP_PWR_MODE_MASK 0x00001000L
++#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__EOF_BLLP_PWR_MODE_MASK 0x00008000L
++#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__HSA_PWR_MODE_MASK 0x00010000L
++#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__HBP_PWR_MODE_MASK 0x00100000L
++#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__HFP_PWR_MODE_MASK 0x01000000L
++#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__PULSE_MODE_OPT_MASK 0x10000000L
++//DSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE
++#define DSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__VS__SHIFT 0x0
++#define DSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__VE__SHIFT 0x8
++#define DSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__HS__SHIFT 0x10
++#define DSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__HE__SHIFT 0x18
++#define DSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__VS_MASK 0x0000003FL
++#define DSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__VE_MASK 0x00003F00L
++#define DSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__HS_MASK 0x003F0000L
++#define DSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__HE_MASK 0x3F000000L
++//DSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD
++#define DSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD__VS_PAYLOAD__SHIFT 0x0
++#define DSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD__VE_PAYLOAD__SHIFT 0x10
++#define DSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD__VS_PAYLOAD_MASK 0x0000FFFFL
++#define DSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD__VE_PAYLOAD_MASK 0xFFFF0000L
++//DSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD
++#define DSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD__HS_PAYLOAD__SHIFT 0x0
++#define DSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD__HE_PAYLOAD__SHIFT 0x10
++#define DSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD__HS_PAYLOAD_MASK 0x0000FFFFL
++#define DSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD__HE_PAYLOAD_MASK 0xFFFF0000L
++//DSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE
++#define DSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB565__SHIFT 0x0
++#define DSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB666_PACKED__SHIFT 0x8
++#define DSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB666__SHIFT 0x10
++#define DSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB888__SHIFT 0x18
++#define DSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB565_MASK 0x0000003FL
++#define DSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB666_PACKED_MASK 0x00003F00L
++#define DSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB666_MASK 0x003F0000L
++#define DSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB888_MASK 0x3F000000L
++//DSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE
++#define DSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE__BLANK_PKT_DATA__SHIFT 0x0
++#define DSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE__BLANK_PKT_DATATYPE__SHIFT 0x8
++#define DSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE__BLANK_PKT_DATA_MASK 0x000000FFL
++#define DSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE__BLANK_PKT_DATATYPE_MASK 0x00003F00L
++//DSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL
++#define DSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL__R_SEL__SHIFT 0x0
++#define DSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL__G_SEL__SHIFT 0x4
++#define DSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL__B_SEL__SHIFT 0x8
++#define DSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL__RGB_SWAP__SHIFT 0xc
++#define DSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL__R_SEL_MASK 0x00000001L
++#define DSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL__G_SEL_MASK 0x00000010L
++#define DSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL__B_SEL_MASK 0x00000100L
++#define DSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL__RGB_SWAP_MASK 0x00007000L
++//DSI0_DISP_DSI_COMMAND_MODE_CTRL
++#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__WC__SHIFT 0x0
++#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__DT__SHIFT 0x10
++#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__VC__SHIFT 0x16
++#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__PACKET_TYPE__SHIFT 0x18
++#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__POWER_MODE__SHIFT 0x1a
++#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__EMBEDDED_MODE__SHIFT 0x1c
++#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__CMD_DATA_ORDER__SHIFT 0x1f
++#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__WC_MASK 0x0000FFFFL
++#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__DT_MASK 0x003F0000L
++#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__VC_MASK 0x00C00000L
++#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__PACKET_TYPE_MASK 0x01000000L
++#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__POWER_MODE_MASK 0x04000000L
++#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__EMBEDDED_MODE_MASK 0x10000000L
++#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__CMD_DATA_ORDER_MASK 0x80000000L
++//DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL
++#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__SRC_FORMAT__SHIFT 0x0
++#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__DST_FORMAT__SHIFT 0x4
++#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__DATA_BUFFER_ID__SHIFT 0x8
++#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__SHADOW_DATA_BUFFER_ID__SHIFT 0xc
++#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__R_SEL__SHIFT 0x10
++#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__G_SEL__SHIFT 0x11
++#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__B_SEL__SHIFT 0x12
++#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__RGB_SWAP__SHIFT 0x14
++#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__DWORD_BYTE_SWAP__SHIFT 0x18
++#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__SRC_FORMAT_MASK 0x0000000FL
++#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__DST_FORMAT_MASK 0x000000F0L
++#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__DATA_BUFFER_ID_MASK 0x00000100L
++#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__SHADOW_DATA_BUFFER_ID_MASK 0x00001000L
++#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__R_SEL_MASK 0x00010000L
++#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__G_SEL_MASK 0x00020000L
++#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__B_SEL_MASK 0x00040000L
++#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__RGB_SWAP_MASK 0x00700000L
++#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__DWORD_BYTE_SWAP_MASK 0x03000000L
++//DSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL
++#define DSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__WR_MEM_START__SHIFT 0x0
++#define DSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__WR_MEM_CONTINUE__SHIFT 0x8
++#define DSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__INSERT_DCS_COMMAND__SHIFT 0x10
++#define DSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__WR_MEM_START_MASK 0x000000FFL
++#define DSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__WR_MEM_CONTINUE_MASK 0x0000FF00L
++#define DSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__INSERT_DCS_COMMAND_MASK 0x00010000L
++//DSI0_DISP_DSI_DMA_CMD_OFFSET
++#define DSI0_DISP_DSI_DMA_CMD_OFFSET__CMD_OFFSET__SHIFT 0x0
++#define DSI0_DISP_DSI_DMA_CMD_OFFSET__CMD_OFFSET_MASK 0xFFFFFFFFL
++//DSI0_DISP_DSI_DMA_CMD_LENGTH
++#define DSI0_DISP_DSI_DMA_CMD_LENGTH__CMD_LENGTH__SHIFT 0x0
++#define DSI0_DISP_DSI_DMA_CMD_LENGTH__CMD_LENGTH_MASK 0x00FFFFFFL
++//DSI0_DISP_DSI_DMA_DATA_OFFSET_0
++#define DSI0_DISP_DSI_DMA_DATA_OFFSET_0__DATA_SRC_OFFSET0__SHIFT 0x0
++#define DSI0_DISP_DSI_DMA_DATA_OFFSET_0__DATA_SRC_OFFSET0_MASK 0xFFFFFFFFL
++//DSI0_DISP_DSI_DMA_DATA_OFFSET_1
++#define DSI0_DISP_DSI_DMA_DATA_OFFSET_1__DATA_SRC_OFFSET1__SHIFT 0x0
++#define DSI0_DISP_DSI_DMA_DATA_OFFSET_1__DATA_SRC_OFFSET1_MASK 0xFFFFFFFFL
++//DSI0_DISP_DSI_DMA_DATA_PITCH
++#define DSI0_DISP_DSI_DMA_DATA_PITCH__DATA_SRC_PITCH__SHIFT 0x0
++#define DSI0_DISP_DSI_DMA_DATA_PITCH__DATA_SRC_PITCH_MASK 0x00007FFFL
++//DSI0_DISP_DSI_DMA_DATA_WIDTH
++#define DSI0_DISP_DSI_DMA_DATA_WIDTH__DATA_SRC_WIDTH__SHIFT 0x0
++#define DSI0_DISP_DSI_DMA_DATA_WIDTH__DATA_SRC_WIDTH_ALIGN__SHIFT 0x18
++#define DSI0_DISP_DSI_DMA_DATA_WIDTH__DATA_SRC_WIDTH_MASK 0x000FFFFFL
++#define DSI0_DISP_DSI_DMA_DATA_WIDTH__DATA_SRC_WIDTH_ALIGN_MASK 0x07000000L
++//DSI0_DISP_DSI_DMA_DATA_HEIGHT
++#define DSI0_DISP_DSI_DMA_DATA_HEIGHT__DATA_SRC_HEIGHT__SHIFT 0x0
++#define DSI0_DISP_DSI_DMA_DATA_HEIGHT__DATA_SRC_HEIGHT_MASK 0x00000FFFL
++//DSI0_DISP_DSI_DMA_FIFO_CTRL
++#define DSI0_DISP_DSI_DMA_FIFO_CTRL__WRITE_WATERMARK__SHIFT 0x0
++#define DSI0_DISP_DSI_DMA_FIFO_CTRL__READ_WATERMARK__SHIFT 0x4
++#define DSI0_DISP_DSI_DMA_FIFO_CTRL__WRITE_WATERMARK_MASK 0x00000003L
++#define DSI0_DISP_DSI_DMA_FIFO_CTRL__READ_WATERMARK_MASK 0x00000030L
++//DSI0_DISP_DSI_DMA_NULL_PACKET_DATA
++#define DSI0_DISP_DSI_DMA_NULL_PACKET_DATA__NULL_DATA__SHIFT 0x0
++#define DSI0_DISP_DSI_DMA_NULL_PACKET_DATA__NULL_DATATYPE__SHIFT 0x8
++#define DSI0_DISP_DSI_DMA_NULL_PACKET_DATA__NULL_DATA_MASK 0x000000FFL
++#define DSI0_DISP_DSI_DMA_NULL_PACKET_DATA__NULL_DATATYPE_MASK 0x00003F00L
++//DSI0_DISP_DSI_DENG_DATA_LENGTH
++#define DSI0_DISP_DSI_DENG_DATA_LENGTH__DENG_LENGTH__SHIFT 0x0
++#define DSI0_DISP_DSI_DENG_DATA_LENGTH__USE_DENG_LENGTH__SHIFT 0x1f
++#define DSI0_DISP_DSI_DENG_DATA_LENGTH__DENG_LENGTH_MASK 0x00FFFFFFL
++#define DSI0_DISP_DSI_DENG_DATA_LENGTH__USE_DENG_LENGTH_MASK 0x80000000L
++//DSI0_DISP_DSI_ACK_ERROR_REPORT
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__SOT_ERR__SHIFT 0x0
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__SOT_ERR_CLR__SHIFT 0x0
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__SOT_SYNC_ERR__SHIFT 0x1
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__SOT_SYNC_ERR_CLR__SHIFT 0x1
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__EOT_ERR__SHIFT 0x2
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__EOT_ERR_CLR__SHIFT 0x2
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ESC_ERR__SHIFT 0x3
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ESC_ERR_CLR__SHIFT 0x3
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__LP_ERR__SHIFT 0x4
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__LP_ERR_CLR__SHIFT 0x4
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__HRX_TO__SHIFT 0x5
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__HRX_TO_CLR__SHIFT 0x5
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__FALSE_CTRL_ERR__SHIFT 0x6
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__FALSE_CTRL_ERR_CLR__SHIFT 0x6
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__CONTENTION_ERR__SHIFT 0x7
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__CONTENTION_ERR_CLR__SHIFT 0x7
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ECC_ERR__SHIFT 0x8
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ECC_ERR_CLR__SHIFT 0x8
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__MULTI_ECC_ERR__SHIFT 0x9
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__MULTI_ECC_ERR_CLR__SHIFT 0x9
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__CRC_ERR__SHIFT 0xa
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__CRC_ERR_CLR__SHIFT 0xa
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__DT_ERR__SHIFT 0xb
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__DT_ERR_CLR__SHIFT 0xb
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__VC_ERR__SHIFT 0xc
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__VC_ERR_CLR__SHIFT 0xc
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__PROTOCOL_VIOLATION__SHIFT 0xd
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__PROTOCOL_VIOLATION_CLR__SHIFT 0xd
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__PANEL_SPECIFIC_ERR__SHIFT 0xf
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__PANEL_SPECIFIC_ERR_CLR__SHIFT 0xf
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_ECC_ERR__SHIFT 0x10
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_ECC_ERR_CLR__SHIFT 0x10
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_MULTI_ECC_ERR__SHIFT 0x11
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_MULTI_ECC_ERR_CLR__SHIFT 0x11
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_CRC_ERR__SHIFT 0x14
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_CRC_ERR_CLR__SHIFT 0x14
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_INCOMPLETE_PACKET_ERR__SHIFT 0x17
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_INCOMPLETE_PACKET_ERR_CLR__SHIFT 0x17
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ERROR__SHIFT 0x18
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ERROR_CLR__SHIFT 0x18
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ACK__SHIFT 0x1c
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ACK_CLR__SHIFT 0x1c
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__SOT_ERR_MASK 0x00000001L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__SOT_ERR_CLR_MASK 0x00000001L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__SOT_SYNC_ERR_MASK 0x00000002L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__SOT_SYNC_ERR_CLR_MASK 0x00000002L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__EOT_ERR_MASK 0x00000004L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__EOT_ERR_CLR_MASK 0x00000004L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ESC_ERR_MASK 0x00000008L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ESC_ERR_CLR_MASK 0x00000008L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__LP_ERR_MASK 0x00000010L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__LP_ERR_CLR_MASK 0x00000010L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__HRX_TO_MASK 0x00000020L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__HRX_TO_CLR_MASK 0x00000020L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__FALSE_CTRL_ERR_MASK 0x00000040L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__FALSE_CTRL_ERR_CLR_MASK 0x00000040L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__CONTENTION_ERR_MASK 0x00000080L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__CONTENTION_ERR_CLR_MASK 0x00000080L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ECC_ERR_MASK 0x00000100L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ECC_ERR_CLR_MASK 0x00000100L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__MULTI_ECC_ERR_MASK 0x00000200L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__MULTI_ECC_ERR_CLR_MASK 0x00000200L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__CRC_ERR_MASK 0x00000400L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__CRC_ERR_CLR_MASK 0x00000400L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__DT_ERR_MASK 0x00000800L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__DT_ERR_CLR_MASK 0x00000800L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__VC_ERR_MASK 0x00001000L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__VC_ERR_CLR_MASK 0x00001000L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__PROTOCOL_VIOLATION_MASK 0x00002000L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__PROTOCOL_VIOLATION_CLR_MASK 0x00002000L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__PANEL_SPECIFIC_ERR_MASK 0x00008000L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__PANEL_SPECIFIC_ERR_CLR_MASK 0x00008000L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_ECC_ERR_MASK 0x00010000L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_ECC_ERR_CLR_MASK 0x00010000L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_MULTI_ECC_ERR_MASK 0x00020000L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_MULTI_ECC_ERR_CLR_MASK 0x00020000L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_CRC_ERR_MASK 0x00100000L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_CRC_ERR_CLR_MASK 0x00100000L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_INCOMPLETE_PACKET_ERR_MASK 0x00800000L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_INCOMPLETE_PACKET_ERR_CLR_MASK 0x00800000L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ERROR_MASK 0x01000000L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ERROR_CLR_MASK 0x01000000L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ACK_MASK 0x10000000L
++#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ACK_CLR_MASK 0x10000000L
++//DSI0_DISP_DSI_RDBK_DATA0
++#define DSI0_DISP_DSI_RDBK_DATA0__RD_DATA0__SHIFT 0x0
++#define DSI0_DISP_DSI_RDBK_DATA0__RD_DATA0_MASK 0xFFFFFFFFL
++//DSI0_DISP_DSI_RDBK_DATA1
++#define DSI0_DISP_DSI_RDBK_DATA1__RD_DATA1__SHIFT 0x0
++#define DSI0_DISP_DSI_RDBK_DATA1__RD_DATA1_MASK 0xFFFFFFFFL
++//DSI0_DISP_DSI_RDBK_DATA2
++#define DSI0_DISP_DSI_RDBK_DATA2__RD_DATA2__SHIFT 0x0
++#define DSI0_DISP_DSI_RDBK_DATA2__RD_DATA2_MASK 0xFFFFFFFFL
++//DSI0_DISP_DSI_RDBK_DATA3
++#define DSI0_DISP_DSI_RDBK_DATA3__RD_DATA3__SHIFT 0x0
++#define DSI0_DISP_DSI_RDBK_DATA3__RD_DATA3_MASK 0xFFFFFFFFL
++//DSI0_DISP_DSI_RDBK_DATATYPE0
++#define DSI0_DISP_DSI_RDBK_DATATYPE0__GENERIC_SHORT_RD_1_BYTE__SHIFT 0x0
++#define DSI0_DISP_DSI_RDBK_DATATYPE0__GENERIC_SHORT_RD_2_BYTE__SHIFT 0x8
++#define DSI0_DISP_DSI_RDBK_DATATYPE0__DCS_SHORT_RD_1_BYTE__SHIFT 0x10
++#define DSI0_DISP_DSI_RDBK_DATATYPE0__DCS_SHORT_RD_2_BYTE__SHIFT 0x18
++#define DSI0_DISP_DSI_RDBK_DATATYPE0__GENERIC_SHORT_RD_1_BYTE_MASK 0x0000003FL
++#define DSI0_DISP_DSI_RDBK_DATATYPE0__GENERIC_SHORT_RD_2_BYTE_MASK 0x00003F00L
++#define DSI0_DISP_DSI_RDBK_DATATYPE0__DCS_SHORT_RD_1_BYTE_MASK 0x003F0000L
++#define DSI0_DISP_DSI_RDBK_DATATYPE0__DCS_SHORT_RD_2_BYTE_MASK 0x3F000000L
++//DSI0_DISP_DSI_RDBK_DATATYPE1
++#define DSI0_DISP_DSI_RDBK_DATATYPE1__ERROR_REPORT__SHIFT 0x0
++#define DSI0_DISP_DSI_RDBK_DATATYPE1__GENERIC_LONG_RD__SHIFT 0x8
++#define DSI0_DISP_DSI_RDBK_DATATYPE1__DCS_LONG_RD__SHIFT 0x10
++#define DSI0_DISP_DSI_RDBK_DATATYPE1__ERROR_REPORT_MASK 0x0000003FL
++#define DSI0_DISP_DSI_RDBK_DATATYPE1__GENERIC_LONG_RD_MASK 0x00003F00L
++#define DSI0_DISP_DSI_RDBK_DATATYPE1__DCS_LONG_RD_MASK 0x003F0000L
++//DSI0_DISP_DSI_TRIG_CTRL
++#define DSI0_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_TRIGGER_MODE__SHIFT 0x0
++#define DSI0_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_TRIGGER_SEL__SHIFT 0x4
++#define DSI0_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DENG_TRIGGER_MODE__SHIFT 0x10
++#define DSI0_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DENG_TRIGGER_SEL__SHIFT 0x14
++#define DSI0_DISP_DSI_TRIG_CTRL__HW_SOURCE_SEL__SHIFT 0x18
++#define DSI0_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_DENG_ORDER__SHIFT 0x1c
++#define DSI0_DISP_DSI_TRIG_CTRL__TE_SEL__SHIFT 0x1f
++#define DSI0_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_TRIGGER_MODE_MASK 0x00000001L
++#define DSI0_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_TRIGGER_SEL_MASK 0x00000030L
++#define DSI0_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DENG_TRIGGER_MODE_MASK 0x00010000L
++#define DSI0_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DENG_TRIGGER_SEL_MASK 0x00300000L
++#define DSI0_DISP_DSI_TRIG_CTRL__HW_SOURCE_SEL_MASK 0x0F000000L
++#define DSI0_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_DENG_ORDER_MASK 0x10000000L
++#define DSI0_DISP_DSI_TRIG_CTRL__TE_SEL_MASK 0x80000000L
++//DSI0_DISP_DSI_EXT_MUX
++#define DSI0_DISP_DSI_EXT_MUX__EXT_TE_MUX__SHIFT 0x0
++#define DSI0_DISP_DSI_EXT_MUX__EXT_TE_MODE__SHIFT 0x4
++#define DSI0_DISP_DSI_EXT_MUX__EXT_RESET_POL__SHIFT 0x6
++#define DSI0_DISP_DSI_EXT_MUX__EXT_TE_POL__SHIFT 0x7
++#define DSI0_DISP_DSI_EXT_MUX__EXT_TE_HSYNC_TRIG_CNT__SHIFT 0x8
++#define DSI0_DISP_DSI_EXT_MUX__EXT_TE_HSYNC_TOTAL__SHIFT 0x14
++#define DSI0_DISP_DSI_EXT_MUX__EXT_TE_MUX_MASK 0x0000000FL
++#define DSI0_DISP_DSI_EXT_MUX__EXT_TE_MODE_MASK 0x00000030L
++#define DSI0_DISP_DSI_EXT_MUX__EXT_RESET_POL_MASK 0x00000040L
++#define DSI0_DISP_DSI_EXT_MUX__EXT_TE_POL_MASK 0x00000080L
++#define DSI0_DISP_DSI_EXT_MUX__EXT_TE_HSYNC_TRIG_CNT_MASK 0x000FFF00L
++#define DSI0_DISP_DSI_EXT_MUX__EXT_TE_HSYNC_TOTAL_MASK 0xFFF00000L
++//DSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL
++#define DSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL__TE_HSYNC_MAX_WIDTH__SHIFT 0x0
++#define DSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL__TE_VSYNC_MIN_WIDTH__SHIFT 0x10
++#define DSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL__TE_HSYNC_MAX_WIDTH_MASK 0x0000FFFFL
++#define DSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL__TE_VSYNC_MIN_WIDTH_MASK 0xFFFF0000L
++//DSI0_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER
++#define DSI0_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER__SW_TRIGGER__SHIFT 0x0
++#define DSI0_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER__SW_TRIGGER_MASK 0x00000001L
++//DSI0_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER
++#define DSI0_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER__SW_TRIGGER__SHIFT 0x0
++#define DSI0_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER__SW_TRIGGER_MASK 0x00000001L
++//DSI0_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER
++#define DSI0_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER__SW_TRIGGER__SHIFT 0x0
++#define DSI0_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER__SW_TRIGGER_MASK 0x00000001L
++//DSI0_DISP_DSI_RESET_SW_TRIGGER
++#define DSI0_DISP_DSI_RESET_SW_TRIGGER__SW_TRIGGER__SHIFT 0x0
++#define DSI0_DISP_DSI_RESET_SW_TRIGGER__SW_TRIGGER_MASK 0x00000001L
++//DSI0_DISP_DSI_EXT_RESET
++#define DSI0_DISP_DSI_EXT_RESET__RESET_PANEL__SHIFT 0x0
++#define DSI0_DISP_DSI_EXT_RESET__RESET_PANEL_MASK 0x00000001L
++//DSI0_DISP_DSI_LANE_CRC_HS_MODE
++#define DSI0_DISP_DSI_LANE_CRC_HS_MODE__DLN0_HS_CRC__SHIFT 0x0
++#define DSI0_DISP_DSI_LANE_CRC_HS_MODE__DLN1_HS_CRC__SHIFT 0x8
++#define DSI0_DISP_DSI_LANE_CRC_HS_MODE__DLN2_HS_CRC__SHIFT 0x10
++#define DSI0_DISP_DSI_LANE_CRC_HS_MODE__DLN3_HS_CRC__SHIFT 0x18
++#define DSI0_DISP_DSI_LANE_CRC_HS_MODE__DLN0_HS_CRC_MASK 0x000000FFL
++#define DSI0_DISP_DSI_LANE_CRC_HS_MODE__DLN1_HS_CRC_MASK 0x0000FF00L
++#define DSI0_DISP_DSI_LANE_CRC_HS_MODE__DLN2_HS_CRC_MASK 0x00FF0000L
++#define DSI0_DISP_DSI_LANE_CRC_HS_MODE__DLN3_HS_CRC_MASK 0xFF000000L
++//DSI0_DISP_DSI_LANE_CRC_LP_MODE
++#define DSI0_DISP_DSI_LANE_CRC_LP_MODE__DLN0_LP_CRC__SHIFT 0x0
++#define DSI0_DISP_DSI_LANE_CRC_LP_MODE__DLN0_LP_CRC_MASK 0x000000FFL
++//DSI0_DISP_DSI_LANE_CRC_CTRL
++#define DSI0_DISP_DSI_LANE_CRC_CTRL__CRC_MAX_HS_DONE_COUNT__SHIFT 0x0
++#define DSI0_DISP_DSI_LANE_CRC_CTRL__CRC_MAX_LP_DONE_COUNT__SHIFT 0x8
++#define DSI0_DISP_DSI_LANE_CRC_CTRL__CRC_ENABLE__SHIFT 0x10
++#define DSI0_DISP_DSI_LANE_CRC_CTRL__CRC_DONE_HS__SHIFT 0x14
++#define DSI0_DISP_DSI_LANE_CRC_CTRL__CRC_DONE_LP__SHIFT 0x18
++#define DSI0_DISP_DSI_LANE_CRC_CTRL__CRC_MAX_HS_DONE_COUNT_MASK 0x000000FFL
++#define DSI0_DISP_DSI_LANE_CRC_CTRL__CRC_MAX_LP_DONE_COUNT_MASK 0x0000FF00L
++#define DSI0_DISP_DSI_LANE_CRC_CTRL__CRC_ENABLE_MASK 0x00010000L
++#define DSI0_DISP_DSI_LANE_CRC_CTRL__CRC_DONE_HS_MASK 0x00100000L
++#define DSI0_DISP_DSI_LANE_CRC_CTRL__CRC_DONE_LP_MASK 0x01000000L
++//DSI0_DISP_DSI_PIXEL_CRC_CTRL
++#define DSI0_DISP_DSI_PIXEL_CRC_CTRL__CRC_MAX_PIXEL_COUNT__SHIFT 0x0
++#define DSI0_DISP_DSI_PIXEL_CRC_CTRL__PIXEL_CRC__SHIFT 0x8
++#define DSI0_DISP_DSI_PIXEL_CRC_CTRL__CRC_DONE_PIXEL__SHIFT 0x10
++#define DSI0_DISP_DSI_PIXEL_CRC_CTRL__CRC_MAX_PIXEL_COUNT_MASK 0x000000FFL
++#define DSI0_DISP_DSI_PIXEL_CRC_CTRL__PIXEL_CRC_MASK 0x0000FF00L
++#define DSI0_DISP_DSI_PIXEL_CRC_CTRL__CRC_DONE_PIXEL_MASK 0x00010000L
++//DSI0_DISP_DSI_LANE_CTRL
++#define DSI0_DISP_DSI_LANE_CTRL__DLN0_ULPS_REQUEST__SHIFT 0x0
++#define DSI0_DISP_DSI_LANE_CTRL__DLN1_ULPS_REQUEST__SHIFT 0x1
++#define DSI0_DISP_DSI_LANE_CTRL__DLN2_ULPS_REQUEST__SHIFT 0x2
++#define DSI0_DISP_DSI_LANE_CTRL__DLN3_ULPS_REQUEST__SHIFT 0x3
++#define DSI0_DISP_DSI_LANE_CTRL__DLN0_ULPS_EXIT__SHIFT 0x4
++#define DSI0_DISP_DSI_LANE_CTRL__DLN1_ULPS_EXIT__SHIFT 0x5
++#define DSI0_DISP_DSI_LANE_CTRL__DLN2_ULPS_EXIT__SHIFT 0x6
++#define DSI0_DISP_DSI_LANE_CTRL__DLN3_ULPS_EXIT__SHIFT 0x7
++#define DSI0_DISP_DSI_LANE_CTRL__DLN0_FORCE_TX_STOP__SHIFT 0x8
++#define DSI0_DISP_DSI_LANE_CTRL__DLN1_FORCE_TX_STOP__SHIFT 0x9
++#define DSI0_DISP_DSI_LANE_CTRL__DLN2_FORCE_TX_STOP__SHIFT 0xa
++#define DSI0_DISP_DSI_LANE_CTRL__DLN3_FORCE_TX_STOP__SHIFT 0xb
++#define DSI0_DISP_DSI_LANE_CTRL__CLKLN_ULPS_REQUEST__SHIFT 0xc
++#define DSI0_DISP_DSI_LANE_CTRL__CLKLN_ULPS_EXIT__SHIFT 0x10
++#define DSI0_DISP_DSI_LANE_CTRL__CLKLN_FORCE_TX_STOP__SHIFT 0x14
++#define DSI0_DISP_DSI_LANE_CTRL__CLKLN_HS_FORCE_REQUEST__SHIFT 0x18
++#define DSI0_DISP_DSI_LANE_CTRL__DLN0_ULPS_REQUEST_MASK 0x00000001L
++#define DSI0_DISP_DSI_LANE_CTRL__DLN1_ULPS_REQUEST_MASK 0x00000002L
++#define DSI0_DISP_DSI_LANE_CTRL__DLN2_ULPS_REQUEST_MASK 0x00000004L
++#define DSI0_DISP_DSI_LANE_CTRL__DLN3_ULPS_REQUEST_MASK 0x00000008L
++#define DSI0_DISP_DSI_LANE_CTRL__DLN0_ULPS_EXIT_MASK 0x00000010L
++#define DSI0_DISP_DSI_LANE_CTRL__DLN1_ULPS_EXIT_MASK 0x00000020L
++#define DSI0_DISP_DSI_LANE_CTRL__DLN2_ULPS_EXIT_MASK 0x00000040L
++#define DSI0_DISP_DSI_LANE_CTRL__DLN3_ULPS_EXIT_MASK 0x00000080L
++#define DSI0_DISP_DSI_LANE_CTRL__DLN0_FORCE_TX_STOP_MASK 0x00000100L
++#define DSI0_DISP_DSI_LANE_CTRL__DLN1_FORCE_TX_STOP_MASK 0x00000200L
++#define DSI0_DISP_DSI_LANE_CTRL__DLN2_FORCE_TX_STOP_MASK 0x00000400L
++#define DSI0_DISP_DSI_LANE_CTRL__DLN3_FORCE_TX_STOP_MASK 0x00000800L
++#define DSI0_DISP_DSI_LANE_CTRL__CLKLN_ULPS_REQUEST_MASK 0x00001000L
++#define DSI0_DISP_DSI_LANE_CTRL__CLKLN_ULPS_EXIT_MASK 0x00010000L
++#define DSI0_DISP_DSI_LANE_CTRL__CLKLN_FORCE_TX_STOP_MASK 0x00100000L
++#define DSI0_DISP_DSI_LANE_CTRL__CLKLN_HS_FORCE_REQUEST_MASK 0x01000000L
++//DSI0_DISP_DSI_DLN0_PHY_ERROR
++#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC__SHIFT 0x0
++#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC_CLR__SHIFT 0x0
++#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC_MASK__SHIFT 0x3
++#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC__SHIFT 0x4
++#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC_CLR__SHIFT 0x4
++#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC_MASK__SHIFT 0x7
++#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL__SHIFT 0x8
++#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL_CLR__SHIFT 0x8
++#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL_MASK__SHIFT 0xb
++#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0__SHIFT 0xc
++#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0_CLR__SHIFT 0xc
++#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0_MASK__SHIFT 0xf
++#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1__SHIFT 0x10
++#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1_CLR__SHIFT 0x10
++#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1_MASK__SHIFT 0x13
++#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC_MASK 0x00000001L
++#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC_CLR_MASK 0x00000001L
++#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC_MASK_MASK 0x00000008L
++#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC_MASK 0x00000010L
++#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC_CLR_MASK 0x00000010L
++#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC_MASK_MASK 0x00000080L
++#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL_MASK 0x00000100L
++#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL_CLR_MASK 0x00000100L
++#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL_MASK_MASK 0x00000800L
++#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0_MASK 0x00001000L
++#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0_CLR_MASK 0x00001000L
++#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0_MASK_MASK 0x00008000L
++#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1_MASK 0x00010000L
++#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1_CLR_MASK 0x00010000L
++#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1_MASK_MASK 0x00080000L
++//DSI0_DISP_DSI_LP_TIMER_CTRL
++#define DSI0_DISP_DSI_LP_TIMER_CTRL__LP_RX_TO__SHIFT 0x0
++#define DSI0_DISP_DSI_LP_TIMER_CTRL__BTA_TO__SHIFT 0x10
++#define DSI0_DISP_DSI_LP_TIMER_CTRL__LP_RX_TO_MASK 0x0000FFFFL
++#define DSI0_DISP_DSI_LP_TIMER_CTRL__BTA_TO_MASK 0xFFFF0000L
++//DSI0_DISP_DSI_HS_TIMER_CTRL
++#define DSI0_DISP_DSI_HS_TIMER_CTRL__HS_TX_TO__SHIFT 0x0
++#define DSI0_DISP_DSI_HS_TIMER_CTRL__HS_TX_TO_MASK 0x0000FFFFL
++//DSI0_DISP_DSI_TIMEOUT_STATUS
++#define DSI0_DISP_DSI_TIMEOUT_STATUS__HS_TX_TIMEOUT__SHIFT 0x0
++#define DSI0_DISP_DSI_TIMEOUT_STATUS__HS_TX_TIMEOUT_CLR__SHIFT 0x0
++#define DSI0_DISP_DSI_TIMEOUT_STATUS__LP_RX_TIMEOUT__SHIFT 0x4
++#define DSI0_DISP_DSI_TIMEOUT_STATUS__LP_RX_TIMEOUT_CLR__SHIFT 0x4
++#define DSI0_DISP_DSI_TIMEOUT_STATUS__BTA_TIMEOUT__SHIFT 0x8
++#define DSI0_DISP_DSI_TIMEOUT_STATUS__BTA_TIMEOUT_CLR__SHIFT 0x8
++#define DSI0_DISP_DSI_TIMEOUT_STATUS__HS_TX_TIMEOUT_MASK 0x00000001L
++#define DSI0_DISP_DSI_TIMEOUT_STATUS__HS_TX_TIMEOUT_CLR_MASK 0x00000001L
++#define DSI0_DISP_DSI_TIMEOUT_STATUS__LP_RX_TIMEOUT_MASK 0x00000010L
++#define DSI0_DISP_DSI_TIMEOUT_STATUS__LP_RX_TIMEOUT_CLR_MASK 0x00000010L
++#define DSI0_DISP_DSI_TIMEOUT_STATUS__BTA_TIMEOUT_MASK 0x00000100L
++#define DSI0_DISP_DSI_TIMEOUT_STATUS__BTA_TIMEOUT_CLR_MASK 0x00000100L
++//DSI0_DISP_DSI_PHY_CLK_TIMING_CTRL
++#define DSI0_DISP_DSI_PHY_CLK_TIMING_CTRL__T_CLK_PRE__SHIFT 0x0
++#define DSI0_DISP_DSI_PHY_CLK_TIMING_CTRL__T_CLK_POST__SHIFT 0x8
++#define DSI0_DISP_DSI_PHY_CLK_TIMING_CTRL__T_CLK_PRE_MASK 0x000000FFL
++#define DSI0_DISP_DSI_PHY_CLK_TIMING_CTRL__T_CLK_POST_MASK 0x00003F00L
++//DSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2
++#define DSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2__T_PRE_TRIGGER__SHIFT 0x0
++#define DSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2__T_INTER_STOP__SHIFT 0x10
++#define DSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2__T_PRE_TRIGGER_MASK 0x000007FFL
++#define DSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2__T_INTER_STOP_MASK 0xFFFF0000L
++//DSI0_DISP_DSI_EOT_PACKET
++#define DSI0_DISP_DSI_EOT_PACKET__DI__SHIFT 0x0
++#define DSI0_DISP_DSI_EOT_PACKET__WC__SHIFT 0x8
++#define DSI0_DISP_DSI_EOT_PACKET__ECC__SHIFT 0x18
++#define DSI0_DISP_DSI_EOT_PACKET__DI_MASK 0x000000FFL
++#define DSI0_DISP_DSI_EOT_PACKET__WC_MASK 0x00FFFF00L
++#define DSI0_DISP_DSI_EOT_PACKET__ECC_MASK 0xFF000000L
++//DSI0_DISP_DSI_EOT_PACKET_CTRL
++#define DSI0_DISP_DSI_EOT_PACKET_CTRL__TX_EOT_APPEND__SHIFT 0x0
++#define DSI0_DISP_DSI_EOT_PACKET_CTRL__RX_EOT_IGNORE__SHIFT 0x4
++#define DSI0_DISP_DSI_EOT_PACKET_CTRL__TX_EOT_APPEND_MASK 0x00000001L
++#define DSI0_DISP_DSI_EOT_PACKET_CTRL__RX_EOT_IGNORE_MASK 0x00000010L
++//DSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER
++#define DSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER__SW_TRIGGER__SHIFT 0x0
++#define DSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER__ENTRY_COMMAND__SHIFT 0x10
++#define DSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER__SW_TRIGGER_MASK 0x00000001L
++#define DSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER__ENTRY_COMMAND_MASK 0x00FF0000L
++//DSI0_DISP_DSI_MIPI_BIST_CTRL
++#define DSI0_DISP_DSI_MIPI_BIST_CTRL__MIPI_BIST_RESET__SHIFT 0x0
++#define DSI0_DISP_DSI_MIPI_BIST_CTRL__MIPI_BIST_EN__SHIFT 0x1
++#define DSI0_DISP_DSI_MIPI_BIST_CTRL__MIPI_BIST_RESET_MASK 0x00000001L
++#define DSI0_DISP_DSI_MIPI_BIST_CTRL__MIPI_BIST_EN_MASK 0x00000002L
++//DSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE
++#define DSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE__MIPI_H_SIZE__SHIFT 0x0
++#define DSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE__MIPI_V_SIZE__SHIFT 0x10
++#define DSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE__MIPI_H_SIZE_MASK 0x0000FFFFL
++#define DSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE__MIPI_V_SIZE_MASK 0xFFFF0000L
++//DSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE
++#define DSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE__MIPI_H_SIZE__SHIFT 0x0
++#define DSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE__MIPI_V_SIZE__SHIFT 0x8
++#define DSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE__MIPI_H_SIZE_MASK 0x000000FFL
++#define DSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE__MIPI_V_SIZE_MASK 0x0000FF00L
++//DSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG
++#define DSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_BLANKING_CYCLES__SHIFT 0x0
++#define DSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_FRAME_REPEAT__SHIFT 0x10
++#define DSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_BIST_VIDEO_FRMT__SHIFT 0x18
++#define DSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_BLANKING_CYCLES_MASK 0x0000FFFFL
++#define DSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_FRAME_REPEAT_MASK 0x00FF0000L
++#define DSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_BIST_VIDEO_FRMT_MASK 0x01000000L
++//DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL
++#define DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_Y_LSFR_POLYNOMIAL__SHIFT 0x0
++#define DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_U_LSFR_POLYNOMIAL__SHIFT 0x8
++#define DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_V_LSFR_POLYNOMIAL__SHIFT 0x10
++#define DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_Y_LSFR_EN__SHIFT 0x18
++#define DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_U_LSFR_EN__SHIFT 0x19
++#define DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_V_LSFR_EN__SHIFT 0x1a
++#define DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_Y_LSFR_POLYNOMIAL_MASK 0x000000FFL
++#define DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_U_LSFR_POLYNOMIAL_MASK 0x0000FF00L
++#define DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_V_LSFR_POLYNOMIAL_MASK 0x00FF0000L
++#define DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_Y_LSFR_EN_MASK 0x01000000L
++#define DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_U_LSFR_EN_MASK 0x02000000L
++#define DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_V_LSFR_EN_MASK 0x04000000L
++//DSI0_DISP_DSI_MIPI_BIST_LSFR_INIT
++#define DSI0_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_Y_INIT_LSFR_VAL__SHIFT 0x0
++#define DSI0_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_U_INIT_LSFR_VAL__SHIFT 0x8
++#define DSI0_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_V_INIT_LSFR_VAL__SHIFT 0x10
++#define DSI0_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_Y_INIT_LSFR_VAL_MASK 0x000000FFL
++#define DSI0_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_U_INIT_LSFR_VAL_MASK 0x0000FF00L
++#define DSI0_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_V_INIT_LSFR_VAL_MASK 0x00FF0000L
++//DSI0_DISP_DSI_MIPI_BIST_START
++#define DSI0_DISP_DSI_MIPI_BIST_START__MIPI_BIST_START__SHIFT 0x0
++#define DSI0_DISP_DSI_MIPI_BIST_START__MIPI_BIST_START_MASK 0x00000001L
++//DSI0_DISP_DSI_MIPI_BIST_STATUS
++#define DSI0_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_STATUS_BUSY__SHIFT 0x0
++#define DSI0_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_DONE__SHIFT 0x4
++#define DSI0_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_DONE_CLR__SHIFT 0x4
++#define DSI0_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_STATUS_BUSY_MASK 0x00000001L
++#define DSI0_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_DONE_MASK 0x00000010L
++#define DSI0_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_DONE_CLR_MASK 0x00000010L
++//DSI0_DISP_DSI_ERROR_INTERRUPT_MASK
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_ECC_ERR_MASK__SHIFT 0x0
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_MULTI_ECC_ERR_MASK__SHIFT 0x1
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_CRC_ERR_MASK__SHIFT 0x2
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_INCOMPLETE_PACKET_ERR_MASK__SHIFT 0x3
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__ERROR_PACKET_MASK__SHIFT 0x4
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__INTERLEAVE_PACKET_BLOCK_MASK__SHIFT 0x5
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__TE_ABORT_MASK__SHIFT 0x6
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_ESC_MASK__SHIFT 0x8
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_SYNC_ESC_MASK__SHIFT 0x9
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTROL_MASK__SHIFT 0xa
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTENTION_LP0_MASK__SHIFT 0xc
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTENTION_LP1_MASK__SHIFT 0xd
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__LP_RX_TO_MASK__SHIFT 0x10
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__HS_TX_TO_MASK__SHIFT 0x11
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__BTA_TO_MASK__SHIFT 0x12
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DMAFIFO_UNDERFLOW_MASK__SHIFT 0x14
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__CMDFIFO_UNDERFLOW_MASK__SHIFT 0x15
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DENGFIFO_OVERFLOW_UNDERFLOW_MASK__SHIFT 0x18
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_HS_FIFO_OVERFLOW_MASK__SHIFT 0x1a
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN1_HS_FIFO_OVERFLOW_MASK__SHIFT 0x1b
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN2_HS_FIFO_OVERFLOW_MASK__SHIFT 0x1c
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN3_HS_FIFO_OVERFLOW_MASK__SHIFT 0x1d
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_LP_FIFO_OVERFLOW_MASK__SHIFT 0x1e
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__INTERLEAVE_OP_CONTENTION_MASK__SHIFT 0x1f
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_ECC_ERR_MASK_MASK 0x00000001L
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_MULTI_ECC_ERR_MASK_MASK 0x00000002L
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_CRC_ERR_MASK_MASK 0x00000004L
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_INCOMPLETE_PACKET_ERR_MASK_MASK 0x00000008L
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__ERROR_PACKET_MASK_MASK 0x00000010L
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__INTERLEAVE_PACKET_BLOCK_MASK_MASK 0x00000020L
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__TE_ABORT_MASK_MASK 0x00000040L
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_ESC_MASK_MASK 0x00000100L
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_SYNC_ESC_MASK_MASK 0x00000200L
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTROL_MASK_MASK 0x00000400L
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTENTION_LP0_MASK_MASK 0x00001000L
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTENTION_LP1_MASK_MASK 0x00002000L
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__LP_RX_TO_MASK_MASK 0x00010000L
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__HS_TX_TO_MASK_MASK 0x00020000L
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__BTA_TO_MASK_MASK 0x00040000L
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DMAFIFO_UNDERFLOW_MASK_MASK 0x00100000L
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__CMDFIFO_UNDERFLOW_MASK_MASK 0x00200000L
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DENGFIFO_OVERFLOW_UNDERFLOW_MASK_MASK 0x01000000L
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_HS_FIFO_OVERFLOW_MASK_MASK 0x04000000L
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN1_HS_FIFO_OVERFLOW_MASK_MASK 0x08000000L
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN2_HS_FIFO_OVERFLOW_MASK_MASK 0x10000000L
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN3_HS_FIFO_OVERFLOW_MASK_MASK 0x20000000L
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_LP_FIFO_OVERFLOW_MASK_MASK 0x40000000L
++#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__INTERLEAVE_OP_CONTENTION_MASK_MASK 0x80000000L
++//DSI0_DISP_DSI_INTERRUPT_CTRL
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_STAT__SHIFT 0x0
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_AK__SHIFT 0x0
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_MASK__SHIFT 0x1
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_STAT__SHIFT 0x4
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_AK__SHIFT 0x4
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_MASK__SHIFT 0x5
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_STAT__SHIFT 0x8
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_AK__SHIFT 0x8
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_MASK__SHIFT 0x9
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_STAT__SHIFT 0xc
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_AK__SHIFT 0xc
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_MASK__SHIFT 0xd
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_STAT__SHIFT 0x10
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_AK__SHIFT 0x10
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_MASK__SHIFT 0x11
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_STAT__SHIFT 0x14
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_AK__SHIFT 0x14
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_MASK__SHIFT 0x15
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_STAT__SHIFT 0x18
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_AK__SHIFT 0x18
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_MASK__SHIFT 0x19
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_STAT_MASK 0x00000001L
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_AK_MASK 0x00000001L
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_MASK_MASK 0x00000002L
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_STAT_MASK 0x00000010L
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_AK_MASK 0x00000010L
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_MASK_MASK 0x00000020L
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_STAT_MASK 0x00000100L
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_AK_MASK 0x00000100L
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_MASK_MASK 0x00000200L
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_STAT_MASK 0x00001000L
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_AK_MASK 0x00001000L
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_MASK_MASK 0x00002000L
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_STAT_MASK 0x00010000L
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_AK_MASK 0x00010000L
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_MASK_MASK 0x00020000L
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_STAT_MASK 0x00100000L
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_AK_MASK 0x00100000L
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_MASK_MASK 0x00200000L
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_STAT_MASK 0x01000000L
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_AK_MASK 0x01000000L
++#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_MASK_MASK 0x02000000L
++//DSI0_DISP_DSI_CLK_CTRL
++#define DSI0_DISP_DSI_CLK_CTRL__DISPCLK_G_ON__SHIFT 0x0
++#define DSI0_DISP_DSI_CLK_CTRL__DISPCLK_R_ON__SHIFT 0x1
++#define DSI0_DISP_DSI_CLK_CTRL__DSICLK_G_ON__SHIFT 0x4
++#define DSI0_DISP_DSI_CLK_CTRL__DSICLK_R_ON__SHIFT 0x5
++#define DSI0_DISP_DSI_CLK_CTRL__DSICLK_TRN_ON__SHIFT 0x6
++#define DSI0_DISP_DSI_CLK_CTRL__BYTECLK_G_ON__SHIFT 0x8
++#define DSI0_DISP_DSI_CLK_CTRL__ESCCLK_G_ON__SHIFT 0x10
++#define DSI0_DISP_DSI_CLK_CTRL__TEST_CLK_SEL__SHIFT 0x18
++#define DSI0_DISP_DSI_CLK_CTRL__DISPCLK_G_ON_MASK 0x00000001L
++#define DSI0_DISP_DSI_CLK_CTRL__DISPCLK_R_ON_MASK 0x00000002L
++#define DSI0_DISP_DSI_CLK_CTRL__DSICLK_G_ON_MASK 0x00000010L
++#define DSI0_DISP_DSI_CLK_CTRL__DSICLK_R_ON_MASK 0x00000020L
++#define DSI0_DISP_DSI_CLK_CTRL__DSICLK_TRN_ON_MASK 0x00000040L
++#define DSI0_DISP_DSI_CLK_CTRL__BYTECLK_G_ON_MASK 0x00000100L
++#define DSI0_DISP_DSI_CLK_CTRL__ESCCLK_G_ON_MASK 0x00010000L
++#define DSI0_DISP_DSI_CLK_CTRL__TEST_CLK_SEL_MASK 0x0F000000L
++//DSI0_DISP_DSI_CLK_STATUS
++#define DSI0_DISP_DSI_CLK_STATUS__DISPCLK_R_ACTIVE__SHIFT 0x0
++#define DSI0_DISP_DSI_CLK_STATUS__DISPCLK_G_ACTIVE__SHIFT 0x1
++#define DSI0_DISP_DSI_CLK_STATUS__DSICLK_R_ACTIVE__SHIFT 0x4
++#define DSI0_DISP_DSI_CLK_STATUS__DSICLK_G_ACTIVE__SHIFT 0x5
++#define DSI0_DISP_DSI_CLK_STATUS__DSICLK_TRN_ACTIVE__SHIFT 0x6
++#define DSI0_DISP_DSI_CLK_STATUS__BYTECLK_G_ACTIVE__SHIFT 0x8
++#define DSI0_DISP_DSI_CLK_STATUS__ESCCLK_G_ACTIVE__SHIFT 0x10
++#define DSI0_DISP_DSI_CLK_STATUS__DISPCLK_R_ACTIVE_MASK 0x00000001L
++#define DSI0_DISP_DSI_CLK_STATUS__DISPCLK_G_ACTIVE_MASK 0x00000002L
++#define DSI0_DISP_DSI_CLK_STATUS__DSICLK_R_ACTIVE_MASK 0x00000010L
++#define DSI0_DISP_DSI_CLK_STATUS__DSICLK_G_ACTIVE_MASK 0x00000020L
++#define DSI0_DISP_DSI_CLK_STATUS__DSICLK_TRN_ACTIVE_MASK 0x00000040L
++#define DSI0_DISP_DSI_CLK_STATUS__BYTECLK_G_ACTIVE_MASK 0x00000100L
++#define DSI0_DISP_DSI_CLK_STATUS__ESCCLK_G_ACTIVE_MASK 0x00010000L
++//DSI0_DISP_DSI_DENG_FIFO_STATUS
++#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_LEVEL_ERROR__SHIFT 0x0
++#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
++#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
++#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_ERROR_ACK__SHIFT 0x9
++#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
++#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_MAXIMUM_LEVEL__SHIFT 0x11
++#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_MINIMUM_LEVEL__SHIFT 0x17
++#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_CALIBRATED__SHIFT 0x1d
++#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
++#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
++#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_LEVEL_ERROR_MASK 0x00000001L
++#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L
++#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_OVERWRITE_LEVEL_MASK 0x000001FCL
++#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_ERROR_ACK_MASK 0x00000200L
++#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0001FC00L
++#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_MAXIMUM_LEVEL_MASK 0x007E0000L
++#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_MINIMUM_LEVEL_MASK 0x0F800000L
++#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_CALIBRATED_MASK 0x20000000L
++#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L
++#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L
++//DSI0_DISP_DSI_DENG_FIFO_CTRL
++#define DSI0_DISP_DSI_DENG_FIFO_CTRL__DENG_FIFO_EN__SHIFT 0x0
++#define DSI0_DISP_DSI_DENG_FIFO_CTRL__DENG_FIFO_START__SHIFT 0x4
++#define DSI0_DISP_DSI_DENG_FIFO_CTRL__DENG_DSICLK_ON__SHIFT 0x8
++#define DSI0_DISP_DSI_DENG_FIFO_CTRL__DENG_FIFO_EN_MASK 0x00000001L
++#define DSI0_DISP_DSI_DENG_FIFO_CTRL__DENG_FIFO_START_MASK 0x00000010L
++#define DSI0_DISP_DSI_DENG_FIFO_CTRL__DENG_DSICLK_ON_MASK 0x00000100L
++//DSI0_DISP_DSI_CMD_FIFO_DATA
++#define DSI0_DISP_DSI_CMD_FIFO_DATA__CMDFIFO_DATA__SHIFT 0x0
++#define DSI0_DISP_DSI_CMD_FIFO_DATA__CMDFIFO_DATA_MASK 0xFFFFFFFFL
++//DSI0_DISP_DSI_CMD_FIFO_CTRL
++#define DSI0_DISP_DSI_CMD_FIFO_CTRL__USE_CMDFIFO__SHIFT 0x0
++#define DSI0_DISP_DSI_CMD_FIFO_CTRL__CMDFIFO_DW_LEVEL__SHIFT 0x4
++#define DSI0_DISP_DSI_CMD_FIFO_CTRL__USE_CMDFIFO_MASK 0x00000001L
++#define DSI0_DISP_DSI_CMD_FIFO_CTRL__CMDFIFO_DW_LEVEL_MASK 0x000007F0L
++//DSI0_DISP_DSI_TE_CTRL
++#define DSI0_DISP_DSI_TE_CTRL__FREEZE_CRTC_HYSTERESIS__SHIFT 0x0
++#define DSI0_DISP_DSI_TE_CTRL__DISABLE_CRTC_FREEZE__SHIFT 0x10
++#define DSI0_DISP_DSI_TE_CTRL__DISABLE_CRTC_FORCE__SHIFT 0x14
++#define DSI0_DISP_DSI_TE_CTRL__CRTC_FREEZE__SHIFT 0x18
++#define DSI0_DISP_DSI_TE_CTRL__CRTC_FREEZE_TRIG__SHIFT 0x18
++#define DSI0_DISP_DSI_TE_CTRL__FREEZE_CRTC_HYSTERESIS_MASK 0x00000FFFL
++#define DSI0_DISP_DSI_TE_CTRL__DISABLE_CRTC_FREEZE_MASK 0x00010000L
++#define DSI0_DISP_DSI_TE_CTRL__DISABLE_CRTC_FORCE_MASK 0x00100000L
++#define DSI0_DISP_DSI_TE_CTRL__CRTC_FREEZE_MASK 0x01000000L
++#define DSI0_DISP_DSI_TE_CTRL__CRTC_FREEZE_TRIG_MASK 0x01000000L
++//DSI0_DISP_DSI_LANE_STATUS
++#define DSI0_DISP_DSI_LANE_STATUS__DLN0_STOPSTATE__SHIFT 0x0
++#define DSI0_DISP_DSI_LANE_STATUS__DLN1_STOPSTATE__SHIFT 0x1
++#define DSI0_DISP_DSI_LANE_STATUS__DLN2_STOPSTATE__SHIFT 0x2
++#define DSI0_DISP_DSI_LANE_STATUS__DLN3_STOPSTATE__SHIFT 0x3
++#define DSI0_DISP_DSI_LANE_STATUS__DLN0_ULPS_ACTIVE_NOT__SHIFT 0x4
++#define DSI0_DISP_DSI_LANE_STATUS__DLN1_ULPS_ACTIVE_NOT__SHIFT 0x5
++#define DSI0_DISP_DSI_LANE_STATUS__DLN2_ULPS_ACTIVE_NOT__SHIFT 0x6
++#define DSI0_DISP_DSI_LANE_STATUS__DLN3_ULPS_ACTIVE_NOT__SHIFT 0x7
++#define DSI0_DISP_DSI_LANE_STATUS__DLN0_DIRECTION__SHIFT 0x8
++#define DSI0_DISP_DSI_LANE_STATUS__CLKLN_STOPSTATE__SHIFT 0x18
++#define DSI0_DISP_DSI_LANE_STATUS__CLKLN_ULPS_ACTIVE_NOT__SHIFT 0x1c
++#define DSI0_DISP_DSI_LANE_STATUS__DLN0_STOPSTATE_MASK 0x00000001L
++#define DSI0_DISP_DSI_LANE_STATUS__DLN1_STOPSTATE_MASK 0x00000002L
++#define DSI0_DISP_DSI_LANE_STATUS__DLN2_STOPSTATE_MASK 0x00000004L
++#define DSI0_DISP_DSI_LANE_STATUS__DLN3_STOPSTATE_MASK 0x00000008L
++#define DSI0_DISP_DSI_LANE_STATUS__DLN0_ULPS_ACTIVE_NOT_MASK 0x00000010L
++#define DSI0_DISP_DSI_LANE_STATUS__DLN1_ULPS_ACTIVE_NOT_MASK 0x00000020L
++#define DSI0_DISP_DSI_LANE_STATUS__DLN2_ULPS_ACTIVE_NOT_MASK 0x00000040L
++#define DSI0_DISP_DSI_LANE_STATUS__DLN3_ULPS_ACTIVE_NOT_MASK 0x00000080L
++#define DSI0_DISP_DSI_LANE_STATUS__DLN0_DIRECTION_MASK 0x00000100L
++#define DSI0_DISP_DSI_LANE_STATUS__CLKLN_STOPSTATE_MASK 0x01000000L
++#define DSI0_DISP_DSI_LANE_STATUS__CLKLN_ULPS_ACTIVE_NOT_MASK 0x10000000L
++//DSI0_DISP_DSI_PERF_CTRL
++#define DSI0_DISP_DSI_PERF_CTRL__PERF_LP_HS_LATENCY_SEL__SHIFT 0x0
++#define DSI0_DISP_DSI_PERF_CTRL__PERF_HS_LP_LATENCY_SEL__SHIFT 0x4
++#define DSI0_DISP_DSI_PERF_CTRL__PERF_LP_HS_LATENCY_SEL_MASK 0x00000003L
++#define DSI0_DISP_DSI_PERF_CTRL__PERF_HS_LP_LATENCY_SEL_MASK 0x00000030L
++//DSI0_DISP_DSI_HSYNC_LENGTH
++#define DSI0_DISP_DSI_HSYNC_LENGTH__HSYNC_LENGTH_MAX__SHIFT 0x0
++#define DSI0_DISP_DSI_HSYNC_LENGTH__HSYNC_LENGTH_MIN__SHIFT 0x10
++#define DSI0_DISP_DSI_HSYNC_LENGTH__HSYNC_LENGTH_MAX_MASK 0x0000FFFFL
++#define DSI0_DISP_DSI_HSYNC_LENGTH__HSYNC_LENGTH_MIN_MASK 0xFFFF0000L
++//DSI0_DISP_DSI_RDBK_NUM
++#define DSI0_DISP_DSI_RDBK_NUM__RD_NUM__SHIFT 0x0
++#define DSI0_DISP_DSI_RDBK_NUM__ALL_NUM__SHIFT 0x10
++#define DSI0_DISP_DSI_RDBK_NUM__RD_NUM_MASK 0x0000FFFFL
++#define DSI0_DISP_DSI_RDBK_NUM__ALL_NUM_MASK 0xFFFF0000L
++//DSI0_DISP_DSI_CMD_MEM_PWR_CTRL
++#define DSI0_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_DIS__SHIFT 0x0
++#define DSI0_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_FORCE__SHIFT 0x4
++#define DSI0_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_STATE__SHIFT 0x8
++#define DSI0_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_MODE_SEL__SHIFT 0xc
++#define DSI0_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_DIS_MASK 0x00000001L
++#define DSI0_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_FORCE_MASK 0x00000030L
++#define DSI0_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_STATE_MASK 0x00000300L
++#define DSI0_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_MODE_SEL_MASK 0x00003000L
++
++
++// addressBlock: dce_dc_dsi1_dispdec
++//DSI1_DISP_DSI_CTRL
++#define DSI1_DISP_DSI_CTRL__DSI_EN__SHIFT 0x0
++#define DSI1_DISP_DSI_CTRL__VIDEO_MODE_EN__SHIFT 0x1
++#define DSI1_DISP_DSI_CTRL__CMD_MODE_EN__SHIFT 0x2
++#define DSI1_DISP_DSI_CTRL__DLN0_EN__SHIFT 0x4
++#define DSI1_DISP_DSI_CTRL__DLN1_EN__SHIFT 0x5
++#define DSI1_DISP_DSI_CTRL__DLN2_EN__SHIFT 0x6
++#define DSI1_DISP_DSI_CTRL__DLN3_EN__SHIFT 0x7
++#define DSI1_DISP_DSI_CTRL__CLKLN_EN__SHIFT 0x8
++#define DSI1_DISP_DSI_CTRL__DLN0_PHY_EN__SHIFT 0xc
++#define DSI1_DISP_DSI_CTRL__DLN1_PHY_EN__SHIFT 0xd
++#define DSI1_DISP_DSI_CTRL__DLN2_PHY_EN__SHIFT 0xe
++#define DSI1_DISP_DSI_CTRL__DLN3_PHY_EN__SHIFT 0xf
++#define DSI1_DISP_DSI_CTRL__RESET_DISPCLK__SHIFT 0x10
++#define DSI1_DISP_DSI_CTRL__RESET_DSICLK__SHIFT 0x11
++#define DSI1_DISP_DSI_CTRL__RESET_BYTECLK__SHIFT 0x12
++#define DSI1_DISP_DSI_CTRL__RESET_ESCCLK__SHIFT 0x13
++#define DSI1_DISP_DSI_CTRL__CRTC_SEL__SHIFT 0x14
++#define DSI1_DISP_DSI_CTRL__ECC_CHK_EN__SHIFT 0x18
++#define DSI1_DISP_DSI_CTRL__CRC_CHK_EN__SHIFT 0x19
++#define DSI1_DISP_DSI_CTRL__PACKET_BYTE_MSB_LSB_FLIP__SHIFT 0x1c
++#define DSI1_DISP_DSI_CTRL__PRE_TRIGGER_EN__SHIFT 0x1d
++#define DSI1_DISP_DSI_CTRL__NEW_INTERLEAVE_MODE_EN__SHIFT 0x1e
++#define DSI1_DISP_DSI_CTRL__DSI_EN_MASK 0x00000001L
++#define DSI1_DISP_DSI_CTRL__VIDEO_MODE_EN_MASK 0x00000002L
++#define DSI1_DISP_DSI_CTRL__CMD_MODE_EN_MASK 0x00000004L
++#define DSI1_DISP_DSI_CTRL__DLN0_EN_MASK 0x00000010L
++#define DSI1_DISP_DSI_CTRL__DLN1_EN_MASK 0x00000020L
++#define DSI1_DISP_DSI_CTRL__DLN2_EN_MASK 0x00000040L
++#define DSI1_DISP_DSI_CTRL__DLN3_EN_MASK 0x00000080L
++#define DSI1_DISP_DSI_CTRL__CLKLN_EN_MASK 0x00000100L
++#define DSI1_DISP_DSI_CTRL__DLN0_PHY_EN_MASK 0x00001000L
++#define DSI1_DISP_DSI_CTRL__DLN1_PHY_EN_MASK 0x00002000L
++#define DSI1_DISP_DSI_CTRL__DLN2_PHY_EN_MASK 0x00004000L
++#define DSI1_DISP_DSI_CTRL__DLN3_PHY_EN_MASK 0x00008000L
++#define DSI1_DISP_DSI_CTRL__RESET_DISPCLK_MASK 0x00010000L
++#define DSI1_DISP_DSI_CTRL__RESET_DSICLK_MASK 0x00020000L
++#define DSI1_DISP_DSI_CTRL__RESET_BYTECLK_MASK 0x00040000L
++#define DSI1_DISP_DSI_CTRL__RESET_ESCCLK_MASK 0x00080000L
++#define DSI1_DISP_DSI_CTRL__CRTC_SEL_MASK 0x00700000L
++#define DSI1_DISP_DSI_CTRL__ECC_CHK_EN_MASK 0x01000000L
++#define DSI1_DISP_DSI_CTRL__CRC_CHK_EN_MASK 0x02000000L
++#define DSI1_DISP_DSI_CTRL__PACKET_BYTE_MSB_LSB_FLIP_MASK 0x10000000L
++#define DSI1_DISP_DSI_CTRL__PRE_TRIGGER_EN_MASK 0x20000000L
++#define DSI1_DISP_DSI_CTRL__NEW_INTERLEAVE_MODE_EN_MASK 0x40000000L
++//DSI1_DISP_DSI_STATUS
++#define DSI1_DISP_DSI_STATUS__CMD_MODE_ENGINE_BUSY__SHIFT 0x0
++#define DSI1_DISP_DSI_STATUS__CMD_MODE_DMA_BUSY__SHIFT 0x1
++#define DSI1_DISP_DSI_STATUS__CMD_MODE_DENG_BUSY__SHIFT 0x2
++#define DSI1_DISP_DSI_STATUS__VIDEO_MODE_ENGINE_BUSY__SHIFT 0x3
++#define DSI1_DISP_DSI_STATUS__BTA_BUSY__SHIFT 0x4
++#define DSI1_DISP_DSI_STATUS__GENERIC_TRIGGER_BUSY__SHIFT 0x5
++#define DSI1_DISP_DSI_STATUS__PHY_RESET_BUSY__SHIFT 0x6
++#define DSI1_DISP_DSI_STATUS__DLN0_HS_FIFO_EMPTY__SHIFT 0x8
++#define DSI1_DISP_DSI_STATUS__DLN0_HS_FIFO_FULL__SHIFT 0x9
++#define DSI1_DISP_DSI_STATUS__DLN1_HS_FIFO_EMPTY__SHIFT 0xa
++#define DSI1_DISP_DSI_STATUS__DLN1_HS_FIFO_FULL__SHIFT 0xb
++#define DSI1_DISP_DSI_STATUS__DLN2_HS_FIFO_EMPTY__SHIFT 0xc
++#define DSI1_DISP_DSI_STATUS__DLN2_HS_FIFO_FULL__SHIFT 0xd
++#define DSI1_DISP_DSI_STATUS__DLN3_HS_FIFO_EMPTY__SHIFT 0xe
++#define DSI1_DISP_DSI_STATUS__DLN3_HS_FIFO_FULL__SHIFT 0xf
++#define DSI1_DISP_DSI_STATUS__DLN0_HS_FIFO_OVERFLOW__SHIFT 0x10
++#define DSI1_DISP_DSI_STATUS__DLN0_HS_FIFO_OVERFLOW_CLR__SHIFT 0x10
++#define DSI1_DISP_DSI_STATUS__DLN1_HS_FIFO_OVERFLOW__SHIFT 0x11
++#define DSI1_DISP_DSI_STATUS__DLN1_HS_FIFO_OVERFLOW_CLR__SHIFT 0x11
++#define DSI1_DISP_DSI_STATUS__DLN2_HS_FIFO_OVERFLOW__SHIFT 0x12
++#define DSI1_DISP_DSI_STATUS__DLN2_HS_FIFO_OVERFLOW_CLR__SHIFT 0x12
++#define DSI1_DISP_DSI_STATUS__DLN3_HS_FIFO_OVERFLOW__SHIFT 0x13
++#define DSI1_DISP_DSI_STATUS__DLN3_HS_FIFO_OVERFLOW_CLR__SHIFT 0x13
++#define DSI1_DISP_DSI_STATUS__DLN0_LP_FIFO_EMPTY__SHIFT 0x14
++#define DSI1_DISP_DSI_STATUS__DLN0_LP_FIFO_FULL__SHIFT 0x15
++#define DSI1_DISP_DSI_STATUS__DLN0_LP_FIFO_OVERFLOW__SHIFT 0x16
++#define DSI1_DISP_DSI_STATUS__DLN0_LP_FIFO_OVERFLOW_CLR__SHIFT 0x16
++#define DSI1_DISP_DSI_STATUS__CMDFIFO_UNDERFLOW__SHIFT 0x17
++#define DSI1_DISP_DSI_STATUS__CMDFIFO_UNDERFLOW_CLR__SHIFT 0x17
++#define DSI1_DISP_DSI_STATUS__INTERLEAVE_PACKET_BLOCK__SHIFT 0x18
++#define DSI1_DISP_DSI_STATUS__INTERLEAVE_PACKET_BLOCK_CLR__SHIFT 0x18
++#define DSI1_DISP_DSI_STATUS__TE_ABORT__SHIFT 0x19
++#define DSI1_DISP_DSI_STATUS__TE_ABORT_CLR__SHIFT 0x19
++#define DSI1_DISP_DSI_STATUS__DMAFIFO_RD_WATERMARK_REACH__SHIFT 0x1c
++#define DSI1_DISP_DSI_STATUS__DMAFIFO_RD_WATERMARK_REACH_CLR__SHIFT 0x1c
++#define DSI1_DISP_DSI_STATUS__DMAFIFO_WR_WATERMARK_REACH__SHIFT 0x1d
++#define DSI1_DISP_DSI_STATUS__DMAFIFO_WR_WATERMARK_REACH_CLR__SHIFT 0x1d
++#define DSI1_DISP_DSI_STATUS__DMAFIFO_UNDERFLOW__SHIFT 0x1e
++#define DSI1_DISP_DSI_STATUS__DMAFIFO_UNDERFLOW_CLR__SHIFT 0x1e
++#define DSI1_DISP_DSI_STATUS__INTERLEAVE_OP_CONTENTION__SHIFT 0x1f
++#define DSI1_DISP_DSI_STATUS__INTERLEAVE_OP_CONTENTION_CLR__SHIFT 0x1f
++#define DSI1_DISP_DSI_STATUS__CMD_MODE_ENGINE_BUSY_MASK 0x00000001L
++#define DSI1_DISP_DSI_STATUS__CMD_MODE_DMA_BUSY_MASK 0x00000002L
++#define DSI1_DISP_DSI_STATUS__CMD_MODE_DENG_BUSY_MASK 0x00000004L
++#define DSI1_DISP_DSI_STATUS__VIDEO_MODE_ENGINE_BUSY_MASK 0x00000008L
++#define DSI1_DISP_DSI_STATUS__BTA_BUSY_MASK 0x00000010L
++#define DSI1_DISP_DSI_STATUS__GENERIC_TRIGGER_BUSY_MASK 0x00000020L
++#define DSI1_DISP_DSI_STATUS__PHY_RESET_BUSY_MASK 0x00000040L
++#define DSI1_DISP_DSI_STATUS__DLN0_HS_FIFO_EMPTY_MASK 0x00000100L
++#define DSI1_DISP_DSI_STATUS__DLN0_HS_FIFO_FULL_MASK 0x00000200L
++#define DSI1_DISP_DSI_STATUS__DLN1_HS_FIFO_EMPTY_MASK 0x00000400L
++#define DSI1_DISP_DSI_STATUS__DLN1_HS_FIFO_FULL_MASK 0x00000800L
++#define DSI1_DISP_DSI_STATUS__DLN2_HS_FIFO_EMPTY_MASK 0x00001000L
++#define DSI1_DISP_DSI_STATUS__DLN2_HS_FIFO_FULL_MASK 0x00002000L
++#define DSI1_DISP_DSI_STATUS__DLN3_HS_FIFO_EMPTY_MASK 0x00004000L
++#define DSI1_DISP_DSI_STATUS__DLN3_HS_FIFO_FULL_MASK 0x00008000L
++#define DSI1_DISP_DSI_STATUS__DLN0_HS_FIFO_OVERFLOW_MASK 0x00010000L
++#define DSI1_DISP_DSI_STATUS__DLN0_HS_FIFO_OVERFLOW_CLR_MASK 0x00010000L
++#define DSI1_DISP_DSI_STATUS__DLN1_HS_FIFO_OVERFLOW_MASK 0x00020000L
++#define DSI1_DISP_DSI_STATUS__DLN1_HS_FIFO_OVERFLOW_CLR_MASK 0x00020000L
++#define DSI1_DISP_DSI_STATUS__DLN2_HS_FIFO_OVERFLOW_MASK 0x00040000L
++#define DSI1_DISP_DSI_STATUS__DLN2_HS_FIFO_OVERFLOW_CLR_MASK 0x00040000L
++#define DSI1_DISP_DSI_STATUS__DLN3_HS_FIFO_OVERFLOW_MASK 0x00080000L
++#define DSI1_DISP_DSI_STATUS__DLN3_HS_FIFO_OVERFLOW_CLR_MASK 0x00080000L
++#define DSI1_DISP_DSI_STATUS__DLN0_LP_FIFO_EMPTY_MASK 0x00100000L
++#define DSI1_DISP_DSI_STATUS__DLN0_LP_FIFO_FULL_MASK 0x00200000L
++#define DSI1_DISP_DSI_STATUS__DLN0_LP_FIFO_OVERFLOW_MASK 0x00400000L
++#define DSI1_DISP_DSI_STATUS__DLN0_LP_FIFO_OVERFLOW_CLR_MASK 0x00400000L
++#define DSI1_DISP_DSI_STATUS__CMDFIFO_UNDERFLOW_MASK 0x00800000L
++#define DSI1_DISP_DSI_STATUS__CMDFIFO_UNDERFLOW_CLR_MASK 0x00800000L
++#define DSI1_DISP_DSI_STATUS__INTERLEAVE_PACKET_BLOCK_MASK 0x01000000L
++#define DSI1_DISP_DSI_STATUS__INTERLEAVE_PACKET_BLOCK_CLR_MASK 0x01000000L
++#define DSI1_DISP_DSI_STATUS__TE_ABORT_MASK 0x02000000L
++#define DSI1_DISP_DSI_STATUS__TE_ABORT_CLR_MASK 0x02000000L
++#define DSI1_DISP_DSI_STATUS__DMAFIFO_RD_WATERMARK_REACH_MASK 0x10000000L
++#define DSI1_DISP_DSI_STATUS__DMAFIFO_RD_WATERMARK_REACH_CLR_MASK 0x10000000L
++#define DSI1_DISP_DSI_STATUS__DMAFIFO_WR_WATERMARK_REACH_MASK 0x20000000L
++#define DSI1_DISP_DSI_STATUS__DMAFIFO_WR_WATERMARK_REACH_CLR_MASK 0x20000000L
++#define DSI1_DISP_DSI_STATUS__DMAFIFO_UNDERFLOW_MASK 0x40000000L
++#define DSI1_DISP_DSI_STATUS__DMAFIFO_UNDERFLOW_CLR_MASK 0x40000000L
++#define DSI1_DISP_DSI_STATUS__INTERLEAVE_OP_CONTENTION_MASK 0x80000000L
++#define DSI1_DISP_DSI_STATUS__INTERLEAVE_OP_CONTENTION_CLR_MASK 0x80000000L
++//DSI1_DISP_DSI_VIDEO_MODE_CTRL
++#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__VC__SHIFT 0x0
++#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__DST_FORMAT__SHIFT 0x4
++#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__TRAFFIC_MODE__SHIFT 0x8
++#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__BLLP_PWR_MODE__SHIFT 0xc
++#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__EOF_BLLP_PWR_MODE__SHIFT 0xf
++#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__HSA_PWR_MODE__SHIFT 0x10
++#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__HBP_PWR_MODE__SHIFT 0x14
++#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__HFP_PWR_MODE__SHIFT 0x18
++#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__PULSE_MODE_OPT__SHIFT 0x1c
++#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__VC_MASK 0x00000003L
++#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__DST_FORMAT_MASK 0x00000030L
++#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__TRAFFIC_MODE_MASK 0x00000300L
++#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__BLLP_PWR_MODE_MASK 0x00001000L
++#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__EOF_BLLP_PWR_MODE_MASK 0x00008000L
++#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__HSA_PWR_MODE_MASK 0x00010000L
++#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__HBP_PWR_MODE_MASK 0x00100000L
++#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__HFP_PWR_MODE_MASK 0x01000000L
++#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__PULSE_MODE_OPT_MASK 0x10000000L
++//DSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE
++#define DSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__VS__SHIFT 0x0
++#define DSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__VE__SHIFT 0x8
++#define DSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__HS__SHIFT 0x10
++#define DSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__HE__SHIFT 0x18
++#define DSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__VS_MASK 0x0000003FL
++#define DSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__VE_MASK 0x00003F00L
++#define DSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__HS_MASK 0x003F0000L
++#define DSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__HE_MASK 0x3F000000L
++//DSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD
++#define DSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD__VS_PAYLOAD__SHIFT 0x0
++#define DSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD__VE_PAYLOAD__SHIFT 0x10
++#define DSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD__VS_PAYLOAD_MASK 0x0000FFFFL
++#define DSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD__VE_PAYLOAD_MASK 0xFFFF0000L
++//DSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD
++#define DSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD__HS_PAYLOAD__SHIFT 0x0
++#define DSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD__HE_PAYLOAD__SHIFT 0x10
++#define DSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD__HS_PAYLOAD_MASK 0x0000FFFFL
++#define DSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD__HE_PAYLOAD_MASK 0xFFFF0000L
++//DSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE
++#define DSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB565__SHIFT 0x0
++#define DSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB666_PACKED__SHIFT 0x8
++#define DSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB666__SHIFT 0x10
++#define DSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB888__SHIFT 0x18
++#define DSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB565_MASK 0x0000003FL
++#define DSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB666_PACKED_MASK 0x00003F00L
++#define DSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB666_MASK 0x003F0000L
++#define DSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB888_MASK 0x3F000000L
++//DSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE
++#define DSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE__BLANK_PKT_DATA__SHIFT 0x0
++#define DSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE__BLANK_PKT_DATATYPE__SHIFT 0x8
++#define DSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE__BLANK_PKT_DATA_MASK 0x000000FFL
++#define DSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE__BLANK_PKT_DATATYPE_MASK 0x00003F00L
++//DSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL
++#define DSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL__R_SEL__SHIFT 0x0
++#define DSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL__G_SEL__SHIFT 0x4
++#define DSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL__B_SEL__SHIFT 0x8
++#define DSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL__RGB_SWAP__SHIFT 0xc
++#define DSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL__R_SEL_MASK 0x00000001L
++#define DSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL__G_SEL_MASK 0x00000010L
++#define DSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL__B_SEL_MASK 0x00000100L
++#define DSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL__RGB_SWAP_MASK 0x00007000L
++//DSI1_DISP_DSI_COMMAND_MODE_CTRL
++#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__WC__SHIFT 0x0
++#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__DT__SHIFT 0x10
++#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__VC__SHIFT 0x16
++#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__PACKET_TYPE__SHIFT 0x18
++#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__POWER_MODE__SHIFT 0x1a
++#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__EMBEDDED_MODE__SHIFT 0x1c
++#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__CMD_DATA_ORDER__SHIFT 0x1f
++#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__WC_MASK 0x0000FFFFL
++#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__DT_MASK 0x003F0000L
++#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__VC_MASK 0x00C00000L
++#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__PACKET_TYPE_MASK 0x01000000L
++#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__POWER_MODE_MASK 0x04000000L
++#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__EMBEDDED_MODE_MASK 0x10000000L
++#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__CMD_DATA_ORDER_MASK 0x80000000L
++//DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL
++#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__SRC_FORMAT__SHIFT 0x0
++#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__DST_FORMAT__SHIFT 0x4
++#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__DATA_BUFFER_ID__SHIFT 0x8
++#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__SHADOW_DATA_BUFFER_ID__SHIFT 0xc
++#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__R_SEL__SHIFT 0x10
++#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__G_SEL__SHIFT 0x11
++#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__B_SEL__SHIFT 0x12
++#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__RGB_SWAP__SHIFT 0x14
++#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__DWORD_BYTE_SWAP__SHIFT 0x18
++#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__SRC_FORMAT_MASK 0x0000000FL
++#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__DST_FORMAT_MASK 0x000000F0L
++#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__DATA_BUFFER_ID_MASK 0x00000100L
++#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__SHADOW_DATA_BUFFER_ID_MASK 0x00001000L
++#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__R_SEL_MASK 0x00010000L
++#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__G_SEL_MASK 0x00020000L
++#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__B_SEL_MASK 0x00040000L
++#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__RGB_SWAP_MASK 0x00700000L
++#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__DWORD_BYTE_SWAP_MASK 0x03000000L
++//DSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL
++#define DSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__WR_MEM_START__SHIFT 0x0
++#define DSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__WR_MEM_CONTINUE__SHIFT 0x8
++#define DSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__INSERT_DCS_COMMAND__SHIFT 0x10
++#define DSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__WR_MEM_START_MASK 0x000000FFL
++#define DSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__WR_MEM_CONTINUE_MASK 0x0000FF00L
++#define DSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__INSERT_DCS_COMMAND_MASK 0x00010000L
++//DSI1_DISP_DSI_DMA_CMD_OFFSET
++#define DSI1_DISP_DSI_DMA_CMD_OFFSET__CMD_OFFSET__SHIFT 0x0
++#define DSI1_DISP_DSI_DMA_CMD_OFFSET__CMD_OFFSET_MASK 0xFFFFFFFFL
++//DSI1_DISP_DSI_DMA_CMD_LENGTH
++#define DSI1_DISP_DSI_DMA_CMD_LENGTH__CMD_LENGTH__SHIFT 0x0
++#define DSI1_DISP_DSI_DMA_CMD_LENGTH__CMD_LENGTH_MASK 0x00FFFFFFL
++//DSI1_DISP_DSI_DMA_DATA_OFFSET_0
++#define DSI1_DISP_DSI_DMA_DATA_OFFSET_0__DATA_SRC_OFFSET0__SHIFT 0x0
++#define DSI1_DISP_DSI_DMA_DATA_OFFSET_0__DATA_SRC_OFFSET0_MASK 0xFFFFFFFFL
++//DSI1_DISP_DSI_DMA_DATA_OFFSET_1
++#define DSI1_DISP_DSI_DMA_DATA_OFFSET_1__DATA_SRC_OFFSET1__SHIFT 0x0
++#define DSI1_DISP_DSI_DMA_DATA_OFFSET_1__DATA_SRC_OFFSET1_MASK 0xFFFFFFFFL
++//DSI1_DISP_DSI_DMA_DATA_PITCH
++#define DSI1_DISP_DSI_DMA_DATA_PITCH__DATA_SRC_PITCH__SHIFT 0x0
++#define DSI1_DISP_DSI_DMA_DATA_PITCH__DATA_SRC_PITCH_MASK 0x00007FFFL
++//DSI1_DISP_DSI_DMA_DATA_WIDTH
++#define DSI1_DISP_DSI_DMA_DATA_WIDTH__DATA_SRC_WIDTH__SHIFT 0x0
++#define DSI1_DISP_DSI_DMA_DATA_WIDTH__DATA_SRC_WIDTH_ALIGN__SHIFT 0x18
++#define DSI1_DISP_DSI_DMA_DATA_WIDTH__DATA_SRC_WIDTH_MASK 0x000FFFFFL
++#define DSI1_DISP_DSI_DMA_DATA_WIDTH__DATA_SRC_WIDTH_ALIGN_MASK 0x07000000L
++//DSI1_DISP_DSI_DMA_DATA_HEIGHT
++#define DSI1_DISP_DSI_DMA_DATA_HEIGHT__DATA_SRC_HEIGHT__SHIFT 0x0
++#define DSI1_DISP_DSI_DMA_DATA_HEIGHT__DATA_SRC_HEIGHT_MASK 0x00000FFFL
++//DSI1_DISP_DSI_DMA_FIFO_CTRL
++#define DSI1_DISP_DSI_DMA_FIFO_CTRL__WRITE_WATERMARK__SHIFT 0x0
++#define DSI1_DISP_DSI_DMA_FIFO_CTRL__READ_WATERMARK__SHIFT 0x4
++#define DSI1_DISP_DSI_DMA_FIFO_CTRL__WRITE_WATERMARK_MASK 0x00000003L
++#define DSI1_DISP_DSI_DMA_FIFO_CTRL__READ_WATERMARK_MASK 0x00000030L
++//DSI1_DISP_DSI_DMA_NULL_PACKET_DATA
++#define DSI1_DISP_DSI_DMA_NULL_PACKET_DATA__NULL_DATA__SHIFT 0x0
++#define DSI1_DISP_DSI_DMA_NULL_PACKET_DATA__NULL_DATATYPE__SHIFT 0x8
++#define DSI1_DISP_DSI_DMA_NULL_PACKET_DATA__NULL_DATA_MASK 0x000000FFL
++#define DSI1_DISP_DSI_DMA_NULL_PACKET_DATA__NULL_DATATYPE_MASK 0x00003F00L
++//DSI1_DISP_DSI_DENG_DATA_LENGTH
++#define DSI1_DISP_DSI_DENG_DATA_LENGTH__DENG_LENGTH__SHIFT 0x0
++#define DSI1_DISP_DSI_DENG_DATA_LENGTH__USE_DENG_LENGTH__SHIFT 0x1f
++#define DSI1_DISP_DSI_DENG_DATA_LENGTH__DENG_LENGTH_MASK 0x00FFFFFFL
++#define DSI1_DISP_DSI_DENG_DATA_LENGTH__USE_DENG_LENGTH_MASK 0x80000000L
++//DSI1_DISP_DSI_ACK_ERROR_REPORT
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__SOT_ERR__SHIFT 0x0
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__SOT_ERR_CLR__SHIFT 0x0
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__SOT_SYNC_ERR__SHIFT 0x1
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__SOT_SYNC_ERR_CLR__SHIFT 0x1
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__EOT_ERR__SHIFT 0x2
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__EOT_ERR_CLR__SHIFT 0x2
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ESC_ERR__SHIFT 0x3
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ESC_ERR_CLR__SHIFT 0x3
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__LP_ERR__SHIFT 0x4
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__LP_ERR_CLR__SHIFT 0x4
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__HRX_TO__SHIFT 0x5
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__HRX_TO_CLR__SHIFT 0x5
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__FALSE_CTRL_ERR__SHIFT 0x6
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__FALSE_CTRL_ERR_CLR__SHIFT 0x6
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__CONTENTION_ERR__SHIFT 0x7
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__CONTENTION_ERR_CLR__SHIFT 0x7
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ECC_ERR__SHIFT 0x8
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ECC_ERR_CLR__SHIFT 0x8
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__MULTI_ECC_ERR__SHIFT 0x9
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__MULTI_ECC_ERR_CLR__SHIFT 0x9
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__CRC_ERR__SHIFT 0xa
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__CRC_ERR_CLR__SHIFT 0xa
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__DT_ERR__SHIFT 0xb
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__DT_ERR_CLR__SHIFT 0xb
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__VC_ERR__SHIFT 0xc
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__VC_ERR_CLR__SHIFT 0xc
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__PROTOCOL_VIOLATION__SHIFT 0xd
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__PROTOCOL_VIOLATION_CLR__SHIFT 0xd
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__PANEL_SPECIFIC_ERR__SHIFT 0xf
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__PANEL_SPECIFIC_ERR_CLR__SHIFT 0xf
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_ECC_ERR__SHIFT 0x10
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_ECC_ERR_CLR__SHIFT 0x10
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_MULTI_ECC_ERR__SHIFT 0x11
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_MULTI_ECC_ERR_CLR__SHIFT 0x11
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_CRC_ERR__SHIFT 0x14
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_CRC_ERR_CLR__SHIFT 0x14
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_INCOMPLETE_PACKET_ERR__SHIFT 0x17
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_INCOMPLETE_PACKET_ERR_CLR__SHIFT 0x17
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ERROR__SHIFT 0x18
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ERROR_CLR__SHIFT 0x18
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ACK__SHIFT 0x1c
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ACK_CLR__SHIFT 0x1c
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__SOT_ERR_MASK 0x00000001L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__SOT_ERR_CLR_MASK 0x00000001L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__SOT_SYNC_ERR_MASK 0x00000002L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__SOT_SYNC_ERR_CLR_MASK 0x00000002L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__EOT_ERR_MASK 0x00000004L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__EOT_ERR_CLR_MASK 0x00000004L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ESC_ERR_MASK 0x00000008L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ESC_ERR_CLR_MASK 0x00000008L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__LP_ERR_MASK 0x00000010L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__LP_ERR_CLR_MASK 0x00000010L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__HRX_TO_MASK 0x00000020L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__HRX_TO_CLR_MASK 0x00000020L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__FALSE_CTRL_ERR_MASK 0x00000040L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__FALSE_CTRL_ERR_CLR_MASK 0x00000040L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__CONTENTION_ERR_MASK 0x00000080L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__CONTENTION_ERR_CLR_MASK 0x00000080L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ECC_ERR_MASK 0x00000100L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ECC_ERR_CLR_MASK 0x00000100L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__MULTI_ECC_ERR_MASK 0x00000200L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__MULTI_ECC_ERR_CLR_MASK 0x00000200L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__CRC_ERR_MASK 0x00000400L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__CRC_ERR_CLR_MASK 0x00000400L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__DT_ERR_MASK 0x00000800L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__DT_ERR_CLR_MASK 0x00000800L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__VC_ERR_MASK 0x00001000L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__VC_ERR_CLR_MASK 0x00001000L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__PROTOCOL_VIOLATION_MASK 0x00002000L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__PROTOCOL_VIOLATION_CLR_MASK 0x00002000L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__PANEL_SPECIFIC_ERR_MASK 0x00008000L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__PANEL_SPECIFIC_ERR_CLR_MASK 0x00008000L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_ECC_ERR_MASK 0x00010000L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_ECC_ERR_CLR_MASK 0x00010000L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_MULTI_ECC_ERR_MASK 0x00020000L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_MULTI_ECC_ERR_CLR_MASK 0x00020000L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_CRC_ERR_MASK 0x00100000L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_CRC_ERR_CLR_MASK 0x00100000L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_INCOMPLETE_PACKET_ERR_MASK 0x00800000L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_INCOMPLETE_PACKET_ERR_CLR_MASK 0x00800000L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ERROR_MASK 0x01000000L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ERROR_CLR_MASK 0x01000000L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ACK_MASK 0x10000000L
++#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ACK_CLR_MASK 0x10000000L
++//DSI1_DISP_DSI_RDBK_DATA0
++#define DSI1_DISP_DSI_RDBK_DATA0__RD_DATA0__SHIFT 0x0
++#define DSI1_DISP_DSI_RDBK_DATA0__RD_DATA0_MASK 0xFFFFFFFFL
++//DSI1_DISP_DSI_RDBK_DATA1
++#define DSI1_DISP_DSI_RDBK_DATA1__RD_DATA1__SHIFT 0x0
++#define DSI1_DISP_DSI_RDBK_DATA1__RD_DATA1_MASK 0xFFFFFFFFL
++//DSI1_DISP_DSI_RDBK_DATA2
++#define DSI1_DISP_DSI_RDBK_DATA2__RD_DATA2__SHIFT 0x0
++#define DSI1_DISP_DSI_RDBK_DATA2__RD_DATA2_MASK 0xFFFFFFFFL
++//DSI1_DISP_DSI_RDBK_DATA3
++#define DSI1_DISP_DSI_RDBK_DATA3__RD_DATA3__SHIFT 0x0
++#define DSI1_DISP_DSI_RDBK_DATA3__RD_DATA3_MASK 0xFFFFFFFFL
++//DSI1_DISP_DSI_RDBK_DATATYPE0
++#define DSI1_DISP_DSI_RDBK_DATATYPE0__GENERIC_SHORT_RD_1_BYTE__SHIFT 0x0
++#define DSI1_DISP_DSI_RDBK_DATATYPE0__GENERIC_SHORT_RD_2_BYTE__SHIFT 0x8
++#define DSI1_DISP_DSI_RDBK_DATATYPE0__DCS_SHORT_RD_1_BYTE__SHIFT 0x10
++#define DSI1_DISP_DSI_RDBK_DATATYPE0__DCS_SHORT_RD_2_BYTE__SHIFT 0x18
++#define DSI1_DISP_DSI_RDBK_DATATYPE0__GENERIC_SHORT_RD_1_BYTE_MASK 0x0000003FL
++#define DSI1_DISP_DSI_RDBK_DATATYPE0__GENERIC_SHORT_RD_2_BYTE_MASK 0x00003F00L
++#define DSI1_DISP_DSI_RDBK_DATATYPE0__DCS_SHORT_RD_1_BYTE_MASK 0x003F0000L
++#define DSI1_DISP_DSI_RDBK_DATATYPE0__DCS_SHORT_RD_2_BYTE_MASK 0x3F000000L
++//DSI1_DISP_DSI_RDBK_DATATYPE1
++#define DSI1_DISP_DSI_RDBK_DATATYPE1__ERROR_REPORT__SHIFT 0x0
++#define DSI1_DISP_DSI_RDBK_DATATYPE1__GENERIC_LONG_RD__SHIFT 0x8
++#define DSI1_DISP_DSI_RDBK_DATATYPE1__DCS_LONG_RD__SHIFT 0x10
++#define DSI1_DISP_DSI_RDBK_DATATYPE1__ERROR_REPORT_MASK 0x0000003FL
++#define DSI1_DISP_DSI_RDBK_DATATYPE1__GENERIC_LONG_RD_MASK 0x00003F00L
++#define DSI1_DISP_DSI_RDBK_DATATYPE1__DCS_LONG_RD_MASK 0x003F0000L
++//DSI1_DISP_DSI_TRIG_CTRL
++#define DSI1_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_TRIGGER_MODE__SHIFT 0x0
++#define DSI1_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_TRIGGER_SEL__SHIFT 0x4
++#define DSI1_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DENG_TRIGGER_MODE__SHIFT 0x10
++#define DSI1_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DENG_TRIGGER_SEL__SHIFT 0x14
++#define DSI1_DISP_DSI_TRIG_CTRL__HW_SOURCE_SEL__SHIFT 0x18
++#define DSI1_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_DENG_ORDER__SHIFT 0x1c
++#define DSI1_DISP_DSI_TRIG_CTRL__TE_SEL__SHIFT 0x1f
++#define DSI1_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_TRIGGER_MODE_MASK 0x00000001L
++#define DSI1_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_TRIGGER_SEL_MASK 0x00000030L
++#define DSI1_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DENG_TRIGGER_MODE_MASK 0x00010000L
++#define DSI1_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DENG_TRIGGER_SEL_MASK 0x00300000L
++#define DSI1_DISP_DSI_TRIG_CTRL__HW_SOURCE_SEL_MASK 0x0F000000L
++#define DSI1_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_DENG_ORDER_MASK 0x10000000L
++#define DSI1_DISP_DSI_TRIG_CTRL__TE_SEL_MASK 0x80000000L
++//DSI1_DISP_DSI_EXT_MUX
++#define DSI1_DISP_DSI_EXT_MUX__EXT_TE_MUX__SHIFT 0x0
++#define DSI1_DISP_DSI_EXT_MUX__EXT_TE_MODE__SHIFT 0x4
++#define DSI1_DISP_DSI_EXT_MUX__EXT_RESET_POL__SHIFT 0x6
++#define DSI1_DISP_DSI_EXT_MUX__EXT_TE_POL__SHIFT 0x7
++#define DSI1_DISP_DSI_EXT_MUX__EXT_TE_HSYNC_TRIG_CNT__SHIFT 0x8
++#define DSI1_DISP_DSI_EXT_MUX__EXT_TE_HSYNC_TOTAL__SHIFT 0x14
++#define DSI1_DISP_DSI_EXT_MUX__EXT_TE_MUX_MASK 0x0000000FL
++#define DSI1_DISP_DSI_EXT_MUX__EXT_TE_MODE_MASK 0x00000030L
++#define DSI1_DISP_DSI_EXT_MUX__EXT_RESET_POL_MASK 0x00000040L
++#define DSI1_DISP_DSI_EXT_MUX__EXT_TE_POL_MASK 0x00000080L
++#define DSI1_DISP_DSI_EXT_MUX__EXT_TE_HSYNC_TRIG_CNT_MASK 0x000FFF00L
++#define DSI1_DISP_DSI_EXT_MUX__EXT_TE_HSYNC_TOTAL_MASK 0xFFF00000L
++//DSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL
++#define DSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL__TE_HSYNC_MAX_WIDTH__SHIFT 0x0
++#define DSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL__TE_VSYNC_MIN_WIDTH__SHIFT 0x10
++#define DSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL__TE_HSYNC_MAX_WIDTH_MASK 0x0000FFFFL
++#define DSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL__TE_VSYNC_MIN_WIDTH_MASK 0xFFFF0000L
++//DSI1_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER
++#define DSI1_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER__SW_TRIGGER__SHIFT 0x0
++#define DSI1_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER__SW_TRIGGER_MASK 0x00000001L
++//DSI1_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER
++#define DSI1_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER__SW_TRIGGER__SHIFT 0x0
++#define DSI1_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER__SW_TRIGGER_MASK 0x00000001L
++//DSI1_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER
++#define DSI1_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER__SW_TRIGGER__SHIFT 0x0
++#define DSI1_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER__SW_TRIGGER_MASK 0x00000001L
++//DSI1_DISP_DSI_RESET_SW_TRIGGER
++#define DSI1_DISP_DSI_RESET_SW_TRIGGER__SW_TRIGGER__SHIFT 0x0
++#define DSI1_DISP_DSI_RESET_SW_TRIGGER__SW_TRIGGER_MASK 0x00000001L
++//DSI1_DISP_DSI_EXT_RESET
++#define DSI1_DISP_DSI_EXT_RESET__RESET_PANEL__SHIFT 0x0
++#define DSI1_DISP_DSI_EXT_RESET__RESET_PANEL_MASK 0x00000001L
++//DSI1_DISP_DSI_LANE_CRC_HS_MODE
++#define DSI1_DISP_DSI_LANE_CRC_HS_MODE__DLN0_HS_CRC__SHIFT 0x0
++#define DSI1_DISP_DSI_LANE_CRC_HS_MODE__DLN1_HS_CRC__SHIFT 0x8
++#define DSI1_DISP_DSI_LANE_CRC_HS_MODE__DLN2_HS_CRC__SHIFT 0x10
++#define DSI1_DISP_DSI_LANE_CRC_HS_MODE__DLN3_HS_CRC__SHIFT 0x18
++#define DSI1_DISP_DSI_LANE_CRC_HS_MODE__DLN0_HS_CRC_MASK 0x000000FFL
++#define DSI1_DISP_DSI_LANE_CRC_HS_MODE__DLN1_HS_CRC_MASK 0x0000FF00L
++#define DSI1_DISP_DSI_LANE_CRC_HS_MODE__DLN2_HS_CRC_MASK 0x00FF0000L
++#define DSI1_DISP_DSI_LANE_CRC_HS_MODE__DLN3_HS_CRC_MASK 0xFF000000L
++//DSI1_DISP_DSI_LANE_CRC_LP_MODE
++#define DSI1_DISP_DSI_LANE_CRC_LP_MODE__DLN0_LP_CRC__SHIFT 0x0
++#define DSI1_DISP_DSI_LANE_CRC_LP_MODE__DLN0_LP_CRC_MASK 0x000000FFL
++//DSI1_DISP_DSI_LANE_CRC_CTRL
++#define DSI1_DISP_DSI_LANE_CRC_CTRL__CRC_MAX_HS_DONE_COUNT__SHIFT 0x0
++#define DSI1_DISP_DSI_LANE_CRC_CTRL__CRC_MAX_LP_DONE_COUNT__SHIFT 0x8
++#define DSI1_DISP_DSI_LANE_CRC_CTRL__CRC_ENABLE__SHIFT 0x10
++#define DSI1_DISP_DSI_LANE_CRC_CTRL__CRC_DONE_HS__SHIFT 0x14
++#define DSI1_DISP_DSI_LANE_CRC_CTRL__CRC_DONE_LP__SHIFT 0x18
++#define DSI1_DISP_DSI_LANE_CRC_CTRL__CRC_MAX_HS_DONE_COUNT_MASK 0x000000FFL
++#define DSI1_DISP_DSI_LANE_CRC_CTRL__CRC_MAX_LP_DONE_COUNT_MASK 0x0000FF00L
++#define DSI1_DISP_DSI_LANE_CRC_CTRL__CRC_ENABLE_MASK 0x00010000L
++#define DSI1_DISP_DSI_LANE_CRC_CTRL__CRC_DONE_HS_MASK 0x00100000L
++#define DSI1_DISP_DSI_LANE_CRC_CTRL__CRC_DONE_LP_MASK 0x01000000L
++//DSI1_DISP_DSI_PIXEL_CRC_CTRL
++#define DSI1_DISP_DSI_PIXEL_CRC_CTRL__CRC_MAX_PIXEL_COUNT__SHIFT 0x0
++#define DSI1_DISP_DSI_PIXEL_CRC_CTRL__PIXEL_CRC__SHIFT 0x8
++#define DSI1_DISP_DSI_PIXEL_CRC_CTRL__CRC_DONE_PIXEL__SHIFT 0x10
++#define DSI1_DISP_DSI_PIXEL_CRC_CTRL__CRC_MAX_PIXEL_COUNT_MASK 0x000000FFL
++#define DSI1_DISP_DSI_PIXEL_CRC_CTRL__PIXEL_CRC_MASK 0x0000FF00L
++#define DSI1_DISP_DSI_PIXEL_CRC_CTRL__CRC_DONE_PIXEL_MASK 0x00010000L
++//DSI1_DISP_DSI_LANE_CTRL
++#define DSI1_DISP_DSI_LANE_CTRL__DLN0_ULPS_REQUEST__SHIFT 0x0
++#define DSI1_DISP_DSI_LANE_CTRL__DLN1_ULPS_REQUEST__SHIFT 0x1
++#define DSI1_DISP_DSI_LANE_CTRL__DLN2_ULPS_REQUEST__SHIFT 0x2
++#define DSI1_DISP_DSI_LANE_CTRL__DLN3_ULPS_REQUEST__SHIFT 0x3
++#define DSI1_DISP_DSI_LANE_CTRL__DLN0_ULPS_EXIT__SHIFT 0x4
++#define DSI1_DISP_DSI_LANE_CTRL__DLN1_ULPS_EXIT__SHIFT 0x5
++#define DSI1_DISP_DSI_LANE_CTRL__DLN2_ULPS_EXIT__SHIFT 0x6
++#define DSI1_DISP_DSI_LANE_CTRL__DLN3_ULPS_EXIT__SHIFT 0x7
++#define DSI1_DISP_DSI_LANE_CTRL__DLN0_FORCE_TX_STOP__SHIFT 0x8
++#define DSI1_DISP_DSI_LANE_CTRL__DLN1_FORCE_TX_STOP__SHIFT 0x9
++#define DSI1_DISP_DSI_LANE_CTRL__DLN2_FORCE_TX_STOP__SHIFT 0xa
++#define DSI1_DISP_DSI_LANE_CTRL__DLN3_FORCE_TX_STOP__SHIFT 0xb
++#define DSI1_DISP_DSI_LANE_CTRL__CLKLN_ULPS_REQUEST__SHIFT 0xc
++#define DSI1_DISP_DSI_LANE_CTRL__CLKLN_ULPS_EXIT__SHIFT 0x10
++#define DSI1_DISP_DSI_LANE_CTRL__CLKLN_FORCE_TX_STOP__SHIFT 0x14
++#define DSI1_DISP_DSI_LANE_CTRL__CLKLN_HS_FORCE_REQUEST__SHIFT 0x18
++#define DSI1_DISP_DSI_LANE_CTRL__DLN0_ULPS_REQUEST_MASK 0x00000001L
++#define DSI1_DISP_DSI_LANE_CTRL__DLN1_ULPS_REQUEST_MASK 0x00000002L
++#define DSI1_DISP_DSI_LANE_CTRL__DLN2_ULPS_REQUEST_MASK 0x00000004L
++#define DSI1_DISP_DSI_LANE_CTRL__DLN3_ULPS_REQUEST_MASK 0x00000008L
++#define DSI1_DISP_DSI_LANE_CTRL__DLN0_ULPS_EXIT_MASK 0x00000010L
++#define DSI1_DISP_DSI_LANE_CTRL__DLN1_ULPS_EXIT_MASK 0x00000020L
++#define DSI1_DISP_DSI_LANE_CTRL__DLN2_ULPS_EXIT_MASK 0x00000040L
++#define DSI1_DISP_DSI_LANE_CTRL__DLN3_ULPS_EXIT_MASK 0x00000080L
++#define DSI1_DISP_DSI_LANE_CTRL__DLN0_FORCE_TX_STOP_MASK 0x00000100L
++#define DSI1_DISP_DSI_LANE_CTRL__DLN1_FORCE_TX_STOP_MASK 0x00000200L
++#define DSI1_DISP_DSI_LANE_CTRL__DLN2_FORCE_TX_STOP_MASK 0x00000400L
++#define DSI1_DISP_DSI_LANE_CTRL__DLN3_FORCE_TX_STOP_MASK 0x00000800L
++#define DSI1_DISP_DSI_LANE_CTRL__CLKLN_ULPS_REQUEST_MASK 0x00001000L
++#define DSI1_DISP_DSI_LANE_CTRL__CLKLN_ULPS_EXIT_MASK 0x00010000L
++#define DSI1_DISP_DSI_LANE_CTRL__CLKLN_FORCE_TX_STOP_MASK 0x00100000L
++#define DSI1_DISP_DSI_LANE_CTRL__CLKLN_HS_FORCE_REQUEST_MASK 0x01000000L
++//DSI1_DISP_DSI_DLN0_PHY_ERROR
++#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC__SHIFT 0x0
++#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC_CLR__SHIFT 0x0
++#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC_MASK__SHIFT 0x3
++#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC__SHIFT 0x4
++#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC_CLR__SHIFT 0x4
++#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC_MASK__SHIFT 0x7
++#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL__SHIFT 0x8
++#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL_CLR__SHIFT 0x8
++#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL_MASK__SHIFT 0xb
++#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0__SHIFT 0xc
++#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0_CLR__SHIFT 0xc
++#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0_MASK__SHIFT 0xf
++#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1__SHIFT 0x10
++#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1_CLR__SHIFT 0x10
++#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1_MASK__SHIFT 0x13
++#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC_MASK 0x00000001L
++#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC_CLR_MASK 0x00000001L
++#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC_MASK_MASK 0x00000008L
++#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC_MASK 0x00000010L
++#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC_CLR_MASK 0x00000010L
++#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC_MASK_MASK 0x00000080L
++#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL_MASK 0x00000100L
++#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL_CLR_MASK 0x00000100L
++#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL_MASK_MASK 0x00000800L
++#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0_MASK 0x00001000L
++#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0_CLR_MASK 0x00001000L
++#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0_MASK_MASK 0x00008000L
++#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1_MASK 0x00010000L
++#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1_CLR_MASK 0x00010000L
++#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1_MASK_MASK 0x00080000L
++//DSI1_DISP_DSI_LP_TIMER_CTRL
++#define DSI1_DISP_DSI_LP_TIMER_CTRL__LP_RX_TO__SHIFT 0x0
++#define DSI1_DISP_DSI_LP_TIMER_CTRL__BTA_TO__SHIFT 0x10
++#define DSI1_DISP_DSI_LP_TIMER_CTRL__LP_RX_TO_MASK 0x0000FFFFL
++#define DSI1_DISP_DSI_LP_TIMER_CTRL__BTA_TO_MASK 0xFFFF0000L
++//DSI1_DISP_DSI_HS_TIMER_CTRL
++#define DSI1_DISP_DSI_HS_TIMER_CTRL__HS_TX_TO__SHIFT 0x0
++#define DSI1_DISP_DSI_HS_TIMER_CTRL__HS_TX_TO_MASK 0x0000FFFFL
++//DSI1_DISP_DSI_TIMEOUT_STATUS
++#define DSI1_DISP_DSI_TIMEOUT_STATUS__HS_TX_TIMEOUT__SHIFT 0x0
++#define DSI1_DISP_DSI_TIMEOUT_STATUS__HS_TX_TIMEOUT_CLR__SHIFT 0x0
++#define DSI1_DISP_DSI_TIMEOUT_STATUS__LP_RX_TIMEOUT__SHIFT 0x4
++#define DSI1_DISP_DSI_TIMEOUT_STATUS__LP_RX_TIMEOUT_CLR__SHIFT 0x4
++#define DSI1_DISP_DSI_TIMEOUT_STATUS__BTA_TIMEOUT__SHIFT 0x8
++#define DSI1_DISP_DSI_TIMEOUT_STATUS__BTA_TIMEOUT_CLR__SHIFT 0x8
++#define DSI1_DISP_DSI_TIMEOUT_STATUS__HS_TX_TIMEOUT_MASK 0x00000001L
++#define DSI1_DISP_DSI_TIMEOUT_STATUS__HS_TX_TIMEOUT_CLR_MASK 0x00000001L
++#define DSI1_DISP_DSI_TIMEOUT_STATUS__LP_RX_TIMEOUT_MASK 0x00000010L
++#define DSI1_DISP_DSI_TIMEOUT_STATUS__LP_RX_TIMEOUT_CLR_MASK 0x00000010L
++#define DSI1_DISP_DSI_TIMEOUT_STATUS__BTA_TIMEOUT_MASK 0x00000100L
++#define DSI1_DISP_DSI_TIMEOUT_STATUS__BTA_TIMEOUT_CLR_MASK 0x00000100L
++//DSI1_DISP_DSI_PHY_CLK_TIMING_CTRL
++#define DSI1_DISP_DSI_PHY_CLK_TIMING_CTRL__T_CLK_PRE__SHIFT 0x0
++#define DSI1_DISP_DSI_PHY_CLK_TIMING_CTRL__T_CLK_POST__SHIFT 0x8
++#define DSI1_DISP_DSI_PHY_CLK_TIMING_CTRL__T_CLK_PRE_MASK 0x000000FFL
++#define DSI1_DISP_DSI_PHY_CLK_TIMING_CTRL__T_CLK_POST_MASK 0x00003F00L
++//DSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2
++#define DSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2__T_PRE_TRIGGER__SHIFT 0x0
++#define DSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2__T_INTER_STOP__SHIFT 0x10
++#define DSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2__T_PRE_TRIGGER_MASK 0x000007FFL
++#define DSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2__T_INTER_STOP_MASK 0xFFFF0000L
++//DSI1_DISP_DSI_EOT_PACKET
++#define DSI1_DISP_DSI_EOT_PACKET__DI__SHIFT 0x0
++#define DSI1_DISP_DSI_EOT_PACKET__WC__SHIFT 0x8
++#define DSI1_DISP_DSI_EOT_PACKET__ECC__SHIFT 0x18
++#define DSI1_DISP_DSI_EOT_PACKET__DI_MASK 0x000000FFL
++#define DSI1_DISP_DSI_EOT_PACKET__WC_MASK 0x00FFFF00L
++#define DSI1_DISP_DSI_EOT_PACKET__ECC_MASK 0xFF000000L
++//DSI1_DISP_DSI_EOT_PACKET_CTRL
++#define DSI1_DISP_DSI_EOT_PACKET_CTRL__TX_EOT_APPEND__SHIFT 0x0
++#define DSI1_DISP_DSI_EOT_PACKET_CTRL__RX_EOT_IGNORE__SHIFT 0x4
++#define DSI1_DISP_DSI_EOT_PACKET_CTRL__TX_EOT_APPEND_MASK 0x00000001L
++#define DSI1_DISP_DSI_EOT_PACKET_CTRL__RX_EOT_IGNORE_MASK 0x00000010L
++//DSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER
++#define DSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER__SW_TRIGGER__SHIFT 0x0
++#define DSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER__ENTRY_COMMAND__SHIFT 0x10
++#define DSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER__SW_TRIGGER_MASK 0x00000001L
++#define DSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER__ENTRY_COMMAND_MASK 0x00FF0000L
++//DSI1_DISP_DSI_MIPI_BIST_CTRL
++#define DSI1_DISP_DSI_MIPI_BIST_CTRL__MIPI_BIST_RESET__SHIFT 0x0
++#define DSI1_DISP_DSI_MIPI_BIST_CTRL__MIPI_BIST_EN__SHIFT 0x1
++#define DSI1_DISP_DSI_MIPI_BIST_CTRL__MIPI_BIST_RESET_MASK 0x00000001L
++#define DSI1_DISP_DSI_MIPI_BIST_CTRL__MIPI_BIST_EN_MASK 0x00000002L
++//DSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE
++#define DSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE__MIPI_H_SIZE__SHIFT 0x0
++#define DSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE__MIPI_V_SIZE__SHIFT 0x10
++#define DSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE__MIPI_H_SIZE_MASK 0x0000FFFFL
++#define DSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE__MIPI_V_SIZE_MASK 0xFFFF0000L
++//DSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE
++#define DSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE__MIPI_H_SIZE__SHIFT 0x0
++#define DSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE__MIPI_V_SIZE__SHIFT 0x8
++#define DSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE__MIPI_H_SIZE_MASK 0x000000FFL
++#define DSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE__MIPI_V_SIZE_MASK 0x0000FF00L
++//DSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG
++#define DSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_BLANKING_CYCLES__SHIFT 0x0
++#define DSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_FRAME_REPEAT__SHIFT 0x10
++#define DSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_BIST_VIDEO_FRMT__SHIFT 0x18
++#define DSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_BLANKING_CYCLES_MASK 0x0000FFFFL
++#define DSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_FRAME_REPEAT_MASK 0x00FF0000L
++#define DSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_BIST_VIDEO_FRMT_MASK 0x01000000L
++//DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL
++#define DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_Y_LSFR_POLYNOMIAL__SHIFT 0x0
++#define DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_U_LSFR_POLYNOMIAL__SHIFT 0x8
++#define DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_V_LSFR_POLYNOMIAL__SHIFT 0x10
++#define DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_Y_LSFR_EN__SHIFT 0x18
++#define DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_U_LSFR_EN__SHIFT 0x19
++#define DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_V_LSFR_EN__SHIFT 0x1a
++#define DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_Y_LSFR_POLYNOMIAL_MASK 0x000000FFL
++#define DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_U_LSFR_POLYNOMIAL_MASK 0x0000FF00L
++#define DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_V_LSFR_POLYNOMIAL_MASK 0x00FF0000L
++#define DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_Y_LSFR_EN_MASK 0x01000000L
++#define DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_U_LSFR_EN_MASK 0x02000000L
++#define DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_V_LSFR_EN_MASK 0x04000000L
++//DSI1_DISP_DSI_MIPI_BIST_LSFR_INIT
++#define DSI1_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_Y_INIT_LSFR_VAL__SHIFT 0x0
++#define DSI1_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_U_INIT_LSFR_VAL__SHIFT 0x8
++#define DSI1_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_V_INIT_LSFR_VAL__SHIFT 0x10
++#define DSI1_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_Y_INIT_LSFR_VAL_MASK 0x000000FFL
++#define DSI1_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_U_INIT_LSFR_VAL_MASK 0x0000FF00L
++#define DSI1_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_V_INIT_LSFR_VAL_MASK 0x00FF0000L
++//DSI1_DISP_DSI_MIPI_BIST_START
++#define DSI1_DISP_DSI_MIPI_BIST_START__MIPI_BIST_START__SHIFT 0x0
++#define DSI1_DISP_DSI_MIPI_BIST_START__MIPI_BIST_START_MASK 0x00000001L
++//DSI1_DISP_DSI_MIPI_BIST_STATUS
++#define DSI1_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_STATUS_BUSY__SHIFT 0x0
++#define DSI1_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_DONE__SHIFT 0x4
++#define DSI1_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_DONE_CLR__SHIFT 0x4
++#define DSI1_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_STATUS_BUSY_MASK 0x00000001L
++#define DSI1_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_DONE_MASK 0x00000010L
++#define DSI1_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_DONE_CLR_MASK 0x00000010L
++//DSI1_DISP_DSI_ERROR_INTERRUPT_MASK
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_ECC_ERR_MASK__SHIFT 0x0
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_MULTI_ECC_ERR_MASK__SHIFT 0x1
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_CRC_ERR_MASK__SHIFT 0x2
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_INCOMPLETE_PACKET_ERR_MASK__SHIFT 0x3
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__ERROR_PACKET_MASK__SHIFT 0x4
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__INTERLEAVE_PACKET_BLOCK_MASK__SHIFT 0x5
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__TE_ABORT_MASK__SHIFT 0x6
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_ESC_MASK__SHIFT 0x8
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_SYNC_ESC_MASK__SHIFT 0x9
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTROL_MASK__SHIFT 0xa
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTENTION_LP0_MASK__SHIFT 0xc
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTENTION_LP1_MASK__SHIFT 0xd
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__LP_RX_TO_MASK__SHIFT 0x10
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__HS_TX_TO_MASK__SHIFT 0x11
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__BTA_TO_MASK__SHIFT 0x12
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DMAFIFO_UNDERFLOW_MASK__SHIFT 0x14
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__CMDFIFO_UNDERFLOW_MASK__SHIFT 0x15
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DENGFIFO_OVERFLOW_UNDERFLOW_MASK__SHIFT 0x18
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_HS_FIFO_OVERFLOW_MASK__SHIFT 0x1a
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN1_HS_FIFO_OVERFLOW_MASK__SHIFT 0x1b
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN2_HS_FIFO_OVERFLOW_MASK__SHIFT 0x1c
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN3_HS_FIFO_OVERFLOW_MASK__SHIFT 0x1d
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_LP_FIFO_OVERFLOW_MASK__SHIFT 0x1e
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__INTERLEAVE_OP_CONTENTION_MASK__SHIFT 0x1f
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_ECC_ERR_MASK_MASK 0x00000001L
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_MULTI_ECC_ERR_MASK_MASK 0x00000002L
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_CRC_ERR_MASK_MASK 0x00000004L
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_INCOMPLETE_PACKET_ERR_MASK_MASK 0x00000008L
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__ERROR_PACKET_MASK_MASK 0x00000010L
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__INTERLEAVE_PACKET_BLOCK_MASK_MASK 0x00000020L
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__TE_ABORT_MASK_MASK 0x00000040L
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_ESC_MASK_MASK 0x00000100L
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_SYNC_ESC_MASK_MASK 0x00000200L
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTROL_MASK_MASK 0x00000400L
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTENTION_LP0_MASK_MASK 0x00001000L
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTENTION_LP1_MASK_MASK 0x00002000L
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__LP_RX_TO_MASK_MASK 0x00010000L
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__HS_TX_TO_MASK_MASK 0x00020000L
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__BTA_TO_MASK_MASK 0x00040000L
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DMAFIFO_UNDERFLOW_MASK_MASK 0x00100000L
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__CMDFIFO_UNDERFLOW_MASK_MASK 0x00200000L
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DENGFIFO_OVERFLOW_UNDERFLOW_MASK_MASK 0x01000000L
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_HS_FIFO_OVERFLOW_MASK_MASK 0x04000000L
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN1_HS_FIFO_OVERFLOW_MASK_MASK 0x08000000L
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN2_HS_FIFO_OVERFLOW_MASK_MASK 0x10000000L
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN3_HS_FIFO_OVERFLOW_MASK_MASK 0x20000000L
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_LP_FIFO_OVERFLOW_MASK_MASK 0x40000000L
++#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__INTERLEAVE_OP_CONTENTION_MASK_MASK 0x80000000L
++//DSI1_DISP_DSI_INTERRUPT_CTRL
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_STAT__SHIFT 0x0
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_AK__SHIFT 0x0
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_MASK__SHIFT 0x1
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_STAT__SHIFT 0x4
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_AK__SHIFT 0x4
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_MASK__SHIFT 0x5
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_STAT__SHIFT 0x8
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_AK__SHIFT 0x8
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_MASK__SHIFT 0x9
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_STAT__SHIFT 0xc
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_AK__SHIFT 0xc
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_MASK__SHIFT 0xd
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_STAT__SHIFT 0x10
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_AK__SHIFT 0x10
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_MASK__SHIFT 0x11
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_STAT__SHIFT 0x14
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_AK__SHIFT 0x14
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_MASK__SHIFT 0x15
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_STAT__SHIFT 0x18
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_AK__SHIFT 0x18
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_MASK__SHIFT 0x19
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_STAT_MASK 0x00000001L
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_AK_MASK 0x00000001L
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_MASK_MASK 0x00000002L
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_STAT_MASK 0x00000010L
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_AK_MASK 0x00000010L
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_MASK_MASK 0x00000020L
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_STAT_MASK 0x00000100L
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_AK_MASK 0x00000100L
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_MASK_MASK 0x00000200L
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_STAT_MASK 0x00001000L
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_AK_MASK 0x00001000L
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_MASK_MASK 0x00002000L
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_STAT_MASK 0x00010000L
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_AK_MASK 0x00010000L
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_MASK_MASK 0x00020000L
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_STAT_MASK 0x00100000L
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_AK_MASK 0x00100000L
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_MASK_MASK 0x00200000L
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_STAT_MASK 0x01000000L
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_AK_MASK 0x01000000L
++#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_MASK_MASK 0x02000000L
++//DSI1_DISP_DSI_CLK_CTRL
++#define DSI1_DISP_DSI_CLK_CTRL__DISPCLK_G_ON__SHIFT 0x0
++#define DSI1_DISP_DSI_CLK_CTRL__DISPCLK_R_ON__SHIFT 0x1
++#define DSI1_DISP_DSI_CLK_CTRL__DSICLK_G_ON__SHIFT 0x4
++#define DSI1_DISP_DSI_CLK_CTRL__DSICLK_R_ON__SHIFT 0x5
++#define DSI1_DISP_DSI_CLK_CTRL__DSICLK_TRN_ON__SHIFT 0x6
++#define DSI1_DISP_DSI_CLK_CTRL__BYTECLK_G_ON__SHIFT 0x8
++#define DSI1_DISP_DSI_CLK_CTRL__ESCCLK_G_ON__SHIFT 0x10
++#define DSI1_DISP_DSI_CLK_CTRL__TEST_CLK_SEL__SHIFT 0x18
++#define DSI1_DISP_DSI_CLK_CTRL__DISPCLK_G_ON_MASK 0x00000001L
++#define DSI1_DISP_DSI_CLK_CTRL__DISPCLK_R_ON_MASK 0x00000002L
++#define DSI1_DISP_DSI_CLK_CTRL__DSICLK_G_ON_MASK 0x00000010L
++#define DSI1_DISP_DSI_CLK_CTRL__DSICLK_R_ON_MASK 0x00000020L
++#define DSI1_DISP_DSI_CLK_CTRL__DSICLK_TRN_ON_MASK 0x00000040L
++#define DSI1_DISP_DSI_CLK_CTRL__BYTECLK_G_ON_MASK 0x00000100L
++#define DSI1_DISP_DSI_CLK_CTRL__ESCCLK_G_ON_MASK 0x00010000L
++#define DSI1_DISP_DSI_CLK_CTRL__TEST_CLK_SEL_MASK 0x0F000000L
++//DSI1_DISP_DSI_CLK_STATUS
++#define DSI1_DISP_DSI_CLK_STATUS__DISPCLK_R_ACTIVE__SHIFT 0x0
++#define DSI1_DISP_DSI_CLK_STATUS__DISPCLK_G_ACTIVE__SHIFT 0x1
++#define DSI1_DISP_DSI_CLK_STATUS__DSICLK_R_ACTIVE__SHIFT 0x4
++#define DSI1_DISP_DSI_CLK_STATUS__DSICLK_G_ACTIVE__SHIFT 0x5
++#define DSI1_DISP_DSI_CLK_STATUS__DSICLK_TRN_ACTIVE__SHIFT 0x6
++#define DSI1_DISP_DSI_CLK_STATUS__BYTECLK_G_ACTIVE__SHIFT 0x8
++#define DSI1_DISP_DSI_CLK_STATUS__ESCCLK_G_ACTIVE__SHIFT 0x10
++#define DSI1_DISP_DSI_CLK_STATUS__DISPCLK_R_ACTIVE_MASK 0x00000001L
++#define DSI1_DISP_DSI_CLK_STATUS__DISPCLK_G_ACTIVE_MASK 0x00000002L
++#define DSI1_DISP_DSI_CLK_STATUS__DSICLK_R_ACTIVE_MASK 0x00000010L
++#define DSI1_DISP_DSI_CLK_STATUS__DSICLK_G_ACTIVE_MASK 0x00000020L
++#define DSI1_DISP_DSI_CLK_STATUS__DSICLK_TRN_ACTIVE_MASK 0x00000040L
++#define DSI1_DISP_DSI_CLK_STATUS__BYTECLK_G_ACTIVE_MASK 0x00000100L
++#define DSI1_DISP_DSI_CLK_STATUS__ESCCLK_G_ACTIVE_MASK 0x00010000L
++//DSI1_DISP_DSI_DENG_FIFO_STATUS
++#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_LEVEL_ERROR__SHIFT 0x0
++#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
++#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
++#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_ERROR_ACK__SHIFT 0x9
++#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
++#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_MAXIMUM_LEVEL__SHIFT 0x11
++#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_MINIMUM_LEVEL__SHIFT 0x17
++#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_CALIBRATED__SHIFT 0x1d
++#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
++#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
++#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_LEVEL_ERROR_MASK 0x00000001L
++#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L
++#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_OVERWRITE_LEVEL_MASK 0x000001FCL
++#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_ERROR_ACK_MASK 0x00000200L
++#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0001FC00L
++#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_MAXIMUM_LEVEL_MASK 0x007E0000L
++#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_MINIMUM_LEVEL_MASK 0x0F800000L
++#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_CALIBRATED_MASK 0x20000000L
++#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L
++#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L
++//DSI1_DISP_DSI_DENG_FIFO_CTRL
++#define DSI1_DISP_DSI_DENG_FIFO_CTRL__DENG_FIFO_EN__SHIFT 0x0
++#define DSI1_DISP_DSI_DENG_FIFO_CTRL__DENG_FIFO_START__SHIFT 0x4
++#define DSI1_DISP_DSI_DENG_FIFO_CTRL__DENG_DSICLK_ON__SHIFT 0x8
++#define DSI1_DISP_DSI_DENG_FIFO_CTRL__DENG_FIFO_EN_MASK 0x00000001L
++#define DSI1_DISP_DSI_DENG_FIFO_CTRL__DENG_FIFO_START_MASK 0x00000010L
++#define DSI1_DISP_DSI_DENG_FIFO_CTRL__DENG_DSICLK_ON_MASK 0x00000100L
++//DSI1_DISP_DSI_CMD_FIFO_DATA
++#define DSI1_DISP_DSI_CMD_FIFO_DATA__CMDFIFO_DATA__SHIFT 0x0
++#define DSI1_DISP_DSI_CMD_FIFO_DATA__CMDFIFO_DATA_MASK 0xFFFFFFFFL
++//DSI1_DISP_DSI_CMD_FIFO_CTRL
++#define DSI1_DISP_DSI_CMD_FIFO_CTRL__USE_CMDFIFO__SHIFT 0x0
++#define DSI1_DISP_DSI_CMD_FIFO_CTRL__CMDFIFO_DW_LEVEL__SHIFT 0x4
++#define DSI1_DISP_DSI_CMD_FIFO_CTRL__USE_CMDFIFO_MASK 0x00000001L
++#define DSI1_DISP_DSI_CMD_FIFO_CTRL__CMDFIFO_DW_LEVEL_MASK 0x000007F0L
++//DSI1_DISP_DSI_TE_CTRL
++#define DSI1_DISP_DSI_TE_CTRL__FREEZE_CRTC_HYSTERESIS__SHIFT 0x0
++#define DSI1_DISP_DSI_TE_CTRL__DISABLE_CRTC_FREEZE__SHIFT 0x10
++#define DSI1_DISP_DSI_TE_CTRL__DISABLE_CRTC_FORCE__SHIFT 0x14
++#define DSI1_DISP_DSI_TE_CTRL__CRTC_FREEZE__SHIFT 0x18
++#define DSI1_DISP_DSI_TE_CTRL__CRTC_FREEZE_TRIG__SHIFT 0x18
++#define DSI1_DISP_DSI_TE_CTRL__FREEZE_CRTC_HYSTERESIS_MASK 0x00000FFFL
++#define DSI1_DISP_DSI_TE_CTRL__DISABLE_CRTC_FREEZE_MASK 0x00010000L
++#define DSI1_DISP_DSI_TE_CTRL__DISABLE_CRTC_FORCE_MASK 0x00100000L
++#define DSI1_DISP_DSI_TE_CTRL__CRTC_FREEZE_MASK 0x01000000L
++#define DSI1_DISP_DSI_TE_CTRL__CRTC_FREEZE_TRIG_MASK 0x01000000L
++//DSI1_DISP_DSI_LANE_STATUS
++#define DSI1_DISP_DSI_LANE_STATUS__DLN0_STOPSTATE__SHIFT 0x0
++#define DSI1_DISP_DSI_LANE_STATUS__DLN1_STOPSTATE__SHIFT 0x1
++#define DSI1_DISP_DSI_LANE_STATUS__DLN2_STOPSTATE__SHIFT 0x2
++#define DSI1_DISP_DSI_LANE_STATUS__DLN3_STOPSTATE__SHIFT 0x3
++#define DSI1_DISP_DSI_LANE_STATUS__DLN0_ULPS_ACTIVE_NOT__SHIFT 0x4
++#define DSI1_DISP_DSI_LANE_STATUS__DLN1_ULPS_ACTIVE_NOT__SHIFT 0x5
++#define DSI1_DISP_DSI_LANE_STATUS__DLN2_ULPS_ACTIVE_NOT__SHIFT 0x6
++#define DSI1_DISP_DSI_LANE_STATUS__DLN3_ULPS_ACTIVE_NOT__SHIFT 0x7
++#define DSI1_DISP_DSI_LANE_STATUS__DLN0_DIRECTION__SHIFT 0x8
++#define DSI1_DISP_DSI_LANE_STATUS__CLKLN_STOPSTATE__SHIFT 0x18
++#define DSI1_DISP_DSI_LANE_STATUS__CLKLN_ULPS_ACTIVE_NOT__SHIFT 0x1c
++#define DSI1_DISP_DSI_LANE_STATUS__DLN0_STOPSTATE_MASK 0x00000001L
++#define DSI1_DISP_DSI_LANE_STATUS__DLN1_STOPSTATE_MASK 0x00000002L
++#define DSI1_DISP_DSI_LANE_STATUS__DLN2_STOPSTATE_MASK 0x00000004L
++#define DSI1_DISP_DSI_LANE_STATUS__DLN3_STOPSTATE_MASK 0x00000008L
++#define DSI1_DISP_DSI_LANE_STATUS__DLN0_ULPS_ACTIVE_NOT_MASK 0x00000010L
++#define DSI1_DISP_DSI_LANE_STATUS__DLN1_ULPS_ACTIVE_NOT_MASK 0x00000020L
++#define DSI1_DISP_DSI_LANE_STATUS__DLN2_ULPS_ACTIVE_NOT_MASK 0x00000040L
++#define DSI1_DISP_DSI_LANE_STATUS__DLN3_ULPS_ACTIVE_NOT_MASK 0x00000080L
++#define DSI1_DISP_DSI_LANE_STATUS__DLN0_DIRECTION_MASK 0x00000100L
++#define DSI1_DISP_DSI_LANE_STATUS__CLKLN_STOPSTATE_MASK 0x01000000L
++#define DSI1_DISP_DSI_LANE_STATUS__CLKLN_ULPS_ACTIVE_NOT_MASK 0x10000000L
++//DSI1_DISP_DSI_PERF_CTRL
++#define DSI1_DISP_DSI_PERF_CTRL__PERF_LP_HS_LATENCY_SEL__SHIFT 0x0
++#define DSI1_DISP_DSI_PERF_CTRL__PERF_HS_LP_LATENCY_SEL__SHIFT 0x4
++#define DSI1_DISP_DSI_PERF_CTRL__PERF_LP_HS_LATENCY_SEL_MASK 0x00000003L
++#define DSI1_DISP_DSI_PERF_CTRL__PERF_HS_LP_LATENCY_SEL_MASK 0x00000030L
++//DSI1_DISP_DSI_HSYNC_LENGTH
++#define DSI1_DISP_DSI_HSYNC_LENGTH__HSYNC_LENGTH_MAX__SHIFT 0x0
++#define DSI1_DISP_DSI_HSYNC_LENGTH__HSYNC_LENGTH_MIN__SHIFT 0x10
++#define DSI1_DISP_DSI_HSYNC_LENGTH__HSYNC_LENGTH_MAX_MASK 0x0000FFFFL
++#define DSI1_DISP_DSI_HSYNC_LENGTH__HSYNC_LENGTH_MIN_MASK 0xFFFF0000L
++//DSI1_DISP_DSI_RDBK_NUM
++#define DSI1_DISP_DSI_RDBK_NUM__RD_NUM__SHIFT 0x0
++#define DSI1_DISP_DSI_RDBK_NUM__ALL_NUM__SHIFT 0x10
++#define DSI1_DISP_DSI_RDBK_NUM__RD_NUM_MASK 0x0000FFFFL
++#define DSI1_DISP_DSI_RDBK_NUM__ALL_NUM_MASK 0xFFFF0000L
++//DSI1_DISP_DSI_CMD_MEM_PWR_CTRL
++#define DSI1_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_DIS__SHIFT 0x0
++#define DSI1_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_FORCE__SHIFT 0x4
++#define DSI1_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_STATE__SHIFT 0x8
++#define DSI1_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_MODE_SEL__SHIFT 0xc
++#define DSI1_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_DIS_MASK 0x00000001L
++#define DSI1_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_FORCE_MASK 0x00000030L
++#define DSI1_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_STATE_MASK 0x00000300L
++#define DSI1_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_MODE_SEL_MASK 0x00003000L
++
++
++// addressBlock: dce_dc_dprx_sd0_dispdec
++//DPRX_SD0_DPRX_SD_CONTROL
++#define DPRX_SD0_DPRX_SD_CONTROL__SD_ENABLE__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_CONTROL__SD_RESET__SHIFT 0x4
++#define DPRX_SD0_DPRX_SD_CONTROL__SD_CLOCK_ENABLE__SHIFT 0x8
++#define DPRX_SD0_DPRX_SD_CONTROL__SD_CLOCK_ON__SHIFT 0xc
++#define DPRX_SD0_DPRX_SD_CONTROL__SD_ENABLE_MASK 0x00000001L
++#define DPRX_SD0_DPRX_SD_CONTROL__SD_RESET_MASK 0x00000010L
++#define DPRX_SD0_DPRX_SD_CONTROL__SD_CLOCK_ENABLE_MASK 0x00000100L
++#define DPRX_SD0_DPRX_SD_CONTROL__SD_CLOCK_ON_MASK 0x00001000L
++//DPRX_SD0_DPRX_SD_STREAM_ENABLE
++#define DPRX_SD0_DPRX_SD_STREAM_ENABLE__VID_STREAM_ENABLE__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_STREAM_ENABLE__VID_STREAM_STATUS__SHIFT 0x8
++#define DPRX_SD0_DPRX_SD_STREAM_ENABLE__VID_STREAM_ENABLE_MASK 0x00000001L
++#define DPRX_SD0_DPRX_SD_STREAM_ENABLE__VID_STREAM_STATUS_MASK 0x00000100L
++//DPRX_SD0_DPRX_SD_MSA0
++#define DPRX_SD0_DPRX_SD_MSA0__MSA0__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_MSA0__MSA0_MASK 0xFFFFFFFFL
++//DPRX_SD0_DPRX_SD_MSA1
++#define DPRX_SD0_DPRX_SD_MSA1__MSA1__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_MSA1__MSA1_MASK 0xFFFFFFFFL
++//DPRX_SD0_DPRX_SD_MSA2
++#define DPRX_SD0_DPRX_SD_MSA2__MSA2__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_MSA2__MSA2_MASK 0xFFFFFFFFL
++//DPRX_SD0_DPRX_SD_MSA3
++#define DPRX_SD0_DPRX_SD_MSA3__MSA3__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_MSA3__MSA3_MASK 0xFFFFFFFFL
++//DPRX_SD0_DPRX_SD_MSA4
++#define DPRX_SD0_DPRX_SD_MSA4__MSA4__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_MSA4__MSA4_MASK 0xFFFFFFFFL
++//DPRX_SD0_DPRX_SD_MSA5
++#define DPRX_SD0_DPRX_SD_MSA5__MSA5__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_MSA5__MSA5_MASK 0xFFFFFFFFL
++//DPRX_SD0_DPRX_SD_MSA6
++#define DPRX_SD0_DPRX_SD_MSA6__MSA6__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_MSA6__MSA6_MASK 0xFFFFFFFFL
++//DPRX_SD0_DPRX_SD_MSA7
++#define DPRX_SD0_DPRX_SD_MSA7__MSA7__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_MSA7__MSA7_MASK 0xFFFFFFFFL
++//DPRX_SD0_DPRX_SD_MSA8
++#define DPRX_SD0_DPRX_SD_MSA8__MSA8__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_MSA8__MSA8_MASK 0xFFFFFFFFL
++//DPRX_SD0_DPRX_SD_VBID
++#define DPRX_SD0_DPRX_SD_VBID__VBID__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_VBID__VBID_MASK 0x000000FFL
++//DPRX_SD0_DPRX_SD_CURRENT_LINE
++#define DPRX_SD0_DPRX_SD_CURRENT_LINE__CURRENT_LINE__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_CURRENT_LINE__CURRENT_FRAME__SHIFT 0x10
++#define DPRX_SD0_DPRX_SD_CURRENT_LINE__CURRENT_LINE_MASK 0x0000FFFFL
++#define DPRX_SD0_DPRX_SD_CURRENT_LINE__CURRENT_FRAME_MASK 0x00FF0000L
++//DPRX_SD0_DPRX_SD_DISPLAY_TIMER_SNAPSHOT
++#define DPRX_SD0_DPRX_SD_DISPLAY_TIMER_SNAPSHOT__DISPLAY_TIMER_SNAPSHOT__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_DISPLAY_TIMER_SNAPSHOT__DISPLAY_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
++//DPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE
++#define DPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE__DISPLAY_TIMER_MODE__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE__DISPLAY_TIMER_UPDATE_LOCKED__SHIFT 0x8
++#define DPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE__DISPLAY_TIMER_MODE_MASK 0x00000001L
++#define DPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE__DISPLAY_TIMER_UPDATE_LOCKED_MASK 0x00000100L
++//DPRX_SD0_DPRX_SD_MSE_SAT
++#define DPRX_SD0_DPRX_SD_MSE_SAT__MSE_SAT_SLOT_START__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_MSE_SAT__MSE_SAT_SLOT_END__SHIFT 0x8
++#define DPRX_SD0_DPRX_SD_MSE_SAT__MSE_SAT_SLOT_START_MASK 0x0000003FL
++#define DPRX_SD0_DPRX_SD_MSE_SAT__MSE_SAT_SLOT_END_MASK 0x00003F00L
++//DPRX_SD0_DPRX_SD_MSE_FORCE_UPDATE
++#define DPRX_SD0_DPRX_SD_MSE_FORCE_UPDATE__MSE_SAT_FORCE_UPDATE__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_MSE_FORCE_UPDATE__MSE_SAT_FORCE_UPDATE_MASK 0x00000001L
++//DPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE
++#define DPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE__MSE_SAT_SLOT_START_ACTIVE__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE__MSE_SAT_SLOT_END_ACTIVE__SHIFT 0x8
++#define DPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE__MSE_SAT_SLOT_START_ACTIVE_MASK 0x0000003FL
++#define DPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE__MSE_SAT_SLOT_END_ACTIVE_MASK 0x00003F00L
++//DPRX_SD0_DPRX_SD_V_PARAMETER
++#define DPRX_SD0_DPRX_SD_V_PARAMETER__V_BLANK_HEIGHT__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_V_PARAMETER__V_BLANK_HEIGHT_MASK 0x0000FFFFL
++//DPRX_SD0_DPRX_SD_PIXEL_FORMAT
++#define DPRX_SD0_DPRX_SD_PIXEL_FORMAT__PIXEL_ENCODING__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_PIXEL_FORMAT__COMPONENT_DEPTH__SHIFT 0x8
++#define DPRX_SD0_DPRX_SD_PIXEL_FORMAT__PIXEL_ENCODING_MASK 0x00000003L
++#define DPRX_SD0_DPRX_SD_PIXEL_FORMAT__COMPONENT_DEPTH_MASK 0x00000700L
++//DPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS
++#define DPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_FLAG__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_ACK__SHIFT 0x4
++#define DPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_MASK__SHIFT 0x8
++#define DPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_FLAG_MASK 0x00000001L
++#define DPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_ACK_MASK 0x00000010L
++#define DPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_MASK_MASK 0x00000100L
++//DPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED
++#define DPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_FLAG__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_ACK__SHIFT 0x4
++#define DPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_MASK__SHIFT 0x8
++#define DPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_FLAG_MASK 0x00000001L
++#define DPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_ACK_MASK 0x00000010L
++#define DPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_MASK_MASK 0x00000100L
++//DPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS
++#define DPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_FLAG__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_ACK__SHIFT 0x4
++#define DPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_MASK__SHIFT 0x8
++#define DPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_TYPE__SHIFT 0xc
++#define DPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_FLAG_MASK 0x00000001L
++#define DPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_ACK_MASK 0x00000010L
++#define DPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_MASK_MASK 0x00000100L
++#define DPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_TYPE_MASK 0x00001000L
++//DPRX_SD0_DPRX_SD_LINE_NUMBER0_CONTROL
++#define DPRX_SD0_DPRX_SD_LINE_NUMBER0_CONTROL__LINE_NUMBER0_INTERRUPT__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_LINE_NUMBER0_CONTROL__LINE_NUMBER0_INTERRUPT_MASK 0x0000FFFFL
++//DPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS
++#define DPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_FLAG__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_ACK__SHIFT 0x4
++#define DPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_MASK__SHIFT 0x8
++#define DPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_TYPE__SHIFT 0xc
++#define DPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_FLAG_MASK 0x00000001L
++#define DPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_ACK_MASK 0x00000010L
++#define DPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_MASK_MASK 0x00000100L
++#define DPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_TYPE_MASK 0x00001000L
++//DPRX_SD0_DPRX_SD_LINE_NUMBER1_CONTROL
++#define DPRX_SD0_DPRX_SD_LINE_NUMBER1_CONTROL__LINE_NUMBER1_INTERRUPT__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_LINE_NUMBER1_CONTROL__LINE_NUMBER1_INTERRUPT_MASK 0x0000FFFFL
++//DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR
++#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__BS1_ERROR__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__VBID_ERROR__SHIFT 0x1
++#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__MVID_ERROR__SHIFT 0x2
++#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__MAUD_ERROR__SHIFT 0x3
++#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__IDLE_ERROR__SHIFT 0x4
++#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__BE_BS_ERROR__SHIFT 0x5
++#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__BE_OTHER_ERROR__SHIFT 0x6
++#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__PIX_ERROR__SHIFT 0x7
++#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FS_BS_ERROR__SHIFT 0x8
++#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FS_OTHER_ERROR__SHIFT 0x9
++#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FILL_BS_ERROR__SHIFT 0xa
++#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FILL_OTHER_ERROR__SHIFT 0xb
++#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FE_BS_ERROR__SHIFT 0xc
++#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FE_OTHER_ERROR__SHIFT 0xd
++#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FILTER_BE_ERROR__SHIFT 0xe
++#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__BS1_ERROR_MASK 0x00000001L
++#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__VBID_ERROR_MASK 0x00000002L
++#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__MVID_ERROR_MASK 0x00000004L
++#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__MAUD_ERROR_MASK 0x00000008L
++#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__IDLE_ERROR_MASK 0x00000010L
++#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__BE_BS_ERROR_MASK 0x00000020L
++#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__BE_OTHER_ERROR_MASK 0x00000040L
++#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__PIX_ERROR_MASK 0x00000080L
++#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FS_BS_ERROR_MASK 0x00000100L
++#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FS_OTHER_ERROR_MASK 0x00000200L
++#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FILL_BS_ERROR_MASK 0x00000400L
++#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FILL_OTHER_ERROR_MASK 0x00000800L
++#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FE_BS_ERROR_MASK 0x00001000L
++#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FE_OTHER_ERROR_MASK 0x00002000L
++#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FILTER_BE_ERROR_MASK 0x00004000L
++//DPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE
++#define DPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_1_ERROR__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_2_ERROR__SHIFT 0x1
++#define DPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_FAIL__SHIFT 0x2
++#define DPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_1_ERROR_MASK 0x00000001L
++#define DPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_2_ERROR_MASK 0x00000002L
++#define DPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_FAIL_MASK 0x00000004L
++//DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR
++#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_MSA_SS0_ERROR__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_MSA_SS1_ERROR__SHIFT 0x1
++#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_MSA_DATA_ERROR__SHIFT 0x2
++#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_EXPIRE_ERROR__SHIFT 0x4
++#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_SE_ILLEGAL_SE_ERROR__SHIFT 0x5
++#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_ERROR__SHIFT 0x6
++#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SS1_ERROR__SHIFT 0x8
++#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SS2_ERROR__SHIFT 0x9
++#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_DATA_ERROR__SHIFT 0xa
++#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_EXPIRE_ERROR__SHIFT 0xb
++#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_ILLEGAL_SE_ERROR__SHIFT 0xc
++#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_ERROR__SHIFT 0xd
++#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_MSA_SS0_ERROR_MASK 0x00000001L
++#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_MSA_SS1_ERROR_MASK 0x00000002L
++#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_MSA_DATA_ERROR_MASK 0x00000004L
++#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_EXPIRE_ERROR_MASK 0x00000010L
++#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_SE_ILLEGAL_SE_ERROR_MASK 0x00000020L
++#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_ERROR_MASK 0x00000040L
++#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SS1_ERROR_MASK 0x00000100L
++#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SS2_ERROR_MASK 0x00000200L
++#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_DATA_ERROR_MASK 0x00000400L
++#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_EXPIRE_ERROR_MASK 0x00000800L
++#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_ILLEGAL_SE_ERROR_MASK 0x00001000L
++#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_ERROR_MASK 0x00002000L
++//DPRX_SD0_DPRX_SD_VCPF_PHASE_LOCKED
++#define DPRX_SD0_DPRX_SD_VCPF_PHASE_LOCKED__VCPF_PHASE_LOCKED__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_VCPF_PHASE_LOCKED__VCPF_PHASE_LOCKED_MASK 0x00000001L
++//DPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR
++#define DPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR__VCPF_PHASE_ERROR__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR__VCPF_1_SYMBOL_ERROR__SHIFT 0x1
++#define DPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR__VCPF_2_SYMBOL_ERROR__SHIFT 0x2
++#define DPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR__VCPF_PHASE_ERROR_MASK 0x00000001L
++#define DPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR__VCPF_1_SYMBOL_ERROR_MASK 0x00000002L
++#define DPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR__VCPF_2_SYMBOL_ERROR_MASK 0x00000004L
++//DPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR
++#define DPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR__CORRECTED_CONTROL_SEQUENCE_ERROR__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR__CORRECTED_DATA_SEQUENCE_ERROR__SHIFT 0x8
++#define DPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR__CORRECTED_CONTROL_SEQUENCE_ERROR_MASK 0x00000001L
++#define DPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR__CORRECTED_DATA_SEQUENCE_ERROR_MASK 0x00000100L
++//DPRX_SD0_DPRX_SD_PIXEL_FIFO_ERROR
++#define DPRX_SD0_DPRX_SD_PIXEL_FIFO_ERROR__PIXEL_FIFO_OVERFLOW_ERROR__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_PIXEL_FIFO_ERROR__PIXEL_FIFO_OVERFLOW_ERROR_MASK 0x00000001L
++//DPRX_SD0_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH
++#define DPRX_SD0_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH__MAXIMUM_SDP_PAYLOAD_LENGTH__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH__MAXIMUM_SDP_PAYLOAD_LENGTH_MASK 0x000003FFL
++//DPRX_SD0_DPRX_SD_SDP_STEER
++#define DPRX_SD0_DPRX_SD_SDP_STEER__FILTER_AUDIO_TIMESTAMP_SDP_EN__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_SDP_STEER__FILTER_AUDIO_TIMESTAMP_SDP_EN_MASK 0x00000001L
++//DPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS
++#define DPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_FLAG__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_ACK__SHIFT 0x4
++#define DPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_MASK__SHIFT 0x8
++#define DPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_FLAG_MASK 0x00000001L
++#define DPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_ACK_MASK 0x00000010L
++#define DPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_MASK_MASK 0x00000100L
++//DPRX_SD0_DPRX_SD_SDP_LEVEL
++#define DPRX_SD0_DPRX_SD_SDP_LEVEL__SDP_FIFO_LEVEL__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_SDP_LEVEL__SDP_CURRENT_SLICE__SHIFT 0x8
++#define DPRX_SD0_DPRX_SD_SDP_LEVEL__SDP_FIFO_LEVEL_MASK 0x0000001FL
++#define DPRX_SD0_DPRX_SD_SDP_LEVEL__SDP_CURRENT_SLICE_MASK 0x00000F00L
++//DPRX_SD0_DPRX_SD_SDP_DATA
++#define DPRX_SD0_DPRX_SD_SDP_DATA__SDP_DATA__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_SDP_DATA__SDP_DATA_MASK 0xFFFFFFFFL
++//DPRX_SD0_DPRX_SD_SDP_ERROR
++#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_FIFO_OVERFLOW_ERROR__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_HEADER_ERROR__SHIFT 0x1
++#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_NON_AUDIO_PAYLOAD_ERROR__SHIFT 0x2
++#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_NON_AUDIO_LENGTH_ERROR__SHIFT 0x3
++#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_RS_CORRECTED_ERROR__SHIFT 0x4
++#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_RS_UNCORRECTABLE_ERROR__SHIFT 0x5
++#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_AUDIO_PAYLOAD_ERROR__SHIFT 0x6
++#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_FIFO_OVERFLOW_ERROR_MASK 0x00000001L
++#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_HEADER_ERROR_MASK 0x00000002L
++#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_NON_AUDIO_PAYLOAD_ERROR_MASK 0x00000004L
++#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_NON_AUDIO_LENGTH_ERROR_MASK 0x00000008L
++#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_RS_CORRECTED_ERROR_MASK 0x00000010L
++#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_RS_UNCORRECTABLE_ERROR_MASK 0x00000020L
++#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_AUDIO_PAYLOAD_ERROR_MASK 0x00000040L
++//DPRX_SD0_DPRX_SD_AUDIO_HEADER
++#define DPRX_SD0_DPRX_SD_AUDIO_HEADER__AUDIO_HEADER__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_AUDIO_HEADER__AUDIO_HEADER_MASK 0xFFFFFFFFL
++//DPRX_SD0_DPRX_SD_AUDIO_FIFO_ERROR
++#define DPRX_SD0_DPRX_SD_AUDIO_FIFO_ERROR__AUDIO_FIFO_OVERFLOW_ERROR__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_AUDIO_FIFO_ERROR__AUDIO_FIFO_OVERFLOW_ERROR_MASK 0x00000001L
++//DPRX_SD0_DPRX_SD_SDP_CONTROL
++#define DPRX_SD0_DPRX_SD_SDP_CONTROL__RS_DECODER_ENABLE__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_SDP_CONTROL__RS_ERROR_CORRECTION_ENABLE__SHIFT 0x4
++#define DPRX_SD0_DPRX_SD_SDP_CONTROL__RS_DECODER_ENABLE_MASK 0x00000001L
++#define DPRX_SD0_DPRX_SD_SDP_CONTROL__RS_ERROR_CORRECTION_ENABLE_MASK 0x00000010L
++//DPRX_SD0_DPRX_SD_V_TOTAL_MEASURED
++#define DPRX_SD0_DPRX_SD_V_TOTAL_MEASURED__V_ACTIVE_LINE_TOTAL__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_V_TOTAL_MEASURED__V_LINE_TOTAL__SHIFT 0x10
++#define DPRX_SD0_DPRX_SD_V_TOTAL_MEASURED__V_ACTIVE_LINE_TOTAL_MASK 0x0000FFFFL
++#define DPRX_SD0_DPRX_SD_V_TOTAL_MEASURED__V_LINE_TOTAL_MASK 0xFFFF0000L
++//DPRX_SD0_DPRX_SD_H_TOTAL_MEASURED
++#define DPRX_SD0_DPRX_SD_H_TOTAL_MEASURED__H_ACTIVE_SYMBOL_TOTAL__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_H_TOTAL_MEASURED__H_ACTIVE_SYMBOL_TOTAL_MASK 0x0000FFFFL
++//DPRX_SD0_DPRX_SD_BS_COUNTER
++#define DPRX_SD0_DPRX_SD_BS_COUNTER__BS_COUNTER__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_BS_COUNTER__BS_COUNTER_MASK 0x000003FFL
++//DPRX_SD0_DPRX_SD_MSE_ACT_HANDLED
++#define DPRX_SD0_DPRX_SD_MSE_ACT_HANDLED__MSE_ACT_HANDLED__SHIFT 0x0
++#define DPRX_SD0_DPRX_SD_MSE_ACT_HANDLED__MSE_ACT_HANDLED_MASK 0x00000001L
++
++
++// addressBlock: dce_dc_dprx_sd1_dispdec
++//DPRX_SD1_DPRX_SD_CONTROL
++#define DPRX_SD1_DPRX_SD_CONTROL__SD_ENABLE__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_CONTROL__SD_RESET__SHIFT 0x4
++#define DPRX_SD1_DPRX_SD_CONTROL__SD_CLOCK_ENABLE__SHIFT 0x8
++#define DPRX_SD1_DPRX_SD_CONTROL__SD_CLOCK_ON__SHIFT 0xc
++#define DPRX_SD1_DPRX_SD_CONTROL__SD_ENABLE_MASK 0x00000001L
++#define DPRX_SD1_DPRX_SD_CONTROL__SD_RESET_MASK 0x00000010L
++#define DPRX_SD1_DPRX_SD_CONTROL__SD_CLOCK_ENABLE_MASK 0x00000100L
++#define DPRX_SD1_DPRX_SD_CONTROL__SD_CLOCK_ON_MASK 0x00001000L
++//DPRX_SD1_DPRX_SD_STREAM_ENABLE
++#define DPRX_SD1_DPRX_SD_STREAM_ENABLE__VID_STREAM_ENABLE__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_STREAM_ENABLE__VID_STREAM_STATUS__SHIFT 0x8
++#define DPRX_SD1_DPRX_SD_STREAM_ENABLE__VID_STREAM_ENABLE_MASK 0x00000001L
++#define DPRX_SD1_DPRX_SD_STREAM_ENABLE__VID_STREAM_STATUS_MASK 0x00000100L
++//DPRX_SD1_DPRX_SD_MSA0
++#define DPRX_SD1_DPRX_SD_MSA0__MSA0__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_MSA0__MSA0_MASK 0xFFFFFFFFL
++//DPRX_SD1_DPRX_SD_MSA1
++#define DPRX_SD1_DPRX_SD_MSA1__MSA1__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_MSA1__MSA1_MASK 0xFFFFFFFFL
++//DPRX_SD1_DPRX_SD_MSA2
++#define DPRX_SD1_DPRX_SD_MSA2__MSA2__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_MSA2__MSA2_MASK 0xFFFFFFFFL
++//DPRX_SD1_DPRX_SD_MSA3
++#define DPRX_SD1_DPRX_SD_MSA3__MSA3__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_MSA3__MSA3_MASK 0xFFFFFFFFL
++//DPRX_SD1_DPRX_SD_MSA4
++#define DPRX_SD1_DPRX_SD_MSA4__MSA4__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_MSA4__MSA4_MASK 0xFFFFFFFFL
++//DPRX_SD1_DPRX_SD_MSA5
++#define DPRX_SD1_DPRX_SD_MSA5__MSA5__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_MSA5__MSA5_MASK 0xFFFFFFFFL
++//DPRX_SD1_DPRX_SD_MSA6
++#define DPRX_SD1_DPRX_SD_MSA6__MSA6__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_MSA6__MSA6_MASK 0xFFFFFFFFL
++//DPRX_SD1_DPRX_SD_MSA7
++#define DPRX_SD1_DPRX_SD_MSA7__MSA7__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_MSA7__MSA7_MASK 0xFFFFFFFFL
++//DPRX_SD1_DPRX_SD_MSA8
++#define DPRX_SD1_DPRX_SD_MSA8__MSA8__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_MSA8__MSA8_MASK 0xFFFFFFFFL
++//DPRX_SD1_DPRX_SD_VBID
++#define DPRX_SD1_DPRX_SD_VBID__VBID__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_VBID__VBID_MASK 0x000000FFL
++//DPRX_SD1_DPRX_SD_CURRENT_LINE
++#define DPRX_SD1_DPRX_SD_CURRENT_LINE__CURRENT_LINE__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_CURRENT_LINE__CURRENT_FRAME__SHIFT 0x10
++#define DPRX_SD1_DPRX_SD_CURRENT_LINE__CURRENT_LINE_MASK 0x0000FFFFL
++#define DPRX_SD1_DPRX_SD_CURRENT_LINE__CURRENT_FRAME_MASK 0x00FF0000L
++//DPRX_SD1_DPRX_SD_DISPLAY_TIMER_SNAPSHOT
++#define DPRX_SD1_DPRX_SD_DISPLAY_TIMER_SNAPSHOT__DISPLAY_TIMER_SNAPSHOT__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_DISPLAY_TIMER_SNAPSHOT__DISPLAY_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
++//DPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE
++#define DPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE__DISPLAY_TIMER_MODE__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE__DISPLAY_TIMER_UPDATE_LOCKED__SHIFT 0x8
++#define DPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE__DISPLAY_TIMER_MODE_MASK 0x00000001L
++#define DPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE__DISPLAY_TIMER_UPDATE_LOCKED_MASK 0x00000100L
++//DPRX_SD1_DPRX_SD_MSE_SAT
++#define DPRX_SD1_DPRX_SD_MSE_SAT__MSE_SAT_SLOT_START__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_MSE_SAT__MSE_SAT_SLOT_END__SHIFT 0x8
++#define DPRX_SD1_DPRX_SD_MSE_SAT__MSE_SAT_SLOT_START_MASK 0x0000003FL
++#define DPRX_SD1_DPRX_SD_MSE_SAT__MSE_SAT_SLOT_END_MASK 0x00003F00L
++//DPRX_SD1_DPRX_SD_MSE_FORCE_UPDATE
++#define DPRX_SD1_DPRX_SD_MSE_FORCE_UPDATE__MSE_SAT_FORCE_UPDATE__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_MSE_FORCE_UPDATE__MSE_SAT_FORCE_UPDATE_MASK 0x00000001L
++//DPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE
++#define DPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE__MSE_SAT_SLOT_START_ACTIVE__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE__MSE_SAT_SLOT_END_ACTIVE__SHIFT 0x8
++#define DPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE__MSE_SAT_SLOT_START_ACTIVE_MASK 0x0000003FL
++#define DPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE__MSE_SAT_SLOT_END_ACTIVE_MASK 0x00003F00L
++//DPRX_SD1_DPRX_SD_V_PARAMETER
++#define DPRX_SD1_DPRX_SD_V_PARAMETER__V_BLANK_HEIGHT__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_V_PARAMETER__V_BLANK_HEIGHT_MASK 0x0000FFFFL
++//DPRX_SD1_DPRX_SD_PIXEL_FORMAT
++#define DPRX_SD1_DPRX_SD_PIXEL_FORMAT__PIXEL_ENCODING__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_PIXEL_FORMAT__COMPONENT_DEPTH__SHIFT 0x8
++#define DPRX_SD1_DPRX_SD_PIXEL_FORMAT__PIXEL_ENCODING_MASK 0x00000003L
++#define DPRX_SD1_DPRX_SD_PIXEL_FORMAT__COMPONENT_DEPTH_MASK 0x00000700L
++//DPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS
++#define DPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_FLAG__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_ACK__SHIFT 0x4
++#define DPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_MASK__SHIFT 0x8
++#define DPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_FLAG_MASK 0x00000001L
++#define DPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_ACK_MASK 0x00000010L
++#define DPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_MASK_MASK 0x00000100L
++//DPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED
++#define DPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_FLAG__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_ACK__SHIFT 0x4
++#define DPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_MASK__SHIFT 0x8
++#define DPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_FLAG_MASK 0x00000001L
++#define DPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_ACK_MASK 0x00000010L
++#define DPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_MASK_MASK 0x00000100L
++//DPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS
++#define DPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_FLAG__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_ACK__SHIFT 0x4
++#define DPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_MASK__SHIFT 0x8
++#define DPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_TYPE__SHIFT 0xc
++#define DPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_FLAG_MASK 0x00000001L
++#define DPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_ACK_MASK 0x00000010L
++#define DPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_MASK_MASK 0x00000100L
++#define DPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_TYPE_MASK 0x00001000L
++//DPRX_SD1_DPRX_SD_LINE_NUMBER0_CONTROL
++#define DPRX_SD1_DPRX_SD_LINE_NUMBER0_CONTROL__LINE_NUMBER0_INTERRUPT__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_LINE_NUMBER0_CONTROL__LINE_NUMBER0_INTERRUPT_MASK 0x0000FFFFL
++//DPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS
++#define DPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_FLAG__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_ACK__SHIFT 0x4
++#define DPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_MASK__SHIFT 0x8
++#define DPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_TYPE__SHIFT 0xc
++#define DPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_FLAG_MASK 0x00000001L
++#define DPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_ACK_MASK 0x00000010L
++#define DPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_MASK_MASK 0x00000100L
++#define DPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_TYPE_MASK 0x00001000L
++//DPRX_SD1_DPRX_SD_LINE_NUMBER1_CONTROL
++#define DPRX_SD1_DPRX_SD_LINE_NUMBER1_CONTROL__LINE_NUMBER1_INTERRUPT__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_LINE_NUMBER1_CONTROL__LINE_NUMBER1_INTERRUPT_MASK 0x0000FFFFL
++//DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR
++#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__BS1_ERROR__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__VBID_ERROR__SHIFT 0x1
++#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__MVID_ERROR__SHIFT 0x2
++#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__MAUD_ERROR__SHIFT 0x3
++#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__IDLE_ERROR__SHIFT 0x4
++#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__BE_BS_ERROR__SHIFT 0x5
++#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__BE_OTHER_ERROR__SHIFT 0x6
++#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__PIX_ERROR__SHIFT 0x7
++#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FS_BS_ERROR__SHIFT 0x8
++#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FS_OTHER_ERROR__SHIFT 0x9
++#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FILL_BS_ERROR__SHIFT 0xa
++#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FILL_OTHER_ERROR__SHIFT 0xb
++#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FE_BS_ERROR__SHIFT 0xc
++#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FE_OTHER_ERROR__SHIFT 0xd
++#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FILTER_BE_ERROR__SHIFT 0xe
++#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__BS1_ERROR_MASK 0x00000001L
++#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__VBID_ERROR_MASK 0x00000002L
++#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__MVID_ERROR_MASK 0x00000004L
++#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__MAUD_ERROR_MASK 0x00000008L
++#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__IDLE_ERROR_MASK 0x00000010L
++#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__BE_BS_ERROR_MASK 0x00000020L
++#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__BE_OTHER_ERROR_MASK 0x00000040L
++#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__PIX_ERROR_MASK 0x00000080L
++#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FS_BS_ERROR_MASK 0x00000100L
++#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FS_OTHER_ERROR_MASK 0x00000200L
++#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FILL_BS_ERROR_MASK 0x00000400L
++#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FILL_OTHER_ERROR_MASK 0x00000800L
++#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FE_BS_ERROR_MASK 0x00001000L
++#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FE_OTHER_ERROR_MASK 0x00002000L
++#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FILTER_BE_ERROR_MASK 0x00004000L
++//DPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE
++#define DPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_1_ERROR__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_2_ERROR__SHIFT 0x1
++#define DPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_FAIL__SHIFT 0x2
++#define DPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_1_ERROR_MASK 0x00000001L
++#define DPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_2_ERROR_MASK 0x00000002L
++#define DPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_FAIL_MASK 0x00000004L
++//DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR
++#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_MSA_SS0_ERROR__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_MSA_SS1_ERROR__SHIFT 0x1
++#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_MSA_DATA_ERROR__SHIFT 0x2
++#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_EXPIRE_ERROR__SHIFT 0x4
++#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_SE_ILLEGAL_SE_ERROR__SHIFT 0x5
++#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_ERROR__SHIFT 0x6
++#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SS1_ERROR__SHIFT 0x8
++#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SS2_ERROR__SHIFT 0x9
++#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_DATA_ERROR__SHIFT 0xa
++#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_EXPIRE_ERROR__SHIFT 0xb
++#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_ILLEGAL_SE_ERROR__SHIFT 0xc
++#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_ERROR__SHIFT 0xd
++#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_MSA_SS0_ERROR_MASK 0x00000001L
++#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_MSA_SS1_ERROR_MASK 0x00000002L
++#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_MSA_DATA_ERROR_MASK 0x00000004L
++#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_EXPIRE_ERROR_MASK 0x00000010L
++#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_SE_ILLEGAL_SE_ERROR_MASK 0x00000020L
++#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_ERROR_MASK 0x00000040L
++#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SS1_ERROR_MASK 0x00000100L
++#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SS2_ERROR_MASK 0x00000200L
++#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_DATA_ERROR_MASK 0x00000400L
++#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_EXPIRE_ERROR_MASK 0x00000800L
++#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_ILLEGAL_SE_ERROR_MASK 0x00001000L
++#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_ERROR_MASK 0x00002000L
++//DPRX_SD1_DPRX_SD_VCPF_PHASE_LOCKED
++#define DPRX_SD1_DPRX_SD_VCPF_PHASE_LOCKED__VCPF_PHASE_LOCKED__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_VCPF_PHASE_LOCKED__VCPF_PHASE_LOCKED_MASK 0x00000001L
++//DPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR
++#define DPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR__VCPF_PHASE_ERROR__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR__VCPF_1_SYMBOL_ERROR__SHIFT 0x1
++#define DPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR__VCPF_2_SYMBOL_ERROR__SHIFT 0x2
++#define DPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR__VCPF_PHASE_ERROR_MASK 0x00000001L
++#define DPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR__VCPF_1_SYMBOL_ERROR_MASK 0x00000002L
++#define DPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR__VCPF_2_SYMBOL_ERROR_MASK 0x00000004L
++//DPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR
++#define DPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR__CORRECTED_CONTROL_SEQUENCE_ERROR__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR__CORRECTED_DATA_SEQUENCE_ERROR__SHIFT 0x8
++#define DPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR__CORRECTED_CONTROL_SEQUENCE_ERROR_MASK 0x00000001L
++#define DPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR__CORRECTED_DATA_SEQUENCE_ERROR_MASK 0x00000100L
++//DPRX_SD1_DPRX_SD_PIXEL_FIFO_ERROR
++#define DPRX_SD1_DPRX_SD_PIXEL_FIFO_ERROR__PIXEL_FIFO_OVERFLOW_ERROR__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_PIXEL_FIFO_ERROR__PIXEL_FIFO_OVERFLOW_ERROR_MASK 0x00000001L
++//DPRX_SD1_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH
++#define DPRX_SD1_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH__MAXIMUM_SDP_PAYLOAD_LENGTH__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH__MAXIMUM_SDP_PAYLOAD_LENGTH_MASK 0x000003FFL
++//DPRX_SD1_DPRX_SD_SDP_STEER
++#define DPRX_SD1_DPRX_SD_SDP_STEER__FILTER_AUDIO_TIMESTAMP_SDP_EN__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_SDP_STEER__FILTER_AUDIO_TIMESTAMP_SDP_EN_MASK 0x00000001L
++//DPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS
++#define DPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_FLAG__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_ACK__SHIFT 0x4
++#define DPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_MASK__SHIFT 0x8
++#define DPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_FLAG_MASK 0x00000001L
++#define DPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_ACK_MASK 0x00000010L
++#define DPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_MASK_MASK 0x00000100L
++//DPRX_SD1_DPRX_SD_SDP_LEVEL
++#define DPRX_SD1_DPRX_SD_SDP_LEVEL__SDP_FIFO_LEVEL__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_SDP_LEVEL__SDP_CURRENT_SLICE__SHIFT 0x8
++#define DPRX_SD1_DPRX_SD_SDP_LEVEL__SDP_FIFO_LEVEL_MASK 0x0000001FL
++#define DPRX_SD1_DPRX_SD_SDP_LEVEL__SDP_CURRENT_SLICE_MASK 0x00000F00L
++//DPRX_SD1_DPRX_SD_SDP_DATA
++#define DPRX_SD1_DPRX_SD_SDP_DATA__SDP_DATA__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_SDP_DATA__SDP_DATA_MASK 0xFFFFFFFFL
++//DPRX_SD1_DPRX_SD_SDP_ERROR
++#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_FIFO_OVERFLOW_ERROR__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_HEADER_ERROR__SHIFT 0x1
++#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_NON_AUDIO_PAYLOAD_ERROR__SHIFT 0x2
++#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_NON_AUDIO_LENGTH_ERROR__SHIFT 0x3
++#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_RS_CORRECTED_ERROR__SHIFT 0x4
++#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_RS_UNCORRECTABLE_ERROR__SHIFT 0x5
++#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_AUDIO_PAYLOAD_ERROR__SHIFT 0x6
++#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_FIFO_OVERFLOW_ERROR_MASK 0x00000001L
++#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_HEADER_ERROR_MASK 0x00000002L
++#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_NON_AUDIO_PAYLOAD_ERROR_MASK 0x00000004L
++#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_NON_AUDIO_LENGTH_ERROR_MASK 0x00000008L
++#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_RS_CORRECTED_ERROR_MASK 0x00000010L
++#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_RS_UNCORRECTABLE_ERROR_MASK 0x00000020L
++#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_AUDIO_PAYLOAD_ERROR_MASK 0x00000040L
++//DPRX_SD1_DPRX_SD_AUDIO_HEADER
++#define DPRX_SD1_DPRX_SD_AUDIO_HEADER__AUDIO_HEADER__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_AUDIO_HEADER__AUDIO_HEADER_MASK 0xFFFFFFFFL
++//DPRX_SD1_DPRX_SD_AUDIO_FIFO_ERROR
++#define DPRX_SD1_DPRX_SD_AUDIO_FIFO_ERROR__AUDIO_FIFO_OVERFLOW_ERROR__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_AUDIO_FIFO_ERROR__AUDIO_FIFO_OVERFLOW_ERROR_MASK 0x00000001L
++//DPRX_SD1_DPRX_SD_SDP_CONTROL
++#define DPRX_SD1_DPRX_SD_SDP_CONTROL__RS_DECODER_ENABLE__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_SDP_CONTROL__RS_ERROR_CORRECTION_ENABLE__SHIFT 0x4
++#define DPRX_SD1_DPRX_SD_SDP_CONTROL__RS_DECODER_ENABLE_MASK 0x00000001L
++#define DPRX_SD1_DPRX_SD_SDP_CONTROL__RS_ERROR_CORRECTION_ENABLE_MASK 0x00000010L
++//DPRX_SD1_DPRX_SD_V_TOTAL_MEASURED
++#define DPRX_SD1_DPRX_SD_V_TOTAL_MEASURED__V_ACTIVE_LINE_TOTAL__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_V_TOTAL_MEASURED__V_LINE_TOTAL__SHIFT 0x10
++#define DPRX_SD1_DPRX_SD_V_TOTAL_MEASURED__V_ACTIVE_LINE_TOTAL_MASK 0x0000FFFFL
++#define DPRX_SD1_DPRX_SD_V_TOTAL_MEASURED__V_LINE_TOTAL_MASK 0xFFFF0000L
++//DPRX_SD1_DPRX_SD_H_TOTAL_MEASURED
++#define DPRX_SD1_DPRX_SD_H_TOTAL_MEASURED__H_ACTIVE_SYMBOL_TOTAL__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_H_TOTAL_MEASURED__H_ACTIVE_SYMBOL_TOTAL_MASK 0x0000FFFFL
++//DPRX_SD1_DPRX_SD_BS_COUNTER
++#define DPRX_SD1_DPRX_SD_BS_COUNTER__BS_COUNTER__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_BS_COUNTER__BS_COUNTER_MASK 0x000003FFL
++//DPRX_SD1_DPRX_SD_MSE_ACT_HANDLED
++#define DPRX_SD1_DPRX_SD_MSE_ACT_HANDLED__MSE_ACT_HANDLED__SHIFT 0x0
++#define DPRX_SD1_DPRX_SD_MSE_ACT_HANDLED__MSE_ACT_HANDLED_MASK 0x00000001L
++
++
++// addressBlock: dce_dc_dc_perfmon10_dispdec
++//DC_PERFMON10_PERFCOUNTER_CNTL
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
++//DC_PERFMON10_PERFCOUNTER_CNTL2
++#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
++#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
++#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
++#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
++#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
++#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
++#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
++#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
++//DC_PERFMON10_PERFCOUNTER_STATE
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
++//DC_PERFMON10_PERFMON_CNTL
++#define DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
++#define DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
++#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
++#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
++#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
++#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
++#define DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
++#define DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
++#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
++#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
++#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
++#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
++//DC_PERFMON10_PERFMON_CNTL2
++#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
++#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
++#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
++#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
++#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
++#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
++#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
++#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
++//DC_PERFMON10_PERFMON_CVALUE_INT_MISC
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
++//DC_PERFMON10_PERFMON_CVALUE_LOW
++#define DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
++#define DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
++//DC_PERFMON10_PERFMON_HI
++#define DC_PERFMON10_PERFMON_HI__PERFMON_HI__SHIFT 0x0
++#define DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
++#define DC_PERFMON10_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
++#define DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
++//DC_PERFMON10_PERFMON_LOW
++#define DC_PERFMON10_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
++#define DC_PERFMON10_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dc_zcalregs_dispdec
++//COMP_EN_CTL
++#define COMP_EN_CTL__comp_en__SHIFT 0x0
++#define COMP_EN_CTL__comp_en_override__SHIFT 0x2
++#define COMP_EN_CTL__comp_done__SHIFT 0x4
++#define COMP_EN_CTL__zcal_code_override__SHIFT 0x6
++#define COMP_EN_CTL__zcal_cal_rtt__SHIFT 0x7
++#define COMP_EN_CTL__zcal_base_en__SHIFT 0x8
++#define COMP_EN_CTL__zcal_ht_rtt_sel__SHIFT 0x9
++#define COMP_EN_CTL__zcal_code__SHIFT 0xa
++#define COMP_EN_CTL__zcal_ron_cal_mode__SHIFT 0x10
++#define COMP_EN_CTL__zcal_ana_dbg_sel__SHIFT 0x11
++#define COMP_EN_CTL__cfg_cml_cmos_sel__SHIFT 0x13
++#define COMP_EN_CTL__dsm_sel__SHIFT 0x14
++#define COMP_EN_CTL__comp_en_MASK 0x00000001L
++#define COMP_EN_CTL__comp_en_override_MASK 0x00000004L
++#define COMP_EN_CTL__comp_done_MASK 0x00000010L
++#define COMP_EN_CTL__zcal_code_override_MASK 0x00000040L
++#define COMP_EN_CTL__zcal_cal_rtt_MASK 0x00000080L
++#define COMP_EN_CTL__zcal_base_en_MASK 0x00000100L
++#define COMP_EN_CTL__zcal_ht_rtt_sel_MASK 0x00000200L
++#define COMP_EN_CTL__zcal_code_MASK 0x00007C00L
++#define COMP_EN_CTL__zcal_ron_cal_mode_MASK 0x00010000L
++#define COMP_EN_CTL__zcal_ana_dbg_sel_MASK 0x00060000L
++#define COMP_EN_CTL__cfg_cml_cmos_sel_MASK 0x00080000L
++#define COMP_EN_CTL__dsm_sel_MASK 0x00F00000L
++//COMP_EN_DFX
++#define COMP_EN_DFX__autocal_ron_code__SHIFT 0x0
++#define COMP_EN_DFX__autocal_rtt_code__SHIFT 0x5
++#define COMP_EN_DFX__pre_fused_ron_code__SHIFT 0xb
++#define COMP_EN_DFX__pre_fused_rtt_code__SHIFT 0x10
++#define COMP_EN_DFX__broadcast_ron_code__SHIFT 0x16
++#define COMP_EN_DFX__broadcast_rtt_code__SHIFT 0x1b
++#define COMP_EN_DFX__autocal_ron_code_MASK 0x0000001FL
++#define COMP_EN_DFX__autocal_rtt_code_MASK 0x000003E0L
++#define COMP_EN_DFX__pre_fused_ron_code_MASK 0x0000F800L
++#define COMP_EN_DFX__pre_fused_rtt_code_MASK 0x001F0000L
++#define COMP_EN_DFX__broadcast_ron_code_MASK 0x07C00000L
++#define COMP_EN_DFX__broadcast_rtt_code_MASK 0xF8000000L
++//ZCAL_FUSES
++#define ZCAL_FUSES__fuse_valid__SHIFT 0x0
++#define ZCAL_FUSES__fuse_ron_override_val__SHIFT 0x3
++#define ZCAL_FUSES__fuse_ron_ctl__SHIFT 0xa
++#define ZCAL_FUSES__fuse_rtt_override_val__SHIFT 0xd
++#define ZCAL_FUSES__fuse_rtt_ctl__SHIFT 0x14
++#define ZCAL_FUSES__fuse_refresh_cal_en__SHIFT 0x16
++#define ZCAL_FUSES__fuse_spare__SHIFT 0x17
++#define ZCAL_FUSES__fuse_valid_MASK 0x00000001L
++#define ZCAL_FUSES__fuse_ron_override_val_MASK 0x000001F8L
++#define ZCAL_FUSES__fuse_ron_ctl_MASK 0x00000C00L
++#define ZCAL_FUSES__fuse_rtt_override_val_MASK 0x0007E000L
++#define ZCAL_FUSES__fuse_rtt_ctl_MASK 0x00300000L
++#define ZCAL_FUSES__fuse_refresh_cal_en_MASK 0x00400000L
++#define ZCAL_FUSES__fuse_spare_MASK 0xFF800000L
++
++
++// addressBlock: dce_dc_dispdec_VGA_MEM_WRITE_PAGE_ADDR
++
++
++// addressBlock: dce_dc_dispdec_VGA_MEM_READ_PAGE_ADDR
++
++
++// addressBlock: dce_dc_dispdec[948..986]
++
++
++// addressBlock: dce_dc_azdec
++//CORB_WRITE_POINTER
++#define CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT 0x0
++#define CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK 0x00FFL
++//CORB_READ_POINTER
++#define CORB_READ_POINTER__CORB_READ_POINTER__SHIFT 0x0
++#define CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT 0xf
++#define CORB_READ_POINTER__CORB_READ_POINTER_MASK 0x00FFL
++#define CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK 0x8000L
++//CORB_CONTROL
++#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT 0x0
++#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT 0x1
++#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x01L
++#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK 0x02L
++//CORB_STATUS
++#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT 0x0
++#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK 0x01L
++//CORB_SIZE
++#define CORB_SIZE__CORB_SIZE__SHIFT 0x0
++#define CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT 0x4
++#define CORB_SIZE__CORB_SIZE_MASK 0x0003L
++#define CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 0x00F0L
++//RIRB_LOWER_BASE_ADDRESS
++#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0
++#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT 0x7
++#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x0000007FL
++#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L
++//RIRB_UPPER_BASE_ADDRESS
++#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT 0x0
++#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL
++//RIRB_WRITE_POINTER
++#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT 0x0
++#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT 0xf
++#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK 0x00FFL
++#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK 0x8000L
++//RESPONSE_INTERRUPT_COUNT
++#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT 0x0
++#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK 0x00FFL
++//RIRB_CONTROL
++#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT 0x0
++#define RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 0x1
++#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT 0x2
++#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK 0x01L
++#define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x02L
++#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK 0x04L
++//RIRB_STATUS
++#define RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 0x0
++#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT 0x2
++#define RIRB_STATUS__RESPONSE_INTERRUPT_MASK 0x01L
++#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK 0x04L
++//RIRB_SIZE
++#define RIRB_SIZE__RIRB_SIZE__SHIFT 0x0
++#define RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 0x4
++#define RIRB_SIZE__RIRB_SIZE_MASK 0x0003L
++#define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 0x00F0L
++//AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA
++#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
++#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL
++//AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX
++#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
++#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL
++//AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA
++#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
++#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL
++//AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX
++#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
++#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL
++//AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA
++#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
++#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL
++//AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX
++#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
++#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL
++//IMMEDIATE_COMMAND_OUTPUT_INTERFACE
++#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT 0x0
++#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT 0x1c
++#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK 0x0FFFFFFFL
++#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK 0xF0000000L
++//IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA
++#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
++#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL
++//IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX
++#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
++#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0000FFFFL
++//IMMEDIATE_RESPONSE_INPUT_INTERFACE
++#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT 0x0
++#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK 0xFFFFFFFFL
++//IMMEDIATE_COMMAND_STATUS
++#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT 0x0
++#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT 0x1
++#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK 0x00000001L
++#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK 0x00000002L
++//DMA_POSITION_LOWER_BASE_ADDRESS
++#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT 0x0
++#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x1
++#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT 0x7
++#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK 0x00000001L
++#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x0000007EL
++#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L
++//DMA_POSITION_UPPER_BASE_ADDRESS
++#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT 0x0
++#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL
++//WALL_CLOCK_COUNTER_ALIAS
++#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT 0x0
++#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_azstream0_azdec
++//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L
++//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL
++//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL
++//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL
++//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL
++//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L
++//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L
++//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL
++//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0
++#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_azstream1_azdec
++//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L
++//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL
++//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL
++//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL
++//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL
++//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L
++//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L
++//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL
++//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0
++#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_azstream2_azdec
++//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L
++//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL
++//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL
++//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL
++//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL
++//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L
++//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L
++//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL
++//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0
++#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_azstream3_azdec
++//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L
++//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL
++//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL
++//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL
++//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL
++//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L
++//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L
++//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL
++//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0
++#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_azstream4_azdec
++//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L
++//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL
++//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL
++//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL
++//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL
++//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L
++//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L
++//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL
++//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0
++#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_azstream5_azdec
++//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L
++//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL
++//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL
++//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL
++//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL
++//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L
++//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L
++//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL
++//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0
++#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_azstream6_azdec
++//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L
++//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL
++//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL
++//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL
++//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL
++//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L
++//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L
++//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL
++//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0
++#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_azstream7_azdec
++//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L
++//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL
++//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL
++//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL
++//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL
++//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L
++//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L
++//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL
++//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0
++#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL
++
++
++// addressBlock: azf0stream0_streamind
++//AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL
++#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
++#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
++#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
++#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
++#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
++#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
++//AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL
++#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
++#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
++//AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT
++#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
++#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
++//AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT
++#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
++#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
++//AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT
++#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
++#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
++
++
++// addressBlock: azf0stream1_streamind
++//AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL
++#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
++#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
++#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
++#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
++#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
++#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
++//AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL
++#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
++#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
++//AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT
++#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
++#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
++//AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT
++#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
++#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
++//AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT
++#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
++#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
++
++
++// addressBlock: azf0stream2_streamind
++//AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL
++#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
++#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
++#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
++#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
++#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
++#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
++//AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL
++#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
++#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
++//AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT
++#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
++#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
++//AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT
++#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
++#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
++//AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT
++#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
++#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
++
++
++// addressBlock: azf0stream3_streamind
++//AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL
++#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
++#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
++#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
++#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
++#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
++#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
++//AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL
++#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
++#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
++//AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT
++#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
++#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
++//AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT
++#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
++#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
++//AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT
++#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
++#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
++
++
++// addressBlock: azf0stream4_streamind
++//AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL
++#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
++#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
++#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
++#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
++#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
++#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
++//AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL
++#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
++#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
++//AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT
++#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
++#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
++//AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT
++#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
++#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
++//AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT
++#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
++#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
++
++
++// addressBlock: azf0stream5_streamind
++//AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL
++#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
++#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
++#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
++#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
++#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
++#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
++//AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL
++#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
++#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
++//AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT
++#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
++#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
++//AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT
++#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
++#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
++//AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT
++#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
++#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
++
++
++// addressBlock: azf0stream6_streamind
++//AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL
++#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
++#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
++#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
++#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
++#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
++#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
++//AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL
++#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
++#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
++//AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT
++#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
++#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
++//AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT
++#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
++#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
++//AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT
++#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
++#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
++
++
++// addressBlock: azf0stream7_streamind
++//AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL
++#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
++#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
++#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
++#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
++#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
++#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
++//AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL
++#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
++#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
++//AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT
++#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
++#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
++//AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT
++#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
++#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
++//AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT
++#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
++#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
++
++
++// addressBlock: azf0stream8_streamind
++//AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL
++#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
++#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
++#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
++#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
++#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
++#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
++//AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL
++#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
++#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
++//AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT
++#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
++#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
++//AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT
++#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
++#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
++//AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT
++#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
++#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
++
++
++// addressBlock: azf0stream9_streamind
++//AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL
++#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
++#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
++#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
++#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
++#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
++#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
++//AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL
++#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
++#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
++//AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT
++#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
++#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
++//AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT
++#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
++#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
++//AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT
++#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
++#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
++
++
++// addressBlock: azf0stream10_streamind
++//AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL
++#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
++#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
++#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
++#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
++#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
++#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
++//AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL
++#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
++#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
++//AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT
++#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
++#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
++//AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT
++#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
++#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
++//AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT
++#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
++#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
++
++
++// addressBlock: azf0stream11_streamind
++//AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL
++#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
++#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
++#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
++#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
++#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
++#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
++//AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL
++#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
++#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
++//AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT
++#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
++#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
++//AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT
++#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
++#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
++//AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT
++#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
++#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
++
++
++// addressBlock: azf0stream12_streamind
++//AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL
++#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
++#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
++#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
++#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
++#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
++#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
++//AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL
++#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
++#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
++//AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT
++#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
++#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
++//AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT
++#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
++#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
++//AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT
++#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
++#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
++
++
++// addressBlock: azf0stream13_streamind
++//AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL
++#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
++#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
++#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
++#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
++#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
++#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
++//AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL
++#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
++#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
++//AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT
++#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
++#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
++//AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT
++#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
++#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
++//AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT
++#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
++#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
++
++
++// addressBlock: azf0stream14_streamind
++//AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL
++#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
++#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
++#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
++#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
++#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
++#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
++//AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL
++#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
++#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
++//AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT
++#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
++#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
++//AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT
++#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
++#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
++//AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT
++#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
++#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
++
++
++// addressBlock: azf0stream15_streamind
++//AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL
++#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
++#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
++#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
++#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
++#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
++#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
++//AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL
++#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
++#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
++//AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT
++#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
++#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
++//AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT
++#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
++#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
++//AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT
++#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
++#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
++
++
++// addressBlock: azf0endpoint0_endpointind
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L
++//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL
++//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L
++//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L
++//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L
++//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L
++//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L
++//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
++//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L
++//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L
++//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS
++#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L
++//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
++#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4
++#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8
++#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L
++#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L
++#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L
++//AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
++#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4
++#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8
++#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L
++#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L
++#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L
++//AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
++#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4
++#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8
++#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L
++#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L
++#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L
++
++
++// addressBlock: azf0endpoint1_endpointind
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L
++//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL
++//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L
++//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L
++//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L
++//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L
++//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L
++//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
++//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L
++//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L
++//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS
++#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L
++//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
++#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4
++#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8
++#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L
++#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L
++#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L
++//AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
++#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4
++#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8
++#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L
++#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L
++#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L
++//AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
++#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4
++#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8
++#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L
++#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L
++#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L
++
++
++// addressBlock: azf0endpoint2_endpointind
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L
++//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL
++//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L
++//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L
++//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L
++//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L
++//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L
++//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
++//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L
++//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L
++//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS
++#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L
++//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
++#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4
++#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8
++#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L
++#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L
++#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L
++//AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
++#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4
++#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8
++#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L
++#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L
++#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L
++//AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
++#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4
++#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8
++#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L
++#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L
++#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L
++
++
++// addressBlock: azf0endpoint3_endpointind
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L
++//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL
++//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L
++//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L
++//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L
++//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L
++//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L
++//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
++//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L
++//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L
++//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS
++#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L
++//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
++#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4
++#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8
++#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L
++#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L
++#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L
++//AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
++#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4
++#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8
++#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L
++#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L
++#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L
++//AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
++#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4
++#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8
++#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L
++#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L
++#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L
++
++
++// addressBlock: azf0endpoint4_endpointind
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L
++//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL
++//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L
++//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L
++//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L
++//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L
++//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L
++//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
++//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L
++//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L
++//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS
++#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L
++//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
++#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4
++#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8
++#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L
++#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L
++#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L
++//AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
++#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4
++#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8
++#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L
++#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L
++#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L
++//AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
++#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4
++#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8
++#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L
++#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L
++#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L
++
++
++// addressBlock: azf0endpoint5_endpointind
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L
++//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL
++//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L
++//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L
++//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L
++//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L
++//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L
++//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
++//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L
++//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L
++//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS
++#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L
++//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
++#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4
++#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8
++#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L
++#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L
++#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L
++//AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
++#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4
++#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8
++#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L
++#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L
++#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L
++//AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
++#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4
++#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8
++#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L
++#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L
++#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L
++
++
++// addressBlock: azf0endpoint6_endpointind
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L
++//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL
++//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L
++//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L
++//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L
++//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L
++//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L
++//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
++//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L
++//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L
++//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS
++#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L
++//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
++#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4
++#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8
++#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L
++#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L
++#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L
++//AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
++#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4
++#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8
++#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L
++#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L
++#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L
++//AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
++#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4
++#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8
++#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L
++#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L
++#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L
++
++
++// addressBlock: azf0endpoint7_endpointind
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L
++//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL
++//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L
++//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L
++//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L
++//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L
++//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L
++//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
++//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L
++//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L
++//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS
++#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L
++//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
++#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4
++#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8
++#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L
++#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L
++#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L
++//AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
++#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4
++#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8
++#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L
++#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L
++#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L
++//AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
++#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4
++#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8
++#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L
++#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L
++#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L
++
++
++// addressBlock: azf0inputendpoint0_inputendpointind
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L
++
++
++// addressBlock: azf0inputendpoint1_inputendpointind
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L
++
++
++// addressBlock: azf0inputendpoint2_inputendpointind
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L
++
++
++// addressBlock: azf0inputendpoint3_inputendpointind
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L
++
++
++// addressBlock: azf0inputendpoint4_inputendpointind
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L
++
++
++// addressBlock: azf0inputendpoint5_inputendpointind
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L
++
++
++// addressBlock: azf0inputendpoint6_inputendpointind
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L
++
++
++// addressBlock: azf0inputendpoint7_inputendpointind
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L
++
++
++// addressBlock: f2codecind
++//AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID
++#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0
++#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xFFFFFFFFL
++//AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID
++#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0
++#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xFFFFFFFFL
++//AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT
++#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0
++#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xFFFFFFFFL
++//AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000FL
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000F0L
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L
++//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000FFL
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000FF00L
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00FF0000L
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xFF000000L
++//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK 0x000000FFL
++//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK 0x000000FFL
++//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK 0x000000FFL
++//AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x000000FFL
++//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L
++//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xFFFFFFFFL
++//AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xFFFFFFFFL
++//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
++//AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xFFFFFFFFL
++//AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3FFFFFFFL
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L
++//AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT 0xf
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK 0x00008000L
++//AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
++//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
++//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK 0x0000007FL
++//AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL
++#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
++#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L
++#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L
++//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT 0x7
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK 0x00000080L
++//AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL
++//AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L
++//AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
++//AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
++//AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
++//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK 0xFFFFFFFFL
++//AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL
++#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
++#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L
++//AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
++#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
++#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
++#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
++//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
++//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
++//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0x0000000FL
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0x000000F0L
++//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0x0000000FL
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0x000000F0L
++//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x0000003FL
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0x000000C0L
++//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT 0x8
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT 0x9
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT 0xa
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK 0x0000007FL
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK 0x00000100L
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK 0x00000200L
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK 0x0000FC00L
++//AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION
++#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL
++//AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO
++#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT 0x3
++#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT 0x7
++#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL_MASK 0x00000003L
++#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK 0x00000078L
++#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK 0x00000080L
++//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT 0x3
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK 0x00000007L
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK 0x00000078L
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
++//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK 0xFFFFFFFFL
++//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L
++//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000001L
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000002L
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x000000F0L
++//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00000001L
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00000002L
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x000000F0L
++//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x00000001L
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK 0x00000002L
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0x000000F0L
++//AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC
++#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
++#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL
++#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L
++//AZALIA_F2_CODEC_PIN_CONTROL_HBR
++#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x00000001L
++#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x00000010L
++//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK 0x000000FFL
++//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK 0xFFFFFFFFL
++//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000001L
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000002L
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L
++//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x00000001L
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x00000002L
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0x000000F0L
++//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x00000001L
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x00000002L
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0x000000F0L
++//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x00000001L
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x00000002L
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0x000000F0L
++//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L
++//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL
++//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L
++//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L
++//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L
++//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L
++//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L
++//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
++//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L
++//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L
++//AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO
++#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL
++//AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
++#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L
++//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
++#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
++#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
++#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
++//AZALIA_F2_CODEC_PIN_CONTROL_LPIB
++#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
++//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
++#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
++//AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE
++#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL
++//AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED
++#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
++#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
++#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L
++#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L
++#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L
++#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L
++//AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
++#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L
++//AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
++#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L
++#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L
++//AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
++//AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
++//AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK 0xFFFFFFFFL
++//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
++//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
++//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
++//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
++//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
++//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0x0000000FL
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0x000000F0L
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0x0000000FL
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0x000000F0L
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x0000003FL
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0x000000C0L
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00000001L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00000002L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x000000F0L
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE_MASK 0x00000001L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE_MASK 0x00000002L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE_MASK 0x00000001L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE_MASK 0x00000002L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID_MASK 0x000000F0L
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x00000001L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x00000010L
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000001L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000002L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x00000001L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x00000002L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0x000000F0L
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x00000001L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x00000002L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0x000000F0L
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x00000001L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x00000002L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0x000000F0L
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L_MASK 0xFFFFFFFFL
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H_MASK 0xFFFFFFFFL
++//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
++//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
++
++
++// addressBlock: descriptorind
++//AUDIO_DESCRIPTOR0
++#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L
++#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
++//AUDIO_DESCRIPTOR1
++#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L
++#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
++//AUDIO_DESCRIPTOR2
++#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L
++#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
++//AUDIO_DESCRIPTOR3
++#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L
++#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
++//AUDIO_DESCRIPTOR4
++#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L
++#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
++//AUDIO_DESCRIPTOR5
++#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L
++#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
++//AUDIO_DESCRIPTOR6
++#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L
++#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
++//AUDIO_DESCRIPTOR7
++#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L
++#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
++//AUDIO_DESCRIPTOR8
++#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L
++#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
++//AUDIO_DESCRIPTOR9
++#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L
++#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
++//AUDIO_DESCRIPTOR10
++#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L
++#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
++//AUDIO_DESCRIPTOR11
++#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L
++#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
++//AUDIO_DESCRIPTOR12
++#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L
++#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
++//AUDIO_DESCRIPTOR13
++#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L
++#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
++#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
++#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
++
++
++// addressBlock: sinkinfoind
++//AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID
++#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK 0x0000FFFFL
++//AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID
++#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK 0x0000FFFFL
++//AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN
++#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK 0x000000FFL
++//AZALIA_F2_CODEC_PIN_CONTROL_PORTID0
++#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK 0xFFFFFFFFL
++//AZALIA_F2_CODEC_PIN_CONTROL_PORTID1
++#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK 0xFFFFFFFFL
++//SINK_DESCRIPTION0
++#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION0__DESCRIPTION_MASK 0x000000FFL
++//SINK_DESCRIPTION1
++#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION1__DESCRIPTION_MASK 0x000000FFL
++//SINK_DESCRIPTION2
++#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION2__DESCRIPTION_MASK 0x000000FFL
++//SINK_DESCRIPTION3
++#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION3__DESCRIPTION_MASK 0x000000FFL
++//SINK_DESCRIPTION4
++#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION4__DESCRIPTION_MASK 0x000000FFL
++//SINK_DESCRIPTION5
++#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION5__DESCRIPTION_MASK 0x000000FFL
++//SINK_DESCRIPTION6
++#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION6__DESCRIPTION_MASK 0x000000FFL
++//SINK_DESCRIPTION7
++#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION7__DESCRIPTION_MASK 0x000000FFL
++//SINK_DESCRIPTION8
++#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION8__DESCRIPTION_MASK 0x000000FFL
++//SINK_DESCRIPTION9
++#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION9__DESCRIPTION_MASK 0x000000FFL
++//SINK_DESCRIPTION10
++#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION10__DESCRIPTION_MASK 0x000000FFL
++//SINK_DESCRIPTION11
++#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION11__DESCRIPTION_MASK 0x000000FFL
++//SINK_DESCRIPTION12
++#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION12__DESCRIPTION_MASK 0x000000FFL
++//SINK_DESCRIPTION13
++#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION13__DESCRIPTION_MASK 0x000000FFL
++//SINK_DESCRIPTION14
++#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION14__DESCRIPTION_MASK 0x000000FFL
++//SINK_DESCRIPTION15
++#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION15__DESCRIPTION_MASK 0x000000FFL
++//SINK_DESCRIPTION16
++#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION16__DESCRIPTION_MASK 0x000000FFL
++//SINK_DESCRIPTION17
++#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION17__DESCRIPTION_MASK 0x000000FFL
++
++
++// addressBlock: azinputcrc0resultind
++//AZALIA_INPUT_CRC0_CHANNEL0
++#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0
++#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xFFFFFFFFL
++//AZALIA_INPUT_CRC0_CHANNEL1
++#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0
++#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xFFFFFFFFL
++//AZALIA_INPUT_CRC0_CHANNEL2
++#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0
++#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xFFFFFFFFL
++//AZALIA_INPUT_CRC0_CHANNEL3
++#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0
++#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xFFFFFFFFL
++//AZALIA_INPUT_CRC0_CHANNEL4
++#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0
++#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xFFFFFFFFL
++//AZALIA_INPUT_CRC0_CHANNEL5
++#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0
++#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xFFFFFFFFL
++//AZALIA_INPUT_CRC0_CHANNEL6
++#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0
++#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xFFFFFFFFL
++//AZALIA_INPUT_CRC0_CHANNEL7
++#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0
++#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xFFFFFFFFL
++
++
++// addressBlock: azinputcrc1resultind
++//AZALIA_INPUT_CRC1_CHANNEL0
++#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0
++#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xFFFFFFFFL
++//AZALIA_INPUT_CRC1_CHANNEL1
++#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0
++#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xFFFFFFFFL
++//AZALIA_INPUT_CRC1_CHANNEL2
++#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0
++#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xFFFFFFFFL
++//AZALIA_INPUT_CRC1_CHANNEL3
++#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0
++#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xFFFFFFFFL
++//AZALIA_INPUT_CRC1_CHANNEL4
++#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0
++#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xFFFFFFFFL
++//AZALIA_INPUT_CRC1_CHANNEL5
++#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0
++#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xFFFFFFFFL
++//AZALIA_INPUT_CRC1_CHANNEL6
++#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0
++#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xFFFFFFFFL
++//AZALIA_INPUT_CRC1_CHANNEL7
++#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0
++#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xFFFFFFFFL
++
++
++// addressBlock: azcrc0resultind
++//AZALIA_CRC0_CHANNEL0
++#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0
++#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK 0xFFFFFFFFL
++//AZALIA_CRC0_CHANNEL1
++#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0
++#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK 0xFFFFFFFFL
++//AZALIA_CRC0_CHANNEL2
++#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0
++#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK 0xFFFFFFFFL
++//AZALIA_CRC0_CHANNEL3
++#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0
++#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK 0xFFFFFFFFL
++//AZALIA_CRC0_CHANNEL4
++#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0
++#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK 0xFFFFFFFFL
++//AZALIA_CRC0_CHANNEL5
++#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0
++#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK 0xFFFFFFFFL
++//AZALIA_CRC0_CHANNEL6
++#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0
++#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK 0xFFFFFFFFL
++//AZALIA_CRC0_CHANNEL7
++#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0
++#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK 0xFFFFFFFFL
++
++
++// addressBlock: azcrc1resultind
++//AZALIA_CRC1_CHANNEL0
++#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0
++#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK 0xFFFFFFFFL
++//AZALIA_CRC1_CHANNEL1
++#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0
++#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK 0xFFFFFFFFL
++//AZALIA_CRC1_CHANNEL2
++#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0
++#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK 0xFFFFFFFFL
++//AZALIA_CRC1_CHANNEL3
++#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0
++#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK 0xFFFFFFFFL
++//AZALIA_CRC1_CHANNEL4
++#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0
++#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK 0xFFFFFFFFL
++//AZALIA_CRC1_CHANNEL5
++#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0
++#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK 0xFFFFFFFFL
++//AZALIA_CRC1_CHANNEL6
++#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0
++#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK 0xFFFFFFFFL
++//AZALIA_CRC1_CHANNEL7
++#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0
++#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK 0xFFFFFFFFL
++
++
++// addressBlock: vgaseqind
++//SEQ00
++#define SEQ00__SEQ_RST0B__SHIFT 0x0
++#define SEQ00__SEQ_RST1B__SHIFT 0x1
++#define SEQ00__SEQ_RST0B_MASK 0x01L
++#define SEQ00__SEQ_RST1B_MASK 0x02L
++//SEQ01
++#define SEQ01__SEQ_DOT8__SHIFT 0x0
++#define SEQ01__SEQ_SHIFT2__SHIFT 0x2
++#define SEQ01__SEQ_PCLKBY2__SHIFT 0x3
++#define SEQ01__SEQ_SHIFT4__SHIFT 0x4
++#define SEQ01__SEQ_MAXBW__SHIFT 0x5
++#define SEQ01__SEQ_DOT8_MASK 0x01L
++#define SEQ01__SEQ_SHIFT2_MASK 0x04L
++#define SEQ01__SEQ_PCLKBY2_MASK 0x08L
++#define SEQ01__SEQ_SHIFT4_MASK 0x10L
++#define SEQ01__SEQ_MAXBW_MASK 0x20L
++//SEQ02
++#define SEQ02__SEQ_MAP0_EN__SHIFT 0x0
++#define SEQ02__SEQ_MAP1_EN__SHIFT 0x1
++#define SEQ02__SEQ_MAP2_EN__SHIFT 0x2
++#define SEQ02__SEQ_MAP3_EN__SHIFT 0x3
++#define SEQ02__SEQ_MAP0_EN_MASK 0x01L
++#define SEQ02__SEQ_MAP1_EN_MASK 0x02L
++#define SEQ02__SEQ_MAP2_EN_MASK 0x04L
++#define SEQ02__SEQ_MAP3_EN_MASK 0x08L
++//SEQ03
++#define SEQ03__SEQ_FONT_B1__SHIFT 0x0
++#define SEQ03__SEQ_FONT_B2__SHIFT 0x1
++#define SEQ03__SEQ_FONT_A1__SHIFT 0x2
++#define SEQ03__SEQ_FONT_A2__SHIFT 0x3
++#define SEQ03__SEQ_FONT_B0__SHIFT 0x4
++#define SEQ03__SEQ_FONT_A0__SHIFT 0x5
++#define SEQ03__SEQ_FONT_B1_MASK 0x01L
++#define SEQ03__SEQ_FONT_B2_MASK 0x02L
++#define SEQ03__SEQ_FONT_A1_MASK 0x04L
++#define SEQ03__SEQ_FONT_A2_MASK 0x08L
++#define SEQ03__SEQ_FONT_B0_MASK 0x10L
++#define SEQ03__SEQ_FONT_A0_MASK 0x20L
++//SEQ04
++#define SEQ04__SEQ_256K__SHIFT 0x1
++#define SEQ04__SEQ_ODDEVEN__SHIFT 0x2
++#define SEQ04__SEQ_CHAIN__SHIFT 0x3
++#define SEQ04__SEQ_256K_MASK 0x02L
++#define SEQ04__SEQ_ODDEVEN_MASK 0x04L
++#define SEQ04__SEQ_CHAIN_MASK 0x08L
++
++
++// addressBlock: vgacrtind
++//CRT00
++#define CRT00__H_TOTAL__SHIFT 0x0
++#define CRT00__H_TOTAL_MASK 0xFFL
++//CRT01
++#define CRT01__H_DISP_END__SHIFT 0x0
++#define CRT01__H_DISP_END_MASK 0xFFL
++//CRT02
++#define CRT02__H_BLANK_START__SHIFT 0x0
++#define CRT02__H_BLANK_START_MASK 0xFFL
++//CRT03
++#define CRT03__H_BLANK_END__SHIFT 0x0
++#define CRT03__H_DE_SKEW__SHIFT 0x5
++#define CRT03__CR10CR11_R_DIS_B__SHIFT 0x7
++#define CRT03__H_BLANK_END_MASK 0x1FL
++#define CRT03__H_DE_SKEW_MASK 0x60L
++#define CRT03__CR10CR11_R_DIS_B_MASK 0x80L
++//CRT04
++#define CRT04__H_SYNC_START__SHIFT 0x0
++#define CRT04__H_SYNC_START_MASK 0xFFL
++//CRT05
++#define CRT05__H_SYNC_END__SHIFT 0x0
++#define CRT05__H_SYNC_SKEW__SHIFT 0x5
++#define CRT05__H_BLANK_END_B5__SHIFT 0x7
++#define CRT05__H_SYNC_END_MASK 0x1FL
++#define CRT05__H_SYNC_SKEW_MASK 0x60L
++#define CRT05__H_BLANK_END_B5_MASK 0x80L
++//CRT06
++#define CRT06__V_TOTAL__SHIFT 0x0
++#define CRT06__V_TOTAL_MASK 0xFFL
++//CRT07
++#define CRT07__V_TOTAL_B8__SHIFT 0x0
++#define CRT07__V_DISP_END_B8__SHIFT 0x1
++#define CRT07__V_SYNC_START_B8__SHIFT 0x2
++#define CRT07__V_BLANK_START_B8__SHIFT 0x3
++#define CRT07__LINE_CMP_B8__SHIFT 0x4
++#define CRT07__V_TOTAL_B9__SHIFT 0x5
++#define CRT07__V_DISP_END_B9__SHIFT 0x6
++#define CRT07__V_SYNC_START_B9__SHIFT 0x7
++#define CRT07__V_TOTAL_B8_MASK 0x01L
++#define CRT07__V_DISP_END_B8_MASK 0x02L
++#define CRT07__V_SYNC_START_B8_MASK 0x04L
++#define CRT07__V_BLANK_START_B8_MASK 0x08L
++#define CRT07__LINE_CMP_B8_MASK 0x10L
++#define CRT07__V_TOTAL_B9_MASK 0x20L
++#define CRT07__V_DISP_END_B9_MASK 0x40L
++#define CRT07__V_SYNC_START_B9_MASK 0x80L
++//CRT08
++#define CRT08__ROW_SCAN_START__SHIFT 0x0
++#define CRT08__BYTE_PAN__SHIFT 0x5
++#define CRT08__ROW_SCAN_START_MASK 0x1FL
++#define CRT08__BYTE_PAN_MASK 0x60L
++//CRT09
++#define CRT09__MAX_ROW_SCAN__SHIFT 0x0
++#define CRT09__V_BLANK_START_B9__SHIFT 0x5
++#define CRT09__LINE_CMP_B9__SHIFT 0x6
++#define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT 0x7
++#define CRT09__MAX_ROW_SCAN_MASK 0x1FL
++#define CRT09__V_BLANK_START_B9_MASK 0x20L
++#define CRT09__LINE_CMP_B9_MASK 0x40L
++#define CRT09__DOUBLE_CHAR_HEIGHT_MASK 0x80L
++//CRT0A
++#define CRT0A__CURSOR_START__SHIFT 0x0
++#define CRT0A__CURSOR_DISABLE__SHIFT 0x5
++#define CRT0A__CURSOR_START_MASK 0x1FL
++#define CRT0A__CURSOR_DISABLE_MASK 0x20L
++//CRT0B
++#define CRT0B__CURSOR_END__SHIFT 0x0
++#define CRT0B__CURSOR_SKEW__SHIFT 0x5
++#define CRT0B__CURSOR_END_MASK 0x1FL
++#define CRT0B__CURSOR_SKEW_MASK 0x60L
++//CRT0C
++#define CRT0C__DISP_START__SHIFT 0x0
++#define CRT0C__DISP_START_MASK 0xFFL
++//CRT0D
++#define CRT0D__DISP_START__SHIFT 0x0
++#define CRT0D__DISP_START_MASK 0xFFL
++//CRT0E
++#define CRT0E__CURSOR_LOC_HI__SHIFT 0x0
++#define CRT0E__CURSOR_LOC_HI_MASK 0xFFL
++//CRT0F
++#define CRT0F__CURSOR_LOC_LO__SHIFT 0x0
++#define CRT0F__CURSOR_LOC_LO_MASK 0xFFL
++//CRT10
++#define CRT10__V_SYNC_START__SHIFT 0x0
++#define CRT10__V_SYNC_START_MASK 0xFFL
++//CRT11
++#define CRT11__V_SYNC_END__SHIFT 0x0
++#define CRT11__V_INTR_CLR__SHIFT 0x4
++#define CRT11__V_INTR_EN__SHIFT 0x5
++#define CRT11__SEL5_REFRESH_CYC__SHIFT 0x6
++#define CRT11__C0T7_WR_ONLY__SHIFT 0x7
++#define CRT11__V_SYNC_END_MASK 0x0FL
++#define CRT11__V_INTR_CLR_MASK 0x10L
++#define CRT11__V_INTR_EN_MASK 0x20L
++#define CRT11__SEL5_REFRESH_CYC_MASK 0x40L
++#define CRT11__C0T7_WR_ONLY_MASK 0x80L
++//CRT12
++#define CRT12__V_DISP_END__SHIFT 0x0
++#define CRT12__V_DISP_END_MASK 0xFFL
++//CRT13
++#define CRT13__DISP_PITCH__SHIFT 0x0
++#define CRT13__DISP_PITCH_MASK 0xFFL
++//CRT14
++#define CRT14__UNDRLN_LOC__SHIFT 0x0
++#define CRT14__ADDR_CNT_BY4__SHIFT 0x5
++#define CRT14__DOUBLE_WORD__SHIFT 0x6
++#define CRT14__UNDRLN_LOC_MASK 0x1FL
++#define CRT14__ADDR_CNT_BY4_MASK 0x20L
++#define CRT14__DOUBLE_WORD_MASK 0x40L
++//CRT15
++#define CRT15__V_BLANK_START__SHIFT 0x0
++#define CRT15__V_BLANK_START_MASK 0xFFL
++//CRT16
++#define CRT16__V_BLANK_END__SHIFT 0x0
++#define CRT16__V_BLANK_END_MASK 0xFFL
++//CRT17
++#define CRT17__RA0_AS_A13B__SHIFT 0x0
++#define CRT17__RA1_AS_A14B__SHIFT 0x1
++#define CRT17__VCOUNT_BY2__SHIFT 0x2
++#define CRT17__ADDR_CNT_BY2__SHIFT 0x3
++#define CRT17__WRAP_A15TOA0__SHIFT 0x5
++#define CRT17__BYTE_MODE__SHIFT 0x6
++#define CRT17__CRTC_SYNC_EN__SHIFT 0x7
++#define CRT17__RA0_AS_A13B_MASK 0x01L
++#define CRT17__RA1_AS_A14B_MASK 0x02L
++#define CRT17__VCOUNT_BY2_MASK 0x04L
++#define CRT17__ADDR_CNT_BY2_MASK 0x08L
++#define CRT17__WRAP_A15TOA0_MASK 0x20L
++#define CRT17__BYTE_MODE_MASK 0x40L
++#define CRT17__CRTC_SYNC_EN_MASK 0x80L
++//CRT18
++#define CRT18__LINE_CMP__SHIFT 0x0
++#define CRT18__LINE_CMP_MASK 0xFFL
++//CRT1E
++#define CRT1E__GRPH_DEC_RD1__SHIFT 0x1
++#define CRT1E__GRPH_DEC_RD1_MASK 0x02L
++//CRT1F
++#define CRT1F__GRPH_DEC_RD0__SHIFT 0x0
++#define CRT1F__GRPH_DEC_RD0_MASK 0xFFL
++//CRT22
++#define CRT22__GRPH_LATCH_DATA__SHIFT 0x0
++#define CRT22__GRPH_LATCH_DATA_MASK 0xFFL
++
++
++// addressBlock: vgagrphind
++//GRA00
++#define GRA00__GRPH_SET_RESET0__SHIFT 0x0
++#define GRA00__GRPH_SET_RESET1__SHIFT 0x1
++#define GRA00__GRPH_SET_RESET2__SHIFT 0x2
++#define GRA00__GRPH_SET_RESET3__SHIFT 0x3
++#define GRA00__GRPH_SET_RESET0_MASK 0x01L
++#define GRA00__GRPH_SET_RESET1_MASK 0x02L
++#define GRA00__GRPH_SET_RESET2_MASK 0x04L
++#define GRA00__GRPH_SET_RESET3_MASK 0x08L
++//GRA01
++#define GRA01__GRPH_SET_RESET_ENA0__SHIFT 0x0
++#define GRA01__GRPH_SET_RESET_ENA1__SHIFT 0x1
++#define GRA01__GRPH_SET_RESET_ENA2__SHIFT 0x2
++#define GRA01__GRPH_SET_RESET_ENA3__SHIFT 0x3
++#define GRA01__GRPH_SET_RESET_ENA0_MASK 0x01L
++#define GRA01__GRPH_SET_RESET_ENA1_MASK 0x02L
++#define GRA01__GRPH_SET_RESET_ENA2_MASK 0x04L
++#define GRA01__GRPH_SET_RESET_ENA3_MASK 0x08L
++//GRA02
++#define GRA02__GRPH_CCOMP__SHIFT 0x0
++#define GRA02__GRPH_CCOMP_MASK 0x0FL
++//GRA03
++#define GRA03__GRPH_ROTATE__SHIFT 0x0
++#define GRA03__GRPH_FN_SEL__SHIFT 0x3
++#define GRA03__GRPH_ROTATE_MASK 0x07L
++#define GRA03__GRPH_FN_SEL_MASK 0x18L
++//GRA04
++#define GRA04__GRPH_RMAP__SHIFT 0x0
++#define GRA04__GRPH_RMAP_MASK 0x03L
++//GRA05
++#define GRA05__GRPH_WRITE_MODE__SHIFT 0x0
++#define GRA05__GRPH_READ1__SHIFT 0x3
++#define GRA05__CGA_ODDEVEN__SHIFT 0x4
++#define GRA05__GRPH_OES__SHIFT 0x5
++#define GRA05__GRPH_PACK__SHIFT 0x6
++#define GRA05__GRPH_WRITE_MODE_MASK 0x03L
++#define GRA05__GRPH_READ1_MASK 0x08L
++#define GRA05__CGA_ODDEVEN_MASK 0x10L
++#define GRA05__GRPH_OES_MASK 0x20L
++#define GRA05__GRPH_PACK_MASK 0x40L
++//GRA06
++#define GRA06__GRPH_GRAPHICS__SHIFT 0x0
++#define GRA06__GRPH_ODDEVEN__SHIFT 0x1
++#define GRA06__GRPH_ADRSEL__SHIFT 0x2
++#define GRA06__GRPH_GRAPHICS_MASK 0x01L
++#define GRA06__GRPH_ODDEVEN_MASK 0x02L
++#define GRA06__GRPH_ADRSEL_MASK 0x0CL
++//GRA07
++#define GRA07__GRPH_XCARE0__SHIFT 0x0
++#define GRA07__GRPH_XCARE1__SHIFT 0x1
++#define GRA07__GRPH_XCARE2__SHIFT 0x2
++#define GRA07__GRPH_XCARE3__SHIFT 0x3
++#define GRA07__GRPH_XCARE0_MASK 0x01L
++#define GRA07__GRPH_XCARE1_MASK 0x02L
++#define GRA07__GRPH_XCARE2_MASK 0x04L
++#define GRA07__GRPH_XCARE3_MASK 0x08L
++//GRA08
++#define GRA08__GRPH_BMSK__SHIFT 0x0
++#define GRA08__GRPH_BMSK_MASK 0xFFL
++
++
++// addressBlock: vgaattrind
++//ATTR00
++#define ATTR00__ATTR_PAL__SHIFT 0x0
++#define ATTR00__ATTR_PAL_MASK 0x3FL
++//ATTR01
++#define ATTR01__ATTR_PAL__SHIFT 0x0
++#define ATTR01__ATTR_PAL_MASK 0x3FL
++//ATTR02
++#define ATTR02__ATTR_PAL__SHIFT 0x0
++#define ATTR02__ATTR_PAL_MASK 0x3FL
++//ATTR03
++#define ATTR03__ATTR_PAL__SHIFT 0x0
++#define ATTR03__ATTR_PAL_MASK 0x3FL
++//ATTR04
++#define ATTR04__ATTR_PAL__SHIFT 0x0
++#define ATTR04__ATTR_PAL_MASK 0x3FL
++//ATTR05
++#define ATTR05__ATTR_PAL__SHIFT 0x0
++#define ATTR05__ATTR_PAL_MASK 0x3FL
++//ATTR06
++#define ATTR06__ATTR_PAL__SHIFT 0x0
++#define ATTR06__ATTR_PAL_MASK 0x3FL
++//ATTR07
++#define ATTR07__ATTR_PAL__SHIFT 0x0
++#define ATTR07__ATTR_PAL_MASK 0x3FL
++//ATTR08
++#define ATTR08__ATTR_PAL__SHIFT 0x0
++#define ATTR08__ATTR_PAL_MASK 0x3FL
++//ATTR09
++#define ATTR09__ATTR_PAL__SHIFT 0x0
++#define ATTR09__ATTR_PAL_MASK 0x3FL
++//ATTR0A
++#define ATTR0A__ATTR_PAL__SHIFT 0x0
++#define ATTR0A__ATTR_PAL_MASK 0x3FL
++//ATTR0B
++#define ATTR0B__ATTR_PAL__SHIFT 0x0
++#define ATTR0B__ATTR_PAL_MASK 0x3FL
++//ATTR0C
++#define ATTR0C__ATTR_PAL__SHIFT 0x0
++#define ATTR0C__ATTR_PAL_MASK 0x3FL
++//ATTR0D
++#define ATTR0D__ATTR_PAL__SHIFT 0x0
++#define ATTR0D__ATTR_PAL_MASK 0x3FL
++//ATTR0E
++#define ATTR0E__ATTR_PAL__SHIFT 0x0
++#define ATTR0E__ATTR_PAL_MASK 0x3FL
++//ATTR0F
++#define ATTR0F__ATTR_PAL__SHIFT 0x0
++#define ATTR0F__ATTR_PAL_MASK 0x3FL
++//ATTR10
++#define ATTR10__ATTR_GRPH_MODE__SHIFT 0x0
++#define ATTR10__ATTR_MONO_EN__SHIFT 0x1
++#define ATTR10__ATTR_LGRPH_EN__SHIFT 0x2
++#define ATTR10__ATTR_BLINK_EN__SHIFT 0x3
++#define ATTR10__ATTR_PANTOPONLY__SHIFT 0x5
++#define ATTR10__ATTR_PCLKBY2__SHIFT 0x6
++#define ATTR10__ATTR_CSEL_EN__SHIFT 0x7
++#define ATTR10__ATTR_GRPH_MODE_MASK 0x01L
++#define ATTR10__ATTR_MONO_EN_MASK 0x02L
++#define ATTR10__ATTR_LGRPH_EN_MASK 0x04L
++#define ATTR10__ATTR_BLINK_EN_MASK 0x08L
++#define ATTR10__ATTR_PANTOPONLY_MASK 0x20L
++#define ATTR10__ATTR_PCLKBY2_MASK 0x40L
++#define ATTR10__ATTR_CSEL_EN_MASK 0x80L
++//ATTR11
++#define ATTR11__ATTR_OVSC__SHIFT 0x0
++#define ATTR11__ATTR_OVSC_MASK 0xFFL
++//ATTR12
++#define ATTR12__ATTR_MAP_EN__SHIFT 0x0
++#define ATTR12__ATTR_VSMUX__SHIFT 0x4
++#define ATTR12__ATTR_MAP_EN_MASK 0x0FL
++#define ATTR12__ATTR_VSMUX_MASK 0x30L
++//ATTR13
++#define ATTR13__ATTR_PPAN__SHIFT 0x0
++#define ATTR13__ATTR_PPAN_MASK 0x0FL
++//ATTR14
++#define ATTR14__ATTR_CSEL1__SHIFT 0x0
++#define ATTR14__ATTR_CSEL2__SHIFT 0x2
++#define ATTR14__ATTR_CSEL1_MASK 0x03L
++#define ATTR14__ATTR_CSEL2_MASK 0x0CL
++
++
++#endif
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_default.h
+deleted file mode 100644
+index 8a0007c..0000000
+--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_default.h
++++ /dev/null
+@@ -1,9868 +0,0 @@
+-/*
+- * Copyright (C) 2017 Advanced Micro Devices, Inc.
+- *
+- * Permission is hereby granted, free of charge, to any person obtaining a
+- * copy of this software and associated documentation files (the "Software"),
+- * to deal in the Software without restriction, including without limitation
+- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+- * and/or sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following conditions:
+- *
+- * The above copyright notice and this permission notice shall be included
+- * in all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+- */
+-#ifndef _dce_12_0_DEFAULT_HEADER
+-#define _dce_12_0_DEFAULT_HEADER
+-
+-
+-// addressBlock: dce_dc_dispdec_VGA_MEM_WRITE_PAGE_ADDR
+-#define mmdispdec_VGA_MEM_WRITE_PAGE_ADDR_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dispdec_VGA_MEM_READ_PAGE_ADDR
+-#define mmdispdec_VGA_MEM_READ_PAGE_ADDR_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dc_perfmon0_dispdec
+-#define mmDC_PERFMON0_PERFCOUNTER_CNTL_DEFAULT 0x00000000
+-#define mmDC_PERFMON0_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
+-#define mmDC_PERFMON0_PERFCOUNTER_STATE_DEFAULT 0x00000000
+-#define mmDC_PERFMON0_PERFMON_CNTL_DEFAULT 0x00000100
+-#define mmDC_PERFMON0_PERFMON_CNTL2_DEFAULT 0x00000000
+-#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
+-#define mmDC_PERFMON0_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
+-#define mmDC_PERFMON0_PERFMON_HI_DEFAULT 0x00000000
+-#define mmDC_PERFMON0_PERFMON_LOW_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dc_perfmon13_dispdec
+-#define mmDC_PERFMON13_PERFCOUNTER_CNTL_DEFAULT 0x00000000
+-#define mmDC_PERFMON13_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
+-#define mmDC_PERFMON13_PERFCOUNTER_STATE_DEFAULT 0x00000000
+-#define mmDC_PERFMON13_PERFMON_CNTL_DEFAULT 0x00000100
+-#define mmDC_PERFMON13_PERFMON_CNTL2_DEFAULT 0x00000000
+-#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
+-#define mmDC_PERFMON13_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
+-#define mmDC_PERFMON13_PERFMON_HI_DEFAULT 0x00000000
+-#define mmDC_PERFMON13_PERFMON_LOW_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dc_displaypllregs_dispdec
+-#define mmPPLL_VREG_CFG_DEFAULT 0x00000000
+-#define mmPPLL_MODE_CNTL_DEFAULT 0x00020100
+-#define mmPPLL_FREQ_CTRL0_DEFAULT 0x00280000
+-#define mmPPLL_FREQ_CTRL1_DEFAULT 0x00000000
+-#define mmPPLL_FREQ_CTRL2_DEFAULT 0x00000000
+-#define mmPPLL_FREQ_CTRL3_DEFAULT 0x00190040
+-#define mmPPLL_BW_CTRL_COARSE_DEFAULT 0x0020c4b1
+-#define mmPPLL_BW_CTRL_FINE_DEFAULT 0x00000001
+-#define mmPPLL_CAL_CTRL_DEFAULT 0x64000002
+-#define mmPPLL_LOOP_CTRL_DEFAULT 0x00000090
+-#define mmPPLL_REFCLK_CNTL_DEFAULT 0x00018004
+-#define mmPPLL_CLKOUT_CNTL_DEFAULT 0x00022500
+-#define mmPPLL_DFT_CNTL_DEFAULT 0x00000004
+-#define mmPPLL_ANALOG_CNTL_DEFAULT 0x00000000
+-#define mmPPLL_POSTDIV_DEFAULT 0x00000400
+-#define mmPPLL_OBSERVE0_DEFAULT 0x00000000
+-#define mmPPLL_OBSERVE1_DEFAULT 0x04b00000
+-#define mmPPLL_UPDATE_CNTL_DEFAULT 0x00000000
+-#define mmPPLL_OBSERVE0_OUT_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dccg_pll0_dispdec
+-#define mmPLL_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000
+-#define mmPLL_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dc_perfmon1_dispdec
+-#define mmDC_PERFMON1_PERFCOUNTER_CNTL_DEFAULT 0x00000000
+-#define mmDC_PERFMON1_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
+-#define mmDC_PERFMON1_PERFCOUNTER_STATE_DEFAULT 0x00000000
+-#define mmDC_PERFMON1_PERFMON_CNTL_DEFAULT 0x00000100
+-#define mmDC_PERFMON1_PERFMON_CNTL2_DEFAULT 0x00000000
+-#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
+-#define mmDC_PERFMON1_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
+-#define mmDC_PERFMON1_PERFMON_HI_DEFAULT 0x00000000
+-#define mmDC_PERFMON1_PERFMON_LOW_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_mcif_wb0_dispdec
+-#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL_DEFAULT 0x00000000
+-#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R_DEFAULT 0x00000000
+-#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS_DEFAULT 0x00000000
+-#define mmMCIF_WB0_MCIF_WB_BUF_PITCH_DEFAULT 0x04000400
+-#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS_DEFAULT 0x00000000
+-#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2_DEFAULT 0x00000000
+-#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS_DEFAULT 0x00000000
+-#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2_DEFAULT 0x00000000
+-#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS_DEFAULT 0x00000000
+-#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2_DEFAULT 0x00000000
+-#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS_DEFAULT 0x00000000
+-#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2_DEFAULT 0x00000000
+-#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL_DEFAULT 0x00000000
+-#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE_DEFAULT 0x00000008
+-#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_DEFAULT 0x00000000
+-#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET_DEFAULT 0x00000000
+-#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_DEFAULT 0x00000000
+-#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET_DEFAULT 0x00000000
+-#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_DEFAULT 0x00000000
+-#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET_DEFAULT 0x00000000
+-#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_DEFAULT 0x00000000
+-#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET_DEFAULT 0x00000000
+-#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_DEFAULT 0x00000000
+-#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET_DEFAULT 0x00000000
+-#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_DEFAULT 0x00000000
+-#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET_DEFAULT 0x00000000
+-#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_DEFAULT 0x00000000
+-#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET_DEFAULT 0x00000000
+-#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_DEFAULT 0x00000000
+-#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET_DEFAULT 0x00000000
+-#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL_DEFAULT 0x000f0000
+-#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_DEFAULT 0x00000000
+-#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_DEFAULT 0x00000040
+-#define mmMCIF_WB0_MCIF_WB_WATERMARK_DEFAULT 0x00000000
+-#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL_DEFAULT 0x00000000
+-#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL_DEFAULT 0x00001000
+-#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_DEFAULT 0x00000002
+-#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL_DEFAULT 0x00000080
+-#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE_DEFAULT 0x000fffff
+-#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE_DEFAULT 0x000fffff
+-
+-
+-// addressBlock: dce_dc_mcif_wb1_dispdec
+-#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL_DEFAULT 0x00000000
+-#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R_DEFAULT 0x00000000
+-#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS_DEFAULT 0x00000000
+-#define mmMCIF_WB1_MCIF_WB_BUF_PITCH_DEFAULT 0x04000400
+-#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS_DEFAULT 0x00000000
+-#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2_DEFAULT 0x00000000
+-#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS_DEFAULT 0x00000000
+-#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2_DEFAULT 0x00000000
+-#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS_DEFAULT 0x00000000
+-#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2_DEFAULT 0x00000000
+-#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS_DEFAULT 0x00000000
+-#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2_DEFAULT 0x00000000
+-#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL_DEFAULT 0x00000000
+-#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE_DEFAULT 0x00000008
+-#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_DEFAULT 0x00000000
+-#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET_DEFAULT 0x00000000
+-#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_DEFAULT 0x00000000
+-#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET_DEFAULT 0x00000000
+-#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_DEFAULT 0x00000000
+-#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET_DEFAULT 0x00000000
+-#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_DEFAULT 0x00000000
+-#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET_DEFAULT 0x00000000
+-#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_DEFAULT 0x00000000
+-#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET_DEFAULT 0x00000000
+-#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_DEFAULT 0x00000000
+-#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET_DEFAULT 0x00000000
+-#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_DEFAULT 0x00000000
+-#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET_DEFAULT 0x00000000
+-#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_DEFAULT 0x00000000
+-#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET_DEFAULT 0x00000000
+-#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL_DEFAULT 0x000f0000
+-#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_DEFAULT 0x00000000
+-#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_DEFAULT 0x00000040
+-#define mmMCIF_WB1_MCIF_WB_WATERMARK_DEFAULT 0x00000000
+-#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL_DEFAULT 0x00000000
+-#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL_DEFAULT 0x00001000
+-#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL_DEFAULT 0x00000002
+-#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL_DEFAULT 0x00000080
+-#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE_DEFAULT 0x000fffff
+-#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE_DEFAULT 0x000fffff
+-
+-
+-// addressBlock: dce_dc_mcif_wb2_dispdec
+-#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL_DEFAULT 0x00000000
+-#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R_DEFAULT 0x00000000
+-#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS_DEFAULT 0x00000000
+-#define mmMCIF_WB2_MCIF_WB_BUF_PITCH_DEFAULT 0x04000400
+-#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS_DEFAULT 0x00000000
+-#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2_DEFAULT 0x00000000
+-#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS_DEFAULT 0x00000000
+-#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2_DEFAULT 0x00000000
+-#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS_DEFAULT 0x00000000
+-#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2_DEFAULT 0x00000000
+-#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS_DEFAULT 0x00000000
+-#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2_DEFAULT 0x00000000
+-#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL_DEFAULT 0x00000000
+-#define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE_DEFAULT 0x00000008
+-#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_DEFAULT 0x00000000
+-#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET_DEFAULT 0x00000000
+-#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_DEFAULT 0x00000000
+-#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET_DEFAULT 0x00000000
+-#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_DEFAULT 0x00000000
+-#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET_DEFAULT 0x00000000
+-#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_DEFAULT 0x00000000
+-#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET_DEFAULT 0x00000000
+-#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_DEFAULT 0x00000000
+-#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET_DEFAULT 0x00000000
+-#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_DEFAULT 0x00000000
+-#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET_DEFAULT 0x00000000
+-#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_DEFAULT 0x00000000
+-#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET_DEFAULT 0x00000000
+-#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_DEFAULT 0x00000000
+-#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET_DEFAULT 0x00000000
+-#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL_DEFAULT 0x000f0000
+-#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_DEFAULT 0x00000000
+-#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL_DEFAULT 0x00000040
+-#define mmMCIF_WB2_MCIF_WB_WATERMARK_DEFAULT 0x00000000
+-#define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL_DEFAULT 0x00000000
+-#define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL_DEFAULT 0x00001000
+-#define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL_DEFAULT 0x00000002
+-#define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL_DEFAULT 0x00000080
+-#define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE_DEFAULT 0x000fffff
+-#define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE_DEFAULT 0x000fffff
+-
+-
+-// addressBlock: dce_dc_cwb0_dispdec
+-#define mmCWB0_CWB_CTRL_DEFAULT 0x00000110
+-#define mmCWB0_CWB_FENCE_PAR0_DEFAULT 0x03ff03ff
+-#define mmCWB0_CWB_FENCE_PAR1_DEFAULT 0x000102ff
+-#define mmCWB0_CWB_CRC_CTRL_DEFAULT 0x00000000
+-#define mmCWB0_CWB_CRC_RED_GREEN_MASK_DEFAULT 0xffffffff
+-#define mmCWB0_CWB_CRC_BLUE_MASK_DEFAULT 0x0000ffff
+-#define mmCWB0_CWB_CRC_RED_GREEN_RESULT_DEFAULT 0x00000000
+-#define mmCWB0_CWB_CRC_BLUE_RESULT_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_cwb1_dispdec
+-#define mmCWB1_CWB_CTRL_DEFAULT 0x00000110
+-#define mmCWB1_CWB_FENCE_PAR0_DEFAULT 0x03ff03ff
+-#define mmCWB1_CWB_FENCE_PAR1_DEFAULT 0x000102ff
+-#define mmCWB1_CWB_CRC_CTRL_DEFAULT 0x00000000
+-#define mmCWB1_CWB_CRC_RED_GREEN_MASK_DEFAULT 0xffffffff
+-#define mmCWB1_CWB_CRC_BLUE_MASK_DEFAULT 0x0000ffff
+-#define mmCWB1_CWB_CRC_RED_GREEN_RESULT_DEFAULT 0x00000000
+-#define mmCWB1_CWB_CRC_BLUE_RESULT_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dc_perfmon9_dispdec
+-#define mmDC_PERFMON9_PERFCOUNTER_CNTL_DEFAULT 0x00000000
+-#define mmDC_PERFMON9_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
+-#define mmDC_PERFMON9_PERFCOUNTER_STATE_DEFAULT 0x00000000
+-#define mmDC_PERFMON9_PERFMON_CNTL_DEFAULT 0x00000100
+-#define mmDC_PERFMON9_PERFMON_CNTL2_DEFAULT 0x00000000
+-#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
+-#define mmDC_PERFMON9_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
+-#define mmDC_PERFMON9_PERFMON_HI_DEFAULT 0x00000000
+-#define mmDC_PERFMON9_PERFMON_LOW_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dispdec
+-#define mmVGA_MEM_WRITE_PAGE_ADDR_DEFAULT 0x00000000
+-#define mmVGA_MEM_READ_PAGE_ADDR_DEFAULT 0x00000000
+-#define mmVGA_RENDER_CONTROL_DEFAULT 0x0000000f
+-#define mmVGA_SEQUENCER_RESET_CONTROL_DEFAULT 0x00003f3f
+-#define mmVGA_MODE_CONTROL_DEFAULT 0x00000000
+-#define mmVGA_SURFACE_PITCH_SELECT_DEFAULT 0x00000002
+-#define mmVGA_MEMORY_BASE_ADDRESS_DEFAULT 0x00000000
+-#define mmVGA_DISPBUF1_SURFACE_ADDR_DEFAULT 0x00000000
+-#define mmVGA_DISPBUF2_SURFACE_ADDR_DEFAULT 0x00000000
+-#define mmVGA_MEMORY_BASE_ADDRESS_HIGH_DEFAULT 0x00000000
+-#define mmVGA_HDP_CONTROL_DEFAULT 0x00000000
+-#define mmVGA_CACHE_CONTROL_DEFAULT 0x00000000
+-#define mmD1VGA_CONTROL_DEFAULT 0x00000000
+-#define mmD2VGA_CONTROL_DEFAULT 0x00000000
+-#define mmVGA_STATUS_DEFAULT 0x00000000
+-#define mmVGA_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmVGA_STATUS_CLEAR_DEFAULT 0x00000000
+-#define mmVGA_INTERRUPT_STATUS_DEFAULT 0x00000000
+-#define mmVGA_MAIN_CONTROL_DEFAULT 0x00005018
+-#define mmVGA_TEST_CONTROL_DEFAULT 0x00000000
+-#define mmVGA_QOS_CTRL_DEFAULT 0x00000000
+-#define mmCRTC8_IDX_DEFAULT 0x00000000
+-#define mmCRTC8_DATA_DEFAULT 0x00000000
+-#define mmGENFC_WT_DEFAULT 0x00000000
+-#define mmGENS1_DEFAULT 0x00000000
+-#define mmATTRDW_DEFAULT 0x00000000
+-#define mmATTRX_DEFAULT 0x00000000
+-#define mmATTRDR_DEFAULT 0x00000000
+-#define mmGENMO_WT_DEFAULT 0x00000000
+-#define mmGENS0_DEFAULT 0x00000000
+-#define mmGENENB_DEFAULT 0x00000000
+-#define mmSEQ8_IDX_DEFAULT 0x00000000
+-#define mmSEQ8_DATA_DEFAULT 0x00000000
+-#define mmDAC_MASK_DEFAULT 0x00000000
+-#define mmDAC_R_INDEX_DEFAULT 0x00000000
+-#define mmDAC_W_INDEX_DEFAULT 0x00000000
+-#define mmDAC_DATA_DEFAULT 0x00000000
+-#define mmGENFC_RD_DEFAULT 0x00000000
+-#define mmGENMO_RD_DEFAULT 0x00000000
+-#define mmGRPH8_IDX_DEFAULT 0x00000000
+-#define mmGRPH8_DATA_DEFAULT 0x00000000
+-#define mmCRTC8_IDX_1_DEFAULT 0x00000000
+-#define mmCRTC8_DATA_1_DEFAULT 0x00000000
+-#define mmGENFC_WT_1_DEFAULT 0x00000000
+-#define mmGENS1_1_DEFAULT 0x00000000
+-#define mmD3VGA_CONTROL_DEFAULT 0x00000000
+-#define mmD4VGA_CONTROL_DEFAULT 0x00000000
+-#define mmD5VGA_CONTROL_DEFAULT 0x00000000
+-#define mmD6VGA_CONTROL_DEFAULT 0x00000000
+-#define mmVGA_SOURCE_SELECT_DEFAULT 0x00000100
+-#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000
+-#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000
+-#define mmPHYPLLC_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000
+-#define mmPHYPLLD_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000
+-#define mmDCFEV0_CRTC_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+-#define mmDCFEV1_CRTC_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+-#define mmSYMCLKLPA_CLOCK_ENABLE_DEFAULT 0x00000000
+-#define mmSYMCLKLPB_CLOCK_ENABLE_DEFAULT 0x00000100
+-#define mmDPREFCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200
+-#define mmREFCLK_CNTL_DEFAULT 0x00000000
+-#define mmMIPI_CLK_CNTL_DEFAULT 0x00000000
+-#define mmREFCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200
+-#define mmPHYPLLE_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000
+-#define mmDCCG_PERFMON_CNTL2_DEFAULT 0x00000000
+-#define mmDSICLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200
+-#define mmDCCG_CBUS_WRCMD_DELAY_DEFAULT 0x00000003
+-#define mmDCCG_DS_DTO_INCR_DEFAULT 0x00000000
+-#define mmDCCG_DS_DTO_MODULO_DEFAULT 0x00000000
+-#define mmDCCG_DS_CNTL_DEFAULT 0x00000000
+-#define mmDCCG_DS_HW_CAL_INTERVAL_DEFAULT 0x00989680
+-#define mmSYMCLKG_CLOCK_ENABLE_DEFAULT 0x00000600
+-#define mmDPREFCLK_CNTL_DEFAULT 0x00000000
+-#define mmAOMCLK0_CNTL_DEFAULT 0x00000000
+-#define mmAOMCLK1_CNTL_DEFAULT 0x00000000
+-#define mmAOMCLK2_CNTL_DEFAULT 0x00000000
+-#define mmDCCG_AUDIO_DTO2_PHASE_DEFAULT 0x00000000
+-#define mmDCCG_AUDIO_DTO2_MODULO_DEFAULT 0x00000001
+-#define mmDCE_VERSION_DEFAULT 0x00000000
+-#define mmPHYPLLG_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000
+-#define mmDCCG_GTC_CNTL_DEFAULT 0x00000000
+-#define mmDCCG_GTC_DTO_INCR_DEFAULT 0x00000000
+-#define mmDCCG_GTC_DTO_MODULO_DEFAULT 0x00000000
+-#define mmDCCG_GTC_CURRENT_DEFAULT 0x00000000
+-#define mmDENTIST_DISPCLK_CNTL_DEFAULT 0x64010064
+-#define mmMIPI_DTO_CNTL_DEFAULT 0x00000000
+-#define mmMIPI_DTO_PHASE_DEFAULT 0x00000000
+-#define mmMIPI_DTO_MODULO_DEFAULT 0x00000000
+-#define mmDAC_CLK_ENABLE_DEFAULT 0x00000000
+-#define mmDVO_CLK_ENABLE_DEFAULT 0x00000000
+-#define mmAVSYNC_COUNTER_WRITE_DEFAULT 0x00000000
+-#define mmAVSYNC_COUNTER_CONTROL_DEFAULT 0x00000000
+-#define mmDMCU_SMU_INTERRUPT_CNTL_DEFAULT 0x00000000
+-#define mmSMU_CONTROL_DEFAULT 0x00000000
+-#define mmSMU_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmAVSYNC_COUNTER_READ_DEFAULT 0x00000000
+-#define mmMILLISECOND_TIME_BASE_DIV_DEFAULT 0x001186a0
+-#define mmDISPCLK_FREQ_CHANGE_CNTL_DEFAULT 0x08010028
+-#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_DEFAULT 0x00000001
+-#define mmDCCG_PERFMON_CNTL_DEFAULT 0xfffff800
+-#define mmDCCG_GATE_DISABLE_CNTL_DEFAULT 0x74ee00fd
+-#define mmDISPCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200
+-#define mmSCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200
+-#define mmDCCG_CAC_STATUS_DEFAULT 0x00000000
+-#define mmPIXCLK1_RESYNC_CNTL_DEFAULT 0x00000000
+-#define mmPIXCLK2_RESYNC_CNTL_DEFAULT 0x00000000
+-#define mmPIXCLK0_RESYNC_CNTL_DEFAULT 0x00000000
+-#define mmMICROSECOND_TIME_BASE_DIV_DEFAULT 0x00120464
+-#define mmDCCG_GATE_DISABLE_CNTL2_DEFAULT 0x037f037f
+-#define mmSYMCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200
+-#define mmPHYPLLF_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000
+-#define mmDCCG_DISP_CNTL_REG_DEFAULT 0x00000000
+-#define mmCRTC0_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+-#define mmDP_DTO0_PHASE_DEFAULT 0x00000000
+-#define mmDP_DTO0_MODULO_DEFAULT 0x00000000
+-#define mmCRTC0_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+-#define mmCRTC1_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+-#define mmDP_DTO1_PHASE_DEFAULT 0x00000000
+-#define mmDP_DTO1_MODULO_DEFAULT 0x00000000
+-#define mmCRTC1_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+-#define mmCRTC2_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+-#define mmDP_DTO2_PHASE_DEFAULT 0x00000000
+-#define mmDP_DTO2_MODULO_DEFAULT 0x00000000
+-#define mmCRTC2_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+-#define mmCRTC3_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+-#define mmDP_DTO3_PHASE_DEFAULT 0x00000000
+-#define mmDP_DTO3_MODULO_DEFAULT 0x00000000
+-#define mmCRTC3_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+-#define mmCRTC4_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+-#define mmDP_DTO4_PHASE_DEFAULT 0x00000000
+-#define mmDP_DTO4_MODULO_DEFAULT 0x00000000
+-#define mmCRTC4_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+-#define mmCRTC5_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+-#define mmDP_DTO5_PHASE_DEFAULT 0x00000000
+-#define mmDP_DTO5_MODULO_DEFAULT 0x00000000
+-#define mmCRTC5_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+-#define mmDCCG_SOFT_RESET_DEFAULT 0x00000000
+-#define mmSYMCLKA_CLOCK_ENABLE_DEFAULT 0x00000000
+-#define mmSYMCLKB_CLOCK_ENABLE_DEFAULT 0x00000100
+-#define mmSYMCLKC_CLOCK_ENABLE_DEFAULT 0x00000200
+-#define mmSYMCLKD_CLOCK_ENABLE_DEFAULT 0x00000300
+-#define mmSYMCLKE_CLOCK_ENABLE_DEFAULT 0x00000400
+-#define mmSYMCLKF_CLOCK_ENABLE_DEFAULT 0x00000500
+-#define mmDVOACLKD_CNTL_DEFAULT 0x00070000
+-#define mmDVOACLKC_MVP_CNTL_DEFAULT 0x00030000
+-#define mmDVOACLKC_CNTL_DEFAULT 0x00030000
+-#define mmDCCG_AUDIO_DTO_SOURCE_DEFAULT 0x00000030
+-#define mmDCCG_AUDIO_DTO0_PHASE_DEFAULT 0x00000000
+-#define mmDCCG_AUDIO_DTO0_MODULE_DEFAULT 0x00000001
+-#define mmDCCG_AUDIO_DTO1_PHASE_DEFAULT 0x00000000
+-#define mmDCCG_AUDIO_DTO1_MODULE_DEFAULT 0x00000001
+-#define mmDCCG_TEST_CLK_SEL_DEFAULT 0x01ff01ff
+-#define mmFBC_CNTL_DEFAULT 0x00000500
+-#define mmFBC_IDLE_FORCE_CLEAR_MASK_DEFAULT 0x00000000
+-#define mmFBC_START_STOP_DELAY_DEFAULT 0x00000000
+-#define mmFBC_COMP_CNTL_DEFAULT 0x0000000f
+-#define mmFBC_COMP_MODE_DEFAULT 0x00000000
+-#define mmFBC_IND_LUT0_DEFAULT 0x00000000
+-#define mmFBC_IND_LUT1_DEFAULT 0x00000000
+-#define mmFBC_IND_LUT2_DEFAULT 0x00000000
+-#define mmFBC_IND_LUT3_DEFAULT 0x00000000
+-#define mmFBC_IND_LUT4_DEFAULT 0x00000000
+-#define mmFBC_IND_LUT5_DEFAULT 0x00000000
+-#define mmFBC_IND_LUT6_DEFAULT 0x00000000
+-#define mmFBC_IND_LUT7_DEFAULT 0x00000000
+-#define mmFBC_IND_LUT8_DEFAULT 0x00000000
+-#define mmFBC_IND_LUT9_DEFAULT 0x00000000
+-#define mmFBC_IND_LUT10_DEFAULT 0x00000000
+-#define mmFBC_IND_LUT11_DEFAULT 0x00000000
+-#define mmFBC_IND_LUT12_DEFAULT 0x00000000
+-#define mmFBC_IND_LUT13_DEFAULT 0x00000000
+-#define mmFBC_IND_LUT14_DEFAULT 0x00000000
+-#define mmFBC_IND_LUT15_DEFAULT 0x00000000
+-#define mmFBC_CSM_REGION_OFFSET_01_DEFAULT 0x00000000
+-#define mmFBC_CSM_REGION_OFFSET_23_DEFAULT 0x00000000
+-#define mmFBC_CLIENT_REGION_MASK_DEFAULT 0x00000000
+-#define mmFBC_DEBUG_COMP_DEFAULT 0x00000000
+-#define mmFBC_MISC_DEFAULT 0x0c306008
+-#define mmFBC_STATUS_DEFAULT 0x00000000
+-#define mmFBC_ALPHA_CNTL_DEFAULT 0x00000000
+-#define mmFBC_ALPHA_RGB_OVERRIDE_DEFAULT 0x00000000
+-#define mmPIPE0_PG_CONFIG_DEFAULT 0x00000001
+-#define mmPIPE0_PG_ENABLE_DEFAULT 0x00000000
+-#define mmPIPE0_PG_STATUS_DEFAULT 0x00000000
+-#define mmPIPE1_PG_CONFIG_DEFAULT 0x00000001
+-#define mmPIPE1_PG_ENABLE_DEFAULT 0x00000000
+-#define mmPIPE1_PG_STATUS_DEFAULT 0x00000000
+-#define mmPIPE2_PG_CONFIG_DEFAULT 0x00000001
+-#define mmPIPE2_PG_ENABLE_DEFAULT 0x00000000
+-#define mmPIPE2_PG_STATUS_DEFAULT 0x00000000
+-#define mmPIPE3_PG_CONFIG_DEFAULT 0x00000001
+-#define mmPIPE3_PG_ENABLE_DEFAULT 0x00000000
+-#define mmPIPE3_PG_STATUS_DEFAULT 0x00000000
+-#define mmPIPE4_PG_CONFIG_DEFAULT 0x00000001
+-#define mmPIPE4_PG_ENABLE_DEFAULT 0x00000000
+-#define mmPIPE4_PG_STATUS_DEFAULT 0x00000000
+-#define mmPIPE5_PG_CONFIG_DEFAULT 0x00000001
+-#define mmPIPE5_PG_ENABLE_DEFAULT 0x00000000
+-#define mmPIPE5_PG_STATUS_DEFAULT 0x00000000
+-#define mmDSI_PG_CONFIG_DEFAULT 0x00000001
+-#define mmDSI_PG_ENABLE_DEFAULT 0x00000000
+-#define mmDSI_PG_STATUS_DEFAULT 0x00000000
+-#define mmDCFEV0_PG_CONFIG_DEFAULT 0x00000001
+-#define mmDCFEV0_PG_ENABLE_DEFAULT 0x00000000
+-#define mmDCFEV0_PG_STATUS_DEFAULT 0x00000000
+-#define mmDCPG_INTERRUPT_STATUS_DEFAULT 0x00000000
+-#define mmDCPG_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmDCPG_INTERRUPT_CONTROL2_DEFAULT 0x00000000
+-#define mmDCFEV1_PG_CONFIG_DEFAULT 0x00000001
+-#define mmDCFEV1_PG_ENABLE_DEFAULT 0x00000000
+-#define mmDCFEV1_PG_STATUS_DEFAULT 0x00000000
+-#define mmDC_IP_REQUEST_CNTL_DEFAULT 0x00000000
+-#define mmDC_PGCNTL_STATUS_REG_DEFAULT 0x00000000
+-#define mmDMIFV_STATUS_DEFAULT 0x00000000
+-#define mmDMIF_CONTROL_DEFAULT 0x00000c04
+-#define mmDMIF_STATUS_DEFAULT 0x0ff00000
+-#define mmDMIF_ARBITRATION_CONTROL_DEFAULT 0x00042710
+-#define mmPIPE0_ARBITRATION_CONTROL3_DEFAULT 0x00000000
+-#define mmPIPE1_ARBITRATION_CONTROL3_DEFAULT 0x00000000
+-#define mmPIPE2_ARBITRATION_CONTROL3_DEFAULT 0x00000000
+-#define mmPIPE3_ARBITRATION_CONTROL3_DEFAULT 0x00000000
+-#define mmPIPE4_ARBITRATION_CONTROL3_DEFAULT 0x00000000
+-#define mmPIPE5_ARBITRATION_CONTROL3_DEFAULT 0x00000000
+-#define mmDMIF_P_VMID_DEFAULT 0x00000000
+-#define mmDMIF_ADDR_CALC_DEFAULT 0x00000000
+-#define mmDMIF_STATUS2_DEFAULT 0x00000000
+-#define mmPIPE0_MAX_REQUESTS_DEFAULT 0x000003ff
+-#define mmPIPE1_MAX_REQUESTS_DEFAULT 0x000003ff
+-#define mmPIPE2_MAX_REQUESTS_DEFAULT 0x000003ff
+-#define mmPIPE3_MAX_REQUESTS_DEFAULT 0x000003ff
+-#define mmPIPE4_MAX_REQUESTS_DEFAULT 0x000003ff
+-#define mmPIPE5_MAX_REQUESTS_DEFAULT 0x000003ff
+-#define mmLOW_POWER_TILING_CONTROL_DEFAULT 0x00001000
+-#define mmMCIF_CONTROL_DEFAULT 0x00000000
+-#define mmMCIF_WRITE_COMBINE_CONTROL_DEFAULT 0x00000080
+-#define mmMCIF_PHASE0_OUTSTANDING_COUNTER_DEFAULT 0x00000000
+-#define mmCC_DC_PIPE_DIS_DEFAULT 0x00000000
+-#define mmSMU_WM_CONTROL_DEFAULT 0x00000000
+-#define mmRBBMIF_TIMEOUT_DEFAULT 0x20000a00
+-#define mmRBBMIF_STATUS_DEFAULT 0x80000000
+-#define mmRBBMIF_TIMEOUT_DIS_DEFAULT 0x00000000
+-#define mmDCI_MEM_PWR_STATUS_DEFAULT 0x00000000
+-#define mmDCI_MEM_PWR_STATUS2_DEFAULT 0x00000000
+-#define mmDCI_CLK_CNTL_DEFAULT 0x00000000
+-#define mmDCI_CLK_CNTL2_DEFAULT 0x00020020
+-#define mmDCI_MEM_PWR_CNTL_DEFAULT 0x00000000
+-#define mmDCI_MEM_PWR_CNTL2_DEFAULT 0x00000000
+-#define mmDCI_MEM_PWR_CNTL3_DEFAULT 0x00000000
+-#define mmPIPE0_DMIF_BUFFER_CONTROL_DEFAULT 0x00000000
+-#define mmPIPE1_DMIF_BUFFER_CONTROL_DEFAULT 0x00000000
+-#define mmPIPE2_DMIF_BUFFER_CONTROL_DEFAULT 0x00000000
+-#define mmPIPE3_DMIF_BUFFER_CONTROL_DEFAULT 0x00000000
+-#define mmPIPE4_DMIF_BUFFER_CONTROL_DEFAULT 0x00000000
+-#define mmPIPE5_DMIF_BUFFER_CONTROL_DEFAULT 0x00000000
+-#define mmRBBMIF_STATUS_FLAG_DEFAULT 0x00000000
+-#define mmDCI_SOFT_RESET_DEFAULT 0x00000000
+-#define mmDMIF_URG_OVERRIDE_DEFAULT 0x00000000
+-#define mmPIPE6_ARBITRATION_CONTROL3_DEFAULT 0x00000000
+-#define mmPIPE7_ARBITRATION_CONTROL3_DEFAULT 0x00000000
+-#define mmPIPE6_MAX_REQUESTS_DEFAULT 0x000003ff
+-#define mmPIPE7_MAX_REQUESTS_DEFAULT 0x000003ff
+-#define mmDVMM_REG_RD_STATUS_DEFAULT 0x00000000
+-#define mmDVMM_REG_RD_DATA_DEFAULT 0x00000000
+-#define mmDVMM_PTE_REQ_DEFAULT 0x000120ff
+-#define mmDVMM_CNTL_DEFAULT 0x00000000
+-#define mmDVMM_FAULT_STATUS_DEFAULT 0x00000000
+-#define mmDVMM_FAULT_ADDR_DEFAULT 0x00000000
+-#define mmFMON_CTRL_DEFAULT 0x0000f040
+-#define mmDVMM_PTE_PGMEM_CONTROL_DEFAULT 0x00000000
+-#define mmDVMM_PTE_PGMEM_STATE_DEFAULT 0x00000000
+-#define mmMCIF_PHASE1_OUTSTANDING_COUNTER_DEFAULT 0x00000000
+-#define mmMCIF_PHASE2_OUTSTANDING_COUNTER_DEFAULT 0x00000000
+-#define mmMCIF_WB_PHASE0_OUTSTANDING_COUNTER_DEFAULT 0x00000000
+-#define mmMCIF_WB_PHASE1_OUTSTANDING_COUNTER_DEFAULT 0x00000000
+-#define mmDCI_MEM_PWR_CNTL4_DEFAULT 0x0000003f
+-#define mmMCIF_WB_MISC_CTRL_DEFAULT 0x00010001
+-#define mmDCI_MEM_PWR_STATUS3_DEFAULT 0x00000000
+-#define mmDMIF_CURSOR_CONTROL_DEFAULT 0x00000000
+-#define mmDMIF_CURSOR_MEM_CONTROL_DEFAULT 0x00000000
+-#define mmDCHUB_FB_LOCATION_DEFAULT 0x00000000
+-#define mmDCHUB_FB_OFFSET_DEFAULT 0x00000000
+-#define mmDCHUB_AGP_BASE_DEFAULT 0x00000000
+-#define mmDCHUB_AGP_BOT_DEFAULT 0x00000000
+-#define mmDCHUB_AGP_TOP_DEFAULT 0x00000000
+-#define mmDCHUB_DRAM_APER_BASE_DEFAULT 0x00000000
+-#define mmDCHUB_DRAM_APER_DEF_DEFAULT 0x00000000
+-#define mmDCHUB_DRAM_APER_TOP_DEFAULT 0x00000000
+-#define mmDCHUB_CONTROL_STATUS_DEFAULT 0x00c00000
+-#define mmWB_ENABLE_DEFAULT 0x00000000
+-#define mmWB_EC_CONFIG_DEFAULT 0x55000000
+-#define mmCNV_MODE_DEFAULT 0x00000000
+-#define mmCNV_WINDOW_START_DEFAULT 0x00000000
+-#define mmCNV_WINDOW_SIZE_DEFAULT 0x00100010
+-#define mmCNV_UPDATE_DEFAULT 0x00000000
+-#define mmCNV_SOURCE_SIZE_DEFAULT 0x00100010
+-#define mmCNV_CSC_CONTROL_DEFAULT 0x00000000
+-#define mmCNV_CSC_C11_C12_DEFAULT 0x00000000
+-#define mmCNV_CSC_C13_C14_DEFAULT 0x00000000
+-#define mmCNV_CSC_C21_C22_DEFAULT 0x00000000
+-#define mmCNV_CSC_C23_C24_DEFAULT 0x00000000
+-#define mmCNV_CSC_C31_C32_DEFAULT 0x00000000
+-#define mmCNV_CSC_C33_C34_DEFAULT 0x00000000
+-#define mmCNV_CSC_ROUND_OFFSET_R_DEFAULT 0x00000000
+-#define mmCNV_CSC_ROUND_OFFSET_G_DEFAULT 0x00000000
+-#define mmCNV_CSC_ROUND_OFFSET_B_DEFAULT 0x00000000
+-#define mmCNV_CSC_CLAMP_R_DEFAULT 0x00000fff
+-#define mmCNV_CSC_CLAMP_G_DEFAULT 0x00000fff
+-#define mmCNV_CSC_CLAMP_B_DEFAULT 0x00000fff
+-#define mmCNV_TEST_CNTL_DEFAULT 0x00000000
+-#define mmCNV_TEST_CRC_RED_DEFAULT 0x0000fff0
+-#define mmCNV_TEST_CRC_GREEN_DEFAULT 0x0000fff0
+-#define mmCNV_TEST_CRC_BLUE_DEFAULT 0x0000fff0
+-#define mmCNV_INPUT_SELECT_DEFAULT 0x00000000
+-#define mmWB_SOFT_RESET_DEFAULT 0x00000000
+-#define mmWB_WARM_UP_MODE_CTL1_DEFAULT 0x88700100
+-#define mmWB_WARM_UP_MODE_CTL2_DEFAULT 0x00000100
+-#define mmWBSCL_COEF_RAM_SELECT_DEFAULT 0x00000000
+-#define mmWBSCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000
+-#define mmWBSCL_MODE_DEFAULT 0x00000000
+-#define mmWBSCL_TAP_CONTROL_DEFAULT 0x00001111
+-#define mmWBSCL_DEST_SIZE_DEFAULT 0x00010001
+-#define mmWBSCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00080000
+-#define mmWBSCL_HORZ_FILTER_INIT_Y_RGB_DEFAULT 0x01000000
+-#define mmWBSCL_HORZ_FILTER_INIT_CBCR_DEFAULT 0x01000000
+-#define mmWBSCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00080000
+-#define mmWBSCL_VERT_FILTER_INIT_Y_RGB_DEFAULT 0x01000000
+-#define mmWBSCL_VERT_FILTER_INIT_CBCR_DEFAULT 0x01000000
+-#define mmWBSCL_ROUND_OFFSET_DEFAULT 0x00800010
+-#define mmWBSCL_CLAMP_DEFAULT 0x01fe01fe
+-#define mmWBSCL_OVERFLOW_STATUS_DEFAULT 0x00000000
+-#define mmWBSCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000
+-#define mmWBSCL_OUTSIDE_PIX_STRATEGY_DEFAULT 0x80108000
+-#define mmWBSCL_TEST_CNTL_DEFAULT 0x00000000
+-#define mmWBSCL_TEST_CRC_RED_DEFAULT 0x0000ff00
+-#define mmWBSCL_TEST_CRC_GREEN_DEFAULT 0x0000ffff
+-#define mmWBSCL_TEST_CRC_BLUE_DEFAULT 0x0000ff00
+-#define mmWBSCL_BACKPRESSURE_CNT_EN_DEFAULT 0x00000000
+-#define mmWB_MCIF_BACKPRESSURE_CNT_DEFAULT 0x00000000
+-#define mmWBSCL_RAM_SHUTDOWN_DEFAULT 0x00000000
+-#define mmDMCU_CTRL_DEFAULT 0xffff0101
+-#define mmDMCU_STATUS_DEFAULT 0x00000001
+-#define mmDMCU_PC_START_ADDR_DEFAULT 0x00000000
+-#define mmDMCU_FW_START_ADDR_DEFAULT 0x00000000
+-#define mmDMCU_FW_END_ADDR_DEFAULT 0x00000000
+-#define mmDMCU_FW_ISR_START_ADDR_DEFAULT 0x00000004
+-#define mmDMCU_FW_CS_HI_DEFAULT 0x00000000
+-#define mmDMCU_FW_CS_LO_DEFAULT 0x00000000
+-#define mmDMCU_RAM_ACCESS_CTRL_DEFAULT 0x00000000
+-#define mmDMCU_ERAM_WR_CTRL_DEFAULT 0x000f0000
+-#define mmDMCU_ERAM_WR_DATA_DEFAULT 0x00000000
+-#define mmDMCU_ERAM_RD_CTRL_DEFAULT 0x000f0000
+-#define mmDMCU_ERAM_RD_DATA_DEFAULT 0x00000000
+-#define mmDMCU_IRAM_WR_CTRL_DEFAULT 0x00000000
+-#define mmDMCU_IRAM_WR_DATA_DEFAULT 0x00000000
+-#define mmDMCU_IRAM_RD_CTRL_DEFAULT 0x00000000
+-#define mmDMCU_IRAM_RD_DATA_DEFAULT 0x00000000
+-#define mmDMCU_EVENT_TRIGGER_DEFAULT 0x00000000
+-#define mmDMCU_UC_INTERNAL_INT_STATUS_DEFAULT 0x00000000
+-#define mmDMCU_SS_INTERRUPT_CNTL_STATUS_DEFAULT 0x00000000
+-#define mmDMCU_INTERRUPT_STATUS_DEFAULT 0x00000000
+-#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_DEFAULT 0x00000000
+-#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_DEFAULT 0x00000000
+-#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_DEFAULT 0x00000000
+-#define mmDC_DMCU_SCRATCH_DEFAULT 0x00000000
+-#define mmDMCU_INT_CNT_DEFAULT 0x00000000
+-#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_DEFAULT 0x00000000
+-#define mmDMCU_UC_CLK_GATING_CNTL_DEFAULT 0x00010102
+-#define mmMASTER_COMM_DATA_REG1_DEFAULT 0x00000000
+-#define mmMASTER_COMM_DATA_REG2_DEFAULT 0x00000000
+-#define mmMASTER_COMM_DATA_REG3_DEFAULT 0x00000000
+-#define mmMASTER_COMM_CMD_REG_DEFAULT 0x00000000
+-#define mmMASTER_COMM_CNTL_REG_DEFAULT 0x00000000
+-#define mmSLAVE_COMM_DATA_REG1_DEFAULT 0x00000000
+-#define mmSLAVE_COMM_DATA_REG2_DEFAULT 0x00000000
+-#define mmSLAVE_COMM_DATA_REG3_DEFAULT 0x00000000
+-#define mmSLAVE_COMM_CMD_REG_DEFAULT 0x00000000
+-#define mmSLAVE_COMM_CNTL_REG_DEFAULT 0x00000000
+-#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL_DEFAULT 0x00000000
+-#define mmBL1_PWM_USER_LEVEL_DEFAULT 0x00000000
+-#define mmBL1_PWM_TARGET_ABM_LEVEL_DEFAULT 0x00000000
+-#define mmBL1_PWM_CURRENT_ABM_LEVEL_DEFAULT 0x00000000
+-#define mmBL1_PWM_FINAL_DUTY_CYCLE_DEFAULT 0x00000000
+-#define mmBL1_PWM_MINIMUM_DUTY_CYCLE_DEFAULT 0x00000000
+-#define mmBL1_PWM_ABM_CNTL_DEFAULT 0x00000000
+-#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE_DEFAULT 0x00000000
+-#define mmBL1_PWM_GRP2_REG_LOCK_DEFAULT 0x00000000
+-#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_DEFAULT 0x00000000
+-#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_DEFAULT 0x00000000
+-#define mmDMCU_INTERRUPT_STATUS_1_DEFAULT 0x00000000
+-#define mmDMCU_DPRX_INTERRUPT_STATUS1_DEFAULT 0x00000000
+-#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_DEFAULT 0x00000000
+-#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_DEFAULT 0x00000000
+-#define mmDC_ABM1_CNTL_DEFAULT 0x00000000
+-#define mmDC_ABM1_IPCSC_COEFF_SEL_DEFAULT 0x00000000
+-#define mmDC_ABM1_ACE_OFFSET_SLOPE_0_DEFAULT 0x00000400
+-#define mmDC_ABM1_ACE_OFFSET_SLOPE_1_DEFAULT 0x00000400
+-#define mmDC_ABM1_ACE_OFFSET_SLOPE_2_DEFAULT 0x00000400
+-#define mmDC_ABM1_ACE_OFFSET_SLOPE_3_DEFAULT 0x00000400
+-#define mmDC_ABM1_ACE_OFFSET_SLOPE_4_DEFAULT 0x00000400
+-#define mmDC_ABM1_ACE_THRES_12_DEFAULT 0x00000000
+-#define mmDC_ABM1_ACE_THRES_34_DEFAULT 0x00000000
+-#define mmDC_ABM1_ACE_CNTL_MISC_DEFAULT 0x00000000
+-#define mmDMCU_PERFMON_INTERRUPT_STATUS5_DEFAULT 0x00000000
+-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_DEFAULT 0x00000000
+-#define mmDMCU_PERFMON_INTERRUPT_STATUS1_DEFAULT 0x00000000
+-#define mmDMCU_PERFMON_INTERRUPT_STATUS2_DEFAULT 0x00000000
+-#define mmDMCU_PERFMON_INTERRUPT_STATUS3_DEFAULT 0x00000000
+-#define mmDMCU_PERFMON_INTERRUPT_STATUS4_DEFAULT 0x00000000
+-#define mmDC_ABM1_HGLS_REG_READ_PROGRESS_DEFAULT 0x00000000
+-#define mmDC_ABM1_HG_MISC_CTRL_DEFAULT 0x00000000
+-#define mmDC_ABM1_LS_SUM_OF_LUMA_DEFAULT 0x00000000
+-#define mmDC_ABM1_LS_MIN_MAX_LUMA_DEFAULT 0x00000000
+-#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA_DEFAULT 0x00000000
+-#define mmDC_ABM1_LS_PIXEL_COUNT_DEFAULT 0x00000000
+-#define mmDC_ABM1_LS_OVR_SCAN_BIN_DEFAULT 0x00000000
+-#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_DEFAULT 0x00000000
+-#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_DEFAULT 0x00000000
+-#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_DEFAULT 0x00000000
+-#define mmDC_ABM1_HG_SAMPLE_RATE_DEFAULT 0x00000000
+-#define mmDC_ABM1_LS_SAMPLE_RATE_DEFAULT 0x00000000
+-#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG_DEFAULT 0x00000000
+-#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX_DEFAULT 0x00000000
+-#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX_DEFAULT 0x00000000
+-#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX_DEFAULT 0x00000000
+-#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX_DEFAULT 0x00000000
+-#define mmDC_ABM1_HG_RESULT_1_DEFAULT 0x00000000
+-#define mmDC_ABM1_HG_RESULT_2_DEFAULT 0x00000000
+-#define mmDC_ABM1_HG_RESULT_3_DEFAULT 0x00000000
+-#define mmDC_ABM1_HG_RESULT_4_DEFAULT 0x00000000
+-#define mmDC_ABM1_HG_RESULT_5_DEFAULT 0x00000000
+-#define mmDC_ABM1_HG_RESULT_6_DEFAULT 0x00000000
+-#define mmDC_ABM1_HG_RESULT_7_DEFAULT 0x00000000
+-#define mmDC_ABM1_HG_RESULT_8_DEFAULT 0x00000000
+-#define mmDC_ABM1_HG_RESULT_9_DEFAULT 0x00000000
+-#define mmDC_ABM1_HG_RESULT_10_DEFAULT 0x00000000
+-#define mmDC_ABM1_HG_RESULT_11_DEFAULT 0x00000000
+-#define mmDC_ABM1_HG_RESULT_12_DEFAULT 0x00000000
+-#define mmDC_ABM1_HG_RESULT_13_DEFAULT 0x00000000
+-#define mmDC_ABM1_HG_RESULT_14_DEFAULT 0x00000000
+-#define mmDC_ABM1_HG_RESULT_15_DEFAULT 0x00000000
+-#define mmDC_ABM1_HG_RESULT_16_DEFAULT 0x00000000
+-#define mmDC_ABM1_HG_RESULT_17_DEFAULT 0x00000000
+-#define mmDC_ABM1_HG_RESULT_18_DEFAULT 0x00000000
+-#define mmDC_ABM1_HG_RESULT_19_DEFAULT 0x00000000
+-#define mmDC_ABM1_HG_RESULT_20_DEFAULT 0x00000000
+-#define mmDC_ABM1_HG_RESULT_21_DEFAULT 0x00000000
+-#define mmDC_ABM1_HG_RESULT_22_DEFAULT 0x00000000
+-#define mmDC_ABM1_HG_RESULT_23_DEFAULT 0x00000000
+-#define mmDC_ABM1_HG_RESULT_24_DEFAULT 0x00000000
+-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_DEFAULT 0x00000000
+-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_DEFAULT 0x00000000
+-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_DEFAULT 0x00000000
+-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_DEFAULT 0x00000000
+-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_DEFAULT 0x00000000
+-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_DEFAULT 0x00000000
+-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_DEFAULT 0x00000000
+-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_DEFAULT 0x00000000
+-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_DEFAULT 0x00000000
+-#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE_DEFAULT 0x00000000
+-#define mmDC_ABM1_BL_MASTER_LOCK_DEFAULT 0x00000000
+-#define mmAZALIA_CONTROLLER_CLOCK_GATING_DEFAULT 0x00000000
+-#define mmAZALIA_AUDIO_DTO_DEFAULT 0x001b0018
+-#define mmAZALIA_AUDIO_DTO_CONTROL_DEFAULT 0x00000000
+-#define mmAZALIA_SOCCLK_CONTROL_DEFAULT 0x00000001
+-#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_DEFAULT 0x00000000
+-#define mmAZALIA_DATA_DMA_CONTROL_DEFAULT 0x0000000a
+-#define mmAZALIA_BDL_DMA_CONTROL_DEFAULT 0x0000000a
+-#define mmAZALIA_RIRB_AND_DP_CONTROL_DEFAULT 0x00000000
+-#define mmAZALIA_CORB_DMA_CONTROL_DEFAULT 0x00000000
+-#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_DEFAULT 0x00000000
+-#define mmAZALIA_CYCLIC_BUFFER_SYNC_DEFAULT 0x00000000
+-#define mmAZALIA_GLOBAL_CAPABILITIES_DEFAULT 0x00000000
+-#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_DEFAULT 0x00000060
+-#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_DEFAULT 0x00080008
+-#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_DEFAULT 0x00000080
+-#define mmAZALIA_INPUT_CRC0_CONTROL0_DEFAULT 0x00000000
+-#define mmAZALIA_INPUT_CRC0_CONTROL1_DEFAULT 0x00000000
+-#define mmAZALIA_INPUT_CRC0_CONTROL2_DEFAULT 0x00000000
+-#define mmAZALIA_INPUT_CRC0_CONTROL3_DEFAULT 0x00000000
+-#define mmAZALIA_INPUT_CRC0_RESULT_DEFAULT 0x00000000
+-#define mmAZALIA_INPUT_CRC1_CONTROL0_DEFAULT 0x00000000
+-#define mmAZALIA_INPUT_CRC1_CONTROL1_DEFAULT 0x00000000
+-#define mmAZALIA_INPUT_CRC1_CONTROL2_DEFAULT 0x00000000
+-#define mmAZALIA_INPUT_CRC1_CONTROL3_DEFAULT 0x00000000
+-#define mmAZALIA_INPUT_CRC1_RESULT_DEFAULT 0x00000000
+-#define mmAZALIA_CRC0_CONTROL0_DEFAULT 0x00000000
+-#define mmAZALIA_CRC0_CONTROL1_DEFAULT 0x00000000
+-#define mmAZALIA_CRC0_CONTROL2_DEFAULT 0x00000000
+-#define mmAZALIA_CRC0_CONTROL3_DEFAULT 0x00000000
+-#define mmAZALIA_CRC0_RESULT_DEFAULT 0x00000000
+-#define mmAZALIA_CRC1_CONTROL0_DEFAULT 0x00000000
+-#define mmAZALIA_CRC1_CONTROL1_DEFAULT 0x00000000
+-#define mmAZALIA_CRC1_CONTROL2_DEFAULT 0x00000000
+-#define mmAZALIA_CRC1_CONTROL3_DEFAULT 0x00000000
+-#define mmAZALIA_CRC1_RESULT_DEFAULT 0x00000000
+-#define mmAZALIA_MEM_PWR_CTRL_DEFAULT 0x00000000
+-#define mmAZALIA_MEM_PWR_STATUS_DEFAULT 0x00000000
+-#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_DEFAULT 0x1002aa01
+-#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_DEFAULT 0x00100700
+-#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_DEFAULT 0x00000000
+-#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_DEFAULT 0x0000000d
+-#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_DEFAULT 0x00000001
+-#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
+-#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
+-#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_DEFAULT 0xc0000009
+-#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_DEFAULT 0x00000200
+-#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_DEFAULT 0x00000000
+-#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_DEFAULT 0x00aa0100
+-#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_DEFAULT 0x00000000
+-#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_DEFAULT 0x00000000
+-#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_DEFAULT 0x00000000
+-#define mmAZALIA_F0_GTC_GROUP_OFFSET0_DEFAULT 0x00000000
+-#define mmAZALIA_F0_GTC_GROUP_OFFSET1_DEFAULT 0x00000000
+-#define mmAZALIA_F0_GTC_GROUP_OFFSET2_DEFAULT 0x00000000
+-#define mmAZALIA_F0_GTC_GROUP_OFFSET3_DEFAULT 0x00000000
+-#define mmAZALIA_F0_GTC_GROUP_OFFSET4_DEFAULT 0x00000000
+-#define mmAZALIA_F0_GTC_GROUP_OFFSET5_DEFAULT 0x00000000
+-#define mmAZALIA_F0_GTC_GROUP_OFFSET6_DEFAULT 0x00000000
+-#define mmREG_DC_AUDIO_PORT_CONNECTIVITY_DEFAULT 0x00000000
+-#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_DEFAULT 0x00000000
+-#define mmDAC_ENABLE_DEFAULT 0x00000004
+-#define mmDAC_SOURCE_SELECT_DEFAULT 0x00000000
+-#define mmDAC_CRC_EN_DEFAULT 0x00000000
+-#define mmDAC_CRC_CONTROL_DEFAULT 0x00000000
+-#define mmDAC_CRC_SIG_RGB_MASK_DEFAULT 0x3fffffff
+-#define mmDAC_CRC_SIG_CONTROL_MASK_DEFAULT 0x0000003f
+-#define mmDAC_CRC_SIG_RGB_DEFAULT 0x3fffffff
+-#define mmDAC_CRC_SIG_CONTROL_DEFAULT 0x0000003f
+-#define mmDAC_SYNC_TRISTATE_CONTROL_DEFAULT 0x00000000
+-#define mmDAC_STEREOSYNC_SELECT_DEFAULT 0x00000000
+-#define mmDAC_AUTODETECT_CONTROL_DEFAULT 0x00070000
+-#define mmDAC_AUTODETECT_CONTROL2_DEFAULT 0x0000000b
+-#define mmDAC_AUTODETECT_CONTROL3_DEFAULT 0x00000519
+-#define mmDAC_AUTODETECT_STATUS_DEFAULT 0x00000000
+-#define mmDAC_AUTODETECT_INT_CONTROL_DEFAULT 0x00000000
+-#define mmDAC_FORCE_OUTPUT_CNTL_DEFAULT 0x00000000
+-#define mmDAC_FORCE_DATA_DEFAULT 0x000001e6
+-#define mmDAC_POWERDOWN_DEFAULT 0x01010100
+-#define mmDAC_CONTROL_DEFAULT 0x00000000
+-#define mmDAC_COMPARATOR_ENABLE_DEFAULT 0x00000000
+-#define mmDAC_COMPARATOR_OUTPUT_DEFAULT 0x00000000
+-#define mmDAC_PWR_CNTL_DEFAULT 0x00000000
+-#define mmDAC_DFT_CONFIG_DEFAULT 0x00000000
+-#define mmDAC_FIFO_STATUS_DEFAULT 0x00000000
+-#define mmDC_I2C_CONTROL_DEFAULT 0x00000000
+-#define mmDC_I2C_ARBITRATION_DEFAULT 0x00000001
+-#define mmDC_I2C_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmDC_I2C_SW_STATUS_DEFAULT 0x00000000
+-#define mmDC_I2C_DDC1_HW_STATUS_DEFAULT 0x00000000
+-#define mmDC_I2C_DDC2_HW_STATUS_DEFAULT 0x00000000
+-#define mmDC_I2C_DDC3_HW_STATUS_DEFAULT 0x00000000
+-#define mmDC_I2C_DDC4_HW_STATUS_DEFAULT 0x00000000
+-#define mmDC_I2C_DDC5_HW_STATUS_DEFAULT 0x00000000
+-#define mmDC_I2C_DDC6_HW_STATUS_DEFAULT 0x00000000
+-#define mmDC_I2C_DDC1_SPEED_DEFAULT 0x00000002
+-#define mmDC_I2C_DDC1_SETUP_DEFAULT 0x00000000
+-#define mmDC_I2C_DDC2_SPEED_DEFAULT 0x00000002
+-#define mmDC_I2C_DDC2_SETUP_DEFAULT 0x00000000
+-#define mmDC_I2C_DDC3_SPEED_DEFAULT 0x00000002
+-#define mmDC_I2C_DDC3_SETUP_DEFAULT 0x00000000
+-#define mmDC_I2C_DDC4_SPEED_DEFAULT 0x00000002
+-#define mmDC_I2C_DDC4_SETUP_DEFAULT 0x00000000
+-#define mmDC_I2C_DDC5_SPEED_DEFAULT 0x00000002
+-#define mmDC_I2C_DDC5_SETUP_DEFAULT 0x00000000
+-#define mmDC_I2C_DDC6_SPEED_DEFAULT 0x00000002
+-#define mmDC_I2C_DDC6_SETUP_DEFAULT 0x00000000
+-#define mmDC_I2C_TRANSACTION0_DEFAULT 0x00000000
+-#define mmDC_I2C_TRANSACTION1_DEFAULT 0x00000000
+-#define mmDC_I2C_TRANSACTION2_DEFAULT 0x00000000
+-#define mmDC_I2C_TRANSACTION3_DEFAULT 0x00000000
+-#define mmDC_I2C_DATA_DEFAULT 0x00000000
+-#define mmDC_I2C_DDCVGA_HW_STATUS_DEFAULT 0x00000000
+-#define mmDC_I2C_DDCVGA_SPEED_DEFAULT 0x00000002
+-#define mmDC_I2C_DDCVGA_SETUP_DEFAULT 0x00000000
+-#define mmDC_I2C_EDID_DETECT_CTRL_DEFAULT 0x004001f4
+-#define mmDC_I2C_READ_REQUEST_INTERRUPT_DEFAULT 0x40000000
+-#define mmGENERIC_I2C_CONTROL_DEFAULT 0x00000000
+-#define mmGENERIC_I2C_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmGENERIC_I2C_STATUS_DEFAULT 0x00000000
+-#define mmGENERIC_I2C_SPEED_DEFAULT 0x00000002
+-#define mmGENERIC_I2C_SETUP_DEFAULT 0x00000000
+-#define mmGENERIC_I2C_TRANSACTION_DEFAULT 0x00000000
+-#define mmGENERIC_I2C_DATA_DEFAULT 0x00000000
+-#define mmGENERIC_I2C_PIN_SELECTION_DEFAULT 0x00000000
+-#define mmDCO_SCRATCH0_DEFAULT 0x00000000
+-#define mmDCO_SCRATCH1_DEFAULT 0x00000000
+-#define mmDCO_SCRATCH2_DEFAULT 0x00000000
+-#define mmDCO_SCRATCH3_DEFAULT 0x00000000
+-#define mmDCO_SCRATCH4_DEFAULT 0x00000000
+-#define mmDCO_SCRATCH5_DEFAULT 0x00000000
+-#define mmDCO_SCRATCH6_DEFAULT 0x00000000
+-#define mmDCO_SCRATCH7_DEFAULT 0x00000000
+-#define mmDCE_VCE_CONTROL_DEFAULT 0x00000000
+-#define mmDISP_INTERRUPT_STATUS_DEFAULT 0x00000000
+-#define mmDISP_INTERRUPT_STATUS_CONTINUE_DEFAULT 0x00000000
+-#define mmDISP_INTERRUPT_STATUS_CONTINUE2_DEFAULT 0x00000000
+-#define mmDISP_INTERRUPT_STATUS_CONTINUE3_DEFAULT 0x00000000
+-#define mmDISP_INTERRUPT_STATUS_CONTINUE4_DEFAULT 0x00000000
+-#define mmDISP_INTERRUPT_STATUS_CONTINUE5_DEFAULT 0x00000000
+-#define mmDISP_INTERRUPT_STATUS_CONTINUE6_DEFAULT 0x00000000
+-#define mmDISP_INTERRUPT_STATUS_CONTINUE7_DEFAULT 0x00000000
+-#define mmDISP_INTERRUPT_STATUS_CONTINUE8_DEFAULT 0x00000000
+-#define mmDISP_INTERRUPT_STATUS_CONTINUE9_DEFAULT 0x00000000
+-#define mmDCO_MEM_PWR_STATUS_DEFAULT 0x00000000
+-#define mmDCO_MEM_PWR_CTRL_DEFAULT 0x6db6d800
+-#define mmDCO_MEM_PWR_CTRL2_DEFAULT 0x001b0000
+-#define mmDCO_CLK_CNTL_DEFAULT 0x00000000
+-#define mmDCO_POWER_MANAGEMENT_CNTL_DEFAULT 0x00000000
+-#define mmDIG_SOFT_RESET_2_DEFAULT 0x00000000
+-#define mmDCO_STEREOSYNC_SEL_DEFAULT 0x00000000
+-#define mmDCO_SOFT_RESET_DEFAULT 0x00000000
+-#define mmDIG_SOFT_RESET_DEFAULT 0x00000000
+-#define mmDCO_MEM_PWR_STATUS1_DEFAULT 0x00000000
+-#define mmDISP_INTERRUPT_STATUS_CONTINUE10_DEFAULT 0x00000000
+-#define mmDCO_CLK_CNTL2_DEFAULT 0x00000000
+-#define mmDCO_CLK_CNTL3_DEFAULT 0x00000000
+-#define mmDCO_HDMI_RXSTATUS_TIMER_CONTROL_DEFAULT 0x00000000
+-#define mmDCO_PSP_INTERRUPT_STATUS_DEFAULT 0x00000000
+-#define mmDCO_PSP_INTERRUPT_CLEAR_DEFAULT 0x00000000
+-#define mmDCO_GENERIC_INTERRUPT_MESSAGE_DEFAULT 0x00000000
+-#define mmDCO_GENERIC_INTERRUPT_CLEAR_DEFAULT 0x00000000
+-#define mmFMT_MEMORY0_CONTROL_DEFAULT 0x00000030
+-#define mmFMT_MEMORY1_CONTROL_DEFAULT 0x00000031
+-#define mmFMT_MEMORY2_CONTROL_DEFAULT 0x00000032
+-#define mmFMT_MEMORY3_CONTROL_DEFAULT 0x00000033
+-#define mmFMT_MEMORY4_CONTROL_DEFAULT 0x00000034
+-#define mmFMT_MEMORY5_CONTROL_DEFAULT 0x00000035
+-#define mmDISP_INTERRUPT_STATUS_CONTINUE11_DEFAULT 0x00000000
+-#define mmDC_GENERICA_DEFAULT 0x00000000
+-#define mmDC_GENERICB_DEFAULT 0x00000000
+-#define mmDC_PAD_EXTERN_SIG_DEFAULT 0x00000000
+-#define mmDC_REF_CLK_CNTL_DEFAULT 0x00000000
+-#define mmDC_GPIO_DEBUG_DEFAULT 0x00000101
+-#define mmUNIPHYA_LINK_CNTL_DEFAULT 0x01100100
+-#define mmUNIPHYA_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100
+-#define mmUNIPHYB_LINK_CNTL_DEFAULT 0x01100100
+-#define mmUNIPHYB_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100
+-#define mmUNIPHYC_LINK_CNTL_DEFAULT 0x01100100
+-#define mmUNIPHYC_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100
+-#define mmUNIPHYD_LINK_CNTL_DEFAULT 0x01100100
+-#define mmUNIPHYD_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100
+-#define mmUNIPHYE_LINK_CNTL_DEFAULT 0x01100100
+-#define mmUNIPHYE_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100
+-#define mmUNIPHYF_LINK_CNTL_DEFAULT 0x01100100
+-#define mmUNIPHYF_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100
+-#define mmUNIPHYG_LINK_CNTL_DEFAULT 0x01100100
+-#define mmUNIPHYG_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100
+-#define mmDCIO_WRCMD_DELAY_DEFAULT 0x00033333
+-#define mmDC_DVODATA_CONFIG_DEFAULT 0x00000000
+-#define mmLVTMA_PWRSEQ_CNTL_DEFAULT 0x00000000
+-#define mmLVTMA_PWRSEQ_STATE_DEFAULT 0x00000000
+-#define mmLVTMA_PWRSEQ_REF_DIV_DEFAULT 0x00010000
+-#define mmLVTMA_PWRSEQ_DELAY1_DEFAULT 0x00000000
+-#define mmLVTMA_PWRSEQ_DELAY2_DEFAULT 0x00000000
+-#define mmBL_PWM_CNTL_DEFAULT 0x00000000
+-#define mmBL_PWM_CNTL2_DEFAULT 0x00000000
+-#define mmBL_PWM_PERIOD_CNTL_DEFAULT 0x00000001
+-#define mmBL_PWM_GRP1_REG_LOCK_DEFAULT 0x00000000
+-#define mmDCIO_GSL_GENLK_PAD_CNTL_DEFAULT 0x00000000
+-#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_DEFAULT 0x00000000
+-#define mmDCIO_GSL0_CNTL_DEFAULT 0x00000000
+-#define mmDCIO_GSL1_CNTL_DEFAULT 0x00000000
+-#define mmDCIO_GSL2_CNTL_DEFAULT 0x00000000
+-#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_DEFAULT 0x00000000
+-#define mmDC_GPU_TIMER_START_POSITION_P_FLIP_DEFAULT 0x00000000
+-#define mmDC_GPU_TIMER_READ_DEFAULT 0x00000000
+-#define mmDC_GPU_TIMER_READ_CNTL_DEFAULT 0x00000000
+-#define mmDCIO_CLOCK_CNTL_DEFAULT 0x00000000
+-#define mmDCO_DCFE_EXT_VSYNC_CNTL_DEFAULT 0x00000000
+-#define mmDCIO_SOFT_RESET_DEFAULT 0x00000000
+-#define mmDCIO_DPHY_SEL_DEFAULT 0x000000e4
+-#define mmUNIPHY_IMPCAL_LINKA_DEFAULT 0x0f000000
+-#define mmUNIPHY_IMPCAL_LINKB_DEFAULT 0x0f000000
+-#define mmUNIPHY_IMPCAL_PERIOD_DEFAULT 0x00000000
+-#define mmAUXP_IMPCAL_DEFAULT 0x0a000000
+-#define mmAUXN_IMPCAL_DEFAULT 0x04000000
+-#define mmDCIO_IMPCAL_CNTL_DEFAULT 0x00000000
+-#define mmUNIPHY_IMPCAL_PSW_AB_DEFAULT 0x00000000
+-#define mmUNIPHY_IMPCAL_LINKC_DEFAULT 0x0f000000
+-#define mmUNIPHY_IMPCAL_LINKD_DEFAULT 0x0f000000
+-#define mmDCIO_IMPCAL_CNTL_CD_DEFAULT 0x00000000
+-#define mmUNIPHY_IMPCAL_PSW_CD_DEFAULT 0x00000000
+-#define mmUNIPHY_IMPCAL_LINKE_DEFAULT 0x0f000000
+-#define mmUNIPHY_IMPCAL_LINKF_DEFAULT 0x0f000000
+-#define mmDCIO_IMPCAL_CNTL_EF_DEFAULT 0x00000000
+-#define mmUNIPHY_IMPCAL_PSW_EF_DEFAULT 0x00000000
+-#define mmUNIPHYLPA_LINK_CNTL_DEFAULT 0x01100100
+-#define mmUNIPHYLPB_LINK_CNTL_DEFAULT 0x01100100
+-#define mmUNIPHYLPA_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100
+-#define mmUNIPHYLPB_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100
+-#define mmDCIO_DPCS_TX_INTERRUPT_DEFAULT 0x00000000
+-#define mmDCIO_DPCS_RX_INTERRUPT_DEFAULT 0x00000000
+-#define mmDCIO_SEMAPHORE0_DEFAULT 0x00000000
+-#define mmDCIO_SEMAPHORE1_DEFAULT 0x00000000
+-#define mmDCIO_SEMAPHORE2_DEFAULT 0x00000000
+-#define mmDCIO_SEMAPHORE3_DEFAULT 0x00000000
+-#define mmDCIO_SEMAPHORE4_DEFAULT 0x00000000
+-#define mmDCIO_SEMAPHORE5_DEFAULT 0x00000000
+-#define mmDCIO_SEMAPHORE6_DEFAULT 0x00000000
+-#define mmDCIO_SEMAPHORE7_DEFAULT 0x00000000
+-#define mmDC_GPIO_GENERIC_MASK_DEFAULT 0x04444444
+-#define mmDC_GPIO_GENERIC_A_DEFAULT 0x00000000
+-#define mmDC_GPIO_GENERIC_EN_DEFAULT 0x00000000
+-#define mmDC_GPIO_GENERIC_Y_DEFAULT 0x00000000
+-#define mmDC_GPIO_DVODATA_MASK_DEFAULT 0x00000000
+-#define mmDC_GPIO_DVODATA_A_DEFAULT 0x00000000
+-#define mmDC_GPIO_DVODATA_EN_DEFAULT 0x00000000
+-#define mmDC_GPIO_DVODATA_Y_DEFAULT 0x00000000
+-#define mmDC_GPIO_DDC1_MASK_DEFAULT 0xcf400000
+-#define mmDC_GPIO_DDC1_A_DEFAULT 0x00000000
+-#define mmDC_GPIO_DDC1_EN_DEFAULT 0x00000000
+-#define mmDC_GPIO_DDC1_Y_DEFAULT 0x00000000
+-#define mmDC_GPIO_DDC2_MASK_DEFAULT 0xcf400000
+-#define mmDC_GPIO_DDC2_A_DEFAULT 0x00000000
+-#define mmDC_GPIO_DDC2_EN_DEFAULT 0x00000000
+-#define mmDC_GPIO_DDC2_Y_DEFAULT 0x00000000
+-#define mmDC_GPIO_DDC3_MASK_DEFAULT 0xcf400000
+-#define mmDC_GPIO_DDC3_A_DEFAULT 0x00000000
+-#define mmDC_GPIO_DDC3_EN_DEFAULT 0x00000000
+-#define mmDC_GPIO_DDC3_Y_DEFAULT 0x00000000
+-#define mmDC_GPIO_DDC4_MASK_DEFAULT 0xcf400000
+-#define mmDC_GPIO_DDC4_A_DEFAULT 0x00000000
+-#define mmDC_GPIO_DDC4_EN_DEFAULT 0x00000000
+-#define mmDC_GPIO_DDC4_Y_DEFAULT 0x00000000
+-#define mmDC_GPIO_DDC5_MASK_DEFAULT 0xcf400000
+-#define mmDC_GPIO_DDC5_A_DEFAULT 0x00000000
+-#define mmDC_GPIO_DDC5_EN_DEFAULT 0x00000000
+-#define mmDC_GPIO_DDC5_Y_DEFAULT 0x00000000
+-#define mmDC_GPIO_DDC6_MASK_DEFAULT 0xcf400000
+-#define mmDC_GPIO_DDC6_A_DEFAULT 0x00000000
+-#define mmDC_GPIO_DDC6_EN_DEFAULT 0x00000000
+-#define mmDC_GPIO_DDC6_Y_DEFAULT 0x00000000
+-#define mmDC_GPIO_DDCVGA_MASK_DEFAULT 0xcf400000
+-#define mmDC_GPIO_DDCVGA_A_DEFAULT 0x00000000
+-#define mmDC_GPIO_DDCVGA_EN_DEFAULT 0x00000000
+-#define mmDC_GPIO_DDCVGA_Y_DEFAULT 0x00000000
+-#define mmDC_GPIO_SYNCA_MASK_DEFAULT 0x00004040
+-#define mmDC_GPIO_SYNCA_A_DEFAULT 0x00000000
+-#define mmDC_GPIO_SYNCA_EN_DEFAULT 0x00000000
+-#define mmDC_GPIO_SYNCA_Y_DEFAULT 0x00000000
+-#define mmDC_GPIO_GENLK_MASK_DEFAULT 0x10101a10
+-#define mmDC_GPIO_GENLK_A_DEFAULT 0x00000000
+-#define mmDC_GPIO_GENLK_EN_DEFAULT 0x00000000
+-#define mmDC_GPIO_GENLK_Y_DEFAULT 0x00000000
+-#define mmDC_GPIO_HPD_MASK_DEFAULT 0x44440440
+-#define mmDC_GPIO_HPD_A_DEFAULT 0x00000000
+-#define mmDC_GPIO_HPD_EN_DEFAULT 0x22220202
+-#define mmDC_GPIO_HPD_Y_DEFAULT 0x00000000
+-#define mmDC_GPIO_PWRSEQ_MASK_DEFAULT 0x66404040
+-#define mmDC_GPIO_PWRSEQ_A_DEFAULT 0x00000000
+-#define mmDC_GPIO_PWRSEQ_EN_DEFAULT 0x00000000
+-#define mmDC_GPIO_PWRSEQ_Y_DEFAULT 0x00000000
+-#define mmDC_GPIO_PAD_STRENGTH_1_DEFAULT 0x47ac470f
+-#define mmDC_GPIO_PAD_STRENGTH_2_DEFAULT 0x00472147
+-#define mmPHY_AUX_CNTL_DEFAULT 0x00010001
+-#define mmDC_GPIO_I2CPAD_MASK_DEFAULT 0x00000000
+-#define mmDC_GPIO_I2CPAD_A_DEFAULT 0x00000000
+-#define mmDC_GPIO_I2CPAD_EN_DEFAULT 0x00000000
+-#define mmDC_GPIO_I2CPAD_Y_DEFAULT 0x00000000
+-#define mmDC_GPIO_I2CPAD_STRENGTH_DEFAULT 0x0000004c
+-#define mmDVO_STRENGTH_CONTROL_DEFAULT 0x31116060
+-#define mmDVO_VREF_CONTROL_DEFAULT 0x00000000
+-#define mmDVO_SKEW_ADJUST_DEFAULT 0x00000000
+-#define mmDC_GPIO_I2S_SPDIF_MASK_DEFAULT 0x00000000
+-#define mmDC_GPIO_I2S_SPDIF_A_DEFAULT 0x00000000
+-#define mmDC_GPIO_I2S_SPDIF_EN_DEFAULT 0x00008000
+-#define mmDC_GPIO_I2S_SPDIF_Y_DEFAULT 0x00000000
+-#define mmDC_GPIO_I2S_SPDIF_STRENGTH_DEFAULT 0x01021202
+-#define mmDC_GPIO_TX12_EN_DEFAULT 0x00000000
+-#define mmDC_GPIO_AUX_CTRL_0_DEFAULT 0x00000000
+-#define mmDC_GPIO_AUX_CTRL_1_DEFAULT 0x00500000
+-#define mmDC_GPIO_AUX_CTRL_2_DEFAULT 0x00000000
+-#define mmDC_GPIO_RXEN_DEFAULT 0x007fff7f
+-#define mmBPHYC_DAC_MACRO_CNTL_DEFAULT 0x00202002
+-#define mmDAC_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
+-#define mmBPHYC_DAC_AUTO_CALIB_CONTROL_DEFAULT 0x00700255
+-#define mmDAC_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
+-#define mmDAC_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
+-#define mmDAC_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
+-#define mmDISP_DSI_DUAL_CTRL_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000
+-#define mmDPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000
+-#define mmDPRX_AUX_REFERENCE_PULSE_DIV_DEFAULT 0x0a640064
+-#define mmDPRX_AUX_CONTROL_DEFAULT 0x01012c00
+-#define mmDPRX_AUX_HPD_CONTROL1_DEFAULT 0x00001407
+-#define mmDPRX_AUX_HPD_CONTROL2_DEFAULT 0x00000000
+-#define mmDPRX_AUX_RX_STATUS_DEFAULT 0x00000000
+-#define mmDPRX_AUX_RX_ERROR_MASK_DEFAULT 0x00000000
+-#define mmDPRX_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000
+-#define mmDPRX_AUX_DPHY_TX_CONTROL_DEFAULT 0x00001002
+-#define mmDPRX_AUX_DPHY_RX_CONTROL0_DEFAULT 0x203d1210
+-#define mmDPRX_AUX_DPHY_RX_CONTROL1_DEFAULT 0x0a00fa00
+-#define mmDPRX_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000
+-#define mmDPRX_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000
+-#define mmDPRX_AUX_DMCU_HW_INT_STATUS_DEFAULT 0x00003f00
+-#define mmDPRX_AUX_DMCU_HW_INT_ACK_DEFAULT 0x00000000
+-#define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT1_DEFAULT 0x00000000
+-#define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT2_DEFAULT 0x00000001
+-#define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT1_DEFAULT 0x00000000
+-#define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT2_DEFAULT 0x00000000
+-#define mmDPRX_AUX_AUX_BUF_INDEX_DEFAULT 0x00000000
+-#define mmDPRX_AUX_AUX_BUF_DATA_DEFAULT 0x00000000
+-#define mmDPRX_AUX_EDID_INDEX_DEFAULT 0x00000000
+-#define mmDPRX_AUX_EDID_DATA_DEFAULT 0x00000000
+-#define mmDPRX_AUX_DPCD_INDEX1_DEFAULT 0x00000000
+-#define mmDPRX_AUX_DPCD_DATA1_DEFAULT 0x00000000
+-#define mmDPRX_AUX_DPCD_INDEX2_DEFAULT 0x00000000
+-#define mmDPRX_AUX_DPCD_DATA2_DEFAULT 0x00000000
+-#define mmDPRX_AUX_MSG_INDEX1_DEFAULT 0x00000000
+-#define mmDPRX_AUX_MSG_DATA1_DEFAULT 0x00000000
+-#define mmDPRX_AUX_MSG_INDEX2_DEFAULT 0x00000000
+-#define mmDPRX_AUX_MSG_DATA2_DEFAULT 0x00000000
+-#define mmDPRX_AUX_KSV_INDEX1_DEFAULT 0x00000000
+-#define mmDPRX_AUX_KSV_DATA1_DEFAULT 0x00000000
+-#define mmDPRX_AUX_KSV_INDEX2_DEFAULT 0x00000000
+-#define mmDPRX_AUX_KSV_DATA2_DEFAULT 0x00000000
+-#define mmDPRX_AUX_MSG_TIMEOUT_CONTROL_DEFAULT 0x00000032
+-#define mmDPRX_AUX_MSG_BUF_CONTROL1_DEFAULT 0x00000000
+-#define mmDPRX_AUX_MSG_BUF_CONTROL2_DEFAULT 0x00000000
+-#define mmDPRX_AUX_SCRATCH1_DEFAULT 0x00000000
+-#define mmDPRX_AUX_SCRATCH2_DEFAULT 0x00000000
+-#define mmDPRX_AUX_MSG1_PENDING_DEFAULT 0x00000000
+-#define mmDPRX_AUX_MSG2_PENDING_DEFAULT 0x00000000
+-#define mmDPRX_AUX_MSG3_PENDING_DEFAULT 0x00000000
+-#define mmDPRX_AUX_MSG4_PENDING_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_DPCD_LANE_COUNT_SET_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_DPCD_TRAINING_PATTERN_SET_DEFAULT 0x00000003
+-#define mmDPRX_DPHY_DPCD_MSTM_CTRL_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_SET_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS_DEFAULT 0x20000000
+-#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_SET_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS_DEFAULT 0x20000000
+-#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_SET_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS_DEFAULT 0x20000000
+-#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_SET_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS_DEFAULT 0x20000000
+-#define mmDPRX_DPHY_READY_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_COMMA_STATUS_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_LANE_ALIGN_ERROR_STATUS_UPDATED_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_LANE_ALIGN_STATUS_UPDATED_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_ERROR_THRESH_A_LANE0_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_ERROR_COUNT_A_LANE0_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_ERROR_COUNT_B_LANE0_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_ERROR_COUNT_C_LANE0_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_ERROR_THRESH_A_LANE1_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_ERROR_COUNT_A_LANE1_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_ERROR_COUNT_B_LANE1_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_ERROR_COUNT_C_LANE1_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_ERROR_THRESH_A_LANE2_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_ERROR_COUNT_A_LANE2_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_ERROR_COUNT_B_LANE2_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_ERROR_COUNT_C_LANE2_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_ERROR_THRESH_A_LANE3_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_ERROR_COUNT_A_LANE3_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_ERROR_COUNT_B_LANE3_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_ERROR_COUNT_C_LANE3_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_BS_ERROR_THRESH_GLOBAL_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_SR_ERROR_COUNT_A_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_BS_ERROR_COUNT_A_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_BS_ERROR_COUNT_B_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_LANESETUP0_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_LANESETUP1_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_LFSRADV_DEFAULT 0x00000039
+-#define mmDPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_SET_ENABLE_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_ECF_LSB_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_ECF_MSB_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_ENHANCED_FRAME_EN_DEFAULT 0x00000001
+-#define mmDPRX_DPHY_MTP_HEADER_COUNT_FORCE_DEFAULT 0x000a6800
+-#define mmDPRX_DPHY_DYNAMIC_DESKEW_DATA_DEFAULT 0xbcbcbcbc
+-#define mmDPRX_DPHY_DYNAMIC_DESKEW_CONTROL_DEFAULT 0x800071c5
+-#define mmDPRX_DPHY_BYPASS_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_INT_RESET_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_DETECT_SR_LOCK_STATUS_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_LOSS_OF_ALIGN_STATUS_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_LOSS_OF_DESKEW_STATUS_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_EXCESSIVE_ERROR_STATUS_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS_DEFAULT 0x00000000
+-#define mmDPRX_DPHY_SPARE_DEFAULT 0x00000000
+-#define mmDCRX_GATE_DISABLE_CNTL_DEFAULT 0x00001f0f
+-#define mmDCRX_SOFT_RESET_DEFAULT 0x00000000
+-#define mmDCRX_LIGHT_SLEEP_CNTL_DEFAULT 0x00000101
+-#define mmDCRX_DISPCLK_GATE_CNTL_DEFAULT 0x00000200
+-#define mmDCRX_CLK_CNTL_DEFAULT 0x00000000
+-#define mmDCRX_TEST_CLK_CNTL_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED160_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED161_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED162_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED163_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED164_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED165_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED166_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED167_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED168_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED169_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED170_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED171_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED172_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED173_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED174_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED175_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED176_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED177_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED178_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED179_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED180_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED181_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED182_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED183_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED184_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED185_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED186_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED187_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED188_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED189_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED190_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED191_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED192_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED193_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED194_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED195_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED196_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED197_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED198_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED199_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED200_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED201_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED202_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED203_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED204_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED205_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED206_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED207_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED208_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED209_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED210_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED211_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED212_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED213_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED214_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED215_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED216_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED217_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED218_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED219_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED220_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED221_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED222_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED223_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED224_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED225_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED226_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED227_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED228_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED229_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED230_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED231_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED232_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED233_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED234_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED235_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED236_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED237_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED238_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED239_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED240_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED241_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED242_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED243_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED244_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED245_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED246_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED247_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED248_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED249_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED250_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED251_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED252_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED253_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED254_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED255_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED256_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED257_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED258_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED259_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED260_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED261_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED262_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED263_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED264_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED265_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED266_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED267_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED268_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED269_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED270_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED271_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED272_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED273_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED274_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED275_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED276_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED277_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED278_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED279_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED280_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED281_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED282_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED283_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED284_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED285_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED286_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED287_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED288_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED289_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED290_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED291_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED292_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED293_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED294_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED295_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED296_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED297_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED298_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED299_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED300_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED301_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED302_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED303_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED304_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED305_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED306_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED307_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED308_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED309_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED310_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED311_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED312_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED313_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED314_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED315_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED316_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED317_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED318_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED319_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED320_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED321_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED322_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED323_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED324_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED325_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED326_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED327_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED328_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED329_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED330_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED331_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED332_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED333_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED334_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED335_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED336_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED337_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED338_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED339_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED340_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED341_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED342_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED343_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED344_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED345_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED346_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED347_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED348_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED349_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED350_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED351_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED352_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED353_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED354_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED355_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED356_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED357_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED358_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED359_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED360_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED361_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED362_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED363_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED364_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED365_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED366_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED367_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED368_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED369_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED370_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED371_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED372_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED373_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED374_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED375_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED376_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED377_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED378_DEFAULT 0x00000000
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED379_DEFAULT 0x00000000
+-#define mmI2S0_CNTL_DEFAULT 0x00010000
+-#define mmSPDIF0_CNTL_DEFAULT 0x00000000
+-#define mmI2S1_CNTL_DEFAULT 0x00010000
+-#define mmSPDIF1_CNTL_DEFAULT 0x00000000
+-#define mmI2S0_STATUS_DEFAULT 0x00000000
+-#define mmI2S1_STATUS_DEFAULT 0x00000000
+-#define mmI2S0_CRC_TEST_CNTL_DEFAULT 0x00000100
+-#define mmI2S0_CRC_TEST_DATA_01_DEFAULT 0x00000000
+-#define mmI2S0_CRC_TEST_DATA_23_DEFAULT 0x00000000
+-#define mmI2S1_CRC_TEST_CNTL_DEFAULT 0x00000100
+-#define mmI2S1_CRC_TEST_DATA_0_DEFAULT 0x00000000
+-#define mmSPDIF0_CRC_TEST_CNTL_DEFAULT 0x00000100
+-#define mmSPDIF0_CRC_TEST_DATA_0_DEFAULT 0x00000000
+-#define mmSPDIF1_CRC_TEST_CNTL_DEFAULT 0x00000100
+-#define mmSPDIF1_CRC_TEST_DATA_DEFAULT 0x00000000
+-#define mmCRC_I2S_CONT_REPEAT_NUM_DEFAULT 0x00000000
+-#define mmCRC_SPDIF_CONT_REPEAT_NUM_DEFAULT 0x00000000
+-#define mmZCAL_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
+-#define mmZCAL_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
+-#define mmZCAL_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
+-#define mmZCAL_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
+-#define mmZCAL_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_azf0stream0_dispdec
+-#define mmAZF0STREAM0_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
+-#define mmAZF0STREAM0_AZALIA_STREAM_DATA_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_azf0stream1_dispdec
+-#define mmAZF0STREAM1_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
+-#define mmAZF0STREAM1_AZALIA_STREAM_DATA_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_azf0stream2_dispdec
+-#define mmAZF0STREAM2_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
+-#define mmAZF0STREAM2_AZALIA_STREAM_DATA_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_azf0stream3_dispdec
+-#define mmAZF0STREAM3_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
+-#define mmAZF0STREAM3_AZALIA_STREAM_DATA_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_azf0stream4_dispdec
+-#define mmAZF0STREAM4_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
+-#define mmAZF0STREAM4_AZALIA_STREAM_DATA_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_azf0stream5_dispdec
+-#define mmAZF0STREAM5_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
+-#define mmAZF0STREAM5_AZALIA_STREAM_DATA_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_azf0stream6_dispdec
+-#define mmAZF0STREAM6_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
+-#define mmAZF0STREAM6_AZALIA_STREAM_DATA_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_azf0stream7_dispdec
+-#define mmAZF0STREAM7_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
+-#define mmAZF0STREAM7_AZALIA_STREAM_DATA_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_azf0endpoint0_dispdec
+-#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000
+-#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_azf0endpoint1_dispdec
+-#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000
+-#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_azf0endpoint2_dispdec
+-#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000
+-#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_azf0endpoint3_dispdec
+-#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000
+-#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_azf0endpoint4_dispdec
+-#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000
+-#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_azf0endpoint5_dispdec
+-#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000
+-#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_azf0endpoint6_dispdec
+-#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000
+-#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_azf0endpoint7_dispdec
+-#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000
+-#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_azf0stream8_dispdec
+-#define mmAZF0STREAM8_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
+-#define mmAZF0STREAM8_AZALIA_STREAM_DATA_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_azf0stream9_dispdec
+-#define mmAZF0STREAM9_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
+-#define mmAZF0STREAM9_AZALIA_STREAM_DATA_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_azf0stream10_dispdec
+-#define mmAZF0STREAM10_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
+-#define mmAZF0STREAM10_AZALIA_STREAM_DATA_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_azf0stream11_dispdec
+-#define mmAZF0STREAM11_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
+-#define mmAZF0STREAM11_AZALIA_STREAM_DATA_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_azf0stream12_dispdec
+-#define mmAZF0STREAM12_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
+-#define mmAZF0STREAM12_AZALIA_STREAM_DATA_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_azf0stream13_dispdec
+-#define mmAZF0STREAM13_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
+-#define mmAZF0STREAM13_AZALIA_STREAM_DATA_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_azf0stream14_dispdec
+-#define mmAZF0STREAM14_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
+-#define mmAZF0STREAM14_AZALIA_STREAM_DATA_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_azf0stream15_dispdec
+-#define mmAZF0STREAM15_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
+-#define mmAZF0STREAM15_AZALIA_STREAM_DATA_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_azf0inputendpoint0_dispdec
+-#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000
+-#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_azf0inputendpoint1_dispdec
+-#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000
+-#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_azf0inputendpoint2_dispdec
+-#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000
+-#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_azf0inputendpoint3_dispdec
+-#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000
+-#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_azf0inputendpoint4_dispdec
+-#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000
+-#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_azf0inputendpoint5_dispdec
+-#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000
+-#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_azf0inputendpoint6_dispdec
+-#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000
+-#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_azf0inputendpoint7_dispdec
+-#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000
+-#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dcp0_dispdec
+-#define mmDCP0_GRPH_ENABLE_DEFAULT 0x00000001
+-#define mmDCP0_GRPH_CONTROL_DEFAULT 0x20002040
+-#define mmDCP0_GRPH_LUT_10BIT_BYPASS_DEFAULT 0x00000000
+-#define mmDCP0_GRPH_SWAP_CNTL_DEFAULT 0x00000000
+-#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000
+-#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000
+-#define mmDCP0_GRPH_PITCH_DEFAULT 0x00000000
+-#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+-#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+-#define mmDCP0_GRPH_SURFACE_OFFSET_X_DEFAULT 0x00000000
+-#define mmDCP0_GRPH_SURFACE_OFFSET_Y_DEFAULT 0x00000000
+-#define mmDCP0_GRPH_X_START_DEFAULT 0x00000000
+-#define mmDCP0_GRPH_Y_START_DEFAULT 0x00000000
+-#define mmDCP0_GRPH_X_END_DEFAULT 0x00000000
+-#define mmDCP0_GRPH_Y_END_DEFAULT 0x00000000
+-#define mmDCP0_INPUT_GAMMA_CONTROL_DEFAULT 0x00000000
+-#define mmDCP0_GRPH_UPDATE_DEFAULT 0x00000000
+-#define mmDCP0_GRPH_FLIP_CONTROL_DEFAULT 0x00000020
+-#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE_DEFAULT 0x00000000
+-#define mmDCP0_GRPH_DFQ_CONTROL_DEFAULT 0x00000000
+-#define mmDCP0_GRPH_DFQ_STATUS_DEFAULT 0x00000000
+-#define mmDCP0_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000
+-#define mmDCP0_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE_DEFAULT 0x00000000
+-#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_DEFAULT 0x00000000
+-#define mmDCP0_GRPH_COMPRESS_PITCH_DEFAULT 0x00000000
+-#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+-#define mmDCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x000000ff
+-#define mmDCP0_PRESCALE_GRPH_CONTROL_DEFAULT 0x00000010
+-#define mmDCP0_PRESCALE_VALUES_GRPH_R_DEFAULT 0x20000000
+-#define mmDCP0_PRESCALE_VALUES_GRPH_G_DEFAULT 0x20000000
+-#define mmDCP0_PRESCALE_VALUES_GRPH_B_DEFAULT 0x20000000
+-#define mmDCP0_INPUT_CSC_CONTROL_DEFAULT 0x00000000
+-#define mmDCP0_INPUT_CSC_C11_C12_DEFAULT 0x00002000
+-#define mmDCP0_INPUT_CSC_C13_C14_DEFAULT 0x00000000
+-#define mmDCP0_INPUT_CSC_C21_C22_DEFAULT 0x20000000
+-#define mmDCP0_INPUT_CSC_C23_C24_DEFAULT 0x00000000
+-#define mmDCP0_INPUT_CSC_C31_C32_DEFAULT 0x00000000
+-#define mmDCP0_INPUT_CSC_C33_C34_DEFAULT 0x00002000
+-#define mmDCP0_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000
+-#define mmDCP0_OUTPUT_CSC_C11_C12_DEFAULT 0x00002000
+-#define mmDCP0_OUTPUT_CSC_C13_C14_DEFAULT 0x00000000
+-#define mmDCP0_OUTPUT_CSC_C21_C22_DEFAULT 0x20000000
+-#define mmDCP0_OUTPUT_CSC_C23_C24_DEFAULT 0x00000000
+-#define mmDCP0_OUTPUT_CSC_C31_C32_DEFAULT 0x00000000
+-#define mmDCP0_OUTPUT_CSC_C33_C34_DEFAULT 0x00002000
+-#define mmDCP0_COMM_MATRIXA_TRANS_C11_C12_DEFAULT 0x00002000
+-#define mmDCP0_COMM_MATRIXA_TRANS_C13_C14_DEFAULT 0x00000000
+-#define mmDCP0_COMM_MATRIXA_TRANS_C21_C22_DEFAULT 0x20000000
+-#define mmDCP0_COMM_MATRIXA_TRANS_C23_C24_DEFAULT 0x00000000
+-#define mmDCP0_COMM_MATRIXA_TRANS_C31_C32_DEFAULT 0x00000000
+-#define mmDCP0_COMM_MATRIXA_TRANS_C33_C34_DEFAULT 0x00002000
+-#define mmDCP0_COMM_MATRIXB_TRANS_C11_C12_DEFAULT 0x00002000
+-#define mmDCP0_COMM_MATRIXB_TRANS_C13_C14_DEFAULT 0x00000000
+-#define mmDCP0_COMM_MATRIXB_TRANS_C21_C22_DEFAULT 0x20000000
+-#define mmDCP0_COMM_MATRIXB_TRANS_C23_C24_DEFAULT 0x00000000
+-#define mmDCP0_COMM_MATRIXB_TRANS_C31_C32_DEFAULT 0x00000000
+-#define mmDCP0_COMM_MATRIXB_TRANS_C33_C34_DEFAULT 0x00002000
+-#define mmDCP0_DENORM_CONTROL_DEFAULT 0x00000003
+-#define mmDCP0_OUT_ROUND_CONTROL_DEFAULT 0x0000000a
+-#define mmDCP0_OUT_CLAMP_CONTROL_R_CR_DEFAULT 0x00003fff
+-#define mmDCP0_OUT_CLAMP_CONTROL_G_Y_DEFAULT 0x00003fff
+-#define mmDCP0_OUT_CLAMP_CONTROL_B_CB_DEFAULT 0x00003fff
+-#define mmDCP0_KEY_CONTROL_DEFAULT 0x00000000
+-#define mmDCP0_KEY_RANGE_ALPHA_DEFAULT 0x00000000
+-#define mmDCP0_KEY_RANGE_RED_DEFAULT 0x00000000
+-#define mmDCP0_KEY_RANGE_GREEN_DEFAULT 0x00000000
+-#define mmDCP0_KEY_RANGE_BLUE_DEFAULT 0x00000000
+-#define mmDCP0_DEGAMMA_CONTROL_DEFAULT 0x00000000
+-#define mmDCP0_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000
+-#define mmDCP0_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000
+-#define mmDCP0_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000
+-#define mmDCP0_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000
+-#define mmDCP0_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000
+-#define mmDCP0_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000
+-#define mmDCP0_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000
+-#define mmDCP0_DCP_SPATIAL_DITHER_CNTL_DEFAULT 0x00000000
+-#define mmDCP0_DCP_RANDOM_SEEDS_DEFAULT 0x00000000
+-#define mmDCP0_DCP_FP_CONVERTED_FIELD_DEFAULT 0x00000000
+-#define mmDCP0_CUR_CONTROL_DEFAULT 0x00000810
+-#define mmDCP0_CUR_SURFACE_ADDRESS_DEFAULT 0x00000000
+-#define mmDCP0_CUR_SIZE_DEFAULT 0x00000000
+-#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+-#define mmDCP0_CUR_POSITION_DEFAULT 0x00000000
+-#define mmDCP0_CUR_HOT_SPOT_DEFAULT 0x00000000
+-#define mmDCP0_CUR_COLOR1_DEFAULT 0x00000000
+-#define mmDCP0_CUR_COLOR2_DEFAULT 0x00000000
+-#define mmDCP0_CUR_UPDATE_DEFAULT 0x00000000
+-#define mmDCP0_CUR_REQUEST_FILTER_CNTL_DEFAULT 0x00000000
+-#define mmDCP0_CUR_STEREO_CONTROL_DEFAULT 0x00000000
+-#define mmDCP0_DC_LUT_RW_MODE_DEFAULT 0x00000000
+-#define mmDCP0_DC_LUT_RW_INDEX_DEFAULT 0x00000000
+-#define mmDCP0_DC_LUT_SEQ_COLOR_DEFAULT 0x00000000
+-#define mmDCP0_DC_LUT_PWL_DATA_DEFAULT 0x00000000
+-#define mmDCP0_DC_LUT_30_COLOR_DEFAULT 0x00000000
+-#define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE_DEFAULT 0x00000000
+-#define mmDCP0_DC_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
+-#define mmDCP0_DC_LUT_AUTOFILL_DEFAULT 0x00000000
+-#define mmDCP0_DC_LUT_CONTROL_DEFAULT 0x00000000
+-#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE_DEFAULT 0x00000000
+-#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN_DEFAULT 0x00000000
+-#define mmDCP0_DC_LUT_BLACK_OFFSET_RED_DEFAULT 0x00000000
+-#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE_DEFAULT 0x0000ffff
+-#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN_DEFAULT 0x0000ffff
+-#define mmDCP0_DC_LUT_WHITE_OFFSET_RED_DEFAULT 0x0000ffff
+-#define mmDCP0_DCP_CRC_CONTROL_DEFAULT 0x00000000
+-#define mmDCP0_DCP_CRC_MASK_DEFAULT 0x00000000
+-#define mmDCP0_DCP_CRC_CURRENT_DEFAULT 0x00000000
+-#define mmDCP0_DVMM_PTE_CONTROL_DEFAULT 0x00004000
+-#define mmDCP0_DCP_CRC_LAST_DEFAULT 0x00000000
+-#define mmDCP0_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220
+-#define mmDCP0_GRPH_FLIP_RATE_CNTL_DEFAULT 0x00000000
+-#define mmDCP0_DCP_GSL_CONTROL_DEFAULT 0x60000020
+-#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000035
+-#define mmDCP0_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00000200
+-#define mmDCP0_HW_ROTATION_DEFAULT 0x00000000
+-#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_DEFAULT 0x00000010
+-#define mmDCP0_REGAMMA_CONTROL_DEFAULT 0x00000000
+-#define mmDCP0_REGAMMA_LUT_INDEX_DEFAULT 0x00000000
+-#define mmDCP0_REGAMMA_LUT_DATA_DEFAULT 0x00000000
+-#define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
+-#define mmDCP0_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000
+-#define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000
+-#define mmDCP0_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000
+-#define mmDCP0_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000
+-#define mmDCP0_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000
+-#define mmDCP0_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000
+-#define mmDCP0_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000
+-#define mmDCP0_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000
+-#define mmDCP0_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000
+-#define mmDCP0_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000
+-#define mmDCP0_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000
+-#define mmDCP0_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000
+-#define mmDCP0_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000
+-#define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000
+-#define mmDCP0_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000
+-#define mmDCP0_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000
+-#define mmDCP0_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000
+-#define mmDCP0_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000
+-#define mmDCP0_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000
+-#define mmDCP0_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000
+-#define mmDCP0_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000
+-#define mmDCP0_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000
+-#define mmDCP0_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000
+-#define mmDCP0_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000
+-#define mmDCP0_ALPHA_CONTROL_DEFAULT 0x00000002
+-#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_DEFAULT 0x00000000
+-#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+-#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_DEFAULT 0x00000000
+-#define mmDCP0_GRPH_XDMA_FLIP_TIMEOUT_DEFAULT 0x00000000
+-#define mmDCP0_GRPH_XDMA_FLIP_AVG_DELAY_DEFAULT 0x00000000
+-#define mmDCP0_GRPH_SURFACE_COUNTER_CONTROL_DEFAULT 0x00000012
+-#define mmDCP0_GRPH_SURFACE_COUNTER_OUTPUT_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_lb0_dispdec
+-#define mmLB0_LB_DATA_FORMAT_DEFAULT 0x00000000
+-#define mmLB0_LB_MEMORY_CTRL_DEFAULT 0x000006b0
+-#define mmLB0_LB_MEMORY_SIZE_STATUS_DEFAULT 0x00000000
+-#define mmLB0_LB_DESKTOP_HEIGHT_DEFAULT 0x00000000
+-#define mmLB0_LB_VLINE_START_END_DEFAULT 0x00000000
+-#define mmLB0_LB_VLINE2_START_END_DEFAULT 0x00000000
+-#define mmLB0_LB_V_COUNTER_DEFAULT 0x00000000
+-#define mmLB0_LB_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000
+-#define mmLB0_LB_INTERRUPT_MASK_DEFAULT 0x00000000
+-#define mmLB0_LB_VLINE_STATUS_DEFAULT 0x00000000
+-#define mmLB0_LB_VLINE2_STATUS_DEFAULT 0x00000000
+-#define mmLB0_LB_VBLANK_STATUS_DEFAULT 0x00000000
+-#define mmLB0_LB_SYNC_RESET_SEL_DEFAULT 0x00000002
+-#define mmLB0_LB_BLACK_KEYER_R_CR_DEFAULT 0x00000000
+-#define mmLB0_LB_BLACK_KEYER_G_Y_DEFAULT 0x00000000
+-#define mmLB0_LB_BLACK_KEYER_B_CB_DEFAULT 0x00000000
+-#define mmLB0_LB_KEYER_COLOR_CTRL_DEFAULT 0x00000000
+-#define mmLB0_LB_KEYER_COLOR_R_CR_DEFAULT 0x00000000
+-#define mmLB0_LB_KEYER_COLOR_G_Y_DEFAULT 0x00000000
+-#define mmLB0_LB_KEYER_COLOR_B_CB_DEFAULT 0x00000000
+-#define mmLB0_LB_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000
+-#define mmLB0_LB_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000
+-#define mmLB0_LB_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000
+-#define mmLB0_LB_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000
+-#define mmLB0_LB_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010
+-#define mmLB0_LB_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000
+-#define mmLB0_LB_BUFFER_STATUS_DEFAULT 0x00000002
+-#define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000
+-#define mmLB0_MVP_AFR_FLIP_MODE_DEFAULT 0x00000000
+-#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL_DEFAULT 0x00000000
+-#define mmLB0_MVP_FLIP_LINE_NUM_INSERT_DEFAULT 0x00000002
+-#define mmLB0_DC_MVP_LB_CONTROL_DEFAULT 0x00000001
+-
+-
+-// addressBlock: dce_dc_dcfe0_dispdec
+-#define mmDCFE0_DCFE_CLOCK_CONTROL_DEFAULT 0x00000000
+-#define mmDCFE0_DCFE_SOFT_RESET_DEFAULT 0x00000000
+-#define mmDCFE0_DCFE_MEM_PWR_CTRL_DEFAULT 0x00000000
+-#define mmDCFE0_DCFE_MEM_PWR_CTRL2_DEFAULT 0x00000000
+-#define mmDCFE0_DCFE_MEM_PWR_STATUS_DEFAULT 0x00000000
+-#define mmDCFE0_DCFE_MISC_DEFAULT 0x00000001
+-#define mmDCFE0_DCFE_FLUSH_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dc_perfmon3_dispdec
+-#define mmDC_PERFMON3_PERFCOUNTER_CNTL_DEFAULT 0x00000000
+-#define mmDC_PERFMON3_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
+-#define mmDC_PERFMON3_PERFCOUNTER_STATE_DEFAULT 0x00000000
+-#define mmDC_PERFMON3_PERFMON_CNTL_DEFAULT 0x00000100
+-#define mmDC_PERFMON3_PERFMON_CNTL2_DEFAULT 0x00000000
+-#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
+-#define mmDC_PERFMON3_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
+-#define mmDC_PERFMON3_PERFMON_HI_DEFAULT 0x00000000
+-#define mmDC_PERFMON3_PERFMON_LOW_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dmif_pg0_dispdec
+-#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000
+-#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000
+-#define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL_DEFAULT 0x000bf777
+-#define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000
+-#define mmDMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL_DEFAULT 0x00000000
+-#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_DEFAULT 0x00000000
+-#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL2_DEFAULT 0x00000000
+-#define mmDMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL_DEFAULT 0x00000000
+-#define mmDMIF_PG0_DPG_REPEATER_PROGRAM_DEFAULT 0x00000000
+-#define mmDMIF_PG0_DPG_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000
+-#define mmDMIF_PG0_DPG_DVMM_STATUS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_scl0_dispdec
+-#define mmSCL0_SCL_COEF_RAM_SELECT_DEFAULT 0x00000000
+-#define mmSCL0_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000
+-#define mmSCL0_SCL_MODE_DEFAULT 0x00000000
+-#define mmSCL0_SCL_TAP_CONTROL_DEFAULT 0x00000000
+-#define mmSCL0_SCL_CONTROL_DEFAULT 0x00000000
+-#define mmSCL0_SCL_BYPASS_CONTROL_DEFAULT 0x00000000
+-#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000
+-#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000
+-#define mmSCL0_SCL_HORZ_FILTER_CONTROL_DEFAULT 0x00000000
+-#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000
+-#define mmSCL0_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000
+-#define mmSCL0_SCL_VERT_FILTER_CONTROL_DEFAULT 0x00000000
+-#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000
+-#define mmSCL0_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000
+-#define mmSCL0_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000
+-#define mmSCL0_SCL_ROUND_OFFSET_DEFAULT 0x80000000
+-#define mmSCL0_SCL_UPDATE_DEFAULT 0x00000000
+-#define mmSCL0_SCL_F_SHARP_CONTROL_DEFAULT 0x00000000
+-#define mmSCL0_SCL_ALU_CONTROL_DEFAULT 0x00000000
+-#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000
+-#define mmSCL0_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000
+-#define mmSCL0_VIEWPORT_START_DEFAULT 0x00000000
+-#define mmSCL0_VIEWPORT_SIZE_DEFAULT 0x00000000
+-#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000
+-#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000
+-#define mmSCL0_SCL_MODE_CHANGE_DET1_DEFAULT 0x00000000
+-#define mmSCL0_SCL_MODE_CHANGE_DET2_DEFAULT 0x00000000
+-#define mmSCL0_SCL_MODE_CHANGE_DET3_DEFAULT 0x00000000
+-#define mmSCL0_SCL_MODE_CHANGE_MASK_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_blnd0_dispdec
+-#define mmBLND0_BLND_CONTROL_DEFAULT 0xff0220ff
+-#define mmBLND0_BLND_SM_CONTROL2_DEFAULT 0x00000000
+-#define mmBLND0_BLND_CONTROL2_DEFAULT 0x00000010
+-#define mmBLND0_BLND_UPDATE_DEFAULT 0x00000000
+-#define mmBLND0_BLND_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000
+-#define mmBLND0_BLND_V_UPDATE_LOCK_DEFAULT 0x80000000
+-#define mmBLND0_BLND_REG_UPDATE_STATUS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_crtc0_dispdec
+-#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM_DEFAULT 0x00000040
+-#define mmCRTC0_CRTC_H_TOTAL_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_H_BLANK_START_END_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_H_SYNC_A_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_H_SYNC_A_CNTL_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_H_SYNC_B_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_H_SYNC_B_CNTL_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_VBI_END_DEFAULT 0x00000003
+-#define mmCRTC0_CRTC_V_TOTAL_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_V_TOTAL_MIN_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_V_TOTAL_MAX_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_V_TOTAL_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_V_BLANK_START_END_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_V_SYNC_A_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_V_SYNC_A_CNTL_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_V_SYNC_B_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_V_SYNC_B_CNTL_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_DTMTEST_CNTL_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_TRIGA_CNTL_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_TRIGB_CNTL_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_FLOW_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_AVSYNC_COUNTER_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_CONTROL_DEFAULT 0x80400110
+-#define mmCRTC0_CRTC_BLANK_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_INTERLACE_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_INTERLACE_STATUS_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_PIXEL_DATA_READBACK0_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_PIXEL_DATA_READBACK1_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_STATUS_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_STATUS_POSITION_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_NOM_VERT_POSITION_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_STATUS_FRAME_COUNT_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_STATUS_VF_COUNT_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_STATUS_HV_COUNT_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_COUNT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_COUNT_RESET_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_VERT_SYNC_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_STEREO_STATUS_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_STEREO_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_SNAPSHOT_STATUS_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_SNAPSHOT_POSITION_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_SNAPSHOT_FRAME_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_START_LINE_CONTROL_DEFAULT 0x00003002
+-#define mmCRTC0_CRTC_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_UPDATE_LOCK_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_TEST_PATTERN_COLOR_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_MASTER_UPDATE_LOCK_DEFAULT 0x00010000
+-#define mmCRTC0_CRTC_MASTER_UPDATE_MODE_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008
+-#define mmCRTC0_CRTC_MVP_STATUS_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_MASTER_EN_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000
+-#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_OVERSCAN_COLOR_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_BLANK_DATA_COLOR_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_BLACK_COLOR_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_BLACK_COLOR_EXT_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_CRC_CNTL_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_CRC0_DATA_RG_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_CRC0_DATA_B_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_CRC1_DATA_RG_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_CRC1_DATA_B_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000
+-#define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010
+-#define mmCRTC0_CRTC_GSL_VSYNC_GAP_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_GSL_WINDOW_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_GSL_CONTROL_DEFAULT 0x00020000
+-#define mmCRTC0_CRTC_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000
+-#define mmCRTC0_CRTC_DRR_CONTROL_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_fmt0_dispdec
+-#define mmFMT0_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000
+-#define mmFMT0_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000
+-#define mmFMT0_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000
+-#define mmFMT0_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000
+-#define mmFMT0_FMT_CONTROL_DEFAULT 0x00000000
+-#define mmFMT0_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000
+-#define mmFMT0_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000
+-#define mmFMT0_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099
+-#define mmFMT0_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd
+-#define mmFMT0_FMT_CLAMP_CNTL_DEFAULT 0x00000000
+-#define mmFMT0_FMT_CRC_CNTL_DEFAULT 0x01000040
+-#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK_DEFAULT 0x00ff00ff
+-#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0x000700ff
+-#define mmFMT0_FMT_CRC_SIG_RED_GREEN_DEFAULT 0x00000000
+-#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_DEFAULT 0x00000000
+-#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000
+-#define mmFMT0_FMT_420_HBLANK_EARLY_START_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dcp1_dispdec
+-#define mmDCP1_GRPH_ENABLE_DEFAULT 0x00000001
+-#define mmDCP1_GRPH_CONTROL_DEFAULT 0x20002040
+-#define mmDCP1_GRPH_LUT_10BIT_BYPASS_DEFAULT 0x00000000
+-#define mmDCP1_GRPH_SWAP_CNTL_DEFAULT 0x00000000
+-#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000
+-#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000
+-#define mmDCP1_GRPH_PITCH_DEFAULT 0x00000000
+-#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+-#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+-#define mmDCP1_GRPH_SURFACE_OFFSET_X_DEFAULT 0x00000000
+-#define mmDCP1_GRPH_SURFACE_OFFSET_Y_DEFAULT 0x00000000
+-#define mmDCP1_GRPH_X_START_DEFAULT 0x00000000
+-#define mmDCP1_GRPH_Y_START_DEFAULT 0x00000000
+-#define mmDCP1_GRPH_X_END_DEFAULT 0x00000000
+-#define mmDCP1_GRPH_Y_END_DEFAULT 0x00000000
+-#define mmDCP1_INPUT_GAMMA_CONTROL_DEFAULT 0x00000000
+-#define mmDCP1_GRPH_UPDATE_DEFAULT 0x00000000
+-#define mmDCP1_GRPH_FLIP_CONTROL_DEFAULT 0x00000020
+-#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE_DEFAULT 0x00000000
+-#define mmDCP1_GRPH_DFQ_CONTROL_DEFAULT 0x00000000
+-#define mmDCP1_GRPH_DFQ_STATUS_DEFAULT 0x00000000
+-#define mmDCP1_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000
+-#define mmDCP1_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE_DEFAULT 0x00000000
+-#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_DEFAULT 0x00000000
+-#define mmDCP1_GRPH_COMPRESS_PITCH_DEFAULT 0x00000000
+-#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+-#define mmDCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x000000ff
+-#define mmDCP1_PRESCALE_GRPH_CONTROL_DEFAULT 0x00000010
+-#define mmDCP1_PRESCALE_VALUES_GRPH_R_DEFAULT 0x20000000
+-#define mmDCP1_PRESCALE_VALUES_GRPH_G_DEFAULT 0x20000000
+-#define mmDCP1_PRESCALE_VALUES_GRPH_B_DEFAULT 0x20000000
+-#define mmDCP1_INPUT_CSC_CONTROL_DEFAULT 0x00000000
+-#define mmDCP1_INPUT_CSC_C11_C12_DEFAULT 0x00002000
+-#define mmDCP1_INPUT_CSC_C13_C14_DEFAULT 0x00000000
+-#define mmDCP1_INPUT_CSC_C21_C22_DEFAULT 0x20000000
+-#define mmDCP1_INPUT_CSC_C23_C24_DEFAULT 0x00000000
+-#define mmDCP1_INPUT_CSC_C31_C32_DEFAULT 0x00000000
+-#define mmDCP1_INPUT_CSC_C33_C34_DEFAULT 0x00002000
+-#define mmDCP1_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000
+-#define mmDCP1_OUTPUT_CSC_C11_C12_DEFAULT 0x00002000
+-#define mmDCP1_OUTPUT_CSC_C13_C14_DEFAULT 0x00000000
+-#define mmDCP1_OUTPUT_CSC_C21_C22_DEFAULT 0x20000000
+-#define mmDCP1_OUTPUT_CSC_C23_C24_DEFAULT 0x00000000
+-#define mmDCP1_OUTPUT_CSC_C31_C32_DEFAULT 0x00000000
+-#define mmDCP1_OUTPUT_CSC_C33_C34_DEFAULT 0x00002000
+-#define mmDCP1_COMM_MATRIXA_TRANS_C11_C12_DEFAULT 0x00002000
+-#define mmDCP1_COMM_MATRIXA_TRANS_C13_C14_DEFAULT 0x00000000
+-#define mmDCP1_COMM_MATRIXA_TRANS_C21_C22_DEFAULT 0x20000000
+-#define mmDCP1_COMM_MATRIXA_TRANS_C23_C24_DEFAULT 0x00000000
+-#define mmDCP1_COMM_MATRIXA_TRANS_C31_C32_DEFAULT 0x00000000
+-#define mmDCP1_COMM_MATRIXA_TRANS_C33_C34_DEFAULT 0x00002000
+-#define mmDCP1_COMM_MATRIXB_TRANS_C11_C12_DEFAULT 0x00002000
+-#define mmDCP1_COMM_MATRIXB_TRANS_C13_C14_DEFAULT 0x00000000
+-#define mmDCP1_COMM_MATRIXB_TRANS_C21_C22_DEFAULT 0x20000000
+-#define mmDCP1_COMM_MATRIXB_TRANS_C23_C24_DEFAULT 0x00000000
+-#define mmDCP1_COMM_MATRIXB_TRANS_C31_C32_DEFAULT 0x00000000
+-#define mmDCP1_COMM_MATRIXB_TRANS_C33_C34_DEFAULT 0x00002000
+-#define mmDCP1_DENORM_CONTROL_DEFAULT 0x00000003
+-#define mmDCP1_OUT_ROUND_CONTROL_DEFAULT 0x0000000a
+-#define mmDCP1_OUT_CLAMP_CONTROL_R_CR_DEFAULT 0x00003fff
+-#define mmDCP1_OUT_CLAMP_CONTROL_G_Y_DEFAULT 0x00003fff
+-#define mmDCP1_OUT_CLAMP_CONTROL_B_CB_DEFAULT 0x00003fff
+-#define mmDCP1_KEY_CONTROL_DEFAULT 0x00000000
+-#define mmDCP1_KEY_RANGE_ALPHA_DEFAULT 0x00000000
+-#define mmDCP1_KEY_RANGE_RED_DEFAULT 0x00000000
+-#define mmDCP1_KEY_RANGE_GREEN_DEFAULT 0x00000000
+-#define mmDCP1_KEY_RANGE_BLUE_DEFAULT 0x00000000
+-#define mmDCP1_DEGAMMA_CONTROL_DEFAULT 0x00000000
+-#define mmDCP1_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000
+-#define mmDCP1_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000
+-#define mmDCP1_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000
+-#define mmDCP1_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000
+-#define mmDCP1_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000
+-#define mmDCP1_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000
+-#define mmDCP1_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000
+-#define mmDCP1_DCP_SPATIAL_DITHER_CNTL_DEFAULT 0x00000000
+-#define mmDCP1_DCP_RANDOM_SEEDS_DEFAULT 0x00000000
+-#define mmDCP1_DCP_FP_CONVERTED_FIELD_DEFAULT 0x00000000
+-#define mmDCP1_CUR_CONTROL_DEFAULT 0x00000810
+-#define mmDCP1_CUR_SURFACE_ADDRESS_DEFAULT 0x00000000
+-#define mmDCP1_CUR_SIZE_DEFAULT 0x00000000
+-#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+-#define mmDCP1_CUR_POSITION_DEFAULT 0x00000000
+-#define mmDCP1_CUR_HOT_SPOT_DEFAULT 0x00000000
+-#define mmDCP1_CUR_COLOR1_DEFAULT 0x00000000
+-#define mmDCP1_CUR_COLOR2_DEFAULT 0x00000000
+-#define mmDCP1_CUR_UPDATE_DEFAULT 0x00000000
+-#define mmDCP1_CUR_REQUEST_FILTER_CNTL_DEFAULT 0x00000000
+-#define mmDCP1_CUR_STEREO_CONTROL_DEFAULT 0x00000000
+-#define mmDCP1_DC_LUT_RW_MODE_DEFAULT 0x00000000
+-#define mmDCP1_DC_LUT_RW_INDEX_DEFAULT 0x00000000
+-#define mmDCP1_DC_LUT_SEQ_COLOR_DEFAULT 0x00000000
+-#define mmDCP1_DC_LUT_PWL_DATA_DEFAULT 0x00000000
+-#define mmDCP1_DC_LUT_30_COLOR_DEFAULT 0x00000000
+-#define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE_DEFAULT 0x00000000
+-#define mmDCP1_DC_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
+-#define mmDCP1_DC_LUT_AUTOFILL_DEFAULT 0x00000000
+-#define mmDCP1_DC_LUT_CONTROL_DEFAULT 0x00000000
+-#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE_DEFAULT 0x00000000
+-#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN_DEFAULT 0x00000000
+-#define mmDCP1_DC_LUT_BLACK_OFFSET_RED_DEFAULT 0x00000000
+-#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE_DEFAULT 0x0000ffff
+-#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN_DEFAULT 0x0000ffff
+-#define mmDCP1_DC_LUT_WHITE_OFFSET_RED_DEFAULT 0x0000ffff
+-#define mmDCP1_DCP_CRC_CONTROL_DEFAULT 0x00000000
+-#define mmDCP1_DCP_CRC_MASK_DEFAULT 0x00000000
+-#define mmDCP1_DCP_CRC_CURRENT_DEFAULT 0x00000000
+-#define mmDCP1_DVMM_PTE_CONTROL_DEFAULT 0x00004000
+-#define mmDCP1_DCP_CRC_LAST_DEFAULT 0x00000000
+-#define mmDCP1_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220
+-#define mmDCP1_GRPH_FLIP_RATE_CNTL_DEFAULT 0x00000000
+-#define mmDCP1_DCP_GSL_CONTROL_DEFAULT 0x60000020
+-#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000035
+-#define mmDCP1_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00000200
+-#define mmDCP1_HW_ROTATION_DEFAULT 0x00000000
+-#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_DEFAULT 0x00000010
+-#define mmDCP1_REGAMMA_CONTROL_DEFAULT 0x00000000
+-#define mmDCP1_REGAMMA_LUT_INDEX_DEFAULT 0x00000000
+-#define mmDCP1_REGAMMA_LUT_DATA_DEFAULT 0x00000000
+-#define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
+-#define mmDCP1_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000
+-#define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000
+-#define mmDCP1_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000
+-#define mmDCP1_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000
+-#define mmDCP1_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000
+-#define mmDCP1_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000
+-#define mmDCP1_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000
+-#define mmDCP1_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000
+-#define mmDCP1_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000
+-#define mmDCP1_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000
+-#define mmDCP1_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000
+-#define mmDCP1_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000
+-#define mmDCP1_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000
+-#define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000
+-#define mmDCP1_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000
+-#define mmDCP1_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000
+-#define mmDCP1_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000
+-#define mmDCP1_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000
+-#define mmDCP1_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000
+-#define mmDCP1_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000
+-#define mmDCP1_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000
+-#define mmDCP1_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000
+-#define mmDCP1_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000
+-#define mmDCP1_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000
+-#define mmDCP1_ALPHA_CONTROL_DEFAULT 0x00000002
+-#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_DEFAULT 0x00000000
+-#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+-#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_DEFAULT 0x00000000
+-#define mmDCP1_GRPH_XDMA_FLIP_TIMEOUT_DEFAULT 0x00000000
+-#define mmDCP1_GRPH_XDMA_FLIP_AVG_DELAY_DEFAULT 0x00000000
+-#define mmDCP1_GRPH_SURFACE_COUNTER_CONTROL_DEFAULT 0x00000012
+-#define mmDCP1_GRPH_SURFACE_COUNTER_OUTPUT_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_lb1_dispdec
+-#define mmLB1_LB_DATA_FORMAT_DEFAULT 0x00000000
+-#define mmLB1_LB_MEMORY_CTRL_DEFAULT 0x000006b0
+-#define mmLB1_LB_MEMORY_SIZE_STATUS_DEFAULT 0x00000000
+-#define mmLB1_LB_DESKTOP_HEIGHT_DEFAULT 0x00000000
+-#define mmLB1_LB_VLINE_START_END_DEFAULT 0x00000000
+-#define mmLB1_LB_VLINE2_START_END_DEFAULT 0x00000000
+-#define mmLB1_LB_V_COUNTER_DEFAULT 0x00000000
+-#define mmLB1_LB_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000
+-#define mmLB1_LB_INTERRUPT_MASK_DEFAULT 0x00000000
+-#define mmLB1_LB_VLINE_STATUS_DEFAULT 0x00000000
+-#define mmLB1_LB_VLINE2_STATUS_DEFAULT 0x00000000
+-#define mmLB1_LB_VBLANK_STATUS_DEFAULT 0x00000000
+-#define mmLB1_LB_SYNC_RESET_SEL_DEFAULT 0x00000002
+-#define mmLB1_LB_BLACK_KEYER_R_CR_DEFAULT 0x00000000
+-#define mmLB1_LB_BLACK_KEYER_G_Y_DEFAULT 0x00000000
+-#define mmLB1_LB_BLACK_KEYER_B_CB_DEFAULT 0x00000000
+-#define mmLB1_LB_KEYER_COLOR_CTRL_DEFAULT 0x00000000
+-#define mmLB1_LB_KEYER_COLOR_R_CR_DEFAULT 0x00000000
+-#define mmLB1_LB_KEYER_COLOR_G_Y_DEFAULT 0x00000000
+-#define mmLB1_LB_KEYER_COLOR_B_CB_DEFAULT 0x00000000
+-#define mmLB1_LB_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000
+-#define mmLB1_LB_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000
+-#define mmLB1_LB_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000
+-#define mmLB1_LB_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000
+-#define mmLB1_LB_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010
+-#define mmLB1_LB_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000
+-#define mmLB1_LB_BUFFER_STATUS_DEFAULT 0x00000002
+-#define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000
+-#define mmLB1_MVP_AFR_FLIP_MODE_DEFAULT 0x00000000
+-#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL_DEFAULT 0x00000000
+-#define mmLB1_MVP_FLIP_LINE_NUM_INSERT_DEFAULT 0x00000002
+-#define mmLB1_DC_MVP_LB_CONTROL_DEFAULT 0x00000001
+-
+-
+-// addressBlock: dce_dc_dcfe1_dispdec
+-#define mmDCFE1_DCFE_CLOCK_CONTROL_DEFAULT 0x00000000
+-#define mmDCFE1_DCFE_SOFT_RESET_DEFAULT 0x00000000
+-#define mmDCFE1_DCFE_MEM_PWR_CTRL_DEFAULT 0x00000000
+-#define mmDCFE1_DCFE_MEM_PWR_CTRL2_DEFAULT 0x00000000
+-#define mmDCFE1_DCFE_MEM_PWR_STATUS_DEFAULT 0x00000000
+-#define mmDCFE1_DCFE_MISC_DEFAULT 0x00000001
+-#define mmDCFE1_DCFE_FLUSH_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dc_perfmon4_dispdec
+-#define mmDC_PERFMON4_PERFCOUNTER_CNTL_DEFAULT 0x00000000
+-#define mmDC_PERFMON4_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
+-#define mmDC_PERFMON4_PERFCOUNTER_STATE_DEFAULT 0x00000000
+-#define mmDC_PERFMON4_PERFMON_CNTL_DEFAULT 0x00000100
+-#define mmDC_PERFMON4_PERFMON_CNTL2_DEFAULT 0x00000000
+-#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
+-#define mmDC_PERFMON4_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
+-#define mmDC_PERFMON4_PERFMON_HI_DEFAULT 0x00000000
+-#define mmDC_PERFMON4_PERFMON_LOW_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dmif_pg1_dispdec
+-#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000
+-#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000
+-#define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL_DEFAULT 0x000bf777
+-#define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000
+-#define mmDMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL_DEFAULT 0x00000000
+-#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_DEFAULT 0x00000000
+-#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL2_DEFAULT 0x00000000
+-#define mmDMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL_DEFAULT 0x00000000
+-#define mmDMIF_PG1_DPG_REPEATER_PROGRAM_DEFAULT 0x00000000
+-#define mmDMIF_PG1_DPG_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000
+-#define mmDMIF_PG1_DPG_DVMM_STATUS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_scl1_dispdec
+-#define mmSCL1_SCL_COEF_RAM_SELECT_DEFAULT 0x00000000
+-#define mmSCL1_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000
+-#define mmSCL1_SCL_MODE_DEFAULT 0x00000000
+-#define mmSCL1_SCL_TAP_CONTROL_DEFAULT 0x00000000
+-#define mmSCL1_SCL_CONTROL_DEFAULT 0x00000000
+-#define mmSCL1_SCL_BYPASS_CONTROL_DEFAULT 0x00000000
+-#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000
+-#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000
+-#define mmSCL1_SCL_HORZ_FILTER_CONTROL_DEFAULT 0x00000000
+-#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000
+-#define mmSCL1_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000
+-#define mmSCL1_SCL_VERT_FILTER_CONTROL_DEFAULT 0x00000000
+-#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000
+-#define mmSCL1_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000
+-#define mmSCL1_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000
+-#define mmSCL1_SCL_ROUND_OFFSET_DEFAULT 0x80000000
+-#define mmSCL1_SCL_UPDATE_DEFAULT 0x00000000
+-#define mmSCL1_SCL_F_SHARP_CONTROL_DEFAULT 0x00000000
+-#define mmSCL1_SCL_ALU_CONTROL_DEFAULT 0x00000000
+-#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000
+-#define mmSCL1_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000
+-#define mmSCL1_VIEWPORT_START_DEFAULT 0x00000000
+-#define mmSCL1_VIEWPORT_SIZE_DEFAULT 0x00000000
+-#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000
+-#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000
+-#define mmSCL1_SCL_MODE_CHANGE_DET1_DEFAULT 0x00000000
+-#define mmSCL1_SCL_MODE_CHANGE_DET2_DEFAULT 0x00000000
+-#define mmSCL1_SCL_MODE_CHANGE_DET3_DEFAULT 0x00000000
+-#define mmSCL1_SCL_MODE_CHANGE_MASK_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_blnd1_dispdec
+-#define mmBLND1_BLND_CONTROL_DEFAULT 0xff0220ff
+-#define mmBLND1_BLND_SM_CONTROL2_DEFAULT 0x00000000
+-#define mmBLND1_BLND_CONTROL2_DEFAULT 0x00000010
+-#define mmBLND1_BLND_UPDATE_DEFAULT 0x00000000
+-#define mmBLND1_BLND_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000
+-#define mmBLND1_BLND_V_UPDATE_LOCK_DEFAULT 0x80000000
+-#define mmBLND1_BLND_REG_UPDATE_STATUS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_crtc1_dispdec
+-#define mmCRTC1_CRTC_H_BLANK_EARLY_NUM_DEFAULT 0x00000040
+-#define mmCRTC1_CRTC_H_TOTAL_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_H_BLANK_START_END_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_H_SYNC_A_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_H_SYNC_A_CNTL_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_H_SYNC_B_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_H_SYNC_B_CNTL_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_VBI_END_DEFAULT 0x00000003
+-#define mmCRTC1_CRTC_V_TOTAL_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_V_TOTAL_MIN_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_V_TOTAL_MAX_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_V_TOTAL_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_V_BLANK_START_END_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_V_SYNC_A_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_V_SYNC_A_CNTL_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_V_SYNC_B_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_V_SYNC_B_CNTL_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_DTMTEST_CNTL_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_TRIGA_CNTL_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_TRIGB_CNTL_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_FLOW_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_AVSYNC_COUNTER_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_CONTROL_DEFAULT 0x80400110
+-#define mmCRTC1_CRTC_BLANK_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_INTERLACE_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_INTERLACE_STATUS_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_PIXEL_DATA_READBACK0_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_PIXEL_DATA_READBACK1_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_STATUS_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_STATUS_POSITION_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_NOM_VERT_POSITION_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_STATUS_FRAME_COUNT_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_STATUS_VF_COUNT_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_STATUS_HV_COUNT_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_COUNT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_COUNT_RESET_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_VERT_SYNC_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_STEREO_STATUS_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_STEREO_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_SNAPSHOT_STATUS_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_SNAPSHOT_POSITION_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_SNAPSHOT_FRAME_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_START_LINE_CONTROL_DEFAULT 0x00003002
+-#define mmCRTC1_CRTC_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_UPDATE_LOCK_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_TEST_PATTERN_COLOR_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_MASTER_UPDATE_LOCK_DEFAULT 0x00010000
+-#define mmCRTC1_CRTC_MASTER_UPDATE_MODE_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008
+-#define mmCRTC1_CRTC_MVP_STATUS_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_MASTER_EN_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000
+-#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_OVERSCAN_COLOR_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_BLANK_DATA_COLOR_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_BLACK_COLOR_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_BLACK_COLOR_EXT_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_CRC_CNTL_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_CRC0_DATA_RG_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_CRC0_DATA_B_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_CRC1_DATA_RG_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_CRC1_DATA_B_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000
+-#define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010
+-#define mmCRTC1_CRTC_GSL_VSYNC_GAP_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_GSL_WINDOW_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_GSL_CONTROL_DEFAULT 0x00020000
+-#define mmCRTC1_CRTC_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000
+-#define mmCRTC1_CRTC_DRR_CONTROL_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_fmt1_dispdec
+-#define mmFMT1_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000
+-#define mmFMT1_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000
+-#define mmFMT1_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000
+-#define mmFMT1_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000
+-#define mmFMT1_FMT_CONTROL_DEFAULT 0x00000000
+-#define mmFMT1_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000
+-#define mmFMT1_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000
+-#define mmFMT1_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099
+-#define mmFMT1_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd
+-#define mmFMT1_FMT_CLAMP_CNTL_DEFAULT 0x00000000
+-#define mmFMT1_FMT_CRC_CNTL_DEFAULT 0x01000040
+-#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK_DEFAULT 0x00ff00ff
+-#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0x000700ff
+-#define mmFMT1_FMT_CRC_SIG_RED_GREEN_DEFAULT 0x00000000
+-#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_DEFAULT 0x00000000
+-#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000
+-#define mmFMT1_FMT_420_HBLANK_EARLY_START_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dcp2_dispdec
+-#define mmDCP2_GRPH_ENABLE_DEFAULT 0x00000001
+-#define mmDCP2_GRPH_CONTROL_DEFAULT 0x20002040
+-#define mmDCP2_GRPH_LUT_10BIT_BYPASS_DEFAULT 0x00000000
+-#define mmDCP2_GRPH_SWAP_CNTL_DEFAULT 0x00000000
+-#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000
+-#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000
+-#define mmDCP2_GRPH_PITCH_DEFAULT 0x00000000
+-#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+-#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+-#define mmDCP2_GRPH_SURFACE_OFFSET_X_DEFAULT 0x00000000
+-#define mmDCP2_GRPH_SURFACE_OFFSET_Y_DEFAULT 0x00000000
+-#define mmDCP2_GRPH_X_START_DEFAULT 0x00000000
+-#define mmDCP2_GRPH_Y_START_DEFAULT 0x00000000
+-#define mmDCP2_GRPH_X_END_DEFAULT 0x00000000
+-#define mmDCP2_GRPH_Y_END_DEFAULT 0x00000000
+-#define mmDCP2_INPUT_GAMMA_CONTROL_DEFAULT 0x00000000
+-#define mmDCP2_GRPH_UPDATE_DEFAULT 0x00000000
+-#define mmDCP2_GRPH_FLIP_CONTROL_DEFAULT 0x00000020
+-#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE_DEFAULT 0x00000000
+-#define mmDCP2_GRPH_DFQ_CONTROL_DEFAULT 0x00000000
+-#define mmDCP2_GRPH_DFQ_STATUS_DEFAULT 0x00000000
+-#define mmDCP2_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000
+-#define mmDCP2_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE_DEFAULT 0x00000000
+-#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_DEFAULT 0x00000000
+-#define mmDCP2_GRPH_COMPRESS_PITCH_DEFAULT 0x00000000
+-#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+-#define mmDCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x000000ff
+-#define mmDCP2_PRESCALE_GRPH_CONTROL_DEFAULT 0x00000010
+-#define mmDCP2_PRESCALE_VALUES_GRPH_R_DEFAULT 0x20000000
+-#define mmDCP2_PRESCALE_VALUES_GRPH_G_DEFAULT 0x20000000
+-#define mmDCP2_PRESCALE_VALUES_GRPH_B_DEFAULT 0x20000000
+-#define mmDCP2_INPUT_CSC_CONTROL_DEFAULT 0x00000000
+-#define mmDCP2_INPUT_CSC_C11_C12_DEFAULT 0x00002000
+-#define mmDCP2_INPUT_CSC_C13_C14_DEFAULT 0x00000000
+-#define mmDCP2_INPUT_CSC_C21_C22_DEFAULT 0x20000000
+-#define mmDCP2_INPUT_CSC_C23_C24_DEFAULT 0x00000000
+-#define mmDCP2_INPUT_CSC_C31_C32_DEFAULT 0x00000000
+-#define mmDCP2_INPUT_CSC_C33_C34_DEFAULT 0x00002000
+-#define mmDCP2_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000
+-#define mmDCP2_OUTPUT_CSC_C11_C12_DEFAULT 0x00002000
+-#define mmDCP2_OUTPUT_CSC_C13_C14_DEFAULT 0x00000000
+-#define mmDCP2_OUTPUT_CSC_C21_C22_DEFAULT 0x20000000
+-#define mmDCP2_OUTPUT_CSC_C23_C24_DEFAULT 0x00000000
+-#define mmDCP2_OUTPUT_CSC_C31_C32_DEFAULT 0x00000000
+-#define mmDCP2_OUTPUT_CSC_C33_C34_DEFAULT 0x00002000
+-#define mmDCP2_COMM_MATRIXA_TRANS_C11_C12_DEFAULT 0x00002000
+-#define mmDCP2_COMM_MATRIXA_TRANS_C13_C14_DEFAULT 0x00000000
+-#define mmDCP2_COMM_MATRIXA_TRANS_C21_C22_DEFAULT 0x20000000
+-#define mmDCP2_COMM_MATRIXA_TRANS_C23_C24_DEFAULT 0x00000000
+-#define mmDCP2_COMM_MATRIXA_TRANS_C31_C32_DEFAULT 0x00000000
+-#define mmDCP2_COMM_MATRIXA_TRANS_C33_C34_DEFAULT 0x00002000
+-#define mmDCP2_COMM_MATRIXB_TRANS_C11_C12_DEFAULT 0x00002000
+-#define mmDCP2_COMM_MATRIXB_TRANS_C13_C14_DEFAULT 0x00000000
+-#define mmDCP2_COMM_MATRIXB_TRANS_C21_C22_DEFAULT 0x20000000
+-#define mmDCP2_COMM_MATRIXB_TRANS_C23_C24_DEFAULT 0x00000000
+-#define mmDCP2_COMM_MATRIXB_TRANS_C31_C32_DEFAULT 0x00000000
+-#define mmDCP2_COMM_MATRIXB_TRANS_C33_C34_DEFAULT 0x00002000
+-#define mmDCP2_DENORM_CONTROL_DEFAULT 0x00000003
+-#define mmDCP2_OUT_ROUND_CONTROL_DEFAULT 0x0000000a
+-#define mmDCP2_OUT_CLAMP_CONTROL_R_CR_DEFAULT 0x00003fff
+-#define mmDCP2_OUT_CLAMP_CONTROL_G_Y_DEFAULT 0x00003fff
+-#define mmDCP2_OUT_CLAMP_CONTROL_B_CB_DEFAULT 0x00003fff
+-#define mmDCP2_KEY_CONTROL_DEFAULT 0x00000000
+-#define mmDCP2_KEY_RANGE_ALPHA_DEFAULT 0x00000000
+-#define mmDCP2_KEY_RANGE_RED_DEFAULT 0x00000000
+-#define mmDCP2_KEY_RANGE_GREEN_DEFAULT 0x00000000
+-#define mmDCP2_KEY_RANGE_BLUE_DEFAULT 0x00000000
+-#define mmDCP2_DEGAMMA_CONTROL_DEFAULT 0x00000000
+-#define mmDCP2_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000
+-#define mmDCP2_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000
+-#define mmDCP2_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000
+-#define mmDCP2_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000
+-#define mmDCP2_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000
+-#define mmDCP2_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000
+-#define mmDCP2_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000
+-#define mmDCP2_DCP_SPATIAL_DITHER_CNTL_DEFAULT 0x00000000
+-#define mmDCP2_DCP_RANDOM_SEEDS_DEFAULT 0x00000000
+-#define mmDCP2_DCP_FP_CONVERTED_FIELD_DEFAULT 0x00000000
+-#define mmDCP2_CUR_CONTROL_DEFAULT 0x00000810
+-#define mmDCP2_CUR_SURFACE_ADDRESS_DEFAULT 0x00000000
+-#define mmDCP2_CUR_SIZE_DEFAULT 0x00000000
+-#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+-#define mmDCP2_CUR_POSITION_DEFAULT 0x00000000
+-#define mmDCP2_CUR_HOT_SPOT_DEFAULT 0x00000000
+-#define mmDCP2_CUR_COLOR1_DEFAULT 0x00000000
+-#define mmDCP2_CUR_COLOR2_DEFAULT 0x00000000
+-#define mmDCP2_CUR_UPDATE_DEFAULT 0x00000000
+-#define mmDCP2_CUR_REQUEST_FILTER_CNTL_DEFAULT 0x00000000
+-#define mmDCP2_CUR_STEREO_CONTROL_DEFAULT 0x00000000
+-#define mmDCP2_DC_LUT_RW_MODE_DEFAULT 0x00000000
+-#define mmDCP2_DC_LUT_RW_INDEX_DEFAULT 0x00000000
+-#define mmDCP2_DC_LUT_SEQ_COLOR_DEFAULT 0x00000000
+-#define mmDCP2_DC_LUT_PWL_DATA_DEFAULT 0x00000000
+-#define mmDCP2_DC_LUT_30_COLOR_DEFAULT 0x00000000
+-#define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE_DEFAULT 0x00000000
+-#define mmDCP2_DC_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
+-#define mmDCP2_DC_LUT_AUTOFILL_DEFAULT 0x00000000
+-#define mmDCP2_DC_LUT_CONTROL_DEFAULT 0x00000000
+-#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE_DEFAULT 0x00000000
+-#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN_DEFAULT 0x00000000
+-#define mmDCP2_DC_LUT_BLACK_OFFSET_RED_DEFAULT 0x00000000
+-#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE_DEFAULT 0x0000ffff
+-#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN_DEFAULT 0x0000ffff
+-#define mmDCP2_DC_LUT_WHITE_OFFSET_RED_DEFAULT 0x0000ffff
+-#define mmDCP2_DCP_CRC_CONTROL_DEFAULT 0x00000000
+-#define mmDCP2_DCP_CRC_MASK_DEFAULT 0x00000000
+-#define mmDCP2_DCP_CRC_CURRENT_DEFAULT 0x00000000
+-#define mmDCP2_DVMM_PTE_CONTROL_DEFAULT 0x00004000
+-#define mmDCP2_DCP_CRC_LAST_DEFAULT 0x00000000
+-#define mmDCP2_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220
+-#define mmDCP2_GRPH_FLIP_RATE_CNTL_DEFAULT 0x00000000
+-#define mmDCP2_DCP_GSL_CONTROL_DEFAULT 0x60000020
+-#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000035
+-#define mmDCP2_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00000200
+-#define mmDCP2_HW_ROTATION_DEFAULT 0x00000000
+-#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_DEFAULT 0x00000010
+-#define mmDCP2_REGAMMA_CONTROL_DEFAULT 0x00000000
+-#define mmDCP2_REGAMMA_LUT_INDEX_DEFAULT 0x00000000
+-#define mmDCP2_REGAMMA_LUT_DATA_DEFAULT 0x00000000
+-#define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
+-#define mmDCP2_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000
+-#define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000
+-#define mmDCP2_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000
+-#define mmDCP2_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000
+-#define mmDCP2_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000
+-#define mmDCP2_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000
+-#define mmDCP2_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000
+-#define mmDCP2_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000
+-#define mmDCP2_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000
+-#define mmDCP2_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000
+-#define mmDCP2_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000
+-#define mmDCP2_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000
+-#define mmDCP2_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000
+-#define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000
+-#define mmDCP2_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000
+-#define mmDCP2_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000
+-#define mmDCP2_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000
+-#define mmDCP2_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000
+-#define mmDCP2_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000
+-#define mmDCP2_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000
+-#define mmDCP2_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000
+-#define mmDCP2_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000
+-#define mmDCP2_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000
+-#define mmDCP2_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000
+-#define mmDCP2_ALPHA_CONTROL_DEFAULT 0x00000002
+-#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_DEFAULT 0x00000000
+-#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+-#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_DEFAULT 0x00000000
+-#define mmDCP2_GRPH_XDMA_FLIP_TIMEOUT_DEFAULT 0x00000000
+-#define mmDCP2_GRPH_XDMA_FLIP_AVG_DELAY_DEFAULT 0x00000000
+-#define mmDCP2_GRPH_SURFACE_COUNTER_CONTROL_DEFAULT 0x00000012
+-#define mmDCP2_GRPH_SURFACE_COUNTER_OUTPUT_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_lb2_dispdec
+-#define mmLB2_LB_DATA_FORMAT_DEFAULT 0x00000000
+-#define mmLB2_LB_MEMORY_CTRL_DEFAULT 0x000006b0
+-#define mmLB2_LB_MEMORY_SIZE_STATUS_DEFAULT 0x00000000
+-#define mmLB2_LB_DESKTOP_HEIGHT_DEFAULT 0x00000000
+-#define mmLB2_LB_VLINE_START_END_DEFAULT 0x00000000
+-#define mmLB2_LB_VLINE2_START_END_DEFAULT 0x00000000
+-#define mmLB2_LB_V_COUNTER_DEFAULT 0x00000000
+-#define mmLB2_LB_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000
+-#define mmLB2_LB_INTERRUPT_MASK_DEFAULT 0x00000000
+-#define mmLB2_LB_VLINE_STATUS_DEFAULT 0x00000000
+-#define mmLB2_LB_VLINE2_STATUS_DEFAULT 0x00000000
+-#define mmLB2_LB_VBLANK_STATUS_DEFAULT 0x00000000
+-#define mmLB2_LB_SYNC_RESET_SEL_DEFAULT 0x00000002
+-#define mmLB2_LB_BLACK_KEYER_R_CR_DEFAULT 0x00000000
+-#define mmLB2_LB_BLACK_KEYER_G_Y_DEFAULT 0x00000000
+-#define mmLB2_LB_BLACK_KEYER_B_CB_DEFAULT 0x00000000
+-#define mmLB2_LB_KEYER_COLOR_CTRL_DEFAULT 0x00000000
+-#define mmLB2_LB_KEYER_COLOR_R_CR_DEFAULT 0x00000000
+-#define mmLB2_LB_KEYER_COLOR_G_Y_DEFAULT 0x00000000
+-#define mmLB2_LB_KEYER_COLOR_B_CB_DEFAULT 0x00000000
+-#define mmLB2_LB_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000
+-#define mmLB2_LB_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000
+-#define mmLB2_LB_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000
+-#define mmLB2_LB_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000
+-#define mmLB2_LB_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010
+-#define mmLB2_LB_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000
+-#define mmLB2_LB_BUFFER_STATUS_DEFAULT 0x00000002
+-#define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000
+-#define mmLB2_MVP_AFR_FLIP_MODE_DEFAULT 0x00000000
+-#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL_DEFAULT 0x00000000
+-#define mmLB2_MVP_FLIP_LINE_NUM_INSERT_DEFAULT 0x00000002
+-#define mmLB2_DC_MVP_LB_CONTROL_DEFAULT 0x00000001
+-
+-
+-// addressBlock: dce_dc_dcfe2_dispdec
+-#define mmDCFE2_DCFE_CLOCK_CONTROL_DEFAULT 0x00000000
+-#define mmDCFE2_DCFE_SOFT_RESET_DEFAULT 0x00000000
+-#define mmDCFE2_DCFE_MEM_PWR_CTRL_DEFAULT 0x00000000
+-#define mmDCFE2_DCFE_MEM_PWR_CTRL2_DEFAULT 0x00000000
+-#define mmDCFE2_DCFE_MEM_PWR_STATUS_DEFAULT 0x00000000
+-#define mmDCFE2_DCFE_MISC_DEFAULT 0x00000001
+-#define mmDCFE2_DCFE_FLUSH_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dc_perfmon5_dispdec
+-#define mmDC_PERFMON5_PERFCOUNTER_CNTL_DEFAULT 0x00000000
+-#define mmDC_PERFMON5_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
+-#define mmDC_PERFMON5_PERFCOUNTER_STATE_DEFAULT 0x00000000
+-#define mmDC_PERFMON5_PERFMON_CNTL_DEFAULT 0x00000100
+-#define mmDC_PERFMON5_PERFMON_CNTL2_DEFAULT 0x00000000
+-#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
+-#define mmDC_PERFMON5_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
+-#define mmDC_PERFMON5_PERFMON_HI_DEFAULT 0x00000000
+-#define mmDC_PERFMON5_PERFMON_LOW_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dmif_pg2_dispdec
+-#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000
+-#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000
+-#define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL_DEFAULT 0x000bf777
+-#define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000
+-#define mmDMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL_DEFAULT 0x00000000
+-#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_DEFAULT 0x00000000
+-#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL2_DEFAULT 0x00000000
+-#define mmDMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL_DEFAULT 0x00000000
+-#define mmDMIF_PG2_DPG_REPEATER_PROGRAM_DEFAULT 0x00000000
+-#define mmDMIF_PG2_DPG_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000
+-#define mmDMIF_PG2_DPG_DVMM_STATUS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_scl2_dispdec
+-#define mmSCL2_SCL_COEF_RAM_SELECT_DEFAULT 0x00000000
+-#define mmSCL2_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000
+-#define mmSCL2_SCL_MODE_DEFAULT 0x00000000
+-#define mmSCL2_SCL_TAP_CONTROL_DEFAULT 0x00000000
+-#define mmSCL2_SCL_CONTROL_DEFAULT 0x00000000
+-#define mmSCL2_SCL_BYPASS_CONTROL_DEFAULT 0x00000000
+-#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000
+-#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000
+-#define mmSCL2_SCL_HORZ_FILTER_CONTROL_DEFAULT 0x00000000
+-#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000
+-#define mmSCL2_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000
+-#define mmSCL2_SCL_VERT_FILTER_CONTROL_DEFAULT 0x00000000
+-#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000
+-#define mmSCL2_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000
+-#define mmSCL2_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000
+-#define mmSCL2_SCL_ROUND_OFFSET_DEFAULT 0x80000000
+-#define mmSCL2_SCL_UPDATE_DEFAULT 0x00000000
+-#define mmSCL2_SCL_F_SHARP_CONTROL_DEFAULT 0x00000000
+-#define mmSCL2_SCL_ALU_CONTROL_DEFAULT 0x00000000
+-#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000
+-#define mmSCL2_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000
+-#define mmSCL2_VIEWPORT_START_DEFAULT 0x00000000
+-#define mmSCL2_VIEWPORT_SIZE_DEFAULT 0x00000000
+-#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000
+-#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000
+-#define mmSCL2_SCL_MODE_CHANGE_DET1_DEFAULT 0x00000000
+-#define mmSCL2_SCL_MODE_CHANGE_DET2_DEFAULT 0x00000000
+-#define mmSCL2_SCL_MODE_CHANGE_DET3_DEFAULT 0x00000000
+-#define mmSCL2_SCL_MODE_CHANGE_MASK_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_blnd2_dispdec
+-#define mmBLND2_BLND_CONTROL_DEFAULT 0xff0220ff
+-#define mmBLND2_BLND_SM_CONTROL2_DEFAULT 0x00000000
+-#define mmBLND2_BLND_CONTROL2_DEFAULT 0x00000010
+-#define mmBLND2_BLND_UPDATE_DEFAULT 0x00000000
+-#define mmBLND2_BLND_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000
+-#define mmBLND2_BLND_V_UPDATE_LOCK_DEFAULT 0x80000000
+-#define mmBLND2_BLND_REG_UPDATE_STATUS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_crtc2_dispdec
+-#define mmCRTC2_CRTC_H_BLANK_EARLY_NUM_DEFAULT 0x00000040
+-#define mmCRTC2_CRTC_H_TOTAL_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_H_BLANK_START_END_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_H_SYNC_A_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_H_SYNC_A_CNTL_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_H_SYNC_B_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_H_SYNC_B_CNTL_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_VBI_END_DEFAULT 0x00000003
+-#define mmCRTC2_CRTC_V_TOTAL_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_V_TOTAL_MIN_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_V_TOTAL_MAX_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_V_TOTAL_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_V_BLANK_START_END_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_V_SYNC_A_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_V_SYNC_A_CNTL_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_V_SYNC_B_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_V_SYNC_B_CNTL_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_DTMTEST_CNTL_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_TRIGA_CNTL_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_TRIGB_CNTL_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_FLOW_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_AVSYNC_COUNTER_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_CONTROL_DEFAULT 0x80400110
+-#define mmCRTC2_CRTC_BLANK_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_INTERLACE_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_INTERLACE_STATUS_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_PIXEL_DATA_READBACK0_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_PIXEL_DATA_READBACK1_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_STATUS_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_STATUS_POSITION_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_NOM_VERT_POSITION_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_STATUS_FRAME_COUNT_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_STATUS_VF_COUNT_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_STATUS_HV_COUNT_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_COUNT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_COUNT_RESET_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_VERT_SYNC_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_STEREO_STATUS_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_STEREO_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_SNAPSHOT_STATUS_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_SNAPSHOT_POSITION_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_SNAPSHOT_FRAME_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_START_LINE_CONTROL_DEFAULT 0x00003002
+-#define mmCRTC2_CRTC_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_UPDATE_LOCK_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_TEST_PATTERN_COLOR_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_MASTER_UPDATE_LOCK_DEFAULT 0x00010000
+-#define mmCRTC2_CRTC_MASTER_UPDATE_MODE_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008
+-#define mmCRTC2_CRTC_MVP_STATUS_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_MASTER_EN_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000
+-#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_OVERSCAN_COLOR_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_BLANK_DATA_COLOR_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_BLACK_COLOR_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_BLACK_COLOR_EXT_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_CRC_CNTL_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_CRC0_DATA_RG_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_CRC0_DATA_B_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_CRC1_DATA_RG_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_CRC1_DATA_B_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000
+-#define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010
+-#define mmCRTC2_CRTC_GSL_VSYNC_GAP_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_GSL_WINDOW_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_GSL_CONTROL_DEFAULT 0x00020000
+-#define mmCRTC2_CRTC_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000
+-#define mmCRTC2_CRTC_DRR_CONTROL_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_fmt2_dispdec
+-#define mmFMT2_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000
+-#define mmFMT2_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000
+-#define mmFMT2_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000
+-#define mmFMT2_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000
+-#define mmFMT2_FMT_CONTROL_DEFAULT 0x00000000
+-#define mmFMT2_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000
+-#define mmFMT2_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000
+-#define mmFMT2_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099
+-#define mmFMT2_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd
+-#define mmFMT2_FMT_CLAMP_CNTL_DEFAULT 0x00000000
+-#define mmFMT2_FMT_CRC_CNTL_DEFAULT 0x01000040
+-#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK_DEFAULT 0x00ff00ff
+-#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0x000700ff
+-#define mmFMT2_FMT_CRC_SIG_RED_GREEN_DEFAULT 0x00000000
+-#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_DEFAULT 0x00000000
+-#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000
+-#define mmFMT2_FMT_420_HBLANK_EARLY_START_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dcp3_dispdec
+-#define mmDCP3_GRPH_ENABLE_DEFAULT 0x00000001
+-#define mmDCP3_GRPH_CONTROL_DEFAULT 0x20002040
+-#define mmDCP3_GRPH_LUT_10BIT_BYPASS_DEFAULT 0x00000000
+-#define mmDCP3_GRPH_SWAP_CNTL_DEFAULT 0x00000000
+-#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000
+-#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000
+-#define mmDCP3_GRPH_PITCH_DEFAULT 0x00000000
+-#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+-#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+-#define mmDCP3_GRPH_SURFACE_OFFSET_X_DEFAULT 0x00000000
+-#define mmDCP3_GRPH_SURFACE_OFFSET_Y_DEFAULT 0x00000000
+-#define mmDCP3_GRPH_X_START_DEFAULT 0x00000000
+-#define mmDCP3_GRPH_Y_START_DEFAULT 0x00000000
+-#define mmDCP3_GRPH_X_END_DEFAULT 0x00000000
+-#define mmDCP3_GRPH_Y_END_DEFAULT 0x00000000
+-#define mmDCP3_INPUT_GAMMA_CONTROL_DEFAULT 0x00000000
+-#define mmDCP3_GRPH_UPDATE_DEFAULT 0x00000000
+-#define mmDCP3_GRPH_FLIP_CONTROL_DEFAULT 0x00000020
+-#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE_DEFAULT 0x00000000
+-#define mmDCP3_GRPH_DFQ_CONTROL_DEFAULT 0x00000000
+-#define mmDCP3_GRPH_DFQ_STATUS_DEFAULT 0x00000000
+-#define mmDCP3_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000
+-#define mmDCP3_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE_DEFAULT 0x00000000
+-#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_DEFAULT 0x00000000
+-#define mmDCP3_GRPH_COMPRESS_PITCH_DEFAULT 0x00000000
+-#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+-#define mmDCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x000000ff
+-#define mmDCP3_PRESCALE_GRPH_CONTROL_DEFAULT 0x00000010
+-#define mmDCP3_PRESCALE_VALUES_GRPH_R_DEFAULT 0x20000000
+-#define mmDCP3_PRESCALE_VALUES_GRPH_G_DEFAULT 0x20000000
+-#define mmDCP3_PRESCALE_VALUES_GRPH_B_DEFAULT 0x20000000
+-#define mmDCP3_INPUT_CSC_CONTROL_DEFAULT 0x00000000
+-#define mmDCP3_INPUT_CSC_C11_C12_DEFAULT 0x00002000
+-#define mmDCP3_INPUT_CSC_C13_C14_DEFAULT 0x00000000
+-#define mmDCP3_INPUT_CSC_C21_C22_DEFAULT 0x20000000
+-#define mmDCP3_INPUT_CSC_C23_C24_DEFAULT 0x00000000
+-#define mmDCP3_INPUT_CSC_C31_C32_DEFAULT 0x00000000
+-#define mmDCP3_INPUT_CSC_C33_C34_DEFAULT 0x00002000
+-#define mmDCP3_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000
+-#define mmDCP3_OUTPUT_CSC_C11_C12_DEFAULT 0x00002000
+-#define mmDCP3_OUTPUT_CSC_C13_C14_DEFAULT 0x00000000
+-#define mmDCP3_OUTPUT_CSC_C21_C22_DEFAULT 0x20000000
+-#define mmDCP3_OUTPUT_CSC_C23_C24_DEFAULT 0x00000000
+-#define mmDCP3_OUTPUT_CSC_C31_C32_DEFAULT 0x00000000
+-#define mmDCP3_OUTPUT_CSC_C33_C34_DEFAULT 0x00002000
+-#define mmDCP3_COMM_MATRIXA_TRANS_C11_C12_DEFAULT 0x00002000
+-#define mmDCP3_COMM_MATRIXA_TRANS_C13_C14_DEFAULT 0x00000000
+-#define mmDCP3_COMM_MATRIXA_TRANS_C21_C22_DEFAULT 0x20000000
+-#define mmDCP3_COMM_MATRIXA_TRANS_C23_C24_DEFAULT 0x00000000
+-#define mmDCP3_COMM_MATRIXA_TRANS_C31_C32_DEFAULT 0x00000000
+-#define mmDCP3_COMM_MATRIXA_TRANS_C33_C34_DEFAULT 0x00002000
+-#define mmDCP3_COMM_MATRIXB_TRANS_C11_C12_DEFAULT 0x00002000
+-#define mmDCP3_COMM_MATRIXB_TRANS_C13_C14_DEFAULT 0x00000000
+-#define mmDCP3_COMM_MATRIXB_TRANS_C21_C22_DEFAULT 0x20000000
+-#define mmDCP3_COMM_MATRIXB_TRANS_C23_C24_DEFAULT 0x00000000
+-#define mmDCP3_COMM_MATRIXB_TRANS_C31_C32_DEFAULT 0x00000000
+-#define mmDCP3_COMM_MATRIXB_TRANS_C33_C34_DEFAULT 0x00002000
+-#define mmDCP3_DENORM_CONTROL_DEFAULT 0x00000003
+-#define mmDCP3_OUT_ROUND_CONTROL_DEFAULT 0x0000000a
+-#define mmDCP3_OUT_CLAMP_CONTROL_R_CR_DEFAULT 0x00003fff
+-#define mmDCP3_OUT_CLAMP_CONTROL_G_Y_DEFAULT 0x00003fff
+-#define mmDCP3_OUT_CLAMP_CONTROL_B_CB_DEFAULT 0x00003fff
+-#define mmDCP3_KEY_CONTROL_DEFAULT 0x00000000
+-#define mmDCP3_KEY_RANGE_ALPHA_DEFAULT 0x00000000
+-#define mmDCP3_KEY_RANGE_RED_DEFAULT 0x00000000
+-#define mmDCP3_KEY_RANGE_GREEN_DEFAULT 0x00000000
+-#define mmDCP3_KEY_RANGE_BLUE_DEFAULT 0x00000000
+-#define mmDCP3_DEGAMMA_CONTROL_DEFAULT 0x00000000
+-#define mmDCP3_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000
+-#define mmDCP3_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000
+-#define mmDCP3_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000
+-#define mmDCP3_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000
+-#define mmDCP3_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000
+-#define mmDCP3_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000
+-#define mmDCP3_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000
+-#define mmDCP3_DCP_SPATIAL_DITHER_CNTL_DEFAULT 0x00000000
+-#define mmDCP3_DCP_RANDOM_SEEDS_DEFAULT 0x00000000
+-#define mmDCP3_DCP_FP_CONVERTED_FIELD_DEFAULT 0x00000000
+-#define mmDCP3_CUR_CONTROL_DEFAULT 0x00000810
+-#define mmDCP3_CUR_SURFACE_ADDRESS_DEFAULT 0x00000000
+-#define mmDCP3_CUR_SIZE_DEFAULT 0x00000000
+-#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+-#define mmDCP3_CUR_POSITION_DEFAULT 0x00000000
+-#define mmDCP3_CUR_HOT_SPOT_DEFAULT 0x00000000
+-#define mmDCP3_CUR_COLOR1_DEFAULT 0x00000000
+-#define mmDCP3_CUR_COLOR2_DEFAULT 0x00000000
+-#define mmDCP3_CUR_UPDATE_DEFAULT 0x00000000
+-#define mmDCP3_CUR_REQUEST_FILTER_CNTL_DEFAULT 0x00000000
+-#define mmDCP3_CUR_STEREO_CONTROL_DEFAULT 0x00000000
+-#define mmDCP3_DC_LUT_RW_MODE_DEFAULT 0x00000000
+-#define mmDCP3_DC_LUT_RW_INDEX_DEFAULT 0x00000000
+-#define mmDCP3_DC_LUT_SEQ_COLOR_DEFAULT 0x00000000
+-#define mmDCP3_DC_LUT_PWL_DATA_DEFAULT 0x00000000
+-#define mmDCP3_DC_LUT_30_COLOR_DEFAULT 0x00000000
+-#define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE_DEFAULT 0x00000000
+-#define mmDCP3_DC_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
+-#define mmDCP3_DC_LUT_AUTOFILL_DEFAULT 0x00000000
+-#define mmDCP3_DC_LUT_CONTROL_DEFAULT 0x00000000
+-#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE_DEFAULT 0x00000000
+-#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN_DEFAULT 0x00000000
+-#define mmDCP3_DC_LUT_BLACK_OFFSET_RED_DEFAULT 0x00000000
+-#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE_DEFAULT 0x0000ffff
+-#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN_DEFAULT 0x0000ffff
+-#define mmDCP3_DC_LUT_WHITE_OFFSET_RED_DEFAULT 0x0000ffff
+-#define mmDCP3_DCP_CRC_CONTROL_DEFAULT 0x00000000
+-#define mmDCP3_DCP_CRC_MASK_DEFAULT 0x00000000
+-#define mmDCP3_DCP_CRC_CURRENT_DEFAULT 0x00000000
+-#define mmDCP3_DVMM_PTE_CONTROL_DEFAULT 0x00004000
+-#define mmDCP3_DCP_CRC_LAST_DEFAULT 0x00000000
+-#define mmDCP3_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220
+-#define mmDCP3_GRPH_FLIP_RATE_CNTL_DEFAULT 0x00000000
+-#define mmDCP3_DCP_GSL_CONTROL_DEFAULT 0x60000020
+-#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000035
+-#define mmDCP3_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00000200
+-#define mmDCP3_HW_ROTATION_DEFAULT 0x00000000
+-#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_DEFAULT 0x00000010
+-#define mmDCP3_REGAMMA_CONTROL_DEFAULT 0x00000000
+-#define mmDCP3_REGAMMA_LUT_INDEX_DEFAULT 0x00000000
+-#define mmDCP3_REGAMMA_LUT_DATA_DEFAULT 0x00000000
+-#define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
+-#define mmDCP3_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000
+-#define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000
+-#define mmDCP3_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000
+-#define mmDCP3_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000
+-#define mmDCP3_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000
+-#define mmDCP3_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000
+-#define mmDCP3_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000
+-#define mmDCP3_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000
+-#define mmDCP3_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000
+-#define mmDCP3_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000
+-#define mmDCP3_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000
+-#define mmDCP3_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000
+-#define mmDCP3_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000
+-#define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000
+-#define mmDCP3_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000
+-#define mmDCP3_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000
+-#define mmDCP3_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000
+-#define mmDCP3_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000
+-#define mmDCP3_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000
+-#define mmDCP3_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000
+-#define mmDCP3_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000
+-#define mmDCP3_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000
+-#define mmDCP3_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000
+-#define mmDCP3_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000
+-#define mmDCP3_ALPHA_CONTROL_DEFAULT 0x00000002
+-#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_DEFAULT 0x00000000
+-#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+-#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_DEFAULT 0x00000000
+-#define mmDCP3_GRPH_XDMA_FLIP_TIMEOUT_DEFAULT 0x00000000
+-#define mmDCP3_GRPH_XDMA_FLIP_AVG_DELAY_DEFAULT 0x00000000
+-#define mmDCP3_GRPH_SURFACE_COUNTER_CONTROL_DEFAULT 0x00000012
+-#define mmDCP3_GRPH_SURFACE_COUNTER_OUTPUT_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_lb3_dispdec
+-#define mmLB3_LB_DATA_FORMAT_DEFAULT 0x00000000
+-#define mmLB3_LB_MEMORY_CTRL_DEFAULT 0x000006b0
+-#define mmLB3_LB_MEMORY_SIZE_STATUS_DEFAULT 0x00000000
+-#define mmLB3_LB_DESKTOP_HEIGHT_DEFAULT 0x00000000
+-#define mmLB3_LB_VLINE_START_END_DEFAULT 0x00000000
+-#define mmLB3_LB_VLINE2_START_END_DEFAULT 0x00000000
+-#define mmLB3_LB_V_COUNTER_DEFAULT 0x00000000
+-#define mmLB3_LB_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000
+-#define mmLB3_LB_INTERRUPT_MASK_DEFAULT 0x00000000
+-#define mmLB3_LB_VLINE_STATUS_DEFAULT 0x00000000
+-#define mmLB3_LB_VLINE2_STATUS_DEFAULT 0x00000000
+-#define mmLB3_LB_VBLANK_STATUS_DEFAULT 0x00000000
+-#define mmLB3_LB_SYNC_RESET_SEL_DEFAULT 0x00000002
+-#define mmLB3_LB_BLACK_KEYER_R_CR_DEFAULT 0x00000000
+-#define mmLB3_LB_BLACK_KEYER_G_Y_DEFAULT 0x00000000
+-#define mmLB3_LB_BLACK_KEYER_B_CB_DEFAULT 0x00000000
+-#define mmLB3_LB_KEYER_COLOR_CTRL_DEFAULT 0x00000000
+-#define mmLB3_LB_KEYER_COLOR_R_CR_DEFAULT 0x00000000
+-#define mmLB3_LB_KEYER_COLOR_G_Y_DEFAULT 0x00000000
+-#define mmLB3_LB_KEYER_COLOR_B_CB_DEFAULT 0x00000000
+-#define mmLB3_LB_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000
+-#define mmLB3_LB_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000
+-#define mmLB3_LB_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000
+-#define mmLB3_LB_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000
+-#define mmLB3_LB_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010
+-#define mmLB3_LB_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000
+-#define mmLB3_LB_BUFFER_STATUS_DEFAULT 0x00000002
+-#define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000
+-#define mmLB3_MVP_AFR_FLIP_MODE_DEFAULT 0x00000000
+-#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL_DEFAULT 0x00000000
+-#define mmLB3_MVP_FLIP_LINE_NUM_INSERT_DEFAULT 0x00000002
+-#define mmLB3_DC_MVP_LB_CONTROL_DEFAULT 0x00000001
+-
+-
+-// addressBlock: dce_dc_dcfe3_dispdec
+-#define mmDCFE3_DCFE_CLOCK_CONTROL_DEFAULT 0x00000000
+-#define mmDCFE3_DCFE_SOFT_RESET_DEFAULT 0x00000000
+-#define mmDCFE3_DCFE_MEM_PWR_CTRL_DEFAULT 0x00000000
+-#define mmDCFE3_DCFE_MEM_PWR_CTRL2_DEFAULT 0x00000000
+-#define mmDCFE3_DCFE_MEM_PWR_STATUS_DEFAULT 0x00000000
+-#define mmDCFE3_DCFE_MISC_DEFAULT 0x00000001
+-#define mmDCFE3_DCFE_FLUSH_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dc_perfmon6_dispdec
+-#define mmDC_PERFMON6_PERFCOUNTER_CNTL_DEFAULT 0x00000000
+-#define mmDC_PERFMON6_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
+-#define mmDC_PERFMON6_PERFCOUNTER_STATE_DEFAULT 0x00000000
+-#define mmDC_PERFMON6_PERFMON_CNTL_DEFAULT 0x00000100
+-#define mmDC_PERFMON6_PERFMON_CNTL2_DEFAULT 0x00000000
+-#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
+-#define mmDC_PERFMON6_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
+-#define mmDC_PERFMON6_PERFMON_HI_DEFAULT 0x00000000
+-#define mmDC_PERFMON6_PERFMON_LOW_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dmif_pg3_dispdec
+-#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000
+-#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000
+-#define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL_DEFAULT 0x000bf777
+-#define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000
+-#define mmDMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL_DEFAULT 0x00000000
+-#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_DEFAULT 0x00000000
+-#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL2_DEFAULT 0x00000000
+-#define mmDMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL_DEFAULT 0x00000000
+-#define mmDMIF_PG3_DPG_REPEATER_PROGRAM_DEFAULT 0x00000000
+-#define mmDMIF_PG3_DPG_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000
+-#define mmDMIF_PG3_DPG_DVMM_STATUS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_scl3_dispdec
+-#define mmSCL3_SCL_COEF_RAM_SELECT_DEFAULT 0x00000000
+-#define mmSCL3_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000
+-#define mmSCL3_SCL_MODE_DEFAULT 0x00000000
+-#define mmSCL3_SCL_TAP_CONTROL_DEFAULT 0x00000000
+-#define mmSCL3_SCL_CONTROL_DEFAULT 0x00000000
+-#define mmSCL3_SCL_BYPASS_CONTROL_DEFAULT 0x00000000
+-#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000
+-#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000
+-#define mmSCL3_SCL_HORZ_FILTER_CONTROL_DEFAULT 0x00000000
+-#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000
+-#define mmSCL3_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000
+-#define mmSCL3_SCL_VERT_FILTER_CONTROL_DEFAULT 0x00000000
+-#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000
+-#define mmSCL3_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000
+-#define mmSCL3_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000
+-#define mmSCL3_SCL_ROUND_OFFSET_DEFAULT 0x80000000
+-#define mmSCL3_SCL_UPDATE_DEFAULT 0x00000000
+-#define mmSCL3_SCL_F_SHARP_CONTROL_DEFAULT 0x00000000
+-#define mmSCL3_SCL_ALU_CONTROL_DEFAULT 0x00000000
+-#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000
+-#define mmSCL3_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000
+-#define mmSCL3_VIEWPORT_START_DEFAULT 0x00000000
+-#define mmSCL3_VIEWPORT_SIZE_DEFAULT 0x00000000
+-#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000
+-#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000
+-#define mmSCL3_SCL_MODE_CHANGE_DET1_DEFAULT 0x00000000
+-#define mmSCL3_SCL_MODE_CHANGE_DET2_DEFAULT 0x00000000
+-#define mmSCL3_SCL_MODE_CHANGE_DET3_DEFAULT 0x00000000
+-#define mmSCL3_SCL_MODE_CHANGE_MASK_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_blnd3_dispdec
+-#define mmBLND3_BLND_CONTROL_DEFAULT 0xff0220ff
+-#define mmBLND3_BLND_SM_CONTROL2_DEFAULT 0x00000000
+-#define mmBLND3_BLND_CONTROL2_DEFAULT 0x00000010
+-#define mmBLND3_BLND_UPDATE_DEFAULT 0x00000000
+-#define mmBLND3_BLND_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000
+-#define mmBLND3_BLND_V_UPDATE_LOCK_DEFAULT 0x80000000
+-#define mmBLND3_BLND_REG_UPDATE_STATUS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_crtc3_dispdec
+-#define mmCRTC3_CRTC_H_BLANK_EARLY_NUM_DEFAULT 0x00000040
+-#define mmCRTC3_CRTC_H_TOTAL_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_H_BLANK_START_END_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_H_SYNC_A_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_H_SYNC_A_CNTL_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_H_SYNC_B_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_H_SYNC_B_CNTL_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_VBI_END_DEFAULT 0x00000003
+-#define mmCRTC3_CRTC_V_TOTAL_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_V_TOTAL_MIN_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_V_TOTAL_MAX_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_V_TOTAL_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_V_BLANK_START_END_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_V_SYNC_A_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_V_SYNC_A_CNTL_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_V_SYNC_B_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_V_SYNC_B_CNTL_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_DTMTEST_CNTL_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_TRIGA_CNTL_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_TRIGB_CNTL_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_FLOW_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_AVSYNC_COUNTER_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_CONTROL_DEFAULT 0x80400110
+-#define mmCRTC3_CRTC_BLANK_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_INTERLACE_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_INTERLACE_STATUS_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_PIXEL_DATA_READBACK0_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_PIXEL_DATA_READBACK1_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_STATUS_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_STATUS_POSITION_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_NOM_VERT_POSITION_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_STATUS_FRAME_COUNT_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_STATUS_VF_COUNT_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_STATUS_HV_COUNT_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_COUNT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_COUNT_RESET_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_VERT_SYNC_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_STEREO_STATUS_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_STEREO_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_SNAPSHOT_STATUS_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_SNAPSHOT_POSITION_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_SNAPSHOT_FRAME_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_START_LINE_CONTROL_DEFAULT 0x00003002
+-#define mmCRTC3_CRTC_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_UPDATE_LOCK_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_TEST_PATTERN_COLOR_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_MASTER_UPDATE_LOCK_DEFAULT 0x00010000
+-#define mmCRTC3_CRTC_MASTER_UPDATE_MODE_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008
+-#define mmCRTC3_CRTC_MVP_STATUS_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_MASTER_EN_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000
+-#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_OVERSCAN_COLOR_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_BLANK_DATA_COLOR_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_BLACK_COLOR_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_BLACK_COLOR_EXT_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_CRC_CNTL_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_CRC0_DATA_RG_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_CRC0_DATA_B_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_CRC1_DATA_RG_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_CRC1_DATA_B_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000
+-#define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010
+-#define mmCRTC3_CRTC_GSL_VSYNC_GAP_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_GSL_WINDOW_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_GSL_CONTROL_DEFAULT 0x00020000
+-#define mmCRTC3_CRTC_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000
+-#define mmCRTC3_CRTC_DRR_CONTROL_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_fmt3_dispdec
+-#define mmFMT3_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000
+-#define mmFMT3_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000
+-#define mmFMT3_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000
+-#define mmFMT3_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000
+-#define mmFMT3_FMT_CONTROL_DEFAULT 0x00000000
+-#define mmFMT3_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000
+-#define mmFMT3_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000
+-#define mmFMT3_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099
+-#define mmFMT3_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd
+-#define mmFMT3_FMT_CLAMP_CNTL_DEFAULT 0x00000000
+-#define mmFMT3_FMT_CRC_CNTL_DEFAULT 0x01000040
+-#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK_DEFAULT 0x00ff00ff
+-#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0x000700ff
+-#define mmFMT3_FMT_CRC_SIG_RED_GREEN_DEFAULT 0x00000000
+-#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_DEFAULT 0x00000000
+-#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000
+-#define mmFMT3_FMT_420_HBLANK_EARLY_START_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dcp4_dispdec
+-#define mmDCP4_GRPH_ENABLE_DEFAULT 0x00000001
+-#define mmDCP4_GRPH_CONTROL_DEFAULT 0x20002040
+-#define mmDCP4_GRPH_LUT_10BIT_BYPASS_DEFAULT 0x00000000
+-#define mmDCP4_GRPH_SWAP_CNTL_DEFAULT 0x00000000
+-#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000
+-#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000
+-#define mmDCP4_GRPH_PITCH_DEFAULT 0x00000000
+-#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+-#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+-#define mmDCP4_GRPH_SURFACE_OFFSET_X_DEFAULT 0x00000000
+-#define mmDCP4_GRPH_SURFACE_OFFSET_Y_DEFAULT 0x00000000
+-#define mmDCP4_GRPH_X_START_DEFAULT 0x00000000
+-#define mmDCP4_GRPH_Y_START_DEFAULT 0x00000000
+-#define mmDCP4_GRPH_X_END_DEFAULT 0x00000000
+-#define mmDCP4_GRPH_Y_END_DEFAULT 0x00000000
+-#define mmDCP4_INPUT_GAMMA_CONTROL_DEFAULT 0x00000000
+-#define mmDCP4_GRPH_UPDATE_DEFAULT 0x00000000
+-#define mmDCP4_GRPH_FLIP_CONTROL_DEFAULT 0x00000020
+-#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE_DEFAULT 0x00000000
+-#define mmDCP4_GRPH_DFQ_CONTROL_DEFAULT 0x00000000
+-#define mmDCP4_GRPH_DFQ_STATUS_DEFAULT 0x00000000
+-#define mmDCP4_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000
+-#define mmDCP4_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE_DEFAULT 0x00000000
+-#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_DEFAULT 0x00000000
+-#define mmDCP4_GRPH_COMPRESS_PITCH_DEFAULT 0x00000000
+-#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+-#define mmDCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x000000ff
+-#define mmDCP4_PRESCALE_GRPH_CONTROL_DEFAULT 0x00000010
+-#define mmDCP4_PRESCALE_VALUES_GRPH_R_DEFAULT 0x20000000
+-#define mmDCP4_PRESCALE_VALUES_GRPH_G_DEFAULT 0x20000000
+-#define mmDCP4_PRESCALE_VALUES_GRPH_B_DEFAULT 0x20000000
+-#define mmDCP4_INPUT_CSC_CONTROL_DEFAULT 0x00000000
+-#define mmDCP4_INPUT_CSC_C11_C12_DEFAULT 0x00002000
+-#define mmDCP4_INPUT_CSC_C13_C14_DEFAULT 0x00000000
+-#define mmDCP4_INPUT_CSC_C21_C22_DEFAULT 0x20000000
+-#define mmDCP4_INPUT_CSC_C23_C24_DEFAULT 0x00000000
+-#define mmDCP4_INPUT_CSC_C31_C32_DEFAULT 0x00000000
+-#define mmDCP4_INPUT_CSC_C33_C34_DEFAULT 0x00002000
+-#define mmDCP4_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000
+-#define mmDCP4_OUTPUT_CSC_C11_C12_DEFAULT 0x00002000
+-#define mmDCP4_OUTPUT_CSC_C13_C14_DEFAULT 0x00000000
+-#define mmDCP4_OUTPUT_CSC_C21_C22_DEFAULT 0x20000000
+-#define mmDCP4_OUTPUT_CSC_C23_C24_DEFAULT 0x00000000
+-#define mmDCP4_OUTPUT_CSC_C31_C32_DEFAULT 0x00000000
+-#define mmDCP4_OUTPUT_CSC_C33_C34_DEFAULT 0x00002000
+-#define mmDCP4_COMM_MATRIXA_TRANS_C11_C12_DEFAULT 0x00002000
+-#define mmDCP4_COMM_MATRIXA_TRANS_C13_C14_DEFAULT 0x00000000
+-#define mmDCP4_COMM_MATRIXA_TRANS_C21_C22_DEFAULT 0x20000000
+-#define mmDCP4_COMM_MATRIXA_TRANS_C23_C24_DEFAULT 0x00000000
+-#define mmDCP4_COMM_MATRIXA_TRANS_C31_C32_DEFAULT 0x00000000
+-#define mmDCP4_COMM_MATRIXA_TRANS_C33_C34_DEFAULT 0x00002000
+-#define mmDCP4_COMM_MATRIXB_TRANS_C11_C12_DEFAULT 0x00002000
+-#define mmDCP4_COMM_MATRIXB_TRANS_C13_C14_DEFAULT 0x00000000
+-#define mmDCP4_COMM_MATRIXB_TRANS_C21_C22_DEFAULT 0x20000000
+-#define mmDCP4_COMM_MATRIXB_TRANS_C23_C24_DEFAULT 0x00000000
+-#define mmDCP4_COMM_MATRIXB_TRANS_C31_C32_DEFAULT 0x00000000
+-#define mmDCP4_COMM_MATRIXB_TRANS_C33_C34_DEFAULT 0x00002000
+-#define mmDCP4_DENORM_CONTROL_DEFAULT 0x00000003
+-#define mmDCP4_OUT_ROUND_CONTROL_DEFAULT 0x0000000a
+-#define mmDCP4_OUT_CLAMP_CONTROL_R_CR_DEFAULT 0x00003fff
+-#define mmDCP4_OUT_CLAMP_CONTROL_G_Y_DEFAULT 0x00003fff
+-#define mmDCP4_OUT_CLAMP_CONTROL_B_CB_DEFAULT 0x00003fff
+-#define mmDCP4_KEY_CONTROL_DEFAULT 0x00000000
+-#define mmDCP4_KEY_RANGE_ALPHA_DEFAULT 0x00000000
+-#define mmDCP4_KEY_RANGE_RED_DEFAULT 0x00000000
+-#define mmDCP4_KEY_RANGE_GREEN_DEFAULT 0x00000000
+-#define mmDCP4_KEY_RANGE_BLUE_DEFAULT 0x00000000
+-#define mmDCP4_DEGAMMA_CONTROL_DEFAULT 0x00000000
+-#define mmDCP4_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000
+-#define mmDCP4_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000
+-#define mmDCP4_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000
+-#define mmDCP4_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000
+-#define mmDCP4_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000
+-#define mmDCP4_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000
+-#define mmDCP4_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000
+-#define mmDCP4_DCP_SPATIAL_DITHER_CNTL_DEFAULT 0x00000000
+-#define mmDCP4_DCP_RANDOM_SEEDS_DEFAULT 0x00000000
+-#define mmDCP4_DCP_FP_CONVERTED_FIELD_DEFAULT 0x00000000
+-#define mmDCP4_CUR_CONTROL_DEFAULT 0x00000810
+-#define mmDCP4_CUR_SURFACE_ADDRESS_DEFAULT 0x00000000
+-#define mmDCP4_CUR_SIZE_DEFAULT 0x00000000
+-#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+-#define mmDCP4_CUR_POSITION_DEFAULT 0x00000000
+-#define mmDCP4_CUR_HOT_SPOT_DEFAULT 0x00000000
+-#define mmDCP4_CUR_COLOR1_DEFAULT 0x00000000
+-#define mmDCP4_CUR_COLOR2_DEFAULT 0x00000000
+-#define mmDCP4_CUR_UPDATE_DEFAULT 0x00000000
+-#define mmDCP4_CUR_REQUEST_FILTER_CNTL_DEFAULT 0x00000000
+-#define mmDCP4_CUR_STEREO_CONTROL_DEFAULT 0x00000000
+-#define mmDCP4_DC_LUT_RW_MODE_DEFAULT 0x00000000
+-#define mmDCP4_DC_LUT_RW_INDEX_DEFAULT 0x00000000
+-#define mmDCP4_DC_LUT_SEQ_COLOR_DEFAULT 0x00000000
+-#define mmDCP4_DC_LUT_PWL_DATA_DEFAULT 0x00000000
+-#define mmDCP4_DC_LUT_30_COLOR_DEFAULT 0x00000000
+-#define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE_DEFAULT 0x00000000
+-#define mmDCP4_DC_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
+-#define mmDCP4_DC_LUT_AUTOFILL_DEFAULT 0x00000000
+-#define mmDCP4_DC_LUT_CONTROL_DEFAULT 0x00000000
+-#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE_DEFAULT 0x00000000
+-#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN_DEFAULT 0x00000000
+-#define mmDCP4_DC_LUT_BLACK_OFFSET_RED_DEFAULT 0x00000000
+-#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE_DEFAULT 0x0000ffff
+-#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN_DEFAULT 0x0000ffff
+-#define mmDCP4_DC_LUT_WHITE_OFFSET_RED_DEFAULT 0x0000ffff
+-#define mmDCP4_DCP_CRC_CONTROL_DEFAULT 0x00000000
+-#define mmDCP4_DCP_CRC_MASK_DEFAULT 0x00000000
+-#define mmDCP4_DCP_CRC_CURRENT_DEFAULT 0x00000000
+-#define mmDCP4_DVMM_PTE_CONTROL_DEFAULT 0x00004000
+-#define mmDCP4_DCP_CRC_LAST_DEFAULT 0x00000000
+-#define mmDCP4_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220
+-#define mmDCP4_GRPH_FLIP_RATE_CNTL_DEFAULT 0x00000000
+-#define mmDCP4_DCP_GSL_CONTROL_DEFAULT 0x60000020
+-#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000035
+-#define mmDCP4_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00000200
+-#define mmDCP4_HW_ROTATION_DEFAULT 0x00000000
+-#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_DEFAULT 0x00000010
+-#define mmDCP4_REGAMMA_CONTROL_DEFAULT 0x00000000
+-#define mmDCP4_REGAMMA_LUT_INDEX_DEFAULT 0x00000000
+-#define mmDCP4_REGAMMA_LUT_DATA_DEFAULT 0x00000000
+-#define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
+-#define mmDCP4_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000
+-#define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000
+-#define mmDCP4_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000
+-#define mmDCP4_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000
+-#define mmDCP4_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000
+-#define mmDCP4_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000
+-#define mmDCP4_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000
+-#define mmDCP4_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000
+-#define mmDCP4_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000
+-#define mmDCP4_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000
+-#define mmDCP4_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000
+-#define mmDCP4_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000
+-#define mmDCP4_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000
+-#define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000
+-#define mmDCP4_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000
+-#define mmDCP4_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000
+-#define mmDCP4_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000
+-#define mmDCP4_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000
+-#define mmDCP4_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000
+-#define mmDCP4_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000
+-#define mmDCP4_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000
+-#define mmDCP4_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000
+-#define mmDCP4_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000
+-#define mmDCP4_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000
+-#define mmDCP4_ALPHA_CONTROL_DEFAULT 0x00000002
+-#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_DEFAULT 0x00000000
+-#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+-#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_DEFAULT 0x00000000
+-#define mmDCP4_GRPH_XDMA_FLIP_TIMEOUT_DEFAULT 0x00000000
+-#define mmDCP4_GRPH_XDMA_FLIP_AVG_DELAY_DEFAULT 0x00000000
+-#define mmDCP4_GRPH_SURFACE_COUNTER_CONTROL_DEFAULT 0x00000012
+-#define mmDCP4_GRPH_SURFACE_COUNTER_OUTPUT_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_lb4_dispdec
+-#define mmLB4_LB_DATA_FORMAT_DEFAULT 0x00000000
+-#define mmLB4_LB_MEMORY_CTRL_DEFAULT 0x000006b0
+-#define mmLB4_LB_MEMORY_SIZE_STATUS_DEFAULT 0x00000000
+-#define mmLB4_LB_DESKTOP_HEIGHT_DEFAULT 0x00000000
+-#define mmLB4_LB_VLINE_START_END_DEFAULT 0x00000000
+-#define mmLB4_LB_VLINE2_START_END_DEFAULT 0x00000000
+-#define mmLB4_LB_V_COUNTER_DEFAULT 0x00000000
+-#define mmLB4_LB_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000
+-#define mmLB4_LB_INTERRUPT_MASK_DEFAULT 0x00000000
+-#define mmLB4_LB_VLINE_STATUS_DEFAULT 0x00000000
+-#define mmLB4_LB_VLINE2_STATUS_DEFAULT 0x00000000
+-#define mmLB4_LB_VBLANK_STATUS_DEFAULT 0x00000000
+-#define mmLB4_LB_SYNC_RESET_SEL_DEFAULT 0x00000002
+-#define mmLB4_LB_BLACK_KEYER_R_CR_DEFAULT 0x00000000
+-#define mmLB4_LB_BLACK_KEYER_G_Y_DEFAULT 0x00000000
+-#define mmLB4_LB_BLACK_KEYER_B_CB_DEFAULT 0x00000000
+-#define mmLB4_LB_KEYER_COLOR_CTRL_DEFAULT 0x00000000
+-#define mmLB4_LB_KEYER_COLOR_R_CR_DEFAULT 0x00000000
+-#define mmLB4_LB_KEYER_COLOR_G_Y_DEFAULT 0x00000000
+-#define mmLB4_LB_KEYER_COLOR_B_CB_DEFAULT 0x00000000
+-#define mmLB4_LB_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000
+-#define mmLB4_LB_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000
+-#define mmLB4_LB_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000
+-#define mmLB4_LB_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000
+-#define mmLB4_LB_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010
+-#define mmLB4_LB_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000
+-#define mmLB4_LB_BUFFER_STATUS_DEFAULT 0x00000002
+-#define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000
+-#define mmLB4_MVP_AFR_FLIP_MODE_DEFAULT 0x00000000
+-#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL_DEFAULT 0x00000000
+-#define mmLB4_MVP_FLIP_LINE_NUM_INSERT_DEFAULT 0x00000002
+-#define mmLB4_DC_MVP_LB_CONTROL_DEFAULT 0x00000001
+-
+-
+-// addressBlock: dce_dc_dcfe4_dispdec
+-#define mmDCFE4_DCFE_CLOCK_CONTROL_DEFAULT 0x00000000
+-#define mmDCFE4_DCFE_SOFT_RESET_DEFAULT 0x00000000
+-#define mmDCFE4_DCFE_MEM_PWR_CTRL_DEFAULT 0x00000000
+-#define mmDCFE4_DCFE_MEM_PWR_CTRL2_DEFAULT 0x00000000
+-#define mmDCFE4_DCFE_MEM_PWR_STATUS_DEFAULT 0x00000000
+-#define mmDCFE4_DCFE_MISC_DEFAULT 0x00000001
+-#define mmDCFE4_DCFE_FLUSH_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dc_perfmon7_dispdec
+-#define mmDC_PERFMON7_PERFCOUNTER_CNTL_DEFAULT 0x00000000
+-#define mmDC_PERFMON7_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
+-#define mmDC_PERFMON7_PERFCOUNTER_STATE_DEFAULT 0x00000000
+-#define mmDC_PERFMON7_PERFMON_CNTL_DEFAULT 0x00000100
+-#define mmDC_PERFMON7_PERFMON_CNTL2_DEFAULT 0x00000000
+-#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
+-#define mmDC_PERFMON7_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
+-#define mmDC_PERFMON7_PERFMON_HI_DEFAULT 0x00000000
+-#define mmDC_PERFMON7_PERFMON_LOW_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dmif_pg4_dispdec
+-#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000
+-#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000
+-#define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL_DEFAULT 0x000bf777
+-#define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000
+-#define mmDMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL_DEFAULT 0x00000000
+-#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_DEFAULT 0x00000000
+-#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL2_DEFAULT 0x00000000
+-#define mmDMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL_DEFAULT 0x00000000
+-#define mmDMIF_PG4_DPG_REPEATER_PROGRAM_DEFAULT 0x00000000
+-#define mmDMIF_PG4_DPG_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000
+-#define mmDMIF_PG4_DPG_DVMM_STATUS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_scl4_dispdec
+-#define mmSCL4_SCL_COEF_RAM_SELECT_DEFAULT 0x00000000
+-#define mmSCL4_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000
+-#define mmSCL4_SCL_MODE_DEFAULT 0x00000000
+-#define mmSCL4_SCL_TAP_CONTROL_DEFAULT 0x00000000
+-#define mmSCL4_SCL_CONTROL_DEFAULT 0x00000000
+-#define mmSCL4_SCL_BYPASS_CONTROL_DEFAULT 0x00000000
+-#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000
+-#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000
+-#define mmSCL4_SCL_HORZ_FILTER_CONTROL_DEFAULT 0x00000000
+-#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000
+-#define mmSCL4_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000
+-#define mmSCL4_SCL_VERT_FILTER_CONTROL_DEFAULT 0x00000000
+-#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000
+-#define mmSCL4_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000
+-#define mmSCL4_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000
+-#define mmSCL4_SCL_ROUND_OFFSET_DEFAULT 0x80000000
+-#define mmSCL4_SCL_UPDATE_DEFAULT 0x00000000
+-#define mmSCL4_SCL_F_SHARP_CONTROL_DEFAULT 0x00000000
+-#define mmSCL4_SCL_ALU_CONTROL_DEFAULT 0x00000000
+-#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000
+-#define mmSCL4_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000
+-#define mmSCL4_VIEWPORT_START_DEFAULT 0x00000000
+-#define mmSCL4_VIEWPORT_SIZE_DEFAULT 0x00000000
+-#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000
+-#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000
+-#define mmSCL4_SCL_MODE_CHANGE_DET1_DEFAULT 0x00000000
+-#define mmSCL4_SCL_MODE_CHANGE_DET2_DEFAULT 0x00000000
+-#define mmSCL4_SCL_MODE_CHANGE_DET3_DEFAULT 0x00000000
+-#define mmSCL4_SCL_MODE_CHANGE_MASK_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_blnd4_dispdec
+-#define mmBLND4_BLND_CONTROL_DEFAULT 0xff0220ff
+-#define mmBLND4_BLND_SM_CONTROL2_DEFAULT 0x00000000
+-#define mmBLND4_BLND_CONTROL2_DEFAULT 0x00000010
+-#define mmBLND4_BLND_UPDATE_DEFAULT 0x00000000
+-#define mmBLND4_BLND_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000
+-#define mmBLND4_BLND_V_UPDATE_LOCK_DEFAULT 0x80000000
+-#define mmBLND4_BLND_REG_UPDATE_STATUS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_crtc4_dispdec
+-#define mmCRTC4_CRTC_H_BLANK_EARLY_NUM_DEFAULT 0x00000040
+-#define mmCRTC4_CRTC_H_TOTAL_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_H_BLANK_START_END_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_H_SYNC_A_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_H_SYNC_A_CNTL_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_H_SYNC_B_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_H_SYNC_B_CNTL_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_VBI_END_DEFAULT 0x00000003
+-#define mmCRTC4_CRTC_V_TOTAL_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_V_TOTAL_MIN_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_V_TOTAL_MAX_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_V_TOTAL_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_V_BLANK_START_END_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_V_SYNC_A_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_V_SYNC_A_CNTL_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_V_SYNC_B_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_V_SYNC_B_CNTL_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_DTMTEST_CNTL_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_TRIGA_CNTL_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_TRIGB_CNTL_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_FLOW_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_AVSYNC_COUNTER_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_CONTROL_DEFAULT 0x80400110
+-#define mmCRTC4_CRTC_BLANK_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_INTERLACE_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_INTERLACE_STATUS_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_PIXEL_DATA_READBACK0_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_PIXEL_DATA_READBACK1_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_STATUS_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_STATUS_POSITION_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_NOM_VERT_POSITION_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_STATUS_FRAME_COUNT_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_STATUS_VF_COUNT_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_STATUS_HV_COUNT_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_COUNT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_COUNT_RESET_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_VERT_SYNC_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_STEREO_STATUS_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_STEREO_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_SNAPSHOT_STATUS_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_SNAPSHOT_POSITION_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_SNAPSHOT_FRAME_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_START_LINE_CONTROL_DEFAULT 0x00003002
+-#define mmCRTC4_CRTC_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_UPDATE_LOCK_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_TEST_PATTERN_COLOR_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_MASTER_UPDATE_LOCK_DEFAULT 0x00010000
+-#define mmCRTC4_CRTC_MASTER_UPDATE_MODE_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008
+-#define mmCRTC4_CRTC_MVP_STATUS_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_MASTER_EN_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000
+-#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_OVERSCAN_COLOR_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_BLANK_DATA_COLOR_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_BLACK_COLOR_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_BLACK_COLOR_EXT_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_CRC_CNTL_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_CRC0_DATA_RG_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_CRC0_DATA_B_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_CRC1_DATA_RG_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_CRC1_DATA_B_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000
+-#define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010
+-#define mmCRTC4_CRTC_GSL_VSYNC_GAP_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_GSL_WINDOW_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_GSL_CONTROL_DEFAULT 0x00020000
+-#define mmCRTC4_CRTC_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000
+-#define mmCRTC4_CRTC_DRR_CONTROL_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_fmt4_dispdec
+-#define mmFMT4_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000
+-#define mmFMT4_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000
+-#define mmFMT4_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000
+-#define mmFMT4_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000
+-#define mmFMT4_FMT_CONTROL_DEFAULT 0x00000000
+-#define mmFMT4_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000
+-#define mmFMT4_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000
+-#define mmFMT4_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099
+-#define mmFMT4_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd
+-#define mmFMT4_FMT_CLAMP_CNTL_DEFAULT 0x00000000
+-#define mmFMT4_FMT_CRC_CNTL_DEFAULT 0x01000040
+-#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK_DEFAULT 0x00ff00ff
+-#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0x000700ff
+-#define mmFMT4_FMT_CRC_SIG_RED_GREEN_DEFAULT 0x00000000
+-#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_DEFAULT 0x00000000
+-#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000
+-#define mmFMT4_FMT_420_HBLANK_EARLY_START_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dcp5_dispdec
+-#define mmDCP5_GRPH_ENABLE_DEFAULT 0x00000001
+-#define mmDCP5_GRPH_CONTROL_DEFAULT 0x20002040
+-#define mmDCP5_GRPH_LUT_10BIT_BYPASS_DEFAULT 0x00000000
+-#define mmDCP5_GRPH_SWAP_CNTL_DEFAULT 0x00000000
+-#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000
+-#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000
+-#define mmDCP5_GRPH_PITCH_DEFAULT 0x00000000
+-#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+-#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+-#define mmDCP5_GRPH_SURFACE_OFFSET_X_DEFAULT 0x00000000
+-#define mmDCP5_GRPH_SURFACE_OFFSET_Y_DEFAULT 0x00000000
+-#define mmDCP5_GRPH_X_START_DEFAULT 0x00000000
+-#define mmDCP5_GRPH_Y_START_DEFAULT 0x00000000
+-#define mmDCP5_GRPH_X_END_DEFAULT 0x00000000
+-#define mmDCP5_GRPH_Y_END_DEFAULT 0x00000000
+-#define mmDCP5_INPUT_GAMMA_CONTROL_DEFAULT 0x00000000
+-#define mmDCP5_GRPH_UPDATE_DEFAULT 0x00000000
+-#define mmDCP5_GRPH_FLIP_CONTROL_DEFAULT 0x00000020
+-#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE_DEFAULT 0x00000000
+-#define mmDCP5_GRPH_DFQ_CONTROL_DEFAULT 0x00000000
+-#define mmDCP5_GRPH_DFQ_STATUS_DEFAULT 0x00000000
+-#define mmDCP5_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000
+-#define mmDCP5_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE_DEFAULT 0x00000000
+-#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_DEFAULT 0x00000000
+-#define mmDCP5_GRPH_COMPRESS_PITCH_DEFAULT 0x00000000
+-#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+-#define mmDCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x000000ff
+-#define mmDCP5_PRESCALE_GRPH_CONTROL_DEFAULT 0x00000010
+-#define mmDCP5_PRESCALE_VALUES_GRPH_R_DEFAULT 0x20000000
+-#define mmDCP5_PRESCALE_VALUES_GRPH_G_DEFAULT 0x20000000
+-#define mmDCP5_PRESCALE_VALUES_GRPH_B_DEFAULT 0x20000000
+-#define mmDCP5_INPUT_CSC_CONTROL_DEFAULT 0x00000000
+-#define mmDCP5_INPUT_CSC_C11_C12_DEFAULT 0x00002000
+-#define mmDCP5_INPUT_CSC_C13_C14_DEFAULT 0x00000000
+-#define mmDCP5_INPUT_CSC_C21_C22_DEFAULT 0x20000000
+-#define mmDCP5_INPUT_CSC_C23_C24_DEFAULT 0x00000000
+-#define mmDCP5_INPUT_CSC_C31_C32_DEFAULT 0x00000000
+-#define mmDCP5_INPUT_CSC_C33_C34_DEFAULT 0x00002000
+-#define mmDCP5_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000
+-#define mmDCP5_OUTPUT_CSC_C11_C12_DEFAULT 0x00002000
+-#define mmDCP5_OUTPUT_CSC_C13_C14_DEFAULT 0x00000000
+-#define mmDCP5_OUTPUT_CSC_C21_C22_DEFAULT 0x20000000
+-#define mmDCP5_OUTPUT_CSC_C23_C24_DEFAULT 0x00000000
+-#define mmDCP5_OUTPUT_CSC_C31_C32_DEFAULT 0x00000000
+-#define mmDCP5_OUTPUT_CSC_C33_C34_DEFAULT 0x00002000
+-#define mmDCP5_COMM_MATRIXA_TRANS_C11_C12_DEFAULT 0x00002000
+-#define mmDCP5_COMM_MATRIXA_TRANS_C13_C14_DEFAULT 0x00000000
+-#define mmDCP5_COMM_MATRIXA_TRANS_C21_C22_DEFAULT 0x20000000
+-#define mmDCP5_COMM_MATRIXA_TRANS_C23_C24_DEFAULT 0x00000000
+-#define mmDCP5_COMM_MATRIXA_TRANS_C31_C32_DEFAULT 0x00000000
+-#define mmDCP5_COMM_MATRIXA_TRANS_C33_C34_DEFAULT 0x00002000
+-#define mmDCP5_COMM_MATRIXB_TRANS_C11_C12_DEFAULT 0x00002000
+-#define mmDCP5_COMM_MATRIXB_TRANS_C13_C14_DEFAULT 0x00000000
+-#define mmDCP5_COMM_MATRIXB_TRANS_C21_C22_DEFAULT 0x20000000
+-#define mmDCP5_COMM_MATRIXB_TRANS_C23_C24_DEFAULT 0x00000000
+-#define mmDCP5_COMM_MATRIXB_TRANS_C31_C32_DEFAULT 0x00000000
+-#define mmDCP5_COMM_MATRIXB_TRANS_C33_C34_DEFAULT 0x00002000
+-#define mmDCP5_DENORM_CONTROL_DEFAULT 0x00000003
+-#define mmDCP5_OUT_ROUND_CONTROL_DEFAULT 0x0000000a
+-#define mmDCP5_OUT_CLAMP_CONTROL_R_CR_DEFAULT 0x00003fff
+-#define mmDCP5_OUT_CLAMP_CONTROL_G_Y_DEFAULT 0x00003fff
+-#define mmDCP5_OUT_CLAMP_CONTROL_B_CB_DEFAULT 0x00003fff
+-#define mmDCP5_KEY_CONTROL_DEFAULT 0x00000000
+-#define mmDCP5_KEY_RANGE_ALPHA_DEFAULT 0x00000000
+-#define mmDCP5_KEY_RANGE_RED_DEFAULT 0x00000000
+-#define mmDCP5_KEY_RANGE_GREEN_DEFAULT 0x00000000
+-#define mmDCP5_KEY_RANGE_BLUE_DEFAULT 0x00000000
+-#define mmDCP5_DEGAMMA_CONTROL_DEFAULT 0x00000000
+-#define mmDCP5_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000
+-#define mmDCP5_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000
+-#define mmDCP5_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000
+-#define mmDCP5_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000
+-#define mmDCP5_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000
+-#define mmDCP5_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000
+-#define mmDCP5_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000
+-#define mmDCP5_DCP_SPATIAL_DITHER_CNTL_DEFAULT 0x00000000
+-#define mmDCP5_DCP_RANDOM_SEEDS_DEFAULT 0x00000000
+-#define mmDCP5_DCP_FP_CONVERTED_FIELD_DEFAULT 0x00000000
+-#define mmDCP5_CUR_CONTROL_DEFAULT 0x00000810
+-#define mmDCP5_CUR_SURFACE_ADDRESS_DEFAULT 0x00000000
+-#define mmDCP5_CUR_SIZE_DEFAULT 0x00000000
+-#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+-#define mmDCP5_CUR_POSITION_DEFAULT 0x00000000
+-#define mmDCP5_CUR_HOT_SPOT_DEFAULT 0x00000000
+-#define mmDCP5_CUR_COLOR1_DEFAULT 0x00000000
+-#define mmDCP5_CUR_COLOR2_DEFAULT 0x00000000
+-#define mmDCP5_CUR_UPDATE_DEFAULT 0x00000000
+-#define mmDCP5_CUR_REQUEST_FILTER_CNTL_DEFAULT 0x00000000
+-#define mmDCP5_CUR_STEREO_CONTROL_DEFAULT 0x00000000
+-#define mmDCP5_DC_LUT_RW_MODE_DEFAULT 0x00000000
+-#define mmDCP5_DC_LUT_RW_INDEX_DEFAULT 0x00000000
+-#define mmDCP5_DC_LUT_SEQ_COLOR_DEFAULT 0x00000000
+-#define mmDCP5_DC_LUT_PWL_DATA_DEFAULT 0x00000000
+-#define mmDCP5_DC_LUT_30_COLOR_DEFAULT 0x00000000
+-#define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE_DEFAULT 0x00000000
+-#define mmDCP5_DC_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
+-#define mmDCP5_DC_LUT_AUTOFILL_DEFAULT 0x00000000
+-#define mmDCP5_DC_LUT_CONTROL_DEFAULT 0x00000000
+-#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE_DEFAULT 0x00000000
+-#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN_DEFAULT 0x00000000
+-#define mmDCP5_DC_LUT_BLACK_OFFSET_RED_DEFAULT 0x00000000
+-#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE_DEFAULT 0x0000ffff
+-#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN_DEFAULT 0x0000ffff
+-#define mmDCP5_DC_LUT_WHITE_OFFSET_RED_DEFAULT 0x0000ffff
+-#define mmDCP5_DCP_CRC_CONTROL_DEFAULT 0x00000000
+-#define mmDCP5_DCP_CRC_MASK_DEFAULT 0x00000000
+-#define mmDCP5_DCP_CRC_CURRENT_DEFAULT 0x00000000
+-#define mmDCP5_DVMM_PTE_CONTROL_DEFAULT 0x00004000
+-#define mmDCP5_DCP_CRC_LAST_DEFAULT 0x00000000
+-#define mmDCP5_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220
+-#define mmDCP5_GRPH_FLIP_RATE_CNTL_DEFAULT 0x00000000
+-#define mmDCP5_DCP_GSL_CONTROL_DEFAULT 0x60000020
+-#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000035
+-#define mmDCP5_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00000200
+-#define mmDCP5_HW_ROTATION_DEFAULT 0x00000000
+-#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_DEFAULT 0x00000010
+-#define mmDCP5_REGAMMA_CONTROL_DEFAULT 0x00000000
+-#define mmDCP5_REGAMMA_LUT_INDEX_DEFAULT 0x00000000
+-#define mmDCP5_REGAMMA_LUT_DATA_DEFAULT 0x00000000
+-#define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
+-#define mmDCP5_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000
+-#define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000
+-#define mmDCP5_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000
+-#define mmDCP5_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000
+-#define mmDCP5_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000
+-#define mmDCP5_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000
+-#define mmDCP5_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000
+-#define mmDCP5_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000
+-#define mmDCP5_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000
+-#define mmDCP5_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000
+-#define mmDCP5_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000
+-#define mmDCP5_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000
+-#define mmDCP5_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000
+-#define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000
+-#define mmDCP5_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000
+-#define mmDCP5_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000
+-#define mmDCP5_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000
+-#define mmDCP5_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000
+-#define mmDCP5_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000
+-#define mmDCP5_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000
+-#define mmDCP5_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000
+-#define mmDCP5_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000
+-#define mmDCP5_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000
+-#define mmDCP5_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000
+-#define mmDCP5_ALPHA_CONTROL_DEFAULT 0x00000002
+-#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_DEFAULT 0x00000000
+-#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+-#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_DEFAULT 0x00000000
+-#define mmDCP5_GRPH_XDMA_FLIP_TIMEOUT_DEFAULT 0x00000000
+-#define mmDCP5_GRPH_XDMA_FLIP_AVG_DELAY_DEFAULT 0x00000000
+-#define mmDCP5_GRPH_SURFACE_COUNTER_CONTROL_DEFAULT 0x00000012
+-#define mmDCP5_GRPH_SURFACE_COUNTER_OUTPUT_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_lb5_dispdec
+-#define mmLB5_LB_DATA_FORMAT_DEFAULT 0x00000000
+-#define mmLB5_LB_MEMORY_CTRL_DEFAULT 0x000006b0
+-#define mmLB5_LB_MEMORY_SIZE_STATUS_DEFAULT 0x00000000
+-#define mmLB5_LB_DESKTOP_HEIGHT_DEFAULT 0x00000000
+-#define mmLB5_LB_VLINE_START_END_DEFAULT 0x00000000
+-#define mmLB5_LB_VLINE2_START_END_DEFAULT 0x00000000
+-#define mmLB5_LB_V_COUNTER_DEFAULT 0x00000000
+-#define mmLB5_LB_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000
+-#define mmLB5_LB_INTERRUPT_MASK_DEFAULT 0x00000000
+-#define mmLB5_LB_VLINE_STATUS_DEFAULT 0x00000000
+-#define mmLB5_LB_VLINE2_STATUS_DEFAULT 0x00000000
+-#define mmLB5_LB_VBLANK_STATUS_DEFAULT 0x00000000
+-#define mmLB5_LB_SYNC_RESET_SEL_DEFAULT 0x00000002
+-#define mmLB5_LB_BLACK_KEYER_R_CR_DEFAULT 0x00000000
+-#define mmLB5_LB_BLACK_KEYER_G_Y_DEFAULT 0x00000000
+-#define mmLB5_LB_BLACK_KEYER_B_CB_DEFAULT 0x00000000
+-#define mmLB5_LB_KEYER_COLOR_CTRL_DEFAULT 0x00000000
+-#define mmLB5_LB_KEYER_COLOR_R_CR_DEFAULT 0x00000000
+-#define mmLB5_LB_KEYER_COLOR_G_Y_DEFAULT 0x00000000
+-#define mmLB5_LB_KEYER_COLOR_B_CB_DEFAULT 0x00000000
+-#define mmLB5_LB_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000
+-#define mmLB5_LB_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000
+-#define mmLB5_LB_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000
+-#define mmLB5_LB_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000
+-#define mmLB5_LB_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010
+-#define mmLB5_LB_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000
+-#define mmLB5_LB_BUFFER_STATUS_DEFAULT 0x00000002
+-#define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000
+-#define mmLB5_MVP_AFR_FLIP_MODE_DEFAULT 0x00000000
+-#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL_DEFAULT 0x00000000
+-#define mmLB5_MVP_FLIP_LINE_NUM_INSERT_DEFAULT 0x00000002
+-#define mmLB5_DC_MVP_LB_CONTROL_DEFAULT 0x00000001
+-
+-
+-// addressBlock: dce_dc_dcfe5_dispdec
+-#define mmDCFE5_DCFE_CLOCK_CONTROL_DEFAULT 0x00000000
+-#define mmDCFE5_DCFE_SOFT_RESET_DEFAULT 0x00000000
+-#define mmDCFE5_DCFE_MEM_PWR_CTRL_DEFAULT 0x00000000
+-#define mmDCFE5_DCFE_MEM_PWR_CTRL2_DEFAULT 0x00000000
+-#define mmDCFE5_DCFE_MEM_PWR_STATUS_DEFAULT 0x00000000
+-#define mmDCFE5_DCFE_MISC_DEFAULT 0x00000001
+-#define mmDCFE5_DCFE_FLUSH_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dc_perfmon8_dispdec
+-#define mmDC_PERFMON8_PERFCOUNTER_CNTL_DEFAULT 0x00000000
+-#define mmDC_PERFMON8_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
+-#define mmDC_PERFMON8_PERFCOUNTER_STATE_DEFAULT 0x00000000
+-#define mmDC_PERFMON8_PERFMON_CNTL_DEFAULT 0x00000100
+-#define mmDC_PERFMON8_PERFMON_CNTL2_DEFAULT 0x00000000
+-#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
+-#define mmDC_PERFMON8_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
+-#define mmDC_PERFMON8_PERFMON_HI_DEFAULT 0x00000000
+-#define mmDC_PERFMON8_PERFMON_LOW_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dmif_pg5_dispdec
+-#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000
+-#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000
+-#define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL_DEFAULT 0x000bf777
+-#define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000
+-#define mmDMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL_DEFAULT 0x00000000
+-#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_DEFAULT 0x00000000
+-#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL2_DEFAULT 0x00000000
+-#define mmDMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL_DEFAULT 0x00000000
+-#define mmDMIF_PG5_DPG_REPEATER_PROGRAM_DEFAULT 0x00000000
+-#define mmDMIF_PG5_DPG_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000
+-#define mmDMIF_PG5_DPG_DVMM_STATUS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_scl5_dispdec
+-#define mmSCL5_SCL_COEF_RAM_SELECT_DEFAULT 0x00000000
+-#define mmSCL5_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000
+-#define mmSCL5_SCL_MODE_DEFAULT 0x00000000
+-#define mmSCL5_SCL_TAP_CONTROL_DEFAULT 0x00000000
+-#define mmSCL5_SCL_CONTROL_DEFAULT 0x00000000
+-#define mmSCL5_SCL_BYPASS_CONTROL_DEFAULT 0x00000000
+-#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000
+-#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000
+-#define mmSCL5_SCL_HORZ_FILTER_CONTROL_DEFAULT 0x00000000
+-#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000
+-#define mmSCL5_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000
+-#define mmSCL5_SCL_VERT_FILTER_CONTROL_DEFAULT 0x00000000
+-#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000
+-#define mmSCL5_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000
+-#define mmSCL5_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000
+-#define mmSCL5_SCL_ROUND_OFFSET_DEFAULT 0x80000000
+-#define mmSCL5_SCL_UPDATE_DEFAULT 0x00000000
+-#define mmSCL5_SCL_F_SHARP_CONTROL_DEFAULT 0x00000000
+-#define mmSCL5_SCL_ALU_CONTROL_DEFAULT 0x00000000
+-#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000
+-#define mmSCL5_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000
+-#define mmSCL5_VIEWPORT_START_DEFAULT 0x00000000
+-#define mmSCL5_VIEWPORT_SIZE_DEFAULT 0x00000000
+-#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000
+-#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000
+-#define mmSCL5_SCL_MODE_CHANGE_DET1_DEFAULT 0x00000000
+-#define mmSCL5_SCL_MODE_CHANGE_DET2_DEFAULT 0x00000000
+-#define mmSCL5_SCL_MODE_CHANGE_DET3_DEFAULT 0x00000000
+-#define mmSCL5_SCL_MODE_CHANGE_MASK_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_blnd5_dispdec
+-#define mmBLND5_BLND_CONTROL_DEFAULT 0xff0220ff
+-#define mmBLND5_BLND_SM_CONTROL2_DEFAULT 0x00000000
+-#define mmBLND5_BLND_CONTROL2_DEFAULT 0x00000010
+-#define mmBLND5_BLND_UPDATE_DEFAULT 0x00000000
+-#define mmBLND5_BLND_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000
+-#define mmBLND5_BLND_V_UPDATE_LOCK_DEFAULT 0x80000000
+-#define mmBLND5_BLND_REG_UPDATE_STATUS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_crtc5_dispdec
+-#define mmCRTC5_CRTC_H_BLANK_EARLY_NUM_DEFAULT 0x00000040
+-#define mmCRTC5_CRTC_H_TOTAL_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_H_BLANK_START_END_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_H_SYNC_A_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_H_SYNC_A_CNTL_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_H_SYNC_B_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_H_SYNC_B_CNTL_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_VBI_END_DEFAULT 0x00000003
+-#define mmCRTC5_CRTC_V_TOTAL_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_V_TOTAL_MIN_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_V_TOTAL_MAX_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_V_TOTAL_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_V_BLANK_START_END_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_V_SYNC_A_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_V_SYNC_A_CNTL_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_V_SYNC_B_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_V_SYNC_B_CNTL_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_DTMTEST_CNTL_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_TRIGA_CNTL_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_TRIGB_CNTL_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_FLOW_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_AVSYNC_COUNTER_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_CONTROL_DEFAULT 0x80400110
+-#define mmCRTC5_CRTC_BLANK_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_INTERLACE_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_INTERLACE_STATUS_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_PIXEL_DATA_READBACK0_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_PIXEL_DATA_READBACK1_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_STATUS_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_STATUS_POSITION_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_NOM_VERT_POSITION_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_STATUS_FRAME_COUNT_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_STATUS_VF_COUNT_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_STATUS_HV_COUNT_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_COUNT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_COUNT_RESET_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_VERT_SYNC_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_STEREO_STATUS_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_STEREO_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_SNAPSHOT_STATUS_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_SNAPSHOT_POSITION_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_SNAPSHOT_FRAME_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_START_LINE_CONTROL_DEFAULT 0x00003002
+-#define mmCRTC5_CRTC_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_UPDATE_LOCK_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_TEST_PATTERN_COLOR_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_MASTER_UPDATE_LOCK_DEFAULT 0x00010000
+-#define mmCRTC5_CRTC_MASTER_UPDATE_MODE_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008
+-#define mmCRTC5_CRTC_MVP_STATUS_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_MASTER_EN_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000
+-#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_OVERSCAN_COLOR_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_BLANK_DATA_COLOR_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_BLACK_COLOR_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_BLACK_COLOR_EXT_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_CRC_CNTL_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_CRC0_DATA_RG_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_CRC0_DATA_B_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_CRC1_DATA_RG_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_CRC1_DATA_B_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000
+-#define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010
+-#define mmCRTC5_CRTC_GSL_VSYNC_GAP_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_GSL_WINDOW_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_GSL_CONTROL_DEFAULT 0x00020000
+-#define mmCRTC5_CRTC_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000
+-#define mmCRTC5_CRTC_DRR_CONTROL_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_fmt5_dispdec
+-#define mmFMT5_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000
+-#define mmFMT5_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000
+-#define mmFMT5_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000
+-#define mmFMT5_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000
+-#define mmFMT5_FMT_CONTROL_DEFAULT 0x00000000
+-#define mmFMT5_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000
+-#define mmFMT5_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000
+-#define mmFMT5_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099
+-#define mmFMT5_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd
+-#define mmFMT5_FMT_CLAMP_CNTL_DEFAULT 0x00000000
+-#define mmFMT5_FMT_CRC_CNTL_DEFAULT 0x01000040
+-#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK_DEFAULT 0x00ff00ff
+-#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0x000700ff
+-#define mmFMT5_FMT_CRC_SIG_RED_GREEN_DEFAULT 0x00000000
+-#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_DEFAULT 0x00000000
+-#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000
+-#define mmFMT5_FMT_420_HBLANK_EARLY_START_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_unp0_dispdec
+-#define mmUNP0_UNP_GRPH_ENABLE_DEFAULT 0x00000001
+-#define mmUNP0_UNP_GRPH_CONTROL_DEFAULT 0x0a008008
+-#define mmUNP0_UNP_GRPH_CONTROL_C_DEFAULT 0x00008000
+-#define mmUNP0_UNP_GRPH_CONTROL_EXP_DEFAULT 0x00000000
+-#define mmUNP0_UNP_GRPH_SWAP_CNTL_DEFAULT 0x00000000
+-#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L_DEFAULT 0x00000000
+-#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000
+-#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000
+-#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000
+-#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_DEFAULT 0x00000000
+-#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_DEFAULT 0x00000000
+-#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000
+-#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000
+-#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L_DEFAULT 0x00000000
+-#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000
+-#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000
+-#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000
+-#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_DEFAULT 0x00000000
+-#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_DEFAULT 0x00000000
+-#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000
+-#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000
+-#define mmUNP0_UNP_GRPH_PITCH_L_DEFAULT 0x00000000
+-#define mmUNP0_UNP_GRPH_PITCH_C_DEFAULT 0x00000000
+-#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_L_DEFAULT 0x00000000
+-#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_C_DEFAULT 0x00000000
+-#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_L_DEFAULT 0x00000000
+-#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_C_DEFAULT 0x00000000
+-#define mmUNP0_UNP_GRPH_X_START_L_DEFAULT 0x00000000
+-#define mmUNP0_UNP_GRPH_X_START_C_DEFAULT 0x00000000
+-#define mmUNP0_UNP_GRPH_Y_START_L_DEFAULT 0x00000000
+-#define mmUNP0_UNP_GRPH_Y_START_C_DEFAULT 0x00000000
+-#define mmUNP0_UNP_GRPH_X_END_L_DEFAULT 0x00000000
+-#define mmUNP0_UNP_GRPH_X_END_C_DEFAULT 0x00000000
+-#define mmUNP0_UNP_GRPH_Y_END_L_DEFAULT 0x00000000
+-#define mmUNP0_UNP_GRPH_Y_END_C_DEFAULT 0x00000000
+-#define mmUNP0_UNP_GRPH_UPDATE_DEFAULT 0x00000000
+-#define mmUNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x0000ffff
+-#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L_DEFAULT 0x00000000
+-#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C_DEFAULT 0x00000000
+-#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_DEFAULT 0x00000000
+-#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_DEFAULT 0x00000000
+-#define mmUNP0_UNP_DVMM_PTE_CONTROL_DEFAULT 0x00004000
+-#define mmUNP0_UNP_DVMM_PTE_CONTROL_C_DEFAULT 0x00004000
+-#define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220
+-#define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL_C_DEFAULT 0x00002220
+-#define mmUNP0_UNP_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000
+-#define mmUNP0_UNP_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmUNP0_UNP_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00002020
+-#define mmUNP0_UNP_FLIP_CONTROL_DEFAULT 0x00000001
+-#define mmUNP0_UNP_CRC_CONTROL_DEFAULT 0x00000000
+-#define mmUNP0_UNP_CRC_MASK_DEFAULT 0x00000000
+-#define mmUNP0_UNP_CRC_CURRENT_DEFAULT 0x00000000
+-#define mmUNP0_UNP_CRC_LAST_DEFAULT 0x00000000
+-#define mmUNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000100
+-#define mmUNP0_UNP_HW_ROTATION_DEFAULT 0x00000010
+-
+-
+-// addressBlock: dce_dc_lbv0_dispdec
+-#define mmLBV0_LBV_DATA_FORMAT_DEFAULT 0x00000000
+-#define mmLBV0_LBV_MEMORY_CTRL_DEFAULT 0x000006b0
+-#define mmLBV0_LBV_MEMORY_SIZE_STATUS_DEFAULT 0x00000000
+-#define mmLBV0_LBV_DESKTOP_HEIGHT_DEFAULT 0x00000000
+-#define mmLBV0_LBV_VLINE_START_END_DEFAULT 0x00000000
+-#define mmLBV0_LBV_VLINE2_START_END_DEFAULT 0x00000000
+-#define mmLBV0_LBV_V_COUNTER_DEFAULT 0x00000000
+-#define mmLBV0_LBV_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000
+-#define mmLBV0_LBV_V_COUNTER_CHROMA_DEFAULT 0x00000000
+-#define mmLBV0_LBV_SNAPSHOT_V_COUNTER_CHROMA_DEFAULT 0x00000000
+-#define mmLBV0_LBV_INTERRUPT_MASK_DEFAULT 0x00000000
+-#define mmLBV0_LBV_VLINE_STATUS_DEFAULT 0x00000000
+-#define mmLBV0_LBV_VLINE2_STATUS_DEFAULT 0x00000000
+-#define mmLBV0_LBV_VBLANK_STATUS_DEFAULT 0x00000000
+-#define mmLBV0_LBV_SYNC_RESET_SEL_DEFAULT 0x00000002
+-#define mmLBV0_LBV_BLACK_KEYER_R_CR_DEFAULT 0x00000000
+-#define mmLBV0_LBV_BLACK_KEYER_G_Y_DEFAULT 0x00000000
+-#define mmLBV0_LBV_BLACK_KEYER_B_CB_DEFAULT 0x00000000
+-#define mmLBV0_LBV_KEYER_COLOR_CTRL_DEFAULT 0x00000000
+-#define mmLBV0_LBV_KEYER_COLOR_R_CR_DEFAULT 0x00000000
+-#define mmLBV0_LBV_KEYER_COLOR_G_Y_DEFAULT 0x00000000
+-#define mmLBV0_LBV_KEYER_COLOR_B_CB_DEFAULT 0x00000000
+-#define mmLBV0_LBV_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000
+-#define mmLBV0_LBV_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000
+-#define mmLBV0_LBV_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000
+-#define mmLBV0_LBV_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000
+-#define mmLBV0_LBV_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010
+-#define mmLBV0_LBV_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000
+-#define mmLBV0_LBV_BUFFER_STATUS_DEFAULT 0x12000002
+-#define mmLBV0_LBV_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_sclv0_dispdec
+-#define mmSCLV0_SCLV_COEF_RAM_SELECT_DEFAULT 0x00000000
+-#define mmSCLV0_SCLV_COEF_RAM_TAP_DATA_DEFAULT 0x00000000
+-#define mmSCLV0_SCLV_MODE_DEFAULT 0x00000000
+-#define mmSCLV0_SCLV_TAP_CONTROL_DEFAULT 0x00000000
+-#define mmSCLV0_SCLV_CONTROL_DEFAULT 0x00000000
+-#define mmSCLV0_SCLV_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000
+-#define mmSCLV0_SCLV_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000
+-#define mmSCLV0_SCLV_HORZ_FILTER_CONTROL_DEFAULT 0x00000000
+-#define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000
+-#define mmSCLV0_SCLV_HORZ_FILTER_INIT_DEFAULT 0x01000000
+-#define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000
+-#define mmSCLV0_SCLV_HORZ_FILTER_INIT_C_DEFAULT 0x01000000
+-#define mmSCLV0_SCLV_VERT_FILTER_CONTROL_DEFAULT 0x00000000
+-#define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000
+-#define mmSCLV0_SCLV_VERT_FILTER_INIT_DEFAULT 0x01000000
+-#define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000
+-#define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000
+-#define mmSCLV0_SCLV_VERT_FILTER_INIT_C_DEFAULT 0x01000000
+-#define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_C_DEFAULT 0x01000000
+-#define mmSCLV0_SCLV_ROUND_OFFSET_DEFAULT 0x80000000
+-#define mmSCLV0_SCLV_UPDATE_DEFAULT 0x00000000
+-#define mmSCLV0_SCLV_ALU_CONTROL_DEFAULT 0x00000000
+-#define mmSCLV0_SCLV_VIEWPORT_START_DEFAULT 0x00000000
+-#define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000
+-#define mmSCLV0_SCLV_VIEWPORT_SIZE_DEFAULT 0x00000000
+-#define mmSCLV0_SCLV_VIEWPORT_START_C_DEFAULT 0x00000000
+-#define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_C_DEFAULT 0x00000000
+-#define mmSCLV0_SCLV_VIEWPORT_SIZE_C_DEFAULT 0x00000000
+-#define mmSCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000
+-#define mmSCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000
+-#define mmSCLV0_SCLV_MODE_CHANGE_DET1_DEFAULT 0x00000000
+-#define mmSCLV0_SCLV_MODE_CHANGE_DET2_DEFAULT 0x00000000
+-#define mmSCLV0_SCLV_MODE_CHANGE_DET3_DEFAULT 0x00000000
+-#define mmSCLV0_SCLV_MODE_CHANGE_MASK_DEFAULT 0x00000000
+-#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_DEFAULT 0x01000000
+-#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_C_DEFAULT 0x01000000
+-
+-
+-// addressBlock: dce_dc_col_man0_dispdec
+-#define mmCOL_MAN0_COL_MAN_UPDATE_DEFAULT 0x00000000
+-#define mmCOL_MAN0_COL_MAN_INPUT_CSC_CONTROL_DEFAULT 0x00000000
+-#define mmCOL_MAN0_INPUT_CSC_C11_C12_A_DEFAULT 0x00002000
+-#define mmCOL_MAN0_INPUT_CSC_C13_C14_A_DEFAULT 0x00000000
+-#define mmCOL_MAN0_INPUT_CSC_C21_C22_A_DEFAULT 0x20000000
+-#define mmCOL_MAN0_INPUT_CSC_C23_C24_A_DEFAULT 0x00000000
+-#define mmCOL_MAN0_INPUT_CSC_C31_C32_A_DEFAULT 0x00000000
+-#define mmCOL_MAN0_INPUT_CSC_C33_C34_A_DEFAULT 0x00002000
+-#define mmCOL_MAN0_INPUT_CSC_C11_C12_B_DEFAULT 0x00002000
+-#define mmCOL_MAN0_INPUT_CSC_C13_C14_B_DEFAULT 0x00000000
+-#define mmCOL_MAN0_INPUT_CSC_C21_C22_B_DEFAULT 0x20000000
+-#define mmCOL_MAN0_INPUT_CSC_C23_C24_B_DEFAULT 0x00000000
+-#define mmCOL_MAN0_INPUT_CSC_C31_C32_B_DEFAULT 0x00000000
+-#define mmCOL_MAN0_INPUT_CSC_C33_C34_B_DEFAULT 0x00002000
+-#define mmCOL_MAN0_PRESCALE_CONTROL_DEFAULT 0x00000000
+-#define mmCOL_MAN0_PRESCALE_VALUES_R_DEFAULT 0x20000000
+-#define mmCOL_MAN0_PRESCALE_VALUES_G_DEFAULT 0x20000000
+-#define mmCOL_MAN0_PRESCALE_VALUES_B_DEFAULT 0x20000000
+-#define mmCOL_MAN0_COL_MAN_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000
+-#define mmCOL_MAN0_OUTPUT_CSC_C11_C12_A_DEFAULT 0x00002000
+-#define mmCOL_MAN0_OUTPUT_CSC_C13_C14_A_DEFAULT 0x00000000
+-#define mmCOL_MAN0_OUTPUT_CSC_C21_C22_A_DEFAULT 0x20000000
+-#define mmCOL_MAN0_OUTPUT_CSC_C23_C24_A_DEFAULT 0x00000000
+-#define mmCOL_MAN0_OUTPUT_CSC_C31_C32_A_DEFAULT 0x00000000
+-#define mmCOL_MAN0_OUTPUT_CSC_C33_C34_A_DEFAULT 0x00002000
+-#define mmCOL_MAN0_OUTPUT_CSC_C11_C12_B_DEFAULT 0x00002000
+-#define mmCOL_MAN0_OUTPUT_CSC_C13_C14_B_DEFAULT 0x00000000
+-#define mmCOL_MAN0_OUTPUT_CSC_C21_C22_B_DEFAULT 0x20000000
+-#define mmCOL_MAN0_OUTPUT_CSC_C23_C24_B_DEFAULT 0x00000000
+-#define mmCOL_MAN0_OUTPUT_CSC_C31_C32_B_DEFAULT 0x00000000
+-#define mmCOL_MAN0_OUTPUT_CSC_C33_C34_B_DEFAULT 0x00002000
+-#define mmCOL_MAN0_DENORM_CLAMP_CONTROL_DEFAULT 0x00000000
+-#define mmCOL_MAN0_DENORM_CLAMP_RANGE_R_CR_DEFAULT 0x00000fff
+-#define mmCOL_MAN0_DENORM_CLAMP_RANGE_G_Y_DEFAULT 0x00000fff
+-#define mmCOL_MAN0_DENORM_CLAMP_RANGE_B_CB_DEFAULT 0x00000fff
+-#define mmCOL_MAN0_COL_MAN_FP_CONVERTED_FIELD_DEFAULT 0x00000000
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CONTROL_DEFAULT 0x00000000
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_INDEX_DEFAULT 0x00000000
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_DATA_DEFAULT 0x00000000
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000
+-#define mmCOL_MAN0_PACK_FIFO_ERROR_DEFAULT 0x00000000
+-#define mmCOL_MAN0_OUTPUT_FIFO_ERROR_DEFAULT 0x00000000
+-#define mmCOL_MAN0_INPUT_GAMMA_LUT_AUTOFILL_DEFAULT 0x00000000
+-#define mmCOL_MAN0_INPUT_GAMMA_LUT_RW_INDEX_DEFAULT 0x00000000
+-#define mmCOL_MAN0_INPUT_GAMMA_LUT_SEQ_COLOR_DEFAULT 0x00000000
+-#define mmCOL_MAN0_INPUT_GAMMA_LUT_PWL_DATA_DEFAULT 0x00000000
+-#define mmCOL_MAN0_INPUT_GAMMA_LUT_30_COLOR_DEFAULT 0x00000000
+-#define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1_DEFAULT 0x00000000
+-#define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2_DEFAULT 0x03800000
+-#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_B_DEFAULT 0xffff0000
+-#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_G_DEFAULT 0xffff0000
+-#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_R_DEFAULT 0xffff0000
+-#define mmCOL_MAN0_COL_MAN_DEGAMMA_CONTROL_DEFAULT 0x00000000
+-#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000
+-#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000
+-#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000
+-#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000
+-#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000
+-#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000
+-#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000
+-
+-
+-// addressBlock: dce_dc_dcfev0_dispdec
+-#define mmDCFEV0_DCFEV_CLOCK_CONTROL_DEFAULT 0x00000000
+-#define mmDCFEV0_DCFEV_SOFT_RESET_DEFAULT 0x00000000
+-#define mmDCFEV0_DCFEV_DMIFV_CLOCK_CONTROL_DEFAULT 0x00000000
+-#define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL_DEFAULT 0x00000000
+-#define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS_DEFAULT 0x00000000
+-#define mmDCFEV0_DCFEV_MEM_PWR_CTRL_DEFAULT 0x00000000
+-#define mmDCFEV0_DCFEV_MEM_PWR_CTRL2_DEFAULT 0x00000000
+-#define mmDCFEV0_DCFEV_MEM_PWR_STATUS_DEFAULT 0x00000000
+-#define mmDCFEV0_DCFEV_L_FLUSH_DEFAULT 0x00000000
+-#define mmDCFEV0_DCFEV_C_FLUSH_DEFAULT 0x00000000
+-#define mmDCFEV0_DCFEV_MISC_DEFAULT 0x00000001
+-
+-
+-// addressBlock: dce_dc_dc_perfmon11_dispdec
+-#define mmDC_PERFMON11_PERFCOUNTER_CNTL_DEFAULT 0x00000000
+-#define mmDC_PERFMON11_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
+-#define mmDC_PERFMON11_PERFCOUNTER_STATE_DEFAULT 0x00000000
+-#define mmDC_PERFMON11_PERFMON_CNTL_DEFAULT 0x00000100
+-#define mmDC_PERFMON11_PERFMON_CNTL2_DEFAULT 0x00000000
+-#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
+-#define mmDC_PERFMON11_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
+-#define mmDC_PERFMON11_PERFMON_HI_DEFAULT 0x00000000
+-#define mmDC_PERFMON11_PERFMON_LOW_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dmifv_pg0_dispdec
+-#define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000
+-#define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000
+-#define mmDMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL_DEFAULT 0x00030303
+-#define mmDMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000
+-#define mmDMIFV_PG0_DPGV0_PIPE_DPM_CONTROL_DEFAULT 0x00003000
+-#define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_DEFAULT 0x00000200
+-#define mmDMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL_DEFAULT 0x00000000
+-#define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH_DEFAULT 0x00000200
+-#define mmDMIFV_PG0_DPGV0_REPEATER_PROGRAM_DEFAULT 0x00000000
+-#define mmDMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000
+-#define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000
+-#define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000
+-#define mmDMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL_DEFAULT 0x00030303
+-#define mmDMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000
+-#define mmDMIFV_PG0_DPGV1_PIPE_DPM_CONTROL_DEFAULT 0x00003000
+-#define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_DEFAULT 0x00000200
+-#define mmDMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL_DEFAULT 0x00000000
+-#define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH_DEFAULT 0x00000200
+-#define mmDMIFV_PG0_DPGV1_REPEATER_PROGRAM_DEFAULT 0x00000000
+-#define mmDMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_blndv0_dispdec
+-#define mmBLNDV0_BLNDV_CONTROL_DEFAULT 0xff0220ff
+-#define mmBLNDV0_BLNDV_SM_CONTROL2_DEFAULT 0x00000000
+-#define mmBLNDV0_BLNDV_CONTROL2_DEFAULT 0x00000010
+-#define mmBLNDV0_BLNDV_UPDATE_DEFAULT 0x00000000
+-#define mmBLNDV0_BLNDV_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000
+-#define mmBLNDV0_BLNDV_V_UPDATE_LOCK_DEFAULT 0x80000000
+-#define mmBLNDV0_BLNDV_REG_UPDATE_STATUS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_crtcv0_dispdec
+-#define mmCRTCV0_CRTCV_H_BLANK_EARLY_NUM_DEFAULT 0x00000040
+-#define mmCRTCV0_CRTCV_H_TOTAL_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_H_BLANK_START_END_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_H_SYNC_A_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_H_SYNC_A_CNTL_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_H_SYNC_B_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_H_SYNC_B_CNTL_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_VBI_END_DEFAULT 0x00000003
+-#define mmCRTCV0_CRTCV_V_TOTAL_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_V_TOTAL_MIN_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_V_TOTAL_MAX_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_V_TOTAL_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_V_TOTAL_INT_STATUS_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_V_BLANK_START_END_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_V_SYNC_A_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_V_SYNC_A_CNTL_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_V_SYNC_B_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_V_SYNC_B_CNTL_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_DTMTEST_CNTL_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_TRIGA_CNTL_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_TRIGB_CNTL_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_FLOW_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_AVSYNC_COUNTER_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_CONTROL_DEFAULT 0x80400110
+-#define mmCRTCV0_CRTCV_BLANK_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_INTERLACE_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_INTERLACE_STATUS_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK0_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK1_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_STATUS_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_STATUS_POSITION_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_NOM_VERT_POSITION_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_STATUS_FRAME_COUNT_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_STATUS_VF_COUNT_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_STATUS_HV_COUNT_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_COUNT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_COUNT_RESET_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_VERT_SYNC_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_STEREO_STATUS_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_STEREO_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_SNAPSHOT_STATUS_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_SNAPSHOT_POSITION_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_SNAPSHOT_FRAME_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_START_LINE_CONTROL_DEFAULT 0x00003002
+-#define mmCRTCV0_CRTCV_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_UPDATE_LOCK_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_TEST_PATTERN_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_TEST_PATTERN_COLOR_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_MASTER_UPDATE_LOCK_DEFAULT 0x00010000
+-#define mmCRTCV0_CRTCV_MASTER_UPDATE_MODE_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008
+-#define mmCRTCV0_CRTCV_MVP_STATUS_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_MASTER_EN_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000
+-#define mmCRTCV0_CRTCV_V_UPDATE_INT_STATUS_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_OVERSCAN_COLOR_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_BLANK_DATA_COLOR_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_BLACK_COLOR_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_BLACK_COLOR_EXT_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_CRC_CNTL_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_CRC0_DATA_RG_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_CRC0_DATA_B_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_CRC1_DATA_RG_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_CRC1_DATA_B_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000
+-#define mmCRTCV0_CRTCV_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010
+-#define mmCRTCV0_CRTCV_GSL_VSYNC_GAP_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_GSL_WINDOW_DEFAULT 0x00000000
+-#define mmCRTCV0_CRTCV_GSL_CONTROL_DEFAULT 0x00020000
+-
+-
+-// addressBlock: dce_dc_unp1_dispdec
+-#define mmUNP1_UNP_GRPH_ENABLE_DEFAULT 0x00000001
+-#define mmUNP1_UNP_GRPH_CONTROL_DEFAULT 0x0a008008
+-#define mmUNP1_UNP_GRPH_CONTROL_C_DEFAULT 0x00008000
+-#define mmUNP1_UNP_GRPH_CONTROL_EXP_DEFAULT 0x00000000
+-#define mmUNP1_UNP_GRPH_SWAP_CNTL_DEFAULT 0x00000000
+-#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L_DEFAULT 0x00000000
+-#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000
+-#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000
+-#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000
+-#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_DEFAULT 0x00000000
+-#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_DEFAULT 0x00000000
+-#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000
+-#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000
+-#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L_DEFAULT 0x00000000
+-#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000
+-#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000
+-#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000
+-#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_DEFAULT 0x00000000
+-#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_DEFAULT 0x00000000
+-#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000
+-#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000
+-#define mmUNP1_UNP_GRPH_PITCH_L_DEFAULT 0x00000000
+-#define mmUNP1_UNP_GRPH_PITCH_C_DEFAULT 0x00000000
+-#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_L_DEFAULT 0x00000000
+-#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_C_DEFAULT 0x00000000
+-#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_L_DEFAULT 0x00000000
+-#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_C_DEFAULT 0x00000000
+-#define mmUNP1_UNP_GRPH_X_START_L_DEFAULT 0x00000000
+-#define mmUNP1_UNP_GRPH_X_START_C_DEFAULT 0x00000000
+-#define mmUNP1_UNP_GRPH_Y_START_L_DEFAULT 0x00000000
+-#define mmUNP1_UNP_GRPH_Y_START_C_DEFAULT 0x00000000
+-#define mmUNP1_UNP_GRPH_X_END_L_DEFAULT 0x00000000
+-#define mmUNP1_UNP_GRPH_X_END_C_DEFAULT 0x00000000
+-#define mmUNP1_UNP_GRPH_Y_END_L_DEFAULT 0x00000000
+-#define mmUNP1_UNP_GRPH_Y_END_C_DEFAULT 0x00000000
+-#define mmUNP1_UNP_GRPH_UPDATE_DEFAULT 0x00000000
+-#define mmUNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x0000ffff
+-#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L_DEFAULT 0x00000000
+-#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C_DEFAULT 0x00000000
+-#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_DEFAULT 0x00000000
+-#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_DEFAULT 0x00000000
+-#define mmUNP1_UNP_DVMM_PTE_CONTROL_DEFAULT 0x00004000
+-#define mmUNP1_UNP_DVMM_PTE_CONTROL_C_DEFAULT 0x00004000
+-#define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220
+-#define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL_C_DEFAULT 0x00002220
+-#define mmUNP1_UNP_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000
+-#define mmUNP1_UNP_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmUNP1_UNP_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00002020
+-#define mmUNP1_UNP_FLIP_CONTROL_DEFAULT 0x00000001
+-#define mmUNP1_UNP_CRC_CONTROL_DEFAULT 0x00000000
+-#define mmUNP1_UNP_CRC_MASK_DEFAULT 0x00000000
+-#define mmUNP1_UNP_CRC_CURRENT_DEFAULT 0x00000000
+-#define mmUNP1_UNP_CRC_LAST_DEFAULT 0x00000000
+-#define mmUNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000100
+-#define mmUNP1_UNP_HW_ROTATION_DEFAULT 0x00000010
+-
+-
+-// addressBlock: dce_dc_lbv1_dispdec
+-#define mmLBV1_LBV_DATA_FORMAT_DEFAULT 0x00000000
+-#define mmLBV1_LBV_MEMORY_CTRL_DEFAULT 0x000006b0
+-#define mmLBV1_LBV_MEMORY_SIZE_STATUS_DEFAULT 0x00000000
+-#define mmLBV1_LBV_DESKTOP_HEIGHT_DEFAULT 0x00000000
+-#define mmLBV1_LBV_VLINE_START_END_DEFAULT 0x00000000
+-#define mmLBV1_LBV_VLINE2_START_END_DEFAULT 0x00000000
+-#define mmLBV1_LBV_V_COUNTER_DEFAULT 0x00000000
+-#define mmLBV1_LBV_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000
+-#define mmLBV1_LBV_V_COUNTER_CHROMA_DEFAULT 0x00000000
+-#define mmLBV1_LBV_SNAPSHOT_V_COUNTER_CHROMA_DEFAULT 0x00000000
+-#define mmLBV1_LBV_INTERRUPT_MASK_DEFAULT 0x00000000
+-#define mmLBV1_LBV_VLINE_STATUS_DEFAULT 0x00000000
+-#define mmLBV1_LBV_VLINE2_STATUS_DEFAULT 0x00000000
+-#define mmLBV1_LBV_VBLANK_STATUS_DEFAULT 0x00000000
+-#define mmLBV1_LBV_SYNC_RESET_SEL_DEFAULT 0x00000002
+-#define mmLBV1_LBV_BLACK_KEYER_R_CR_DEFAULT 0x00000000
+-#define mmLBV1_LBV_BLACK_KEYER_G_Y_DEFAULT 0x00000000
+-#define mmLBV1_LBV_BLACK_KEYER_B_CB_DEFAULT 0x00000000
+-#define mmLBV1_LBV_KEYER_COLOR_CTRL_DEFAULT 0x00000000
+-#define mmLBV1_LBV_KEYER_COLOR_R_CR_DEFAULT 0x00000000
+-#define mmLBV1_LBV_KEYER_COLOR_G_Y_DEFAULT 0x00000000
+-#define mmLBV1_LBV_KEYER_COLOR_B_CB_DEFAULT 0x00000000
+-#define mmLBV1_LBV_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000
+-#define mmLBV1_LBV_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000
+-#define mmLBV1_LBV_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000
+-#define mmLBV1_LBV_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000
+-#define mmLBV1_LBV_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010
+-#define mmLBV1_LBV_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000
+-#define mmLBV1_LBV_BUFFER_STATUS_DEFAULT 0x12000002
+-#define mmLBV1_LBV_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_sclv1_dispdec
+-#define mmSCLV1_SCLV_COEF_RAM_SELECT_DEFAULT 0x00000000
+-#define mmSCLV1_SCLV_COEF_RAM_TAP_DATA_DEFAULT 0x00000000
+-#define mmSCLV1_SCLV_MODE_DEFAULT 0x00000000
+-#define mmSCLV1_SCLV_TAP_CONTROL_DEFAULT 0x00000000
+-#define mmSCLV1_SCLV_CONTROL_DEFAULT 0x00000000
+-#define mmSCLV1_SCLV_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000
+-#define mmSCLV1_SCLV_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000
+-#define mmSCLV1_SCLV_HORZ_FILTER_CONTROL_DEFAULT 0x00000000
+-#define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000
+-#define mmSCLV1_SCLV_HORZ_FILTER_INIT_DEFAULT 0x01000000
+-#define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000
+-#define mmSCLV1_SCLV_HORZ_FILTER_INIT_C_DEFAULT 0x01000000
+-#define mmSCLV1_SCLV_VERT_FILTER_CONTROL_DEFAULT 0x00000000
+-#define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000
+-#define mmSCLV1_SCLV_VERT_FILTER_INIT_DEFAULT 0x01000000
+-#define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000
+-#define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000
+-#define mmSCLV1_SCLV_VERT_FILTER_INIT_C_DEFAULT 0x01000000
+-#define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_C_DEFAULT 0x01000000
+-#define mmSCLV1_SCLV_ROUND_OFFSET_DEFAULT 0x80000000
+-#define mmSCLV1_SCLV_UPDATE_DEFAULT 0x00000000
+-#define mmSCLV1_SCLV_ALU_CONTROL_DEFAULT 0x00000000
+-#define mmSCLV1_SCLV_VIEWPORT_START_DEFAULT 0x00000000
+-#define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000
+-#define mmSCLV1_SCLV_VIEWPORT_SIZE_DEFAULT 0x00000000
+-#define mmSCLV1_SCLV_VIEWPORT_START_C_DEFAULT 0x00000000
+-#define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_C_DEFAULT 0x00000000
+-#define mmSCLV1_SCLV_VIEWPORT_SIZE_C_DEFAULT 0x00000000
+-#define mmSCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000
+-#define mmSCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000
+-#define mmSCLV1_SCLV_MODE_CHANGE_DET1_DEFAULT 0x00000000
+-#define mmSCLV1_SCLV_MODE_CHANGE_DET2_DEFAULT 0x00000000
+-#define mmSCLV1_SCLV_MODE_CHANGE_DET3_DEFAULT 0x00000000
+-#define mmSCLV1_SCLV_MODE_CHANGE_MASK_DEFAULT 0x00000000
+-#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_DEFAULT 0x01000000
+-#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_C_DEFAULT 0x01000000
+-
+-
+-// addressBlock: dce_dc_col_man1_dispdec
+-#define mmCOL_MAN1_COL_MAN_UPDATE_DEFAULT 0x00000000
+-#define mmCOL_MAN1_COL_MAN_INPUT_CSC_CONTROL_DEFAULT 0x00000000
+-#define mmCOL_MAN1_INPUT_CSC_C11_C12_A_DEFAULT 0x00002000
+-#define mmCOL_MAN1_INPUT_CSC_C13_C14_A_DEFAULT 0x00000000
+-#define mmCOL_MAN1_INPUT_CSC_C21_C22_A_DEFAULT 0x20000000
+-#define mmCOL_MAN1_INPUT_CSC_C23_C24_A_DEFAULT 0x00000000
+-#define mmCOL_MAN1_INPUT_CSC_C31_C32_A_DEFAULT 0x00000000
+-#define mmCOL_MAN1_INPUT_CSC_C33_C34_A_DEFAULT 0x00002000
+-#define mmCOL_MAN1_INPUT_CSC_C11_C12_B_DEFAULT 0x00002000
+-#define mmCOL_MAN1_INPUT_CSC_C13_C14_B_DEFAULT 0x00000000
+-#define mmCOL_MAN1_INPUT_CSC_C21_C22_B_DEFAULT 0x20000000
+-#define mmCOL_MAN1_INPUT_CSC_C23_C24_B_DEFAULT 0x00000000
+-#define mmCOL_MAN1_INPUT_CSC_C31_C32_B_DEFAULT 0x00000000
+-#define mmCOL_MAN1_INPUT_CSC_C33_C34_B_DEFAULT 0x00002000
+-#define mmCOL_MAN1_PRESCALE_CONTROL_DEFAULT 0x00000000
+-#define mmCOL_MAN1_PRESCALE_VALUES_R_DEFAULT 0x20000000
+-#define mmCOL_MAN1_PRESCALE_VALUES_G_DEFAULT 0x20000000
+-#define mmCOL_MAN1_PRESCALE_VALUES_B_DEFAULT 0x20000000
+-#define mmCOL_MAN1_COL_MAN_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000
+-#define mmCOL_MAN1_OUTPUT_CSC_C11_C12_A_DEFAULT 0x00002000
+-#define mmCOL_MAN1_OUTPUT_CSC_C13_C14_A_DEFAULT 0x00000000
+-#define mmCOL_MAN1_OUTPUT_CSC_C21_C22_A_DEFAULT 0x20000000
+-#define mmCOL_MAN1_OUTPUT_CSC_C23_C24_A_DEFAULT 0x00000000
+-#define mmCOL_MAN1_OUTPUT_CSC_C31_C32_A_DEFAULT 0x00000000
+-#define mmCOL_MAN1_OUTPUT_CSC_C33_C34_A_DEFAULT 0x00002000
+-#define mmCOL_MAN1_OUTPUT_CSC_C11_C12_B_DEFAULT 0x00002000
+-#define mmCOL_MAN1_OUTPUT_CSC_C13_C14_B_DEFAULT 0x00000000
+-#define mmCOL_MAN1_OUTPUT_CSC_C21_C22_B_DEFAULT 0x20000000
+-#define mmCOL_MAN1_OUTPUT_CSC_C23_C24_B_DEFAULT 0x00000000
+-#define mmCOL_MAN1_OUTPUT_CSC_C31_C32_B_DEFAULT 0x00000000
+-#define mmCOL_MAN1_OUTPUT_CSC_C33_C34_B_DEFAULT 0x00002000
+-#define mmCOL_MAN1_DENORM_CLAMP_CONTROL_DEFAULT 0x00000000
+-#define mmCOL_MAN1_DENORM_CLAMP_RANGE_R_CR_DEFAULT 0x00000fff
+-#define mmCOL_MAN1_DENORM_CLAMP_RANGE_G_Y_DEFAULT 0x00000fff
+-#define mmCOL_MAN1_DENORM_CLAMP_RANGE_B_CB_DEFAULT 0x00000fff
+-#define mmCOL_MAN1_COL_MAN_FP_CONVERTED_FIELD_DEFAULT 0x00000000
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CONTROL_DEFAULT 0x00000000
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_INDEX_DEFAULT 0x00000000
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_DATA_DEFAULT 0x00000000
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000
+-#define mmCOL_MAN1_PACK_FIFO_ERROR_DEFAULT 0x00000000
+-#define mmCOL_MAN1_OUTPUT_FIFO_ERROR_DEFAULT 0x00000000
+-#define mmCOL_MAN1_INPUT_GAMMA_LUT_AUTOFILL_DEFAULT 0x00000000
+-#define mmCOL_MAN1_INPUT_GAMMA_LUT_RW_INDEX_DEFAULT 0x00000000
+-#define mmCOL_MAN1_INPUT_GAMMA_LUT_SEQ_COLOR_DEFAULT 0x00000000
+-#define mmCOL_MAN1_INPUT_GAMMA_LUT_PWL_DATA_DEFAULT 0x00000000
+-#define mmCOL_MAN1_INPUT_GAMMA_LUT_30_COLOR_DEFAULT 0x00000000
+-#define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1_DEFAULT 0x00000000
+-#define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2_DEFAULT 0x03800000
+-#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_B_DEFAULT 0xffff0000
+-#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_G_DEFAULT 0xffff0000
+-#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_R_DEFAULT 0xffff0000
+-#define mmCOL_MAN1_COL_MAN_DEGAMMA_CONTROL_DEFAULT 0x00000000
+-#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000
+-#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000
+-#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000
+-#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000
+-#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000
+-#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000
+-#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000
+-
+-
+-// addressBlock: dce_dc_dcfev1_dispdec
+-#define mmDCFEV1_DCFEV_CLOCK_CONTROL_DEFAULT 0x00000000
+-#define mmDCFEV1_DCFEV_SOFT_RESET_DEFAULT 0x00000000
+-#define mmDCFEV1_DCFEV_DMIFV_CLOCK_CONTROL_DEFAULT 0x00000000
+-#define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL_DEFAULT 0x00000000
+-#define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS_DEFAULT 0x00000000
+-#define mmDCFEV1_DCFEV_MEM_PWR_CTRL_DEFAULT 0x00000000
+-#define mmDCFEV1_DCFEV_MEM_PWR_CTRL2_DEFAULT 0x00000000
+-#define mmDCFEV1_DCFEV_MEM_PWR_STATUS_DEFAULT 0x00000000
+-#define mmDCFEV1_DCFEV_L_FLUSH_DEFAULT 0x00000000
+-#define mmDCFEV1_DCFEV_C_FLUSH_DEFAULT 0x00000000
+-#define mmDCFEV1_DCFEV_MISC_DEFAULT 0x00000001
+-
+-
+-// addressBlock: dce_dc_dc_perfmon12_dispdec
+-#define mmDC_PERFMON12_PERFCOUNTER_CNTL_DEFAULT 0x00000000
+-#define mmDC_PERFMON12_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
+-#define mmDC_PERFMON12_PERFCOUNTER_STATE_DEFAULT 0x00000000
+-#define mmDC_PERFMON12_PERFMON_CNTL_DEFAULT 0x00000100
+-#define mmDC_PERFMON12_PERFMON_CNTL2_DEFAULT 0x00000000
+-#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
+-#define mmDC_PERFMON12_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
+-#define mmDC_PERFMON12_PERFMON_HI_DEFAULT 0x00000000
+-#define mmDC_PERFMON12_PERFMON_LOW_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dmifv_pg1_dispdec
+-#define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000
+-#define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000
+-#define mmDMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL_DEFAULT 0x00030303
+-#define mmDMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000
+-#define mmDMIFV_PG1_DPGV0_PIPE_DPM_CONTROL_DEFAULT 0x00003000
+-#define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_DEFAULT 0x00000200
+-#define mmDMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL_DEFAULT 0x00000000
+-#define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH_DEFAULT 0x00000200
+-#define mmDMIFV_PG1_DPGV0_REPEATER_PROGRAM_DEFAULT 0x00000000
+-#define mmDMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000
+-#define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000
+-#define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000
+-#define mmDMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL_DEFAULT 0x00030303
+-#define mmDMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000
+-#define mmDMIFV_PG1_DPGV1_PIPE_DPM_CONTROL_DEFAULT 0x00003000
+-#define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_DEFAULT 0x00000200
+-#define mmDMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL_DEFAULT 0x00000000
+-#define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH_DEFAULT 0x00000200
+-#define mmDMIFV_PG1_DPGV1_REPEATER_PROGRAM_DEFAULT 0x00000000
+-#define mmDMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_blndv1_dispdec
+-#define mmBLNDV1_BLNDV_CONTROL_DEFAULT 0xff0220ff
+-#define mmBLNDV1_BLNDV_SM_CONTROL2_DEFAULT 0x00000000
+-#define mmBLNDV1_BLNDV_CONTROL2_DEFAULT 0x00000010
+-#define mmBLNDV1_BLNDV_UPDATE_DEFAULT 0x00000000
+-#define mmBLNDV1_BLNDV_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000
+-#define mmBLNDV1_BLNDV_V_UPDATE_LOCK_DEFAULT 0x80000000
+-#define mmBLNDV1_BLNDV_REG_UPDATE_STATUS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_crtcv1_dispdec
+-#define mmCRTCV1_CRTCV_H_BLANK_EARLY_NUM_DEFAULT 0x00000040
+-#define mmCRTCV1_CRTCV_H_TOTAL_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_H_BLANK_START_END_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_H_SYNC_A_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_H_SYNC_A_CNTL_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_H_SYNC_B_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_H_SYNC_B_CNTL_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_VBI_END_DEFAULT 0x00000003
+-#define mmCRTCV1_CRTCV_V_TOTAL_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_V_TOTAL_MIN_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_V_TOTAL_MAX_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_V_TOTAL_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_V_TOTAL_INT_STATUS_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_V_BLANK_START_END_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_V_SYNC_A_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_V_SYNC_A_CNTL_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_V_SYNC_B_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_V_SYNC_B_CNTL_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_DTMTEST_CNTL_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_TRIGA_CNTL_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_TRIGB_CNTL_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_FLOW_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_AVSYNC_COUNTER_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_CONTROL_DEFAULT 0x80400110
+-#define mmCRTCV1_CRTCV_BLANK_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_INTERLACE_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_INTERLACE_STATUS_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK0_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK1_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_STATUS_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_STATUS_POSITION_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_NOM_VERT_POSITION_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_STATUS_FRAME_COUNT_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_STATUS_VF_COUNT_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_STATUS_HV_COUNT_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_COUNT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_COUNT_RESET_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_VERT_SYNC_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_STEREO_STATUS_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_STEREO_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_SNAPSHOT_STATUS_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_SNAPSHOT_POSITION_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_SNAPSHOT_FRAME_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_START_LINE_CONTROL_DEFAULT 0x00003002
+-#define mmCRTCV1_CRTCV_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_UPDATE_LOCK_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_TEST_PATTERN_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_TEST_PATTERN_COLOR_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_MASTER_UPDATE_LOCK_DEFAULT 0x00010000
+-#define mmCRTCV1_CRTCV_MASTER_UPDATE_MODE_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008
+-#define mmCRTCV1_CRTCV_MVP_STATUS_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_MASTER_EN_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000
+-#define mmCRTCV1_CRTCV_V_UPDATE_INT_STATUS_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_OVERSCAN_COLOR_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_BLANK_DATA_COLOR_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_BLACK_COLOR_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_BLACK_COLOR_EXT_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_CRC_CNTL_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_CRC0_DATA_RG_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_CRC0_DATA_B_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_CRC1_DATA_RG_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_CRC1_DATA_B_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000
+-#define mmCRTCV1_CRTCV_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010
+-#define mmCRTCV1_CRTCV_GSL_VSYNC_GAP_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_GSL_WINDOW_DEFAULT 0x00000000
+-#define mmCRTCV1_CRTCV_GSL_CONTROL_DEFAULT 0x00020000
+-
+-
+-// addressBlock: dce_dc_hpd0_dispdec
+-#define mmHPD0_DC_HPD_INT_STATUS_DEFAULT 0x00000000
+-#define mmHPD0_DC_HPD_INT_CONTROL_DEFAULT 0x00000000
+-#define mmHPD0_DC_HPD_CONTROL_DEFAULT 0x10fa09c4
+-#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000
+-#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_hpd1_dispdec
+-#define mmHPD1_DC_HPD_INT_STATUS_DEFAULT 0x00000000
+-#define mmHPD1_DC_HPD_INT_CONTROL_DEFAULT 0x00000000
+-#define mmHPD1_DC_HPD_CONTROL_DEFAULT 0x10fa09c4
+-#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000
+-#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_hpd2_dispdec
+-#define mmHPD2_DC_HPD_INT_STATUS_DEFAULT 0x00000000
+-#define mmHPD2_DC_HPD_INT_CONTROL_DEFAULT 0x00000000
+-#define mmHPD2_DC_HPD_CONTROL_DEFAULT 0x10fa09c4
+-#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000
+-#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_hpd3_dispdec
+-#define mmHPD3_DC_HPD_INT_STATUS_DEFAULT 0x00000000
+-#define mmHPD3_DC_HPD_INT_CONTROL_DEFAULT 0x00000000
+-#define mmHPD3_DC_HPD_CONTROL_DEFAULT 0x10fa09c4
+-#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000
+-#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_hpd4_dispdec
+-#define mmHPD4_DC_HPD_INT_STATUS_DEFAULT 0x00000000
+-#define mmHPD4_DC_HPD_INT_CONTROL_DEFAULT 0x00000000
+-#define mmHPD4_DC_HPD_CONTROL_DEFAULT 0x10fa09c4
+-#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000
+-#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_hpd5_dispdec
+-#define mmHPD5_DC_HPD_INT_STATUS_DEFAULT 0x00000000
+-#define mmHPD5_DC_HPD_INT_CONTROL_DEFAULT 0x00000000
+-#define mmHPD5_DC_HPD_CONTROL_DEFAULT 0x10fa09c4
+-#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000
+-#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dc_perfmon2_dispdec
+-#define mmDC_PERFMON2_PERFCOUNTER_CNTL_DEFAULT 0x00000000
+-#define mmDC_PERFMON2_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
+-#define mmDC_PERFMON2_PERFCOUNTER_STATE_DEFAULT 0x00000000
+-#define mmDC_PERFMON2_PERFMON_CNTL_DEFAULT 0x00000100
+-#define mmDC_PERFMON2_PERFMON_CNTL2_DEFAULT 0x00000000
+-#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
+-#define mmDC_PERFMON2_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
+-#define mmDC_PERFMON2_PERFMON_HI_DEFAULT 0x00000000
+-#define mmDC_PERFMON2_PERFMON_LOW_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dp_aux0_dispdec
+-#define mmDP_AUX0_AUX_CONTROL_DEFAULT 0x01040000
+-#define mmDP_AUX0_AUX_SW_CONTROL_DEFAULT 0x00000000
+-#define mmDP_AUX0_AUX_ARB_CONTROL_DEFAULT 0x00000000
+-#define mmDP_AUX0_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmDP_AUX0_AUX_SW_STATUS_DEFAULT 0x00000000
+-#define mmDP_AUX0_AUX_LS_STATUS_DEFAULT 0x00000000
+-#define mmDP_AUX0_AUX_SW_DATA_DEFAULT 0x00000000
+-#define mmDP_AUX0_AUX_LS_DATA_DEFAULT 0x00000000
+-#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000
+-#define mmDP_AUX0_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002
+-#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210
+-#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000
+-#define mmDP_AUX0_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000
+-#define mmDP_AUX0_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000
+-#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000
+-#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000
+-#define mmDP_AUX0_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dp_aux1_dispdec
+-#define mmDP_AUX1_AUX_CONTROL_DEFAULT 0x01040000
+-#define mmDP_AUX1_AUX_SW_CONTROL_DEFAULT 0x00000000
+-#define mmDP_AUX1_AUX_ARB_CONTROL_DEFAULT 0x00000000
+-#define mmDP_AUX1_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmDP_AUX1_AUX_SW_STATUS_DEFAULT 0x00000000
+-#define mmDP_AUX1_AUX_LS_STATUS_DEFAULT 0x00000000
+-#define mmDP_AUX1_AUX_SW_DATA_DEFAULT 0x00000000
+-#define mmDP_AUX1_AUX_LS_DATA_DEFAULT 0x00000000
+-#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000
+-#define mmDP_AUX1_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002
+-#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210
+-#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000
+-#define mmDP_AUX1_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000
+-#define mmDP_AUX1_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000
+-#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000
+-#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000
+-#define mmDP_AUX1_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dp_aux2_dispdec
+-#define mmDP_AUX2_AUX_CONTROL_DEFAULT 0x01040000
+-#define mmDP_AUX2_AUX_SW_CONTROL_DEFAULT 0x00000000
+-#define mmDP_AUX2_AUX_ARB_CONTROL_DEFAULT 0x00000000
+-#define mmDP_AUX2_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmDP_AUX2_AUX_SW_STATUS_DEFAULT 0x00000000
+-#define mmDP_AUX2_AUX_LS_STATUS_DEFAULT 0x00000000
+-#define mmDP_AUX2_AUX_SW_DATA_DEFAULT 0x00000000
+-#define mmDP_AUX2_AUX_LS_DATA_DEFAULT 0x00000000
+-#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000
+-#define mmDP_AUX2_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002
+-#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210
+-#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000
+-#define mmDP_AUX2_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000
+-#define mmDP_AUX2_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000
+-#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000
+-#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000
+-#define mmDP_AUX2_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dp_aux3_dispdec
+-#define mmDP_AUX3_AUX_CONTROL_DEFAULT 0x01040000
+-#define mmDP_AUX3_AUX_SW_CONTROL_DEFAULT 0x00000000
+-#define mmDP_AUX3_AUX_ARB_CONTROL_DEFAULT 0x00000000
+-#define mmDP_AUX3_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmDP_AUX3_AUX_SW_STATUS_DEFAULT 0x00000000
+-#define mmDP_AUX3_AUX_LS_STATUS_DEFAULT 0x00000000
+-#define mmDP_AUX3_AUX_SW_DATA_DEFAULT 0x00000000
+-#define mmDP_AUX3_AUX_LS_DATA_DEFAULT 0x00000000
+-#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000
+-#define mmDP_AUX3_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002
+-#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210
+-#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000
+-#define mmDP_AUX3_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000
+-#define mmDP_AUX3_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000
+-#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000
+-#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000
+-#define mmDP_AUX3_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dp_aux4_dispdec
+-#define mmDP_AUX4_AUX_CONTROL_DEFAULT 0x01040000
+-#define mmDP_AUX4_AUX_SW_CONTROL_DEFAULT 0x00000000
+-#define mmDP_AUX4_AUX_ARB_CONTROL_DEFAULT 0x00000000
+-#define mmDP_AUX4_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmDP_AUX4_AUX_SW_STATUS_DEFAULT 0x00000000
+-#define mmDP_AUX4_AUX_LS_STATUS_DEFAULT 0x00000000
+-#define mmDP_AUX4_AUX_SW_DATA_DEFAULT 0x00000000
+-#define mmDP_AUX4_AUX_LS_DATA_DEFAULT 0x00000000
+-#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000
+-#define mmDP_AUX4_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002
+-#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210
+-#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000
+-#define mmDP_AUX4_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000
+-#define mmDP_AUX4_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000
+-#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000
+-#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000
+-#define mmDP_AUX4_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dp_aux5_dispdec
+-#define mmDP_AUX5_AUX_CONTROL_DEFAULT 0x01040000
+-#define mmDP_AUX5_AUX_SW_CONTROL_DEFAULT 0x00000000
+-#define mmDP_AUX5_AUX_ARB_CONTROL_DEFAULT 0x00000000
+-#define mmDP_AUX5_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000
+-#define mmDP_AUX5_AUX_SW_STATUS_DEFAULT 0x00000000
+-#define mmDP_AUX5_AUX_LS_STATUS_DEFAULT 0x00000000
+-#define mmDP_AUX5_AUX_SW_DATA_DEFAULT 0x00000000
+-#define mmDP_AUX5_AUX_LS_DATA_DEFAULT 0x00000000
+-#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000
+-#define mmDP_AUX5_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002
+-#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210
+-#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000
+-#define mmDP_AUX5_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000
+-#define mmDP_AUX5_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000
+-#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000
+-#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000
+-#define mmDP_AUX5_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dig0_dispdec
+-#define mmDIG0_DIG_FE_CNTL_DEFAULT 0x00000000
+-#define mmDIG0_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100
+-#define mmDIG0_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000
+-#define mmDIG0_DIG_CLOCK_PATTERN_DEFAULT 0x00000063
+-#define mmDIG0_DIG_TEST_PATTERN_DEFAULT 0x00000060
+-#define mmDIG0_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222
+-#define mmDIG0_DIG_FIFO_STATUS_DEFAULT 0x00000000
+-#define mmDIG0_HDMI_CONTROL_DEFAULT 0x00010001
+-#define mmDIG0_HDMI_STATUS_DEFAULT 0x00000000
+-#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010
+-#define mmDIG0_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000
+-#define mmDIG0_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000
+-#define mmDIG0_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000
+-#define mmDIG0_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000
+-#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000
+-#define mmDIG0_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000
+-#define mmDIG0_HDMI_GC_DEFAULT 0x00000004
+-#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000
+-#define mmDIG0_AFMT_ISRC1_0_DEFAULT 0x00000000
+-#define mmDIG0_AFMT_ISRC1_1_DEFAULT 0x00000000
+-#define mmDIG0_AFMT_ISRC1_2_DEFAULT 0x00000000
+-#define mmDIG0_AFMT_ISRC1_3_DEFAULT 0x00000000
+-#define mmDIG0_AFMT_ISRC1_4_DEFAULT 0x00000000
+-#define mmDIG0_AFMT_ISRC2_0_DEFAULT 0x00000000
+-#define mmDIG0_AFMT_ISRC2_1_DEFAULT 0x00000000
+-#define mmDIG0_AFMT_ISRC2_2_DEFAULT 0x00000000
+-#define mmDIG0_AFMT_ISRC2_3_DEFAULT 0x00000000
+-#define mmDIG0_AFMT_AVI_INFO0_DEFAULT 0x00000000
+-#define mmDIG0_AFMT_AVI_INFO1_DEFAULT 0x00000000
+-#define mmDIG0_AFMT_AVI_INFO2_DEFAULT 0x00000000
+-#define mmDIG0_AFMT_AVI_INFO3_DEFAULT 0x02000000
+-#define mmDIG0_AFMT_MPEG_INFO0_DEFAULT 0x00000000
+-#define mmDIG0_AFMT_MPEG_INFO1_DEFAULT 0x00000000
+-#define mmDIG0_AFMT_GENERIC_HDR_DEFAULT 0x00000000
+-#define mmDIG0_AFMT_GENERIC_0_DEFAULT 0x00000000
+-#define mmDIG0_AFMT_GENERIC_1_DEFAULT 0x00000000
+-#define mmDIG0_AFMT_GENERIC_2_DEFAULT 0x00000000
+-#define mmDIG0_AFMT_GENERIC_3_DEFAULT 0x00000000
+-#define mmDIG0_AFMT_GENERIC_4_DEFAULT 0x00000000
+-#define mmDIG0_AFMT_GENERIC_5_DEFAULT 0x00000000
+-#define mmDIG0_AFMT_GENERIC_6_DEFAULT 0x00000000
+-#define mmDIG0_AFMT_GENERIC_7_DEFAULT 0x00000000
+-#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000
+-#define mmDIG0_HDMI_ACR_32_0_DEFAULT 0x00000000
+-#define mmDIG0_HDMI_ACR_32_1_DEFAULT 0x00000000
+-#define mmDIG0_HDMI_ACR_44_0_DEFAULT 0x00000000
+-#define mmDIG0_HDMI_ACR_44_1_DEFAULT 0x00000000
+-#define mmDIG0_HDMI_ACR_48_0_DEFAULT 0x00000000
+-#define mmDIG0_HDMI_ACR_48_1_DEFAULT 0x00000000
+-#define mmDIG0_HDMI_ACR_STATUS_0_DEFAULT 0x00000000
+-#define mmDIG0_HDMI_ACR_STATUS_1_DEFAULT 0x00000000
+-#define mmDIG0_AFMT_AUDIO_INFO0_DEFAULT 0x00000170
+-#define mmDIG0_AFMT_AUDIO_INFO1_DEFAULT 0x00000000
+-#define mmDIG0_AFMT_60958_0_DEFAULT 0x00000000
+-#define mmDIG0_AFMT_60958_1_DEFAULT 0x00000000
+-#define mmDIG0_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000
+-#define mmDIG0_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000
+-#define mmDIG0_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000
+-#define mmDIG0_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000
+-#define mmDIG0_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000
+-#define mmDIG0_AFMT_60958_2_DEFAULT 0x00000000
+-#define mmDIG0_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000
+-#define mmDIG0_AFMT_STATUS_DEFAULT 0x00000000
+-#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800
+-#define mmDIG0_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000
+-#define mmDIG0_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000
+-#define mmDIG0_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000
+-#define mmDIG0_DIG_BE_CNTL_DEFAULT 0x00010000
+-#define mmDIG0_DIG_BE_EN_CNTL_DEFAULT 0x00000000
+-#define mmDIG0_TMDS_CNTL_DEFAULT 0x00000001
+-#define mmDIG0_TMDS_CONTROL_CHAR_DEFAULT 0x00000000
+-#define mmDIG0_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000
+-#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000
+-#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000
+-#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000
+-#define mmDIG0_TMDS_CTL_BITS_DEFAULT 0x00000000
+-#define mmDIG0_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001
+-#define mmDIG0_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000
+-#define mmDIG0_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000
+-#define mmDIG0_DIG_VERSION_DEFAULT 0x00000000
+-#define mmDIG0_DIG_LANE_ENABLE_DEFAULT 0x00000000
+-#define mmDIG0_AFMT_CNTL_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dp0_dispdec
+-#define mmDP0_DP_LINK_CNTL_DEFAULT 0x00000000
+-#define mmDP0_DP_PIXEL_FORMAT_DEFAULT 0x00000000
+-#define mmDP0_DP_MSA_COLORIMETRY_DEFAULT 0x00000000
+-#define mmDP0_DP_CONFIG_DEFAULT 0x00000000
+-#define mmDP0_DP_VID_STREAM_CNTL_DEFAULT 0x00000200
+-#define mmDP0_DP_STEER_FIFO_DEFAULT 0x00000000
+-#define mmDP0_DP_MSA_MISC_DEFAULT 0x00000000
+-#define mmDP0_DP_VID_TIMING_DEFAULT 0x00000000
+-#define mmDP0_DP_VID_N_DEFAULT 0x00002000
+-#define mmDP0_DP_VID_M_DEFAULT 0x00000000
+-#define mmDP0_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000
+-#define mmDP0_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000
+-#define mmDP0_DP_VID_MSA_VBID_DEFAULT 0x01000000
+-#define mmDP0_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000
+-#define mmDP0_DP_DPHY_CNTL_DEFAULT 0x00000000
+-#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000
+-#define mmDP0_DP_DPHY_SYM0_DEFAULT 0x00000000
+-#define mmDP0_DP_DPHY_SYM1_DEFAULT 0x00000000
+-#define mmDP0_DP_DPHY_SYM2_DEFAULT 0x00000000
+-#define mmDP0_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000
+-#define mmDP0_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00
+-#define mmDP0_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10
+-#define mmDP0_DP_DPHY_CRC_EN_DEFAULT 0x00000000
+-#define mmDP0_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000
+-#define mmDP0_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000
+-#define mmDP0_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000
+-#define mmDP0_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000
+-#define mmDP0_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000
+-#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000
+-#define mmDP0_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000
+-#define mmDP0_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000
+-#define mmDP0_DP_SEC_CNTL_DEFAULT 0x00000000
+-#define mmDP0_DP_SEC_CNTL1_DEFAULT 0x00000000
+-#define mmDP0_DP_SEC_FRAMING1_DEFAULT 0x00000000
+-#define mmDP0_DP_SEC_FRAMING2_DEFAULT 0x00000000
+-#define mmDP0_DP_SEC_FRAMING3_DEFAULT 0x00000200
+-#define mmDP0_DP_SEC_FRAMING4_DEFAULT 0x00000000
+-#define mmDP0_DP_SEC_AUD_N_DEFAULT 0x00008000
+-#define mmDP0_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000
+-#define mmDP0_DP_SEC_AUD_M_DEFAULT 0x00000000
+-#define mmDP0_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000
+-#define mmDP0_DP_SEC_TIMESTAMP_DEFAULT 0x00000000
+-#define mmDP0_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100
+-#define mmDP0_DP_MSE_RATE_CNTL_DEFAULT 0x00000000
+-#define mmDP0_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000
+-#define mmDP0_DP_MSE_SAT0_DEFAULT 0x00000000
+-#define mmDP0_DP_MSE_SAT1_DEFAULT 0x00000000
+-#define mmDP0_DP_MSE_SAT2_DEFAULT 0x00000000
+-#define mmDP0_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000
+-#define mmDP0_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff
+-#define mmDP0_DP_MSE_MISC_CNTL_DEFAULT 0x00000000
+-#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005
+-#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000
+-#define mmDP0_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000
+-#define mmDP0_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000
+-#define mmDP0_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dig1_dispdec
+-#define mmDIG1_DIG_FE_CNTL_DEFAULT 0x00000000
+-#define mmDIG1_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100
+-#define mmDIG1_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000
+-#define mmDIG1_DIG_CLOCK_PATTERN_DEFAULT 0x00000063
+-#define mmDIG1_DIG_TEST_PATTERN_DEFAULT 0x00000060
+-#define mmDIG1_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222
+-#define mmDIG1_DIG_FIFO_STATUS_DEFAULT 0x00000000
+-#define mmDIG1_HDMI_CONTROL_DEFAULT 0x00010001
+-#define mmDIG1_HDMI_STATUS_DEFAULT 0x00000000
+-#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010
+-#define mmDIG1_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000
+-#define mmDIG1_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000
+-#define mmDIG1_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000
+-#define mmDIG1_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000
+-#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000
+-#define mmDIG1_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000
+-#define mmDIG1_HDMI_GC_DEFAULT 0x00000004
+-#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000
+-#define mmDIG1_AFMT_ISRC1_0_DEFAULT 0x00000000
+-#define mmDIG1_AFMT_ISRC1_1_DEFAULT 0x00000000
+-#define mmDIG1_AFMT_ISRC1_2_DEFAULT 0x00000000
+-#define mmDIG1_AFMT_ISRC1_3_DEFAULT 0x00000000
+-#define mmDIG1_AFMT_ISRC1_4_DEFAULT 0x00000000
+-#define mmDIG1_AFMT_ISRC2_0_DEFAULT 0x00000000
+-#define mmDIG1_AFMT_ISRC2_1_DEFAULT 0x00000000
+-#define mmDIG1_AFMT_ISRC2_2_DEFAULT 0x00000000
+-#define mmDIG1_AFMT_ISRC2_3_DEFAULT 0x00000000
+-#define mmDIG1_AFMT_AVI_INFO0_DEFAULT 0x00000000
+-#define mmDIG1_AFMT_AVI_INFO1_DEFAULT 0x00000000
+-#define mmDIG1_AFMT_AVI_INFO2_DEFAULT 0x00000000
+-#define mmDIG1_AFMT_AVI_INFO3_DEFAULT 0x02000000
+-#define mmDIG1_AFMT_MPEG_INFO0_DEFAULT 0x00000000
+-#define mmDIG1_AFMT_MPEG_INFO1_DEFAULT 0x00000000
+-#define mmDIG1_AFMT_GENERIC_HDR_DEFAULT 0x00000000
+-#define mmDIG1_AFMT_GENERIC_0_DEFAULT 0x00000000
+-#define mmDIG1_AFMT_GENERIC_1_DEFAULT 0x00000000
+-#define mmDIG1_AFMT_GENERIC_2_DEFAULT 0x00000000
+-#define mmDIG1_AFMT_GENERIC_3_DEFAULT 0x00000000
+-#define mmDIG1_AFMT_GENERIC_4_DEFAULT 0x00000000
+-#define mmDIG1_AFMT_GENERIC_5_DEFAULT 0x00000000
+-#define mmDIG1_AFMT_GENERIC_6_DEFAULT 0x00000000
+-#define mmDIG1_AFMT_GENERIC_7_DEFAULT 0x00000000
+-#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000
+-#define mmDIG1_HDMI_ACR_32_0_DEFAULT 0x00000000
+-#define mmDIG1_HDMI_ACR_32_1_DEFAULT 0x00000000
+-#define mmDIG1_HDMI_ACR_44_0_DEFAULT 0x00000000
+-#define mmDIG1_HDMI_ACR_44_1_DEFAULT 0x00000000
+-#define mmDIG1_HDMI_ACR_48_0_DEFAULT 0x00000000
+-#define mmDIG1_HDMI_ACR_48_1_DEFAULT 0x00000000
+-#define mmDIG1_HDMI_ACR_STATUS_0_DEFAULT 0x00000000
+-#define mmDIG1_HDMI_ACR_STATUS_1_DEFAULT 0x00000000
+-#define mmDIG1_AFMT_AUDIO_INFO0_DEFAULT 0x00000170
+-#define mmDIG1_AFMT_AUDIO_INFO1_DEFAULT 0x00000000
+-#define mmDIG1_AFMT_60958_0_DEFAULT 0x00000000
+-#define mmDIG1_AFMT_60958_1_DEFAULT 0x00000000
+-#define mmDIG1_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000
+-#define mmDIG1_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000
+-#define mmDIG1_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000
+-#define mmDIG1_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000
+-#define mmDIG1_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000
+-#define mmDIG1_AFMT_60958_2_DEFAULT 0x00000000
+-#define mmDIG1_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000
+-#define mmDIG1_AFMT_STATUS_DEFAULT 0x00000000
+-#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800
+-#define mmDIG1_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000
+-#define mmDIG1_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000
+-#define mmDIG1_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000
+-#define mmDIG1_DIG_BE_CNTL_DEFAULT 0x00010000
+-#define mmDIG1_DIG_BE_EN_CNTL_DEFAULT 0x00000000
+-#define mmDIG1_TMDS_CNTL_DEFAULT 0x00000001
+-#define mmDIG1_TMDS_CONTROL_CHAR_DEFAULT 0x00000000
+-#define mmDIG1_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000
+-#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000
+-#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000
+-#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000
+-#define mmDIG1_TMDS_CTL_BITS_DEFAULT 0x00000000
+-#define mmDIG1_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001
+-#define mmDIG1_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000
+-#define mmDIG1_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000
+-#define mmDIG1_DIG_VERSION_DEFAULT 0x00000000
+-#define mmDIG1_DIG_LANE_ENABLE_DEFAULT 0x00000000
+-#define mmDIG1_AFMT_CNTL_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dp1_dispdec
+-#define mmDP1_DP_LINK_CNTL_DEFAULT 0x00000000
+-#define mmDP1_DP_PIXEL_FORMAT_DEFAULT 0x00000000
+-#define mmDP1_DP_MSA_COLORIMETRY_DEFAULT 0x00000000
+-#define mmDP1_DP_CONFIG_DEFAULT 0x00000000
+-#define mmDP1_DP_VID_STREAM_CNTL_DEFAULT 0x00000200
+-#define mmDP1_DP_STEER_FIFO_DEFAULT 0x00000000
+-#define mmDP1_DP_MSA_MISC_DEFAULT 0x00000000
+-#define mmDP1_DP_VID_TIMING_DEFAULT 0x00000000
+-#define mmDP1_DP_VID_N_DEFAULT 0x00002000
+-#define mmDP1_DP_VID_M_DEFAULT 0x00000000
+-#define mmDP1_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000
+-#define mmDP1_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000
+-#define mmDP1_DP_VID_MSA_VBID_DEFAULT 0x01000000
+-#define mmDP1_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000
+-#define mmDP1_DP_DPHY_CNTL_DEFAULT 0x00000000
+-#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000
+-#define mmDP1_DP_DPHY_SYM0_DEFAULT 0x00000000
+-#define mmDP1_DP_DPHY_SYM1_DEFAULT 0x00000000
+-#define mmDP1_DP_DPHY_SYM2_DEFAULT 0x00000000
+-#define mmDP1_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000
+-#define mmDP1_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00
+-#define mmDP1_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10
+-#define mmDP1_DP_DPHY_CRC_EN_DEFAULT 0x00000000
+-#define mmDP1_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000
+-#define mmDP1_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000
+-#define mmDP1_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000
+-#define mmDP1_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000
+-#define mmDP1_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000
+-#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000
+-#define mmDP1_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000
+-#define mmDP1_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000
+-#define mmDP1_DP_SEC_CNTL_DEFAULT 0x00000000
+-#define mmDP1_DP_SEC_CNTL1_DEFAULT 0x00000000
+-#define mmDP1_DP_SEC_FRAMING1_DEFAULT 0x00000000
+-#define mmDP1_DP_SEC_FRAMING2_DEFAULT 0x00000000
+-#define mmDP1_DP_SEC_FRAMING3_DEFAULT 0x00000200
+-#define mmDP1_DP_SEC_FRAMING4_DEFAULT 0x00000000
+-#define mmDP1_DP_SEC_AUD_N_DEFAULT 0x00008000
+-#define mmDP1_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000
+-#define mmDP1_DP_SEC_AUD_M_DEFAULT 0x00000000
+-#define mmDP1_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000
+-#define mmDP1_DP_SEC_TIMESTAMP_DEFAULT 0x00000000
+-#define mmDP1_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100
+-#define mmDP1_DP_MSE_RATE_CNTL_DEFAULT 0x00000000
+-#define mmDP1_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000
+-#define mmDP1_DP_MSE_SAT0_DEFAULT 0x00000000
+-#define mmDP1_DP_MSE_SAT1_DEFAULT 0x00000000
+-#define mmDP1_DP_MSE_SAT2_DEFAULT 0x00000000
+-#define mmDP1_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000
+-#define mmDP1_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff
+-#define mmDP1_DP_MSE_MISC_CNTL_DEFAULT 0x00000000
+-#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005
+-#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000
+-#define mmDP1_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000
+-#define mmDP1_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000
+-#define mmDP1_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dig2_dispdec
+-#define mmDIG2_DIG_FE_CNTL_DEFAULT 0x00000000
+-#define mmDIG2_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100
+-#define mmDIG2_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000
+-#define mmDIG2_DIG_CLOCK_PATTERN_DEFAULT 0x00000063
+-#define mmDIG2_DIG_TEST_PATTERN_DEFAULT 0x00000060
+-#define mmDIG2_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222
+-#define mmDIG2_DIG_FIFO_STATUS_DEFAULT 0x00000000
+-#define mmDIG2_HDMI_CONTROL_DEFAULT 0x00010001
+-#define mmDIG2_HDMI_STATUS_DEFAULT 0x00000000
+-#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010
+-#define mmDIG2_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000
+-#define mmDIG2_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000
+-#define mmDIG2_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000
+-#define mmDIG2_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000
+-#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000
+-#define mmDIG2_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000
+-#define mmDIG2_HDMI_GC_DEFAULT 0x00000004
+-#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000
+-#define mmDIG2_AFMT_ISRC1_0_DEFAULT 0x00000000
+-#define mmDIG2_AFMT_ISRC1_1_DEFAULT 0x00000000
+-#define mmDIG2_AFMT_ISRC1_2_DEFAULT 0x00000000
+-#define mmDIG2_AFMT_ISRC1_3_DEFAULT 0x00000000
+-#define mmDIG2_AFMT_ISRC1_4_DEFAULT 0x00000000
+-#define mmDIG2_AFMT_ISRC2_0_DEFAULT 0x00000000
+-#define mmDIG2_AFMT_ISRC2_1_DEFAULT 0x00000000
+-#define mmDIG2_AFMT_ISRC2_2_DEFAULT 0x00000000
+-#define mmDIG2_AFMT_ISRC2_3_DEFAULT 0x00000000
+-#define mmDIG2_AFMT_AVI_INFO0_DEFAULT 0x00000000
+-#define mmDIG2_AFMT_AVI_INFO1_DEFAULT 0x00000000
+-#define mmDIG2_AFMT_AVI_INFO2_DEFAULT 0x00000000
+-#define mmDIG2_AFMT_AVI_INFO3_DEFAULT 0x02000000
+-#define mmDIG2_AFMT_MPEG_INFO0_DEFAULT 0x00000000
+-#define mmDIG2_AFMT_MPEG_INFO1_DEFAULT 0x00000000
+-#define mmDIG2_AFMT_GENERIC_HDR_DEFAULT 0x00000000
+-#define mmDIG2_AFMT_GENERIC_0_DEFAULT 0x00000000
+-#define mmDIG2_AFMT_GENERIC_1_DEFAULT 0x00000000
+-#define mmDIG2_AFMT_GENERIC_2_DEFAULT 0x00000000
+-#define mmDIG2_AFMT_GENERIC_3_DEFAULT 0x00000000
+-#define mmDIG2_AFMT_GENERIC_4_DEFAULT 0x00000000
+-#define mmDIG2_AFMT_GENERIC_5_DEFAULT 0x00000000
+-#define mmDIG2_AFMT_GENERIC_6_DEFAULT 0x00000000
+-#define mmDIG2_AFMT_GENERIC_7_DEFAULT 0x00000000
+-#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000
+-#define mmDIG2_HDMI_ACR_32_0_DEFAULT 0x00000000
+-#define mmDIG2_HDMI_ACR_32_1_DEFAULT 0x00000000
+-#define mmDIG2_HDMI_ACR_44_0_DEFAULT 0x00000000
+-#define mmDIG2_HDMI_ACR_44_1_DEFAULT 0x00000000
+-#define mmDIG2_HDMI_ACR_48_0_DEFAULT 0x00000000
+-#define mmDIG2_HDMI_ACR_48_1_DEFAULT 0x00000000
+-#define mmDIG2_HDMI_ACR_STATUS_0_DEFAULT 0x00000000
+-#define mmDIG2_HDMI_ACR_STATUS_1_DEFAULT 0x00000000
+-#define mmDIG2_AFMT_AUDIO_INFO0_DEFAULT 0x00000170
+-#define mmDIG2_AFMT_AUDIO_INFO1_DEFAULT 0x00000000
+-#define mmDIG2_AFMT_60958_0_DEFAULT 0x00000000
+-#define mmDIG2_AFMT_60958_1_DEFAULT 0x00000000
+-#define mmDIG2_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000
+-#define mmDIG2_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000
+-#define mmDIG2_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000
+-#define mmDIG2_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000
+-#define mmDIG2_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000
+-#define mmDIG2_AFMT_60958_2_DEFAULT 0x00000000
+-#define mmDIG2_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000
+-#define mmDIG2_AFMT_STATUS_DEFAULT 0x00000000
+-#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800
+-#define mmDIG2_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000
+-#define mmDIG2_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000
+-#define mmDIG2_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000
+-#define mmDIG2_DIG_BE_CNTL_DEFAULT 0x00010000
+-#define mmDIG2_DIG_BE_EN_CNTL_DEFAULT 0x00000000
+-#define mmDIG2_TMDS_CNTL_DEFAULT 0x00000001
+-#define mmDIG2_TMDS_CONTROL_CHAR_DEFAULT 0x00000000
+-#define mmDIG2_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000
+-#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000
+-#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000
+-#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000
+-#define mmDIG2_TMDS_CTL_BITS_DEFAULT 0x00000000
+-#define mmDIG2_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001
+-#define mmDIG2_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000
+-#define mmDIG2_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000
+-#define mmDIG2_DIG_VERSION_DEFAULT 0x00000000
+-#define mmDIG2_DIG_LANE_ENABLE_DEFAULT 0x00000000
+-#define mmDIG2_AFMT_CNTL_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dp2_dispdec
+-#define mmDP2_DP_LINK_CNTL_DEFAULT 0x00000000
+-#define mmDP2_DP_PIXEL_FORMAT_DEFAULT 0x00000000
+-#define mmDP2_DP_MSA_COLORIMETRY_DEFAULT 0x00000000
+-#define mmDP2_DP_CONFIG_DEFAULT 0x00000000
+-#define mmDP2_DP_VID_STREAM_CNTL_DEFAULT 0x00000200
+-#define mmDP2_DP_STEER_FIFO_DEFAULT 0x00000000
+-#define mmDP2_DP_MSA_MISC_DEFAULT 0x00000000
+-#define mmDP2_DP_VID_TIMING_DEFAULT 0x00000000
+-#define mmDP2_DP_VID_N_DEFAULT 0x00002000
+-#define mmDP2_DP_VID_M_DEFAULT 0x00000000
+-#define mmDP2_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000
+-#define mmDP2_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000
+-#define mmDP2_DP_VID_MSA_VBID_DEFAULT 0x01000000
+-#define mmDP2_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000
+-#define mmDP2_DP_DPHY_CNTL_DEFAULT 0x00000000
+-#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000
+-#define mmDP2_DP_DPHY_SYM0_DEFAULT 0x00000000
+-#define mmDP2_DP_DPHY_SYM1_DEFAULT 0x00000000
+-#define mmDP2_DP_DPHY_SYM2_DEFAULT 0x00000000
+-#define mmDP2_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000
+-#define mmDP2_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00
+-#define mmDP2_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10
+-#define mmDP2_DP_DPHY_CRC_EN_DEFAULT 0x00000000
+-#define mmDP2_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000
+-#define mmDP2_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000
+-#define mmDP2_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000
+-#define mmDP2_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000
+-#define mmDP2_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000
+-#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000
+-#define mmDP2_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000
+-#define mmDP2_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000
+-#define mmDP2_DP_SEC_CNTL_DEFAULT 0x00000000
+-#define mmDP2_DP_SEC_CNTL1_DEFAULT 0x00000000
+-#define mmDP2_DP_SEC_FRAMING1_DEFAULT 0x00000000
+-#define mmDP2_DP_SEC_FRAMING2_DEFAULT 0x00000000
+-#define mmDP2_DP_SEC_FRAMING3_DEFAULT 0x00000200
+-#define mmDP2_DP_SEC_FRAMING4_DEFAULT 0x00000000
+-#define mmDP2_DP_SEC_AUD_N_DEFAULT 0x00008000
+-#define mmDP2_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000
+-#define mmDP2_DP_SEC_AUD_M_DEFAULT 0x00000000
+-#define mmDP2_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000
+-#define mmDP2_DP_SEC_TIMESTAMP_DEFAULT 0x00000000
+-#define mmDP2_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100
+-#define mmDP2_DP_MSE_RATE_CNTL_DEFAULT 0x00000000
+-#define mmDP2_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000
+-#define mmDP2_DP_MSE_SAT0_DEFAULT 0x00000000
+-#define mmDP2_DP_MSE_SAT1_DEFAULT 0x00000000
+-#define mmDP2_DP_MSE_SAT2_DEFAULT 0x00000000
+-#define mmDP2_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000
+-#define mmDP2_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff
+-#define mmDP2_DP_MSE_MISC_CNTL_DEFAULT 0x00000000
+-#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005
+-#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000
+-#define mmDP2_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000
+-#define mmDP2_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000
+-#define mmDP2_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dig3_dispdec
+-#define mmDIG3_DIG_FE_CNTL_DEFAULT 0x00000000
+-#define mmDIG3_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100
+-#define mmDIG3_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000
+-#define mmDIG3_DIG_CLOCK_PATTERN_DEFAULT 0x00000063
+-#define mmDIG3_DIG_TEST_PATTERN_DEFAULT 0x00000060
+-#define mmDIG3_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222
+-#define mmDIG3_DIG_FIFO_STATUS_DEFAULT 0x00000000
+-#define mmDIG3_HDMI_CONTROL_DEFAULT 0x00010001
+-#define mmDIG3_HDMI_STATUS_DEFAULT 0x00000000
+-#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010
+-#define mmDIG3_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000
+-#define mmDIG3_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000
+-#define mmDIG3_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000
+-#define mmDIG3_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000
+-#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000
+-#define mmDIG3_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000
+-#define mmDIG3_HDMI_GC_DEFAULT 0x00000004
+-#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000
+-#define mmDIG3_AFMT_ISRC1_0_DEFAULT 0x00000000
+-#define mmDIG3_AFMT_ISRC1_1_DEFAULT 0x00000000
+-#define mmDIG3_AFMT_ISRC1_2_DEFAULT 0x00000000
+-#define mmDIG3_AFMT_ISRC1_3_DEFAULT 0x00000000
+-#define mmDIG3_AFMT_ISRC1_4_DEFAULT 0x00000000
+-#define mmDIG3_AFMT_ISRC2_0_DEFAULT 0x00000000
+-#define mmDIG3_AFMT_ISRC2_1_DEFAULT 0x00000000
+-#define mmDIG3_AFMT_ISRC2_2_DEFAULT 0x00000000
+-#define mmDIG3_AFMT_ISRC2_3_DEFAULT 0x00000000
+-#define mmDIG3_AFMT_AVI_INFO0_DEFAULT 0x00000000
+-#define mmDIG3_AFMT_AVI_INFO1_DEFAULT 0x00000000
+-#define mmDIG3_AFMT_AVI_INFO2_DEFAULT 0x00000000
+-#define mmDIG3_AFMT_AVI_INFO3_DEFAULT 0x02000000
+-#define mmDIG3_AFMT_MPEG_INFO0_DEFAULT 0x00000000
+-#define mmDIG3_AFMT_MPEG_INFO1_DEFAULT 0x00000000
+-#define mmDIG3_AFMT_GENERIC_HDR_DEFAULT 0x00000000
+-#define mmDIG3_AFMT_GENERIC_0_DEFAULT 0x00000000
+-#define mmDIG3_AFMT_GENERIC_1_DEFAULT 0x00000000
+-#define mmDIG3_AFMT_GENERIC_2_DEFAULT 0x00000000
+-#define mmDIG3_AFMT_GENERIC_3_DEFAULT 0x00000000
+-#define mmDIG3_AFMT_GENERIC_4_DEFAULT 0x00000000
+-#define mmDIG3_AFMT_GENERIC_5_DEFAULT 0x00000000
+-#define mmDIG3_AFMT_GENERIC_6_DEFAULT 0x00000000
+-#define mmDIG3_AFMT_GENERIC_7_DEFAULT 0x00000000
+-#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000
+-#define mmDIG3_HDMI_ACR_32_0_DEFAULT 0x00000000
+-#define mmDIG3_HDMI_ACR_32_1_DEFAULT 0x00000000
+-#define mmDIG3_HDMI_ACR_44_0_DEFAULT 0x00000000
+-#define mmDIG3_HDMI_ACR_44_1_DEFAULT 0x00000000
+-#define mmDIG3_HDMI_ACR_48_0_DEFAULT 0x00000000
+-#define mmDIG3_HDMI_ACR_48_1_DEFAULT 0x00000000
+-#define mmDIG3_HDMI_ACR_STATUS_0_DEFAULT 0x00000000
+-#define mmDIG3_HDMI_ACR_STATUS_1_DEFAULT 0x00000000
+-#define mmDIG3_AFMT_AUDIO_INFO0_DEFAULT 0x00000170
+-#define mmDIG3_AFMT_AUDIO_INFO1_DEFAULT 0x00000000
+-#define mmDIG3_AFMT_60958_0_DEFAULT 0x00000000
+-#define mmDIG3_AFMT_60958_1_DEFAULT 0x00000000
+-#define mmDIG3_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000
+-#define mmDIG3_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000
+-#define mmDIG3_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000
+-#define mmDIG3_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000
+-#define mmDIG3_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000
+-#define mmDIG3_AFMT_60958_2_DEFAULT 0x00000000
+-#define mmDIG3_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000
+-#define mmDIG3_AFMT_STATUS_DEFAULT 0x00000000
+-#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800
+-#define mmDIG3_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000
+-#define mmDIG3_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000
+-#define mmDIG3_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000
+-#define mmDIG3_DIG_BE_CNTL_DEFAULT 0x00010000
+-#define mmDIG3_DIG_BE_EN_CNTL_DEFAULT 0x00000000
+-#define mmDIG3_TMDS_CNTL_DEFAULT 0x00000001
+-#define mmDIG3_TMDS_CONTROL_CHAR_DEFAULT 0x00000000
+-#define mmDIG3_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000
+-#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000
+-#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000
+-#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000
+-#define mmDIG3_TMDS_CTL_BITS_DEFAULT 0x00000000
+-#define mmDIG3_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001
+-#define mmDIG3_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000
+-#define mmDIG3_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000
+-#define mmDIG3_DIG_VERSION_DEFAULT 0x00000000
+-#define mmDIG3_DIG_LANE_ENABLE_DEFAULT 0x00000000
+-#define mmDIG3_AFMT_CNTL_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dp3_dispdec
+-#define mmDP3_DP_LINK_CNTL_DEFAULT 0x00000000
+-#define mmDP3_DP_PIXEL_FORMAT_DEFAULT 0x00000000
+-#define mmDP3_DP_MSA_COLORIMETRY_DEFAULT 0x00000000
+-#define mmDP3_DP_CONFIG_DEFAULT 0x00000000
+-#define mmDP3_DP_VID_STREAM_CNTL_DEFAULT 0x00000200
+-#define mmDP3_DP_STEER_FIFO_DEFAULT 0x00000000
+-#define mmDP3_DP_MSA_MISC_DEFAULT 0x00000000
+-#define mmDP3_DP_VID_TIMING_DEFAULT 0x00000000
+-#define mmDP3_DP_VID_N_DEFAULT 0x00002000
+-#define mmDP3_DP_VID_M_DEFAULT 0x00000000
+-#define mmDP3_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000
+-#define mmDP3_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000
+-#define mmDP3_DP_VID_MSA_VBID_DEFAULT 0x01000000
+-#define mmDP3_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000
+-#define mmDP3_DP_DPHY_CNTL_DEFAULT 0x00000000
+-#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000
+-#define mmDP3_DP_DPHY_SYM0_DEFAULT 0x00000000
+-#define mmDP3_DP_DPHY_SYM1_DEFAULT 0x00000000
+-#define mmDP3_DP_DPHY_SYM2_DEFAULT 0x00000000
+-#define mmDP3_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000
+-#define mmDP3_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00
+-#define mmDP3_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10
+-#define mmDP3_DP_DPHY_CRC_EN_DEFAULT 0x00000000
+-#define mmDP3_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000
+-#define mmDP3_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000
+-#define mmDP3_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000
+-#define mmDP3_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000
+-#define mmDP3_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000
+-#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000
+-#define mmDP3_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000
+-#define mmDP3_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000
+-#define mmDP3_DP_SEC_CNTL_DEFAULT 0x00000000
+-#define mmDP3_DP_SEC_CNTL1_DEFAULT 0x00000000
+-#define mmDP3_DP_SEC_FRAMING1_DEFAULT 0x00000000
+-#define mmDP3_DP_SEC_FRAMING2_DEFAULT 0x00000000
+-#define mmDP3_DP_SEC_FRAMING3_DEFAULT 0x00000200
+-#define mmDP3_DP_SEC_FRAMING4_DEFAULT 0x00000000
+-#define mmDP3_DP_SEC_AUD_N_DEFAULT 0x00008000
+-#define mmDP3_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000
+-#define mmDP3_DP_SEC_AUD_M_DEFAULT 0x00000000
+-#define mmDP3_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000
+-#define mmDP3_DP_SEC_TIMESTAMP_DEFAULT 0x00000000
+-#define mmDP3_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100
+-#define mmDP3_DP_MSE_RATE_CNTL_DEFAULT 0x00000000
+-#define mmDP3_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000
+-#define mmDP3_DP_MSE_SAT0_DEFAULT 0x00000000
+-#define mmDP3_DP_MSE_SAT1_DEFAULT 0x00000000
+-#define mmDP3_DP_MSE_SAT2_DEFAULT 0x00000000
+-#define mmDP3_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000
+-#define mmDP3_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff
+-#define mmDP3_DP_MSE_MISC_CNTL_DEFAULT 0x00000000
+-#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005
+-#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000
+-#define mmDP3_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000
+-#define mmDP3_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000
+-#define mmDP3_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dig4_dispdec
+-#define mmDIG4_DIG_FE_CNTL_DEFAULT 0x00000000
+-#define mmDIG4_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100
+-#define mmDIG4_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000
+-#define mmDIG4_DIG_CLOCK_PATTERN_DEFAULT 0x00000063
+-#define mmDIG4_DIG_TEST_PATTERN_DEFAULT 0x00000060
+-#define mmDIG4_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222
+-#define mmDIG4_DIG_FIFO_STATUS_DEFAULT 0x00000000
+-#define mmDIG4_HDMI_CONTROL_DEFAULT 0x00010001
+-#define mmDIG4_HDMI_STATUS_DEFAULT 0x00000000
+-#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010
+-#define mmDIG4_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000
+-#define mmDIG4_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000
+-#define mmDIG4_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000
+-#define mmDIG4_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000
+-#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000
+-#define mmDIG4_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000
+-#define mmDIG4_HDMI_GC_DEFAULT 0x00000004
+-#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000
+-#define mmDIG4_AFMT_ISRC1_0_DEFAULT 0x00000000
+-#define mmDIG4_AFMT_ISRC1_1_DEFAULT 0x00000000
+-#define mmDIG4_AFMT_ISRC1_2_DEFAULT 0x00000000
+-#define mmDIG4_AFMT_ISRC1_3_DEFAULT 0x00000000
+-#define mmDIG4_AFMT_ISRC1_4_DEFAULT 0x00000000
+-#define mmDIG4_AFMT_ISRC2_0_DEFAULT 0x00000000
+-#define mmDIG4_AFMT_ISRC2_1_DEFAULT 0x00000000
+-#define mmDIG4_AFMT_ISRC2_2_DEFAULT 0x00000000
+-#define mmDIG4_AFMT_ISRC2_3_DEFAULT 0x00000000
+-#define mmDIG4_AFMT_AVI_INFO0_DEFAULT 0x00000000
+-#define mmDIG4_AFMT_AVI_INFO1_DEFAULT 0x00000000
+-#define mmDIG4_AFMT_AVI_INFO2_DEFAULT 0x00000000
+-#define mmDIG4_AFMT_AVI_INFO3_DEFAULT 0x02000000
+-#define mmDIG4_AFMT_MPEG_INFO0_DEFAULT 0x00000000
+-#define mmDIG4_AFMT_MPEG_INFO1_DEFAULT 0x00000000
+-#define mmDIG4_AFMT_GENERIC_HDR_DEFAULT 0x00000000
+-#define mmDIG4_AFMT_GENERIC_0_DEFAULT 0x00000000
+-#define mmDIG4_AFMT_GENERIC_1_DEFAULT 0x00000000
+-#define mmDIG4_AFMT_GENERIC_2_DEFAULT 0x00000000
+-#define mmDIG4_AFMT_GENERIC_3_DEFAULT 0x00000000
+-#define mmDIG4_AFMT_GENERIC_4_DEFAULT 0x00000000
+-#define mmDIG4_AFMT_GENERIC_5_DEFAULT 0x00000000
+-#define mmDIG4_AFMT_GENERIC_6_DEFAULT 0x00000000
+-#define mmDIG4_AFMT_GENERIC_7_DEFAULT 0x00000000
+-#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000
+-#define mmDIG4_HDMI_ACR_32_0_DEFAULT 0x00000000
+-#define mmDIG4_HDMI_ACR_32_1_DEFAULT 0x00000000
+-#define mmDIG4_HDMI_ACR_44_0_DEFAULT 0x00000000
+-#define mmDIG4_HDMI_ACR_44_1_DEFAULT 0x00000000
+-#define mmDIG4_HDMI_ACR_48_0_DEFAULT 0x00000000
+-#define mmDIG4_HDMI_ACR_48_1_DEFAULT 0x00000000
+-#define mmDIG4_HDMI_ACR_STATUS_0_DEFAULT 0x00000000
+-#define mmDIG4_HDMI_ACR_STATUS_1_DEFAULT 0x00000000
+-#define mmDIG4_AFMT_AUDIO_INFO0_DEFAULT 0x00000170
+-#define mmDIG4_AFMT_AUDIO_INFO1_DEFAULT 0x00000000
+-#define mmDIG4_AFMT_60958_0_DEFAULT 0x00000000
+-#define mmDIG4_AFMT_60958_1_DEFAULT 0x00000000
+-#define mmDIG4_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000
+-#define mmDIG4_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000
+-#define mmDIG4_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000
+-#define mmDIG4_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000
+-#define mmDIG4_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000
+-#define mmDIG4_AFMT_60958_2_DEFAULT 0x00000000
+-#define mmDIG4_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000
+-#define mmDIG4_AFMT_STATUS_DEFAULT 0x00000000
+-#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800
+-#define mmDIG4_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000
+-#define mmDIG4_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000
+-#define mmDIG4_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000
+-#define mmDIG4_DIG_BE_CNTL_DEFAULT 0x00010000
+-#define mmDIG4_DIG_BE_EN_CNTL_DEFAULT 0x00000000
+-#define mmDIG4_TMDS_CNTL_DEFAULT 0x00000001
+-#define mmDIG4_TMDS_CONTROL_CHAR_DEFAULT 0x00000000
+-#define mmDIG4_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000
+-#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000
+-#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000
+-#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000
+-#define mmDIG4_TMDS_CTL_BITS_DEFAULT 0x00000000
+-#define mmDIG4_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001
+-#define mmDIG4_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000
+-#define mmDIG4_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000
+-#define mmDIG4_DIG_VERSION_DEFAULT 0x00000000
+-#define mmDIG4_DIG_LANE_ENABLE_DEFAULT 0x00000000
+-#define mmDIG4_AFMT_CNTL_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dp4_dispdec
+-#define mmDP4_DP_LINK_CNTL_DEFAULT 0x00000000
+-#define mmDP4_DP_PIXEL_FORMAT_DEFAULT 0x00000000
+-#define mmDP4_DP_MSA_COLORIMETRY_DEFAULT 0x00000000
+-#define mmDP4_DP_CONFIG_DEFAULT 0x00000000
+-#define mmDP4_DP_VID_STREAM_CNTL_DEFAULT 0x00000200
+-#define mmDP4_DP_STEER_FIFO_DEFAULT 0x00000000
+-#define mmDP4_DP_MSA_MISC_DEFAULT 0x00000000
+-#define mmDP4_DP_VID_TIMING_DEFAULT 0x00000000
+-#define mmDP4_DP_VID_N_DEFAULT 0x00002000
+-#define mmDP4_DP_VID_M_DEFAULT 0x00000000
+-#define mmDP4_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000
+-#define mmDP4_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000
+-#define mmDP4_DP_VID_MSA_VBID_DEFAULT 0x01000000
+-#define mmDP4_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000
+-#define mmDP4_DP_DPHY_CNTL_DEFAULT 0x00000000
+-#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000
+-#define mmDP4_DP_DPHY_SYM0_DEFAULT 0x00000000
+-#define mmDP4_DP_DPHY_SYM1_DEFAULT 0x00000000
+-#define mmDP4_DP_DPHY_SYM2_DEFAULT 0x00000000
+-#define mmDP4_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000
+-#define mmDP4_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00
+-#define mmDP4_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10
+-#define mmDP4_DP_DPHY_CRC_EN_DEFAULT 0x00000000
+-#define mmDP4_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000
+-#define mmDP4_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000
+-#define mmDP4_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000
+-#define mmDP4_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000
+-#define mmDP4_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000
+-#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000
+-#define mmDP4_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000
+-#define mmDP4_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000
+-#define mmDP4_DP_SEC_CNTL_DEFAULT 0x00000000
+-#define mmDP4_DP_SEC_CNTL1_DEFAULT 0x00000000
+-#define mmDP4_DP_SEC_FRAMING1_DEFAULT 0x00000000
+-#define mmDP4_DP_SEC_FRAMING2_DEFAULT 0x00000000
+-#define mmDP4_DP_SEC_FRAMING3_DEFAULT 0x00000200
+-#define mmDP4_DP_SEC_FRAMING4_DEFAULT 0x00000000
+-#define mmDP4_DP_SEC_AUD_N_DEFAULT 0x00008000
+-#define mmDP4_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000
+-#define mmDP4_DP_SEC_AUD_M_DEFAULT 0x00000000
+-#define mmDP4_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000
+-#define mmDP4_DP_SEC_TIMESTAMP_DEFAULT 0x00000000
+-#define mmDP4_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100
+-#define mmDP4_DP_MSE_RATE_CNTL_DEFAULT 0x00000000
+-#define mmDP4_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000
+-#define mmDP4_DP_MSE_SAT0_DEFAULT 0x00000000
+-#define mmDP4_DP_MSE_SAT1_DEFAULT 0x00000000
+-#define mmDP4_DP_MSE_SAT2_DEFAULT 0x00000000
+-#define mmDP4_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000
+-#define mmDP4_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff
+-#define mmDP4_DP_MSE_MISC_CNTL_DEFAULT 0x00000000
+-#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005
+-#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000
+-#define mmDP4_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000
+-#define mmDP4_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000
+-#define mmDP4_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dig5_dispdec
+-#define mmDIG5_DIG_FE_CNTL_DEFAULT 0x00000000
+-#define mmDIG5_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100
+-#define mmDIG5_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000
+-#define mmDIG5_DIG_CLOCK_PATTERN_DEFAULT 0x00000063
+-#define mmDIG5_DIG_TEST_PATTERN_DEFAULT 0x00000060
+-#define mmDIG5_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222
+-#define mmDIG5_DIG_FIFO_STATUS_DEFAULT 0x00000000
+-#define mmDIG5_HDMI_CONTROL_DEFAULT 0x00010001
+-#define mmDIG5_HDMI_STATUS_DEFAULT 0x00000000
+-#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010
+-#define mmDIG5_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000
+-#define mmDIG5_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000
+-#define mmDIG5_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000
+-#define mmDIG5_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000
+-#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000
+-#define mmDIG5_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000
+-#define mmDIG5_HDMI_GC_DEFAULT 0x00000004
+-#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000
+-#define mmDIG5_AFMT_ISRC1_0_DEFAULT 0x00000000
+-#define mmDIG5_AFMT_ISRC1_1_DEFAULT 0x00000000
+-#define mmDIG5_AFMT_ISRC1_2_DEFAULT 0x00000000
+-#define mmDIG5_AFMT_ISRC1_3_DEFAULT 0x00000000
+-#define mmDIG5_AFMT_ISRC1_4_DEFAULT 0x00000000
+-#define mmDIG5_AFMT_ISRC2_0_DEFAULT 0x00000000
+-#define mmDIG5_AFMT_ISRC2_1_DEFAULT 0x00000000
+-#define mmDIG5_AFMT_ISRC2_2_DEFAULT 0x00000000
+-#define mmDIG5_AFMT_ISRC2_3_DEFAULT 0x00000000
+-#define mmDIG5_AFMT_AVI_INFO0_DEFAULT 0x00000000
+-#define mmDIG5_AFMT_AVI_INFO1_DEFAULT 0x00000000
+-#define mmDIG5_AFMT_AVI_INFO2_DEFAULT 0x00000000
+-#define mmDIG5_AFMT_AVI_INFO3_DEFAULT 0x02000000
+-#define mmDIG5_AFMT_MPEG_INFO0_DEFAULT 0x00000000
+-#define mmDIG5_AFMT_MPEG_INFO1_DEFAULT 0x00000000
+-#define mmDIG5_AFMT_GENERIC_HDR_DEFAULT 0x00000000
+-#define mmDIG5_AFMT_GENERIC_0_DEFAULT 0x00000000
+-#define mmDIG5_AFMT_GENERIC_1_DEFAULT 0x00000000
+-#define mmDIG5_AFMT_GENERIC_2_DEFAULT 0x00000000
+-#define mmDIG5_AFMT_GENERIC_3_DEFAULT 0x00000000
+-#define mmDIG5_AFMT_GENERIC_4_DEFAULT 0x00000000
+-#define mmDIG5_AFMT_GENERIC_5_DEFAULT 0x00000000
+-#define mmDIG5_AFMT_GENERIC_6_DEFAULT 0x00000000
+-#define mmDIG5_AFMT_GENERIC_7_DEFAULT 0x00000000
+-#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000
+-#define mmDIG5_HDMI_ACR_32_0_DEFAULT 0x00000000
+-#define mmDIG5_HDMI_ACR_32_1_DEFAULT 0x00000000
+-#define mmDIG5_HDMI_ACR_44_0_DEFAULT 0x00000000
+-#define mmDIG5_HDMI_ACR_44_1_DEFAULT 0x00000000
+-#define mmDIG5_HDMI_ACR_48_0_DEFAULT 0x00000000
+-#define mmDIG5_HDMI_ACR_48_1_DEFAULT 0x00000000
+-#define mmDIG5_HDMI_ACR_STATUS_0_DEFAULT 0x00000000
+-#define mmDIG5_HDMI_ACR_STATUS_1_DEFAULT 0x00000000
+-#define mmDIG5_AFMT_AUDIO_INFO0_DEFAULT 0x00000170
+-#define mmDIG5_AFMT_AUDIO_INFO1_DEFAULT 0x00000000
+-#define mmDIG5_AFMT_60958_0_DEFAULT 0x00000000
+-#define mmDIG5_AFMT_60958_1_DEFAULT 0x00000000
+-#define mmDIG5_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000
+-#define mmDIG5_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000
+-#define mmDIG5_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000
+-#define mmDIG5_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000
+-#define mmDIG5_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000
+-#define mmDIG5_AFMT_60958_2_DEFAULT 0x00000000
+-#define mmDIG5_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000
+-#define mmDIG5_AFMT_STATUS_DEFAULT 0x00000000
+-#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800
+-#define mmDIG5_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000
+-#define mmDIG5_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000
+-#define mmDIG5_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000
+-#define mmDIG5_DIG_BE_CNTL_DEFAULT 0x00010000
+-#define mmDIG5_DIG_BE_EN_CNTL_DEFAULT 0x00000000
+-#define mmDIG5_TMDS_CNTL_DEFAULT 0x00000001
+-#define mmDIG5_TMDS_CONTROL_CHAR_DEFAULT 0x00000000
+-#define mmDIG5_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000
+-#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000
+-#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000
+-#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000
+-#define mmDIG5_TMDS_CTL_BITS_DEFAULT 0x00000000
+-#define mmDIG5_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001
+-#define mmDIG5_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000
+-#define mmDIG5_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000
+-#define mmDIG5_DIG_VERSION_DEFAULT 0x00000000
+-#define mmDIG5_DIG_LANE_ENABLE_DEFAULT 0x00000000
+-#define mmDIG5_AFMT_CNTL_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dp5_dispdec
+-#define mmDP5_DP_LINK_CNTL_DEFAULT 0x00000000
+-#define mmDP5_DP_PIXEL_FORMAT_DEFAULT 0x00000000
+-#define mmDP5_DP_MSA_COLORIMETRY_DEFAULT 0x00000000
+-#define mmDP5_DP_CONFIG_DEFAULT 0x00000000
+-#define mmDP5_DP_VID_STREAM_CNTL_DEFAULT 0x00000200
+-#define mmDP5_DP_STEER_FIFO_DEFAULT 0x00000000
+-#define mmDP5_DP_MSA_MISC_DEFAULT 0x00000000
+-#define mmDP5_DP_VID_TIMING_DEFAULT 0x00000000
+-#define mmDP5_DP_VID_N_DEFAULT 0x00002000
+-#define mmDP5_DP_VID_M_DEFAULT 0x00000000
+-#define mmDP5_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000
+-#define mmDP5_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000
+-#define mmDP5_DP_VID_MSA_VBID_DEFAULT 0x01000000
+-#define mmDP5_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000
+-#define mmDP5_DP_DPHY_CNTL_DEFAULT 0x00000000
+-#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000
+-#define mmDP5_DP_DPHY_SYM0_DEFAULT 0x00000000
+-#define mmDP5_DP_DPHY_SYM1_DEFAULT 0x00000000
+-#define mmDP5_DP_DPHY_SYM2_DEFAULT 0x00000000
+-#define mmDP5_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000
+-#define mmDP5_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00
+-#define mmDP5_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10
+-#define mmDP5_DP_DPHY_CRC_EN_DEFAULT 0x00000000
+-#define mmDP5_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000
+-#define mmDP5_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000
+-#define mmDP5_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000
+-#define mmDP5_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000
+-#define mmDP5_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000
+-#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000
+-#define mmDP5_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000
+-#define mmDP5_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000
+-#define mmDP5_DP_SEC_CNTL_DEFAULT 0x00000000
+-#define mmDP5_DP_SEC_CNTL1_DEFAULT 0x00000000
+-#define mmDP5_DP_SEC_FRAMING1_DEFAULT 0x00000000
+-#define mmDP5_DP_SEC_FRAMING2_DEFAULT 0x00000000
+-#define mmDP5_DP_SEC_FRAMING3_DEFAULT 0x00000200
+-#define mmDP5_DP_SEC_FRAMING4_DEFAULT 0x00000000
+-#define mmDP5_DP_SEC_AUD_N_DEFAULT 0x00008000
+-#define mmDP5_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000
+-#define mmDP5_DP_SEC_AUD_M_DEFAULT 0x00000000
+-#define mmDP5_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000
+-#define mmDP5_DP_SEC_TIMESTAMP_DEFAULT 0x00000000
+-#define mmDP5_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100
+-#define mmDP5_DP_MSE_RATE_CNTL_DEFAULT 0x00000000
+-#define mmDP5_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000
+-#define mmDP5_DP_MSE_SAT0_DEFAULT 0x00000000
+-#define mmDP5_DP_MSE_SAT1_DEFAULT 0x00000000
+-#define mmDP5_DP_MSE_SAT2_DEFAULT 0x00000000
+-#define mmDP5_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000
+-#define mmDP5_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff
+-#define mmDP5_DP_MSE_MISC_CNTL_DEFAULT 0x00000000
+-#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005
+-#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000
+-#define mmDP5_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000
+-#define mmDP5_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000
+-#define mmDP5_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dig6_dispdec
+-#define mmDIG6_DIG_FE_CNTL_DEFAULT 0x00000000
+-#define mmDIG6_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100
+-#define mmDIG6_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000
+-#define mmDIG6_DIG_CLOCK_PATTERN_DEFAULT 0x00000063
+-#define mmDIG6_DIG_TEST_PATTERN_DEFAULT 0x00000060
+-#define mmDIG6_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222
+-#define mmDIG6_DIG_FIFO_STATUS_DEFAULT 0x00000000
+-#define mmDIG6_HDMI_CONTROL_DEFAULT 0x00010001
+-#define mmDIG6_HDMI_STATUS_DEFAULT 0x00000000
+-#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010
+-#define mmDIG6_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000
+-#define mmDIG6_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000
+-#define mmDIG6_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000
+-#define mmDIG6_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000
+-#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000
+-#define mmDIG6_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000
+-#define mmDIG6_HDMI_GC_DEFAULT 0x00000004
+-#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000
+-#define mmDIG6_AFMT_ISRC1_0_DEFAULT 0x00000000
+-#define mmDIG6_AFMT_ISRC1_1_DEFAULT 0x00000000
+-#define mmDIG6_AFMT_ISRC1_2_DEFAULT 0x00000000
+-#define mmDIG6_AFMT_ISRC1_3_DEFAULT 0x00000000
+-#define mmDIG6_AFMT_ISRC1_4_DEFAULT 0x00000000
+-#define mmDIG6_AFMT_ISRC2_0_DEFAULT 0x00000000
+-#define mmDIG6_AFMT_ISRC2_1_DEFAULT 0x00000000
+-#define mmDIG6_AFMT_ISRC2_2_DEFAULT 0x00000000
+-#define mmDIG6_AFMT_ISRC2_3_DEFAULT 0x00000000
+-#define mmDIG6_AFMT_AVI_INFO0_DEFAULT 0x00000000
+-#define mmDIG6_AFMT_AVI_INFO1_DEFAULT 0x00000000
+-#define mmDIG6_AFMT_AVI_INFO2_DEFAULT 0x00000000
+-#define mmDIG6_AFMT_AVI_INFO3_DEFAULT 0x02000000
+-#define mmDIG6_AFMT_MPEG_INFO0_DEFAULT 0x00000000
+-#define mmDIG6_AFMT_MPEG_INFO1_DEFAULT 0x00000000
+-#define mmDIG6_AFMT_GENERIC_HDR_DEFAULT 0x00000000
+-#define mmDIG6_AFMT_GENERIC_0_DEFAULT 0x00000000
+-#define mmDIG6_AFMT_GENERIC_1_DEFAULT 0x00000000
+-#define mmDIG6_AFMT_GENERIC_2_DEFAULT 0x00000000
+-#define mmDIG6_AFMT_GENERIC_3_DEFAULT 0x00000000
+-#define mmDIG6_AFMT_GENERIC_4_DEFAULT 0x00000000
+-#define mmDIG6_AFMT_GENERIC_5_DEFAULT 0x00000000
+-#define mmDIG6_AFMT_GENERIC_6_DEFAULT 0x00000000
+-#define mmDIG6_AFMT_GENERIC_7_DEFAULT 0x00000000
+-#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000
+-#define mmDIG6_HDMI_ACR_32_0_DEFAULT 0x00000000
+-#define mmDIG6_HDMI_ACR_32_1_DEFAULT 0x00000000
+-#define mmDIG6_HDMI_ACR_44_0_DEFAULT 0x00000000
+-#define mmDIG6_HDMI_ACR_44_1_DEFAULT 0x00000000
+-#define mmDIG6_HDMI_ACR_48_0_DEFAULT 0x00000000
+-#define mmDIG6_HDMI_ACR_48_1_DEFAULT 0x00000000
+-#define mmDIG6_HDMI_ACR_STATUS_0_DEFAULT 0x00000000
+-#define mmDIG6_HDMI_ACR_STATUS_1_DEFAULT 0x00000000
+-#define mmDIG6_AFMT_AUDIO_INFO0_DEFAULT 0x00000170
+-#define mmDIG6_AFMT_AUDIO_INFO1_DEFAULT 0x00000000
+-#define mmDIG6_AFMT_60958_0_DEFAULT 0x00000000
+-#define mmDIG6_AFMT_60958_1_DEFAULT 0x00000000
+-#define mmDIG6_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000
+-#define mmDIG6_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000
+-#define mmDIG6_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000
+-#define mmDIG6_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000
+-#define mmDIG6_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000
+-#define mmDIG6_AFMT_60958_2_DEFAULT 0x00000000
+-#define mmDIG6_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000
+-#define mmDIG6_AFMT_STATUS_DEFAULT 0x00000000
+-#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800
+-#define mmDIG6_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000
+-#define mmDIG6_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000
+-#define mmDIG6_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000
+-#define mmDIG6_DIG_BE_CNTL_DEFAULT 0x00010000
+-#define mmDIG6_DIG_BE_EN_CNTL_DEFAULT 0x00000000
+-#define mmDIG6_TMDS_CNTL_DEFAULT 0x00000001
+-#define mmDIG6_TMDS_CONTROL_CHAR_DEFAULT 0x00000000
+-#define mmDIG6_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000
+-#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000
+-#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000
+-#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000
+-#define mmDIG6_TMDS_CTL_BITS_DEFAULT 0x00000000
+-#define mmDIG6_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001
+-#define mmDIG6_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000
+-#define mmDIG6_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000
+-#define mmDIG6_DIG_VERSION_DEFAULT 0x00000000
+-#define mmDIG6_DIG_LANE_ENABLE_DEFAULT 0x00000000
+-#define mmDIG6_AFMT_CNTL_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dp6_dispdec
+-#define mmDP6_DP_LINK_CNTL_DEFAULT 0x00000000
+-#define mmDP6_DP_PIXEL_FORMAT_DEFAULT 0x00000000
+-#define mmDP6_DP_MSA_COLORIMETRY_DEFAULT 0x00000000
+-#define mmDP6_DP_CONFIG_DEFAULT 0x00000000
+-#define mmDP6_DP_VID_STREAM_CNTL_DEFAULT 0x00000200
+-#define mmDP6_DP_STEER_FIFO_DEFAULT 0x00000000
+-#define mmDP6_DP_MSA_MISC_DEFAULT 0x00000000
+-#define mmDP6_DP_VID_TIMING_DEFAULT 0x00000000
+-#define mmDP6_DP_VID_N_DEFAULT 0x00002000
+-#define mmDP6_DP_VID_M_DEFAULT 0x00000000
+-#define mmDP6_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000
+-#define mmDP6_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000
+-#define mmDP6_DP_VID_MSA_VBID_DEFAULT 0x01000000
+-#define mmDP6_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000
+-#define mmDP6_DP_DPHY_CNTL_DEFAULT 0x00000000
+-#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000
+-#define mmDP6_DP_DPHY_SYM0_DEFAULT 0x00000000
+-#define mmDP6_DP_DPHY_SYM1_DEFAULT 0x00000000
+-#define mmDP6_DP_DPHY_SYM2_DEFAULT 0x00000000
+-#define mmDP6_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000
+-#define mmDP6_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00
+-#define mmDP6_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10
+-#define mmDP6_DP_DPHY_CRC_EN_DEFAULT 0x00000000
+-#define mmDP6_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000
+-#define mmDP6_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000
+-#define mmDP6_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000
+-#define mmDP6_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000
+-#define mmDP6_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000
+-#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000
+-#define mmDP6_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000
+-#define mmDP6_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000
+-#define mmDP6_DP_SEC_CNTL_DEFAULT 0x00000000
+-#define mmDP6_DP_SEC_CNTL1_DEFAULT 0x00000000
+-#define mmDP6_DP_SEC_FRAMING1_DEFAULT 0x00000000
+-#define mmDP6_DP_SEC_FRAMING2_DEFAULT 0x00000000
+-#define mmDP6_DP_SEC_FRAMING3_DEFAULT 0x00000200
+-#define mmDP6_DP_SEC_FRAMING4_DEFAULT 0x00000000
+-#define mmDP6_DP_SEC_AUD_N_DEFAULT 0x00008000
+-#define mmDP6_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000
+-#define mmDP6_DP_SEC_AUD_M_DEFAULT 0x00000000
+-#define mmDP6_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000
+-#define mmDP6_DP_SEC_TIMESTAMP_DEFAULT 0x00000000
+-#define mmDP6_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100
+-#define mmDP6_DP_MSE_RATE_CNTL_DEFAULT 0x00000000
+-#define mmDP6_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000
+-#define mmDP6_DP_MSE_SAT0_DEFAULT 0x00000000
+-#define mmDP6_DP_MSE_SAT1_DEFAULT 0x00000000
+-#define mmDP6_DP_MSE_SAT2_DEFAULT 0x00000000
+-#define mmDP6_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000
+-#define mmDP6_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff
+-#define mmDP6_DP_MSE_MISC_CNTL_DEFAULT 0x00000000
+-#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005
+-#define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000
+-#define mmDP6_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000
+-#define mmDP6_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000
+-#define mmDP6_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dcio_uniphy0_dispdec
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dc_combophycmregs0_dispdec
+-#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00
+-#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004
+-#define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL_DEFAULT 0x00000007
+-#define mmDC_COMBOPHYCMREGS0_COMMON_TMDP_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS_DEFAULT 0x000000ff
+-#define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dc_combophytxregs0_dispdec
+-#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006
+-#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006
+-#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006
+-#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006
+-#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dc_combophypllregs0_dispdec
+-#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0_DEFAULT 0x00280000
+-#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3_DEFAULT 0x00e80000
+-#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE_DEFAULT 0x0020c4b1
+-#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE_DEFAULT 0x00000001
+-#define mmDC_COMBOPHYPLLREGS0_CAL_CTRL_DEFAULT 0x64000000
+-#define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL_DEFAULT 0x00000090
+-#define mmDC_COMBOPHYPLLREGS0_VREG_CFG_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYPLLREGS0_OBSERVE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYPLLREGS0_OBSERVE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYPLLREGS0_DFT_OUT_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dcio_uniphy1_dispdec
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dc_combophycmregs1_dispdec
+-#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00
+-#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004
+-#define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL_DEFAULT 0x00000007
+-#define mmDC_COMBOPHYCMREGS1_COMMON_TMDP_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS_DEFAULT 0x000000ff
+-#define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dc_combophytxregs1_dispdec
+-#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006
+-#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006
+-#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006
+-#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006
+-#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dc_combophypllregs1_dispdec
+-#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0_DEFAULT 0x00280000
+-#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3_DEFAULT 0x00e80000
+-#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE_DEFAULT 0x0020c4b1
+-#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE_DEFAULT 0x00000001
+-#define mmDC_COMBOPHYPLLREGS1_CAL_CTRL_DEFAULT 0x64000000
+-#define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL_DEFAULT 0x00000090
+-#define mmDC_COMBOPHYPLLREGS1_VREG_CFG_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYPLLREGS1_OBSERVE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYPLLREGS1_OBSERVE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYPLLREGS1_DFT_OUT_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dcio_uniphy2_dispdec
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dc_combophycmregs2_dispdec
+-#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00
+-#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004
+-#define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL_DEFAULT 0x00000007
+-#define mmDC_COMBOPHYCMREGS2_COMMON_TMDP_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS_DEFAULT 0x000000ff
+-#define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dc_combophytxregs2_dispdec
+-#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006
+-#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006
+-#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006
+-#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006
+-#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dc_combophypllregs2_dispdec
+-#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0_DEFAULT 0x00280000
+-#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3_DEFAULT 0x00e80000
+-#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE_DEFAULT 0x0020c4b1
+-#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE_DEFAULT 0x00000001
+-#define mmDC_COMBOPHYPLLREGS2_CAL_CTRL_DEFAULT 0x64000000
+-#define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL_DEFAULT 0x00000090
+-#define mmDC_COMBOPHYPLLREGS2_VREG_CFG_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYPLLREGS2_OBSERVE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYPLLREGS2_OBSERVE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYPLLREGS2_DFT_OUT_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dcio_uniphy3_dispdec
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dc_combophycmregs3_dispdec
+-#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00
+-#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004
+-#define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL_DEFAULT 0x00000007
+-#define mmDC_COMBOPHYCMREGS3_COMMON_TMDP_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS_DEFAULT 0x000000ff
+-#define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dc_combophytxregs3_dispdec
+-#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006
+-#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006
+-#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006
+-#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006
+-#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dc_combophypllregs3_dispdec
+-#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0_DEFAULT 0x00280000
+-#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3_DEFAULT 0x00e80000
+-#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE_DEFAULT 0x0020c4b1
+-#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE_DEFAULT 0x00000001
+-#define mmDC_COMBOPHYPLLREGS3_CAL_CTRL_DEFAULT 0x64000000
+-#define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL_DEFAULT 0x00000090
+-#define mmDC_COMBOPHYPLLREGS3_VREG_CFG_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYPLLREGS3_OBSERVE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYPLLREGS3_OBSERVE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYPLLREGS3_DFT_OUT_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dcio_uniphy4_dispdec
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dc_combophycmregs4_dispdec
+-#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00
+-#define mmDC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004
+-#define mmDC_COMBOPHYCMREGS4_COMMON_TXCNTRL_DEFAULT 0x00000007
+-#define mmDC_COMBOPHYCMREGS4_COMMON_TMDP_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS4_COMMON_LANE_RESETS_DEFAULT 0x000000ff
+-#define mmDC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU4_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU5_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU6_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU7_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dc_combophytxregs4_dispdec
+-#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006
+-#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006
+-#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006
+-#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006
+-#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dc_combophypllregs4_dispdec
+-#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL0_DEFAULT 0x00280000
+-#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL3_DEFAULT 0x00e80000
+-#define mmDC_COMBOPHYPLLREGS4_BW_CTRL_COARSE_DEFAULT 0x0020c4b1
+-#define mmDC_COMBOPHYPLLREGS4_BW_CTRL_FINE_DEFAULT 0x00000001
+-#define mmDC_COMBOPHYPLLREGS4_CAL_CTRL_DEFAULT 0x64000000
+-#define mmDC_COMBOPHYPLLREGS4_LOOP_CTRL_DEFAULT 0x00000090
+-#define mmDC_COMBOPHYPLLREGS4_VREG_CFG_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYPLLREGS4_OBSERVE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYPLLREGS4_OBSERVE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYPLLREGS4_DFT_OUT_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dcio_uniphy5_dispdec
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dc_combophycmregs5_dispdec
+-#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00
+-#define mmDC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004
+-#define mmDC_COMBOPHYCMREGS5_COMMON_TXCNTRL_DEFAULT 0x00000007
+-#define mmDC_COMBOPHYCMREGS5_COMMON_TMDP_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS5_COMMON_LANE_RESETS_DEFAULT 0x000000ff
+-#define mmDC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU4_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU5_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU6_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU7_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dc_combophytxregs5_dispdec
+-#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006
+-#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006
+-#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006
+-#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006
+-#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dc_combophypllregs5_dispdec
+-#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL0_DEFAULT 0x00280000
+-#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL3_DEFAULT 0x00e80000
+-#define mmDC_COMBOPHYPLLREGS5_BW_CTRL_COARSE_DEFAULT 0x0020c4b1
+-#define mmDC_COMBOPHYPLLREGS5_BW_CTRL_FINE_DEFAULT 0x00000001
+-#define mmDC_COMBOPHYPLLREGS5_CAL_CTRL_DEFAULT 0x64000000
+-#define mmDC_COMBOPHYPLLREGS5_LOOP_CTRL_DEFAULT 0x00000090
+-#define mmDC_COMBOPHYPLLREGS5_VREG_CFG_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYPLLREGS5_OBSERVE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYPLLREGS5_OBSERVE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYPLLREGS5_DFT_OUT_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dcio_uniphy6_dispdec
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dc_combophycmregs6_dispdec
+-#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00
+-#define mmDC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004
+-#define mmDC_COMBOPHYCMREGS6_COMMON_TXCNTRL_DEFAULT 0x00000007
+-#define mmDC_COMBOPHYCMREGS6_COMMON_TMDP_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS6_COMMON_LANE_RESETS_DEFAULT 0x000000ff
+-#define mmDC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU4_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU5_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU6_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU7_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dc_combophytxregs6_dispdec
+-#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006
+-#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006
+-#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006
+-#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006
+-#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dc_combophypllregs6_dispdec
+-#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL0_DEFAULT 0x00280000
+-#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL3_DEFAULT 0x00e80000
+-#define mmDC_COMBOPHYPLLREGS6_BW_CTRL_COARSE_DEFAULT 0x0020c4b1
+-#define mmDC_COMBOPHYPLLREGS6_BW_CTRL_FINE_DEFAULT 0x00000001
+-#define mmDC_COMBOPHYPLLREGS6_CAL_CTRL_DEFAULT 0x64000000
+-#define mmDC_COMBOPHYPLLREGS6_LOOP_CTRL_DEFAULT 0x00000090
+-#define mmDC_COMBOPHYPLLREGS6_VREG_CFG_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYPLLREGS6_OBSERVE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYPLLREGS6_OBSERVE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYPLLREGS6_DFT_OUT_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dcio_uniphy8_dispdec
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dc_combophycmregs8_dispdec
+-#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00
+-#define mmDC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004
+-#define mmDC_COMBOPHYCMREGS8_COMMON_TXCNTRL_DEFAULT 0x00000007
+-#define mmDC_COMBOPHYCMREGS8_COMMON_TMDP_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS8_COMMON_LANE_RESETS_DEFAULT 0x000000ff
+-#define mmDC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU4_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU5_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU6_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU7_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dc_combophytxregs8_dispdec
+-#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006
+-#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006
+-#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006
+-#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006
+-#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dc_combophypllregs8_dispdec
+-#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL0_DEFAULT 0x00280000
+-#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL2_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL3_DEFAULT 0x00e80000
+-#define mmDC_COMBOPHYPLLREGS8_BW_CTRL_COARSE_DEFAULT 0x0020c4b1
+-#define mmDC_COMBOPHYPLLREGS8_BW_CTRL_FINE_DEFAULT 0x00000001
+-#define mmDC_COMBOPHYPLLREGS8_CAL_CTRL_DEFAULT 0x64000000
+-#define mmDC_COMBOPHYPLLREGS8_LOOP_CTRL_DEFAULT 0x00000090
+-#define mmDC_COMBOPHYPLLREGS8_VREG_CFG_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYPLLREGS8_OBSERVE0_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYPLLREGS8_OBSERVE1_DEFAULT 0x00000000
+-#define mmDC_COMBOPHYPLLREGS8_DFT_OUT_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dsi0_dispdec
+-#define mmDSI0_DISP_DSI_CTRL_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_STATUS_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_VIDEO_MODE_CTRL_DEFAULT 0x00008000
+-#define mmDSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE_DEFAULT 0x31211101
+-#define mmDSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE_DEFAULT 0x3e2e1e0e
+-#define mmDSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE_DEFAULT 0x00001900
+-#define mmDSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_COMMAND_MODE_CTRL_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL_DEFAULT 0x00000066
+-#define mmDSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL_DEFAULT 0x00003c2c
+-#define mmDSI0_DISP_DSI_DMA_CMD_OFFSET_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_DMA_CMD_LENGTH_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_DMA_DATA_OFFSET_0_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_DMA_DATA_OFFSET_1_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_DMA_DATA_PITCH_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_DMA_DATA_WIDTH_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_DMA_DATA_HEIGHT_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_DMA_FIFO_CTRL_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_DMA_NULL_PACKET_DATA_DEFAULT 0x00000900
+-#define mmDSI0_DISP_DSI_DENG_DATA_LENGTH_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_ACK_ERROR_REPORT_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_RDBK_DATA0_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_RDBK_DATA1_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_RDBK_DATA2_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_RDBK_DATA3_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_RDBK_DATATYPE0_DEFAULT 0x22211211
+-#define mmDSI0_DISP_DSI_RDBK_DATATYPE1_DEFAULT 0x001c1a02
+-#define mmDSI0_DISP_DSI_TRIG_CTRL_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_EXT_MUX_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_RESET_SW_TRIGGER_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_EXT_RESET_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_LANE_CRC_HS_MODE_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_LANE_CRC_LP_MODE_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_LANE_CRC_CTRL_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_PIXEL_CRC_CTRL_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_LANE_CTRL_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_DLN0_PHY_ERROR_DEFAULT 0x00088888
+-#define mmDSI0_DISP_DSI_LP_TIMER_CTRL_DEFAULT 0xffffffff
+-#define mmDSI0_DISP_DSI_HS_TIMER_CTRL_DEFAULT 0x0000ffff
+-#define mmDSI0_DISP_DSI_TIMEOUT_STATUS_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_EOT_PACKET_DEFAULT 0x010f0f08
+-#define mmDSI0_DISP_DSI_EOT_PACKET_CTRL_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_MIPI_BIST_CTRL_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_MIPI_BIST_LSFR_INIT_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_MIPI_BIST_START_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_MIPI_BIST_STATUS_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_ERROR_INTERRUPT_MASK_DEFAULT 0xfd37377f
+-#define mmDSI0_DISP_DSI_INTERRUPT_CTRL_DEFAULT 0x02222222
+-#define mmDSI0_DISP_DSI_CLK_CTRL_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_CLK_STATUS_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_DENG_FIFO_STATUS_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_DENG_FIFO_CTRL_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_CMD_FIFO_DATA_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_CMD_FIFO_CTRL_DEFAULT 0x00000001
+-#define mmDSI0_DISP_DSI_TE_CTRL_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_LANE_STATUS_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_PERF_CTRL_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_HSYNC_LENGTH_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_RDBK_NUM_DEFAULT 0x00000000
+-#define mmDSI0_DISP_DSI_CMD_MEM_PWR_CTRL_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dsi1_dispdec
+-#define mmDSI1_DISP_DSI_CTRL_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_STATUS_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_VIDEO_MODE_CTRL_DEFAULT 0x00008000
+-#define mmDSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE_DEFAULT 0x31211101
+-#define mmDSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE_DEFAULT 0x3e2e1e0e
+-#define mmDSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE_DEFAULT 0x00001900
+-#define mmDSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_COMMAND_MODE_CTRL_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL_DEFAULT 0x00000066
+-#define mmDSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL_DEFAULT 0x00003c2c
+-#define mmDSI1_DISP_DSI_DMA_CMD_OFFSET_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_DMA_CMD_LENGTH_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_DMA_DATA_OFFSET_0_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_DMA_DATA_OFFSET_1_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_DMA_DATA_PITCH_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_DMA_DATA_WIDTH_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_DMA_DATA_HEIGHT_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_DMA_FIFO_CTRL_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_DMA_NULL_PACKET_DATA_DEFAULT 0x00000900
+-#define mmDSI1_DISP_DSI_DENG_DATA_LENGTH_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_ACK_ERROR_REPORT_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_RDBK_DATA0_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_RDBK_DATA1_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_RDBK_DATA2_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_RDBK_DATA3_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_RDBK_DATATYPE0_DEFAULT 0x22211211
+-#define mmDSI1_DISP_DSI_RDBK_DATATYPE1_DEFAULT 0x001c1a02
+-#define mmDSI1_DISP_DSI_TRIG_CTRL_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_EXT_MUX_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_RESET_SW_TRIGGER_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_EXT_RESET_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_LANE_CRC_HS_MODE_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_LANE_CRC_LP_MODE_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_LANE_CRC_CTRL_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_PIXEL_CRC_CTRL_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_LANE_CTRL_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_DLN0_PHY_ERROR_DEFAULT 0x00088888
+-#define mmDSI1_DISP_DSI_LP_TIMER_CTRL_DEFAULT 0xffffffff
+-#define mmDSI1_DISP_DSI_HS_TIMER_CTRL_DEFAULT 0x0000ffff
+-#define mmDSI1_DISP_DSI_TIMEOUT_STATUS_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_EOT_PACKET_DEFAULT 0x010f0f08
+-#define mmDSI1_DISP_DSI_EOT_PACKET_CTRL_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_MIPI_BIST_CTRL_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_MIPI_BIST_LSFR_INIT_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_MIPI_BIST_START_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_MIPI_BIST_STATUS_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_ERROR_INTERRUPT_MASK_DEFAULT 0xfd37377f
+-#define mmDSI1_DISP_DSI_INTERRUPT_CTRL_DEFAULT 0x02222222
+-#define mmDSI1_DISP_DSI_CLK_CTRL_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_CLK_STATUS_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_DENG_FIFO_STATUS_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_DENG_FIFO_CTRL_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_CMD_FIFO_DATA_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_CMD_FIFO_CTRL_DEFAULT 0x00000001
+-#define mmDSI1_DISP_DSI_TE_CTRL_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_LANE_STATUS_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_PERF_CTRL_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_HSYNC_LENGTH_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_RDBK_NUM_DEFAULT 0x00000000
+-#define mmDSI1_DISP_DSI_CMD_MEM_PWR_CTRL_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dprx_sd0_dispdec
+-#define mmDPRX_SD0_DPRX_SD_CONTROL_DEFAULT 0x00000000
+-#define mmDPRX_SD0_DPRX_SD_STREAM_ENABLE_DEFAULT 0x00000000
+-#define mmDPRX_SD0_DPRX_SD_MSA0_DEFAULT 0x00000000
+-#define mmDPRX_SD0_DPRX_SD_MSA1_DEFAULT 0x00000000
+-#define mmDPRX_SD0_DPRX_SD_MSA2_DEFAULT 0x00000000
+-#define mmDPRX_SD0_DPRX_SD_MSA3_DEFAULT 0x00000000
+-#define mmDPRX_SD0_DPRX_SD_MSA4_DEFAULT 0x00000000
+-#define mmDPRX_SD0_DPRX_SD_MSA5_DEFAULT 0x00000000
+-#define mmDPRX_SD0_DPRX_SD_MSA6_DEFAULT 0x00000000
+-#define mmDPRX_SD0_DPRX_SD_MSA7_DEFAULT 0x00000000
+-#define mmDPRX_SD0_DPRX_SD_MSA8_DEFAULT 0x00000000
+-#define mmDPRX_SD0_DPRX_SD_VBID_DEFAULT 0x00000000
+-#define mmDPRX_SD0_DPRX_SD_CURRENT_LINE_DEFAULT 0x00000000
+-#define mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_SNAPSHOT_DEFAULT 0x00000000
+-#define mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE_DEFAULT 0x00000000
+-#define mmDPRX_SD0_DPRX_SD_MSE_SAT_DEFAULT 0x00000000
+-#define mmDPRX_SD0_DPRX_SD_MSE_FORCE_UPDATE_DEFAULT 0x00000000
+-#define mmDPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE_DEFAULT 0x00000000
+-#define mmDPRX_SD0_DPRX_SD_V_PARAMETER_DEFAULT 0x00000000
+-#define mmDPRX_SD0_DPRX_SD_PIXEL_FORMAT_DEFAULT 0x00000000
+-#define mmDPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS_DEFAULT 0x00000000
+-#define mmDPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED_DEFAULT 0x00000000
+-#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS_DEFAULT 0x00000000
+-#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_CONTROL_DEFAULT 0x0000ffff
+-#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS_DEFAULT 0x00000000
+-#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_CONTROL_DEFAULT 0x0000ffff
+-#define mmDPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR_DEFAULT 0x00000000
+-#define mmDPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE_DEFAULT 0x00000000
+-#define mmDPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR_DEFAULT 0x00000000
+-#define mmDPRX_SD0_DPRX_SD_VCPF_PHASE_LOCKED_DEFAULT 0x00000000
+-#define mmDPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR_DEFAULT 0x00000000
+-#define mmDPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR_DEFAULT 0x00000000
+-#define mmDPRX_SD0_DPRX_SD_PIXEL_FIFO_ERROR_DEFAULT 0x00000000
+-#define mmDPRX_SD0_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH_DEFAULT 0x000003ff
+-#define mmDPRX_SD0_DPRX_SD_SDP_STEER_DEFAULT 0x00000001
+-#define mmDPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS_DEFAULT 0x00000000
+-#define mmDPRX_SD0_DPRX_SD_SDP_LEVEL_DEFAULT 0x00000000
+-#define mmDPRX_SD0_DPRX_SD_SDP_DATA_DEFAULT 0x00000000
+-#define mmDPRX_SD0_DPRX_SD_SDP_ERROR_DEFAULT 0x00000000
+-#define mmDPRX_SD0_DPRX_SD_AUDIO_HEADER_DEFAULT 0x00000000
+-#define mmDPRX_SD0_DPRX_SD_AUDIO_FIFO_ERROR_DEFAULT 0x00000000
+-#define mmDPRX_SD0_DPRX_SD_SDP_CONTROL_DEFAULT 0x00000001
+-#define mmDPRX_SD0_DPRX_SD_V_TOTAL_MEASURED_DEFAULT 0x00000000
+-#define mmDPRX_SD0_DPRX_SD_H_TOTAL_MEASURED_DEFAULT 0x00000000
+-#define mmDPRX_SD0_DPRX_SD_BS_COUNTER_DEFAULT 0x00000000
+-#define mmDPRX_SD0_DPRX_SD_MSE_ACT_HANDLED_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dprx_sd1_dispdec
+-#define mmDPRX_SD1_DPRX_SD_CONTROL_DEFAULT 0x00000000
+-#define mmDPRX_SD1_DPRX_SD_STREAM_ENABLE_DEFAULT 0x00000000
+-#define mmDPRX_SD1_DPRX_SD_MSA0_DEFAULT 0x00000000
+-#define mmDPRX_SD1_DPRX_SD_MSA1_DEFAULT 0x00000000
+-#define mmDPRX_SD1_DPRX_SD_MSA2_DEFAULT 0x00000000
+-#define mmDPRX_SD1_DPRX_SD_MSA3_DEFAULT 0x00000000
+-#define mmDPRX_SD1_DPRX_SD_MSA4_DEFAULT 0x00000000
+-#define mmDPRX_SD1_DPRX_SD_MSA5_DEFAULT 0x00000000
+-#define mmDPRX_SD1_DPRX_SD_MSA6_DEFAULT 0x00000000
+-#define mmDPRX_SD1_DPRX_SD_MSA7_DEFAULT 0x00000000
+-#define mmDPRX_SD1_DPRX_SD_MSA8_DEFAULT 0x00000000
+-#define mmDPRX_SD1_DPRX_SD_VBID_DEFAULT 0x00000000
+-#define mmDPRX_SD1_DPRX_SD_CURRENT_LINE_DEFAULT 0x00000000
+-#define mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_SNAPSHOT_DEFAULT 0x00000000
+-#define mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE_DEFAULT 0x00000000
+-#define mmDPRX_SD1_DPRX_SD_MSE_SAT_DEFAULT 0x00000000
+-#define mmDPRX_SD1_DPRX_SD_MSE_FORCE_UPDATE_DEFAULT 0x00000000
+-#define mmDPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE_DEFAULT 0x00000000
+-#define mmDPRX_SD1_DPRX_SD_V_PARAMETER_DEFAULT 0x00000000
+-#define mmDPRX_SD1_DPRX_SD_PIXEL_FORMAT_DEFAULT 0x00000000
+-#define mmDPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS_DEFAULT 0x00000000
+-#define mmDPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED_DEFAULT 0x00000000
+-#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS_DEFAULT 0x00000000
+-#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_CONTROL_DEFAULT 0x0000ffff
+-#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS_DEFAULT 0x00000000
+-#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_CONTROL_DEFAULT 0x0000ffff
+-#define mmDPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR_DEFAULT 0x00000000
+-#define mmDPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE_DEFAULT 0x00000000
+-#define mmDPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR_DEFAULT 0x00000000
+-#define mmDPRX_SD1_DPRX_SD_VCPF_PHASE_LOCKED_DEFAULT 0x00000000
+-#define mmDPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR_DEFAULT 0x00000000
+-#define mmDPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR_DEFAULT 0x00000000
+-#define mmDPRX_SD1_DPRX_SD_PIXEL_FIFO_ERROR_DEFAULT 0x00000000
+-#define mmDPRX_SD1_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH_DEFAULT 0x000003ff
+-#define mmDPRX_SD1_DPRX_SD_SDP_STEER_DEFAULT 0x00000001
+-#define mmDPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS_DEFAULT 0x00000000
+-#define mmDPRX_SD1_DPRX_SD_SDP_LEVEL_DEFAULT 0x00000000
+-#define mmDPRX_SD1_DPRX_SD_SDP_DATA_DEFAULT 0x00000000
+-#define mmDPRX_SD1_DPRX_SD_SDP_ERROR_DEFAULT 0x00000000
+-#define mmDPRX_SD1_DPRX_SD_AUDIO_HEADER_DEFAULT 0x00000000
+-#define mmDPRX_SD1_DPRX_SD_AUDIO_FIFO_ERROR_DEFAULT 0x00000000
+-#define mmDPRX_SD1_DPRX_SD_SDP_CONTROL_DEFAULT 0x00000001
+-#define mmDPRX_SD1_DPRX_SD_V_TOTAL_MEASURED_DEFAULT 0x00000000
+-#define mmDPRX_SD1_DPRX_SD_H_TOTAL_MEASURED_DEFAULT 0x00000000
+-#define mmDPRX_SD1_DPRX_SD_BS_COUNTER_DEFAULT 0x00000000
+-#define mmDPRX_SD1_DPRX_SD_MSE_ACT_HANDLED_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dc_perfmon10_dispdec
+-#define mmDC_PERFMON10_PERFCOUNTER_CNTL_DEFAULT 0x00000000
+-#define mmDC_PERFMON10_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
+-#define mmDC_PERFMON10_PERFCOUNTER_STATE_DEFAULT 0x00000000
+-#define mmDC_PERFMON10_PERFMON_CNTL_DEFAULT 0x00000100
+-#define mmDC_PERFMON10_PERFMON_CNTL2_DEFAULT 0x00000000
+-#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
+-#define mmDC_PERFMON10_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
+-#define mmDC_PERFMON10_PERFMON_HI_DEFAULT 0x00000000
+-#define mmDC_PERFMON10_PERFMON_LOW_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dc_zcalregs_dispdec
+-#define mmCOMP_EN_CTL_DEFAULT 0x00080000
+-#define mmCOMP_EN_DFX_DEFAULT 0x00000000
+-#define mmZCAL_FUSES_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_dispdec_VGA_MEM_WRITE_PAGE_ADDR
+-
+-
+-// addressBlock: dce_dc_dispdec_VGA_MEM_READ_PAGE_ADDR
+-
+-
+-// addressBlock: dce_dc_dispdec[948..986]
+-
+-
+-// addressBlock: dce_dc_azdec
+-#define mmCORB_WRITE_POINTER_DEFAULT 0x00000000
+-#define mmCORB_READ_POINTER_DEFAULT 0x00000000
+-#define mmCORB_CONTROL_DEFAULT 0x00000000
+-#define mmCORB_STATUS_DEFAULT 0x00000000
+-#define mmCORB_SIZE_DEFAULT 0x00000002
+-#define mmRIRB_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
+-#define mmRIRB_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
+-#define mmRIRB_WRITE_POINTER_DEFAULT 0x00000000
+-#define mmRESPONSE_INTERRUPT_COUNT_DEFAULT 0x00000000
+-#define mmRIRB_CONTROL_DEFAULT 0x00000000
+-#define mmRIRB_STATUS_DEFAULT 0x00000000
+-#define mmRIRB_SIZE_DEFAULT 0x00000002
+-#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_DEFAULT 0x00000000
+-#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_DEFAULT 0x00000000
+-#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000
+-#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000
+-#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000
+-#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000
+-#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DEFAULT 0x00000000
+-#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000
+-#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000
+-#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_DEFAULT 0x00000000
+-#define mmIMMEDIATE_COMMAND_STATUS_DEFAULT 0x00000000
+-#define mmDMA_POSITION_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
+-#define mmDMA_POSITION_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
+-#define mmWALL_CLOCK_COUNTER_ALIAS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_azstream0_azdec
+-#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000
+-#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000
+-#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000
+-#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000
+-#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000
+-#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000
+-#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
+-#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
+-#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_azstream1_azdec
+-#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000
+-#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000
+-#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000
+-#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000
+-#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000
+-#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000
+-#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
+-#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
+-#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_azstream2_azdec
+-#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000
+-#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000
+-#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000
+-#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000
+-#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000
+-#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000
+-#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
+-#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
+-#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_azstream3_azdec
+-#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000
+-#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000
+-#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000
+-#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000
+-#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000
+-#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000
+-#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
+-#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
+-#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_azstream4_azdec
+-#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000
+-#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000
+-#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000
+-#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000
+-#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000
+-#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000
+-#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
+-#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
+-#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_azstream5_azdec
+-#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000
+-#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000
+-#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000
+-#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000
+-#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000
+-#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000
+-#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
+-#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
+-#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_azstream6_azdec
+-#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000
+-#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000
+-#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000
+-#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000
+-#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000
+-#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000
+-#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
+-#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
+-#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: dce_dc_azstream7_azdec
+-#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000
+-#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000
+-#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000
+-#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000
+-#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000
+-#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000
+-#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
+-#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
+-#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: azf0stream0_streamind
+-#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
+-#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
+-#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
+-#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
+-
+-
+-// addressBlock: azf0stream1_streamind
+-#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
+-#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
+-#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
+-#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
+-
+-
+-// addressBlock: azf0stream2_streamind
+-#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
+-#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
+-#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
+-#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
+-
+-
+-// addressBlock: azf0stream3_streamind
+-#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
+-#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
+-#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
+-#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
+-
+-
+-// addressBlock: azf0stream4_streamind
+-#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
+-#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
+-#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
+-#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
+-
+-
+-// addressBlock: azf0stream5_streamind
+-#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
+-#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
+-#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
+-#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
+-
+-
+-// addressBlock: azf0stream6_streamind
+-#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
+-#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
+-#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
+-#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
+-
+-
+-// addressBlock: azf0stream7_streamind
+-#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
+-#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
+-#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
+-#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
+-
+-
+-// addressBlock: azf0stream8_streamind
+-#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
+-#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
+-#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
+-#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
+-
+-
+-// addressBlock: azf0stream9_streamind
+-#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
+-#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
+-#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
+-#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
+-
+-
+-// addressBlock: azf0stream10_streamind
+-#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
+-#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
+-#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
+-#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
+-
+-
+-// addressBlock: azf0stream11_streamind
+-#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
+-#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
+-#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
+-#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
+-
+-
+-// addressBlock: azf0stream12_streamind
+-#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
+-#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
+-#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
+-#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
+-
+-
+-// addressBlock: azf0stream13_streamind
+-#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
+-#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
+-#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
+-#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
+-
+-
+-// addressBlock: azf0stream14_streamind
+-#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
+-#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
+-#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
+-#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
+-
+-
+-// addressBlock: azf0stream15_streamind
+-#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
+-#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
+-#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
+-#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
+-
+-
+-// addressBlock: azf0endpoint0_endpointind
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: azf0endpoint1_endpointind
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: azf0endpoint2_endpointind
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: azf0endpoint3_endpointind
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: azf0endpoint4_endpointind
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: azf0endpoint5_endpointind
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: azf0endpoint6_endpointind
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: azf0endpoint7_endpointind
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000
+-#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: azf0inputendpoint0_inputendpointind
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000
+-
+-
+-// addressBlock: azf0inputendpoint1_inputendpointind
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000
+-
+-
+-// addressBlock: azf0inputendpoint2_inputendpointind
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000
+-
+-
+-// addressBlock: azf0inputendpoint3_inputendpointind
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000
+-
+-
+-// addressBlock: azf0inputendpoint4_inputendpointind
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000
+-
+-
+-// addressBlock: azf0inputendpoint5_inputendpointind
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000
+-
+-
+-// addressBlock: azf0inputendpoint6_inputendpointind
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000
+-
+-
+-// addressBlock: azf0inputendpoint7_inputendpointind
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000
+-
+-
+-// addressBlock: f2codecind
+-#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE_DEFAULT 0x00000003
+-#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2_DEFAULT 0x00000001
+-#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3_DEFAULT 0x000000aa
+-#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x000000b4
+-#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000020
+-#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000040
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x00000010
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3_DEFAULT 0x00000056
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4_DEFAULT 0x00000018
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000
+-#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000
+-#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000
+-#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000
+-#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000
+-#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000
+-#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000
+-#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000
+-#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000
+-#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000020
+-#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x000000f0
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3_DEFAULT 0x000000d6
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4_DEFAULT 0x00000018
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000010
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000000
+-
+-
+-// addressBlock: descriptorind
+-#define ixAUDIO_DESCRIPTOR0_DEFAULT 0x00000000
+-#define ixAUDIO_DESCRIPTOR1_DEFAULT 0x00000000
+-#define ixAUDIO_DESCRIPTOR2_DEFAULT 0x00000000
+-#define ixAUDIO_DESCRIPTOR3_DEFAULT 0x00000000
+-#define ixAUDIO_DESCRIPTOR4_DEFAULT 0x00000000
+-#define ixAUDIO_DESCRIPTOR5_DEFAULT 0x00000000
+-#define ixAUDIO_DESCRIPTOR6_DEFAULT 0x00000000
+-#define ixAUDIO_DESCRIPTOR7_DEFAULT 0x00000000
+-#define ixAUDIO_DESCRIPTOR8_DEFAULT 0x00000000
+-#define ixAUDIO_DESCRIPTOR9_DEFAULT 0x00000000
+-#define ixAUDIO_DESCRIPTOR10_DEFAULT 0x00000000
+-#define ixAUDIO_DESCRIPTOR11_DEFAULT 0x00000000
+-#define ixAUDIO_DESCRIPTOR12_DEFAULT 0x00000000
+-#define ixAUDIO_DESCRIPTOR13_DEFAULT 0x00000000
+-
+-
+-// addressBlock: sinkinfoind
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0_DEFAULT 0x00000000
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1_DEFAULT 0x00000000
+-#define ixSINK_DESCRIPTION0_DEFAULT 0x00000000
+-#define ixSINK_DESCRIPTION1_DEFAULT 0x00000000
+-#define ixSINK_DESCRIPTION2_DEFAULT 0x00000000
+-#define ixSINK_DESCRIPTION3_DEFAULT 0x00000000
+-#define ixSINK_DESCRIPTION4_DEFAULT 0x00000000
+-#define ixSINK_DESCRIPTION5_DEFAULT 0x00000000
+-#define ixSINK_DESCRIPTION6_DEFAULT 0x00000000
+-#define ixSINK_DESCRIPTION7_DEFAULT 0x00000000
+-#define ixSINK_DESCRIPTION8_DEFAULT 0x00000000
+-#define ixSINK_DESCRIPTION9_DEFAULT 0x00000000
+-#define ixSINK_DESCRIPTION10_DEFAULT 0x00000000
+-#define ixSINK_DESCRIPTION11_DEFAULT 0x00000000
+-#define ixSINK_DESCRIPTION12_DEFAULT 0x00000000
+-#define ixSINK_DESCRIPTION13_DEFAULT 0x00000000
+-#define ixSINK_DESCRIPTION14_DEFAULT 0x00000000
+-#define ixSINK_DESCRIPTION15_DEFAULT 0x00000000
+-#define ixSINK_DESCRIPTION16_DEFAULT 0x00000000
+-#define ixSINK_DESCRIPTION17_DEFAULT 0x00000000
+-
+-
+-// addressBlock: azinputcrc0resultind
+-#define ixAZALIA_INPUT_CRC0_CHANNEL0_DEFAULT 0x00000000
+-#define ixAZALIA_INPUT_CRC0_CHANNEL1_DEFAULT 0x00000000
+-#define ixAZALIA_INPUT_CRC0_CHANNEL2_DEFAULT 0x00000000
+-#define ixAZALIA_INPUT_CRC0_CHANNEL3_DEFAULT 0x00000000
+-#define ixAZALIA_INPUT_CRC0_CHANNEL4_DEFAULT 0x00000000
+-#define ixAZALIA_INPUT_CRC0_CHANNEL5_DEFAULT 0x00000000
+-#define ixAZALIA_INPUT_CRC0_CHANNEL6_DEFAULT 0x00000000
+-#define ixAZALIA_INPUT_CRC0_CHANNEL7_DEFAULT 0x00000000
+-
+-
+-// addressBlock: azinputcrc1resultind
+-#define ixAZALIA_INPUT_CRC1_CHANNEL0_DEFAULT 0x00000000
+-#define ixAZALIA_INPUT_CRC1_CHANNEL1_DEFAULT 0x00000000
+-#define ixAZALIA_INPUT_CRC1_CHANNEL2_DEFAULT 0x00000000
+-#define ixAZALIA_INPUT_CRC1_CHANNEL3_DEFAULT 0x00000000
+-#define ixAZALIA_INPUT_CRC1_CHANNEL4_DEFAULT 0x00000000
+-#define ixAZALIA_INPUT_CRC1_CHANNEL5_DEFAULT 0x00000000
+-#define ixAZALIA_INPUT_CRC1_CHANNEL6_DEFAULT 0x00000000
+-#define ixAZALIA_INPUT_CRC1_CHANNEL7_DEFAULT 0x00000000
+-
+-
+-// addressBlock: azcrc0resultind
+-#define ixAZALIA_CRC0_CHANNEL0_DEFAULT 0x00000000
+-#define ixAZALIA_CRC0_CHANNEL1_DEFAULT 0x00000000
+-#define ixAZALIA_CRC0_CHANNEL2_DEFAULT 0x00000000
+-#define ixAZALIA_CRC0_CHANNEL3_DEFAULT 0x00000000
+-#define ixAZALIA_CRC0_CHANNEL4_DEFAULT 0x00000000
+-#define ixAZALIA_CRC0_CHANNEL5_DEFAULT 0x00000000
+-#define ixAZALIA_CRC0_CHANNEL6_DEFAULT 0x00000000
+-#define ixAZALIA_CRC0_CHANNEL7_DEFAULT 0x00000000
+-
+-
+-// addressBlock: azcrc1resultind
+-#define ixAZALIA_CRC1_CHANNEL0_DEFAULT 0x00000000
+-#define ixAZALIA_CRC1_CHANNEL1_DEFAULT 0x00000000
+-#define ixAZALIA_CRC1_CHANNEL2_DEFAULT 0x00000000
+-#define ixAZALIA_CRC1_CHANNEL3_DEFAULT 0x00000000
+-#define ixAZALIA_CRC1_CHANNEL4_DEFAULT 0x00000000
+-#define ixAZALIA_CRC1_CHANNEL5_DEFAULT 0x00000000
+-#define ixAZALIA_CRC1_CHANNEL6_DEFAULT 0x00000000
+-#define ixAZALIA_CRC1_CHANNEL7_DEFAULT 0x00000000
+-
+-
+-// addressBlock: vgaseqind
+-#define ixSEQ00_DEFAULT 0x00000003
+-#define ixSEQ01_DEFAULT 0x00000021
+-#define ixSEQ02_DEFAULT 0x00000000
+-#define ixSEQ03_DEFAULT 0x00000000
+-#define ixSEQ04_DEFAULT 0x00000000
+-
+-
+-// addressBlock: vgacrtind
+-#define ixCRT00_DEFAULT 0x00000000
+-#define ixCRT01_DEFAULT 0x00000000
+-#define ixCRT02_DEFAULT 0x00000000
+-#define ixCRT03_DEFAULT 0x00000000
+-#define ixCRT04_DEFAULT 0x00000000
+-#define ixCRT05_DEFAULT 0x00000000
+-#define ixCRT06_DEFAULT 0x00000000
+-#define ixCRT07_DEFAULT 0x00000000
+-#define ixCRT08_DEFAULT 0x00000000
+-#define ixCRT09_DEFAULT 0x00000000
+-#define ixCRT0A_DEFAULT 0x00000000
+-#define ixCRT0B_DEFAULT 0x00000000
+-#define ixCRT0C_DEFAULT 0x00000000
+-#define ixCRT0D_DEFAULT 0x00000000
+-#define ixCRT0E_DEFAULT 0x00000000
+-#define ixCRT0F_DEFAULT 0x00000000
+-#define ixCRT10_DEFAULT 0x00000000
+-#define ixCRT11_DEFAULT 0x00000000
+-#define ixCRT12_DEFAULT 0x00000000
+-#define ixCRT13_DEFAULT 0x00000000
+-#define ixCRT14_DEFAULT 0x00000000
+-#define ixCRT15_DEFAULT 0x00000000
+-#define ixCRT16_DEFAULT 0x00000000
+-#define ixCRT17_DEFAULT 0x00000000
+-#define ixCRT18_DEFAULT 0x00000000
+-#define ixCRT1E_DEFAULT 0x00000000
+-#define ixCRT1F_DEFAULT 0x00000000
+-#define ixCRT22_DEFAULT 0x00000000
+-
+-
+-// addressBlock: vgagrphind
+-#define ixGRA00_DEFAULT 0x00000000
+-#define ixGRA01_DEFAULT 0x00000000
+-#define ixGRA02_DEFAULT 0x00000000
+-#define ixGRA03_DEFAULT 0x00000000
+-#define ixGRA04_DEFAULT 0x00000000
+-#define ixGRA05_DEFAULT 0x00000000
+-#define ixGRA06_DEFAULT 0x00000000
+-#define ixGRA07_DEFAULT 0x00000000
+-#define ixGRA08_DEFAULT 0x00000000
+-
+-
+-// addressBlock: vgaattrind
+-#define ixATTR00_DEFAULT 0x00000000
+-#define ixATTR01_DEFAULT 0x00000000
+-#define ixATTR02_DEFAULT 0x00000000
+-#define ixATTR03_DEFAULT 0x00000000
+-#define ixATTR04_DEFAULT 0x00000000
+-#define ixATTR05_DEFAULT 0x00000000
+-#define ixATTR06_DEFAULT 0x00000000
+-#define ixATTR07_DEFAULT 0x00000000
+-#define ixATTR08_DEFAULT 0x00000000
+-#define ixATTR09_DEFAULT 0x00000000
+-#define ixATTR0A_DEFAULT 0x00000000
+-#define ixATTR0B_DEFAULT 0x00000000
+-#define ixATTR0C_DEFAULT 0x00000000
+-#define ixATTR0D_DEFAULT 0x00000000
+-#define ixATTR0E_DEFAULT 0x00000000
+-#define ixATTR0F_DEFAULT 0x00000000
+-#define ixATTR10_DEFAULT 0x00000000
+-#define ixATTR11_DEFAULT 0x00000000
+-#define ixATTR12_DEFAULT 0x00000000
+-#define ixATTR13_DEFAULT 0x00000000
+-#define ixATTR14_DEFAULT 0x00000000
+-
+-
+-#endif
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_offset.h
+deleted file mode 100644
+index 75b660d..0000000
+--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_offset.h
++++ /dev/null
+@@ -1,18193 +0,0 @@
+-/*
+- * Copyright (C) 2017 Advanced Micro Devices, Inc.
+- *
+- * Permission is hereby granted, free of charge, to any person obtaining a
+- * copy of this software and associated documentation files (the "Software"),
+- * to deal in the Software without restriction, including without limitation
+- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+- * and/or sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following conditions:
+- *
+- * The above copyright notice and this permission notice shall be included
+- * in all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+- */
+-#ifndef _dce_12_0_OFFSET_HEADER
+-#define _dce_12_0_OFFSET_HEADER
+-
+-
+-
+-// addressBlock: dce_dc_dispdec_VGA_MEM_WRITE_PAGE_ADDR
+-// base address: 0x48
+-#define mmdispdec_VGA_MEM_WRITE_PAGE_ADDR 0x0012
+-#define mmdispdec_VGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
+-
+-
+-// addressBlock: dce_dc_dispdec_VGA_MEM_READ_PAGE_ADDR
+-// base address: 0x4c
+-#define mmdispdec_VGA_MEM_READ_PAGE_ADDR 0x0014
+-#define mmdispdec_VGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
+-
+-
+-// addressBlock: dce_dc_dc_perfmon0_dispdec
+-// base address: 0x0
+-#define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x0020
+-#define mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2
+-#define mmDC_PERFMON0_PERFCOUNTER_CNTL2 0x0021
+-#define mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2
+-#define mmDC_PERFMON0_PERFCOUNTER_STATE 0x0022
+-#define mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2
+-#define mmDC_PERFMON0_PERFMON_CNTL 0x0023
+-#define mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2
+-#define mmDC_PERFMON0_PERFMON_CNTL2 0x0024
+-#define mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2
+-#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x0025
+-#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+-#define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x0026
+-#define mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2
+-#define mmDC_PERFMON0_PERFMON_HI 0x0027
+-#define mmDC_PERFMON0_PERFMON_HI_BASE_IDX 2
+-#define mmDC_PERFMON0_PERFMON_LOW 0x0028
+-#define mmDC_PERFMON0_PERFMON_LOW_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dc_perfmon13_dispdec
+-// base address: 0x30
+-#define mmDC_PERFMON13_PERFCOUNTER_CNTL 0x002c
+-#define mmDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX 2
+-#define mmDC_PERFMON13_PERFCOUNTER_CNTL2 0x002d
+-#define mmDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX 2
+-#define mmDC_PERFMON13_PERFCOUNTER_STATE 0x002e
+-#define mmDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX 2
+-#define mmDC_PERFMON13_PERFMON_CNTL 0x002f
+-#define mmDC_PERFMON13_PERFMON_CNTL_BASE_IDX 2
+-#define mmDC_PERFMON13_PERFMON_CNTL2 0x0030
+-#define mmDC_PERFMON13_PERFMON_CNTL2_BASE_IDX 2
+-#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0x0031
+-#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+-#define mmDC_PERFMON13_PERFMON_CVALUE_LOW 0x0032
+-#define mmDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX 2
+-#define mmDC_PERFMON13_PERFMON_HI 0x0033
+-#define mmDC_PERFMON13_PERFMON_HI_BASE_IDX 2
+-#define mmDC_PERFMON13_PERFMON_LOW 0x0034
+-#define mmDC_PERFMON13_PERFMON_LOW_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dc_displaypllregs_dispdec
+-// base address: 0x0
+-#define mmPPLL_VREG_CFG 0x0038
+-#define mmPPLL_VREG_CFG_BASE_IDX 2
+-#define mmPPLL_MODE_CNTL 0x0039
+-#define mmPPLL_MODE_CNTL_BASE_IDX 2
+-#define mmPPLL_FREQ_CTRL0 0x003a
+-#define mmPPLL_FREQ_CTRL0_BASE_IDX 2
+-#define mmPPLL_FREQ_CTRL1 0x003b
+-#define mmPPLL_FREQ_CTRL1_BASE_IDX 2
+-#define mmPPLL_FREQ_CTRL2 0x003c
+-#define mmPPLL_FREQ_CTRL2_BASE_IDX 2
+-#define mmPPLL_FREQ_CTRL3 0x003d
+-#define mmPPLL_FREQ_CTRL3_BASE_IDX 2
+-#define mmPPLL_BW_CTRL_COARSE 0x003e
+-#define mmPPLL_BW_CTRL_COARSE_BASE_IDX 2
+-#define mmPPLL_BW_CTRL_FINE 0x0040
+-#define mmPPLL_BW_CTRL_FINE_BASE_IDX 2
+-#define mmPPLL_CAL_CTRL 0x0041
+-#define mmPPLL_CAL_CTRL_BASE_IDX 2
+-#define mmPPLL_LOOP_CTRL 0x0042
+-#define mmPPLL_LOOP_CTRL_BASE_IDX 2
+-#define mmPPLL_REFCLK_CNTL 0x0050
+-#define mmPPLL_REFCLK_CNTL_BASE_IDX 2
+-#define mmPPLL_CLKOUT_CNTL 0x0051
+-#define mmPPLL_CLKOUT_CNTL_BASE_IDX 2
+-#define mmPPLL_DFT_CNTL 0x0052
+-#define mmPPLL_DFT_CNTL_BASE_IDX 2
+-#define mmPPLL_ANALOG_CNTL 0x0053
+-#define mmPPLL_ANALOG_CNTL_BASE_IDX 2
+-#define mmPPLL_POSTDIV 0x0054
+-#define mmPPLL_POSTDIV_BASE_IDX 2
+-#define mmPPLL_OBSERVE0 0x0059
+-#define mmPPLL_OBSERVE0_BASE_IDX 2
+-#define mmPPLL_OBSERVE1 0x005a
+-#define mmPPLL_OBSERVE1_BASE_IDX 2
+-#define mmPPLL_UPDATE_CNTL 0x005c
+-#define mmPPLL_UPDATE_CNTL_BASE_IDX 2
+-#define mmPPLL_OBSERVE0_OUT 0x005d
+-#define mmPPLL_OBSERVE0_OUT_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dccg_pll0_dispdec
+-// base address: 0x0
+-#define mmPLL_MACRO_CNTL_RESERVED0 0x0038
+-#define mmPLL_MACRO_CNTL_RESERVED0_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED1 0x0039
+-#define mmPLL_MACRO_CNTL_RESERVED1_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED2 0x003a
+-#define mmPLL_MACRO_CNTL_RESERVED2_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED3 0x003b
+-#define mmPLL_MACRO_CNTL_RESERVED3_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED4 0x003c
+-#define mmPLL_MACRO_CNTL_RESERVED4_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED5 0x003d
+-#define mmPLL_MACRO_CNTL_RESERVED5_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED6 0x003e
+-#define mmPLL_MACRO_CNTL_RESERVED6_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED7 0x003f
+-#define mmPLL_MACRO_CNTL_RESERVED7_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED8 0x0040
+-#define mmPLL_MACRO_CNTL_RESERVED8_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED9 0x0041
+-#define mmPLL_MACRO_CNTL_RESERVED9_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED10 0x0042
+-#define mmPLL_MACRO_CNTL_RESERVED10_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED11 0x0043
+-#define mmPLL_MACRO_CNTL_RESERVED11_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED12 0x0044
+-#define mmPLL_MACRO_CNTL_RESERVED12_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED13 0x0045
+-#define mmPLL_MACRO_CNTL_RESERVED13_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED14 0x0046
+-#define mmPLL_MACRO_CNTL_RESERVED14_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED15 0x0047
+-#define mmPLL_MACRO_CNTL_RESERVED15_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED16 0x0048
+-#define mmPLL_MACRO_CNTL_RESERVED16_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED17 0x0049
+-#define mmPLL_MACRO_CNTL_RESERVED17_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED18 0x004a
+-#define mmPLL_MACRO_CNTL_RESERVED18_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED19 0x004b
+-#define mmPLL_MACRO_CNTL_RESERVED19_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED20 0x004c
+-#define mmPLL_MACRO_CNTL_RESERVED20_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED21 0x004d
+-#define mmPLL_MACRO_CNTL_RESERVED21_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED22 0x004e
+-#define mmPLL_MACRO_CNTL_RESERVED22_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED23 0x004f
+-#define mmPLL_MACRO_CNTL_RESERVED23_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED24 0x0050
+-#define mmPLL_MACRO_CNTL_RESERVED24_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED25 0x0051
+-#define mmPLL_MACRO_CNTL_RESERVED25_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED26 0x0052
+-#define mmPLL_MACRO_CNTL_RESERVED26_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED27 0x0053
+-#define mmPLL_MACRO_CNTL_RESERVED27_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED28 0x0054
+-#define mmPLL_MACRO_CNTL_RESERVED28_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED29 0x0055
+-#define mmPLL_MACRO_CNTL_RESERVED29_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED30 0x0056
+-#define mmPLL_MACRO_CNTL_RESERVED30_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED31 0x0057
+-#define mmPLL_MACRO_CNTL_RESERVED31_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED32 0x0058
+-#define mmPLL_MACRO_CNTL_RESERVED32_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED33 0x0059
+-#define mmPLL_MACRO_CNTL_RESERVED33_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED34 0x005a
+-#define mmPLL_MACRO_CNTL_RESERVED34_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED35 0x005b
+-#define mmPLL_MACRO_CNTL_RESERVED35_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED36 0x005c
+-#define mmPLL_MACRO_CNTL_RESERVED36_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED37 0x005d
+-#define mmPLL_MACRO_CNTL_RESERVED37_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED38 0x005e
+-#define mmPLL_MACRO_CNTL_RESERVED38_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED39 0x005f
+-#define mmPLL_MACRO_CNTL_RESERVED39_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED40 0x0060
+-#define mmPLL_MACRO_CNTL_RESERVED40_BASE_IDX 2
+-#define mmPLL_MACRO_CNTL_RESERVED41 0x0061
+-#define mmPLL_MACRO_CNTL_RESERVED41_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dc_perfmon1_dispdec
+-// base address: 0x598
+-#define mmDC_PERFMON1_PERFCOUNTER_CNTL 0x0186
+-#define mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2
+-#define mmDC_PERFMON1_PERFCOUNTER_CNTL2 0x0187
+-#define mmDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX 2
+-#define mmDC_PERFMON1_PERFCOUNTER_STATE 0x0188
+-#define mmDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX 2
+-#define mmDC_PERFMON1_PERFMON_CNTL 0x0189
+-#define mmDC_PERFMON1_PERFMON_CNTL_BASE_IDX 2
+-#define mmDC_PERFMON1_PERFMON_CNTL2 0x018a
+-#define mmDC_PERFMON1_PERFMON_CNTL2_BASE_IDX 2
+-#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x018b
+-#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+-#define mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x018c
+-#define mmDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX 2
+-#define mmDC_PERFMON1_PERFMON_HI 0x018d
+-#define mmDC_PERFMON1_PERFMON_HI_BASE_IDX 2
+-#define mmDC_PERFMON1_PERFMON_LOW 0x018e
+-#define mmDC_PERFMON1_PERFMON_LOW_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_mcif_wb0_dispdec
+-// base address: 0x0
+-#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL 0x0272
+-#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2
+-#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R 0x0273
+-#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2
+-#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS 0x0274
+-#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2
+-#define mmMCIF_WB0_MCIF_WB_BUF_PITCH 0x0275
+-#define mmMCIF_WB0_MCIF_WB_BUF_PITCH_BASE_IDX 2
+-#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS 0x0276
+-#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS_BASE_IDX 2
+-#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2 0x0277
+-#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2
+-#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS 0x0278
+-#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS_BASE_IDX 2
+-#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2 0x0279
+-#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2
+-#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS 0x027a
+-#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS_BASE_IDX 2
+-#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2 0x027b
+-#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2
+-#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS 0x027c
+-#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS_BASE_IDX 2
+-#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2 0x027d
+-#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2
+-#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL 0x027e
+-#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2
+-#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE 0x027f
+-#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE_BASE_IDX 2
+-#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y 0x0282
+-#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2
+-#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x0283
+-#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2
+-#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C 0x0284
+-#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2
+-#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x0285
+-#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2
+-#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y 0x0286
+-#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2
+-#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x0287
+-#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2
+-#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C 0x0288
+-#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2
+-#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x0289
+-#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2
+-#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y 0x028a
+-#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2
+-#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x028b
+-#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2
+-#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C 0x028c
+-#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2
+-#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x028d
+-#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2
+-#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y 0x028e
+-#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2
+-#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x028f
+-#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2
+-#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C 0x0290
+-#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2
+-#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x0291
+-#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2
+-#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL 0x0292
+-#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2
+-#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x0293
+-#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2
+-#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL 0x0294
+-#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2
+-#define mmMCIF_WB0_MCIF_WB_WATERMARK 0x0295
+-#define mmMCIF_WB0_MCIF_WB_WATERMARK_BASE_IDX 2
+-#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL 0x0296
+-#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2
+-#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL 0x0297
+-#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2
+-#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL 0x0298
+-#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2
+-#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL 0x0299
+-#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2
+-#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE 0x029b
+-#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2
+-#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE 0x029c
+-#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_mcif_wb1_dispdec
+-// base address: 0x100
+-#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL 0x02b2
+-#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2
+-#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R 0x02b3
+-#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2
+-#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS 0x02b4
+-#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2
+-#define mmMCIF_WB1_MCIF_WB_BUF_PITCH 0x02b5
+-#define mmMCIF_WB1_MCIF_WB_BUF_PITCH_BASE_IDX 2
+-#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS 0x02b6
+-#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS_BASE_IDX 2
+-#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2 0x02b7
+-#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2
+-#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS 0x02b8
+-#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS_BASE_IDX 2
+-#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2 0x02b9
+-#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2
+-#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS 0x02ba
+-#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS_BASE_IDX 2
+-#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2 0x02bb
+-#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2
+-#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS 0x02bc
+-#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS_BASE_IDX 2
+-#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2 0x02bd
+-#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2
+-#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL 0x02be
+-#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2
+-#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE 0x02bf
+-#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE_BASE_IDX 2
+-#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y 0x02c2
+-#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2
+-#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x02c3
+-#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2
+-#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C 0x02c4
+-#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2
+-#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x02c5
+-#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2
+-#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y 0x02c6
+-#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2
+-#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x02c7
+-#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2
+-#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C 0x02c8
+-#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2
+-#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x02c9
+-#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2
+-#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y 0x02ca
+-#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2
+-#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x02cb
+-#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2
+-#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C 0x02cc
+-#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2
+-#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x02cd
+-#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2
+-#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y 0x02ce
+-#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2
+-#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x02cf
+-#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2
+-#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C 0x02d0
+-#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2
+-#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x02d1
+-#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2
+-#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL 0x02d2
+-#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2
+-#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02d3
+-#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2
+-#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL 0x02d4
+-#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2
+-#define mmMCIF_WB1_MCIF_WB_WATERMARK 0x02d5
+-#define mmMCIF_WB1_MCIF_WB_WATERMARK_BASE_IDX 2
+-#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL 0x02d6
+-#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2
+-#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL 0x02d7
+-#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2
+-#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL 0x02d8
+-#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2
+-#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL 0x02d9
+-#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2
+-#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE 0x02db
+-#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2
+-#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE 0x02dc
+-#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_mcif_wb2_dispdec
+-// base address: 0x200
+-#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL 0x02f2
+-#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2
+-#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R 0x02f3
+-#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2
+-#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS 0x02f4
+-#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2
+-#define mmMCIF_WB2_MCIF_WB_BUF_PITCH 0x02f5
+-#define mmMCIF_WB2_MCIF_WB_BUF_PITCH_BASE_IDX 2
+-#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS 0x02f6
+-#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS_BASE_IDX 2
+-#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2 0x02f7
+-#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2
+-#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS 0x02f8
+-#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS_BASE_IDX 2
+-#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2 0x02f9
+-#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2
+-#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS 0x02fa
+-#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS_BASE_IDX 2
+-#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2 0x02fb
+-#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2
+-#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS 0x02fc
+-#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS_BASE_IDX 2
+-#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2 0x02fd
+-#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2
+-#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL 0x02fe
+-#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2
+-#define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE 0x02ff
+-#define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE_BASE_IDX 2
+-#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y 0x0302
+-#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2
+-#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x0303
+-#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2
+-#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C 0x0304
+-#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2
+-#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x0305
+-#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2
+-#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y 0x0306
+-#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2
+-#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x0307
+-#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2
+-#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C 0x0308
+-#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2
+-#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x0309
+-#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2
+-#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y 0x030a
+-#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2
+-#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x030b
+-#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2
+-#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C 0x030c
+-#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2
+-#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x030d
+-#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2
+-#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y 0x030e
+-#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2
+-#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x030f
+-#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2
+-#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C 0x0310
+-#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2
+-#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x0311
+-#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2
+-#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL 0x0312
+-#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2
+-#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x0313
+-#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2
+-#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL 0x0314
+-#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2
+-#define mmMCIF_WB2_MCIF_WB_WATERMARK 0x0315
+-#define mmMCIF_WB2_MCIF_WB_WATERMARK_BASE_IDX 2
+-#define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL 0x0316
+-#define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2
+-#define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL 0x0317
+-#define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2
+-#define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL 0x0318
+-#define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2
+-#define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL 0x0319
+-#define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2
+-#define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE 0x031b
+-#define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2
+-#define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE 0x031c
+-#define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_cwb0_dispdec
+-// base address: 0x0
+-#define mmCWB0_CWB_CTRL 0x0332
+-#define mmCWB0_CWB_CTRL_BASE_IDX 2
+-#define mmCWB0_CWB_FENCE_PAR0 0x0334
+-#define mmCWB0_CWB_FENCE_PAR0_BASE_IDX 2
+-#define mmCWB0_CWB_FENCE_PAR1 0x0335
+-#define mmCWB0_CWB_FENCE_PAR1_BASE_IDX 2
+-#define mmCWB0_CWB_CRC_CTRL 0x0339
+-#define mmCWB0_CWB_CRC_CTRL_BASE_IDX 2
+-#define mmCWB0_CWB_CRC_RED_GREEN_MASK 0x033a
+-#define mmCWB0_CWB_CRC_RED_GREEN_MASK_BASE_IDX 2
+-#define mmCWB0_CWB_CRC_BLUE_MASK 0x033b
+-#define mmCWB0_CWB_CRC_BLUE_MASK_BASE_IDX 2
+-#define mmCWB0_CWB_CRC_RED_GREEN_RESULT 0x033c
+-#define mmCWB0_CWB_CRC_RED_GREEN_RESULT_BASE_IDX 2
+-#define mmCWB0_CWB_CRC_BLUE_RESULT 0x033d
+-#define mmCWB0_CWB_CRC_BLUE_RESULT_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_cwb1_dispdec
+-// base address: 0x60
+-#define mmCWB1_CWB_CTRL 0x034a
+-#define mmCWB1_CWB_CTRL_BASE_IDX 2
+-#define mmCWB1_CWB_FENCE_PAR0 0x034c
+-#define mmCWB1_CWB_FENCE_PAR0_BASE_IDX 2
+-#define mmCWB1_CWB_FENCE_PAR1 0x034d
+-#define mmCWB1_CWB_FENCE_PAR1_BASE_IDX 2
+-#define mmCWB1_CWB_CRC_CTRL 0x0351
+-#define mmCWB1_CWB_CRC_CTRL_BASE_IDX 2
+-#define mmCWB1_CWB_CRC_RED_GREEN_MASK 0x0352
+-#define mmCWB1_CWB_CRC_RED_GREEN_MASK_BASE_IDX 2
+-#define mmCWB1_CWB_CRC_BLUE_MASK 0x0353
+-#define mmCWB1_CWB_CRC_BLUE_MASK_BASE_IDX 2
+-#define mmCWB1_CWB_CRC_RED_GREEN_RESULT 0x0354
+-#define mmCWB1_CWB_CRC_RED_GREEN_RESULT_BASE_IDX 2
+-#define mmCWB1_CWB_CRC_BLUE_RESULT 0x0355
+-#define mmCWB1_CWB_CRC_BLUE_RESULT_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dc_perfmon9_dispdec
+-// base address: 0xd08
+-#define mmDC_PERFMON9_PERFCOUNTER_CNTL 0x0362
+-#define mmDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX 2
+-#define mmDC_PERFMON9_PERFCOUNTER_CNTL2 0x0363
+-#define mmDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX 2
+-#define mmDC_PERFMON9_PERFCOUNTER_STATE 0x0364
+-#define mmDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX 2
+-#define mmDC_PERFMON9_PERFMON_CNTL 0x0365
+-#define mmDC_PERFMON9_PERFMON_CNTL_BASE_IDX 2
+-#define mmDC_PERFMON9_PERFMON_CNTL2 0x0366
+-#define mmDC_PERFMON9_PERFMON_CNTL2_BASE_IDX 2
+-#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x0367
+-#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+-#define mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x0368
+-#define mmDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX 2
+-#define mmDC_PERFMON9_PERFMON_HI 0x0369
+-#define mmDC_PERFMON9_PERFMON_HI_BASE_IDX 2
+-#define mmDC_PERFMON9_PERFMON_LOW 0x036a
+-#define mmDC_PERFMON9_PERFMON_LOW_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dispdec
+-// base address: 0x0
+-#define mmVGA_MEM_WRITE_PAGE_ADDR 0x0000
+-#define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
+-#define mmVGA_MEM_READ_PAGE_ADDR 0x0001
+-#define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
+-#define mmVGA_RENDER_CONTROL 0x0000
+-#define mmVGA_RENDER_CONTROL_BASE_IDX 1
+-#define mmVGA_SEQUENCER_RESET_CONTROL 0x0001
+-#define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX 1
+-#define mmVGA_MODE_CONTROL 0x0002
+-#define mmVGA_MODE_CONTROL_BASE_IDX 1
+-#define mmVGA_SURFACE_PITCH_SELECT 0x0003
+-#define mmVGA_SURFACE_PITCH_SELECT_BASE_IDX 1
+-#define mmVGA_MEMORY_BASE_ADDRESS 0x0004
+-#define mmVGA_MEMORY_BASE_ADDRESS_BASE_IDX 1
+-#define mmVGA_DISPBUF1_SURFACE_ADDR 0x0006
+-#define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX 1
+-#define mmVGA_DISPBUF2_SURFACE_ADDR 0x0008
+-#define mmVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX 1
+-#define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0x0009
+-#define mmVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX 1
+-#define mmVGA_HDP_CONTROL 0x000a
+-#define mmVGA_HDP_CONTROL_BASE_IDX 1
+-#define mmVGA_CACHE_CONTROL 0x000b
+-#define mmVGA_CACHE_CONTROL_BASE_IDX 1
+-#define mmD1VGA_CONTROL 0x000c
+-#define mmD1VGA_CONTROL_BASE_IDX 1
+-#define mmD2VGA_CONTROL 0x000e
+-#define mmD2VGA_CONTROL_BASE_IDX 1
+-#define mmVGA_STATUS 0x0010
+-#define mmVGA_STATUS_BASE_IDX 1
+-#define mmVGA_INTERRUPT_CONTROL 0x0011
+-#define mmVGA_INTERRUPT_CONTROL_BASE_IDX 1
+-#define mmVGA_STATUS_CLEAR 0x0012
+-#define mmVGA_STATUS_CLEAR_BASE_IDX 1
+-#define mmVGA_INTERRUPT_STATUS 0x0013
+-#define mmVGA_INTERRUPT_STATUS_BASE_IDX 1
+-#define mmVGA_MAIN_CONTROL 0x0014
+-#define mmVGA_MAIN_CONTROL_BASE_IDX 1
+-#define mmVGA_TEST_CONTROL 0x0015
+-#define mmVGA_TEST_CONTROL_BASE_IDX 1
+-#define mmVGA_QOS_CTRL 0x0018
+-#define mmVGA_QOS_CTRL_BASE_IDX 1
+-#define mmCRTC8_IDX 0x002d
+-#define mmCRTC8_IDX_BASE_IDX 1
+-#define mmCRTC8_DATA 0x002d
+-#define mmCRTC8_DATA_BASE_IDX 1
+-#define mmGENFC_WT 0x002e
+-#define mmGENFC_WT_BASE_IDX 1
+-#define mmGENS1 0x002e
+-#define mmGENS1_BASE_IDX 1
+-#define mmATTRDW 0x0030
+-#define mmATTRDW_BASE_IDX 1
+-#define mmATTRX 0x0030
+-#define mmATTRX_BASE_IDX 1
+-#define mmATTRDR 0x0030
+-#define mmATTRDR_BASE_IDX 1
+-#define mmGENMO_WT 0x0030
+-#define mmGENMO_WT_BASE_IDX 1
+-#define mmGENS0 0x0030
+-#define mmGENS0_BASE_IDX 1
+-#define mmGENENB 0x0030
+-#define mmGENENB_BASE_IDX 1
+-#define mmSEQ8_IDX 0x0031
+-#define mmSEQ8_IDX_BASE_IDX 1
+-#define mmSEQ8_DATA 0x0031
+-#define mmSEQ8_DATA_BASE_IDX 1
+-#define mmDAC_MASK 0x0031
+-#define mmDAC_MASK_BASE_IDX 1
+-#define mmDAC_R_INDEX 0x0031
+-#define mmDAC_R_INDEX_BASE_IDX 1
+-#define mmDAC_W_INDEX 0x0032
+-#define mmDAC_W_INDEX_BASE_IDX 1
+-#define mmDAC_DATA 0x0032
+-#define mmDAC_DATA_BASE_IDX 1
+-#define mmGENFC_RD 0x0032
+-#define mmGENFC_RD_BASE_IDX 1
+-#define mmGENMO_RD 0x0033
+-#define mmGENMO_RD_BASE_IDX 1
+-#define mmGRPH8_IDX 0x0033
+-#define mmGRPH8_IDX_BASE_IDX 1
+-#define mmGRPH8_DATA 0x0033
+-#define mmGRPH8_DATA_BASE_IDX 1
+-#define mmCRTC8_IDX_1 0x0035
+-#define mmCRTC8_IDX_1_BASE_IDX 1
+-#define mmCRTC8_DATA_1 0x0035
+-#define mmCRTC8_DATA_1_BASE_IDX 1
+-#define mmGENFC_WT_1 0x0036
+-#define mmGENFC_WT_1_BASE_IDX 1
+-#define mmGENS1_1 0x0036
+-#define mmGENS1_1_BASE_IDX 1
+-#define mmD3VGA_CONTROL 0x0038
+-#define mmD3VGA_CONTROL_BASE_IDX 1
+-#define mmD4VGA_CONTROL 0x0039
+-#define mmD4VGA_CONTROL_BASE_IDX 1
+-#define mmD5VGA_CONTROL 0x003a
+-#define mmD5VGA_CONTROL_BASE_IDX 1
+-#define mmD6VGA_CONTROL 0x003b
+-#define mmD6VGA_CONTROL_BASE_IDX 1
+-#define mmVGA_SOURCE_SELECT 0x003c
+-#define mmVGA_SOURCE_SELECT_BASE_IDX 1
+-#define mmPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
+-#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1
+-#define mmPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
+-#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1
+-#define mmPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042
+-#define mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1
+-#define mmPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043
+-#define mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1
+-#define mmDCFEV0_CRTC_PIXEL_RATE_CNTL 0x0044
+-#define mmDCFEV0_CRTC_PIXEL_RATE_CNTL_BASE_IDX 1
+-#define mmDCFEV1_CRTC_PIXEL_RATE_CNTL 0x0045
+-#define mmDCFEV1_CRTC_PIXEL_RATE_CNTL_BASE_IDX 1
+-#define mmSYMCLKLPA_CLOCK_ENABLE 0x0046
+-#define mmSYMCLKLPA_CLOCK_ENABLE_BASE_IDX 1
+-#define mmSYMCLKLPB_CLOCK_ENABLE 0x0047
+-#define mmSYMCLKLPB_CLOCK_ENABLE_BASE_IDX 1
+-#define mmDPREFCLK_CGTT_BLK_CTRL_REG 0x0048
+-#define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
+-#define mmREFCLK_CNTL 0x0049
+-#define mmREFCLK_CNTL_BASE_IDX 1
+-#define mmMIPI_CLK_CNTL 0x004a
+-#define mmMIPI_CLK_CNTL_BASE_IDX 1
+-#define mmREFCLK_CGTT_BLK_CTRL_REG 0x004b
+-#define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
+-#define mmPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c
+-#define mmPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1
+-#define mmDCCG_PERFMON_CNTL2 0x004e
+-#define mmDCCG_PERFMON_CNTL2_BASE_IDX 1
+-#define mmDSICLK_CGTT_BLK_CTRL_REG 0x004f
+-#define mmDSICLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
+-#define mmDCCG_CBUS_WRCMD_DELAY 0x0050
+-#define mmDCCG_CBUS_WRCMD_DELAY_BASE_IDX 1
+-#define mmDCCG_DS_DTO_INCR 0x0053
+-#define mmDCCG_DS_DTO_INCR_BASE_IDX 1
+-#define mmDCCG_DS_DTO_MODULO 0x0054
+-#define mmDCCG_DS_DTO_MODULO_BASE_IDX 1
+-#define mmDCCG_DS_CNTL 0x0055
+-#define mmDCCG_DS_CNTL_BASE_IDX 1
+-#define mmDCCG_DS_HW_CAL_INTERVAL 0x0056
+-#define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1
+-#define mmSYMCLKG_CLOCK_ENABLE 0x0057
+-#define mmSYMCLKG_CLOCK_ENABLE_BASE_IDX 1
+-#define mmDPREFCLK_CNTL 0x0058
+-#define mmDPREFCLK_CNTL_BASE_IDX 1
+-#define mmAOMCLK0_CNTL 0x0059
+-#define mmAOMCLK0_CNTL_BASE_IDX 1
+-#define mmAOMCLK1_CNTL 0x005a
+-#define mmAOMCLK1_CNTL_BASE_IDX 1
+-#define mmAOMCLK2_CNTL 0x005b
+-#define mmAOMCLK2_CNTL_BASE_IDX 1
+-#define mmDCCG_AUDIO_DTO2_PHASE 0x005c
+-#define mmDCCG_AUDIO_DTO2_PHASE_BASE_IDX 1
+-#define mmDCCG_AUDIO_DTO2_MODULO 0x005d
+-#define mmDCCG_AUDIO_DTO2_MODULO_BASE_IDX 1
+-#define mmDCE_VERSION 0x005e
+-#define mmDCE_VERSION_BASE_IDX 1
+-#define mmPHYPLLG_PIXCLK_RESYNC_CNTL 0x005f
+-#define mmPHYPLLG_PIXCLK_RESYNC_CNTL_BASE_IDX 1
+-#define mmDCCG_GTC_CNTL 0x0060
+-#define mmDCCG_GTC_CNTL_BASE_IDX 1
+-#define mmDCCG_GTC_DTO_INCR 0x0061
+-#define mmDCCG_GTC_DTO_INCR_BASE_IDX 1
+-#define mmDCCG_GTC_DTO_MODULO 0x0062
+-#define mmDCCG_GTC_DTO_MODULO_BASE_IDX 1
+-#define mmDCCG_GTC_CURRENT 0x0063
+-#define mmDCCG_GTC_CURRENT_BASE_IDX 1
+-#define mmDENTIST_DISPCLK_CNTL 0x0064
+-#define mmDENTIST_DISPCLK_CNTL_BASE_IDX 1
+-#define mmMIPI_DTO_CNTL 0x0065
+-#define mmMIPI_DTO_CNTL_BASE_IDX 1
+-#define mmMIPI_DTO_PHASE 0x0066
+-#define mmMIPI_DTO_PHASE_BASE_IDX 1
+-#define mmMIPI_DTO_MODULO 0x0067
+-#define mmMIPI_DTO_MODULO_BASE_IDX 1
+-#define mmDAC_CLK_ENABLE 0x0068
+-#define mmDAC_CLK_ENABLE_BASE_IDX 1
+-#define mmDVO_CLK_ENABLE 0x0069
+-#define mmDVO_CLK_ENABLE_BASE_IDX 1
+-#define mmAVSYNC_COUNTER_WRITE 0x006a
+-#define mmAVSYNC_COUNTER_WRITE_BASE_IDX 1
+-#define mmAVSYNC_COUNTER_CONTROL 0x006b
+-#define mmAVSYNC_COUNTER_CONTROL_BASE_IDX 1
+-#define mmDMCU_SMU_INTERRUPT_CNTL 0x006c
+-#define mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX 1
+-#define mmSMU_CONTROL 0x006d
+-#define mmSMU_CONTROL_BASE_IDX 1
+-#define mmSMU_INTERRUPT_CONTROL 0x006e
+-#define mmSMU_INTERRUPT_CONTROL_BASE_IDX 1
+-#define mmAVSYNC_COUNTER_READ 0x006f
+-#define mmAVSYNC_COUNTER_READ_BASE_IDX 1
+-#define mmMILLISECOND_TIME_BASE_DIV 0x0070
+-#define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX 1
+-#define mmDISPCLK_FREQ_CHANGE_CNTL 0x0071
+-#define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1
+-#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072
+-#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1
+-#define mmDCCG_PERFMON_CNTL 0x0073
+-#define mmDCCG_PERFMON_CNTL_BASE_IDX 1
+-#define mmDCCG_GATE_DISABLE_CNTL 0x0074
+-#define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX 1
+-#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x0075
+-#define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
+-#define mmSCLK_CGTT_BLK_CTRL_REG 0x0076
+-#define mmSCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
+-#define mmDCCG_CAC_STATUS 0x0077
+-#define mmDCCG_CAC_STATUS_BASE_IDX 1
+-#define mmPIXCLK1_RESYNC_CNTL 0x0078
+-#define mmPIXCLK1_RESYNC_CNTL_BASE_IDX 1
+-#define mmPIXCLK2_RESYNC_CNTL 0x0079
+-#define mmPIXCLK2_RESYNC_CNTL_BASE_IDX 1
+-#define mmPIXCLK0_RESYNC_CNTL 0x007a
+-#define mmPIXCLK0_RESYNC_CNTL_BASE_IDX 1
+-#define mmMICROSECOND_TIME_BASE_DIV 0x007b
+-#define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX 1
+-#define mmDCCG_GATE_DISABLE_CNTL2 0x007c
+-#define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1
+-#define mmSYMCLK_CGTT_BLK_CTRL_REG 0x007d
+-#define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
+-#define mmPHYPLLF_PIXCLK_RESYNC_CNTL 0x007e
+-#define mmPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX 1
+-#define mmDCCG_DISP_CNTL_REG 0x007f
+-#define mmDCCG_DISP_CNTL_REG_BASE_IDX 1
+-#define mmCRTC0_PIXEL_RATE_CNTL 0x0080
+-#define mmCRTC0_PIXEL_RATE_CNTL_BASE_IDX 1
+-#define mmDP_DTO0_PHASE 0x0081
+-#define mmDP_DTO0_PHASE_BASE_IDX 1
+-#define mmDP_DTO0_MODULO 0x0082
+-#define mmDP_DTO0_MODULO_BASE_IDX 1
+-#define mmCRTC0_PHYPLL_PIXEL_RATE_CNTL 0x0083
+-#define mmCRTC0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
+-#define mmCRTC1_PIXEL_RATE_CNTL 0x0084
+-#define mmCRTC1_PIXEL_RATE_CNTL_BASE_IDX 1
+-#define mmDP_DTO1_PHASE 0x0085
+-#define mmDP_DTO1_PHASE_BASE_IDX 1
+-#define mmDP_DTO1_MODULO 0x0086
+-#define mmDP_DTO1_MODULO_BASE_IDX 1
+-#define mmCRTC1_PHYPLL_PIXEL_RATE_CNTL 0x0087
+-#define mmCRTC1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
+-#define mmCRTC2_PIXEL_RATE_CNTL 0x0088
+-#define mmCRTC2_PIXEL_RATE_CNTL_BASE_IDX 1
+-#define mmDP_DTO2_PHASE 0x0089
+-#define mmDP_DTO2_PHASE_BASE_IDX 1
+-#define mmDP_DTO2_MODULO 0x008a
+-#define mmDP_DTO2_MODULO_BASE_IDX 1
+-#define mmCRTC2_PHYPLL_PIXEL_RATE_CNTL 0x008b
+-#define mmCRTC2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
+-#define mmCRTC3_PIXEL_RATE_CNTL 0x008c
+-#define mmCRTC3_PIXEL_RATE_CNTL_BASE_IDX 1
+-#define mmDP_DTO3_PHASE 0x008d
+-#define mmDP_DTO3_PHASE_BASE_IDX 1
+-#define mmDP_DTO3_MODULO 0x008e
+-#define mmDP_DTO3_MODULO_BASE_IDX 1
+-#define mmCRTC3_PHYPLL_PIXEL_RATE_CNTL 0x008f
+-#define mmCRTC3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
+-#define mmCRTC4_PIXEL_RATE_CNTL 0x0090
+-#define mmCRTC4_PIXEL_RATE_CNTL_BASE_IDX 1
+-#define mmDP_DTO4_PHASE 0x0091
+-#define mmDP_DTO4_PHASE_BASE_IDX 1
+-#define mmDP_DTO4_MODULO 0x0092
+-#define mmDP_DTO4_MODULO_BASE_IDX 1
+-#define mmCRTC4_PHYPLL_PIXEL_RATE_CNTL 0x0093
+-#define mmCRTC4_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
+-#define mmCRTC5_PIXEL_RATE_CNTL 0x0094
+-#define mmCRTC5_PIXEL_RATE_CNTL_BASE_IDX 1
+-#define mmDP_DTO5_PHASE 0x0095
+-#define mmDP_DTO5_PHASE_BASE_IDX 1
+-#define mmDP_DTO5_MODULO 0x0096
+-#define mmDP_DTO5_MODULO_BASE_IDX 1
+-#define mmCRTC5_PHYPLL_PIXEL_RATE_CNTL 0x0097
+-#define mmCRTC5_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
+-#define mmDCCG_SOFT_RESET 0x009f
+-#define mmDCCG_SOFT_RESET_BASE_IDX 1
+-#define mmSYMCLKA_CLOCK_ENABLE 0x00a0
+-#define mmSYMCLKA_CLOCK_ENABLE_BASE_IDX 1
+-#define mmSYMCLKB_CLOCK_ENABLE 0x00a1
+-#define mmSYMCLKB_CLOCK_ENABLE_BASE_IDX 1
+-#define mmSYMCLKC_CLOCK_ENABLE 0x00a2
+-#define mmSYMCLKC_CLOCK_ENABLE_BASE_IDX 1
+-#define mmSYMCLKD_CLOCK_ENABLE 0x00a3
+-#define mmSYMCLKD_CLOCK_ENABLE_BASE_IDX 1
+-#define mmSYMCLKE_CLOCK_ENABLE 0x00a4
+-#define mmSYMCLKE_CLOCK_ENABLE_BASE_IDX 1
+-#define mmSYMCLKF_CLOCK_ENABLE 0x00a5
+-#define mmSYMCLKF_CLOCK_ENABLE_BASE_IDX 1
+-#define mmDVOACLKD_CNTL 0x00a8
+-#define mmDVOACLKD_CNTL_BASE_IDX 1
+-#define mmDVOACLKC_MVP_CNTL 0x00a9
+-#define mmDVOACLKC_MVP_CNTL_BASE_IDX 1
+-#define mmDVOACLKC_CNTL 0x00aa
+-#define mmDVOACLKC_CNTL_BASE_IDX 1
+-#define mmDCCG_AUDIO_DTO_SOURCE 0x00ab
+-#define mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1
+-#define mmDCCG_AUDIO_DTO0_PHASE 0x00ac
+-#define mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1
+-#define mmDCCG_AUDIO_DTO0_MODULE 0x00ad
+-#define mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1
+-#define mmDCCG_AUDIO_DTO1_PHASE 0x00ae
+-#define mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1
+-#define mmDCCG_AUDIO_DTO1_MODULE 0x00af
+-#define mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1
+-#define mmDCCG_TEST_CLK_SEL 0x00be
+-#define mmDCCG_TEST_CLK_SEL_BASE_IDX 1
+-#define mmFBC_CNTL 0x0062
+-#define mmFBC_CNTL_BASE_IDX 2
+-#define mmFBC_IDLE_FORCE_CLEAR_MASK 0x0064
+-#define mmFBC_IDLE_FORCE_CLEAR_MASK_BASE_IDX 2
+-#define mmFBC_START_STOP_DELAY 0x0065
+-#define mmFBC_START_STOP_DELAY_BASE_IDX 2
+-#define mmFBC_COMP_CNTL 0x0066
+-#define mmFBC_COMP_CNTL_BASE_IDX 2
+-#define mmFBC_COMP_MODE 0x0067
+-#define mmFBC_COMP_MODE_BASE_IDX 2
+-#define mmFBC_IND_LUT0 0x006b
+-#define mmFBC_IND_LUT0_BASE_IDX 2
+-#define mmFBC_IND_LUT1 0x006c
+-#define mmFBC_IND_LUT1_BASE_IDX 2
+-#define mmFBC_IND_LUT2 0x006d
+-#define mmFBC_IND_LUT2_BASE_IDX 2
+-#define mmFBC_IND_LUT3 0x006e
+-#define mmFBC_IND_LUT3_BASE_IDX 2
+-#define mmFBC_IND_LUT4 0x006f
+-#define mmFBC_IND_LUT4_BASE_IDX 2
+-#define mmFBC_IND_LUT5 0x0070
+-#define mmFBC_IND_LUT5_BASE_IDX 2
+-#define mmFBC_IND_LUT6 0x0071
+-#define mmFBC_IND_LUT6_BASE_IDX 2
+-#define mmFBC_IND_LUT7 0x0072
+-#define mmFBC_IND_LUT7_BASE_IDX 2
+-#define mmFBC_IND_LUT8 0x0073
+-#define mmFBC_IND_LUT8_BASE_IDX 2
+-#define mmFBC_IND_LUT9 0x0074
+-#define mmFBC_IND_LUT9_BASE_IDX 2
+-#define mmFBC_IND_LUT10 0x0075
+-#define mmFBC_IND_LUT10_BASE_IDX 2
+-#define mmFBC_IND_LUT11 0x0076
+-#define mmFBC_IND_LUT11_BASE_IDX 2
+-#define mmFBC_IND_LUT12 0x0077
+-#define mmFBC_IND_LUT12_BASE_IDX 2
+-#define mmFBC_IND_LUT13 0x0078
+-#define mmFBC_IND_LUT13_BASE_IDX 2
+-#define mmFBC_IND_LUT14 0x0079
+-#define mmFBC_IND_LUT14_BASE_IDX 2
+-#define mmFBC_IND_LUT15 0x007a
+-#define mmFBC_IND_LUT15_BASE_IDX 2
+-#define mmFBC_CSM_REGION_OFFSET_01 0x007b
+-#define mmFBC_CSM_REGION_OFFSET_01_BASE_IDX 2
+-#define mmFBC_CSM_REGION_OFFSET_23 0x007c
+-#define mmFBC_CSM_REGION_OFFSET_23_BASE_IDX 2
+-#define mmFBC_CLIENT_REGION_MASK 0x007d
+-#define mmFBC_CLIENT_REGION_MASK_BASE_IDX 2
+-#define mmFBC_DEBUG_COMP 0x007e
+-#define mmFBC_DEBUG_COMP_BASE_IDX 2
+-#define mmFBC_MISC 0x0084
+-#define mmFBC_MISC_BASE_IDX 2
+-#define mmFBC_STATUS 0x0085
+-#define mmFBC_STATUS_BASE_IDX 2
+-#define mmFBC_ALPHA_CNTL 0x0088
+-#define mmFBC_ALPHA_CNTL_BASE_IDX 2
+-#define mmFBC_ALPHA_RGB_OVERRIDE 0x0089
+-#define mmFBC_ALPHA_RGB_OVERRIDE_BASE_IDX 2
+-#define mmPIPE0_PG_CONFIG 0x008e
+-#define mmPIPE0_PG_CONFIG_BASE_IDX 2
+-#define mmPIPE0_PG_ENABLE 0x008f
+-#define mmPIPE0_PG_ENABLE_BASE_IDX 2
+-#define mmPIPE0_PG_STATUS 0x0090
+-#define mmPIPE0_PG_STATUS_BASE_IDX 2
+-#define mmPIPE1_PG_CONFIG 0x0091
+-#define mmPIPE1_PG_CONFIG_BASE_IDX 2
+-#define mmPIPE1_PG_ENABLE 0x0092
+-#define mmPIPE1_PG_ENABLE_BASE_IDX 2
+-#define mmPIPE1_PG_STATUS 0x0093
+-#define mmPIPE1_PG_STATUS_BASE_IDX 2
+-#define mmPIPE2_PG_CONFIG 0x0094
+-#define mmPIPE2_PG_CONFIG_BASE_IDX 2
+-#define mmPIPE2_PG_ENABLE 0x0095
+-#define mmPIPE2_PG_ENABLE_BASE_IDX 2
+-#define mmPIPE2_PG_STATUS 0x0096
+-#define mmPIPE2_PG_STATUS_BASE_IDX 2
+-#define mmPIPE3_PG_CONFIG 0x0097
+-#define mmPIPE3_PG_CONFIG_BASE_IDX 2
+-#define mmPIPE3_PG_ENABLE 0x0098
+-#define mmPIPE3_PG_ENABLE_BASE_IDX 2
+-#define mmPIPE3_PG_STATUS 0x0099
+-#define mmPIPE3_PG_STATUS_BASE_IDX 2
+-#define mmPIPE4_PG_CONFIG 0x009a
+-#define mmPIPE4_PG_CONFIG_BASE_IDX 2
+-#define mmPIPE4_PG_ENABLE 0x009b
+-#define mmPIPE4_PG_ENABLE_BASE_IDX 2
+-#define mmPIPE4_PG_STATUS 0x009c
+-#define mmPIPE4_PG_STATUS_BASE_IDX 2
+-#define mmPIPE5_PG_CONFIG 0x009d
+-#define mmPIPE5_PG_CONFIG_BASE_IDX 2
+-#define mmPIPE5_PG_ENABLE 0x009e
+-#define mmPIPE5_PG_ENABLE_BASE_IDX 2
+-#define mmPIPE5_PG_STATUS 0x009f
+-#define mmPIPE5_PG_STATUS_BASE_IDX 2
+-#define mmDSI_PG_CONFIG 0x00a0
+-#define mmDSI_PG_CONFIG_BASE_IDX 2
+-#define mmDSI_PG_ENABLE 0x00a1
+-#define mmDSI_PG_ENABLE_BASE_IDX 2
+-#define mmDSI_PG_STATUS 0x00a2
+-#define mmDSI_PG_STATUS_BASE_IDX 2
+-#define mmDCFEV0_PG_CONFIG 0x00a3
+-#define mmDCFEV0_PG_CONFIG_BASE_IDX 2
+-#define mmDCFEV0_PG_ENABLE 0x00a4
+-#define mmDCFEV0_PG_ENABLE_BASE_IDX 2
+-#define mmDCFEV0_PG_STATUS 0x00a5
+-#define mmDCFEV0_PG_STATUS_BASE_IDX 2
+-#define mmDCPG_INTERRUPT_STATUS 0x00a6
+-#define mmDCPG_INTERRUPT_STATUS_BASE_IDX 2
+-#define mmDCPG_INTERRUPT_CONTROL 0x00a7
+-#define mmDCPG_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmDCPG_INTERRUPT_CONTROL2 0x00a8
+-#define mmDCPG_INTERRUPT_CONTROL2_BASE_IDX 2
+-#define mmDCFEV1_PG_CONFIG 0x00a9
+-#define mmDCFEV1_PG_CONFIG_BASE_IDX 2
+-#define mmDCFEV1_PG_ENABLE 0x00aa
+-#define mmDCFEV1_PG_ENABLE_BASE_IDX 2
+-#define mmDCFEV1_PG_STATUS 0x00ab
+-#define mmDCFEV1_PG_STATUS_BASE_IDX 2
+-#define mmDC_IP_REQUEST_CNTL 0x00ac
+-#define mmDC_IP_REQUEST_CNTL_BASE_IDX 2
+-#define mmDC_PGCNTL_STATUS_REG 0x00ad
+-#define mmDC_PGCNTL_STATUS_REG_BASE_IDX 2
+-#define mmDMIFV_STATUS 0x00c3
+-#define mmDMIFV_STATUS_BASE_IDX 2
+-#define mmDMIF_CONTROL 0x00c4
+-#define mmDMIF_CONTROL_BASE_IDX 2
+-#define mmDMIF_STATUS 0x00c5
+-#define mmDMIF_STATUS_BASE_IDX 2
+-#define mmDMIF_ARBITRATION_CONTROL 0x00c7
+-#define mmDMIF_ARBITRATION_CONTROL_BASE_IDX 2
+-#define mmPIPE0_ARBITRATION_CONTROL3 0x00c8
+-#define mmPIPE0_ARBITRATION_CONTROL3_BASE_IDX 2
+-#define mmPIPE1_ARBITRATION_CONTROL3 0x00c9
+-#define mmPIPE1_ARBITRATION_CONTROL3_BASE_IDX 2
+-#define mmPIPE2_ARBITRATION_CONTROL3 0x00ca
+-#define mmPIPE2_ARBITRATION_CONTROL3_BASE_IDX 2
+-#define mmPIPE3_ARBITRATION_CONTROL3 0x00cb
+-#define mmPIPE3_ARBITRATION_CONTROL3_BASE_IDX 2
+-#define mmPIPE4_ARBITRATION_CONTROL3 0x00cc
+-#define mmPIPE4_ARBITRATION_CONTROL3_BASE_IDX 2
+-#define mmPIPE5_ARBITRATION_CONTROL3 0x00cd
+-#define mmPIPE5_ARBITRATION_CONTROL3_BASE_IDX 2
+-#define mmDMIF_P_VMID 0x00ce
+-#define mmDMIF_P_VMID_BASE_IDX 2
+-#define mmDMIF_ADDR_CALC 0x00d1
+-#define mmDMIF_ADDR_CALC_BASE_IDX 2
+-#define mmDMIF_STATUS2 0x00d2
+-#define mmDMIF_STATUS2_BASE_IDX 2
+-#define mmPIPE0_MAX_REQUESTS 0x00d3
+-#define mmPIPE0_MAX_REQUESTS_BASE_IDX 2
+-#define mmPIPE1_MAX_REQUESTS 0x00d4
+-#define mmPIPE1_MAX_REQUESTS_BASE_IDX 2
+-#define mmPIPE2_MAX_REQUESTS 0x00d5
+-#define mmPIPE2_MAX_REQUESTS_BASE_IDX 2
+-#define mmPIPE3_MAX_REQUESTS 0x00d6
+-#define mmPIPE3_MAX_REQUESTS_BASE_IDX 2
+-#define mmPIPE4_MAX_REQUESTS 0x00d7
+-#define mmPIPE4_MAX_REQUESTS_BASE_IDX 2
+-#define mmPIPE5_MAX_REQUESTS 0x00d8
+-#define mmPIPE5_MAX_REQUESTS_BASE_IDX 2
+-#define mmLOW_POWER_TILING_CONTROL 0x00d9
+-#define mmLOW_POWER_TILING_CONTROL_BASE_IDX 2
+-#define mmMCIF_CONTROL 0x00da
+-#define mmMCIF_CONTROL_BASE_IDX 2
+-#define mmMCIF_WRITE_COMBINE_CONTROL 0x00db
+-#define mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX 2
+-#define mmMCIF_PHASE0_OUTSTANDING_COUNTER 0x00de
+-#define mmMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2
+-#define mmCC_DC_PIPE_DIS 0x00e0
+-#define mmCC_DC_PIPE_DIS_BASE_IDX 2
+-#define mmSMU_WM_CONTROL 0x00e1
+-#define mmSMU_WM_CONTROL_BASE_IDX 2
+-#define mmRBBMIF_TIMEOUT 0x00e2
+-#define mmRBBMIF_TIMEOUT_BASE_IDX 2
+-#define mmRBBMIF_STATUS 0x00e3
+-#define mmRBBMIF_STATUS_BASE_IDX 2
+-#define mmRBBMIF_TIMEOUT_DIS 0x00e4
+-#define mmRBBMIF_TIMEOUT_DIS_BASE_IDX 2
+-#define mmDCI_MEM_PWR_STATUS 0x00e5
+-#define mmDCI_MEM_PWR_STATUS_BASE_IDX 2
+-#define mmDCI_MEM_PWR_STATUS2 0x00e6
+-#define mmDCI_MEM_PWR_STATUS2_BASE_IDX 2
+-#define mmDCI_CLK_CNTL 0x00e7
+-#define mmDCI_CLK_CNTL_BASE_IDX 2
+-#define mmDCI_CLK_CNTL2 0x00e8
+-#define mmDCI_CLK_CNTL2_BASE_IDX 2
+-#define mmDCI_MEM_PWR_CNTL 0x00e9
+-#define mmDCI_MEM_PWR_CNTL_BASE_IDX 2
+-#define mmDCI_MEM_PWR_CNTL2 0x00ea
+-#define mmDCI_MEM_PWR_CNTL2_BASE_IDX 2
+-#define mmDCI_MEM_PWR_CNTL3 0x00eb
+-#define mmDCI_MEM_PWR_CNTL3_BASE_IDX 2
+-#define mmPIPE0_DMIF_BUFFER_CONTROL 0x00ef
+-#define mmPIPE0_DMIF_BUFFER_CONTROL_BASE_IDX 2
+-#define mmPIPE1_DMIF_BUFFER_CONTROL 0x00f0
+-#define mmPIPE1_DMIF_BUFFER_CONTROL_BASE_IDX 2
+-#define mmPIPE2_DMIF_BUFFER_CONTROL 0x00f1
+-#define mmPIPE2_DMIF_BUFFER_CONTROL_BASE_IDX 2
+-#define mmPIPE3_DMIF_BUFFER_CONTROL 0x00f2
+-#define mmPIPE3_DMIF_BUFFER_CONTROL_BASE_IDX 2
+-#define mmPIPE4_DMIF_BUFFER_CONTROL 0x00f3
+-#define mmPIPE4_DMIF_BUFFER_CONTROL_BASE_IDX 2
+-#define mmPIPE5_DMIF_BUFFER_CONTROL 0x00f4
+-#define mmPIPE5_DMIF_BUFFER_CONTROL_BASE_IDX 2
+-#define mmRBBMIF_STATUS_FLAG 0x00f5
+-#define mmRBBMIF_STATUS_FLAG_BASE_IDX 2
+-#define mmDCI_SOFT_RESET 0x00f6
+-#define mmDCI_SOFT_RESET_BASE_IDX 2
+-#define mmDMIF_URG_OVERRIDE 0x00f7
+-#define mmDMIF_URG_OVERRIDE_BASE_IDX 2
+-#define mmPIPE6_ARBITRATION_CONTROL3 0x00f8
+-#define mmPIPE6_ARBITRATION_CONTROL3_BASE_IDX 2
+-#define mmPIPE7_ARBITRATION_CONTROL3 0x00f9
+-#define mmPIPE7_ARBITRATION_CONTROL3_BASE_IDX 2
+-#define mmPIPE6_MAX_REQUESTS 0x00fa
+-#define mmPIPE6_MAX_REQUESTS_BASE_IDX 2
+-#define mmPIPE7_MAX_REQUESTS 0x00fb
+-#define mmPIPE7_MAX_REQUESTS_BASE_IDX 2
+-#define mmDVMM_REG_RD_STATUS 0x00fc
+-#define mmDVMM_REG_RD_STATUS_BASE_IDX 2
+-#define mmDVMM_REG_RD_DATA 0x00fd
+-#define mmDVMM_REG_RD_DATA_BASE_IDX 2
+-#define mmDVMM_PTE_REQ 0x00fe
+-#define mmDVMM_PTE_REQ_BASE_IDX 2
+-#define mmDVMM_CNTL 0x00ff
+-#define mmDVMM_CNTL_BASE_IDX 2
+-#define mmDVMM_FAULT_STATUS 0x0100
+-#define mmDVMM_FAULT_STATUS_BASE_IDX 2
+-#define mmDVMM_FAULT_ADDR 0x0101
+-#define mmDVMM_FAULT_ADDR_BASE_IDX 2
+-#define mmFMON_CTRL 0x0102
+-#define mmFMON_CTRL_BASE_IDX 2
+-#define mmDVMM_PTE_PGMEM_CONTROL 0x0103
+-#define mmDVMM_PTE_PGMEM_CONTROL_BASE_IDX 2
+-#define mmDVMM_PTE_PGMEM_STATE 0x0104
+-#define mmDVMM_PTE_PGMEM_STATE_BASE_IDX 2
+-#define mmMCIF_PHASE1_OUTSTANDING_COUNTER 0x0105
+-#define mmMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2
+-#define mmMCIF_PHASE2_OUTSTANDING_COUNTER 0x0106
+-#define mmMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX 2
+-#define mmMCIF_WB_PHASE0_OUTSTANDING_COUNTER 0x0107
+-#define mmMCIF_WB_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2
+-#define mmMCIF_WB_PHASE1_OUTSTANDING_COUNTER 0x0108
+-#define mmMCIF_WB_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2
+-#define mmDCI_MEM_PWR_CNTL4 0x0109
+-#define mmDCI_MEM_PWR_CNTL4_BASE_IDX 2
+-#define mmMCIF_WB_MISC_CTRL 0x010a
+-#define mmMCIF_WB_MISC_CTRL_BASE_IDX 2
+-#define mmDCI_MEM_PWR_STATUS3 0x010b
+-#define mmDCI_MEM_PWR_STATUS3_BASE_IDX 2
+-#define mmDMIF_CURSOR_CONTROL 0x010c
+-#define mmDMIF_CURSOR_CONTROL_BASE_IDX 2
+-#define mmDMIF_CURSOR_MEM_CONTROL 0x010d
+-#define mmDMIF_CURSOR_MEM_CONTROL_BASE_IDX 2
+-#define mmDCHUB_FB_LOCATION 0x0126
+-#define mmDCHUB_FB_LOCATION_BASE_IDX 2
+-#define mmDCHUB_FB_OFFSET 0x0127
+-#define mmDCHUB_FB_OFFSET_BASE_IDX 2
+-#define mmDCHUB_AGP_BASE 0x0128
+-#define mmDCHUB_AGP_BASE_BASE_IDX 2
+-#define mmDCHUB_AGP_BOT 0x0129
+-#define mmDCHUB_AGP_BOT_BASE_IDX 2
+-#define mmDCHUB_AGP_TOP 0x012a
+-#define mmDCHUB_AGP_TOP_BASE_IDX 2
+-#define mmDCHUB_DRAM_APER_BASE 0x012b
+-#define mmDCHUB_DRAM_APER_BASE_BASE_IDX 2
+-#define mmDCHUB_DRAM_APER_DEF 0x012c
+-#define mmDCHUB_DRAM_APER_DEF_BASE_IDX 2
+-#define mmDCHUB_DRAM_APER_TOP 0x012d
+-#define mmDCHUB_DRAM_APER_TOP_BASE_IDX 2
+-#define mmDCHUB_CONTROL_STATUS 0x012e
+-#define mmDCHUB_CONTROL_STATUS_BASE_IDX 2
+-#define mmWB_ENABLE 0x0212
+-#define mmWB_ENABLE_BASE_IDX 2
+-#define mmWB_EC_CONFIG 0x0213
+-#define mmWB_EC_CONFIG_BASE_IDX 2
+-#define mmCNV_MODE 0x0214
+-#define mmCNV_MODE_BASE_IDX 2
+-#define mmCNV_WINDOW_START 0x0215
+-#define mmCNV_WINDOW_START_BASE_IDX 2
+-#define mmCNV_WINDOW_SIZE 0x0216
+-#define mmCNV_WINDOW_SIZE_BASE_IDX 2
+-#define mmCNV_UPDATE 0x0217
+-#define mmCNV_UPDATE_BASE_IDX 2
+-#define mmCNV_SOURCE_SIZE 0x0218
+-#define mmCNV_SOURCE_SIZE_BASE_IDX 2
+-#define mmCNV_CSC_CONTROL 0x0219
+-#define mmCNV_CSC_CONTROL_BASE_IDX 2
+-#define mmCNV_CSC_C11_C12 0x021a
+-#define mmCNV_CSC_C11_C12_BASE_IDX 2
+-#define mmCNV_CSC_C13_C14 0x021b
+-#define mmCNV_CSC_C13_C14_BASE_IDX 2
+-#define mmCNV_CSC_C21_C22 0x021c
+-#define mmCNV_CSC_C21_C22_BASE_IDX 2
+-#define mmCNV_CSC_C23_C24 0x021d
+-#define mmCNV_CSC_C23_C24_BASE_IDX 2
+-#define mmCNV_CSC_C31_C32 0x021e
+-#define mmCNV_CSC_C31_C32_BASE_IDX 2
+-#define mmCNV_CSC_C33_C34 0x021f
+-#define mmCNV_CSC_C33_C34_BASE_IDX 2
+-#define mmCNV_CSC_ROUND_OFFSET_R 0x0220
+-#define mmCNV_CSC_ROUND_OFFSET_R_BASE_IDX 2
+-#define mmCNV_CSC_ROUND_OFFSET_G 0x0221
+-#define mmCNV_CSC_ROUND_OFFSET_G_BASE_IDX 2
+-#define mmCNV_CSC_ROUND_OFFSET_B 0x0222
+-#define mmCNV_CSC_ROUND_OFFSET_B_BASE_IDX 2
+-#define mmCNV_CSC_CLAMP_R 0x0223
+-#define mmCNV_CSC_CLAMP_R_BASE_IDX 2
+-#define mmCNV_CSC_CLAMP_G 0x0224
+-#define mmCNV_CSC_CLAMP_G_BASE_IDX 2
+-#define mmCNV_CSC_CLAMP_B 0x0225
+-#define mmCNV_CSC_CLAMP_B_BASE_IDX 2
+-#define mmCNV_TEST_CNTL 0x0226
+-#define mmCNV_TEST_CNTL_BASE_IDX 2
+-#define mmCNV_TEST_CRC_RED 0x0227
+-#define mmCNV_TEST_CRC_RED_BASE_IDX 2
+-#define mmCNV_TEST_CRC_GREEN 0x0228
+-#define mmCNV_TEST_CRC_GREEN_BASE_IDX 2
+-#define mmCNV_TEST_CRC_BLUE 0x0229
+-#define mmCNV_TEST_CRC_BLUE_BASE_IDX 2
+-#define mmCNV_INPUT_SELECT 0x022d
+-#define mmCNV_INPUT_SELECT_BASE_IDX 2
+-#define mmWB_SOFT_RESET 0x0230
+-#define mmWB_SOFT_RESET_BASE_IDX 2
+-#define mmWB_WARM_UP_MODE_CTL1 0x0231
+-#define mmWB_WARM_UP_MODE_CTL1_BASE_IDX 2
+-#define mmWB_WARM_UP_MODE_CTL2 0x0232
+-#define mmWB_WARM_UP_MODE_CTL2_BASE_IDX 2
+-#define mmWBSCL_COEF_RAM_SELECT 0x0242
+-#define mmWBSCL_COEF_RAM_SELECT_BASE_IDX 2
+-#define mmWBSCL_COEF_RAM_TAP_DATA 0x0243
+-#define mmWBSCL_COEF_RAM_TAP_DATA_BASE_IDX 2
+-#define mmWBSCL_MODE 0x0244
+-#define mmWBSCL_MODE_BASE_IDX 2
+-#define mmWBSCL_TAP_CONTROL 0x0245
+-#define mmWBSCL_TAP_CONTROL_BASE_IDX 2
+-#define mmWBSCL_DEST_SIZE 0x0246
+-#define mmWBSCL_DEST_SIZE_BASE_IDX 2
+-#define mmWBSCL_HORZ_FILTER_SCALE_RATIO 0x0247
+-#define mmWBSCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
+-#define mmWBSCL_HORZ_FILTER_INIT_Y_RGB 0x0248
+-#define mmWBSCL_HORZ_FILTER_INIT_Y_RGB_BASE_IDX 2
+-#define mmWBSCL_HORZ_FILTER_INIT_CBCR 0x0249
+-#define mmWBSCL_HORZ_FILTER_INIT_CBCR_BASE_IDX 2
+-#define mmWBSCL_VERT_FILTER_SCALE_RATIO 0x024a
+-#define mmWBSCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
+-#define mmWBSCL_VERT_FILTER_INIT_Y_RGB 0x024b
+-#define mmWBSCL_VERT_FILTER_INIT_Y_RGB_BASE_IDX 2
+-#define mmWBSCL_VERT_FILTER_INIT_CBCR 0x024c
+-#define mmWBSCL_VERT_FILTER_INIT_CBCR_BASE_IDX 2
+-#define mmWBSCL_ROUND_OFFSET 0x024d
+-#define mmWBSCL_ROUND_OFFSET_BASE_IDX 2
+-#define mmWBSCL_CLAMP 0x024e
+-#define mmWBSCL_CLAMP_BASE_IDX 2
+-#define mmWBSCL_OVERFLOW_STATUS 0x024f
+-#define mmWBSCL_OVERFLOW_STATUS_BASE_IDX 2
+-#define mmWBSCL_COEF_RAM_CONFLICT_STATUS 0x0250
+-#define mmWBSCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
+-#define mmWBSCL_OUTSIDE_PIX_STRATEGY 0x0251
+-#define mmWBSCL_OUTSIDE_PIX_STRATEGY_BASE_IDX 2
+-#define mmWBSCL_TEST_CNTL 0x0252
+-#define mmWBSCL_TEST_CNTL_BASE_IDX 2
+-#define mmWBSCL_TEST_CRC_RED 0x0253
+-#define mmWBSCL_TEST_CRC_RED_BASE_IDX 2
+-#define mmWBSCL_TEST_CRC_GREEN 0x0254
+-#define mmWBSCL_TEST_CRC_GREEN_BASE_IDX 2
+-#define mmWBSCL_TEST_CRC_BLUE 0x0255
+-#define mmWBSCL_TEST_CRC_BLUE_BASE_IDX 2
+-#define mmWBSCL_BACKPRESSURE_CNT_EN 0x0256
+-#define mmWBSCL_BACKPRESSURE_CNT_EN_BASE_IDX 2
+-#define mmWB_MCIF_BACKPRESSURE_CNT 0x0257
+-#define mmWB_MCIF_BACKPRESSURE_CNT_BASE_IDX 2
+-#define mmWBSCL_RAM_SHUTDOWN 0x025a
+-#define mmWBSCL_RAM_SHUTDOWN_BASE_IDX 2
+-#define mmDMCU_CTRL 0x03b6
+-#define mmDMCU_CTRL_BASE_IDX 2
+-#define mmDMCU_STATUS 0x03b7
+-#define mmDMCU_STATUS_BASE_IDX 2
+-#define mmDMCU_PC_START_ADDR 0x03b8
+-#define mmDMCU_PC_START_ADDR_BASE_IDX 2
+-#define mmDMCU_FW_START_ADDR 0x03b9
+-#define mmDMCU_FW_START_ADDR_BASE_IDX 2
+-#define mmDMCU_FW_END_ADDR 0x03ba
+-#define mmDMCU_FW_END_ADDR_BASE_IDX 2
+-#define mmDMCU_FW_ISR_START_ADDR 0x03bb
+-#define mmDMCU_FW_ISR_START_ADDR_BASE_IDX 2
+-#define mmDMCU_FW_CS_HI 0x03bc
+-#define mmDMCU_FW_CS_HI_BASE_IDX 2
+-#define mmDMCU_FW_CS_LO 0x03bd
+-#define mmDMCU_FW_CS_LO_BASE_IDX 2
+-#define mmDMCU_RAM_ACCESS_CTRL 0x03be
+-#define mmDMCU_RAM_ACCESS_CTRL_BASE_IDX 2
+-#define mmDMCU_ERAM_WR_CTRL 0x03bf
+-#define mmDMCU_ERAM_WR_CTRL_BASE_IDX 2
+-#define mmDMCU_ERAM_WR_DATA 0x03c0
+-#define mmDMCU_ERAM_WR_DATA_BASE_IDX 2
+-#define mmDMCU_ERAM_RD_CTRL 0x03c1
+-#define mmDMCU_ERAM_RD_CTRL_BASE_IDX 2
+-#define mmDMCU_ERAM_RD_DATA 0x03c2
+-#define mmDMCU_ERAM_RD_DATA_BASE_IDX 2
+-#define mmDMCU_IRAM_WR_CTRL 0x03c3
+-#define mmDMCU_IRAM_WR_CTRL_BASE_IDX 2
+-#define mmDMCU_IRAM_WR_DATA 0x03c4
+-#define mmDMCU_IRAM_WR_DATA_BASE_IDX 2
+-#define mmDMCU_IRAM_RD_CTRL 0x03c5
+-#define mmDMCU_IRAM_RD_CTRL_BASE_IDX 2
+-#define mmDMCU_IRAM_RD_DATA 0x03c6
+-#define mmDMCU_IRAM_RD_DATA_BASE_IDX 2
+-#define mmDMCU_EVENT_TRIGGER 0x03c7
+-#define mmDMCU_EVENT_TRIGGER_BASE_IDX 2
+-#define mmDMCU_UC_INTERNAL_INT_STATUS 0x03c8
+-#define mmDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX 2
+-#define mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x03c9
+-#define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX 2
+-#define mmDMCU_INTERRUPT_STATUS 0x03ca
+-#define mmDMCU_INTERRUPT_STATUS_BASE_IDX 2
+-#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x03cb
+-#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX 2
+-#define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x03cc
+-#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX 2
+-#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x03cd
+-#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX 2
+-#define mmDC_DMCU_SCRATCH 0x03ce
+-#define mmDC_DMCU_SCRATCH_BASE_IDX 2
+-#define mmDMCU_INT_CNT 0x03cf
+-#define mmDMCU_INT_CNT_BASE_IDX 2
+-#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x03d0
+-#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX 2
+-#define mmDMCU_UC_CLK_GATING_CNTL 0x03d1
+-#define mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX 2
+-#define mmMASTER_COMM_DATA_REG1 0x03d2
+-#define mmMASTER_COMM_DATA_REG1_BASE_IDX 2
+-#define mmMASTER_COMM_DATA_REG2 0x03d3
+-#define mmMASTER_COMM_DATA_REG2_BASE_IDX 2
+-#define mmMASTER_COMM_DATA_REG3 0x03d4
+-#define mmMASTER_COMM_DATA_REG3_BASE_IDX 2
+-#define mmMASTER_COMM_CMD_REG 0x03d5
+-#define mmMASTER_COMM_CMD_REG_BASE_IDX 2
+-#define mmMASTER_COMM_CNTL_REG 0x03d6
+-#define mmMASTER_COMM_CNTL_REG_BASE_IDX 2
+-#define mmSLAVE_COMM_DATA_REG1 0x03d7
+-#define mmSLAVE_COMM_DATA_REG1_BASE_IDX 2
+-#define mmSLAVE_COMM_DATA_REG2 0x03d8
+-#define mmSLAVE_COMM_DATA_REG2_BASE_IDX 2
+-#define mmSLAVE_COMM_DATA_REG3 0x03d9
+-#define mmSLAVE_COMM_DATA_REG3_BASE_IDX 2
+-#define mmSLAVE_COMM_CMD_REG 0x03da
+-#define mmSLAVE_COMM_CMD_REG_BASE_IDX 2
+-#define mmSLAVE_COMM_CNTL_REG 0x03db
+-#define mmSLAVE_COMM_CNTL_REG_BASE_IDX 2
+-#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x03de
+-#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 2
+-#define mmBL1_PWM_USER_LEVEL 0x03df
+-#define mmBL1_PWM_USER_LEVEL_BASE_IDX 2
+-#define mmBL1_PWM_TARGET_ABM_LEVEL 0x03e0
+-#define mmBL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 2
+-#define mmBL1_PWM_CURRENT_ABM_LEVEL 0x03e1
+-#define mmBL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 2
+-#define mmBL1_PWM_FINAL_DUTY_CYCLE 0x03e2
+-#define mmBL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 2
+-#define mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x03e3
+-#define mmBL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 2
+-#define mmBL1_PWM_ABM_CNTL 0x03e4
+-#define mmBL1_PWM_ABM_CNTL_BASE_IDX 2
+-#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x03e5
+-#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 2
+-#define mmBL1_PWM_GRP2_REG_LOCK 0x03e6
+-#define mmBL1_PWM_GRP2_REG_LOCK_BASE_IDX 2
+-#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x03e7
+-#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX 2
+-#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x03e8
+-#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX 2
+-#define mmDMCU_INTERRUPT_STATUS_1 0x03e9
+-#define mmDMCU_INTERRUPT_STATUS_1_BASE_IDX 2
+-#define mmDMCU_DPRX_INTERRUPT_STATUS1 0x03ea
+-#define mmDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX 2
+-#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x03eb
+-#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2
+-#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x03ec
+-#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2
+-#define mmDC_ABM1_CNTL 0x03ee
+-#define mmDC_ABM1_CNTL_BASE_IDX 2
+-#define mmDC_ABM1_IPCSC_COEFF_SEL 0x03ef
+-#define mmDC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 2
+-#define mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x03f0
+-#define mmDC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 2
+-#define mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x03f1
+-#define mmDC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 2
+-#define mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x03f2
+-#define mmDC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 2
+-#define mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x03f3
+-#define mmDC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 2
+-#define mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x03f4
+-#define mmDC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 2
+-#define mmDC_ABM1_ACE_THRES_12 0x03f5
+-#define mmDC_ABM1_ACE_THRES_12_BASE_IDX 2
+-#define mmDC_ABM1_ACE_THRES_34 0x03f6
+-#define mmDC_ABM1_ACE_THRES_34_BASE_IDX 2
+-#define mmDC_ABM1_ACE_CNTL_MISC 0x03f7
+-#define mmDC_ABM1_ACE_CNTL_MISC_BASE_IDX 2
+-#define mmDMCU_PERFMON_INTERRUPT_STATUS5 0x03f8
+-#define mmDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX 2
+-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x03f9
+-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX 2
+-#define mmDMCU_PERFMON_INTERRUPT_STATUS1 0x03fa
+-#define mmDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX 2
+-#define mmDMCU_PERFMON_INTERRUPT_STATUS2 0x03fb
+-#define mmDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX 2
+-#define mmDMCU_PERFMON_INTERRUPT_STATUS3 0x03fc
+-#define mmDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX 2
+-#define mmDMCU_PERFMON_INTERRUPT_STATUS4 0x03fd
+-#define mmDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX 2
+-#define mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x0400
+-#define mmDC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 2
+-#define mmDC_ABM1_HG_MISC_CTRL 0x0401
+-#define mmDC_ABM1_HG_MISC_CTRL_BASE_IDX 2
+-#define mmDC_ABM1_LS_SUM_OF_LUMA 0x0402
+-#define mmDC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 2
+-#define mmDC_ABM1_LS_MIN_MAX_LUMA 0x0403
+-#define mmDC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 2
+-#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0404
+-#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 2
+-#define mmDC_ABM1_LS_PIXEL_COUNT 0x0405
+-#define mmDC_ABM1_LS_PIXEL_COUNT_BASE_IDX 2
+-#define mmDC_ABM1_LS_OVR_SCAN_BIN 0x0406
+-#define mmDC_ABM1_LS_OVR_SCAN_BIN_BASE_IDX 2
+-#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0407
+-#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 2
+-#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0408
+-#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 2
+-#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0409
+-#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 2
+-#define mmDC_ABM1_HG_SAMPLE_RATE 0x040a
+-#define mmDC_ABM1_HG_SAMPLE_RATE_BASE_IDX 2
+-#define mmDC_ABM1_LS_SAMPLE_RATE 0x040b
+-#define mmDC_ABM1_LS_SAMPLE_RATE_BASE_IDX 2
+-#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x040c
+-#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 2
+-#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x040d
+-#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 2
+-#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x040e
+-#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 2
+-#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x040f
+-#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 2
+-#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0410
+-#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 2
+-#define mmDC_ABM1_HG_RESULT_1 0x0411
+-#define mmDC_ABM1_HG_RESULT_1_BASE_IDX 2
+-#define mmDC_ABM1_HG_RESULT_2 0x0412
+-#define mmDC_ABM1_HG_RESULT_2_BASE_IDX 2
+-#define mmDC_ABM1_HG_RESULT_3 0x0413
+-#define mmDC_ABM1_HG_RESULT_3_BASE_IDX 2
+-#define mmDC_ABM1_HG_RESULT_4 0x0414
+-#define mmDC_ABM1_HG_RESULT_4_BASE_IDX 2
+-#define mmDC_ABM1_HG_RESULT_5 0x0415
+-#define mmDC_ABM1_HG_RESULT_5_BASE_IDX 2
+-#define mmDC_ABM1_HG_RESULT_6 0x0416
+-#define mmDC_ABM1_HG_RESULT_6_BASE_IDX 2
+-#define mmDC_ABM1_HG_RESULT_7 0x0417
+-#define mmDC_ABM1_HG_RESULT_7_BASE_IDX 2
+-#define mmDC_ABM1_HG_RESULT_8 0x0418
+-#define mmDC_ABM1_HG_RESULT_8_BASE_IDX 2
+-#define mmDC_ABM1_HG_RESULT_9 0x0419
+-#define mmDC_ABM1_HG_RESULT_9_BASE_IDX 2
+-#define mmDC_ABM1_HG_RESULT_10 0x041a
+-#define mmDC_ABM1_HG_RESULT_10_BASE_IDX 2
+-#define mmDC_ABM1_HG_RESULT_11 0x041b
+-#define mmDC_ABM1_HG_RESULT_11_BASE_IDX 2
+-#define mmDC_ABM1_HG_RESULT_12 0x041c
+-#define mmDC_ABM1_HG_RESULT_12_BASE_IDX 2
+-#define mmDC_ABM1_HG_RESULT_13 0x041d
+-#define mmDC_ABM1_HG_RESULT_13_BASE_IDX 2
+-#define mmDC_ABM1_HG_RESULT_14 0x041e
+-#define mmDC_ABM1_HG_RESULT_14_BASE_IDX 2
+-#define mmDC_ABM1_HG_RESULT_15 0x041f
+-#define mmDC_ABM1_HG_RESULT_15_BASE_IDX 2
+-#define mmDC_ABM1_HG_RESULT_16 0x0420
+-#define mmDC_ABM1_HG_RESULT_16_BASE_IDX 2
+-#define mmDC_ABM1_HG_RESULT_17 0x0421
+-#define mmDC_ABM1_HG_RESULT_17_BASE_IDX 2
+-#define mmDC_ABM1_HG_RESULT_18 0x0422
+-#define mmDC_ABM1_HG_RESULT_18_BASE_IDX 2
+-#define mmDC_ABM1_HG_RESULT_19 0x0423
+-#define mmDC_ABM1_HG_RESULT_19_BASE_IDX 2
+-#define mmDC_ABM1_HG_RESULT_20 0x0424
+-#define mmDC_ABM1_HG_RESULT_20_BASE_IDX 2
+-#define mmDC_ABM1_HG_RESULT_21 0x0425
+-#define mmDC_ABM1_HG_RESULT_21_BASE_IDX 2
+-#define mmDC_ABM1_HG_RESULT_22 0x0426
+-#define mmDC_ABM1_HG_RESULT_22_BASE_IDX 2
+-#define mmDC_ABM1_HG_RESULT_23 0x0427
+-#define mmDC_ABM1_HG_RESULT_23_BASE_IDX 2
+-#define mmDC_ABM1_HG_RESULT_24 0x0428
+-#define mmDC_ABM1_HG_RESULT_24_BASE_IDX 2
+-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x0429
+-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX 2
+-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x042a
+-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2
+-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x042b
+-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX 2
+-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x042c
+-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX 2
+-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x042d
+-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX 2
+-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x042e
+-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2
+-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x042f
+-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX 2
+-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x0430
+-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX 2
+-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x0431
+-#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX 2
+-#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE 0x0451
+-#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE_BASE_IDX 2
+-#define mmDC_ABM1_BL_MASTER_LOCK 0x0452
+-#define mmDC_ABM1_BL_MASTER_LOCK_BASE_IDX 2
+-#define mmAZALIA_CONTROLLER_CLOCK_GATING 0x04bc
+-#define mmAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2
+-#define mmAZALIA_AUDIO_DTO 0x04bd
+-#define mmAZALIA_AUDIO_DTO_BASE_IDX 2
+-#define mmAZALIA_AUDIO_DTO_CONTROL 0x04be
+-#define mmAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2
+-#define mmAZALIA_SOCCLK_CONTROL 0x04bf
+-#define mmAZALIA_SOCCLK_CONTROL_BASE_IDX 2
+-#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x04c0
+-#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2
+-#define mmAZALIA_DATA_DMA_CONTROL 0x04c1
+-#define mmAZALIA_DATA_DMA_CONTROL_BASE_IDX 2
+-#define mmAZALIA_BDL_DMA_CONTROL 0x04c2
+-#define mmAZALIA_BDL_DMA_CONTROL_BASE_IDX 2
+-#define mmAZALIA_RIRB_AND_DP_CONTROL 0x04c3
+-#define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2
+-#define mmAZALIA_CORB_DMA_CONTROL 0x04c4
+-#define mmAZALIA_CORB_DMA_CONTROL_BASE_IDX 2
+-#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x04cb
+-#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX 2
+-#define mmAZALIA_CYCLIC_BUFFER_SYNC 0x04cc
+-#define mmAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX 2
+-#define mmAZALIA_GLOBAL_CAPABILITIES 0x04cd
+-#define mmAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2
+-#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x04ce
+-#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2
+-#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x04cf
+-#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2
+-#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x04d0
+-#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2
+-#define mmAZALIA_INPUT_CRC0_CONTROL0 0x04d3
+-#define mmAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2
+-#define mmAZALIA_INPUT_CRC0_CONTROL1 0x04d4
+-#define mmAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2
+-#define mmAZALIA_INPUT_CRC0_CONTROL2 0x04d5
+-#define mmAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2
+-#define mmAZALIA_INPUT_CRC0_CONTROL3 0x04d6
+-#define mmAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2
+-#define mmAZALIA_INPUT_CRC0_RESULT 0x04d7
+-#define mmAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2
+-#define mmAZALIA_INPUT_CRC1_CONTROL0 0x04d8
+-#define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2
+-#define mmAZALIA_INPUT_CRC1_CONTROL1 0x04d9
+-#define mmAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2
+-#define mmAZALIA_INPUT_CRC1_CONTROL2 0x04da
+-#define mmAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2
+-#define mmAZALIA_INPUT_CRC1_CONTROL3 0x04db
+-#define mmAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2
+-#define mmAZALIA_INPUT_CRC1_RESULT 0x04dc
+-#define mmAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2
+-#define mmAZALIA_CRC0_CONTROL0 0x04dd
+-#define mmAZALIA_CRC0_CONTROL0_BASE_IDX 2
+-#define mmAZALIA_CRC0_CONTROL1 0x04de
+-#define mmAZALIA_CRC0_CONTROL1_BASE_IDX 2
+-#define mmAZALIA_CRC0_CONTROL2 0x04df
+-#define mmAZALIA_CRC0_CONTROL2_BASE_IDX 2
+-#define mmAZALIA_CRC0_CONTROL3 0x04e0
+-#define mmAZALIA_CRC0_CONTROL3_BASE_IDX 2
+-#define mmAZALIA_CRC0_RESULT 0x04e1
+-#define mmAZALIA_CRC0_RESULT_BASE_IDX 2
+-#define mmAZALIA_CRC1_CONTROL0 0x04e2
+-#define mmAZALIA_CRC1_CONTROL0_BASE_IDX 2
+-#define mmAZALIA_CRC1_CONTROL1 0x04e3
+-#define mmAZALIA_CRC1_CONTROL1_BASE_IDX 2
+-#define mmAZALIA_CRC1_CONTROL2 0x04e4
+-#define mmAZALIA_CRC1_CONTROL2_BASE_IDX 2
+-#define mmAZALIA_CRC1_CONTROL3 0x04e5
+-#define mmAZALIA_CRC1_CONTROL3_BASE_IDX 2
+-#define mmAZALIA_CRC1_RESULT 0x04e6
+-#define mmAZALIA_CRC1_RESULT_BASE_IDX 2
+-#define mmAZALIA_MEM_PWR_CTRL 0x04e8
+-#define mmAZALIA_MEM_PWR_CTRL_BASE_IDX 2
+-#define mmAZALIA_MEM_PWR_STATUS 0x04e9
+-#define mmAZALIA_MEM_PWR_STATUS_BASE_IDX 2
+-#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0500
+-#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2
+-#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0501
+-#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2
+-#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0502
+-#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2
+-#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0503
+-#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2
+-#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x0504
+-#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2
+-#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x0505
+-#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2
+-#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x0506
+-#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2
+-#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x0507
+-#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2
+-#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x0508
+-#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2
+-#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x0509
+-#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2
+-#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x050a
+-#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2
+-#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x050b
+-#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2
+-#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x050c
+-#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2
+-#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x050d
+-#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2
+-#define mmAZALIA_F0_GTC_GROUP_OFFSET0 0x050f
+-#define mmAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX 2
+-#define mmAZALIA_F0_GTC_GROUP_OFFSET1 0x0510
+-#define mmAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX 2
+-#define mmAZALIA_F0_GTC_GROUP_OFFSET2 0x0511
+-#define mmAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX 2
+-#define mmAZALIA_F0_GTC_GROUP_OFFSET3 0x0512
+-#define mmAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX 2
+-#define mmAZALIA_F0_GTC_GROUP_OFFSET4 0x0513
+-#define mmAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX 2
+-#define mmAZALIA_F0_GTC_GROUP_OFFSET5 0x0514
+-#define mmAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX 2
+-#define mmAZALIA_F0_GTC_GROUP_OFFSET6 0x0515
+-#define mmAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX 2
+-#define mmREG_DC_AUDIO_PORT_CONNECTIVITY 0x0516
+-#define mmREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2
+-#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0517
+-#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2
+-#define mmDAC_ENABLE 0x155a
+-#define mmDAC_ENABLE_BASE_IDX 2
+-#define mmDAC_SOURCE_SELECT 0x155b
+-#define mmDAC_SOURCE_SELECT_BASE_IDX 2
+-#define mmDAC_CRC_EN 0x155c
+-#define mmDAC_CRC_EN_BASE_IDX 2
+-#define mmDAC_CRC_CONTROL 0x155d
+-#define mmDAC_CRC_CONTROL_BASE_IDX 2
+-#define mmDAC_CRC_SIG_RGB_MASK 0x155e
+-#define mmDAC_CRC_SIG_RGB_MASK_BASE_IDX 2
+-#define mmDAC_CRC_SIG_CONTROL_MASK 0x155f
+-#define mmDAC_CRC_SIG_CONTROL_MASK_BASE_IDX 2
+-#define mmDAC_CRC_SIG_RGB 0x1560
+-#define mmDAC_CRC_SIG_RGB_BASE_IDX 2
+-#define mmDAC_CRC_SIG_CONTROL 0x1561
+-#define mmDAC_CRC_SIG_CONTROL_BASE_IDX 2
+-#define mmDAC_SYNC_TRISTATE_CONTROL 0x1562
+-#define mmDAC_SYNC_TRISTATE_CONTROL_BASE_IDX 2
+-#define mmDAC_STEREOSYNC_SELECT 0x1563
+-#define mmDAC_STEREOSYNC_SELECT_BASE_IDX 2
+-#define mmDAC_AUTODETECT_CONTROL 0x1564
+-#define mmDAC_AUTODETECT_CONTROL_BASE_IDX 2
+-#define mmDAC_AUTODETECT_CONTROL2 0x1565
+-#define mmDAC_AUTODETECT_CONTROL2_BASE_IDX 2
+-#define mmDAC_AUTODETECT_CONTROL3 0x1566
+-#define mmDAC_AUTODETECT_CONTROL3_BASE_IDX 2
+-#define mmDAC_AUTODETECT_STATUS 0x1567
+-#define mmDAC_AUTODETECT_STATUS_BASE_IDX 2
+-#define mmDAC_AUTODETECT_INT_CONTROL 0x1568
+-#define mmDAC_AUTODETECT_INT_CONTROL_BASE_IDX 2
+-#define mmDAC_FORCE_OUTPUT_CNTL 0x1569
+-#define mmDAC_FORCE_OUTPUT_CNTL_BASE_IDX 2
+-#define mmDAC_FORCE_DATA 0x156a
+-#define mmDAC_FORCE_DATA_BASE_IDX 2
+-#define mmDAC_POWERDOWN 0x156b
+-#define mmDAC_POWERDOWN_BASE_IDX 2
+-#define mmDAC_CONTROL 0x156c
+-#define mmDAC_CONTROL_BASE_IDX 2
+-#define mmDAC_COMPARATOR_ENABLE 0x156d
+-#define mmDAC_COMPARATOR_ENABLE_BASE_IDX 2
+-#define mmDAC_COMPARATOR_OUTPUT 0x156e
+-#define mmDAC_COMPARATOR_OUTPUT_BASE_IDX 2
+-#define mmDAC_PWR_CNTL 0x156f
+-#define mmDAC_PWR_CNTL_BASE_IDX 2
+-#define mmDAC_DFT_CONFIG 0x1570
+-#define mmDAC_DFT_CONFIG_BASE_IDX 2
+-#define mmDAC_FIFO_STATUS 0x1571
+-#define mmDAC_FIFO_STATUS_BASE_IDX 2
+-#define mmDC_I2C_CONTROL 0x1584
+-#define mmDC_I2C_CONTROL_BASE_IDX 2
+-#define mmDC_I2C_ARBITRATION 0x1585
+-#define mmDC_I2C_ARBITRATION_BASE_IDX 2
+-#define mmDC_I2C_INTERRUPT_CONTROL 0x1586
+-#define mmDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmDC_I2C_SW_STATUS 0x1587
+-#define mmDC_I2C_SW_STATUS_BASE_IDX 2
+-#define mmDC_I2C_DDC1_HW_STATUS 0x1588
+-#define mmDC_I2C_DDC1_HW_STATUS_BASE_IDX 2
+-#define mmDC_I2C_DDC2_HW_STATUS 0x1589
+-#define mmDC_I2C_DDC2_HW_STATUS_BASE_IDX 2
+-#define mmDC_I2C_DDC3_HW_STATUS 0x158a
+-#define mmDC_I2C_DDC3_HW_STATUS_BASE_IDX 2
+-#define mmDC_I2C_DDC4_HW_STATUS 0x158b
+-#define mmDC_I2C_DDC4_HW_STATUS_BASE_IDX 2
+-#define mmDC_I2C_DDC5_HW_STATUS 0x158c
+-#define mmDC_I2C_DDC5_HW_STATUS_BASE_IDX 2
+-#define mmDC_I2C_DDC6_HW_STATUS 0x158d
+-#define mmDC_I2C_DDC6_HW_STATUS_BASE_IDX 2
+-#define mmDC_I2C_DDC1_SPEED 0x158e
+-#define mmDC_I2C_DDC1_SPEED_BASE_IDX 2
+-#define mmDC_I2C_DDC1_SETUP 0x158f
+-#define mmDC_I2C_DDC1_SETUP_BASE_IDX 2
+-#define mmDC_I2C_DDC2_SPEED 0x1590
+-#define mmDC_I2C_DDC2_SPEED_BASE_IDX 2
+-#define mmDC_I2C_DDC2_SETUP 0x1591
+-#define mmDC_I2C_DDC2_SETUP_BASE_IDX 2
+-#define mmDC_I2C_DDC3_SPEED 0x1592
+-#define mmDC_I2C_DDC3_SPEED_BASE_IDX 2
+-#define mmDC_I2C_DDC3_SETUP 0x1593
+-#define mmDC_I2C_DDC3_SETUP_BASE_IDX 2
+-#define mmDC_I2C_DDC4_SPEED 0x1594
+-#define mmDC_I2C_DDC4_SPEED_BASE_IDX 2
+-#define mmDC_I2C_DDC4_SETUP 0x1595
+-#define mmDC_I2C_DDC4_SETUP_BASE_IDX 2
+-#define mmDC_I2C_DDC5_SPEED 0x1596
+-#define mmDC_I2C_DDC5_SPEED_BASE_IDX 2
+-#define mmDC_I2C_DDC5_SETUP 0x1597
+-#define mmDC_I2C_DDC5_SETUP_BASE_IDX 2
+-#define mmDC_I2C_DDC6_SPEED 0x1598
+-#define mmDC_I2C_DDC6_SPEED_BASE_IDX 2
+-#define mmDC_I2C_DDC6_SETUP 0x1599
+-#define mmDC_I2C_DDC6_SETUP_BASE_IDX 2
+-#define mmDC_I2C_TRANSACTION0 0x159a
+-#define mmDC_I2C_TRANSACTION0_BASE_IDX 2
+-#define mmDC_I2C_TRANSACTION1 0x159b
+-#define mmDC_I2C_TRANSACTION1_BASE_IDX 2
+-#define mmDC_I2C_TRANSACTION2 0x159c
+-#define mmDC_I2C_TRANSACTION2_BASE_IDX 2
+-#define mmDC_I2C_TRANSACTION3 0x159d
+-#define mmDC_I2C_TRANSACTION3_BASE_IDX 2
+-#define mmDC_I2C_DATA 0x159e
+-#define mmDC_I2C_DATA_BASE_IDX 2
+-#define mmDC_I2C_DDCVGA_HW_STATUS 0x159f
+-#define mmDC_I2C_DDCVGA_HW_STATUS_BASE_IDX 2
+-#define mmDC_I2C_DDCVGA_SPEED 0x15a0
+-#define mmDC_I2C_DDCVGA_SPEED_BASE_IDX 2
+-#define mmDC_I2C_DDCVGA_SETUP 0x15a1
+-#define mmDC_I2C_DDCVGA_SETUP_BASE_IDX 2
+-#define mmDC_I2C_EDID_DETECT_CTRL 0x15a2
+-#define mmDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2
+-#define mmDC_I2C_READ_REQUEST_INTERRUPT 0x15a3
+-#define mmDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2
+-#define mmGENERIC_I2C_CONTROL 0x15a4
+-#define mmGENERIC_I2C_CONTROL_BASE_IDX 2
+-#define mmGENERIC_I2C_INTERRUPT_CONTROL 0x15a5
+-#define mmGENERIC_I2C_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmGENERIC_I2C_STATUS 0x15a6
+-#define mmGENERIC_I2C_STATUS_BASE_IDX 2
+-#define mmGENERIC_I2C_SPEED 0x15a7
+-#define mmGENERIC_I2C_SPEED_BASE_IDX 2
+-#define mmGENERIC_I2C_SETUP 0x15a8
+-#define mmGENERIC_I2C_SETUP_BASE_IDX 2
+-#define mmGENERIC_I2C_TRANSACTION 0x15a9
+-#define mmGENERIC_I2C_TRANSACTION_BASE_IDX 2
+-#define mmGENERIC_I2C_DATA 0x15aa
+-#define mmGENERIC_I2C_DATA_BASE_IDX 2
+-#define mmGENERIC_I2C_PIN_SELECTION 0x15ab
+-#define mmGENERIC_I2C_PIN_SELECTION_BASE_IDX 2
+-#define mmDCO_SCRATCH0 0x15b6
+-#define mmDCO_SCRATCH0_BASE_IDX 2
+-#define mmDCO_SCRATCH1 0x15b7
+-#define mmDCO_SCRATCH1_BASE_IDX 2
+-#define mmDCO_SCRATCH2 0x15b8
+-#define mmDCO_SCRATCH2_BASE_IDX 2
+-#define mmDCO_SCRATCH3 0x15b9
+-#define mmDCO_SCRATCH3_BASE_IDX 2
+-#define mmDCO_SCRATCH4 0x15ba
+-#define mmDCO_SCRATCH4_BASE_IDX 2
+-#define mmDCO_SCRATCH5 0x15bb
+-#define mmDCO_SCRATCH5_BASE_IDX 2
+-#define mmDCO_SCRATCH6 0x15bc
+-#define mmDCO_SCRATCH6_BASE_IDX 2
+-#define mmDCO_SCRATCH7 0x15bd
+-#define mmDCO_SCRATCH7_BASE_IDX 2
+-#define mmDCE_VCE_CONTROL 0x15be
+-#define mmDCE_VCE_CONTROL_BASE_IDX 2
+-#define mmDISP_INTERRUPT_STATUS 0x15bf
+-#define mmDISP_INTERRUPT_STATUS_BASE_IDX 2
+-#define mmDISP_INTERRUPT_STATUS_CONTINUE 0x15c0
+-#define mmDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2
+-#define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x15c1
+-#define mmDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2
+-#define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x15c2
+-#define mmDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2
+-#define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x15c3
+-#define mmDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2
+-#define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x15c4
+-#define mmDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2
+-#define mmDISP_INTERRUPT_STATUS_CONTINUE6 0x15c5
+-#define mmDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2
+-#define mmDISP_INTERRUPT_STATUS_CONTINUE7 0x15c6
+-#define mmDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2
+-#define mmDISP_INTERRUPT_STATUS_CONTINUE8 0x15c7
+-#define mmDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2
+-#define mmDISP_INTERRUPT_STATUS_CONTINUE9 0x15c8
+-#define mmDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2
+-#define mmDCO_MEM_PWR_STATUS 0x15c9
+-#define mmDCO_MEM_PWR_STATUS_BASE_IDX 2
+-#define mmDCO_MEM_PWR_CTRL 0x15ca
+-#define mmDCO_MEM_PWR_CTRL_BASE_IDX 2
+-#define mmDCO_MEM_PWR_CTRL2 0x15cb
+-#define mmDCO_MEM_PWR_CTRL2_BASE_IDX 2
+-#define mmDCO_CLK_CNTL 0x15cc
+-#define mmDCO_CLK_CNTL_BASE_IDX 2
+-#define mmDCO_POWER_MANAGEMENT_CNTL 0x15d0
+-#define mmDCO_POWER_MANAGEMENT_CNTL_BASE_IDX 2
+-#define mmDIG_SOFT_RESET_2 0x15d2
+-#define mmDIG_SOFT_RESET_2_BASE_IDX 2
+-#define mmDCO_STEREOSYNC_SEL 0x15d6
+-#define mmDCO_STEREOSYNC_SEL_BASE_IDX 2
+-#define mmDCO_SOFT_RESET 0x15d9
+-#define mmDCO_SOFT_RESET_BASE_IDX 2
+-#define mmDIG_SOFT_RESET 0x15da
+-#define mmDIG_SOFT_RESET_BASE_IDX 2
+-#define mmDCO_MEM_PWR_STATUS1 0x15dc
+-#define mmDCO_MEM_PWR_STATUS1_BASE_IDX 2
+-#define mmDISP_INTERRUPT_STATUS_CONTINUE10 0x15dd
+-#define mmDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2
+-#define mmDCO_CLK_CNTL2 0x15de
+-#define mmDCO_CLK_CNTL2_BASE_IDX 2
+-#define mmDCO_CLK_CNTL3 0x15df
+-#define mmDCO_CLK_CNTL3_BASE_IDX 2
+-#define mmDCO_HDMI_RXSTATUS_TIMER_CONTROL 0x15eb
+-#define mmDCO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2
+-#define mmDCO_PSP_INTERRUPT_STATUS 0x15ec
+-#define mmDCO_PSP_INTERRUPT_STATUS_BASE_IDX 2
+-#define mmDCO_PSP_INTERRUPT_CLEAR 0x15ed
+-#define mmDCO_PSP_INTERRUPT_CLEAR_BASE_IDX 2
+-#define mmDCO_GENERIC_INTERRUPT_MESSAGE 0x15ee
+-#define mmDCO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX 2
+-#define mmDCO_GENERIC_INTERRUPT_CLEAR 0x15ef
+-#define mmDCO_GENERIC_INTERRUPT_CLEAR_BASE_IDX 2
+-#define mmFMT_MEMORY0_CONTROL 0x15f0
+-#define mmFMT_MEMORY0_CONTROL_BASE_IDX 2
+-#define mmFMT_MEMORY1_CONTROL 0x15f1
+-#define mmFMT_MEMORY1_CONTROL_BASE_IDX 2
+-#define mmFMT_MEMORY2_CONTROL 0x15f2
+-#define mmFMT_MEMORY2_CONTROL_BASE_IDX 2
+-#define mmFMT_MEMORY3_CONTROL 0x15f3
+-#define mmFMT_MEMORY3_CONTROL_BASE_IDX 2
+-#define mmFMT_MEMORY4_CONTROL 0x15f4
+-#define mmFMT_MEMORY4_CONTROL_BASE_IDX 2
+-#define mmFMT_MEMORY5_CONTROL 0x15f5
+-#define mmFMT_MEMORY5_CONTROL_BASE_IDX 2
+-#define mmDISP_INTERRUPT_STATUS_CONTINUE11 0x15f6
+-#define mmDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2
+-#define mmDC_GENERICA 0x207e
+-#define mmDC_GENERICA_BASE_IDX 2
+-#define mmDC_GENERICB 0x207f
+-#define mmDC_GENERICB_BASE_IDX 2
+-#define mmDC_PAD_EXTERN_SIG 0x2080
+-#define mmDC_PAD_EXTERN_SIG_BASE_IDX 2
+-#define mmDC_REF_CLK_CNTL 0x2081
+-#define mmDC_REF_CLK_CNTL_BASE_IDX 2
+-#define mmDC_GPIO_DEBUG 0x2082
+-#define mmDC_GPIO_DEBUG_BASE_IDX 2
+-#define mmUNIPHYA_LINK_CNTL 0x2083
+-#define mmUNIPHYA_LINK_CNTL_BASE_IDX 2
+-#define mmUNIPHYA_CHANNEL_XBAR_CNTL 0x2084
+-#define mmUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2
+-#define mmUNIPHYB_LINK_CNTL 0x2085
+-#define mmUNIPHYB_LINK_CNTL_BASE_IDX 2
+-#define mmUNIPHYB_CHANNEL_XBAR_CNTL 0x2086
+-#define mmUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2
+-#define mmUNIPHYC_LINK_CNTL 0x2087
+-#define mmUNIPHYC_LINK_CNTL_BASE_IDX 2
+-#define mmUNIPHYC_CHANNEL_XBAR_CNTL 0x2088
+-#define mmUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2
+-#define mmUNIPHYD_LINK_CNTL 0x2089
+-#define mmUNIPHYD_LINK_CNTL_BASE_IDX 2
+-#define mmUNIPHYD_CHANNEL_XBAR_CNTL 0x208a
+-#define mmUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2
+-#define mmUNIPHYE_LINK_CNTL 0x208b
+-#define mmUNIPHYE_LINK_CNTL_BASE_IDX 2
+-#define mmUNIPHYE_CHANNEL_XBAR_CNTL 0x208c
+-#define mmUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2
+-#define mmUNIPHYF_LINK_CNTL 0x208d
+-#define mmUNIPHYF_LINK_CNTL_BASE_IDX 2
+-#define mmUNIPHYF_CHANNEL_XBAR_CNTL 0x208e
+-#define mmUNIPHYF_CHANNEL_XBAR_CNTL_BASE_IDX 2
+-#define mmUNIPHYG_LINK_CNTL 0x208f
+-#define mmUNIPHYG_LINK_CNTL_BASE_IDX 2
+-#define mmUNIPHYG_CHANNEL_XBAR_CNTL 0x2090
+-#define mmUNIPHYG_CHANNEL_XBAR_CNTL_BASE_IDX 2
+-#define mmDCIO_WRCMD_DELAY 0x2094
+-#define mmDCIO_WRCMD_DELAY_BASE_IDX 2
+-#define mmDC_DVODATA_CONFIG 0x2098
+-#define mmDC_DVODATA_CONFIG_BASE_IDX 2
+-#define mmLVTMA_PWRSEQ_CNTL 0x2099
+-#define mmLVTMA_PWRSEQ_CNTL_BASE_IDX 2
+-#define mmLVTMA_PWRSEQ_STATE 0x209a
+-#define mmLVTMA_PWRSEQ_STATE_BASE_IDX 2
+-#define mmLVTMA_PWRSEQ_REF_DIV 0x209b
+-#define mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX 2
+-#define mmLVTMA_PWRSEQ_DELAY1 0x209c
+-#define mmLVTMA_PWRSEQ_DELAY1_BASE_IDX 2
+-#define mmLVTMA_PWRSEQ_DELAY2 0x209d
+-#define mmLVTMA_PWRSEQ_DELAY2_BASE_IDX 2
+-#define mmBL_PWM_CNTL 0x209e
+-#define mmBL_PWM_CNTL_BASE_IDX 2
+-#define mmBL_PWM_CNTL2 0x209f
+-#define mmBL_PWM_CNTL2_BASE_IDX 2
+-#define mmBL_PWM_PERIOD_CNTL 0x20a0
+-#define mmBL_PWM_PERIOD_CNTL_BASE_IDX 2
+-#define mmBL_PWM_GRP1_REG_LOCK 0x20a1
+-#define mmBL_PWM_GRP1_REG_LOCK_BASE_IDX 2
+-#define mmDCIO_GSL_GENLK_PAD_CNTL 0x20a2
+-#define mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2
+-#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x20a3
+-#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2
+-#define mmDCIO_GSL0_CNTL 0x20a4
+-#define mmDCIO_GSL0_CNTL_BASE_IDX 2
+-#define mmDCIO_GSL1_CNTL 0x20a5
+-#define mmDCIO_GSL1_CNTL_BASE_IDX 2
+-#define mmDCIO_GSL2_CNTL 0x20a6
+-#define mmDCIO_GSL2_CNTL_BASE_IDX 2
+-#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x20a7
+-#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2
+-#define mmDC_GPU_TIMER_START_POSITION_P_FLIP 0x20a8
+-#define mmDC_GPU_TIMER_START_POSITION_P_FLIP_BASE_IDX 2
+-#define mmDC_GPU_TIMER_READ 0x20a9
+-#define mmDC_GPU_TIMER_READ_BASE_IDX 2
+-#define mmDC_GPU_TIMER_READ_CNTL 0x20aa
+-#define mmDC_GPU_TIMER_READ_CNTL_BASE_IDX 2
+-#define mmDCIO_CLOCK_CNTL 0x20ab
+-#define mmDCIO_CLOCK_CNTL_BASE_IDX 2
+-#define mmDCO_DCFE_EXT_VSYNC_CNTL 0x20ae
+-#define mmDCO_DCFE_EXT_VSYNC_CNTL_BASE_IDX 2
+-#define mmDCIO_SOFT_RESET 0x20b4
+-#define mmDCIO_SOFT_RESET_BASE_IDX 2
+-#define mmDCIO_DPHY_SEL 0x20b5
+-#define mmDCIO_DPHY_SEL_BASE_IDX 2
+-#define mmUNIPHY_IMPCAL_LINKA 0x20b6
+-#define mmUNIPHY_IMPCAL_LINKA_BASE_IDX 2
+-#define mmUNIPHY_IMPCAL_LINKB 0x20b7
+-#define mmUNIPHY_IMPCAL_LINKB_BASE_IDX 2
+-#define mmUNIPHY_IMPCAL_PERIOD 0x20b8
+-#define mmUNIPHY_IMPCAL_PERIOD_BASE_IDX 2
+-#define mmAUXP_IMPCAL 0x20b9
+-#define mmAUXP_IMPCAL_BASE_IDX 2
+-#define mmAUXN_IMPCAL 0x20ba
+-#define mmAUXN_IMPCAL_BASE_IDX 2
+-#define mmDCIO_IMPCAL_CNTL 0x20bb
+-#define mmDCIO_IMPCAL_CNTL_BASE_IDX 2
+-#define mmUNIPHY_IMPCAL_PSW_AB 0x20bc
+-#define mmUNIPHY_IMPCAL_PSW_AB_BASE_IDX 2
+-#define mmUNIPHY_IMPCAL_LINKC 0x20bd
+-#define mmUNIPHY_IMPCAL_LINKC_BASE_IDX 2
+-#define mmUNIPHY_IMPCAL_LINKD 0x20be
+-#define mmUNIPHY_IMPCAL_LINKD_BASE_IDX 2
+-#define mmDCIO_IMPCAL_CNTL_CD 0x20bf
+-#define mmDCIO_IMPCAL_CNTL_CD_BASE_IDX 2
+-#define mmUNIPHY_IMPCAL_PSW_CD 0x20c0
+-#define mmUNIPHY_IMPCAL_PSW_CD_BASE_IDX 2
+-#define mmUNIPHY_IMPCAL_LINKE 0x20c1
+-#define mmUNIPHY_IMPCAL_LINKE_BASE_IDX 2
+-#define mmUNIPHY_IMPCAL_LINKF 0x20c2
+-#define mmUNIPHY_IMPCAL_LINKF_BASE_IDX 2
+-#define mmDCIO_IMPCAL_CNTL_EF 0x20c3
+-#define mmDCIO_IMPCAL_CNTL_EF_BASE_IDX 2
+-#define mmUNIPHY_IMPCAL_PSW_EF 0x20c4
+-#define mmUNIPHY_IMPCAL_PSW_EF_BASE_IDX 2
+-#define mmUNIPHYLPA_LINK_CNTL 0x20c5
+-#define mmUNIPHYLPA_LINK_CNTL_BASE_IDX 2
+-#define mmUNIPHYLPB_LINK_CNTL 0x20c6
+-#define mmUNIPHYLPB_LINK_CNTL_BASE_IDX 2
+-#define mmUNIPHYLPA_CHANNEL_XBAR_CNTL 0x20c7
+-#define mmUNIPHYLPA_CHANNEL_XBAR_CNTL_BASE_IDX 2
+-#define mmUNIPHYLPB_CHANNEL_XBAR_CNTL 0x20c8
+-#define mmUNIPHYLPB_CHANNEL_XBAR_CNTL_BASE_IDX 2
+-#define mmDCIO_DPCS_TX_INTERRUPT 0x20c9
+-#define mmDCIO_DPCS_TX_INTERRUPT_BASE_IDX 2
+-#define mmDCIO_DPCS_RX_INTERRUPT 0x20ca
+-#define mmDCIO_DPCS_RX_INTERRUPT_BASE_IDX 2
+-#define mmDCIO_SEMAPHORE0 0x20cb
+-#define mmDCIO_SEMAPHORE0_BASE_IDX 2
+-#define mmDCIO_SEMAPHORE1 0x20cc
+-#define mmDCIO_SEMAPHORE1_BASE_IDX 2
+-#define mmDCIO_SEMAPHORE2 0x20cd
+-#define mmDCIO_SEMAPHORE2_BASE_IDX 2
+-#define mmDCIO_SEMAPHORE3 0x20ce
+-#define mmDCIO_SEMAPHORE3_BASE_IDX 2
+-#define mmDCIO_SEMAPHORE4 0x20cf
+-#define mmDCIO_SEMAPHORE4_BASE_IDX 2
+-#define mmDCIO_SEMAPHORE5 0x20d0
+-#define mmDCIO_SEMAPHORE5_BASE_IDX 2
+-#define mmDCIO_SEMAPHORE6 0x20d1
+-#define mmDCIO_SEMAPHORE6_BASE_IDX 2
+-#define mmDCIO_SEMAPHORE7 0x20d2
+-#define mmDCIO_SEMAPHORE7_BASE_IDX 2
+-#define mmDC_GPIO_GENERIC_MASK 0x20de
+-#define mmDC_GPIO_GENERIC_MASK_BASE_IDX 2
+-#define mmDC_GPIO_GENERIC_A 0x20df
+-#define mmDC_GPIO_GENERIC_A_BASE_IDX 2
+-#define mmDC_GPIO_GENERIC_EN 0x20e0
+-#define mmDC_GPIO_GENERIC_EN_BASE_IDX 2
+-#define mmDC_GPIO_GENERIC_Y 0x20e1
+-#define mmDC_GPIO_GENERIC_Y_BASE_IDX 2
+-#define mmDC_GPIO_DVODATA_MASK 0x20e2
+-#define mmDC_GPIO_DVODATA_MASK_BASE_IDX 2
+-#define mmDC_GPIO_DVODATA_A 0x20e3
+-#define mmDC_GPIO_DVODATA_A_BASE_IDX 2
+-#define mmDC_GPIO_DVODATA_EN 0x20e4
+-#define mmDC_GPIO_DVODATA_EN_BASE_IDX 2
+-#define mmDC_GPIO_DVODATA_Y 0x20e5
+-#define mmDC_GPIO_DVODATA_Y_BASE_IDX 2
+-#define mmDC_GPIO_DDC1_MASK 0x20e6
+-#define mmDC_GPIO_DDC1_MASK_BASE_IDX 2
+-#define mmDC_GPIO_DDC1_A 0x20e7
+-#define mmDC_GPIO_DDC1_A_BASE_IDX 2
+-#define mmDC_GPIO_DDC1_EN 0x20e8
+-#define mmDC_GPIO_DDC1_EN_BASE_IDX 2
+-#define mmDC_GPIO_DDC1_Y 0x20e9
+-#define mmDC_GPIO_DDC1_Y_BASE_IDX 2
+-#define mmDC_GPIO_DDC2_MASK 0x20ea
+-#define mmDC_GPIO_DDC2_MASK_BASE_IDX 2
+-#define mmDC_GPIO_DDC2_A 0x20eb
+-#define mmDC_GPIO_DDC2_A_BASE_IDX 2
+-#define mmDC_GPIO_DDC2_EN 0x20ec
+-#define mmDC_GPIO_DDC2_EN_BASE_IDX 2
+-#define mmDC_GPIO_DDC2_Y 0x20ed
+-#define mmDC_GPIO_DDC2_Y_BASE_IDX 2
+-#define mmDC_GPIO_DDC3_MASK 0x20ee
+-#define mmDC_GPIO_DDC3_MASK_BASE_IDX 2
+-#define mmDC_GPIO_DDC3_A 0x20ef
+-#define mmDC_GPIO_DDC3_A_BASE_IDX 2
+-#define mmDC_GPIO_DDC3_EN 0x20f0
+-#define mmDC_GPIO_DDC3_EN_BASE_IDX 2
+-#define mmDC_GPIO_DDC3_Y 0x20f1
+-#define mmDC_GPIO_DDC3_Y_BASE_IDX 2
+-#define mmDC_GPIO_DDC4_MASK 0x20f2
+-#define mmDC_GPIO_DDC4_MASK_BASE_IDX 2
+-#define mmDC_GPIO_DDC4_A 0x20f3
+-#define mmDC_GPIO_DDC4_A_BASE_IDX 2
+-#define mmDC_GPIO_DDC4_EN 0x20f4
+-#define mmDC_GPIO_DDC4_EN_BASE_IDX 2
+-#define mmDC_GPIO_DDC4_Y 0x20f5
+-#define mmDC_GPIO_DDC4_Y_BASE_IDX 2
+-#define mmDC_GPIO_DDC5_MASK 0x20f6
+-#define mmDC_GPIO_DDC5_MASK_BASE_IDX 2
+-#define mmDC_GPIO_DDC5_A 0x20f7
+-#define mmDC_GPIO_DDC5_A_BASE_IDX 2
+-#define mmDC_GPIO_DDC5_EN 0x20f8
+-#define mmDC_GPIO_DDC5_EN_BASE_IDX 2
+-#define mmDC_GPIO_DDC5_Y 0x20f9
+-#define mmDC_GPIO_DDC5_Y_BASE_IDX 2
+-#define mmDC_GPIO_DDC6_MASK 0x20fa
+-#define mmDC_GPIO_DDC6_MASK_BASE_IDX 2
+-#define mmDC_GPIO_DDC6_A 0x20fb
+-#define mmDC_GPIO_DDC6_A_BASE_IDX 2
+-#define mmDC_GPIO_DDC6_EN 0x20fc
+-#define mmDC_GPIO_DDC6_EN_BASE_IDX 2
+-#define mmDC_GPIO_DDC6_Y 0x20fd
+-#define mmDC_GPIO_DDC6_Y_BASE_IDX 2
+-#define mmDC_GPIO_DDCVGA_MASK 0x20fe
+-#define mmDC_GPIO_DDCVGA_MASK_BASE_IDX 2
+-#define mmDC_GPIO_DDCVGA_A 0x20ff
+-#define mmDC_GPIO_DDCVGA_A_BASE_IDX 2
+-#define mmDC_GPIO_DDCVGA_EN 0x2100
+-#define mmDC_GPIO_DDCVGA_EN_BASE_IDX 2
+-#define mmDC_GPIO_DDCVGA_Y 0x2101
+-#define mmDC_GPIO_DDCVGA_Y_BASE_IDX 2
+-#define mmDC_GPIO_SYNCA_MASK 0x2102
+-#define mmDC_GPIO_SYNCA_MASK_BASE_IDX 2
+-#define mmDC_GPIO_SYNCA_A 0x2103
+-#define mmDC_GPIO_SYNCA_A_BASE_IDX 2
+-#define mmDC_GPIO_SYNCA_EN 0x2104
+-#define mmDC_GPIO_SYNCA_EN_BASE_IDX 2
+-#define mmDC_GPIO_SYNCA_Y 0x2105
+-#define mmDC_GPIO_SYNCA_Y_BASE_IDX 2
+-#define mmDC_GPIO_GENLK_MASK 0x2106
+-#define mmDC_GPIO_GENLK_MASK_BASE_IDX 2
+-#define mmDC_GPIO_GENLK_A 0x2107
+-#define mmDC_GPIO_GENLK_A_BASE_IDX 2
+-#define mmDC_GPIO_GENLK_EN 0x2108
+-#define mmDC_GPIO_GENLK_EN_BASE_IDX 2
+-#define mmDC_GPIO_GENLK_Y 0x2109
+-#define mmDC_GPIO_GENLK_Y_BASE_IDX 2
+-#define mmDC_GPIO_HPD_MASK 0x210a
+-#define mmDC_GPIO_HPD_MASK_BASE_IDX 2
+-#define mmDC_GPIO_HPD_A 0x210b
+-#define mmDC_GPIO_HPD_A_BASE_IDX 2
+-#define mmDC_GPIO_HPD_EN 0x210c
+-#define mmDC_GPIO_HPD_EN_BASE_IDX 2
+-#define mmDC_GPIO_HPD_Y 0x210d
+-#define mmDC_GPIO_HPD_Y_BASE_IDX 2
+-#define mmDC_GPIO_PWRSEQ_MASK 0x210e
+-#define mmDC_GPIO_PWRSEQ_MASK_BASE_IDX 2
+-#define mmDC_GPIO_PWRSEQ_A 0x210f
+-#define mmDC_GPIO_PWRSEQ_A_BASE_IDX 2
+-#define mmDC_GPIO_PWRSEQ_EN 0x2110
+-#define mmDC_GPIO_PWRSEQ_EN_BASE_IDX 2
+-#define mmDC_GPIO_PWRSEQ_Y 0x2111
+-#define mmDC_GPIO_PWRSEQ_Y_BASE_IDX 2
+-#define mmDC_GPIO_PAD_STRENGTH_1 0x2112
+-#define mmDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2
+-#define mmDC_GPIO_PAD_STRENGTH_2 0x2113
+-#define mmDC_GPIO_PAD_STRENGTH_2_BASE_IDX 2
+-#define mmPHY_AUX_CNTL 0x2115
+-#define mmPHY_AUX_CNTL_BASE_IDX 2
+-#define mmDC_GPIO_I2CPAD_MASK 0x2116
+-#define mmDC_GPIO_I2CPAD_MASK_BASE_IDX 2
+-#define mmDC_GPIO_I2CPAD_A 0x2117
+-#define mmDC_GPIO_I2CPAD_A_BASE_IDX 2
+-#define mmDC_GPIO_I2CPAD_EN 0x2118
+-#define mmDC_GPIO_I2CPAD_EN_BASE_IDX 2
+-#define mmDC_GPIO_I2CPAD_Y 0x2119
+-#define mmDC_GPIO_I2CPAD_Y_BASE_IDX 2
+-#define mmDC_GPIO_I2CPAD_STRENGTH 0x211a
+-#define mmDC_GPIO_I2CPAD_STRENGTH_BASE_IDX 2
+-#define mmDVO_STRENGTH_CONTROL 0x211b
+-#define mmDVO_STRENGTH_CONTROL_BASE_IDX 2
+-#define mmDVO_VREF_CONTROL 0x211c
+-#define mmDVO_VREF_CONTROL_BASE_IDX 2
+-#define mmDVO_SKEW_ADJUST 0x211d
+-#define mmDVO_SKEW_ADJUST_BASE_IDX 2
+-#define mmDC_GPIO_I2S_SPDIF_MASK 0x2126
+-#define mmDC_GPIO_I2S_SPDIF_MASK_BASE_IDX 2
+-#define mmDC_GPIO_I2S_SPDIF_A 0x2127
+-#define mmDC_GPIO_I2S_SPDIF_A_BASE_IDX 2
+-#define mmDC_GPIO_I2S_SPDIF_EN 0x2128
+-#define mmDC_GPIO_I2S_SPDIF_EN_BASE_IDX 2
+-#define mmDC_GPIO_I2S_SPDIF_Y 0x2129
+-#define mmDC_GPIO_I2S_SPDIF_Y_BASE_IDX 2
+-#define mmDC_GPIO_I2S_SPDIF_STRENGTH 0x212a
+-#define mmDC_GPIO_I2S_SPDIF_STRENGTH_BASE_IDX 2
+-#define mmDC_GPIO_TX12_EN 0x212b
+-#define mmDC_GPIO_TX12_EN_BASE_IDX 2
+-#define mmDC_GPIO_AUX_CTRL_0 0x212c
+-#define mmDC_GPIO_AUX_CTRL_0_BASE_IDX 2
+-#define mmDC_GPIO_AUX_CTRL_1 0x212d
+-#define mmDC_GPIO_AUX_CTRL_1_BASE_IDX 2
+-#define mmDC_GPIO_AUX_CTRL_2 0x212e
+-#define mmDC_GPIO_AUX_CTRL_2_BASE_IDX 2
+-#define mmDC_GPIO_RXEN 0x212f
+-#define mmDC_GPIO_RXEN_BASE_IDX 2
+-#define mmBPHYC_DAC_MACRO_CNTL 0x2136
+-#define mmBPHYC_DAC_MACRO_CNTL_BASE_IDX 2
+-#define mmDAC_MACRO_CNTL_RESERVED0 0x2136
+-#define mmDAC_MACRO_CNTL_RESERVED0_BASE_IDX 2
+-#define mmBPHYC_DAC_AUTO_CALIB_CONTROL 0x2137
+-#define mmBPHYC_DAC_AUTO_CALIB_CONTROL_BASE_IDX 2
+-#define mmDAC_MACRO_CNTL_RESERVED1 0x2137
+-#define mmDAC_MACRO_CNTL_RESERVED1_BASE_IDX 2
+-#define mmDAC_MACRO_CNTL_RESERVED2 0x2138
+-#define mmDAC_MACRO_CNTL_RESERVED2_BASE_IDX 2
+-#define mmDAC_MACRO_CNTL_RESERVED3 0x2139
+-#define mmDAC_MACRO_CNTL_RESERVED3_BASE_IDX 2
+-#define mmDISP_DSI_DUAL_CTRL 0x277e
+-#define mmDISP_DSI_DUAL_CTRL_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED0 0x283e
+-#define mmDPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED1 0x283f
+-#define mmDPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED2 0x2840
+-#define mmDPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED3 0x2841
+-#define mmDPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED4 0x2842
+-#define mmDPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED5 0x2843
+-#define mmDPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED6 0x2844
+-#define mmDPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED7 0x2845
+-#define mmDPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED8 0x2846
+-#define mmDPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED9 0x2847
+-#define mmDPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED10 0x2848
+-#define mmDPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED11 0x2849
+-#define mmDPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED12 0x284a
+-#define mmDPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED13 0x284b
+-#define mmDPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED14 0x284c
+-#define mmDPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED15 0x284d
+-#define mmDPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED16 0x284e
+-#define mmDPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED17 0x284f
+-#define mmDPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED18 0x2850
+-#define mmDPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED19 0x2851
+-#define mmDPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED20 0x2852
+-#define mmDPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED21 0x2853
+-#define mmDPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED22 0x2854
+-#define mmDPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED23 0x2855
+-#define mmDPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED24 0x2856
+-#define mmDPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED25 0x2857
+-#define mmDPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED26 0x2858
+-#define mmDPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED27 0x2859
+-#define mmDPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED28 0x285a
+-#define mmDPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED29 0x285b
+-#define mmDPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED30 0x285c
+-#define mmDPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED31 0x285d
+-#define mmDPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED32 0x285e
+-#define mmDPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED33 0x285f
+-#define mmDPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED34 0x2860
+-#define mmDPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED35 0x2861
+-#define mmDPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED36 0x2862
+-#define mmDPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED37 0x2863
+-#define mmDPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED38 0x2864
+-#define mmDPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED39 0x2865
+-#define mmDPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED40 0x2866
+-#define mmDPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED41 0x2867
+-#define mmDPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED42 0x2868
+-#define mmDPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED43 0x2869
+-#define mmDPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED44 0x286a
+-#define mmDPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED45 0x286b
+-#define mmDPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED46 0x286c
+-#define mmDPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED47 0x286d
+-#define mmDPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED48 0x286e
+-#define mmDPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED49 0x286f
+-#define mmDPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED50 0x2870
+-#define mmDPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED51 0x2871
+-#define mmDPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED52 0x2872
+-#define mmDPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED53 0x2873
+-#define mmDPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED54 0x2874
+-#define mmDPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED55 0x2875
+-#define mmDPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED56 0x2876
+-#define mmDPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED57 0x2877
+-#define mmDPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED58 0x2878
+-#define mmDPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED59 0x2879
+-#define mmDPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED60 0x287a
+-#define mmDPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED61 0x287b
+-#define mmDPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED62 0x287c
+-#define mmDPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
+-#define mmDPHY_MACRO_CNTL_RESERVED63 0x287d
+-#define mmDPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
+-#define mmDPRX_AUX_REFERENCE_PULSE_DIV 0x2a7e
+-#define mmDPRX_AUX_REFERENCE_PULSE_DIV_BASE_IDX 2
+-#define mmDPRX_AUX_CONTROL 0x2a7f
+-#define mmDPRX_AUX_CONTROL_BASE_IDX 2
+-#define mmDPRX_AUX_HPD_CONTROL1 0x2a80
+-#define mmDPRX_AUX_HPD_CONTROL1_BASE_IDX 2
+-#define mmDPRX_AUX_HPD_CONTROL2 0x2a81
+-#define mmDPRX_AUX_HPD_CONTROL2_BASE_IDX 2
+-#define mmDPRX_AUX_RX_STATUS 0x2a82
+-#define mmDPRX_AUX_RX_STATUS_BASE_IDX 2
+-#define mmDPRX_AUX_RX_ERROR_MASK 0x2a83
+-#define mmDPRX_AUX_RX_ERROR_MASK_BASE_IDX 2
+-#define mmDPRX_AUX_DPHY_TX_REF_CONTROL 0x2a84
+-#define mmDPRX_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
+-#define mmDPRX_AUX_DPHY_TX_CONTROL 0x2a85
+-#define mmDPRX_AUX_DPHY_TX_CONTROL_BASE_IDX 2
+-#define mmDPRX_AUX_DPHY_RX_CONTROL0 0x2a86
+-#define mmDPRX_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
+-#define mmDPRX_AUX_DPHY_RX_CONTROL1 0x2a87
+-#define mmDPRX_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
+-#define mmDPRX_AUX_DPHY_TX_STATUS 0x2a88
+-#define mmDPRX_AUX_DPHY_TX_STATUS_BASE_IDX 2
+-#define mmDPRX_AUX_DPHY_RX_STATUS 0x2a89
+-#define mmDPRX_AUX_DPHY_RX_STATUS_BASE_IDX 2
+-#define mmDPRX_AUX_DMCU_HW_INT_STATUS 0x2a8a
+-#define mmDPRX_AUX_DMCU_HW_INT_STATUS_BASE_IDX 2
+-#define mmDPRX_AUX_DMCU_HW_INT_ACK 0x2a8b
+-#define mmDPRX_AUX_DMCU_HW_INT_ACK_BASE_IDX 2
+-#define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT1 0x2a8c
+-#define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT1_BASE_IDX 2
+-#define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT2 0x2a8d
+-#define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT2_BASE_IDX 2
+-#define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT1 0x2a8e
+-#define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT1_BASE_IDX 2
+-#define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT2 0x2a8f
+-#define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT2_BASE_IDX 2
+-#define mmDPRX_AUX_AUX_BUF_INDEX 0x2a90
+-#define mmDPRX_AUX_AUX_BUF_INDEX_BASE_IDX 2
+-#define mmDPRX_AUX_AUX_BUF_DATA 0x2a91
+-#define mmDPRX_AUX_AUX_BUF_DATA_BASE_IDX 2
+-#define mmDPRX_AUX_EDID_INDEX 0x2a92
+-#define mmDPRX_AUX_EDID_INDEX_BASE_IDX 2
+-#define mmDPRX_AUX_EDID_DATA 0x2a93
+-#define mmDPRX_AUX_EDID_DATA_BASE_IDX 2
+-#define mmDPRX_AUX_DPCD_INDEX1 0x2a94
+-#define mmDPRX_AUX_DPCD_INDEX1_BASE_IDX 2
+-#define mmDPRX_AUX_DPCD_DATA1 0x2a95
+-#define mmDPRX_AUX_DPCD_DATA1_BASE_IDX 2
+-#define mmDPRX_AUX_DPCD_INDEX2 0x2a96
+-#define mmDPRX_AUX_DPCD_INDEX2_BASE_IDX 2
+-#define mmDPRX_AUX_DPCD_DATA2 0x2a97
+-#define mmDPRX_AUX_DPCD_DATA2_BASE_IDX 2
+-#define mmDPRX_AUX_MSG_INDEX1 0x2a98
+-#define mmDPRX_AUX_MSG_INDEX1_BASE_IDX 2
+-#define mmDPRX_AUX_MSG_DATA1 0x2a99
+-#define mmDPRX_AUX_MSG_DATA1_BASE_IDX 2
+-#define mmDPRX_AUX_MSG_INDEX2 0x2a9a
+-#define mmDPRX_AUX_MSG_INDEX2_BASE_IDX 2
+-#define mmDPRX_AUX_MSG_DATA2 0x2a9b
+-#define mmDPRX_AUX_MSG_DATA2_BASE_IDX 2
+-#define mmDPRX_AUX_KSV_INDEX1 0x2a9c
+-#define mmDPRX_AUX_KSV_INDEX1_BASE_IDX 2
+-#define mmDPRX_AUX_KSV_DATA1 0x2a9d
+-#define mmDPRX_AUX_KSV_DATA1_BASE_IDX 2
+-#define mmDPRX_AUX_KSV_INDEX2 0x2a9e
+-#define mmDPRX_AUX_KSV_INDEX2_BASE_IDX 2
+-#define mmDPRX_AUX_KSV_DATA2 0x2a9f
+-#define mmDPRX_AUX_KSV_DATA2_BASE_IDX 2
+-#define mmDPRX_AUX_MSG_TIMEOUT_CONTROL 0x2aa0
+-#define mmDPRX_AUX_MSG_TIMEOUT_CONTROL_BASE_IDX 2
+-#define mmDPRX_AUX_MSG_BUF_CONTROL1 0x2aa1
+-#define mmDPRX_AUX_MSG_BUF_CONTROL1_BASE_IDX 2
+-#define mmDPRX_AUX_MSG_BUF_CONTROL2 0x2aa2
+-#define mmDPRX_AUX_MSG_BUF_CONTROL2_BASE_IDX 2
+-#define mmDPRX_AUX_SCRATCH1 0x2aa3
+-#define mmDPRX_AUX_SCRATCH1_BASE_IDX 2
+-#define mmDPRX_AUX_SCRATCH2 0x2aa4
+-#define mmDPRX_AUX_SCRATCH2_BASE_IDX 2
+-#define mmDPRX_AUX_MSG1_PENDING 0x2aa5
+-#define mmDPRX_AUX_MSG1_PENDING_BASE_IDX 2
+-#define mmDPRX_AUX_MSG2_PENDING 0x2aa6
+-#define mmDPRX_AUX_MSG2_PENDING_BASE_IDX 2
+-#define mmDPRX_AUX_MSG3_PENDING 0x2aa7
+-#define mmDPRX_AUX_MSG3_PENDING_BASE_IDX 2
+-#define mmDPRX_AUX_MSG4_PENDING 0x2aa8
+-#define mmDPRX_AUX_MSG4_PENDING_BASE_IDX 2
+-#define mmDPRX_DPHY_DPCD_LANE_COUNT_SET 0x2afe
+-#define mmDPRX_DPHY_DPCD_LANE_COUNT_SET_BASE_IDX 2
+-#define mmDPRX_DPHY_DPCD_TRAINING_PATTERN_SET 0x2aff
+-#define mmDPRX_DPHY_DPCD_TRAINING_PATTERN_SET_BASE_IDX 2
+-#define mmDPRX_DPHY_DPCD_MSTM_CTRL 0x2b00
+-#define mmDPRX_DPHY_DPCD_MSTM_CTRL_BASE_IDX 2
+-#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_SET 0x2b01
+-#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_SET_BASE_IDX 2
+-#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS 0x2b02
+-#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS_BASE_IDX 2
+-#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_SET 0x2b03
+-#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_SET_BASE_IDX 2
+-#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS 0x2b04
+-#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS_BASE_IDX 2
+-#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_SET 0x2b05
+-#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_SET_BASE_IDX 2
+-#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS 0x2b06
+-#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS_BASE_IDX 2
+-#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_SET 0x2b07
+-#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_SET_BASE_IDX 2
+-#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS 0x2b08
+-#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS_BASE_IDX 2
+-#define mmDPRX_DPHY_READY 0x2b09
+-#define mmDPRX_DPHY_READY_BASE_IDX 2
+-#define mmDPRX_DPHY_COMMA_STATUS 0x2b0b
+-#define mmDPRX_DPHY_COMMA_STATUS_BASE_IDX 2
+-#define mmDPRX_DPHY_LANE_ALIGN_ERROR_STATUS_UPDATED 0x2b0c
+-#define mmDPRX_DPHY_LANE_ALIGN_ERROR_STATUS_UPDATED_BASE_IDX 2
+-#define mmDPRX_DPHY_LANE_ALIGN_STATUS_UPDATED 0x2b0d
+-#define mmDPRX_DPHY_LANE_ALIGN_STATUS_UPDATED_BASE_IDX 2
+-#define mmDPRX_DPHY_ERROR_THRESH_A_LANE0 0x2b0f
+-#define mmDPRX_DPHY_ERROR_THRESH_A_LANE0_BASE_IDX 2
+-#define mmDPRX_DPHY_ERROR_COUNT_A_LANE0 0x2b11
+-#define mmDPRX_DPHY_ERROR_COUNT_A_LANE0_BASE_IDX 2
+-#define mmDPRX_DPHY_ERROR_COUNT_B_LANE0 0x2b12
+-#define mmDPRX_DPHY_ERROR_COUNT_B_LANE0_BASE_IDX 2
+-#define mmDPRX_DPHY_ERROR_COUNT_C_LANE0 0x2b13
+-#define mmDPRX_DPHY_ERROR_COUNT_C_LANE0_BASE_IDX 2
+-#define mmDPRX_DPHY_ERROR_THRESH_A_LANE1 0x2b14
+-#define mmDPRX_DPHY_ERROR_THRESH_A_LANE1_BASE_IDX 2
+-#define mmDPRX_DPHY_ERROR_COUNT_A_LANE1 0x2b16
+-#define mmDPRX_DPHY_ERROR_COUNT_A_LANE1_BASE_IDX 2
+-#define mmDPRX_DPHY_ERROR_COUNT_B_LANE1 0x2b17
+-#define mmDPRX_DPHY_ERROR_COUNT_B_LANE1_BASE_IDX 2
+-#define mmDPRX_DPHY_ERROR_COUNT_C_LANE1 0x2b18
+-#define mmDPRX_DPHY_ERROR_COUNT_C_LANE1_BASE_IDX 2
+-#define mmDPRX_DPHY_ERROR_THRESH_A_LANE2 0x2b19
+-#define mmDPRX_DPHY_ERROR_THRESH_A_LANE2_BASE_IDX 2
+-#define mmDPRX_DPHY_ERROR_COUNT_A_LANE2 0x2b1b
+-#define mmDPRX_DPHY_ERROR_COUNT_A_LANE2_BASE_IDX 2
+-#define mmDPRX_DPHY_ERROR_COUNT_B_LANE2 0x2b1c
+-#define mmDPRX_DPHY_ERROR_COUNT_B_LANE2_BASE_IDX 2
+-#define mmDPRX_DPHY_ERROR_COUNT_C_LANE2 0x2b1d
+-#define mmDPRX_DPHY_ERROR_COUNT_C_LANE2_BASE_IDX 2
+-#define mmDPRX_DPHY_ERROR_THRESH_A_LANE3 0x2b1e
+-#define mmDPRX_DPHY_ERROR_THRESH_A_LANE3_BASE_IDX 2
+-#define mmDPRX_DPHY_ERROR_COUNT_A_LANE3 0x2b20
+-#define mmDPRX_DPHY_ERROR_COUNT_A_LANE3_BASE_IDX 2
+-#define mmDPRX_DPHY_ERROR_COUNT_B_LANE3 0x2b21
+-#define mmDPRX_DPHY_ERROR_COUNT_B_LANE3_BASE_IDX 2
+-#define mmDPRX_DPHY_ERROR_COUNT_C_LANE3 0x2b22
+-#define mmDPRX_DPHY_ERROR_COUNT_C_LANE3_BASE_IDX 2
+-#define mmDPRX_DPHY_BS_ERROR_THRESH_GLOBAL 0x2b24
+-#define mmDPRX_DPHY_BS_ERROR_THRESH_GLOBAL_BASE_IDX 2
+-#define mmDPRX_DPHY_SR_ERROR_COUNT_A 0x2b25
+-#define mmDPRX_DPHY_SR_ERROR_COUNT_A_BASE_IDX 2
+-#define mmDPRX_DPHY_BS_ERROR_COUNT_A 0x2b27
+-#define mmDPRX_DPHY_BS_ERROR_COUNT_A_BASE_IDX 2
+-#define mmDPRX_DPHY_BS_ERROR_COUNT_B 0x2b28
+-#define mmDPRX_DPHY_BS_ERROR_COUNT_B_BASE_IDX 2
+-#define mmDPRX_DPHY_LANESETUP0 0x2b2d
+-#define mmDPRX_DPHY_LANESETUP0_BASE_IDX 2
+-#define mmDPRX_DPHY_LANESETUP1 0x2b2e
+-#define mmDPRX_DPHY_LANESETUP1_BASE_IDX 2
+-#define mmDPRX_DPHY_LFSRADV 0x2b31
+-#define mmDPRX_DPHY_LFSRADV_BASE_IDX 2
+-#define mmDPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT 0x2b32
+-#define mmDPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT_BASE_IDX 2
+-#define mmDPRX_DPHY_SET_ENABLE 0x2b33
+-#define mmDPRX_DPHY_SET_ENABLE_BASE_IDX 2
+-#define mmDPRX_DPHY_ECF_LSB 0x2b34
+-#define mmDPRX_DPHY_ECF_LSB_BASE_IDX 2
+-#define mmDPRX_DPHY_ECF_MSB 0x2b35
+-#define mmDPRX_DPHY_ECF_MSB_BASE_IDX 2
+-#define mmDPRX_DPHY_ENHANCED_FRAME_EN 0x2b36
+-#define mmDPRX_DPHY_ENHANCED_FRAME_EN_BASE_IDX 2
+-#define mmDPRX_DPHY_MTP_HEADER_COUNT_FORCE 0x2b3c
+-#define mmDPRX_DPHY_MTP_HEADER_COUNT_FORCE_BASE_IDX 2
+-#define mmDPRX_DPHY_DYNAMIC_DESKEW_DATA 0x2b3d
+-#define mmDPRX_DPHY_DYNAMIC_DESKEW_DATA_BASE_IDX 2
+-#define mmDPRX_DPHY_DYNAMIC_DESKEW_CONTROL 0x2b3e
+-#define mmDPRX_DPHY_DYNAMIC_DESKEW_CONTROL_BASE_IDX 2
+-#define mmDPRX_DPHY_BYPASS 0x2b3f
+-#define mmDPRX_DPHY_BYPASS_BASE_IDX 2
+-#define mmDPRX_DPHY_INT_RESET 0x2b40
+-#define mmDPRX_DPHY_INT_RESET_BASE_IDX 2
+-#define mmDPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS 0x2b41
+-#define mmDPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS_BASE_IDX 2
+-#define mmDPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS 0x2b43
+-#define mmDPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS_BASE_IDX 2
+-#define mmDPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS 0x2b44
+-#define mmDPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS_BASE_IDX 2
+-#define mmDPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS 0x2b46
+-#define mmDPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS_BASE_IDX 2
+-#define mmDPRX_DPHY_DETECT_SR_LOCK_STATUS 0x2b48
+-#define mmDPRX_DPHY_DETECT_SR_LOCK_STATUS_BASE_IDX 2
+-#define mmDPRX_DPHY_LOSS_OF_ALIGN_STATUS 0x2b49
+-#define mmDPRX_DPHY_LOSS_OF_ALIGN_STATUS_BASE_IDX 2
+-#define mmDPRX_DPHY_LOSS_OF_DESKEW_STATUS 0x2b4a
+-#define mmDPRX_DPHY_LOSS_OF_DESKEW_STATUS_BASE_IDX 2
+-#define mmDPRX_DPHY_EXCESSIVE_ERROR_STATUS 0x2b4b
+-#define mmDPRX_DPHY_EXCESSIVE_ERROR_STATUS_BASE_IDX 2
+-#define mmDPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS 0x2b4c
+-#define mmDPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS_BASE_IDX 2
+-#define mmDPRX_DPHY_SPARE 0x2b4d
+-#define mmDPRX_DPHY_SPARE_BASE_IDX 2
+-#define mmDCRX_GATE_DISABLE_CNTL 0x2b6e
+-#define mmDCRX_GATE_DISABLE_CNTL_BASE_IDX 2
+-#define mmDCRX_SOFT_RESET 0x2b6f
+-#define mmDCRX_SOFT_RESET_BASE_IDX 2
+-#define mmDCRX_LIGHT_SLEEP_CNTL 0x2b70
+-#define mmDCRX_LIGHT_SLEEP_CNTL_BASE_IDX 2
+-#define mmDCRX_DISPCLK_GATE_CNTL 0x2b73
+-#define mmDCRX_DISPCLK_GATE_CNTL_BASE_IDX 2
+-#define mmDCRX_CLK_CNTL 0x2b74
+-#define mmDCRX_CLK_CNTL_BASE_IDX 2
+-#define mmDCRX_TEST_CLK_CNTL 0x2b75
+-#define mmDCRX_TEST_CLK_CNTL_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED0 0x2c06
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED1 0x2c07
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED2 0x2c08
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED3 0x2c09
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED4 0x2c0a
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED5 0x2c0b
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED6 0x2c0c
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED7 0x2c0d
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED8 0x2c0e
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED9 0x2c0f
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED10 0x2c10
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED11 0x2c11
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED12 0x2c12
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED13 0x2c13
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED14 0x2c14
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED15 0x2c15
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED16 0x2c16
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED17 0x2c17
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED18 0x2c18
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED19 0x2c19
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED20 0x2c1a
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED21 0x2c1b
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED22 0x2c1c
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED23 0x2c1d
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED24 0x2c1e
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED25 0x2c1f
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED26 0x2c20
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED27 0x2c21
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED28 0x2c22
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED29 0x2c23
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED30 0x2c24
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED31 0x2c25
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED32 0x2c26
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED33 0x2c27
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED34 0x2c28
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED35 0x2c29
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED36 0x2c2a
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED37 0x2c2b
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED38 0x2c2c
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED39 0x2c2d
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED40 0x2c2e
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED41 0x2c2f
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED42 0x2c30
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED43 0x2c31
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED44 0x2c32
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED45 0x2c33
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED46 0x2c34
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED47 0x2c35
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED48 0x2c36
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED49 0x2c37
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED50 0x2c38
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED51 0x2c39
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED52 0x2c3a
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED53 0x2c3b
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED54 0x2c3c
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED55 0x2c3d
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED56 0x2c3e
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED57 0x2c3f
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED58 0x2c40
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED59 0x2c41
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED60 0x2c42
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED61 0x2c43
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED62 0x2c44
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED63 0x2c45
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED64 0x2c46
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED65 0x2c47
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED66 0x2c48
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED67 0x2c49
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED68 0x2c4a
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED69 0x2c4b
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED70 0x2c4c
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED71 0x2c4d
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED72 0x2c4e
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED73 0x2c4f
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED74 0x2c50
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED75 0x2c51
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED76 0x2c52
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED77 0x2c53
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED78 0x2c54
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED79 0x2c55
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED80 0x2c56
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED81 0x2c57
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED82 0x2c58
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED83 0x2c59
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED84 0x2c5a
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED85 0x2c5b
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED86 0x2c5c
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED87 0x2c5d
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED88 0x2c5e
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED89 0x2c5f
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED90 0x2c60
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED91 0x2c61
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED92 0x2c62
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED93 0x2c63
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED94 0x2c64
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED95 0x2c65
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED96 0x2c66
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED97 0x2c67
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED98 0x2c68
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED99 0x2c69
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED100 0x2c6a
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED101 0x2c6b
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED102 0x2c6c
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED103 0x2c6d
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED104 0x2c6e
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED105 0x2c6f
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED106 0x2c70
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED107 0x2c71
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED108 0x2c72
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED109 0x2c73
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED110 0x2c74
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED111 0x2c75
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED112 0x2c76
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED113 0x2c77
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED114 0x2c78
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED115 0x2c79
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED116 0x2c7a
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED117 0x2c7b
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED118 0x2c7c
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED119 0x2c7d
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED120 0x2c7e
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED121 0x2c7f
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED122 0x2c80
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED123 0x2c81
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED124 0x2c82
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED125 0x2c83
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED126 0x2c84
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED127 0x2c85
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED128 0x2c86
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED129 0x2c87
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED130 0x2c88
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED131 0x2c89
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED132 0x2c8a
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED133 0x2c8b
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED134 0x2c8c
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED135 0x2c8d
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED136 0x2c8e
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED137 0x2c8f
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED138 0x2c90
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED139 0x2c91
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED140 0x2c92
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED141 0x2c93
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED142 0x2c94
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED143 0x2c95
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED144 0x2c96
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED145 0x2c97
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED146 0x2c98
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED147 0x2c99
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED148 0x2c9a
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED149 0x2c9b
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED150 0x2c9c
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED151 0x2c9d
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED152 0x2c9e
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED153 0x2c9f
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED154 0x2ca0
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED155 0x2ca1
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED156 0x2ca2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED157 0x2ca3
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED158 0x2ca4
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED159 0x2ca5
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED160 0x2ca6
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED160_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED161 0x2ca7
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED161_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED162 0x2ca8
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED162_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED163 0x2ca9
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED163_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED164 0x2caa
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED164_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED165 0x2cab
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED165_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED166 0x2cac
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED166_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED167 0x2cad
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED167_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED168 0x2cae
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED168_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED169 0x2caf
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED169_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED170 0x2cb0
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED170_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED171 0x2cb1
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED171_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED172 0x2cb2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED172_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED173 0x2cb3
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED173_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED174 0x2cb4
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED174_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED175 0x2cb5
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED175_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED176 0x2cb6
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED176_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED177 0x2cb7
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED177_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED178 0x2cb8
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED178_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED179 0x2cb9
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED179_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED180 0x2cba
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED180_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED181 0x2cbb
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED181_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED182 0x2cbc
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED182_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED183 0x2cbd
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED183_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED184 0x2cbe
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED184_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED185 0x2cbf
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED185_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED186 0x2cc0
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED186_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED187 0x2cc1
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED187_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED188 0x2cc2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED188_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED189 0x2cc3
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED189_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED190 0x2cc4
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED190_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED191 0x2cc5
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED191_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED192 0x2cc6
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED192_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED193 0x2cc7
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED193_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED194 0x2cc8
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED194_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED195 0x2cc9
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED195_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED196 0x2cca
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED196_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED197 0x2ccb
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED197_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED198 0x2ccc
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED198_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED199 0x2ccd
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED199_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED200 0x2cce
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED200_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED201 0x2ccf
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED201_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED202 0x2cd0
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED202_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED203 0x2cd1
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED203_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED204 0x2cd2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED204_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED205 0x2cd3
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED205_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED206 0x2cd4
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED206_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED207 0x2cd5
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED207_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED208 0x2cd6
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED208_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED209 0x2cd7
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED209_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED210 0x2cd8
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED210_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED211 0x2cd9
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED211_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED212 0x2cda
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED212_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED213 0x2cdb
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED213_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED214 0x2cdc
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED214_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED215 0x2cdd
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED215_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED216 0x2cde
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED216_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED217 0x2cdf
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED217_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED218 0x2ce0
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED218_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED219 0x2ce1
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED219_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED220 0x2ce2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED220_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED221 0x2ce3
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED221_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED222 0x2ce4
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED222_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED223 0x2ce5
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED223_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED224 0x2ce6
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED224_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED225 0x2ce7
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED225_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED226 0x2ce8
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED226_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED227 0x2ce9
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED227_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED228 0x2cea
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED228_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED229 0x2ceb
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED229_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED230 0x2cec
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED230_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED231 0x2ced
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED231_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED232 0x2cee
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED232_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED233 0x2cef
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED233_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED234 0x2cf0
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED234_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED235 0x2cf1
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED235_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED236 0x2cf2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED236_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED237 0x2cf3
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED237_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED238 0x2cf4
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED238_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED239 0x2cf5
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED239_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED240 0x2cf6
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED240_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED241 0x2cf7
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED241_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED242 0x2cf8
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED242_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED243 0x2cf9
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED243_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED244 0x2cfa
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED244_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED245 0x2cfb
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED245_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED246 0x2cfc
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED246_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED247 0x2cfd
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED247_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED248 0x2cfe
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED248_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED249 0x2cff
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED249_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED250 0x2d00
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED250_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED251 0x2d01
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED251_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED252 0x2d02
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED252_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED253 0x2d03
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED253_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED254 0x2d04
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED254_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED255 0x2d05
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED255_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED256 0x2d06
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED256_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED257 0x2d07
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED257_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED258 0x2d08
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED258_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED259 0x2d09
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED259_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED260 0x2d0a
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED260_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED261 0x2d0b
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED261_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED262 0x2d0c
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED262_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED263 0x2d0d
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED263_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED264 0x2d0e
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED264_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED265 0x2d0f
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED265_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED266 0x2d10
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED266_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED267 0x2d11
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED267_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED268 0x2d12
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED268_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED269 0x2d13
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED269_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED270 0x2d14
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED270_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED271 0x2d15
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED271_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED272 0x2d16
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED272_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED273 0x2d17
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED273_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED274 0x2d18
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED274_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED275 0x2d19
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED275_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED276 0x2d1a
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED276_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED277 0x2d1b
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED277_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED278 0x2d1c
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED278_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED279 0x2d1d
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED279_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED280 0x2d1e
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED280_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED281 0x2d1f
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED281_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED282 0x2d20
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED282_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED283 0x2d21
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED283_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED284 0x2d22
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED284_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED285 0x2d23
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED285_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED286 0x2d24
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED286_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED287 0x2d25
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED287_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED288 0x2d26
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED288_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED289 0x2d27
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED289_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED290 0x2d28
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED290_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED291 0x2d29
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED291_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED292 0x2d2a
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED292_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED293 0x2d2b
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED293_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED294 0x2d2c
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED294_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED295 0x2d2d
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED295_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED296 0x2d2e
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED296_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED297 0x2d2f
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED297_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED298 0x2d30
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED298_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED299 0x2d31
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED299_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED300 0x2d32
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED300_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED301 0x2d33
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED301_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED302 0x2d34
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED302_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED303 0x2d35
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED303_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED304 0x2d36
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED304_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED305 0x2d37
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED305_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED306 0x2d38
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED306_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED307 0x2d39
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED307_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED308 0x2d3a
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED308_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED309 0x2d3b
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED309_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED310 0x2d3c
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED310_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED311 0x2d3d
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED311_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED312 0x2d3e
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED312_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED313 0x2d3f
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED313_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED314 0x2d40
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED314_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED315 0x2d41
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED315_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED316 0x2d42
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED316_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED317 0x2d43
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED317_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED318 0x2d44
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED318_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED319 0x2d45
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED319_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED320 0x2d46
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED320_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED321 0x2d47
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED321_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED322 0x2d48
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED322_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED323 0x2d49
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED323_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED324 0x2d4a
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED324_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED325 0x2d4b
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED325_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED326 0x2d4c
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED326_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED327 0x2d4d
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED327_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED328 0x2d4e
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED328_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED329 0x2d4f
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED329_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED330 0x2d50
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED330_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED331 0x2d51
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED331_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED332 0x2d52
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED332_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED333 0x2d53
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED333_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED334 0x2d54
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED334_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED335 0x2d55
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED335_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED336 0x2d56
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED336_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED337 0x2d57
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED337_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED338 0x2d58
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED338_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED339 0x2d59
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED339_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED340 0x2d5a
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED340_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED341 0x2d5b
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED341_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED342 0x2d5c
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED342_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED343 0x2d5d
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED343_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED344 0x2d5e
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED344_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED345 0x2d5f
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED345_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED346 0x2d60
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED346_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED347 0x2d61
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED347_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED348 0x2d62
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED348_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED349 0x2d63
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED349_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED350 0x2d64
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED350_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED351 0x2d65
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED351_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED352 0x2d66
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED352_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED353 0x2d67
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED353_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED354 0x2d68
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED354_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED355 0x2d69
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED355_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED356 0x2d6a
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED356_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED357 0x2d6b
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED357_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED358 0x2d6c
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED358_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED359 0x2d6d
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED359_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED360 0x2d6e
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED360_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED361 0x2d6f
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED361_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED362 0x2d70
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED362_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED363 0x2d71
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED363_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED364 0x2d72
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED364_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED365 0x2d73
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED365_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED366 0x2d74
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED366_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED367 0x2d75
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED367_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED368 0x2d76
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED368_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED369 0x2d77
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED369_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED370 0x2d78
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED370_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED371 0x2d79
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED371_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED372 0x2d7a
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED372_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED373 0x2d7b
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED373_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED374 0x2d7c
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED374_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED375 0x2d7d
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED375_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED376 0x2d7e
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED376_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED377 0x2d7f
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED377_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED378 0x2d80
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED378_BASE_IDX 2
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED379 0x2d81
+-#define mmDCRX_PHY_MACRO_CNTL_RESERVED379_BASE_IDX 2
+-#define mmI2S0_CNTL 0x2d82
+-#define mmI2S0_CNTL_BASE_IDX 2
+-#define mmSPDIF0_CNTL 0x2d83
+-#define mmSPDIF0_CNTL_BASE_IDX 2
+-#define mmI2S1_CNTL 0x2d84
+-#define mmI2S1_CNTL_BASE_IDX 2
+-#define mmSPDIF1_CNTL 0x2d85
+-#define mmSPDIF1_CNTL_BASE_IDX 2
+-#define mmI2S0_STATUS 0x2d86
+-#define mmI2S0_STATUS_BASE_IDX 2
+-#define mmI2S1_STATUS 0x2d87
+-#define mmI2S1_STATUS_BASE_IDX 2
+-#define mmI2S0_CRC_TEST_CNTL 0x2d8a
+-#define mmI2S0_CRC_TEST_CNTL_BASE_IDX 2
+-#define mmI2S0_CRC_TEST_DATA_01 0x2d8b
+-#define mmI2S0_CRC_TEST_DATA_01_BASE_IDX 2
+-#define mmI2S0_CRC_TEST_DATA_23 0x2d8c
+-#define mmI2S0_CRC_TEST_DATA_23_BASE_IDX 2
+-#define mmI2S1_CRC_TEST_CNTL 0x2d8d
+-#define mmI2S1_CRC_TEST_CNTL_BASE_IDX 2
+-#define mmI2S1_CRC_TEST_DATA_0 0x2d8e
+-#define mmI2S1_CRC_TEST_DATA_0_BASE_IDX 2
+-#define mmSPDIF0_CRC_TEST_CNTL 0x2d8f
+-#define mmSPDIF0_CRC_TEST_CNTL_BASE_IDX 2
+-#define mmSPDIF0_CRC_TEST_DATA_0 0x2d90
+-#define mmSPDIF0_CRC_TEST_DATA_0_BASE_IDX 2
+-#define mmSPDIF1_CRC_TEST_CNTL 0x2d91
+-#define mmSPDIF1_CRC_TEST_CNTL_BASE_IDX 2
+-#define mmSPDIF1_CRC_TEST_DATA 0x2d92
+-#define mmSPDIF1_CRC_TEST_DATA_BASE_IDX 2
+-#define mmCRC_I2S_CONT_REPEAT_NUM 0x2d93
+-#define mmCRC_I2S_CONT_REPEAT_NUM_BASE_IDX 2
+-#define mmCRC_SPDIF_CONT_REPEAT_NUM 0x2d94
+-#define mmCRC_SPDIF_CONT_REPEAT_NUM_BASE_IDX 2
+-#define mmZCAL_MACRO_CNTL_RESERVED0 0x2d96
+-#define mmZCAL_MACRO_CNTL_RESERVED0_BASE_IDX 2
+-#define mmZCAL_MACRO_CNTL_RESERVED1 0x2d97
+-#define mmZCAL_MACRO_CNTL_RESERVED1_BASE_IDX 2
+-#define mmZCAL_MACRO_CNTL_RESERVED2 0x2d98
+-#define mmZCAL_MACRO_CNTL_RESERVED2_BASE_IDX 2
+-#define mmZCAL_MACRO_CNTL_RESERVED3 0x2d99
+-#define mmZCAL_MACRO_CNTL_RESERVED3_BASE_IDX 2
+-#define mmZCAL_MACRO_CNTL_RESERVED4 0x2d9a
+-#define mmZCAL_MACRO_CNTL_RESERVED4_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_azf0stream0_dispdec
+-// base address: 0x0
+-#define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x0458
+-#define mmAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2
+-#define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x0459
+-#define mmAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_azf0stream1_dispdec
+-// base address: 0x8
+-#define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x045a
+-#define mmAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2
+-#define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x045b
+-#define mmAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_azf0stream2_dispdec
+-// base address: 0x10
+-#define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x045c
+-#define mmAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2
+-#define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x045d
+-#define mmAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_azf0stream3_dispdec
+-// base address: 0x18
+-#define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x045e
+-#define mmAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2
+-#define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x045f
+-#define mmAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_azf0stream4_dispdec
+-// base address: 0x20
+-#define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x0460
+-#define mmAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2
+-#define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x0461
+-#define mmAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_azf0stream5_dispdec
+-// base address: 0x28
+-#define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x0462
+-#define mmAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2
+-#define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x0463
+-#define mmAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_azf0stream6_dispdec
+-// base address: 0x30
+-#define mmAZF0STREAM6_AZALIA_STREAM_INDEX 0x0464
+-#define mmAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2
+-#define mmAZF0STREAM6_AZALIA_STREAM_DATA 0x0465
+-#define mmAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_azf0stream7_dispdec
+-// base address: 0x38
+-#define mmAZF0STREAM7_AZALIA_STREAM_INDEX 0x0466
+-#define mmAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2
+-#define mmAZF0STREAM7_AZALIA_STREAM_DATA 0x0467
+-#define mmAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_azf0endpoint0_dispdec
+-// base address: 0x0
+-#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0480
+-#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
+-#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0481
+-#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_azf0endpoint1_dispdec
+-// base address: 0x18
+-#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0486
+-#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
+-#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0487
+-#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_azf0endpoint2_dispdec
+-// base address: 0x30
+-#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x048c
+-#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
+-#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x048d
+-#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_azf0endpoint3_dispdec
+-// base address: 0x48
+-#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0492
+-#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
+-#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0493
+-#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_azf0endpoint4_dispdec
+-// base address: 0x60
+-#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0498
+-#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
+-#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0499
+-#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_azf0endpoint5_dispdec
+-// base address: 0x78
+-#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x049e
+-#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
+-#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x049f
+-#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_azf0endpoint6_dispdec
+-// base address: 0x90
+-#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x04a4
+-#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
+-#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x04a5
+-#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_azf0endpoint7_dispdec
+-// base address: 0xa8
+-#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x04aa
+-#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
+-#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x04ab
+-#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_azf0stream8_dispdec
+-// base address: 0x320
+-#define mmAZF0STREAM8_AZALIA_STREAM_INDEX 0x0520
+-#define mmAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2
+-#define mmAZF0STREAM8_AZALIA_STREAM_DATA 0x0521
+-#define mmAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_azf0stream9_dispdec
+-// base address: 0x328
+-#define mmAZF0STREAM9_AZALIA_STREAM_INDEX 0x0522
+-#define mmAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2
+-#define mmAZF0STREAM9_AZALIA_STREAM_DATA 0x0523
+-#define mmAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_azf0stream10_dispdec
+-// base address: 0x330
+-#define mmAZF0STREAM10_AZALIA_STREAM_INDEX 0x0524
+-#define mmAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2
+-#define mmAZF0STREAM10_AZALIA_STREAM_DATA 0x0525
+-#define mmAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_azf0stream11_dispdec
+-// base address: 0x338
+-#define mmAZF0STREAM11_AZALIA_STREAM_INDEX 0x0526
+-#define mmAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2
+-#define mmAZF0STREAM11_AZALIA_STREAM_DATA 0x0527
+-#define mmAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_azf0stream12_dispdec
+-// base address: 0x340
+-#define mmAZF0STREAM12_AZALIA_STREAM_INDEX 0x0528
+-#define mmAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2
+-#define mmAZF0STREAM12_AZALIA_STREAM_DATA 0x0529
+-#define mmAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_azf0stream13_dispdec
+-// base address: 0x348
+-#define mmAZF0STREAM13_AZALIA_STREAM_INDEX 0x052a
+-#define mmAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2
+-#define mmAZF0STREAM13_AZALIA_STREAM_DATA 0x052b
+-#define mmAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_azf0stream14_dispdec
+-// base address: 0x350
+-#define mmAZF0STREAM14_AZALIA_STREAM_INDEX 0x052c
+-#define mmAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2
+-#define mmAZF0STREAM14_AZALIA_STREAM_DATA 0x052d
+-#define mmAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_azf0stream15_dispdec
+-// base address: 0x358
+-#define mmAZF0STREAM15_AZALIA_STREAM_INDEX 0x052e
+-#define mmAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2
+-#define mmAZF0STREAM15_AZALIA_STREAM_DATA 0x052f
+-#define mmAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_azf0inputendpoint0_dispdec
+-// base address: 0x0
+-#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0534
+-#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
+-#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0535
+-#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_azf0inputendpoint1_dispdec
+-// base address: 0x10
+-#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0538
+-#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
+-#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0539
+-#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_azf0inputendpoint2_dispdec
+-// base address: 0x20
+-#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x053c
+-#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
+-#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x053d
+-#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_azf0inputendpoint3_dispdec
+-// base address: 0x30
+-#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0540
+-#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
+-#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0541
+-#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_azf0inputendpoint4_dispdec
+-// base address: 0x40
+-#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0544
+-#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
+-#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0545
+-#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_azf0inputendpoint5_dispdec
+-// base address: 0x50
+-#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0548
+-#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
+-#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0549
+-#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_azf0inputendpoint6_dispdec
+-// base address: 0x60
+-#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x054c
+-#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
+-#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x054d
+-#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_azf0inputendpoint7_dispdec
+-// base address: 0x70
+-#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0550
+-#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
+-#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0551
+-#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dcp0_dispdec
+-// base address: 0x0
+-#define mmDCP0_GRPH_ENABLE 0x055a
+-#define mmDCP0_GRPH_ENABLE_BASE_IDX 2
+-#define mmDCP0_GRPH_CONTROL 0x055b
+-#define mmDCP0_GRPH_CONTROL_BASE_IDX 2
+-#define mmDCP0_GRPH_LUT_10BIT_BYPASS 0x055c
+-#define mmDCP0_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2
+-#define mmDCP0_GRPH_SWAP_CNTL 0x055d
+-#define mmDCP0_GRPH_SWAP_CNTL_BASE_IDX 2
+-#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS 0x055e
+-#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
+-#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS 0x055f
+-#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
+-#define mmDCP0_GRPH_PITCH 0x0560
+-#define mmDCP0_GRPH_PITCH_BASE_IDX 2
+-#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0561
+-#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+-#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0562
+-#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+-#define mmDCP0_GRPH_SURFACE_OFFSET_X 0x0563
+-#define mmDCP0_GRPH_SURFACE_OFFSET_X_BASE_IDX 2
+-#define mmDCP0_GRPH_SURFACE_OFFSET_Y 0x0564
+-#define mmDCP0_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2
+-#define mmDCP0_GRPH_X_START 0x0565
+-#define mmDCP0_GRPH_X_START_BASE_IDX 2
+-#define mmDCP0_GRPH_Y_START 0x0566
+-#define mmDCP0_GRPH_Y_START_BASE_IDX 2
+-#define mmDCP0_GRPH_X_END 0x0567
+-#define mmDCP0_GRPH_X_END_BASE_IDX 2
+-#define mmDCP0_GRPH_Y_END 0x0568
+-#define mmDCP0_GRPH_Y_END_BASE_IDX 2
+-#define mmDCP0_INPUT_GAMMA_CONTROL 0x0569
+-#define mmDCP0_INPUT_GAMMA_CONTROL_BASE_IDX 2
+-#define mmDCP0_GRPH_UPDATE 0x056a
+-#define mmDCP0_GRPH_UPDATE_BASE_IDX 2
+-#define mmDCP0_GRPH_FLIP_CONTROL 0x056b
+-#define mmDCP0_GRPH_FLIP_CONTROL_BASE_IDX 2
+-#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE 0x056c
+-#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2
+-#define mmDCP0_GRPH_DFQ_CONTROL 0x056d
+-#define mmDCP0_GRPH_DFQ_CONTROL_BASE_IDX 2
+-#define mmDCP0_GRPH_DFQ_STATUS 0x056e
+-#define mmDCP0_GRPH_DFQ_STATUS_BASE_IDX 2
+-#define mmDCP0_GRPH_INTERRUPT_STATUS 0x056f
+-#define mmDCP0_GRPH_INTERRUPT_STATUS_BASE_IDX 2
+-#define mmDCP0_GRPH_INTERRUPT_CONTROL 0x0570
+-#define mmDCP0_GRPH_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0571
+-#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2
+-#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS 0x0572
+-#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2
+-#define mmDCP0_GRPH_COMPRESS_PITCH 0x0573
+-#define mmDCP0_GRPH_COMPRESS_PITCH_BASE_IDX 2
+-#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0574
+-#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+-#define mmDCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0575
+-#define mmDCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2
+-#define mmDCP0_PRESCALE_GRPH_CONTROL 0x0576
+-#define mmDCP0_PRESCALE_GRPH_CONTROL_BASE_IDX 2
+-#define mmDCP0_PRESCALE_VALUES_GRPH_R 0x0577
+-#define mmDCP0_PRESCALE_VALUES_GRPH_R_BASE_IDX 2
+-#define mmDCP0_PRESCALE_VALUES_GRPH_G 0x0578
+-#define mmDCP0_PRESCALE_VALUES_GRPH_G_BASE_IDX 2
+-#define mmDCP0_PRESCALE_VALUES_GRPH_B 0x0579
+-#define mmDCP0_PRESCALE_VALUES_GRPH_B_BASE_IDX 2
+-#define mmDCP0_INPUT_CSC_CONTROL 0x057a
+-#define mmDCP0_INPUT_CSC_CONTROL_BASE_IDX 2
+-#define mmDCP0_INPUT_CSC_C11_C12 0x057b
+-#define mmDCP0_INPUT_CSC_C11_C12_BASE_IDX 2
+-#define mmDCP0_INPUT_CSC_C13_C14 0x057c
+-#define mmDCP0_INPUT_CSC_C13_C14_BASE_IDX 2
+-#define mmDCP0_INPUT_CSC_C21_C22 0x057d
+-#define mmDCP0_INPUT_CSC_C21_C22_BASE_IDX 2
+-#define mmDCP0_INPUT_CSC_C23_C24 0x057e
+-#define mmDCP0_INPUT_CSC_C23_C24_BASE_IDX 2
+-#define mmDCP0_INPUT_CSC_C31_C32 0x057f
+-#define mmDCP0_INPUT_CSC_C31_C32_BASE_IDX 2
+-#define mmDCP0_INPUT_CSC_C33_C34 0x0580
+-#define mmDCP0_INPUT_CSC_C33_C34_BASE_IDX 2
+-#define mmDCP0_OUTPUT_CSC_CONTROL 0x0581
+-#define mmDCP0_OUTPUT_CSC_CONTROL_BASE_IDX 2
+-#define mmDCP0_OUTPUT_CSC_C11_C12 0x0582
+-#define mmDCP0_OUTPUT_CSC_C11_C12_BASE_IDX 2
+-#define mmDCP0_OUTPUT_CSC_C13_C14 0x0583
+-#define mmDCP0_OUTPUT_CSC_C13_C14_BASE_IDX 2
+-#define mmDCP0_OUTPUT_CSC_C21_C22 0x0584
+-#define mmDCP0_OUTPUT_CSC_C21_C22_BASE_IDX 2
+-#define mmDCP0_OUTPUT_CSC_C23_C24 0x0585
+-#define mmDCP0_OUTPUT_CSC_C23_C24_BASE_IDX 2
+-#define mmDCP0_OUTPUT_CSC_C31_C32 0x0586
+-#define mmDCP0_OUTPUT_CSC_C31_C32_BASE_IDX 2
+-#define mmDCP0_OUTPUT_CSC_C33_C34 0x0587
+-#define mmDCP0_OUTPUT_CSC_C33_C34_BASE_IDX 2
+-#define mmDCP0_COMM_MATRIXA_TRANS_C11_C12 0x0588
+-#define mmDCP0_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2
+-#define mmDCP0_COMM_MATRIXA_TRANS_C13_C14 0x0589
+-#define mmDCP0_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2
+-#define mmDCP0_COMM_MATRIXA_TRANS_C21_C22 0x058a
+-#define mmDCP0_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2
+-#define mmDCP0_COMM_MATRIXA_TRANS_C23_C24 0x058b
+-#define mmDCP0_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2
+-#define mmDCP0_COMM_MATRIXA_TRANS_C31_C32 0x058c
+-#define mmDCP0_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2
+-#define mmDCP0_COMM_MATRIXA_TRANS_C33_C34 0x058d
+-#define mmDCP0_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2
+-#define mmDCP0_COMM_MATRIXB_TRANS_C11_C12 0x058e
+-#define mmDCP0_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2
+-#define mmDCP0_COMM_MATRIXB_TRANS_C13_C14 0x058f
+-#define mmDCP0_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2
+-#define mmDCP0_COMM_MATRIXB_TRANS_C21_C22 0x0590
+-#define mmDCP0_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2
+-#define mmDCP0_COMM_MATRIXB_TRANS_C23_C24 0x0591
+-#define mmDCP0_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2
+-#define mmDCP0_COMM_MATRIXB_TRANS_C31_C32 0x0592
+-#define mmDCP0_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2
+-#define mmDCP0_COMM_MATRIXB_TRANS_C33_C34 0x0593
+-#define mmDCP0_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2
+-#define mmDCP0_DENORM_CONTROL 0x0594
+-#define mmDCP0_DENORM_CONTROL_BASE_IDX 2
+-#define mmDCP0_OUT_ROUND_CONTROL 0x0595
+-#define mmDCP0_OUT_ROUND_CONTROL_BASE_IDX 2
+-#define mmDCP0_OUT_CLAMP_CONTROL_R_CR 0x0596
+-#define mmDCP0_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2
+-#define mmDCP0_OUT_CLAMP_CONTROL_G_Y 0x0597
+-#define mmDCP0_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2
+-#define mmDCP0_OUT_CLAMP_CONTROL_B_CB 0x0598
+-#define mmDCP0_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2
+-#define mmDCP0_KEY_CONTROL 0x0599
+-#define mmDCP0_KEY_CONTROL_BASE_IDX 2
+-#define mmDCP0_KEY_RANGE_ALPHA 0x059a
+-#define mmDCP0_KEY_RANGE_ALPHA_BASE_IDX 2
+-#define mmDCP0_KEY_RANGE_RED 0x059b
+-#define mmDCP0_KEY_RANGE_RED_BASE_IDX 2
+-#define mmDCP0_KEY_RANGE_GREEN 0x059c
+-#define mmDCP0_KEY_RANGE_GREEN_BASE_IDX 2
+-#define mmDCP0_KEY_RANGE_BLUE 0x059d
+-#define mmDCP0_KEY_RANGE_BLUE_BASE_IDX 2
+-#define mmDCP0_DEGAMMA_CONTROL 0x059e
+-#define mmDCP0_DEGAMMA_CONTROL_BASE_IDX 2
+-#define mmDCP0_GAMUT_REMAP_CONTROL 0x059f
+-#define mmDCP0_GAMUT_REMAP_CONTROL_BASE_IDX 2
+-#define mmDCP0_GAMUT_REMAP_C11_C12 0x05a0
+-#define mmDCP0_GAMUT_REMAP_C11_C12_BASE_IDX 2
+-#define mmDCP0_GAMUT_REMAP_C13_C14 0x05a1
+-#define mmDCP0_GAMUT_REMAP_C13_C14_BASE_IDX 2
+-#define mmDCP0_GAMUT_REMAP_C21_C22 0x05a2
+-#define mmDCP0_GAMUT_REMAP_C21_C22_BASE_IDX 2
+-#define mmDCP0_GAMUT_REMAP_C23_C24 0x05a3
+-#define mmDCP0_GAMUT_REMAP_C23_C24_BASE_IDX 2
+-#define mmDCP0_GAMUT_REMAP_C31_C32 0x05a4
+-#define mmDCP0_GAMUT_REMAP_C31_C32_BASE_IDX 2
+-#define mmDCP0_GAMUT_REMAP_C33_C34 0x05a5
+-#define mmDCP0_GAMUT_REMAP_C33_C34_BASE_IDX 2
+-#define mmDCP0_DCP_SPATIAL_DITHER_CNTL 0x05a6
+-#define mmDCP0_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2
+-#define mmDCP0_DCP_RANDOM_SEEDS 0x05a7
+-#define mmDCP0_DCP_RANDOM_SEEDS_BASE_IDX 2
+-#define mmDCP0_DCP_FP_CONVERTED_FIELD 0x05a8
+-#define mmDCP0_DCP_FP_CONVERTED_FIELD_BASE_IDX 2
+-#define mmDCP0_CUR_CONTROL 0x05a9
+-#define mmDCP0_CUR_CONTROL_BASE_IDX 2
+-#define mmDCP0_CUR_SURFACE_ADDRESS 0x05aa
+-#define mmDCP0_CUR_SURFACE_ADDRESS_BASE_IDX 2
+-#define mmDCP0_CUR_SIZE 0x05ab
+-#define mmDCP0_CUR_SIZE_BASE_IDX 2
+-#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH 0x05ac
+-#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+-#define mmDCP0_CUR_POSITION 0x05ad
+-#define mmDCP0_CUR_POSITION_BASE_IDX 2
+-#define mmDCP0_CUR_HOT_SPOT 0x05ae
+-#define mmDCP0_CUR_HOT_SPOT_BASE_IDX 2
+-#define mmDCP0_CUR_COLOR1 0x05af
+-#define mmDCP0_CUR_COLOR1_BASE_IDX 2
+-#define mmDCP0_CUR_COLOR2 0x05b0
+-#define mmDCP0_CUR_COLOR2_BASE_IDX 2
+-#define mmDCP0_CUR_UPDATE 0x05b1
+-#define mmDCP0_CUR_UPDATE_BASE_IDX 2
+-#define mmDCP0_CUR_REQUEST_FILTER_CNTL 0x05bb
+-#define mmDCP0_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2
+-#define mmDCP0_CUR_STEREO_CONTROL 0x05bc
+-#define mmDCP0_CUR_STEREO_CONTROL_BASE_IDX 2
+-#define mmDCP0_DC_LUT_RW_MODE 0x05be
+-#define mmDCP0_DC_LUT_RW_MODE_BASE_IDX 2
+-#define mmDCP0_DC_LUT_RW_INDEX 0x05bf
+-#define mmDCP0_DC_LUT_RW_INDEX_BASE_IDX 2
+-#define mmDCP0_DC_LUT_SEQ_COLOR 0x05c0
+-#define mmDCP0_DC_LUT_SEQ_COLOR_BASE_IDX 2
+-#define mmDCP0_DC_LUT_PWL_DATA 0x05c1
+-#define mmDCP0_DC_LUT_PWL_DATA_BASE_IDX 2
+-#define mmDCP0_DC_LUT_30_COLOR 0x05c2
+-#define mmDCP0_DC_LUT_30_COLOR_BASE_IDX 2
+-#define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE 0x05c3
+-#define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2
+-#define mmDCP0_DC_LUT_WRITE_EN_MASK 0x05c4
+-#define mmDCP0_DC_LUT_WRITE_EN_MASK_BASE_IDX 2
+-#define mmDCP0_DC_LUT_AUTOFILL 0x05c5
+-#define mmDCP0_DC_LUT_AUTOFILL_BASE_IDX 2
+-#define mmDCP0_DC_LUT_CONTROL 0x05c6
+-#define mmDCP0_DC_LUT_CONTROL_BASE_IDX 2
+-#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE 0x05c7
+-#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2
+-#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN 0x05c8
+-#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2
+-#define mmDCP0_DC_LUT_BLACK_OFFSET_RED 0x05c9
+-#define mmDCP0_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2
+-#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE 0x05ca
+-#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2
+-#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN 0x05cb
+-#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2
+-#define mmDCP0_DC_LUT_WHITE_OFFSET_RED 0x05cc
+-#define mmDCP0_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2
+-#define mmDCP0_DCP_CRC_CONTROL 0x05cd
+-#define mmDCP0_DCP_CRC_CONTROL_BASE_IDX 2
+-#define mmDCP0_DCP_CRC_MASK 0x05ce
+-#define mmDCP0_DCP_CRC_MASK_BASE_IDX 2
+-#define mmDCP0_DCP_CRC_CURRENT 0x05cf
+-#define mmDCP0_DCP_CRC_CURRENT_BASE_IDX 2
+-#define mmDCP0_DVMM_PTE_CONTROL 0x05d0
+-#define mmDCP0_DVMM_PTE_CONTROL_BASE_IDX 2
+-#define mmDCP0_DCP_CRC_LAST 0x05d1
+-#define mmDCP0_DCP_CRC_LAST_BASE_IDX 2
+-#define mmDCP0_DVMM_PTE_ARB_CONTROL 0x05d2
+-#define mmDCP0_DVMM_PTE_ARB_CONTROL_BASE_IDX 2
+-#define mmDCP0_GRPH_FLIP_RATE_CNTL 0x05d4
+-#define mmDCP0_GRPH_FLIP_RATE_CNTL_BASE_IDX 2
+-#define mmDCP0_DCP_GSL_CONTROL 0x05d5
+-#define mmDCP0_DCP_GSL_CONTROL_BASE_IDX 2
+-#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x05d6
+-#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2
+-#define mmDCP0_GRPH_STEREOSYNC_FLIP 0x05dc
+-#define mmDCP0_GRPH_STEREOSYNC_FLIP_BASE_IDX 2
+-#define mmDCP0_HW_ROTATION 0x05de
+-#define mmDCP0_HW_ROTATION_BASE_IDX 2
+-#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x05df
+-#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2
+-#define mmDCP0_REGAMMA_CONTROL 0x05e0
+-#define mmDCP0_REGAMMA_CONTROL_BASE_IDX 2
+-#define mmDCP0_REGAMMA_LUT_INDEX 0x05e1
+-#define mmDCP0_REGAMMA_LUT_INDEX_BASE_IDX 2
+-#define mmDCP0_REGAMMA_LUT_DATA 0x05e2
+-#define mmDCP0_REGAMMA_LUT_DATA_BASE_IDX 2
+-#define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK 0x05e3
+-#define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2
+-#define mmDCP0_REGAMMA_CNTLA_START_CNTL 0x05e4
+-#define mmDCP0_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2
+-#define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL 0x05e5
+-#define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2
+-#define mmDCP0_REGAMMA_CNTLA_END_CNTL1 0x05e6
+-#define mmDCP0_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2
+-#define mmDCP0_REGAMMA_CNTLA_END_CNTL2 0x05e7
+-#define mmDCP0_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2
+-#define mmDCP0_REGAMMA_CNTLA_REGION_0_1 0x05e8
+-#define mmDCP0_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2
+-#define mmDCP0_REGAMMA_CNTLA_REGION_2_3 0x05e9
+-#define mmDCP0_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2
+-#define mmDCP0_REGAMMA_CNTLA_REGION_4_5 0x05ea
+-#define mmDCP0_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2
+-#define mmDCP0_REGAMMA_CNTLA_REGION_6_7 0x05eb
+-#define mmDCP0_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2
+-#define mmDCP0_REGAMMA_CNTLA_REGION_8_9 0x05ec
+-#define mmDCP0_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2
+-#define mmDCP0_REGAMMA_CNTLA_REGION_10_11 0x05ed
+-#define mmDCP0_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2
+-#define mmDCP0_REGAMMA_CNTLA_REGION_12_13 0x05ee
+-#define mmDCP0_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2
+-#define mmDCP0_REGAMMA_CNTLA_REGION_14_15 0x05ef
+-#define mmDCP0_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2
+-#define mmDCP0_REGAMMA_CNTLB_START_CNTL 0x05f0
+-#define mmDCP0_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2
+-#define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL 0x05f1
+-#define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2
+-#define mmDCP0_REGAMMA_CNTLB_END_CNTL1 0x05f2
+-#define mmDCP0_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2
+-#define mmDCP0_REGAMMA_CNTLB_END_CNTL2 0x05f3
+-#define mmDCP0_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2
+-#define mmDCP0_REGAMMA_CNTLB_REGION_0_1 0x05f4
+-#define mmDCP0_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2
+-#define mmDCP0_REGAMMA_CNTLB_REGION_2_3 0x05f5
+-#define mmDCP0_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2
+-#define mmDCP0_REGAMMA_CNTLB_REGION_4_5 0x05f6
+-#define mmDCP0_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2
+-#define mmDCP0_REGAMMA_CNTLB_REGION_6_7 0x05f7
+-#define mmDCP0_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2
+-#define mmDCP0_REGAMMA_CNTLB_REGION_8_9 0x05f8
+-#define mmDCP0_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2
+-#define mmDCP0_REGAMMA_CNTLB_REGION_10_11 0x05f9
+-#define mmDCP0_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2
+-#define mmDCP0_REGAMMA_CNTLB_REGION_12_13 0x05fa
+-#define mmDCP0_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2
+-#define mmDCP0_REGAMMA_CNTLB_REGION_14_15 0x05fb
+-#define mmDCP0_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2
+-#define mmDCP0_ALPHA_CONTROL 0x05fc
+-#define mmDCP0_ALPHA_CONTROL_BASE_IDX 2
+-#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x05fd
+-#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2
+-#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x05fe
+-#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+-#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x05ff
+-#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2
+-#define mmDCP0_GRPH_XDMA_FLIP_TIMEOUT 0x0600
+-#define mmDCP0_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2
+-#define mmDCP0_GRPH_XDMA_FLIP_AVG_DELAY 0x0601
+-#define mmDCP0_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2
+-#define mmDCP0_GRPH_SURFACE_COUNTER_CONTROL 0x0602
+-#define mmDCP0_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2
+-#define mmDCP0_GRPH_SURFACE_COUNTER_OUTPUT 0x0603
+-#define mmDCP0_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_lb0_dispdec
+-// base address: 0x0
+-#define mmLB0_LB_DATA_FORMAT 0x061a
+-#define mmLB0_LB_DATA_FORMAT_BASE_IDX 2
+-#define mmLB0_LB_MEMORY_CTRL 0x061b
+-#define mmLB0_LB_MEMORY_CTRL_BASE_IDX 2
+-#define mmLB0_LB_MEMORY_SIZE_STATUS 0x061c
+-#define mmLB0_LB_MEMORY_SIZE_STATUS_BASE_IDX 2
+-#define mmLB0_LB_DESKTOP_HEIGHT 0x061d
+-#define mmLB0_LB_DESKTOP_HEIGHT_BASE_IDX 2
+-#define mmLB0_LB_VLINE_START_END 0x061e
+-#define mmLB0_LB_VLINE_START_END_BASE_IDX 2
+-#define mmLB0_LB_VLINE2_START_END 0x061f
+-#define mmLB0_LB_VLINE2_START_END_BASE_IDX 2
+-#define mmLB0_LB_V_COUNTER 0x0620
+-#define mmLB0_LB_V_COUNTER_BASE_IDX 2
+-#define mmLB0_LB_SNAPSHOT_V_COUNTER 0x0621
+-#define mmLB0_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2
+-#define mmLB0_LB_INTERRUPT_MASK 0x0622
+-#define mmLB0_LB_INTERRUPT_MASK_BASE_IDX 2
+-#define mmLB0_LB_VLINE_STATUS 0x0623
+-#define mmLB0_LB_VLINE_STATUS_BASE_IDX 2
+-#define mmLB0_LB_VLINE2_STATUS 0x0624
+-#define mmLB0_LB_VLINE2_STATUS_BASE_IDX 2
+-#define mmLB0_LB_VBLANK_STATUS 0x0625
+-#define mmLB0_LB_VBLANK_STATUS_BASE_IDX 2
+-#define mmLB0_LB_SYNC_RESET_SEL 0x0626
+-#define mmLB0_LB_SYNC_RESET_SEL_BASE_IDX 2
+-#define mmLB0_LB_BLACK_KEYER_R_CR 0x0627
+-#define mmLB0_LB_BLACK_KEYER_R_CR_BASE_IDX 2
+-#define mmLB0_LB_BLACK_KEYER_G_Y 0x0628
+-#define mmLB0_LB_BLACK_KEYER_G_Y_BASE_IDX 2
+-#define mmLB0_LB_BLACK_KEYER_B_CB 0x0629
+-#define mmLB0_LB_BLACK_KEYER_B_CB_BASE_IDX 2
+-#define mmLB0_LB_KEYER_COLOR_CTRL 0x062a
+-#define mmLB0_LB_KEYER_COLOR_CTRL_BASE_IDX 2
+-#define mmLB0_LB_KEYER_COLOR_R_CR 0x062b
+-#define mmLB0_LB_KEYER_COLOR_R_CR_BASE_IDX 2
+-#define mmLB0_LB_KEYER_COLOR_G_Y 0x062c
+-#define mmLB0_LB_KEYER_COLOR_G_Y_BASE_IDX 2
+-#define mmLB0_LB_KEYER_COLOR_B_CB 0x062d
+-#define mmLB0_LB_KEYER_COLOR_B_CB_BASE_IDX 2
+-#define mmLB0_LB_KEYER_COLOR_REP_R_CR 0x062e
+-#define mmLB0_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2
+-#define mmLB0_LB_KEYER_COLOR_REP_G_Y 0x062f
+-#define mmLB0_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2
+-#define mmLB0_LB_KEYER_COLOR_REP_B_CB 0x0630
+-#define mmLB0_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2
+-#define mmLB0_LB_BUFFER_LEVEL_STATUS 0x0631
+-#define mmLB0_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2
+-#define mmLB0_LB_BUFFER_URGENCY_CTRL 0x0632
+-#define mmLB0_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2
+-#define mmLB0_LB_BUFFER_URGENCY_STATUS 0x0633
+-#define mmLB0_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2
+-#define mmLB0_LB_BUFFER_STATUS 0x0634
+-#define mmLB0_LB_BUFFER_STATUS_BASE_IDX 2
+-#define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0x0635
+-#define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2
+-#define mmLB0_MVP_AFR_FLIP_MODE 0x0636
+-#define mmLB0_MVP_AFR_FLIP_MODE_BASE_IDX 2
+-#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0x0637
+-#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2
+-#define mmLB0_MVP_FLIP_LINE_NUM_INSERT 0x0638
+-#define mmLB0_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2
+-#define mmLB0_DC_MVP_LB_CONTROL 0x0639
+-#define mmLB0_DC_MVP_LB_CONTROL_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dcfe0_dispdec
+-// base address: 0x0
+-#define mmDCFE0_DCFE_CLOCK_CONTROL 0x065a
+-#define mmDCFE0_DCFE_CLOCK_CONTROL_BASE_IDX 2
+-#define mmDCFE0_DCFE_SOFT_RESET 0x065b
+-#define mmDCFE0_DCFE_SOFT_RESET_BASE_IDX 2
+-#define mmDCFE0_DCFE_MEM_PWR_CTRL 0x065d
+-#define mmDCFE0_DCFE_MEM_PWR_CTRL_BASE_IDX 2
+-#define mmDCFE0_DCFE_MEM_PWR_CTRL2 0x065e
+-#define mmDCFE0_DCFE_MEM_PWR_CTRL2_BASE_IDX 2
+-#define mmDCFE0_DCFE_MEM_PWR_STATUS 0x065f
+-#define mmDCFE0_DCFE_MEM_PWR_STATUS_BASE_IDX 2
+-#define mmDCFE0_DCFE_MISC 0x0660
+-#define mmDCFE0_DCFE_MISC_BASE_IDX 2
+-#define mmDCFE0_DCFE_FLUSH 0x0661
+-#define mmDCFE0_DCFE_FLUSH_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dc_perfmon3_dispdec
+-// base address: 0x1938
+-#define mmDC_PERFMON3_PERFCOUNTER_CNTL 0x066e
+-#define mmDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX 2
+-#define mmDC_PERFMON3_PERFCOUNTER_CNTL2 0x066f
+-#define mmDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX 2
+-#define mmDC_PERFMON3_PERFCOUNTER_STATE 0x0670
+-#define mmDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX 2
+-#define mmDC_PERFMON3_PERFMON_CNTL 0x0671
+-#define mmDC_PERFMON3_PERFMON_CNTL_BASE_IDX 2
+-#define mmDC_PERFMON3_PERFMON_CNTL2 0x0672
+-#define mmDC_PERFMON3_PERFMON_CNTL2_BASE_IDX 2
+-#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x0673
+-#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+-#define mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x0674
+-#define mmDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX 2
+-#define mmDC_PERFMON3_PERFMON_HI 0x0675
+-#define mmDC_PERFMON3_PERFMON_HI_BASE_IDX 2
+-#define mmDC_PERFMON3_PERFMON_LOW 0x0676
+-#define mmDC_PERFMON3_PERFMON_LOW_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dmif_pg0_dispdec
+-// base address: 0x0
+-#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 0x067a
+-#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
+-#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 0x067b
+-#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
+-#define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 0x067c
+-#define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2
+-#define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL 0x067d
+-#define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2
+-#define mmDMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL 0x067e
+-#define mmDMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2
+-#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL 0x067f
+-#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2
+-#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL2 0x0680
+-#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2
+-#define mmDMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL 0x0681
+-#define mmDMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2
+-#define mmDMIF_PG0_DPG_REPEATER_PROGRAM 0x0682
+-#define mmDMIF_PG0_DPG_REPEATER_PROGRAM_BASE_IDX 2
+-#define mmDMIF_PG0_DPG_CHK_PRE_PROC_CNTL 0x0686
+-#define mmDMIF_PG0_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2
+-#define mmDMIF_PG0_DPG_DVMM_STATUS 0x0687
+-#define mmDMIF_PG0_DPG_DVMM_STATUS_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_scl0_dispdec
+-// base address: 0x0
+-#define mmSCL0_SCL_COEF_RAM_SELECT 0x069a
+-#define mmSCL0_SCL_COEF_RAM_SELECT_BASE_IDX 2
+-#define mmSCL0_SCL_COEF_RAM_TAP_DATA 0x069b
+-#define mmSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
+-#define mmSCL0_SCL_MODE 0x069c
+-#define mmSCL0_SCL_MODE_BASE_IDX 2
+-#define mmSCL0_SCL_TAP_CONTROL 0x069d
+-#define mmSCL0_SCL_TAP_CONTROL_BASE_IDX 2
+-#define mmSCL0_SCL_CONTROL 0x069e
+-#define mmSCL0_SCL_CONTROL_BASE_IDX 2
+-#define mmSCL0_SCL_BYPASS_CONTROL 0x069f
+-#define mmSCL0_SCL_BYPASS_CONTROL_BASE_IDX 2
+-#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x06a0
+-#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
+-#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL 0x06a1
+-#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2
+-#define mmSCL0_SCL_HORZ_FILTER_CONTROL 0x06a2
+-#define mmSCL0_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2
+-#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x06a3
+-#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
+-#define mmSCL0_SCL_HORZ_FILTER_INIT 0x06a4
+-#define mmSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2
+-#define mmSCL0_SCL_VERT_FILTER_CONTROL 0x06a5
+-#define mmSCL0_SCL_VERT_FILTER_CONTROL_BASE_IDX 2
+-#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x06a6
+-#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
+-#define mmSCL0_SCL_VERT_FILTER_INIT 0x06a7
+-#define mmSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2
+-#define mmSCL0_SCL_VERT_FILTER_INIT_BOT 0x06a8
+-#define mmSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
+-#define mmSCL0_SCL_ROUND_OFFSET 0x06a9
+-#define mmSCL0_SCL_ROUND_OFFSET_BASE_IDX 2
+-#define mmSCL0_SCL_UPDATE 0x06aa
+-#define mmSCL0_SCL_UPDATE_BASE_IDX 2
+-#define mmSCL0_SCL_F_SHARP_CONTROL 0x06ab
+-#define mmSCL0_SCL_F_SHARP_CONTROL_BASE_IDX 2
+-#define mmSCL0_SCL_ALU_CONTROL 0x06ac
+-#define mmSCL0_SCL_ALU_CONTROL_BASE_IDX 2
+-#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0x06ad
+-#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
+-#define mmSCL0_VIEWPORT_START_SECONDARY 0x06ae
+-#define mmSCL0_VIEWPORT_START_SECONDARY_BASE_IDX 2
+-#define mmSCL0_VIEWPORT_START 0x06af
+-#define mmSCL0_VIEWPORT_START_BASE_IDX 2
+-#define mmSCL0_VIEWPORT_SIZE 0x06b0
+-#define mmSCL0_VIEWPORT_SIZE_BASE_IDX 2
+-#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT 0x06b1
+-#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
+-#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM 0x06b2
+-#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
+-#define mmSCL0_SCL_MODE_CHANGE_DET1 0x06b3
+-#define mmSCL0_SCL_MODE_CHANGE_DET1_BASE_IDX 2
+-#define mmSCL0_SCL_MODE_CHANGE_DET2 0x06b4
+-#define mmSCL0_SCL_MODE_CHANGE_DET2_BASE_IDX 2
+-#define mmSCL0_SCL_MODE_CHANGE_DET3 0x06b5
+-#define mmSCL0_SCL_MODE_CHANGE_DET3_BASE_IDX 2
+-#define mmSCL0_SCL_MODE_CHANGE_MASK 0x06b6
+-#define mmSCL0_SCL_MODE_CHANGE_MASK_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_blnd0_dispdec
+-// base address: 0x0
+-#define mmBLND0_BLND_CONTROL 0x06c7
+-#define mmBLND0_BLND_CONTROL_BASE_IDX 2
+-#define mmBLND0_BLND_SM_CONTROL2 0x06c8
+-#define mmBLND0_BLND_SM_CONTROL2_BASE_IDX 2
+-#define mmBLND0_BLND_CONTROL2 0x06c9
+-#define mmBLND0_BLND_CONTROL2_BASE_IDX 2
+-#define mmBLND0_BLND_UPDATE 0x06ca
+-#define mmBLND0_BLND_UPDATE_BASE_IDX 2
+-#define mmBLND0_BLND_UNDERFLOW_INTERRUPT 0x06cb
+-#define mmBLND0_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2
+-#define mmBLND0_BLND_V_UPDATE_LOCK 0x06cc
+-#define mmBLND0_BLND_V_UPDATE_LOCK_BASE_IDX 2
+-#define mmBLND0_BLND_REG_UPDATE_STATUS 0x06cd
+-#define mmBLND0_BLND_REG_UPDATE_STATUS_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_crtc0_dispdec
+-// base address: 0x0
+-#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM 0x06d2
+-#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2
+-#define mmCRTC0_CRTC_H_TOTAL 0x06d3
+-#define mmCRTC0_CRTC_H_TOTAL_BASE_IDX 2
+-#define mmCRTC0_CRTC_H_BLANK_START_END 0x06d4
+-#define mmCRTC0_CRTC_H_BLANK_START_END_BASE_IDX 2
+-#define mmCRTC0_CRTC_H_SYNC_A 0x06d5
+-#define mmCRTC0_CRTC_H_SYNC_A_BASE_IDX 2
+-#define mmCRTC0_CRTC_H_SYNC_A_CNTL 0x06d6
+-#define mmCRTC0_CRTC_H_SYNC_A_CNTL_BASE_IDX 2
+-#define mmCRTC0_CRTC_H_SYNC_B 0x06d7
+-#define mmCRTC0_CRTC_H_SYNC_B_BASE_IDX 2
+-#define mmCRTC0_CRTC_H_SYNC_B_CNTL 0x06d8
+-#define mmCRTC0_CRTC_H_SYNC_B_CNTL_BASE_IDX 2
+-#define mmCRTC0_CRTC_VBI_END 0x06d9
+-#define mmCRTC0_CRTC_VBI_END_BASE_IDX 2
+-#define mmCRTC0_CRTC_V_TOTAL 0x06da
+-#define mmCRTC0_CRTC_V_TOTAL_BASE_IDX 2
+-#define mmCRTC0_CRTC_V_TOTAL_MIN 0x06db
+-#define mmCRTC0_CRTC_V_TOTAL_MIN_BASE_IDX 2
+-#define mmCRTC0_CRTC_V_TOTAL_MAX 0x06dc
+-#define mmCRTC0_CRTC_V_TOTAL_MAX_BASE_IDX 2
+-#define mmCRTC0_CRTC_V_TOTAL_CONTROL 0x06dd
+-#define mmCRTC0_CRTC_V_TOTAL_CONTROL_BASE_IDX 2
+-#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS 0x06de
+-#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2
+-#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS 0x06df
+-#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2
+-#define mmCRTC0_CRTC_V_BLANK_START_END 0x06e0
+-#define mmCRTC0_CRTC_V_BLANK_START_END_BASE_IDX 2
+-#define mmCRTC0_CRTC_V_SYNC_A 0x06e1
+-#define mmCRTC0_CRTC_V_SYNC_A_BASE_IDX 2
+-#define mmCRTC0_CRTC_V_SYNC_A_CNTL 0x06e2
+-#define mmCRTC0_CRTC_V_SYNC_A_CNTL_BASE_IDX 2
+-#define mmCRTC0_CRTC_V_SYNC_B 0x06e3
+-#define mmCRTC0_CRTC_V_SYNC_B_BASE_IDX 2
+-#define mmCRTC0_CRTC_V_SYNC_B_CNTL 0x06e4
+-#define mmCRTC0_CRTC_V_SYNC_B_CNTL_BASE_IDX 2
+-#define mmCRTC0_CRTC_DTMTEST_CNTL 0x06e5
+-#define mmCRTC0_CRTC_DTMTEST_CNTL_BASE_IDX 2
+-#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION 0x06e6
+-#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2
+-#define mmCRTC0_CRTC_TRIGA_CNTL 0x06e7
+-#define mmCRTC0_CRTC_TRIGA_CNTL_BASE_IDX 2
+-#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG 0x06e8
+-#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2
+-#define mmCRTC0_CRTC_TRIGB_CNTL 0x06e9
+-#define mmCRTC0_CRTC_TRIGB_CNTL_BASE_IDX 2
+-#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG 0x06ea
+-#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2
+-#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL 0x06eb
+-#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
+-#define mmCRTC0_CRTC_FLOW_CONTROL 0x06ec
+-#define mmCRTC0_CRTC_FLOW_CONTROL_BASE_IDX 2
+-#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE 0x06ed
+-#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
+-#define mmCRTC0_CRTC_AVSYNC_COUNTER 0x06ee
+-#define mmCRTC0_CRTC_AVSYNC_COUNTER_BASE_IDX 2
+-#define mmCRTC0_CRTC_CONTROL 0x06ef
+-#define mmCRTC0_CRTC_CONTROL_BASE_IDX 2
+-#define mmCRTC0_CRTC_BLANK_CONTROL 0x06f0
+-#define mmCRTC0_CRTC_BLANK_CONTROL_BASE_IDX 2
+-#define mmCRTC0_CRTC_INTERLACE_CONTROL 0x06f1
+-#define mmCRTC0_CRTC_INTERLACE_CONTROL_BASE_IDX 2
+-#define mmCRTC0_CRTC_INTERLACE_STATUS 0x06f2
+-#define mmCRTC0_CRTC_INTERLACE_STATUS_BASE_IDX 2
+-#define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL 0x06f3
+-#define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2
+-#define mmCRTC0_CRTC_PIXEL_DATA_READBACK0 0x06f4
+-#define mmCRTC0_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2
+-#define mmCRTC0_CRTC_PIXEL_DATA_READBACK1 0x06f5
+-#define mmCRTC0_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2
+-#define mmCRTC0_CRTC_STATUS 0x06f6
+-#define mmCRTC0_CRTC_STATUS_BASE_IDX 2
+-#define mmCRTC0_CRTC_STATUS_POSITION 0x06f7
+-#define mmCRTC0_CRTC_STATUS_POSITION_BASE_IDX 2
+-#define mmCRTC0_CRTC_NOM_VERT_POSITION 0x06f8
+-#define mmCRTC0_CRTC_NOM_VERT_POSITION_BASE_IDX 2
+-#define mmCRTC0_CRTC_STATUS_FRAME_COUNT 0x06f9
+-#define mmCRTC0_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2
+-#define mmCRTC0_CRTC_STATUS_VF_COUNT 0x06fa
+-#define mmCRTC0_CRTC_STATUS_VF_COUNT_BASE_IDX 2
+-#define mmCRTC0_CRTC_STATUS_HV_COUNT 0x06fb
+-#define mmCRTC0_CRTC_STATUS_HV_COUNT_BASE_IDX 2
+-#define mmCRTC0_CRTC_COUNT_CONTROL 0x06fc
+-#define mmCRTC0_CRTC_COUNT_CONTROL_BASE_IDX 2
+-#define mmCRTC0_CRTC_COUNT_RESET 0x06fd
+-#define mmCRTC0_CRTC_COUNT_RESET_BASE_IDX 2
+-#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x06fe
+-#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
+-#define mmCRTC0_CRTC_VERT_SYNC_CONTROL 0x06ff
+-#define mmCRTC0_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2
+-#define mmCRTC0_CRTC_STEREO_STATUS 0x0700
+-#define mmCRTC0_CRTC_STEREO_STATUS_BASE_IDX 2
+-#define mmCRTC0_CRTC_STEREO_CONTROL 0x0701
+-#define mmCRTC0_CRTC_STEREO_CONTROL_BASE_IDX 2
+-#define mmCRTC0_CRTC_SNAPSHOT_STATUS 0x0702
+-#define mmCRTC0_CRTC_SNAPSHOT_STATUS_BASE_IDX 2
+-#define mmCRTC0_CRTC_SNAPSHOT_CONTROL 0x0703
+-#define mmCRTC0_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2
+-#define mmCRTC0_CRTC_SNAPSHOT_POSITION 0x0704
+-#define mmCRTC0_CRTC_SNAPSHOT_POSITION_BASE_IDX 2
+-#define mmCRTC0_CRTC_SNAPSHOT_FRAME 0x0705
+-#define mmCRTC0_CRTC_SNAPSHOT_FRAME_BASE_IDX 2
+-#define mmCRTC0_CRTC_START_LINE_CONTROL 0x0706
+-#define mmCRTC0_CRTC_START_LINE_CONTROL_BASE_IDX 2
+-#define mmCRTC0_CRTC_INTERRUPT_CONTROL 0x0707
+-#define mmCRTC0_CRTC_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmCRTC0_CRTC_UPDATE_LOCK 0x0708
+-#define mmCRTC0_CRTC_UPDATE_LOCK_BASE_IDX 2
+-#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL 0x0709
+-#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
+-#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x070a
+-#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2
+-#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x070b
+-#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2
+-#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS 0x070c
+-#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2
+-#define mmCRTC0_CRTC_TEST_PATTERN_COLOR 0x070d
+-#define mmCRTC0_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2
+-#define mmCRTC0_CRTC_MASTER_UPDATE_LOCK 0x070e
+-#define mmCRTC0_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2
+-#define mmCRTC0_CRTC_MASTER_UPDATE_MODE 0x070f
+-#define mmCRTC0_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2
+-#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT 0x0710
+-#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2
+-#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x0711
+-#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2
+-#define mmCRTC0_CRTC_MVP_STATUS 0x0712
+-#define mmCRTC0_CRTC_MVP_STATUS_BASE_IDX 2
+-#define mmCRTC0_CRTC_MASTER_EN 0x0713
+-#define mmCRTC0_CRTC_MASTER_EN_BASE_IDX 2
+-#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT 0x0714
+-#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2
+-#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS 0x0715
+-#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2
+-#define mmCRTC0_CRTC_OVERSCAN_COLOR 0x0717
+-#define mmCRTC0_CRTC_OVERSCAN_COLOR_BASE_IDX 2
+-#define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT 0x0718
+-#define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2
+-#define mmCRTC0_CRTC_BLANK_DATA_COLOR 0x0719
+-#define mmCRTC0_CRTC_BLANK_DATA_COLOR_BASE_IDX 2
+-#define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT 0x071a
+-#define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2
+-#define mmCRTC0_CRTC_BLACK_COLOR 0x071b
+-#define mmCRTC0_CRTC_BLACK_COLOR_BASE_IDX 2
+-#define mmCRTC0_CRTC_BLACK_COLOR_EXT 0x071c
+-#define mmCRTC0_CRTC_BLACK_COLOR_EXT_BASE_IDX 2
+-#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION 0x071d
+-#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
+-#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x071e
+-#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
+-#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION 0x071f
+-#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
+-#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x0720
+-#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
+-#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION 0x0721
+-#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
+-#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x0722
+-#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
+-#define mmCRTC0_CRTC_CRC_CNTL 0x0723
+-#define mmCRTC0_CRTC_CRC_CNTL_BASE_IDX 2
+-#define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL 0x0724
+-#define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
+-#define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL 0x0725
+-#define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
+-#define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL 0x0726
+-#define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
+-#define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL 0x0727
+-#define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
+-#define mmCRTC0_CRTC_CRC0_DATA_RG 0x0728
+-#define mmCRTC0_CRTC_CRC0_DATA_RG_BASE_IDX 2
+-#define mmCRTC0_CRTC_CRC0_DATA_B 0x0729
+-#define mmCRTC0_CRTC_CRC0_DATA_B_BASE_IDX 2
+-#define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL 0x072a
+-#define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
+-#define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL 0x072b
+-#define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
+-#define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL 0x072c
+-#define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
+-#define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL 0x072d
+-#define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
+-#define mmCRTC0_CRTC_CRC1_DATA_RG 0x072e
+-#define mmCRTC0_CRTC_CRC1_DATA_RG_BASE_IDX 2
+-#define mmCRTC0_CRTC_CRC1_DATA_B 0x072f
+-#define mmCRTC0_CRTC_CRC1_DATA_B_BASE_IDX 2
+-#define mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL 0x0730
+-#define mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2
+-#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x0731
+-#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2
+-#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x0732
+-#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2
+-#define mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x0733
+-#define mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x0734
+-#define mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x0735
+-#define mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL 0x0736
+-#define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2
+-#define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL 0x0737
+-#define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2
+-#define mmCRTC0_CRTC_GSL_VSYNC_GAP 0x0738
+-#define mmCRTC0_CRTC_GSL_VSYNC_GAP_BASE_IDX 2
+-#define mmCRTC0_CRTC_GSL_WINDOW 0x0739
+-#define mmCRTC0_CRTC_GSL_WINDOW_BASE_IDX 2
+-#define mmCRTC0_CRTC_GSL_CONTROL 0x073a
+-#define mmCRTC0_CRTC_GSL_CONTROL_BASE_IDX 2
+-#define mmCRTC0_CRTC_RANGE_TIMING_INT_STATUS 0x073d
+-#define mmCRTC0_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2
+-#define mmCRTC0_CRTC_DRR_CONTROL 0x073e
+-#define mmCRTC0_CRTC_DRR_CONTROL_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_fmt0_dispdec
+-// base address: 0x0
+-#define mmFMT0_FMT_CLAMP_COMPONENT_R 0x0742
+-#define mmFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
+-#define mmFMT0_FMT_CLAMP_COMPONENT_G 0x0743
+-#define mmFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
+-#define mmFMT0_FMT_CLAMP_COMPONENT_B 0x0744
+-#define mmFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
+-#define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x0745
+-#define mmFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
+-#define mmFMT0_FMT_CONTROL 0x0746
+-#define mmFMT0_FMT_CONTROL_BASE_IDX 2
+-#define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x0747
+-#define mmFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
+-#define mmFMT0_FMT_DITHER_RAND_R_SEED 0x0748
+-#define mmFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
+-#define mmFMT0_FMT_DITHER_RAND_G_SEED 0x0749
+-#define mmFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
+-#define mmFMT0_FMT_DITHER_RAND_B_SEED 0x074a
+-#define mmFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
+-#define mmFMT0_FMT_CLAMP_CNTL 0x074e
+-#define mmFMT0_FMT_CLAMP_CNTL_BASE_IDX 2
+-#define mmFMT0_FMT_CRC_CNTL 0x074f
+-#define mmFMT0_FMT_CRC_CNTL_BASE_IDX 2
+-#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK 0x0750
+-#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
+-#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x0751
+-#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
+-#define mmFMT0_FMT_CRC_SIG_RED_GREEN 0x0752
+-#define mmFMT0_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2
+-#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL 0x0753
+-#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2
+-#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x0754
+-#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
+-#define mmFMT0_FMT_420_HBLANK_EARLY_START 0x0755
+-#define mmFMT0_FMT_420_HBLANK_EARLY_START_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dcp1_dispdec
+-// base address: 0x800
+-#define mmDCP1_GRPH_ENABLE 0x075a
+-#define mmDCP1_GRPH_ENABLE_BASE_IDX 2
+-#define mmDCP1_GRPH_CONTROL 0x075b
+-#define mmDCP1_GRPH_CONTROL_BASE_IDX 2
+-#define mmDCP1_GRPH_LUT_10BIT_BYPASS 0x075c
+-#define mmDCP1_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2
+-#define mmDCP1_GRPH_SWAP_CNTL 0x075d
+-#define mmDCP1_GRPH_SWAP_CNTL_BASE_IDX 2
+-#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS 0x075e
+-#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
+-#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS 0x075f
+-#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
+-#define mmDCP1_GRPH_PITCH 0x0760
+-#define mmDCP1_GRPH_PITCH_BASE_IDX 2
+-#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0761
+-#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+-#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0762
+-#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+-#define mmDCP1_GRPH_SURFACE_OFFSET_X 0x0763
+-#define mmDCP1_GRPH_SURFACE_OFFSET_X_BASE_IDX 2
+-#define mmDCP1_GRPH_SURFACE_OFFSET_Y 0x0764
+-#define mmDCP1_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2
+-#define mmDCP1_GRPH_X_START 0x0765
+-#define mmDCP1_GRPH_X_START_BASE_IDX 2
+-#define mmDCP1_GRPH_Y_START 0x0766
+-#define mmDCP1_GRPH_Y_START_BASE_IDX 2
+-#define mmDCP1_GRPH_X_END 0x0767
+-#define mmDCP1_GRPH_X_END_BASE_IDX 2
+-#define mmDCP1_GRPH_Y_END 0x0768
+-#define mmDCP1_GRPH_Y_END_BASE_IDX 2
+-#define mmDCP1_INPUT_GAMMA_CONTROL 0x0769
+-#define mmDCP1_INPUT_GAMMA_CONTROL_BASE_IDX 2
+-#define mmDCP1_GRPH_UPDATE 0x076a
+-#define mmDCP1_GRPH_UPDATE_BASE_IDX 2
+-#define mmDCP1_GRPH_FLIP_CONTROL 0x076b
+-#define mmDCP1_GRPH_FLIP_CONTROL_BASE_IDX 2
+-#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE 0x076c
+-#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2
+-#define mmDCP1_GRPH_DFQ_CONTROL 0x076d
+-#define mmDCP1_GRPH_DFQ_CONTROL_BASE_IDX 2
+-#define mmDCP1_GRPH_DFQ_STATUS 0x076e
+-#define mmDCP1_GRPH_DFQ_STATUS_BASE_IDX 2
+-#define mmDCP1_GRPH_INTERRUPT_STATUS 0x076f
+-#define mmDCP1_GRPH_INTERRUPT_STATUS_BASE_IDX 2
+-#define mmDCP1_GRPH_INTERRUPT_CONTROL 0x0770
+-#define mmDCP1_GRPH_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0771
+-#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2
+-#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS 0x0772
+-#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2
+-#define mmDCP1_GRPH_COMPRESS_PITCH 0x0773
+-#define mmDCP1_GRPH_COMPRESS_PITCH_BASE_IDX 2
+-#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0774
+-#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+-#define mmDCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0775
+-#define mmDCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2
+-#define mmDCP1_PRESCALE_GRPH_CONTROL 0x0776
+-#define mmDCP1_PRESCALE_GRPH_CONTROL_BASE_IDX 2
+-#define mmDCP1_PRESCALE_VALUES_GRPH_R 0x0777
+-#define mmDCP1_PRESCALE_VALUES_GRPH_R_BASE_IDX 2
+-#define mmDCP1_PRESCALE_VALUES_GRPH_G 0x0778
+-#define mmDCP1_PRESCALE_VALUES_GRPH_G_BASE_IDX 2
+-#define mmDCP1_PRESCALE_VALUES_GRPH_B 0x0779
+-#define mmDCP1_PRESCALE_VALUES_GRPH_B_BASE_IDX 2
+-#define mmDCP1_INPUT_CSC_CONTROL 0x077a
+-#define mmDCP1_INPUT_CSC_CONTROL_BASE_IDX 2
+-#define mmDCP1_INPUT_CSC_C11_C12 0x077b
+-#define mmDCP1_INPUT_CSC_C11_C12_BASE_IDX 2
+-#define mmDCP1_INPUT_CSC_C13_C14 0x077c
+-#define mmDCP1_INPUT_CSC_C13_C14_BASE_IDX 2
+-#define mmDCP1_INPUT_CSC_C21_C22 0x077d
+-#define mmDCP1_INPUT_CSC_C21_C22_BASE_IDX 2
+-#define mmDCP1_INPUT_CSC_C23_C24 0x077e
+-#define mmDCP1_INPUT_CSC_C23_C24_BASE_IDX 2
+-#define mmDCP1_INPUT_CSC_C31_C32 0x077f
+-#define mmDCP1_INPUT_CSC_C31_C32_BASE_IDX 2
+-#define mmDCP1_INPUT_CSC_C33_C34 0x0780
+-#define mmDCP1_INPUT_CSC_C33_C34_BASE_IDX 2
+-#define mmDCP1_OUTPUT_CSC_CONTROL 0x0781
+-#define mmDCP1_OUTPUT_CSC_CONTROL_BASE_IDX 2
+-#define mmDCP1_OUTPUT_CSC_C11_C12 0x0782
+-#define mmDCP1_OUTPUT_CSC_C11_C12_BASE_IDX 2
+-#define mmDCP1_OUTPUT_CSC_C13_C14 0x0783
+-#define mmDCP1_OUTPUT_CSC_C13_C14_BASE_IDX 2
+-#define mmDCP1_OUTPUT_CSC_C21_C22 0x0784
+-#define mmDCP1_OUTPUT_CSC_C21_C22_BASE_IDX 2
+-#define mmDCP1_OUTPUT_CSC_C23_C24 0x0785
+-#define mmDCP1_OUTPUT_CSC_C23_C24_BASE_IDX 2
+-#define mmDCP1_OUTPUT_CSC_C31_C32 0x0786
+-#define mmDCP1_OUTPUT_CSC_C31_C32_BASE_IDX 2
+-#define mmDCP1_OUTPUT_CSC_C33_C34 0x0787
+-#define mmDCP1_OUTPUT_CSC_C33_C34_BASE_IDX 2
+-#define mmDCP1_COMM_MATRIXA_TRANS_C11_C12 0x0788
+-#define mmDCP1_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2
+-#define mmDCP1_COMM_MATRIXA_TRANS_C13_C14 0x0789
+-#define mmDCP1_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2
+-#define mmDCP1_COMM_MATRIXA_TRANS_C21_C22 0x078a
+-#define mmDCP1_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2
+-#define mmDCP1_COMM_MATRIXA_TRANS_C23_C24 0x078b
+-#define mmDCP1_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2
+-#define mmDCP1_COMM_MATRIXA_TRANS_C31_C32 0x078c
+-#define mmDCP1_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2
+-#define mmDCP1_COMM_MATRIXA_TRANS_C33_C34 0x078d
+-#define mmDCP1_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2
+-#define mmDCP1_COMM_MATRIXB_TRANS_C11_C12 0x078e
+-#define mmDCP1_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2
+-#define mmDCP1_COMM_MATRIXB_TRANS_C13_C14 0x078f
+-#define mmDCP1_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2
+-#define mmDCP1_COMM_MATRIXB_TRANS_C21_C22 0x0790
+-#define mmDCP1_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2
+-#define mmDCP1_COMM_MATRIXB_TRANS_C23_C24 0x0791
+-#define mmDCP1_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2
+-#define mmDCP1_COMM_MATRIXB_TRANS_C31_C32 0x0792
+-#define mmDCP1_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2
+-#define mmDCP1_COMM_MATRIXB_TRANS_C33_C34 0x0793
+-#define mmDCP1_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2
+-#define mmDCP1_DENORM_CONTROL 0x0794
+-#define mmDCP1_DENORM_CONTROL_BASE_IDX 2
+-#define mmDCP1_OUT_ROUND_CONTROL 0x0795
+-#define mmDCP1_OUT_ROUND_CONTROL_BASE_IDX 2
+-#define mmDCP1_OUT_CLAMP_CONTROL_R_CR 0x0796
+-#define mmDCP1_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2
+-#define mmDCP1_OUT_CLAMP_CONTROL_G_Y 0x0797
+-#define mmDCP1_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2
+-#define mmDCP1_OUT_CLAMP_CONTROL_B_CB 0x0798
+-#define mmDCP1_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2
+-#define mmDCP1_KEY_CONTROL 0x0799
+-#define mmDCP1_KEY_CONTROL_BASE_IDX 2
+-#define mmDCP1_KEY_RANGE_ALPHA 0x079a
+-#define mmDCP1_KEY_RANGE_ALPHA_BASE_IDX 2
+-#define mmDCP1_KEY_RANGE_RED 0x079b
+-#define mmDCP1_KEY_RANGE_RED_BASE_IDX 2
+-#define mmDCP1_KEY_RANGE_GREEN 0x079c
+-#define mmDCP1_KEY_RANGE_GREEN_BASE_IDX 2
+-#define mmDCP1_KEY_RANGE_BLUE 0x079d
+-#define mmDCP1_KEY_RANGE_BLUE_BASE_IDX 2
+-#define mmDCP1_DEGAMMA_CONTROL 0x079e
+-#define mmDCP1_DEGAMMA_CONTROL_BASE_IDX 2
+-#define mmDCP1_GAMUT_REMAP_CONTROL 0x079f
+-#define mmDCP1_GAMUT_REMAP_CONTROL_BASE_IDX 2
+-#define mmDCP1_GAMUT_REMAP_C11_C12 0x07a0
+-#define mmDCP1_GAMUT_REMAP_C11_C12_BASE_IDX 2
+-#define mmDCP1_GAMUT_REMAP_C13_C14 0x07a1
+-#define mmDCP1_GAMUT_REMAP_C13_C14_BASE_IDX 2
+-#define mmDCP1_GAMUT_REMAP_C21_C22 0x07a2
+-#define mmDCP1_GAMUT_REMAP_C21_C22_BASE_IDX 2
+-#define mmDCP1_GAMUT_REMAP_C23_C24 0x07a3
+-#define mmDCP1_GAMUT_REMAP_C23_C24_BASE_IDX 2
+-#define mmDCP1_GAMUT_REMAP_C31_C32 0x07a4
+-#define mmDCP1_GAMUT_REMAP_C31_C32_BASE_IDX 2
+-#define mmDCP1_GAMUT_REMAP_C33_C34 0x07a5
+-#define mmDCP1_GAMUT_REMAP_C33_C34_BASE_IDX 2
+-#define mmDCP1_DCP_SPATIAL_DITHER_CNTL 0x07a6
+-#define mmDCP1_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2
+-#define mmDCP1_DCP_RANDOM_SEEDS 0x07a7
+-#define mmDCP1_DCP_RANDOM_SEEDS_BASE_IDX 2
+-#define mmDCP1_DCP_FP_CONVERTED_FIELD 0x07a8
+-#define mmDCP1_DCP_FP_CONVERTED_FIELD_BASE_IDX 2
+-#define mmDCP1_CUR_CONTROL 0x07a9
+-#define mmDCP1_CUR_CONTROL_BASE_IDX 2
+-#define mmDCP1_CUR_SURFACE_ADDRESS 0x07aa
+-#define mmDCP1_CUR_SURFACE_ADDRESS_BASE_IDX 2
+-#define mmDCP1_CUR_SIZE 0x07ab
+-#define mmDCP1_CUR_SIZE_BASE_IDX 2
+-#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH 0x07ac
+-#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+-#define mmDCP1_CUR_POSITION 0x07ad
+-#define mmDCP1_CUR_POSITION_BASE_IDX 2
+-#define mmDCP1_CUR_HOT_SPOT 0x07ae
+-#define mmDCP1_CUR_HOT_SPOT_BASE_IDX 2
+-#define mmDCP1_CUR_COLOR1 0x07af
+-#define mmDCP1_CUR_COLOR1_BASE_IDX 2
+-#define mmDCP1_CUR_COLOR2 0x07b0
+-#define mmDCP1_CUR_COLOR2_BASE_IDX 2
+-#define mmDCP1_CUR_UPDATE 0x07b1
+-#define mmDCP1_CUR_UPDATE_BASE_IDX 2
+-#define mmDCP1_CUR_REQUEST_FILTER_CNTL 0x07bb
+-#define mmDCP1_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2
+-#define mmDCP1_CUR_STEREO_CONTROL 0x07bc
+-#define mmDCP1_CUR_STEREO_CONTROL_BASE_IDX 2
+-#define mmDCP1_DC_LUT_RW_MODE 0x07be
+-#define mmDCP1_DC_LUT_RW_MODE_BASE_IDX 2
+-#define mmDCP1_DC_LUT_RW_INDEX 0x07bf
+-#define mmDCP1_DC_LUT_RW_INDEX_BASE_IDX 2
+-#define mmDCP1_DC_LUT_SEQ_COLOR 0x07c0
+-#define mmDCP1_DC_LUT_SEQ_COLOR_BASE_IDX 2
+-#define mmDCP1_DC_LUT_PWL_DATA 0x07c1
+-#define mmDCP1_DC_LUT_PWL_DATA_BASE_IDX 2
+-#define mmDCP1_DC_LUT_30_COLOR 0x07c2
+-#define mmDCP1_DC_LUT_30_COLOR_BASE_IDX 2
+-#define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE 0x07c3
+-#define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2
+-#define mmDCP1_DC_LUT_WRITE_EN_MASK 0x07c4
+-#define mmDCP1_DC_LUT_WRITE_EN_MASK_BASE_IDX 2
+-#define mmDCP1_DC_LUT_AUTOFILL 0x07c5
+-#define mmDCP1_DC_LUT_AUTOFILL_BASE_IDX 2
+-#define mmDCP1_DC_LUT_CONTROL 0x07c6
+-#define mmDCP1_DC_LUT_CONTROL_BASE_IDX 2
+-#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE 0x07c7
+-#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2
+-#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN 0x07c8
+-#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2
+-#define mmDCP1_DC_LUT_BLACK_OFFSET_RED 0x07c9
+-#define mmDCP1_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2
+-#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE 0x07ca
+-#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2
+-#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN 0x07cb
+-#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2
+-#define mmDCP1_DC_LUT_WHITE_OFFSET_RED 0x07cc
+-#define mmDCP1_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2
+-#define mmDCP1_DCP_CRC_CONTROL 0x07cd
+-#define mmDCP1_DCP_CRC_CONTROL_BASE_IDX 2
+-#define mmDCP1_DCP_CRC_MASK 0x07ce
+-#define mmDCP1_DCP_CRC_MASK_BASE_IDX 2
+-#define mmDCP1_DCP_CRC_CURRENT 0x07cf
+-#define mmDCP1_DCP_CRC_CURRENT_BASE_IDX 2
+-#define mmDCP1_DVMM_PTE_CONTROL 0x07d0
+-#define mmDCP1_DVMM_PTE_CONTROL_BASE_IDX 2
+-#define mmDCP1_DCP_CRC_LAST 0x07d1
+-#define mmDCP1_DCP_CRC_LAST_BASE_IDX 2
+-#define mmDCP1_DVMM_PTE_ARB_CONTROL 0x07d2
+-#define mmDCP1_DVMM_PTE_ARB_CONTROL_BASE_IDX 2
+-#define mmDCP1_GRPH_FLIP_RATE_CNTL 0x07d4
+-#define mmDCP1_GRPH_FLIP_RATE_CNTL_BASE_IDX 2
+-#define mmDCP1_DCP_GSL_CONTROL 0x07d5
+-#define mmDCP1_DCP_GSL_CONTROL_BASE_IDX 2
+-#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x07d6
+-#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2
+-#define mmDCP1_GRPH_STEREOSYNC_FLIP 0x07dc
+-#define mmDCP1_GRPH_STEREOSYNC_FLIP_BASE_IDX 2
+-#define mmDCP1_HW_ROTATION 0x07de
+-#define mmDCP1_HW_ROTATION_BASE_IDX 2
+-#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x07df
+-#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2
+-#define mmDCP1_REGAMMA_CONTROL 0x07e0
+-#define mmDCP1_REGAMMA_CONTROL_BASE_IDX 2
+-#define mmDCP1_REGAMMA_LUT_INDEX 0x07e1
+-#define mmDCP1_REGAMMA_LUT_INDEX_BASE_IDX 2
+-#define mmDCP1_REGAMMA_LUT_DATA 0x07e2
+-#define mmDCP1_REGAMMA_LUT_DATA_BASE_IDX 2
+-#define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK 0x07e3
+-#define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2
+-#define mmDCP1_REGAMMA_CNTLA_START_CNTL 0x07e4
+-#define mmDCP1_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2
+-#define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL 0x07e5
+-#define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2
+-#define mmDCP1_REGAMMA_CNTLA_END_CNTL1 0x07e6
+-#define mmDCP1_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2
+-#define mmDCP1_REGAMMA_CNTLA_END_CNTL2 0x07e7
+-#define mmDCP1_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2
+-#define mmDCP1_REGAMMA_CNTLA_REGION_0_1 0x07e8
+-#define mmDCP1_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2
+-#define mmDCP1_REGAMMA_CNTLA_REGION_2_3 0x07e9
+-#define mmDCP1_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2
+-#define mmDCP1_REGAMMA_CNTLA_REGION_4_5 0x07ea
+-#define mmDCP1_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2
+-#define mmDCP1_REGAMMA_CNTLA_REGION_6_7 0x07eb
+-#define mmDCP1_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2
+-#define mmDCP1_REGAMMA_CNTLA_REGION_8_9 0x07ec
+-#define mmDCP1_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2
+-#define mmDCP1_REGAMMA_CNTLA_REGION_10_11 0x07ed
+-#define mmDCP1_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2
+-#define mmDCP1_REGAMMA_CNTLA_REGION_12_13 0x07ee
+-#define mmDCP1_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2
+-#define mmDCP1_REGAMMA_CNTLA_REGION_14_15 0x07ef
+-#define mmDCP1_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2
+-#define mmDCP1_REGAMMA_CNTLB_START_CNTL 0x07f0
+-#define mmDCP1_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2
+-#define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL 0x07f1
+-#define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2
+-#define mmDCP1_REGAMMA_CNTLB_END_CNTL1 0x07f2
+-#define mmDCP1_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2
+-#define mmDCP1_REGAMMA_CNTLB_END_CNTL2 0x07f3
+-#define mmDCP1_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2
+-#define mmDCP1_REGAMMA_CNTLB_REGION_0_1 0x07f4
+-#define mmDCP1_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2
+-#define mmDCP1_REGAMMA_CNTLB_REGION_2_3 0x07f5
+-#define mmDCP1_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2
+-#define mmDCP1_REGAMMA_CNTLB_REGION_4_5 0x07f6
+-#define mmDCP1_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2
+-#define mmDCP1_REGAMMA_CNTLB_REGION_6_7 0x07f7
+-#define mmDCP1_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2
+-#define mmDCP1_REGAMMA_CNTLB_REGION_8_9 0x07f8
+-#define mmDCP1_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2
+-#define mmDCP1_REGAMMA_CNTLB_REGION_10_11 0x07f9
+-#define mmDCP1_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2
+-#define mmDCP1_REGAMMA_CNTLB_REGION_12_13 0x07fa
+-#define mmDCP1_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2
+-#define mmDCP1_REGAMMA_CNTLB_REGION_14_15 0x07fb
+-#define mmDCP1_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2
+-#define mmDCP1_ALPHA_CONTROL 0x07fc
+-#define mmDCP1_ALPHA_CONTROL_BASE_IDX 2
+-#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x07fd
+-#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2
+-#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x07fe
+-#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+-#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x07ff
+-#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2
+-#define mmDCP1_GRPH_XDMA_FLIP_TIMEOUT 0x0800
+-#define mmDCP1_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2
+-#define mmDCP1_GRPH_XDMA_FLIP_AVG_DELAY 0x0801
+-#define mmDCP1_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2
+-#define mmDCP1_GRPH_SURFACE_COUNTER_CONTROL 0x0802
+-#define mmDCP1_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2
+-#define mmDCP1_GRPH_SURFACE_COUNTER_OUTPUT 0x0803
+-#define mmDCP1_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_lb1_dispdec
+-// base address: 0x800
+-#define mmLB1_LB_DATA_FORMAT 0x081a
+-#define mmLB1_LB_DATA_FORMAT_BASE_IDX 2
+-#define mmLB1_LB_MEMORY_CTRL 0x081b
+-#define mmLB1_LB_MEMORY_CTRL_BASE_IDX 2
+-#define mmLB1_LB_MEMORY_SIZE_STATUS 0x081c
+-#define mmLB1_LB_MEMORY_SIZE_STATUS_BASE_IDX 2
+-#define mmLB1_LB_DESKTOP_HEIGHT 0x081d
+-#define mmLB1_LB_DESKTOP_HEIGHT_BASE_IDX 2
+-#define mmLB1_LB_VLINE_START_END 0x081e
+-#define mmLB1_LB_VLINE_START_END_BASE_IDX 2
+-#define mmLB1_LB_VLINE2_START_END 0x081f
+-#define mmLB1_LB_VLINE2_START_END_BASE_IDX 2
+-#define mmLB1_LB_V_COUNTER 0x0820
+-#define mmLB1_LB_V_COUNTER_BASE_IDX 2
+-#define mmLB1_LB_SNAPSHOT_V_COUNTER 0x0821
+-#define mmLB1_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2
+-#define mmLB1_LB_INTERRUPT_MASK 0x0822
+-#define mmLB1_LB_INTERRUPT_MASK_BASE_IDX 2
+-#define mmLB1_LB_VLINE_STATUS 0x0823
+-#define mmLB1_LB_VLINE_STATUS_BASE_IDX 2
+-#define mmLB1_LB_VLINE2_STATUS 0x0824
+-#define mmLB1_LB_VLINE2_STATUS_BASE_IDX 2
+-#define mmLB1_LB_VBLANK_STATUS 0x0825
+-#define mmLB1_LB_VBLANK_STATUS_BASE_IDX 2
+-#define mmLB1_LB_SYNC_RESET_SEL 0x0826
+-#define mmLB1_LB_SYNC_RESET_SEL_BASE_IDX 2
+-#define mmLB1_LB_BLACK_KEYER_R_CR 0x0827
+-#define mmLB1_LB_BLACK_KEYER_R_CR_BASE_IDX 2
+-#define mmLB1_LB_BLACK_KEYER_G_Y 0x0828
+-#define mmLB1_LB_BLACK_KEYER_G_Y_BASE_IDX 2
+-#define mmLB1_LB_BLACK_KEYER_B_CB 0x0829
+-#define mmLB1_LB_BLACK_KEYER_B_CB_BASE_IDX 2
+-#define mmLB1_LB_KEYER_COLOR_CTRL 0x082a
+-#define mmLB1_LB_KEYER_COLOR_CTRL_BASE_IDX 2
+-#define mmLB1_LB_KEYER_COLOR_R_CR 0x082b
+-#define mmLB1_LB_KEYER_COLOR_R_CR_BASE_IDX 2
+-#define mmLB1_LB_KEYER_COLOR_G_Y 0x082c
+-#define mmLB1_LB_KEYER_COLOR_G_Y_BASE_IDX 2
+-#define mmLB1_LB_KEYER_COLOR_B_CB 0x082d
+-#define mmLB1_LB_KEYER_COLOR_B_CB_BASE_IDX 2
+-#define mmLB1_LB_KEYER_COLOR_REP_R_CR 0x082e
+-#define mmLB1_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2
+-#define mmLB1_LB_KEYER_COLOR_REP_G_Y 0x082f
+-#define mmLB1_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2
+-#define mmLB1_LB_KEYER_COLOR_REP_B_CB 0x0830
+-#define mmLB1_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2
+-#define mmLB1_LB_BUFFER_LEVEL_STATUS 0x0831
+-#define mmLB1_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2
+-#define mmLB1_LB_BUFFER_URGENCY_CTRL 0x0832
+-#define mmLB1_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2
+-#define mmLB1_LB_BUFFER_URGENCY_STATUS 0x0833
+-#define mmLB1_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2
+-#define mmLB1_LB_BUFFER_STATUS 0x0834
+-#define mmLB1_LB_BUFFER_STATUS_BASE_IDX 2
+-#define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0x0835
+-#define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2
+-#define mmLB1_MVP_AFR_FLIP_MODE 0x0836
+-#define mmLB1_MVP_AFR_FLIP_MODE_BASE_IDX 2
+-#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0x0837
+-#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2
+-#define mmLB1_MVP_FLIP_LINE_NUM_INSERT 0x0838
+-#define mmLB1_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2
+-#define mmLB1_DC_MVP_LB_CONTROL 0x0839
+-#define mmLB1_DC_MVP_LB_CONTROL_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dcfe1_dispdec
+-// base address: 0x800
+-#define mmDCFE1_DCFE_CLOCK_CONTROL 0x085a
+-#define mmDCFE1_DCFE_CLOCK_CONTROL_BASE_IDX 2
+-#define mmDCFE1_DCFE_SOFT_RESET 0x085b
+-#define mmDCFE1_DCFE_SOFT_RESET_BASE_IDX 2
+-#define mmDCFE1_DCFE_MEM_PWR_CTRL 0x085d
+-#define mmDCFE1_DCFE_MEM_PWR_CTRL_BASE_IDX 2
+-#define mmDCFE1_DCFE_MEM_PWR_CTRL2 0x085e
+-#define mmDCFE1_DCFE_MEM_PWR_CTRL2_BASE_IDX 2
+-#define mmDCFE1_DCFE_MEM_PWR_STATUS 0x085f
+-#define mmDCFE1_DCFE_MEM_PWR_STATUS_BASE_IDX 2
+-#define mmDCFE1_DCFE_MISC 0x0860
+-#define mmDCFE1_DCFE_MISC_BASE_IDX 2
+-#define mmDCFE1_DCFE_FLUSH 0x0861
+-#define mmDCFE1_DCFE_FLUSH_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dc_perfmon4_dispdec
+-// base address: 0x2138
+-#define mmDC_PERFMON4_PERFCOUNTER_CNTL 0x086e
+-#define mmDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX 2
+-#define mmDC_PERFMON4_PERFCOUNTER_CNTL2 0x086f
+-#define mmDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX 2
+-#define mmDC_PERFMON4_PERFCOUNTER_STATE 0x0870
+-#define mmDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX 2
+-#define mmDC_PERFMON4_PERFMON_CNTL 0x0871
+-#define mmDC_PERFMON4_PERFMON_CNTL_BASE_IDX 2
+-#define mmDC_PERFMON4_PERFMON_CNTL2 0x0872
+-#define mmDC_PERFMON4_PERFMON_CNTL2_BASE_IDX 2
+-#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x0873
+-#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+-#define mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x0874
+-#define mmDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX 2
+-#define mmDC_PERFMON4_PERFMON_HI 0x0875
+-#define mmDC_PERFMON4_PERFMON_HI_BASE_IDX 2
+-#define mmDC_PERFMON4_PERFMON_LOW 0x0876
+-#define mmDC_PERFMON4_PERFMON_LOW_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dmif_pg1_dispdec
+-// base address: 0x800
+-#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 0x087a
+-#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
+-#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 0x087b
+-#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
+-#define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 0x087c
+-#define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2
+-#define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL 0x087d
+-#define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2
+-#define mmDMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL 0x087e
+-#define mmDMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2
+-#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL 0x087f
+-#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2
+-#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL2 0x0880
+-#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2
+-#define mmDMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL 0x0881
+-#define mmDMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2
+-#define mmDMIF_PG1_DPG_REPEATER_PROGRAM 0x0882
+-#define mmDMIF_PG1_DPG_REPEATER_PROGRAM_BASE_IDX 2
+-#define mmDMIF_PG1_DPG_CHK_PRE_PROC_CNTL 0x0886
+-#define mmDMIF_PG1_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2
+-#define mmDMIF_PG1_DPG_DVMM_STATUS 0x0887
+-#define mmDMIF_PG1_DPG_DVMM_STATUS_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_scl1_dispdec
+-// base address: 0x800
+-#define mmSCL1_SCL_COEF_RAM_SELECT 0x089a
+-#define mmSCL1_SCL_COEF_RAM_SELECT_BASE_IDX 2
+-#define mmSCL1_SCL_COEF_RAM_TAP_DATA 0x089b
+-#define mmSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
+-#define mmSCL1_SCL_MODE 0x089c
+-#define mmSCL1_SCL_MODE_BASE_IDX 2
+-#define mmSCL1_SCL_TAP_CONTROL 0x089d
+-#define mmSCL1_SCL_TAP_CONTROL_BASE_IDX 2
+-#define mmSCL1_SCL_CONTROL 0x089e
+-#define mmSCL1_SCL_CONTROL_BASE_IDX 2
+-#define mmSCL1_SCL_BYPASS_CONTROL 0x089f
+-#define mmSCL1_SCL_BYPASS_CONTROL_BASE_IDX 2
+-#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x08a0
+-#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
+-#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL 0x08a1
+-#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2
+-#define mmSCL1_SCL_HORZ_FILTER_CONTROL 0x08a2
+-#define mmSCL1_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2
+-#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x08a3
+-#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
+-#define mmSCL1_SCL_HORZ_FILTER_INIT 0x08a4
+-#define mmSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2
+-#define mmSCL1_SCL_VERT_FILTER_CONTROL 0x08a5
+-#define mmSCL1_SCL_VERT_FILTER_CONTROL_BASE_IDX 2
+-#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x08a6
+-#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
+-#define mmSCL1_SCL_VERT_FILTER_INIT 0x08a7
+-#define mmSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2
+-#define mmSCL1_SCL_VERT_FILTER_INIT_BOT 0x08a8
+-#define mmSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
+-#define mmSCL1_SCL_ROUND_OFFSET 0x08a9
+-#define mmSCL1_SCL_ROUND_OFFSET_BASE_IDX 2
+-#define mmSCL1_SCL_UPDATE 0x08aa
+-#define mmSCL1_SCL_UPDATE_BASE_IDX 2
+-#define mmSCL1_SCL_F_SHARP_CONTROL 0x08ab
+-#define mmSCL1_SCL_F_SHARP_CONTROL_BASE_IDX 2
+-#define mmSCL1_SCL_ALU_CONTROL 0x08ac
+-#define mmSCL1_SCL_ALU_CONTROL_BASE_IDX 2
+-#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0x08ad
+-#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
+-#define mmSCL1_VIEWPORT_START_SECONDARY 0x08ae
+-#define mmSCL1_VIEWPORT_START_SECONDARY_BASE_IDX 2
+-#define mmSCL1_VIEWPORT_START 0x08af
+-#define mmSCL1_VIEWPORT_START_BASE_IDX 2
+-#define mmSCL1_VIEWPORT_SIZE 0x08b0
+-#define mmSCL1_VIEWPORT_SIZE_BASE_IDX 2
+-#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT 0x08b1
+-#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
+-#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM 0x08b2
+-#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
+-#define mmSCL1_SCL_MODE_CHANGE_DET1 0x08b3
+-#define mmSCL1_SCL_MODE_CHANGE_DET1_BASE_IDX 2
+-#define mmSCL1_SCL_MODE_CHANGE_DET2 0x08b4
+-#define mmSCL1_SCL_MODE_CHANGE_DET2_BASE_IDX 2
+-#define mmSCL1_SCL_MODE_CHANGE_DET3 0x08b5
+-#define mmSCL1_SCL_MODE_CHANGE_DET3_BASE_IDX 2
+-#define mmSCL1_SCL_MODE_CHANGE_MASK 0x08b6
+-#define mmSCL1_SCL_MODE_CHANGE_MASK_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_blnd1_dispdec
+-// base address: 0x800
+-#define mmBLND1_BLND_CONTROL 0x08c7
+-#define mmBLND1_BLND_CONTROL_BASE_IDX 2
+-#define mmBLND1_BLND_SM_CONTROL2 0x08c8
+-#define mmBLND1_BLND_SM_CONTROL2_BASE_IDX 2
+-#define mmBLND1_BLND_CONTROL2 0x08c9
+-#define mmBLND1_BLND_CONTROL2_BASE_IDX 2
+-#define mmBLND1_BLND_UPDATE 0x08ca
+-#define mmBLND1_BLND_UPDATE_BASE_IDX 2
+-#define mmBLND1_BLND_UNDERFLOW_INTERRUPT 0x08cb
+-#define mmBLND1_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2
+-#define mmBLND1_BLND_V_UPDATE_LOCK 0x08cc
+-#define mmBLND1_BLND_V_UPDATE_LOCK_BASE_IDX 2
+-#define mmBLND1_BLND_REG_UPDATE_STATUS 0x08cd
+-#define mmBLND1_BLND_REG_UPDATE_STATUS_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_crtc1_dispdec
+-// base address: 0x800
+-#define mmCRTC1_CRTC_H_BLANK_EARLY_NUM 0x08d2
+-#define mmCRTC1_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2
+-#define mmCRTC1_CRTC_H_TOTAL 0x08d3
+-#define mmCRTC1_CRTC_H_TOTAL_BASE_IDX 2
+-#define mmCRTC1_CRTC_H_BLANK_START_END 0x08d4
+-#define mmCRTC1_CRTC_H_BLANK_START_END_BASE_IDX 2
+-#define mmCRTC1_CRTC_H_SYNC_A 0x08d5
+-#define mmCRTC1_CRTC_H_SYNC_A_BASE_IDX 2
+-#define mmCRTC1_CRTC_H_SYNC_A_CNTL 0x08d6
+-#define mmCRTC1_CRTC_H_SYNC_A_CNTL_BASE_IDX 2
+-#define mmCRTC1_CRTC_H_SYNC_B 0x08d7
+-#define mmCRTC1_CRTC_H_SYNC_B_BASE_IDX 2
+-#define mmCRTC1_CRTC_H_SYNC_B_CNTL 0x08d8
+-#define mmCRTC1_CRTC_H_SYNC_B_CNTL_BASE_IDX 2
+-#define mmCRTC1_CRTC_VBI_END 0x08d9
+-#define mmCRTC1_CRTC_VBI_END_BASE_IDX 2
+-#define mmCRTC1_CRTC_V_TOTAL 0x08da
+-#define mmCRTC1_CRTC_V_TOTAL_BASE_IDX 2
+-#define mmCRTC1_CRTC_V_TOTAL_MIN 0x08db
+-#define mmCRTC1_CRTC_V_TOTAL_MIN_BASE_IDX 2
+-#define mmCRTC1_CRTC_V_TOTAL_MAX 0x08dc
+-#define mmCRTC1_CRTC_V_TOTAL_MAX_BASE_IDX 2
+-#define mmCRTC1_CRTC_V_TOTAL_CONTROL 0x08dd
+-#define mmCRTC1_CRTC_V_TOTAL_CONTROL_BASE_IDX 2
+-#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS 0x08de
+-#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2
+-#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS 0x08df
+-#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2
+-#define mmCRTC1_CRTC_V_BLANK_START_END 0x08e0
+-#define mmCRTC1_CRTC_V_BLANK_START_END_BASE_IDX 2
+-#define mmCRTC1_CRTC_V_SYNC_A 0x08e1
+-#define mmCRTC1_CRTC_V_SYNC_A_BASE_IDX 2
+-#define mmCRTC1_CRTC_V_SYNC_A_CNTL 0x08e2
+-#define mmCRTC1_CRTC_V_SYNC_A_CNTL_BASE_IDX 2
+-#define mmCRTC1_CRTC_V_SYNC_B 0x08e3
+-#define mmCRTC1_CRTC_V_SYNC_B_BASE_IDX 2
+-#define mmCRTC1_CRTC_V_SYNC_B_CNTL 0x08e4
+-#define mmCRTC1_CRTC_V_SYNC_B_CNTL_BASE_IDX 2
+-#define mmCRTC1_CRTC_DTMTEST_CNTL 0x08e5
+-#define mmCRTC1_CRTC_DTMTEST_CNTL_BASE_IDX 2
+-#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION 0x08e6
+-#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2
+-#define mmCRTC1_CRTC_TRIGA_CNTL 0x08e7
+-#define mmCRTC1_CRTC_TRIGA_CNTL_BASE_IDX 2
+-#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG 0x08e8
+-#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2
+-#define mmCRTC1_CRTC_TRIGB_CNTL 0x08e9
+-#define mmCRTC1_CRTC_TRIGB_CNTL_BASE_IDX 2
+-#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG 0x08ea
+-#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2
+-#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL 0x08eb
+-#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
+-#define mmCRTC1_CRTC_FLOW_CONTROL 0x08ec
+-#define mmCRTC1_CRTC_FLOW_CONTROL_BASE_IDX 2
+-#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE 0x08ed
+-#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
+-#define mmCRTC1_CRTC_AVSYNC_COUNTER 0x08ee
+-#define mmCRTC1_CRTC_AVSYNC_COUNTER_BASE_IDX 2
+-#define mmCRTC1_CRTC_CONTROL 0x08ef
+-#define mmCRTC1_CRTC_CONTROL_BASE_IDX 2
+-#define mmCRTC1_CRTC_BLANK_CONTROL 0x08f0
+-#define mmCRTC1_CRTC_BLANK_CONTROL_BASE_IDX 2
+-#define mmCRTC1_CRTC_INTERLACE_CONTROL 0x08f1
+-#define mmCRTC1_CRTC_INTERLACE_CONTROL_BASE_IDX 2
+-#define mmCRTC1_CRTC_INTERLACE_STATUS 0x08f2
+-#define mmCRTC1_CRTC_INTERLACE_STATUS_BASE_IDX 2
+-#define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL 0x08f3
+-#define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2
+-#define mmCRTC1_CRTC_PIXEL_DATA_READBACK0 0x08f4
+-#define mmCRTC1_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2
+-#define mmCRTC1_CRTC_PIXEL_DATA_READBACK1 0x08f5
+-#define mmCRTC1_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2
+-#define mmCRTC1_CRTC_STATUS 0x08f6
+-#define mmCRTC1_CRTC_STATUS_BASE_IDX 2
+-#define mmCRTC1_CRTC_STATUS_POSITION 0x08f7
+-#define mmCRTC1_CRTC_STATUS_POSITION_BASE_IDX 2
+-#define mmCRTC1_CRTC_NOM_VERT_POSITION 0x08f8
+-#define mmCRTC1_CRTC_NOM_VERT_POSITION_BASE_IDX 2
+-#define mmCRTC1_CRTC_STATUS_FRAME_COUNT 0x08f9
+-#define mmCRTC1_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2
+-#define mmCRTC1_CRTC_STATUS_VF_COUNT 0x08fa
+-#define mmCRTC1_CRTC_STATUS_VF_COUNT_BASE_IDX 2
+-#define mmCRTC1_CRTC_STATUS_HV_COUNT 0x08fb
+-#define mmCRTC1_CRTC_STATUS_HV_COUNT_BASE_IDX 2
+-#define mmCRTC1_CRTC_COUNT_CONTROL 0x08fc
+-#define mmCRTC1_CRTC_COUNT_CONTROL_BASE_IDX 2
+-#define mmCRTC1_CRTC_COUNT_RESET 0x08fd
+-#define mmCRTC1_CRTC_COUNT_RESET_BASE_IDX 2
+-#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x08fe
+-#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
+-#define mmCRTC1_CRTC_VERT_SYNC_CONTROL 0x08ff
+-#define mmCRTC1_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2
+-#define mmCRTC1_CRTC_STEREO_STATUS 0x0900
+-#define mmCRTC1_CRTC_STEREO_STATUS_BASE_IDX 2
+-#define mmCRTC1_CRTC_STEREO_CONTROL 0x0901
+-#define mmCRTC1_CRTC_STEREO_CONTROL_BASE_IDX 2
+-#define mmCRTC1_CRTC_SNAPSHOT_STATUS 0x0902
+-#define mmCRTC1_CRTC_SNAPSHOT_STATUS_BASE_IDX 2
+-#define mmCRTC1_CRTC_SNAPSHOT_CONTROL 0x0903
+-#define mmCRTC1_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2
+-#define mmCRTC1_CRTC_SNAPSHOT_POSITION 0x0904
+-#define mmCRTC1_CRTC_SNAPSHOT_POSITION_BASE_IDX 2
+-#define mmCRTC1_CRTC_SNAPSHOT_FRAME 0x0905
+-#define mmCRTC1_CRTC_SNAPSHOT_FRAME_BASE_IDX 2
+-#define mmCRTC1_CRTC_START_LINE_CONTROL 0x0906
+-#define mmCRTC1_CRTC_START_LINE_CONTROL_BASE_IDX 2
+-#define mmCRTC1_CRTC_INTERRUPT_CONTROL 0x0907
+-#define mmCRTC1_CRTC_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmCRTC1_CRTC_UPDATE_LOCK 0x0908
+-#define mmCRTC1_CRTC_UPDATE_LOCK_BASE_IDX 2
+-#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL 0x0909
+-#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
+-#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x090a
+-#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2
+-#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL 0x090b
+-#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2
+-#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS 0x090c
+-#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2
+-#define mmCRTC1_CRTC_TEST_PATTERN_COLOR 0x090d
+-#define mmCRTC1_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2
+-#define mmCRTC1_CRTC_MASTER_UPDATE_LOCK 0x090e
+-#define mmCRTC1_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2
+-#define mmCRTC1_CRTC_MASTER_UPDATE_MODE 0x090f
+-#define mmCRTC1_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2
+-#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT 0x0910
+-#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2
+-#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x0911
+-#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2
+-#define mmCRTC1_CRTC_MVP_STATUS 0x0912
+-#define mmCRTC1_CRTC_MVP_STATUS_BASE_IDX 2
+-#define mmCRTC1_CRTC_MASTER_EN 0x0913
+-#define mmCRTC1_CRTC_MASTER_EN_BASE_IDX 2
+-#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT 0x0914
+-#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2
+-#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS 0x0915
+-#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2
+-#define mmCRTC1_CRTC_OVERSCAN_COLOR 0x0917
+-#define mmCRTC1_CRTC_OVERSCAN_COLOR_BASE_IDX 2
+-#define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT 0x0918
+-#define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2
+-#define mmCRTC1_CRTC_BLANK_DATA_COLOR 0x0919
+-#define mmCRTC1_CRTC_BLANK_DATA_COLOR_BASE_IDX 2
+-#define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT 0x091a
+-#define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2
+-#define mmCRTC1_CRTC_BLACK_COLOR 0x091b
+-#define mmCRTC1_CRTC_BLACK_COLOR_BASE_IDX 2
+-#define mmCRTC1_CRTC_BLACK_COLOR_EXT 0x091c
+-#define mmCRTC1_CRTC_BLACK_COLOR_EXT_BASE_IDX 2
+-#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION 0x091d
+-#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
+-#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x091e
+-#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
+-#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION 0x091f
+-#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
+-#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x0920
+-#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
+-#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION 0x0921
+-#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
+-#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x0922
+-#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
+-#define mmCRTC1_CRTC_CRC_CNTL 0x0923
+-#define mmCRTC1_CRTC_CRC_CNTL_BASE_IDX 2
+-#define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL 0x0924
+-#define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
+-#define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL 0x0925
+-#define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
+-#define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL 0x0926
+-#define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
+-#define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL 0x0927
+-#define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
+-#define mmCRTC1_CRTC_CRC0_DATA_RG 0x0928
+-#define mmCRTC1_CRTC_CRC0_DATA_RG_BASE_IDX 2
+-#define mmCRTC1_CRTC_CRC0_DATA_B 0x0929
+-#define mmCRTC1_CRTC_CRC0_DATA_B_BASE_IDX 2
+-#define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL 0x092a
+-#define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
+-#define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL 0x092b
+-#define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
+-#define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL 0x092c
+-#define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
+-#define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL 0x092d
+-#define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
+-#define mmCRTC1_CRTC_CRC1_DATA_RG 0x092e
+-#define mmCRTC1_CRTC_CRC1_DATA_RG_BASE_IDX 2
+-#define mmCRTC1_CRTC_CRC1_DATA_B 0x092f
+-#define mmCRTC1_CRTC_CRC1_DATA_B_BASE_IDX 2
+-#define mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL 0x0930
+-#define mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2
+-#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x0931
+-#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2
+-#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x0932
+-#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2
+-#define mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x0933
+-#define mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x0934
+-#define mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x0935
+-#define mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL 0x0936
+-#define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2
+-#define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL 0x0937
+-#define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2
+-#define mmCRTC1_CRTC_GSL_VSYNC_GAP 0x0938
+-#define mmCRTC1_CRTC_GSL_VSYNC_GAP_BASE_IDX 2
+-#define mmCRTC1_CRTC_GSL_WINDOW 0x0939
+-#define mmCRTC1_CRTC_GSL_WINDOW_BASE_IDX 2
+-#define mmCRTC1_CRTC_GSL_CONTROL 0x093a
+-#define mmCRTC1_CRTC_GSL_CONTROL_BASE_IDX 2
+-#define mmCRTC1_CRTC_RANGE_TIMING_INT_STATUS 0x093d
+-#define mmCRTC1_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2
+-#define mmCRTC1_CRTC_DRR_CONTROL 0x093e
+-#define mmCRTC1_CRTC_DRR_CONTROL_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_fmt1_dispdec
+-// base address: 0x800
+-#define mmFMT1_FMT_CLAMP_COMPONENT_R 0x0942
+-#define mmFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
+-#define mmFMT1_FMT_CLAMP_COMPONENT_G 0x0943
+-#define mmFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
+-#define mmFMT1_FMT_CLAMP_COMPONENT_B 0x0944
+-#define mmFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
+-#define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x0945
+-#define mmFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
+-#define mmFMT1_FMT_CONTROL 0x0946
+-#define mmFMT1_FMT_CONTROL_BASE_IDX 2
+-#define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x0947
+-#define mmFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
+-#define mmFMT1_FMT_DITHER_RAND_R_SEED 0x0948
+-#define mmFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
+-#define mmFMT1_FMT_DITHER_RAND_G_SEED 0x0949
+-#define mmFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
+-#define mmFMT1_FMT_DITHER_RAND_B_SEED 0x094a
+-#define mmFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
+-#define mmFMT1_FMT_CLAMP_CNTL 0x094e
+-#define mmFMT1_FMT_CLAMP_CNTL_BASE_IDX 2
+-#define mmFMT1_FMT_CRC_CNTL 0x094f
+-#define mmFMT1_FMT_CRC_CNTL_BASE_IDX 2
+-#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK 0x0950
+-#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
+-#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x0951
+-#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
+-#define mmFMT1_FMT_CRC_SIG_RED_GREEN 0x0952
+-#define mmFMT1_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2
+-#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL 0x0953
+-#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2
+-#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x0954
+-#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
+-#define mmFMT1_FMT_420_HBLANK_EARLY_START 0x0955
+-#define mmFMT1_FMT_420_HBLANK_EARLY_START_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dcp2_dispdec
+-// base address: 0x1000
+-#define mmDCP2_GRPH_ENABLE 0x095a
+-#define mmDCP2_GRPH_ENABLE_BASE_IDX 2
+-#define mmDCP2_GRPH_CONTROL 0x095b
+-#define mmDCP2_GRPH_CONTROL_BASE_IDX 2
+-#define mmDCP2_GRPH_LUT_10BIT_BYPASS 0x095c
+-#define mmDCP2_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2
+-#define mmDCP2_GRPH_SWAP_CNTL 0x095d
+-#define mmDCP2_GRPH_SWAP_CNTL_BASE_IDX 2
+-#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS 0x095e
+-#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
+-#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS 0x095f
+-#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
+-#define mmDCP2_GRPH_PITCH 0x0960
+-#define mmDCP2_GRPH_PITCH_BASE_IDX 2
+-#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0961
+-#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+-#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0962
+-#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+-#define mmDCP2_GRPH_SURFACE_OFFSET_X 0x0963
+-#define mmDCP2_GRPH_SURFACE_OFFSET_X_BASE_IDX 2
+-#define mmDCP2_GRPH_SURFACE_OFFSET_Y 0x0964
+-#define mmDCP2_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2
+-#define mmDCP2_GRPH_X_START 0x0965
+-#define mmDCP2_GRPH_X_START_BASE_IDX 2
+-#define mmDCP2_GRPH_Y_START 0x0966
+-#define mmDCP2_GRPH_Y_START_BASE_IDX 2
+-#define mmDCP2_GRPH_X_END 0x0967
+-#define mmDCP2_GRPH_X_END_BASE_IDX 2
+-#define mmDCP2_GRPH_Y_END 0x0968
+-#define mmDCP2_GRPH_Y_END_BASE_IDX 2
+-#define mmDCP2_INPUT_GAMMA_CONTROL 0x0969
+-#define mmDCP2_INPUT_GAMMA_CONTROL_BASE_IDX 2
+-#define mmDCP2_GRPH_UPDATE 0x096a
+-#define mmDCP2_GRPH_UPDATE_BASE_IDX 2
+-#define mmDCP2_GRPH_FLIP_CONTROL 0x096b
+-#define mmDCP2_GRPH_FLIP_CONTROL_BASE_IDX 2
+-#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE 0x096c
+-#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2
+-#define mmDCP2_GRPH_DFQ_CONTROL 0x096d
+-#define mmDCP2_GRPH_DFQ_CONTROL_BASE_IDX 2
+-#define mmDCP2_GRPH_DFQ_STATUS 0x096e
+-#define mmDCP2_GRPH_DFQ_STATUS_BASE_IDX 2
+-#define mmDCP2_GRPH_INTERRUPT_STATUS 0x096f
+-#define mmDCP2_GRPH_INTERRUPT_STATUS_BASE_IDX 2
+-#define mmDCP2_GRPH_INTERRUPT_CONTROL 0x0970
+-#define mmDCP2_GRPH_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0971
+-#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2
+-#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS 0x0972
+-#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2
+-#define mmDCP2_GRPH_COMPRESS_PITCH 0x0973
+-#define mmDCP2_GRPH_COMPRESS_PITCH_BASE_IDX 2
+-#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0974
+-#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+-#define mmDCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0975
+-#define mmDCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2
+-#define mmDCP2_PRESCALE_GRPH_CONTROL 0x0976
+-#define mmDCP2_PRESCALE_GRPH_CONTROL_BASE_IDX 2
+-#define mmDCP2_PRESCALE_VALUES_GRPH_R 0x0977
+-#define mmDCP2_PRESCALE_VALUES_GRPH_R_BASE_IDX 2
+-#define mmDCP2_PRESCALE_VALUES_GRPH_G 0x0978
+-#define mmDCP2_PRESCALE_VALUES_GRPH_G_BASE_IDX 2
+-#define mmDCP2_PRESCALE_VALUES_GRPH_B 0x0979
+-#define mmDCP2_PRESCALE_VALUES_GRPH_B_BASE_IDX 2
+-#define mmDCP2_INPUT_CSC_CONTROL 0x097a
+-#define mmDCP2_INPUT_CSC_CONTROL_BASE_IDX 2
+-#define mmDCP2_INPUT_CSC_C11_C12 0x097b
+-#define mmDCP2_INPUT_CSC_C11_C12_BASE_IDX 2
+-#define mmDCP2_INPUT_CSC_C13_C14 0x097c
+-#define mmDCP2_INPUT_CSC_C13_C14_BASE_IDX 2
+-#define mmDCP2_INPUT_CSC_C21_C22 0x097d
+-#define mmDCP2_INPUT_CSC_C21_C22_BASE_IDX 2
+-#define mmDCP2_INPUT_CSC_C23_C24 0x097e
+-#define mmDCP2_INPUT_CSC_C23_C24_BASE_IDX 2
+-#define mmDCP2_INPUT_CSC_C31_C32 0x097f
+-#define mmDCP2_INPUT_CSC_C31_C32_BASE_IDX 2
+-#define mmDCP2_INPUT_CSC_C33_C34 0x0980
+-#define mmDCP2_INPUT_CSC_C33_C34_BASE_IDX 2
+-#define mmDCP2_OUTPUT_CSC_CONTROL 0x0981
+-#define mmDCP2_OUTPUT_CSC_CONTROL_BASE_IDX 2
+-#define mmDCP2_OUTPUT_CSC_C11_C12 0x0982
+-#define mmDCP2_OUTPUT_CSC_C11_C12_BASE_IDX 2
+-#define mmDCP2_OUTPUT_CSC_C13_C14 0x0983
+-#define mmDCP2_OUTPUT_CSC_C13_C14_BASE_IDX 2
+-#define mmDCP2_OUTPUT_CSC_C21_C22 0x0984
+-#define mmDCP2_OUTPUT_CSC_C21_C22_BASE_IDX 2
+-#define mmDCP2_OUTPUT_CSC_C23_C24 0x0985
+-#define mmDCP2_OUTPUT_CSC_C23_C24_BASE_IDX 2
+-#define mmDCP2_OUTPUT_CSC_C31_C32 0x0986
+-#define mmDCP2_OUTPUT_CSC_C31_C32_BASE_IDX 2
+-#define mmDCP2_OUTPUT_CSC_C33_C34 0x0987
+-#define mmDCP2_OUTPUT_CSC_C33_C34_BASE_IDX 2
+-#define mmDCP2_COMM_MATRIXA_TRANS_C11_C12 0x0988
+-#define mmDCP2_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2
+-#define mmDCP2_COMM_MATRIXA_TRANS_C13_C14 0x0989
+-#define mmDCP2_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2
+-#define mmDCP2_COMM_MATRIXA_TRANS_C21_C22 0x098a
+-#define mmDCP2_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2
+-#define mmDCP2_COMM_MATRIXA_TRANS_C23_C24 0x098b
+-#define mmDCP2_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2
+-#define mmDCP2_COMM_MATRIXA_TRANS_C31_C32 0x098c
+-#define mmDCP2_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2
+-#define mmDCP2_COMM_MATRIXA_TRANS_C33_C34 0x098d
+-#define mmDCP2_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2
+-#define mmDCP2_COMM_MATRIXB_TRANS_C11_C12 0x098e
+-#define mmDCP2_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2
+-#define mmDCP2_COMM_MATRIXB_TRANS_C13_C14 0x098f
+-#define mmDCP2_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2
+-#define mmDCP2_COMM_MATRIXB_TRANS_C21_C22 0x0990
+-#define mmDCP2_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2
+-#define mmDCP2_COMM_MATRIXB_TRANS_C23_C24 0x0991
+-#define mmDCP2_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2
+-#define mmDCP2_COMM_MATRIXB_TRANS_C31_C32 0x0992
+-#define mmDCP2_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2
+-#define mmDCP2_COMM_MATRIXB_TRANS_C33_C34 0x0993
+-#define mmDCP2_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2
+-#define mmDCP2_DENORM_CONTROL 0x0994
+-#define mmDCP2_DENORM_CONTROL_BASE_IDX 2
+-#define mmDCP2_OUT_ROUND_CONTROL 0x0995
+-#define mmDCP2_OUT_ROUND_CONTROL_BASE_IDX 2
+-#define mmDCP2_OUT_CLAMP_CONTROL_R_CR 0x0996
+-#define mmDCP2_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2
+-#define mmDCP2_OUT_CLAMP_CONTROL_G_Y 0x0997
+-#define mmDCP2_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2
+-#define mmDCP2_OUT_CLAMP_CONTROL_B_CB 0x0998
+-#define mmDCP2_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2
+-#define mmDCP2_KEY_CONTROL 0x0999
+-#define mmDCP2_KEY_CONTROL_BASE_IDX 2
+-#define mmDCP2_KEY_RANGE_ALPHA 0x099a
+-#define mmDCP2_KEY_RANGE_ALPHA_BASE_IDX 2
+-#define mmDCP2_KEY_RANGE_RED 0x099b
+-#define mmDCP2_KEY_RANGE_RED_BASE_IDX 2
+-#define mmDCP2_KEY_RANGE_GREEN 0x099c
+-#define mmDCP2_KEY_RANGE_GREEN_BASE_IDX 2
+-#define mmDCP2_KEY_RANGE_BLUE 0x099d
+-#define mmDCP2_KEY_RANGE_BLUE_BASE_IDX 2
+-#define mmDCP2_DEGAMMA_CONTROL 0x099e
+-#define mmDCP2_DEGAMMA_CONTROL_BASE_IDX 2
+-#define mmDCP2_GAMUT_REMAP_CONTROL 0x099f
+-#define mmDCP2_GAMUT_REMAP_CONTROL_BASE_IDX 2
+-#define mmDCP2_GAMUT_REMAP_C11_C12 0x09a0
+-#define mmDCP2_GAMUT_REMAP_C11_C12_BASE_IDX 2
+-#define mmDCP2_GAMUT_REMAP_C13_C14 0x09a1
+-#define mmDCP2_GAMUT_REMAP_C13_C14_BASE_IDX 2
+-#define mmDCP2_GAMUT_REMAP_C21_C22 0x09a2
+-#define mmDCP2_GAMUT_REMAP_C21_C22_BASE_IDX 2
+-#define mmDCP2_GAMUT_REMAP_C23_C24 0x09a3
+-#define mmDCP2_GAMUT_REMAP_C23_C24_BASE_IDX 2
+-#define mmDCP2_GAMUT_REMAP_C31_C32 0x09a4
+-#define mmDCP2_GAMUT_REMAP_C31_C32_BASE_IDX 2
+-#define mmDCP2_GAMUT_REMAP_C33_C34 0x09a5
+-#define mmDCP2_GAMUT_REMAP_C33_C34_BASE_IDX 2
+-#define mmDCP2_DCP_SPATIAL_DITHER_CNTL 0x09a6
+-#define mmDCP2_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2
+-#define mmDCP2_DCP_RANDOM_SEEDS 0x09a7
+-#define mmDCP2_DCP_RANDOM_SEEDS_BASE_IDX 2
+-#define mmDCP2_DCP_FP_CONVERTED_FIELD 0x09a8
+-#define mmDCP2_DCP_FP_CONVERTED_FIELD_BASE_IDX 2
+-#define mmDCP2_CUR_CONTROL 0x09a9
+-#define mmDCP2_CUR_CONTROL_BASE_IDX 2
+-#define mmDCP2_CUR_SURFACE_ADDRESS 0x09aa
+-#define mmDCP2_CUR_SURFACE_ADDRESS_BASE_IDX 2
+-#define mmDCP2_CUR_SIZE 0x09ab
+-#define mmDCP2_CUR_SIZE_BASE_IDX 2
+-#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH 0x09ac
+-#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+-#define mmDCP2_CUR_POSITION 0x09ad
+-#define mmDCP2_CUR_POSITION_BASE_IDX 2
+-#define mmDCP2_CUR_HOT_SPOT 0x09ae
+-#define mmDCP2_CUR_HOT_SPOT_BASE_IDX 2
+-#define mmDCP2_CUR_COLOR1 0x09af
+-#define mmDCP2_CUR_COLOR1_BASE_IDX 2
+-#define mmDCP2_CUR_COLOR2 0x09b0
+-#define mmDCP2_CUR_COLOR2_BASE_IDX 2
+-#define mmDCP2_CUR_UPDATE 0x09b1
+-#define mmDCP2_CUR_UPDATE_BASE_IDX 2
+-#define mmDCP2_CUR_REQUEST_FILTER_CNTL 0x09bb
+-#define mmDCP2_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2
+-#define mmDCP2_CUR_STEREO_CONTROL 0x09bc
+-#define mmDCP2_CUR_STEREO_CONTROL_BASE_IDX 2
+-#define mmDCP2_DC_LUT_RW_MODE 0x09be
+-#define mmDCP2_DC_LUT_RW_MODE_BASE_IDX 2
+-#define mmDCP2_DC_LUT_RW_INDEX 0x09bf
+-#define mmDCP2_DC_LUT_RW_INDEX_BASE_IDX 2
+-#define mmDCP2_DC_LUT_SEQ_COLOR 0x09c0
+-#define mmDCP2_DC_LUT_SEQ_COLOR_BASE_IDX 2
+-#define mmDCP2_DC_LUT_PWL_DATA 0x09c1
+-#define mmDCP2_DC_LUT_PWL_DATA_BASE_IDX 2
+-#define mmDCP2_DC_LUT_30_COLOR 0x09c2
+-#define mmDCP2_DC_LUT_30_COLOR_BASE_IDX 2
+-#define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE 0x09c3
+-#define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2
+-#define mmDCP2_DC_LUT_WRITE_EN_MASK 0x09c4
+-#define mmDCP2_DC_LUT_WRITE_EN_MASK_BASE_IDX 2
+-#define mmDCP2_DC_LUT_AUTOFILL 0x09c5
+-#define mmDCP2_DC_LUT_AUTOFILL_BASE_IDX 2
+-#define mmDCP2_DC_LUT_CONTROL 0x09c6
+-#define mmDCP2_DC_LUT_CONTROL_BASE_IDX 2
+-#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE 0x09c7
+-#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2
+-#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN 0x09c8
+-#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2
+-#define mmDCP2_DC_LUT_BLACK_OFFSET_RED 0x09c9
+-#define mmDCP2_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2
+-#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE 0x09ca
+-#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2
+-#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN 0x09cb
+-#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2
+-#define mmDCP2_DC_LUT_WHITE_OFFSET_RED 0x09cc
+-#define mmDCP2_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2
+-#define mmDCP2_DCP_CRC_CONTROL 0x09cd
+-#define mmDCP2_DCP_CRC_CONTROL_BASE_IDX 2
+-#define mmDCP2_DCP_CRC_MASK 0x09ce
+-#define mmDCP2_DCP_CRC_MASK_BASE_IDX 2
+-#define mmDCP2_DCP_CRC_CURRENT 0x09cf
+-#define mmDCP2_DCP_CRC_CURRENT_BASE_IDX 2
+-#define mmDCP2_DVMM_PTE_CONTROL 0x09d0
+-#define mmDCP2_DVMM_PTE_CONTROL_BASE_IDX 2
+-#define mmDCP2_DCP_CRC_LAST 0x09d1
+-#define mmDCP2_DCP_CRC_LAST_BASE_IDX 2
+-#define mmDCP2_DVMM_PTE_ARB_CONTROL 0x09d2
+-#define mmDCP2_DVMM_PTE_ARB_CONTROL_BASE_IDX 2
+-#define mmDCP2_GRPH_FLIP_RATE_CNTL 0x09d4
+-#define mmDCP2_GRPH_FLIP_RATE_CNTL_BASE_IDX 2
+-#define mmDCP2_DCP_GSL_CONTROL 0x09d5
+-#define mmDCP2_DCP_GSL_CONTROL_BASE_IDX 2
+-#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x09d6
+-#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2
+-#define mmDCP2_GRPH_STEREOSYNC_FLIP 0x09dc
+-#define mmDCP2_GRPH_STEREOSYNC_FLIP_BASE_IDX 2
+-#define mmDCP2_HW_ROTATION 0x09de
+-#define mmDCP2_HW_ROTATION_BASE_IDX 2
+-#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x09df
+-#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2
+-#define mmDCP2_REGAMMA_CONTROL 0x09e0
+-#define mmDCP2_REGAMMA_CONTROL_BASE_IDX 2
+-#define mmDCP2_REGAMMA_LUT_INDEX 0x09e1
+-#define mmDCP2_REGAMMA_LUT_INDEX_BASE_IDX 2
+-#define mmDCP2_REGAMMA_LUT_DATA 0x09e2
+-#define mmDCP2_REGAMMA_LUT_DATA_BASE_IDX 2
+-#define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK 0x09e3
+-#define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2
+-#define mmDCP2_REGAMMA_CNTLA_START_CNTL 0x09e4
+-#define mmDCP2_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2
+-#define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL 0x09e5
+-#define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2
+-#define mmDCP2_REGAMMA_CNTLA_END_CNTL1 0x09e6
+-#define mmDCP2_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2
+-#define mmDCP2_REGAMMA_CNTLA_END_CNTL2 0x09e7
+-#define mmDCP2_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2
+-#define mmDCP2_REGAMMA_CNTLA_REGION_0_1 0x09e8
+-#define mmDCP2_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2
+-#define mmDCP2_REGAMMA_CNTLA_REGION_2_3 0x09e9
+-#define mmDCP2_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2
+-#define mmDCP2_REGAMMA_CNTLA_REGION_4_5 0x09ea
+-#define mmDCP2_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2
+-#define mmDCP2_REGAMMA_CNTLA_REGION_6_7 0x09eb
+-#define mmDCP2_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2
+-#define mmDCP2_REGAMMA_CNTLA_REGION_8_9 0x09ec
+-#define mmDCP2_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2
+-#define mmDCP2_REGAMMA_CNTLA_REGION_10_11 0x09ed
+-#define mmDCP2_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2
+-#define mmDCP2_REGAMMA_CNTLA_REGION_12_13 0x09ee
+-#define mmDCP2_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2
+-#define mmDCP2_REGAMMA_CNTLA_REGION_14_15 0x09ef
+-#define mmDCP2_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2
+-#define mmDCP2_REGAMMA_CNTLB_START_CNTL 0x09f0
+-#define mmDCP2_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2
+-#define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL 0x09f1
+-#define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2
+-#define mmDCP2_REGAMMA_CNTLB_END_CNTL1 0x09f2
+-#define mmDCP2_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2
+-#define mmDCP2_REGAMMA_CNTLB_END_CNTL2 0x09f3
+-#define mmDCP2_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2
+-#define mmDCP2_REGAMMA_CNTLB_REGION_0_1 0x09f4
+-#define mmDCP2_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2
+-#define mmDCP2_REGAMMA_CNTLB_REGION_2_3 0x09f5
+-#define mmDCP2_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2
+-#define mmDCP2_REGAMMA_CNTLB_REGION_4_5 0x09f6
+-#define mmDCP2_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2
+-#define mmDCP2_REGAMMA_CNTLB_REGION_6_7 0x09f7
+-#define mmDCP2_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2
+-#define mmDCP2_REGAMMA_CNTLB_REGION_8_9 0x09f8
+-#define mmDCP2_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2
+-#define mmDCP2_REGAMMA_CNTLB_REGION_10_11 0x09f9
+-#define mmDCP2_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2
+-#define mmDCP2_REGAMMA_CNTLB_REGION_12_13 0x09fa
+-#define mmDCP2_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2
+-#define mmDCP2_REGAMMA_CNTLB_REGION_14_15 0x09fb
+-#define mmDCP2_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2
+-#define mmDCP2_ALPHA_CONTROL 0x09fc
+-#define mmDCP2_ALPHA_CONTROL_BASE_IDX 2
+-#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x09fd
+-#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2
+-#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x09fe
+-#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+-#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x09ff
+-#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2
+-#define mmDCP2_GRPH_XDMA_FLIP_TIMEOUT 0x0a00
+-#define mmDCP2_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2
+-#define mmDCP2_GRPH_XDMA_FLIP_AVG_DELAY 0x0a01
+-#define mmDCP2_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2
+-#define mmDCP2_GRPH_SURFACE_COUNTER_CONTROL 0x0a02
+-#define mmDCP2_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2
+-#define mmDCP2_GRPH_SURFACE_COUNTER_OUTPUT 0x0a03
+-#define mmDCP2_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_lb2_dispdec
+-// base address: 0x1000
+-#define mmLB2_LB_DATA_FORMAT 0x0a1a
+-#define mmLB2_LB_DATA_FORMAT_BASE_IDX 2
+-#define mmLB2_LB_MEMORY_CTRL 0x0a1b
+-#define mmLB2_LB_MEMORY_CTRL_BASE_IDX 2
+-#define mmLB2_LB_MEMORY_SIZE_STATUS 0x0a1c
+-#define mmLB2_LB_MEMORY_SIZE_STATUS_BASE_IDX 2
+-#define mmLB2_LB_DESKTOP_HEIGHT 0x0a1d
+-#define mmLB2_LB_DESKTOP_HEIGHT_BASE_IDX 2
+-#define mmLB2_LB_VLINE_START_END 0x0a1e
+-#define mmLB2_LB_VLINE_START_END_BASE_IDX 2
+-#define mmLB2_LB_VLINE2_START_END 0x0a1f
+-#define mmLB2_LB_VLINE2_START_END_BASE_IDX 2
+-#define mmLB2_LB_V_COUNTER 0x0a20
+-#define mmLB2_LB_V_COUNTER_BASE_IDX 2
+-#define mmLB2_LB_SNAPSHOT_V_COUNTER 0x0a21
+-#define mmLB2_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2
+-#define mmLB2_LB_INTERRUPT_MASK 0x0a22
+-#define mmLB2_LB_INTERRUPT_MASK_BASE_IDX 2
+-#define mmLB2_LB_VLINE_STATUS 0x0a23
+-#define mmLB2_LB_VLINE_STATUS_BASE_IDX 2
+-#define mmLB2_LB_VLINE2_STATUS 0x0a24
+-#define mmLB2_LB_VLINE2_STATUS_BASE_IDX 2
+-#define mmLB2_LB_VBLANK_STATUS 0x0a25
+-#define mmLB2_LB_VBLANK_STATUS_BASE_IDX 2
+-#define mmLB2_LB_SYNC_RESET_SEL 0x0a26
+-#define mmLB2_LB_SYNC_RESET_SEL_BASE_IDX 2
+-#define mmLB2_LB_BLACK_KEYER_R_CR 0x0a27
+-#define mmLB2_LB_BLACK_KEYER_R_CR_BASE_IDX 2
+-#define mmLB2_LB_BLACK_KEYER_G_Y 0x0a28
+-#define mmLB2_LB_BLACK_KEYER_G_Y_BASE_IDX 2
+-#define mmLB2_LB_BLACK_KEYER_B_CB 0x0a29
+-#define mmLB2_LB_BLACK_KEYER_B_CB_BASE_IDX 2
+-#define mmLB2_LB_KEYER_COLOR_CTRL 0x0a2a
+-#define mmLB2_LB_KEYER_COLOR_CTRL_BASE_IDX 2
+-#define mmLB2_LB_KEYER_COLOR_R_CR 0x0a2b
+-#define mmLB2_LB_KEYER_COLOR_R_CR_BASE_IDX 2
+-#define mmLB2_LB_KEYER_COLOR_G_Y 0x0a2c
+-#define mmLB2_LB_KEYER_COLOR_G_Y_BASE_IDX 2
+-#define mmLB2_LB_KEYER_COLOR_B_CB 0x0a2d
+-#define mmLB2_LB_KEYER_COLOR_B_CB_BASE_IDX 2
+-#define mmLB2_LB_KEYER_COLOR_REP_R_CR 0x0a2e
+-#define mmLB2_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2
+-#define mmLB2_LB_KEYER_COLOR_REP_G_Y 0x0a2f
+-#define mmLB2_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2
+-#define mmLB2_LB_KEYER_COLOR_REP_B_CB 0x0a30
+-#define mmLB2_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2
+-#define mmLB2_LB_BUFFER_LEVEL_STATUS 0x0a31
+-#define mmLB2_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2
+-#define mmLB2_LB_BUFFER_URGENCY_CTRL 0x0a32
+-#define mmLB2_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2
+-#define mmLB2_LB_BUFFER_URGENCY_STATUS 0x0a33
+-#define mmLB2_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2
+-#define mmLB2_LB_BUFFER_STATUS 0x0a34
+-#define mmLB2_LB_BUFFER_STATUS_BASE_IDX 2
+-#define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0x0a35
+-#define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2
+-#define mmLB2_MVP_AFR_FLIP_MODE 0x0a36
+-#define mmLB2_MVP_AFR_FLIP_MODE_BASE_IDX 2
+-#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0x0a37
+-#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2
+-#define mmLB2_MVP_FLIP_LINE_NUM_INSERT 0x0a38
+-#define mmLB2_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2
+-#define mmLB2_DC_MVP_LB_CONTROL 0x0a39
+-#define mmLB2_DC_MVP_LB_CONTROL_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dcfe2_dispdec
+-// base address: 0x1000
+-#define mmDCFE2_DCFE_CLOCK_CONTROL 0x0a5a
+-#define mmDCFE2_DCFE_CLOCK_CONTROL_BASE_IDX 2
+-#define mmDCFE2_DCFE_SOFT_RESET 0x0a5b
+-#define mmDCFE2_DCFE_SOFT_RESET_BASE_IDX 2
+-#define mmDCFE2_DCFE_MEM_PWR_CTRL 0x0a5d
+-#define mmDCFE2_DCFE_MEM_PWR_CTRL_BASE_IDX 2
+-#define mmDCFE2_DCFE_MEM_PWR_CTRL2 0x0a5e
+-#define mmDCFE2_DCFE_MEM_PWR_CTRL2_BASE_IDX 2
+-#define mmDCFE2_DCFE_MEM_PWR_STATUS 0x0a5f
+-#define mmDCFE2_DCFE_MEM_PWR_STATUS_BASE_IDX 2
+-#define mmDCFE2_DCFE_MISC 0x0a60
+-#define mmDCFE2_DCFE_MISC_BASE_IDX 2
+-#define mmDCFE2_DCFE_FLUSH 0x0a61
+-#define mmDCFE2_DCFE_FLUSH_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dc_perfmon5_dispdec
+-// base address: 0x2938
+-#define mmDC_PERFMON5_PERFCOUNTER_CNTL 0x0a6e
+-#define mmDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX 2
+-#define mmDC_PERFMON5_PERFCOUNTER_CNTL2 0x0a6f
+-#define mmDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX 2
+-#define mmDC_PERFMON5_PERFCOUNTER_STATE 0x0a70
+-#define mmDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX 2
+-#define mmDC_PERFMON5_PERFMON_CNTL 0x0a71
+-#define mmDC_PERFMON5_PERFMON_CNTL_BASE_IDX 2
+-#define mmDC_PERFMON5_PERFMON_CNTL2 0x0a72
+-#define mmDC_PERFMON5_PERFMON_CNTL2_BASE_IDX 2
+-#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x0a73
+-#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+-#define mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x0a74
+-#define mmDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX 2
+-#define mmDC_PERFMON5_PERFMON_HI 0x0a75
+-#define mmDC_PERFMON5_PERFMON_HI_BASE_IDX 2
+-#define mmDC_PERFMON5_PERFMON_LOW 0x0a76
+-#define mmDC_PERFMON5_PERFMON_LOW_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dmif_pg2_dispdec
+-// base address: 0x1000
+-#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 0x0a7a
+-#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
+-#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 0x0a7b
+-#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
+-#define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 0x0a7c
+-#define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2
+-#define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL 0x0a7d
+-#define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2
+-#define mmDMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL 0x0a7e
+-#define mmDMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2
+-#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL 0x0a7f
+-#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2
+-#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL2 0x0a80
+-#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2
+-#define mmDMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL 0x0a81
+-#define mmDMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2
+-#define mmDMIF_PG2_DPG_REPEATER_PROGRAM 0x0a82
+-#define mmDMIF_PG2_DPG_REPEATER_PROGRAM_BASE_IDX 2
+-#define mmDMIF_PG2_DPG_CHK_PRE_PROC_CNTL 0x0a86
+-#define mmDMIF_PG2_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2
+-#define mmDMIF_PG2_DPG_DVMM_STATUS 0x0a87
+-#define mmDMIF_PG2_DPG_DVMM_STATUS_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_scl2_dispdec
+-// base address: 0x1000
+-#define mmSCL2_SCL_COEF_RAM_SELECT 0x0a9a
+-#define mmSCL2_SCL_COEF_RAM_SELECT_BASE_IDX 2
+-#define mmSCL2_SCL_COEF_RAM_TAP_DATA 0x0a9b
+-#define mmSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
+-#define mmSCL2_SCL_MODE 0x0a9c
+-#define mmSCL2_SCL_MODE_BASE_IDX 2
+-#define mmSCL2_SCL_TAP_CONTROL 0x0a9d
+-#define mmSCL2_SCL_TAP_CONTROL_BASE_IDX 2
+-#define mmSCL2_SCL_CONTROL 0x0a9e
+-#define mmSCL2_SCL_CONTROL_BASE_IDX 2
+-#define mmSCL2_SCL_BYPASS_CONTROL 0x0a9f
+-#define mmSCL2_SCL_BYPASS_CONTROL_BASE_IDX 2
+-#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0aa0
+-#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
+-#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL 0x0aa1
+-#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2
+-#define mmSCL2_SCL_HORZ_FILTER_CONTROL 0x0aa2
+-#define mmSCL2_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2
+-#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0aa3
+-#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
+-#define mmSCL2_SCL_HORZ_FILTER_INIT 0x0aa4
+-#define mmSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2
+-#define mmSCL2_SCL_VERT_FILTER_CONTROL 0x0aa5
+-#define mmSCL2_SCL_VERT_FILTER_CONTROL_BASE_IDX 2
+-#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0aa6
+-#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
+-#define mmSCL2_SCL_VERT_FILTER_INIT 0x0aa7
+-#define mmSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2
+-#define mmSCL2_SCL_VERT_FILTER_INIT_BOT 0x0aa8
+-#define mmSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
+-#define mmSCL2_SCL_ROUND_OFFSET 0x0aa9
+-#define mmSCL2_SCL_ROUND_OFFSET_BASE_IDX 2
+-#define mmSCL2_SCL_UPDATE 0x0aaa
+-#define mmSCL2_SCL_UPDATE_BASE_IDX 2
+-#define mmSCL2_SCL_F_SHARP_CONTROL 0x0aab
+-#define mmSCL2_SCL_F_SHARP_CONTROL_BASE_IDX 2
+-#define mmSCL2_SCL_ALU_CONTROL 0x0aac
+-#define mmSCL2_SCL_ALU_CONTROL_BASE_IDX 2
+-#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0x0aad
+-#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
+-#define mmSCL2_VIEWPORT_START_SECONDARY 0x0aae
+-#define mmSCL2_VIEWPORT_START_SECONDARY_BASE_IDX 2
+-#define mmSCL2_VIEWPORT_START 0x0aaf
+-#define mmSCL2_VIEWPORT_START_BASE_IDX 2
+-#define mmSCL2_VIEWPORT_SIZE 0x0ab0
+-#define mmSCL2_VIEWPORT_SIZE_BASE_IDX 2
+-#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT 0x0ab1
+-#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
+-#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM 0x0ab2
+-#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
+-#define mmSCL2_SCL_MODE_CHANGE_DET1 0x0ab3
+-#define mmSCL2_SCL_MODE_CHANGE_DET1_BASE_IDX 2
+-#define mmSCL2_SCL_MODE_CHANGE_DET2 0x0ab4
+-#define mmSCL2_SCL_MODE_CHANGE_DET2_BASE_IDX 2
+-#define mmSCL2_SCL_MODE_CHANGE_DET3 0x0ab5
+-#define mmSCL2_SCL_MODE_CHANGE_DET3_BASE_IDX 2
+-#define mmSCL2_SCL_MODE_CHANGE_MASK 0x0ab6
+-#define mmSCL2_SCL_MODE_CHANGE_MASK_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_blnd2_dispdec
+-// base address: 0x1000
+-#define mmBLND2_BLND_CONTROL 0x0ac7
+-#define mmBLND2_BLND_CONTROL_BASE_IDX 2
+-#define mmBLND2_BLND_SM_CONTROL2 0x0ac8
+-#define mmBLND2_BLND_SM_CONTROL2_BASE_IDX 2
+-#define mmBLND2_BLND_CONTROL2 0x0ac9
+-#define mmBLND2_BLND_CONTROL2_BASE_IDX 2
+-#define mmBLND2_BLND_UPDATE 0x0aca
+-#define mmBLND2_BLND_UPDATE_BASE_IDX 2
+-#define mmBLND2_BLND_UNDERFLOW_INTERRUPT 0x0acb
+-#define mmBLND2_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2
+-#define mmBLND2_BLND_V_UPDATE_LOCK 0x0acc
+-#define mmBLND2_BLND_V_UPDATE_LOCK_BASE_IDX 2
+-#define mmBLND2_BLND_REG_UPDATE_STATUS 0x0acd
+-#define mmBLND2_BLND_REG_UPDATE_STATUS_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_crtc2_dispdec
+-// base address: 0x1000
+-#define mmCRTC2_CRTC_H_BLANK_EARLY_NUM 0x0ad2
+-#define mmCRTC2_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2
+-#define mmCRTC2_CRTC_H_TOTAL 0x0ad3
+-#define mmCRTC2_CRTC_H_TOTAL_BASE_IDX 2
+-#define mmCRTC2_CRTC_H_BLANK_START_END 0x0ad4
+-#define mmCRTC2_CRTC_H_BLANK_START_END_BASE_IDX 2
+-#define mmCRTC2_CRTC_H_SYNC_A 0x0ad5
+-#define mmCRTC2_CRTC_H_SYNC_A_BASE_IDX 2
+-#define mmCRTC2_CRTC_H_SYNC_A_CNTL 0x0ad6
+-#define mmCRTC2_CRTC_H_SYNC_A_CNTL_BASE_IDX 2
+-#define mmCRTC2_CRTC_H_SYNC_B 0x0ad7
+-#define mmCRTC2_CRTC_H_SYNC_B_BASE_IDX 2
+-#define mmCRTC2_CRTC_H_SYNC_B_CNTL 0x0ad8
+-#define mmCRTC2_CRTC_H_SYNC_B_CNTL_BASE_IDX 2
+-#define mmCRTC2_CRTC_VBI_END 0x0ad9
+-#define mmCRTC2_CRTC_VBI_END_BASE_IDX 2
+-#define mmCRTC2_CRTC_V_TOTAL 0x0ada
+-#define mmCRTC2_CRTC_V_TOTAL_BASE_IDX 2
+-#define mmCRTC2_CRTC_V_TOTAL_MIN 0x0adb
+-#define mmCRTC2_CRTC_V_TOTAL_MIN_BASE_IDX 2
+-#define mmCRTC2_CRTC_V_TOTAL_MAX 0x0adc
+-#define mmCRTC2_CRTC_V_TOTAL_MAX_BASE_IDX 2
+-#define mmCRTC2_CRTC_V_TOTAL_CONTROL 0x0add
+-#define mmCRTC2_CRTC_V_TOTAL_CONTROL_BASE_IDX 2
+-#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS 0x0ade
+-#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2
+-#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS 0x0adf
+-#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2
+-#define mmCRTC2_CRTC_V_BLANK_START_END 0x0ae0
+-#define mmCRTC2_CRTC_V_BLANK_START_END_BASE_IDX 2
+-#define mmCRTC2_CRTC_V_SYNC_A 0x0ae1
+-#define mmCRTC2_CRTC_V_SYNC_A_BASE_IDX 2
+-#define mmCRTC2_CRTC_V_SYNC_A_CNTL 0x0ae2
+-#define mmCRTC2_CRTC_V_SYNC_A_CNTL_BASE_IDX 2
+-#define mmCRTC2_CRTC_V_SYNC_B 0x0ae3
+-#define mmCRTC2_CRTC_V_SYNC_B_BASE_IDX 2
+-#define mmCRTC2_CRTC_V_SYNC_B_CNTL 0x0ae4
+-#define mmCRTC2_CRTC_V_SYNC_B_CNTL_BASE_IDX 2
+-#define mmCRTC2_CRTC_DTMTEST_CNTL 0x0ae5
+-#define mmCRTC2_CRTC_DTMTEST_CNTL_BASE_IDX 2
+-#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION 0x0ae6
+-#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2
+-#define mmCRTC2_CRTC_TRIGA_CNTL 0x0ae7
+-#define mmCRTC2_CRTC_TRIGA_CNTL_BASE_IDX 2
+-#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG 0x0ae8
+-#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2
+-#define mmCRTC2_CRTC_TRIGB_CNTL 0x0ae9
+-#define mmCRTC2_CRTC_TRIGB_CNTL_BASE_IDX 2
+-#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG 0x0aea
+-#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2
+-#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL 0x0aeb
+-#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
+-#define mmCRTC2_CRTC_FLOW_CONTROL 0x0aec
+-#define mmCRTC2_CRTC_FLOW_CONTROL_BASE_IDX 2
+-#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE 0x0aed
+-#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
+-#define mmCRTC2_CRTC_AVSYNC_COUNTER 0x0aee
+-#define mmCRTC2_CRTC_AVSYNC_COUNTER_BASE_IDX 2
+-#define mmCRTC2_CRTC_CONTROL 0x0aef
+-#define mmCRTC2_CRTC_CONTROL_BASE_IDX 2
+-#define mmCRTC2_CRTC_BLANK_CONTROL 0x0af0
+-#define mmCRTC2_CRTC_BLANK_CONTROL_BASE_IDX 2
+-#define mmCRTC2_CRTC_INTERLACE_CONTROL 0x0af1
+-#define mmCRTC2_CRTC_INTERLACE_CONTROL_BASE_IDX 2
+-#define mmCRTC2_CRTC_INTERLACE_STATUS 0x0af2
+-#define mmCRTC2_CRTC_INTERLACE_STATUS_BASE_IDX 2
+-#define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL 0x0af3
+-#define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2
+-#define mmCRTC2_CRTC_PIXEL_DATA_READBACK0 0x0af4
+-#define mmCRTC2_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2
+-#define mmCRTC2_CRTC_PIXEL_DATA_READBACK1 0x0af5
+-#define mmCRTC2_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2
+-#define mmCRTC2_CRTC_STATUS 0x0af6
+-#define mmCRTC2_CRTC_STATUS_BASE_IDX 2
+-#define mmCRTC2_CRTC_STATUS_POSITION 0x0af7
+-#define mmCRTC2_CRTC_STATUS_POSITION_BASE_IDX 2
+-#define mmCRTC2_CRTC_NOM_VERT_POSITION 0x0af8
+-#define mmCRTC2_CRTC_NOM_VERT_POSITION_BASE_IDX 2
+-#define mmCRTC2_CRTC_STATUS_FRAME_COUNT 0x0af9
+-#define mmCRTC2_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2
+-#define mmCRTC2_CRTC_STATUS_VF_COUNT 0x0afa
+-#define mmCRTC2_CRTC_STATUS_VF_COUNT_BASE_IDX 2
+-#define mmCRTC2_CRTC_STATUS_HV_COUNT 0x0afb
+-#define mmCRTC2_CRTC_STATUS_HV_COUNT_BASE_IDX 2
+-#define mmCRTC2_CRTC_COUNT_CONTROL 0x0afc
+-#define mmCRTC2_CRTC_COUNT_CONTROL_BASE_IDX 2
+-#define mmCRTC2_CRTC_COUNT_RESET 0x0afd
+-#define mmCRTC2_CRTC_COUNT_RESET_BASE_IDX 2
+-#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x0afe
+-#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
+-#define mmCRTC2_CRTC_VERT_SYNC_CONTROL 0x0aff
+-#define mmCRTC2_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2
+-#define mmCRTC2_CRTC_STEREO_STATUS 0x0b00
+-#define mmCRTC2_CRTC_STEREO_STATUS_BASE_IDX 2
+-#define mmCRTC2_CRTC_STEREO_CONTROL 0x0b01
+-#define mmCRTC2_CRTC_STEREO_CONTROL_BASE_IDX 2
+-#define mmCRTC2_CRTC_SNAPSHOT_STATUS 0x0b02
+-#define mmCRTC2_CRTC_SNAPSHOT_STATUS_BASE_IDX 2
+-#define mmCRTC2_CRTC_SNAPSHOT_CONTROL 0x0b03
+-#define mmCRTC2_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2
+-#define mmCRTC2_CRTC_SNAPSHOT_POSITION 0x0b04
+-#define mmCRTC2_CRTC_SNAPSHOT_POSITION_BASE_IDX 2
+-#define mmCRTC2_CRTC_SNAPSHOT_FRAME 0x0b05
+-#define mmCRTC2_CRTC_SNAPSHOT_FRAME_BASE_IDX 2
+-#define mmCRTC2_CRTC_START_LINE_CONTROL 0x0b06
+-#define mmCRTC2_CRTC_START_LINE_CONTROL_BASE_IDX 2
+-#define mmCRTC2_CRTC_INTERRUPT_CONTROL 0x0b07
+-#define mmCRTC2_CRTC_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmCRTC2_CRTC_UPDATE_LOCK 0x0b08
+-#define mmCRTC2_CRTC_UPDATE_LOCK_BASE_IDX 2
+-#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL 0x0b09
+-#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
+-#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x0b0a
+-#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2
+-#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL 0x0b0b
+-#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2
+-#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS 0x0b0c
+-#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2
+-#define mmCRTC2_CRTC_TEST_PATTERN_COLOR 0x0b0d
+-#define mmCRTC2_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2
+-#define mmCRTC2_CRTC_MASTER_UPDATE_LOCK 0x0b0e
+-#define mmCRTC2_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2
+-#define mmCRTC2_CRTC_MASTER_UPDATE_MODE 0x0b0f
+-#define mmCRTC2_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2
+-#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT 0x0b10
+-#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2
+-#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x0b11
+-#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2
+-#define mmCRTC2_CRTC_MVP_STATUS 0x0b12
+-#define mmCRTC2_CRTC_MVP_STATUS_BASE_IDX 2
+-#define mmCRTC2_CRTC_MASTER_EN 0x0b13
+-#define mmCRTC2_CRTC_MASTER_EN_BASE_IDX 2
+-#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT 0x0b14
+-#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2
+-#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS 0x0b15
+-#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2
+-#define mmCRTC2_CRTC_OVERSCAN_COLOR 0x0b17
+-#define mmCRTC2_CRTC_OVERSCAN_COLOR_BASE_IDX 2
+-#define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT 0x0b18
+-#define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2
+-#define mmCRTC2_CRTC_BLANK_DATA_COLOR 0x0b19
+-#define mmCRTC2_CRTC_BLANK_DATA_COLOR_BASE_IDX 2
+-#define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT 0x0b1a
+-#define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2
+-#define mmCRTC2_CRTC_BLACK_COLOR 0x0b1b
+-#define mmCRTC2_CRTC_BLACK_COLOR_BASE_IDX 2
+-#define mmCRTC2_CRTC_BLACK_COLOR_EXT 0x0b1c
+-#define mmCRTC2_CRTC_BLACK_COLOR_EXT_BASE_IDX 2
+-#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION 0x0b1d
+-#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
+-#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x0b1e
+-#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
+-#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION 0x0b1f
+-#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
+-#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x0b20
+-#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
+-#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION 0x0b21
+-#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
+-#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x0b22
+-#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
+-#define mmCRTC2_CRTC_CRC_CNTL 0x0b23
+-#define mmCRTC2_CRTC_CRC_CNTL_BASE_IDX 2
+-#define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL 0x0b24
+-#define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
+-#define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL 0x0b25
+-#define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
+-#define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL 0x0b26
+-#define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
+-#define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL 0x0b27
+-#define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
+-#define mmCRTC2_CRTC_CRC0_DATA_RG 0x0b28
+-#define mmCRTC2_CRTC_CRC0_DATA_RG_BASE_IDX 2
+-#define mmCRTC2_CRTC_CRC0_DATA_B 0x0b29
+-#define mmCRTC2_CRTC_CRC0_DATA_B_BASE_IDX 2
+-#define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL 0x0b2a
+-#define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
+-#define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL 0x0b2b
+-#define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
+-#define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL 0x0b2c
+-#define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
+-#define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL 0x0b2d
+-#define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
+-#define mmCRTC2_CRTC_CRC1_DATA_RG 0x0b2e
+-#define mmCRTC2_CRTC_CRC1_DATA_RG_BASE_IDX 2
+-#define mmCRTC2_CRTC_CRC1_DATA_B 0x0b2f
+-#define mmCRTC2_CRTC_CRC1_DATA_B_BASE_IDX 2
+-#define mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL 0x0b30
+-#define mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2
+-#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x0b31
+-#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2
+-#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x0b32
+-#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2
+-#define mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x0b33
+-#define mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x0b34
+-#define mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x0b35
+-#define mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL 0x0b36
+-#define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2
+-#define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL 0x0b37
+-#define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2
+-#define mmCRTC2_CRTC_GSL_VSYNC_GAP 0x0b38
+-#define mmCRTC2_CRTC_GSL_VSYNC_GAP_BASE_IDX 2
+-#define mmCRTC2_CRTC_GSL_WINDOW 0x0b39
+-#define mmCRTC2_CRTC_GSL_WINDOW_BASE_IDX 2
+-#define mmCRTC2_CRTC_GSL_CONTROL 0x0b3a
+-#define mmCRTC2_CRTC_GSL_CONTROL_BASE_IDX 2
+-#define mmCRTC2_CRTC_RANGE_TIMING_INT_STATUS 0x0b3d
+-#define mmCRTC2_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2
+-#define mmCRTC2_CRTC_DRR_CONTROL 0x0b3e
+-#define mmCRTC2_CRTC_DRR_CONTROL_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_fmt2_dispdec
+-// base address: 0x1000
+-#define mmFMT2_FMT_CLAMP_COMPONENT_R 0x0b42
+-#define mmFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
+-#define mmFMT2_FMT_CLAMP_COMPONENT_G 0x0b43
+-#define mmFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
+-#define mmFMT2_FMT_CLAMP_COMPONENT_B 0x0b44
+-#define mmFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
+-#define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x0b45
+-#define mmFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
+-#define mmFMT2_FMT_CONTROL 0x0b46
+-#define mmFMT2_FMT_CONTROL_BASE_IDX 2
+-#define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x0b47
+-#define mmFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
+-#define mmFMT2_FMT_DITHER_RAND_R_SEED 0x0b48
+-#define mmFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
+-#define mmFMT2_FMT_DITHER_RAND_G_SEED 0x0b49
+-#define mmFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
+-#define mmFMT2_FMT_DITHER_RAND_B_SEED 0x0b4a
+-#define mmFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
+-#define mmFMT2_FMT_CLAMP_CNTL 0x0b4e
+-#define mmFMT2_FMT_CLAMP_CNTL_BASE_IDX 2
+-#define mmFMT2_FMT_CRC_CNTL 0x0b4f
+-#define mmFMT2_FMT_CRC_CNTL_BASE_IDX 2
+-#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK 0x0b50
+-#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
+-#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x0b51
+-#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
+-#define mmFMT2_FMT_CRC_SIG_RED_GREEN 0x0b52
+-#define mmFMT2_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2
+-#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL 0x0b53
+-#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2
+-#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x0b54
+-#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
+-#define mmFMT2_FMT_420_HBLANK_EARLY_START 0x0b55
+-#define mmFMT2_FMT_420_HBLANK_EARLY_START_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dcp3_dispdec
+-// base address: 0x1800
+-#define mmDCP3_GRPH_ENABLE 0x0b5a
+-#define mmDCP3_GRPH_ENABLE_BASE_IDX 2
+-#define mmDCP3_GRPH_CONTROL 0x0b5b
+-#define mmDCP3_GRPH_CONTROL_BASE_IDX 2
+-#define mmDCP3_GRPH_LUT_10BIT_BYPASS 0x0b5c
+-#define mmDCP3_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2
+-#define mmDCP3_GRPH_SWAP_CNTL 0x0b5d
+-#define mmDCP3_GRPH_SWAP_CNTL_BASE_IDX 2
+-#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS 0x0b5e
+-#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
+-#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS 0x0b5f
+-#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
+-#define mmDCP3_GRPH_PITCH 0x0b60
+-#define mmDCP3_GRPH_PITCH_BASE_IDX 2
+-#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0b61
+-#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+-#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0b62
+-#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+-#define mmDCP3_GRPH_SURFACE_OFFSET_X 0x0b63
+-#define mmDCP3_GRPH_SURFACE_OFFSET_X_BASE_IDX 2
+-#define mmDCP3_GRPH_SURFACE_OFFSET_Y 0x0b64
+-#define mmDCP3_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2
+-#define mmDCP3_GRPH_X_START 0x0b65
+-#define mmDCP3_GRPH_X_START_BASE_IDX 2
+-#define mmDCP3_GRPH_Y_START 0x0b66
+-#define mmDCP3_GRPH_Y_START_BASE_IDX 2
+-#define mmDCP3_GRPH_X_END 0x0b67
+-#define mmDCP3_GRPH_X_END_BASE_IDX 2
+-#define mmDCP3_GRPH_Y_END 0x0b68
+-#define mmDCP3_GRPH_Y_END_BASE_IDX 2
+-#define mmDCP3_INPUT_GAMMA_CONTROL 0x0b69
+-#define mmDCP3_INPUT_GAMMA_CONTROL_BASE_IDX 2
+-#define mmDCP3_GRPH_UPDATE 0x0b6a
+-#define mmDCP3_GRPH_UPDATE_BASE_IDX 2
+-#define mmDCP3_GRPH_FLIP_CONTROL 0x0b6b
+-#define mmDCP3_GRPH_FLIP_CONTROL_BASE_IDX 2
+-#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE 0x0b6c
+-#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2
+-#define mmDCP3_GRPH_DFQ_CONTROL 0x0b6d
+-#define mmDCP3_GRPH_DFQ_CONTROL_BASE_IDX 2
+-#define mmDCP3_GRPH_DFQ_STATUS 0x0b6e
+-#define mmDCP3_GRPH_DFQ_STATUS_BASE_IDX 2
+-#define mmDCP3_GRPH_INTERRUPT_STATUS 0x0b6f
+-#define mmDCP3_GRPH_INTERRUPT_STATUS_BASE_IDX 2
+-#define mmDCP3_GRPH_INTERRUPT_CONTROL 0x0b70
+-#define mmDCP3_GRPH_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0b71
+-#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2
+-#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS 0x0b72
+-#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2
+-#define mmDCP3_GRPH_COMPRESS_PITCH 0x0b73
+-#define mmDCP3_GRPH_COMPRESS_PITCH_BASE_IDX 2
+-#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0b74
+-#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+-#define mmDCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0b75
+-#define mmDCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2
+-#define mmDCP3_PRESCALE_GRPH_CONTROL 0x0b76
+-#define mmDCP3_PRESCALE_GRPH_CONTROL_BASE_IDX 2
+-#define mmDCP3_PRESCALE_VALUES_GRPH_R 0x0b77
+-#define mmDCP3_PRESCALE_VALUES_GRPH_R_BASE_IDX 2
+-#define mmDCP3_PRESCALE_VALUES_GRPH_G 0x0b78
+-#define mmDCP3_PRESCALE_VALUES_GRPH_G_BASE_IDX 2
+-#define mmDCP3_PRESCALE_VALUES_GRPH_B 0x0b79
+-#define mmDCP3_PRESCALE_VALUES_GRPH_B_BASE_IDX 2
+-#define mmDCP3_INPUT_CSC_CONTROL 0x0b7a
+-#define mmDCP3_INPUT_CSC_CONTROL_BASE_IDX 2
+-#define mmDCP3_INPUT_CSC_C11_C12 0x0b7b
+-#define mmDCP3_INPUT_CSC_C11_C12_BASE_IDX 2
+-#define mmDCP3_INPUT_CSC_C13_C14 0x0b7c
+-#define mmDCP3_INPUT_CSC_C13_C14_BASE_IDX 2
+-#define mmDCP3_INPUT_CSC_C21_C22 0x0b7d
+-#define mmDCP3_INPUT_CSC_C21_C22_BASE_IDX 2
+-#define mmDCP3_INPUT_CSC_C23_C24 0x0b7e
+-#define mmDCP3_INPUT_CSC_C23_C24_BASE_IDX 2
+-#define mmDCP3_INPUT_CSC_C31_C32 0x0b7f
+-#define mmDCP3_INPUT_CSC_C31_C32_BASE_IDX 2
+-#define mmDCP3_INPUT_CSC_C33_C34 0x0b80
+-#define mmDCP3_INPUT_CSC_C33_C34_BASE_IDX 2
+-#define mmDCP3_OUTPUT_CSC_CONTROL 0x0b81
+-#define mmDCP3_OUTPUT_CSC_CONTROL_BASE_IDX 2
+-#define mmDCP3_OUTPUT_CSC_C11_C12 0x0b82
+-#define mmDCP3_OUTPUT_CSC_C11_C12_BASE_IDX 2
+-#define mmDCP3_OUTPUT_CSC_C13_C14 0x0b83
+-#define mmDCP3_OUTPUT_CSC_C13_C14_BASE_IDX 2
+-#define mmDCP3_OUTPUT_CSC_C21_C22 0x0b84
+-#define mmDCP3_OUTPUT_CSC_C21_C22_BASE_IDX 2
+-#define mmDCP3_OUTPUT_CSC_C23_C24 0x0b85
+-#define mmDCP3_OUTPUT_CSC_C23_C24_BASE_IDX 2
+-#define mmDCP3_OUTPUT_CSC_C31_C32 0x0b86
+-#define mmDCP3_OUTPUT_CSC_C31_C32_BASE_IDX 2
+-#define mmDCP3_OUTPUT_CSC_C33_C34 0x0b87
+-#define mmDCP3_OUTPUT_CSC_C33_C34_BASE_IDX 2
+-#define mmDCP3_COMM_MATRIXA_TRANS_C11_C12 0x0b88
+-#define mmDCP3_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2
+-#define mmDCP3_COMM_MATRIXA_TRANS_C13_C14 0x0b89
+-#define mmDCP3_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2
+-#define mmDCP3_COMM_MATRIXA_TRANS_C21_C22 0x0b8a
+-#define mmDCP3_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2
+-#define mmDCP3_COMM_MATRIXA_TRANS_C23_C24 0x0b8b
+-#define mmDCP3_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2
+-#define mmDCP3_COMM_MATRIXA_TRANS_C31_C32 0x0b8c
+-#define mmDCP3_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2
+-#define mmDCP3_COMM_MATRIXA_TRANS_C33_C34 0x0b8d
+-#define mmDCP3_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2
+-#define mmDCP3_COMM_MATRIXB_TRANS_C11_C12 0x0b8e
+-#define mmDCP3_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2
+-#define mmDCP3_COMM_MATRIXB_TRANS_C13_C14 0x0b8f
+-#define mmDCP3_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2
+-#define mmDCP3_COMM_MATRIXB_TRANS_C21_C22 0x0b90
+-#define mmDCP3_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2
+-#define mmDCP3_COMM_MATRIXB_TRANS_C23_C24 0x0b91
+-#define mmDCP3_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2
+-#define mmDCP3_COMM_MATRIXB_TRANS_C31_C32 0x0b92
+-#define mmDCP3_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2
+-#define mmDCP3_COMM_MATRIXB_TRANS_C33_C34 0x0b93
+-#define mmDCP3_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2
+-#define mmDCP3_DENORM_CONTROL 0x0b94
+-#define mmDCP3_DENORM_CONTROL_BASE_IDX 2
+-#define mmDCP3_OUT_ROUND_CONTROL 0x0b95
+-#define mmDCP3_OUT_ROUND_CONTROL_BASE_IDX 2
+-#define mmDCP3_OUT_CLAMP_CONTROL_R_CR 0x0b96
+-#define mmDCP3_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2
+-#define mmDCP3_OUT_CLAMP_CONTROL_G_Y 0x0b97
+-#define mmDCP3_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2
+-#define mmDCP3_OUT_CLAMP_CONTROL_B_CB 0x0b98
+-#define mmDCP3_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2
+-#define mmDCP3_KEY_CONTROL 0x0b99
+-#define mmDCP3_KEY_CONTROL_BASE_IDX 2
+-#define mmDCP3_KEY_RANGE_ALPHA 0x0b9a
+-#define mmDCP3_KEY_RANGE_ALPHA_BASE_IDX 2
+-#define mmDCP3_KEY_RANGE_RED 0x0b9b
+-#define mmDCP3_KEY_RANGE_RED_BASE_IDX 2
+-#define mmDCP3_KEY_RANGE_GREEN 0x0b9c
+-#define mmDCP3_KEY_RANGE_GREEN_BASE_IDX 2
+-#define mmDCP3_KEY_RANGE_BLUE 0x0b9d
+-#define mmDCP3_KEY_RANGE_BLUE_BASE_IDX 2
+-#define mmDCP3_DEGAMMA_CONTROL 0x0b9e
+-#define mmDCP3_DEGAMMA_CONTROL_BASE_IDX 2
+-#define mmDCP3_GAMUT_REMAP_CONTROL 0x0b9f
+-#define mmDCP3_GAMUT_REMAP_CONTROL_BASE_IDX 2
+-#define mmDCP3_GAMUT_REMAP_C11_C12 0x0ba0
+-#define mmDCP3_GAMUT_REMAP_C11_C12_BASE_IDX 2
+-#define mmDCP3_GAMUT_REMAP_C13_C14 0x0ba1
+-#define mmDCP3_GAMUT_REMAP_C13_C14_BASE_IDX 2
+-#define mmDCP3_GAMUT_REMAP_C21_C22 0x0ba2
+-#define mmDCP3_GAMUT_REMAP_C21_C22_BASE_IDX 2
+-#define mmDCP3_GAMUT_REMAP_C23_C24 0x0ba3
+-#define mmDCP3_GAMUT_REMAP_C23_C24_BASE_IDX 2
+-#define mmDCP3_GAMUT_REMAP_C31_C32 0x0ba4
+-#define mmDCP3_GAMUT_REMAP_C31_C32_BASE_IDX 2
+-#define mmDCP3_GAMUT_REMAP_C33_C34 0x0ba5
+-#define mmDCP3_GAMUT_REMAP_C33_C34_BASE_IDX 2
+-#define mmDCP3_DCP_SPATIAL_DITHER_CNTL 0x0ba6
+-#define mmDCP3_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2
+-#define mmDCP3_DCP_RANDOM_SEEDS 0x0ba7
+-#define mmDCP3_DCP_RANDOM_SEEDS_BASE_IDX 2
+-#define mmDCP3_DCP_FP_CONVERTED_FIELD 0x0ba8
+-#define mmDCP3_DCP_FP_CONVERTED_FIELD_BASE_IDX 2
+-#define mmDCP3_CUR_CONTROL 0x0ba9
+-#define mmDCP3_CUR_CONTROL_BASE_IDX 2
+-#define mmDCP3_CUR_SURFACE_ADDRESS 0x0baa
+-#define mmDCP3_CUR_SURFACE_ADDRESS_BASE_IDX 2
+-#define mmDCP3_CUR_SIZE 0x0bab
+-#define mmDCP3_CUR_SIZE_BASE_IDX 2
+-#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH 0x0bac
+-#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+-#define mmDCP3_CUR_POSITION 0x0bad
+-#define mmDCP3_CUR_POSITION_BASE_IDX 2
+-#define mmDCP3_CUR_HOT_SPOT 0x0bae
+-#define mmDCP3_CUR_HOT_SPOT_BASE_IDX 2
+-#define mmDCP3_CUR_COLOR1 0x0baf
+-#define mmDCP3_CUR_COLOR1_BASE_IDX 2
+-#define mmDCP3_CUR_COLOR2 0x0bb0
+-#define mmDCP3_CUR_COLOR2_BASE_IDX 2
+-#define mmDCP3_CUR_UPDATE 0x0bb1
+-#define mmDCP3_CUR_UPDATE_BASE_IDX 2
+-#define mmDCP3_CUR_REQUEST_FILTER_CNTL 0x0bbb
+-#define mmDCP3_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2
+-#define mmDCP3_CUR_STEREO_CONTROL 0x0bbc
+-#define mmDCP3_CUR_STEREO_CONTROL_BASE_IDX 2
+-#define mmDCP3_DC_LUT_RW_MODE 0x0bbe
+-#define mmDCP3_DC_LUT_RW_MODE_BASE_IDX 2
+-#define mmDCP3_DC_LUT_RW_INDEX 0x0bbf
+-#define mmDCP3_DC_LUT_RW_INDEX_BASE_IDX 2
+-#define mmDCP3_DC_LUT_SEQ_COLOR 0x0bc0
+-#define mmDCP3_DC_LUT_SEQ_COLOR_BASE_IDX 2
+-#define mmDCP3_DC_LUT_PWL_DATA 0x0bc1
+-#define mmDCP3_DC_LUT_PWL_DATA_BASE_IDX 2
+-#define mmDCP3_DC_LUT_30_COLOR 0x0bc2
+-#define mmDCP3_DC_LUT_30_COLOR_BASE_IDX 2
+-#define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE 0x0bc3
+-#define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2
+-#define mmDCP3_DC_LUT_WRITE_EN_MASK 0x0bc4
+-#define mmDCP3_DC_LUT_WRITE_EN_MASK_BASE_IDX 2
+-#define mmDCP3_DC_LUT_AUTOFILL 0x0bc5
+-#define mmDCP3_DC_LUT_AUTOFILL_BASE_IDX 2
+-#define mmDCP3_DC_LUT_CONTROL 0x0bc6
+-#define mmDCP3_DC_LUT_CONTROL_BASE_IDX 2
+-#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE 0x0bc7
+-#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2
+-#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN 0x0bc8
+-#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2
+-#define mmDCP3_DC_LUT_BLACK_OFFSET_RED 0x0bc9
+-#define mmDCP3_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2
+-#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE 0x0bca
+-#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2
+-#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN 0x0bcb
+-#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2
+-#define mmDCP3_DC_LUT_WHITE_OFFSET_RED 0x0bcc
+-#define mmDCP3_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2
+-#define mmDCP3_DCP_CRC_CONTROL 0x0bcd
+-#define mmDCP3_DCP_CRC_CONTROL_BASE_IDX 2
+-#define mmDCP3_DCP_CRC_MASK 0x0bce
+-#define mmDCP3_DCP_CRC_MASK_BASE_IDX 2
+-#define mmDCP3_DCP_CRC_CURRENT 0x0bcf
+-#define mmDCP3_DCP_CRC_CURRENT_BASE_IDX 2
+-#define mmDCP3_DVMM_PTE_CONTROL 0x0bd0
+-#define mmDCP3_DVMM_PTE_CONTROL_BASE_IDX 2
+-#define mmDCP3_DCP_CRC_LAST 0x0bd1
+-#define mmDCP3_DCP_CRC_LAST_BASE_IDX 2
+-#define mmDCP3_DVMM_PTE_ARB_CONTROL 0x0bd2
+-#define mmDCP3_DVMM_PTE_ARB_CONTROL_BASE_IDX 2
+-#define mmDCP3_GRPH_FLIP_RATE_CNTL 0x0bd4
+-#define mmDCP3_GRPH_FLIP_RATE_CNTL_BASE_IDX 2
+-#define mmDCP3_DCP_GSL_CONTROL 0x0bd5
+-#define mmDCP3_DCP_GSL_CONTROL_BASE_IDX 2
+-#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x0bd6
+-#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2
+-#define mmDCP3_GRPH_STEREOSYNC_FLIP 0x0bdc
+-#define mmDCP3_GRPH_STEREOSYNC_FLIP_BASE_IDX 2
+-#define mmDCP3_HW_ROTATION 0x0bde
+-#define mmDCP3_HW_ROTATION_BASE_IDX 2
+-#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x0bdf
+-#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2
+-#define mmDCP3_REGAMMA_CONTROL 0x0be0
+-#define mmDCP3_REGAMMA_CONTROL_BASE_IDX 2
+-#define mmDCP3_REGAMMA_LUT_INDEX 0x0be1
+-#define mmDCP3_REGAMMA_LUT_INDEX_BASE_IDX 2
+-#define mmDCP3_REGAMMA_LUT_DATA 0x0be2
+-#define mmDCP3_REGAMMA_LUT_DATA_BASE_IDX 2
+-#define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK 0x0be3
+-#define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2
+-#define mmDCP3_REGAMMA_CNTLA_START_CNTL 0x0be4
+-#define mmDCP3_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2
+-#define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL 0x0be5
+-#define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2
+-#define mmDCP3_REGAMMA_CNTLA_END_CNTL1 0x0be6
+-#define mmDCP3_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2
+-#define mmDCP3_REGAMMA_CNTLA_END_CNTL2 0x0be7
+-#define mmDCP3_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2
+-#define mmDCP3_REGAMMA_CNTLA_REGION_0_1 0x0be8
+-#define mmDCP3_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2
+-#define mmDCP3_REGAMMA_CNTLA_REGION_2_3 0x0be9
+-#define mmDCP3_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2
+-#define mmDCP3_REGAMMA_CNTLA_REGION_4_5 0x0bea
+-#define mmDCP3_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2
+-#define mmDCP3_REGAMMA_CNTLA_REGION_6_7 0x0beb
+-#define mmDCP3_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2
+-#define mmDCP3_REGAMMA_CNTLA_REGION_8_9 0x0bec
+-#define mmDCP3_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2
+-#define mmDCP3_REGAMMA_CNTLA_REGION_10_11 0x0bed
+-#define mmDCP3_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2
+-#define mmDCP3_REGAMMA_CNTLA_REGION_12_13 0x0bee
+-#define mmDCP3_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2
+-#define mmDCP3_REGAMMA_CNTLA_REGION_14_15 0x0bef
+-#define mmDCP3_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2
+-#define mmDCP3_REGAMMA_CNTLB_START_CNTL 0x0bf0
+-#define mmDCP3_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2
+-#define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL 0x0bf1
+-#define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2
+-#define mmDCP3_REGAMMA_CNTLB_END_CNTL1 0x0bf2
+-#define mmDCP3_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2
+-#define mmDCP3_REGAMMA_CNTLB_END_CNTL2 0x0bf3
+-#define mmDCP3_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2
+-#define mmDCP3_REGAMMA_CNTLB_REGION_0_1 0x0bf4
+-#define mmDCP3_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2
+-#define mmDCP3_REGAMMA_CNTLB_REGION_2_3 0x0bf5
+-#define mmDCP3_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2
+-#define mmDCP3_REGAMMA_CNTLB_REGION_4_5 0x0bf6
+-#define mmDCP3_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2
+-#define mmDCP3_REGAMMA_CNTLB_REGION_6_7 0x0bf7
+-#define mmDCP3_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2
+-#define mmDCP3_REGAMMA_CNTLB_REGION_8_9 0x0bf8
+-#define mmDCP3_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2
+-#define mmDCP3_REGAMMA_CNTLB_REGION_10_11 0x0bf9
+-#define mmDCP3_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2
+-#define mmDCP3_REGAMMA_CNTLB_REGION_12_13 0x0bfa
+-#define mmDCP3_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2
+-#define mmDCP3_REGAMMA_CNTLB_REGION_14_15 0x0bfb
+-#define mmDCP3_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2
+-#define mmDCP3_ALPHA_CONTROL 0x0bfc
+-#define mmDCP3_ALPHA_CONTROL_BASE_IDX 2
+-#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x0bfd
+-#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2
+-#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x0bfe
+-#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+-#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x0bff
+-#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2
+-#define mmDCP3_GRPH_XDMA_FLIP_TIMEOUT 0x0c00
+-#define mmDCP3_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2
+-#define mmDCP3_GRPH_XDMA_FLIP_AVG_DELAY 0x0c01
+-#define mmDCP3_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2
+-#define mmDCP3_GRPH_SURFACE_COUNTER_CONTROL 0x0c02
+-#define mmDCP3_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2
+-#define mmDCP3_GRPH_SURFACE_COUNTER_OUTPUT 0x0c03
+-#define mmDCP3_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_lb3_dispdec
+-// base address: 0x1800
+-#define mmLB3_LB_DATA_FORMAT 0x0c1a
+-#define mmLB3_LB_DATA_FORMAT_BASE_IDX 2
+-#define mmLB3_LB_MEMORY_CTRL 0x0c1b
+-#define mmLB3_LB_MEMORY_CTRL_BASE_IDX 2
+-#define mmLB3_LB_MEMORY_SIZE_STATUS 0x0c1c
+-#define mmLB3_LB_MEMORY_SIZE_STATUS_BASE_IDX 2
+-#define mmLB3_LB_DESKTOP_HEIGHT 0x0c1d
+-#define mmLB3_LB_DESKTOP_HEIGHT_BASE_IDX 2
+-#define mmLB3_LB_VLINE_START_END 0x0c1e
+-#define mmLB3_LB_VLINE_START_END_BASE_IDX 2
+-#define mmLB3_LB_VLINE2_START_END 0x0c1f
+-#define mmLB3_LB_VLINE2_START_END_BASE_IDX 2
+-#define mmLB3_LB_V_COUNTER 0x0c20
+-#define mmLB3_LB_V_COUNTER_BASE_IDX 2
+-#define mmLB3_LB_SNAPSHOT_V_COUNTER 0x0c21
+-#define mmLB3_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2
+-#define mmLB3_LB_INTERRUPT_MASK 0x0c22
+-#define mmLB3_LB_INTERRUPT_MASK_BASE_IDX 2
+-#define mmLB3_LB_VLINE_STATUS 0x0c23
+-#define mmLB3_LB_VLINE_STATUS_BASE_IDX 2
+-#define mmLB3_LB_VLINE2_STATUS 0x0c24
+-#define mmLB3_LB_VLINE2_STATUS_BASE_IDX 2
+-#define mmLB3_LB_VBLANK_STATUS 0x0c25
+-#define mmLB3_LB_VBLANK_STATUS_BASE_IDX 2
+-#define mmLB3_LB_SYNC_RESET_SEL 0x0c26
+-#define mmLB3_LB_SYNC_RESET_SEL_BASE_IDX 2
+-#define mmLB3_LB_BLACK_KEYER_R_CR 0x0c27
+-#define mmLB3_LB_BLACK_KEYER_R_CR_BASE_IDX 2
+-#define mmLB3_LB_BLACK_KEYER_G_Y 0x0c28
+-#define mmLB3_LB_BLACK_KEYER_G_Y_BASE_IDX 2
+-#define mmLB3_LB_BLACK_KEYER_B_CB 0x0c29
+-#define mmLB3_LB_BLACK_KEYER_B_CB_BASE_IDX 2
+-#define mmLB3_LB_KEYER_COLOR_CTRL 0x0c2a
+-#define mmLB3_LB_KEYER_COLOR_CTRL_BASE_IDX 2
+-#define mmLB3_LB_KEYER_COLOR_R_CR 0x0c2b
+-#define mmLB3_LB_KEYER_COLOR_R_CR_BASE_IDX 2
+-#define mmLB3_LB_KEYER_COLOR_G_Y 0x0c2c
+-#define mmLB3_LB_KEYER_COLOR_G_Y_BASE_IDX 2
+-#define mmLB3_LB_KEYER_COLOR_B_CB 0x0c2d
+-#define mmLB3_LB_KEYER_COLOR_B_CB_BASE_IDX 2
+-#define mmLB3_LB_KEYER_COLOR_REP_R_CR 0x0c2e
+-#define mmLB3_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2
+-#define mmLB3_LB_KEYER_COLOR_REP_G_Y 0x0c2f
+-#define mmLB3_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2
+-#define mmLB3_LB_KEYER_COLOR_REP_B_CB 0x0c30
+-#define mmLB3_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2
+-#define mmLB3_LB_BUFFER_LEVEL_STATUS 0x0c31
+-#define mmLB3_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2
+-#define mmLB3_LB_BUFFER_URGENCY_CTRL 0x0c32
+-#define mmLB3_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2
+-#define mmLB3_LB_BUFFER_URGENCY_STATUS 0x0c33
+-#define mmLB3_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2
+-#define mmLB3_LB_BUFFER_STATUS 0x0c34
+-#define mmLB3_LB_BUFFER_STATUS_BASE_IDX 2
+-#define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0x0c35
+-#define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2
+-#define mmLB3_MVP_AFR_FLIP_MODE 0x0c36
+-#define mmLB3_MVP_AFR_FLIP_MODE_BASE_IDX 2
+-#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0x0c37
+-#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2
+-#define mmLB3_MVP_FLIP_LINE_NUM_INSERT 0x0c38
+-#define mmLB3_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2
+-#define mmLB3_DC_MVP_LB_CONTROL 0x0c39
+-#define mmLB3_DC_MVP_LB_CONTROL_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dcfe3_dispdec
+-// base address: 0x1800
+-#define mmDCFE3_DCFE_CLOCK_CONTROL 0x0c5a
+-#define mmDCFE3_DCFE_CLOCK_CONTROL_BASE_IDX 2
+-#define mmDCFE3_DCFE_SOFT_RESET 0x0c5b
+-#define mmDCFE3_DCFE_SOFT_RESET_BASE_IDX 2
+-#define mmDCFE3_DCFE_MEM_PWR_CTRL 0x0c5d
+-#define mmDCFE3_DCFE_MEM_PWR_CTRL_BASE_IDX 2
+-#define mmDCFE3_DCFE_MEM_PWR_CTRL2 0x0c5e
+-#define mmDCFE3_DCFE_MEM_PWR_CTRL2_BASE_IDX 2
+-#define mmDCFE3_DCFE_MEM_PWR_STATUS 0x0c5f
+-#define mmDCFE3_DCFE_MEM_PWR_STATUS_BASE_IDX 2
+-#define mmDCFE3_DCFE_MISC 0x0c60
+-#define mmDCFE3_DCFE_MISC_BASE_IDX 2
+-#define mmDCFE3_DCFE_FLUSH 0x0c61
+-#define mmDCFE3_DCFE_FLUSH_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dc_perfmon6_dispdec
+-// base address: 0x3138
+-#define mmDC_PERFMON6_PERFCOUNTER_CNTL 0x0c6e
+-#define mmDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX 2
+-#define mmDC_PERFMON6_PERFCOUNTER_CNTL2 0x0c6f
+-#define mmDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX 2
+-#define mmDC_PERFMON6_PERFCOUNTER_STATE 0x0c70
+-#define mmDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX 2
+-#define mmDC_PERFMON6_PERFMON_CNTL 0x0c71
+-#define mmDC_PERFMON6_PERFMON_CNTL_BASE_IDX 2
+-#define mmDC_PERFMON6_PERFMON_CNTL2 0x0c72
+-#define mmDC_PERFMON6_PERFMON_CNTL2_BASE_IDX 2
+-#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x0c73
+-#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+-#define mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x0c74
+-#define mmDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX 2
+-#define mmDC_PERFMON6_PERFMON_HI 0x0c75
+-#define mmDC_PERFMON6_PERFMON_HI_BASE_IDX 2
+-#define mmDC_PERFMON6_PERFMON_LOW 0x0c76
+-#define mmDC_PERFMON6_PERFMON_LOW_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dmif_pg3_dispdec
+-// base address: 0x1800
+-#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 0x0c7a
+-#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
+-#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 0x0c7b
+-#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
+-#define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 0x0c7c
+-#define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2
+-#define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL 0x0c7d
+-#define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2
+-#define mmDMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL 0x0c7e
+-#define mmDMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2
+-#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL 0x0c7f
+-#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2
+-#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL2 0x0c80
+-#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2
+-#define mmDMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL 0x0c81
+-#define mmDMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2
+-#define mmDMIF_PG3_DPG_REPEATER_PROGRAM 0x0c82
+-#define mmDMIF_PG3_DPG_REPEATER_PROGRAM_BASE_IDX 2
+-#define mmDMIF_PG3_DPG_CHK_PRE_PROC_CNTL 0x0c86
+-#define mmDMIF_PG3_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2
+-#define mmDMIF_PG3_DPG_DVMM_STATUS 0x0c87
+-#define mmDMIF_PG3_DPG_DVMM_STATUS_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_scl3_dispdec
+-// base address: 0x1800
+-#define mmSCL3_SCL_COEF_RAM_SELECT 0x0c9a
+-#define mmSCL3_SCL_COEF_RAM_SELECT_BASE_IDX 2
+-#define mmSCL3_SCL_COEF_RAM_TAP_DATA 0x0c9b
+-#define mmSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
+-#define mmSCL3_SCL_MODE 0x0c9c
+-#define mmSCL3_SCL_MODE_BASE_IDX 2
+-#define mmSCL3_SCL_TAP_CONTROL 0x0c9d
+-#define mmSCL3_SCL_TAP_CONTROL_BASE_IDX 2
+-#define mmSCL3_SCL_CONTROL 0x0c9e
+-#define mmSCL3_SCL_CONTROL_BASE_IDX 2
+-#define mmSCL3_SCL_BYPASS_CONTROL 0x0c9f
+-#define mmSCL3_SCL_BYPASS_CONTROL_BASE_IDX 2
+-#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x0ca0
+-#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
+-#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL 0x0ca1
+-#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2
+-#define mmSCL3_SCL_HORZ_FILTER_CONTROL 0x0ca2
+-#define mmSCL3_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2
+-#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x0ca3
+-#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
+-#define mmSCL3_SCL_HORZ_FILTER_INIT 0x0ca4
+-#define mmSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2
+-#define mmSCL3_SCL_VERT_FILTER_CONTROL 0x0ca5
+-#define mmSCL3_SCL_VERT_FILTER_CONTROL_BASE_IDX 2
+-#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x0ca6
+-#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
+-#define mmSCL3_SCL_VERT_FILTER_INIT 0x0ca7
+-#define mmSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2
+-#define mmSCL3_SCL_VERT_FILTER_INIT_BOT 0x0ca8
+-#define mmSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
+-#define mmSCL3_SCL_ROUND_OFFSET 0x0ca9
+-#define mmSCL3_SCL_ROUND_OFFSET_BASE_IDX 2
+-#define mmSCL3_SCL_UPDATE 0x0caa
+-#define mmSCL3_SCL_UPDATE_BASE_IDX 2
+-#define mmSCL3_SCL_F_SHARP_CONTROL 0x0cab
+-#define mmSCL3_SCL_F_SHARP_CONTROL_BASE_IDX 2
+-#define mmSCL3_SCL_ALU_CONTROL 0x0cac
+-#define mmSCL3_SCL_ALU_CONTROL_BASE_IDX 2
+-#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0x0cad
+-#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
+-#define mmSCL3_VIEWPORT_START_SECONDARY 0x0cae
+-#define mmSCL3_VIEWPORT_START_SECONDARY_BASE_IDX 2
+-#define mmSCL3_VIEWPORT_START 0x0caf
+-#define mmSCL3_VIEWPORT_START_BASE_IDX 2
+-#define mmSCL3_VIEWPORT_SIZE 0x0cb0
+-#define mmSCL3_VIEWPORT_SIZE_BASE_IDX 2
+-#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT 0x0cb1
+-#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
+-#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM 0x0cb2
+-#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
+-#define mmSCL3_SCL_MODE_CHANGE_DET1 0x0cb3
+-#define mmSCL3_SCL_MODE_CHANGE_DET1_BASE_IDX 2
+-#define mmSCL3_SCL_MODE_CHANGE_DET2 0x0cb4
+-#define mmSCL3_SCL_MODE_CHANGE_DET2_BASE_IDX 2
+-#define mmSCL3_SCL_MODE_CHANGE_DET3 0x0cb5
+-#define mmSCL3_SCL_MODE_CHANGE_DET3_BASE_IDX 2
+-#define mmSCL3_SCL_MODE_CHANGE_MASK 0x0cb6
+-#define mmSCL3_SCL_MODE_CHANGE_MASK_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_blnd3_dispdec
+-// base address: 0x1800
+-#define mmBLND3_BLND_CONTROL 0x0cc7
+-#define mmBLND3_BLND_CONTROL_BASE_IDX 2
+-#define mmBLND3_BLND_SM_CONTROL2 0x0cc8
+-#define mmBLND3_BLND_SM_CONTROL2_BASE_IDX 2
+-#define mmBLND3_BLND_CONTROL2 0x0cc9
+-#define mmBLND3_BLND_CONTROL2_BASE_IDX 2
+-#define mmBLND3_BLND_UPDATE 0x0cca
+-#define mmBLND3_BLND_UPDATE_BASE_IDX 2
+-#define mmBLND3_BLND_UNDERFLOW_INTERRUPT 0x0ccb
+-#define mmBLND3_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2
+-#define mmBLND3_BLND_V_UPDATE_LOCK 0x0ccc
+-#define mmBLND3_BLND_V_UPDATE_LOCK_BASE_IDX 2
+-#define mmBLND3_BLND_REG_UPDATE_STATUS 0x0ccd
+-#define mmBLND3_BLND_REG_UPDATE_STATUS_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_crtc3_dispdec
+-// base address: 0x1800
+-#define mmCRTC3_CRTC_H_BLANK_EARLY_NUM 0x0cd2
+-#define mmCRTC3_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2
+-#define mmCRTC3_CRTC_H_TOTAL 0x0cd3
+-#define mmCRTC3_CRTC_H_TOTAL_BASE_IDX 2
+-#define mmCRTC3_CRTC_H_BLANK_START_END 0x0cd4
+-#define mmCRTC3_CRTC_H_BLANK_START_END_BASE_IDX 2
+-#define mmCRTC3_CRTC_H_SYNC_A 0x0cd5
+-#define mmCRTC3_CRTC_H_SYNC_A_BASE_IDX 2
+-#define mmCRTC3_CRTC_H_SYNC_A_CNTL 0x0cd6
+-#define mmCRTC3_CRTC_H_SYNC_A_CNTL_BASE_IDX 2
+-#define mmCRTC3_CRTC_H_SYNC_B 0x0cd7
+-#define mmCRTC3_CRTC_H_SYNC_B_BASE_IDX 2
+-#define mmCRTC3_CRTC_H_SYNC_B_CNTL 0x0cd8
+-#define mmCRTC3_CRTC_H_SYNC_B_CNTL_BASE_IDX 2
+-#define mmCRTC3_CRTC_VBI_END 0x0cd9
+-#define mmCRTC3_CRTC_VBI_END_BASE_IDX 2
+-#define mmCRTC3_CRTC_V_TOTAL 0x0cda
+-#define mmCRTC3_CRTC_V_TOTAL_BASE_IDX 2
+-#define mmCRTC3_CRTC_V_TOTAL_MIN 0x0cdb
+-#define mmCRTC3_CRTC_V_TOTAL_MIN_BASE_IDX 2
+-#define mmCRTC3_CRTC_V_TOTAL_MAX 0x0cdc
+-#define mmCRTC3_CRTC_V_TOTAL_MAX_BASE_IDX 2
+-#define mmCRTC3_CRTC_V_TOTAL_CONTROL 0x0cdd
+-#define mmCRTC3_CRTC_V_TOTAL_CONTROL_BASE_IDX 2
+-#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS 0x0cde
+-#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2
+-#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS 0x0cdf
+-#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2
+-#define mmCRTC3_CRTC_V_BLANK_START_END 0x0ce0
+-#define mmCRTC3_CRTC_V_BLANK_START_END_BASE_IDX 2
+-#define mmCRTC3_CRTC_V_SYNC_A 0x0ce1
+-#define mmCRTC3_CRTC_V_SYNC_A_BASE_IDX 2
+-#define mmCRTC3_CRTC_V_SYNC_A_CNTL 0x0ce2
+-#define mmCRTC3_CRTC_V_SYNC_A_CNTL_BASE_IDX 2
+-#define mmCRTC3_CRTC_V_SYNC_B 0x0ce3
+-#define mmCRTC3_CRTC_V_SYNC_B_BASE_IDX 2
+-#define mmCRTC3_CRTC_V_SYNC_B_CNTL 0x0ce4
+-#define mmCRTC3_CRTC_V_SYNC_B_CNTL_BASE_IDX 2
+-#define mmCRTC3_CRTC_DTMTEST_CNTL 0x0ce5
+-#define mmCRTC3_CRTC_DTMTEST_CNTL_BASE_IDX 2
+-#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION 0x0ce6
+-#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2
+-#define mmCRTC3_CRTC_TRIGA_CNTL 0x0ce7
+-#define mmCRTC3_CRTC_TRIGA_CNTL_BASE_IDX 2
+-#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG 0x0ce8
+-#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2
+-#define mmCRTC3_CRTC_TRIGB_CNTL 0x0ce9
+-#define mmCRTC3_CRTC_TRIGB_CNTL_BASE_IDX 2
+-#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG 0x0cea
+-#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2
+-#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL 0x0ceb
+-#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
+-#define mmCRTC3_CRTC_FLOW_CONTROL 0x0cec
+-#define mmCRTC3_CRTC_FLOW_CONTROL_BASE_IDX 2
+-#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE 0x0ced
+-#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
+-#define mmCRTC3_CRTC_AVSYNC_COUNTER 0x0cee
+-#define mmCRTC3_CRTC_AVSYNC_COUNTER_BASE_IDX 2
+-#define mmCRTC3_CRTC_CONTROL 0x0cef
+-#define mmCRTC3_CRTC_CONTROL_BASE_IDX 2
+-#define mmCRTC3_CRTC_BLANK_CONTROL 0x0cf0
+-#define mmCRTC3_CRTC_BLANK_CONTROL_BASE_IDX 2
+-#define mmCRTC3_CRTC_INTERLACE_CONTROL 0x0cf1
+-#define mmCRTC3_CRTC_INTERLACE_CONTROL_BASE_IDX 2
+-#define mmCRTC3_CRTC_INTERLACE_STATUS 0x0cf2
+-#define mmCRTC3_CRTC_INTERLACE_STATUS_BASE_IDX 2
+-#define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL 0x0cf3
+-#define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2
+-#define mmCRTC3_CRTC_PIXEL_DATA_READBACK0 0x0cf4
+-#define mmCRTC3_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2
+-#define mmCRTC3_CRTC_PIXEL_DATA_READBACK1 0x0cf5
+-#define mmCRTC3_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2
+-#define mmCRTC3_CRTC_STATUS 0x0cf6
+-#define mmCRTC3_CRTC_STATUS_BASE_IDX 2
+-#define mmCRTC3_CRTC_STATUS_POSITION 0x0cf7
+-#define mmCRTC3_CRTC_STATUS_POSITION_BASE_IDX 2
+-#define mmCRTC3_CRTC_NOM_VERT_POSITION 0x0cf8
+-#define mmCRTC3_CRTC_NOM_VERT_POSITION_BASE_IDX 2
+-#define mmCRTC3_CRTC_STATUS_FRAME_COUNT 0x0cf9
+-#define mmCRTC3_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2
+-#define mmCRTC3_CRTC_STATUS_VF_COUNT 0x0cfa
+-#define mmCRTC3_CRTC_STATUS_VF_COUNT_BASE_IDX 2
+-#define mmCRTC3_CRTC_STATUS_HV_COUNT 0x0cfb
+-#define mmCRTC3_CRTC_STATUS_HV_COUNT_BASE_IDX 2
+-#define mmCRTC3_CRTC_COUNT_CONTROL 0x0cfc
+-#define mmCRTC3_CRTC_COUNT_CONTROL_BASE_IDX 2
+-#define mmCRTC3_CRTC_COUNT_RESET 0x0cfd
+-#define mmCRTC3_CRTC_COUNT_RESET_BASE_IDX 2
+-#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x0cfe
+-#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
+-#define mmCRTC3_CRTC_VERT_SYNC_CONTROL 0x0cff
+-#define mmCRTC3_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2
+-#define mmCRTC3_CRTC_STEREO_STATUS 0x0d00
+-#define mmCRTC3_CRTC_STEREO_STATUS_BASE_IDX 2
+-#define mmCRTC3_CRTC_STEREO_CONTROL 0x0d01
+-#define mmCRTC3_CRTC_STEREO_CONTROL_BASE_IDX 2
+-#define mmCRTC3_CRTC_SNAPSHOT_STATUS 0x0d02
+-#define mmCRTC3_CRTC_SNAPSHOT_STATUS_BASE_IDX 2
+-#define mmCRTC3_CRTC_SNAPSHOT_CONTROL 0x0d03
+-#define mmCRTC3_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2
+-#define mmCRTC3_CRTC_SNAPSHOT_POSITION 0x0d04
+-#define mmCRTC3_CRTC_SNAPSHOT_POSITION_BASE_IDX 2
+-#define mmCRTC3_CRTC_SNAPSHOT_FRAME 0x0d05
+-#define mmCRTC3_CRTC_SNAPSHOT_FRAME_BASE_IDX 2
+-#define mmCRTC3_CRTC_START_LINE_CONTROL 0x0d06
+-#define mmCRTC3_CRTC_START_LINE_CONTROL_BASE_IDX 2
+-#define mmCRTC3_CRTC_INTERRUPT_CONTROL 0x0d07
+-#define mmCRTC3_CRTC_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmCRTC3_CRTC_UPDATE_LOCK 0x0d08
+-#define mmCRTC3_CRTC_UPDATE_LOCK_BASE_IDX 2
+-#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL 0x0d09
+-#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
+-#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x0d0a
+-#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2
+-#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL 0x0d0b
+-#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2
+-#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS 0x0d0c
+-#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2
+-#define mmCRTC3_CRTC_TEST_PATTERN_COLOR 0x0d0d
+-#define mmCRTC3_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2
+-#define mmCRTC3_CRTC_MASTER_UPDATE_LOCK 0x0d0e
+-#define mmCRTC3_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2
+-#define mmCRTC3_CRTC_MASTER_UPDATE_MODE 0x0d0f
+-#define mmCRTC3_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2
+-#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT 0x0d10
+-#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2
+-#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x0d11
+-#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2
+-#define mmCRTC3_CRTC_MVP_STATUS 0x0d12
+-#define mmCRTC3_CRTC_MVP_STATUS_BASE_IDX 2
+-#define mmCRTC3_CRTC_MASTER_EN 0x0d13
+-#define mmCRTC3_CRTC_MASTER_EN_BASE_IDX 2
+-#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT 0x0d14
+-#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2
+-#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS 0x0d15
+-#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2
+-#define mmCRTC3_CRTC_OVERSCAN_COLOR 0x0d17
+-#define mmCRTC3_CRTC_OVERSCAN_COLOR_BASE_IDX 2
+-#define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT 0x0d18
+-#define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2
+-#define mmCRTC3_CRTC_BLANK_DATA_COLOR 0x0d19
+-#define mmCRTC3_CRTC_BLANK_DATA_COLOR_BASE_IDX 2
+-#define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT 0x0d1a
+-#define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2
+-#define mmCRTC3_CRTC_BLACK_COLOR 0x0d1b
+-#define mmCRTC3_CRTC_BLACK_COLOR_BASE_IDX 2
+-#define mmCRTC3_CRTC_BLACK_COLOR_EXT 0x0d1c
+-#define mmCRTC3_CRTC_BLACK_COLOR_EXT_BASE_IDX 2
+-#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION 0x0d1d
+-#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
+-#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x0d1e
+-#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
+-#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION 0x0d1f
+-#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
+-#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x0d20
+-#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
+-#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION 0x0d21
+-#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
+-#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x0d22
+-#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
+-#define mmCRTC3_CRTC_CRC_CNTL 0x0d23
+-#define mmCRTC3_CRTC_CRC_CNTL_BASE_IDX 2
+-#define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL 0x0d24
+-#define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
+-#define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL 0x0d25
+-#define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
+-#define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL 0x0d26
+-#define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
+-#define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL 0x0d27
+-#define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
+-#define mmCRTC3_CRTC_CRC0_DATA_RG 0x0d28
+-#define mmCRTC3_CRTC_CRC0_DATA_RG_BASE_IDX 2
+-#define mmCRTC3_CRTC_CRC0_DATA_B 0x0d29
+-#define mmCRTC3_CRTC_CRC0_DATA_B_BASE_IDX 2
+-#define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL 0x0d2a
+-#define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
+-#define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL 0x0d2b
+-#define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
+-#define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL 0x0d2c
+-#define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
+-#define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL 0x0d2d
+-#define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
+-#define mmCRTC3_CRTC_CRC1_DATA_RG 0x0d2e
+-#define mmCRTC3_CRTC_CRC1_DATA_RG_BASE_IDX 2
+-#define mmCRTC3_CRTC_CRC1_DATA_B 0x0d2f
+-#define mmCRTC3_CRTC_CRC1_DATA_B_BASE_IDX 2
+-#define mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL 0x0d30
+-#define mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2
+-#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x0d31
+-#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2
+-#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x0d32
+-#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2
+-#define mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x0d33
+-#define mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x0d34
+-#define mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x0d35
+-#define mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL 0x0d36
+-#define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2
+-#define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL 0x0d37
+-#define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2
+-#define mmCRTC3_CRTC_GSL_VSYNC_GAP 0x0d38
+-#define mmCRTC3_CRTC_GSL_VSYNC_GAP_BASE_IDX 2
+-#define mmCRTC3_CRTC_GSL_WINDOW 0x0d39
+-#define mmCRTC3_CRTC_GSL_WINDOW_BASE_IDX 2
+-#define mmCRTC3_CRTC_GSL_CONTROL 0x0d3a
+-#define mmCRTC3_CRTC_GSL_CONTROL_BASE_IDX 2
+-#define mmCRTC3_CRTC_RANGE_TIMING_INT_STATUS 0x0d3d
+-#define mmCRTC3_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2
+-#define mmCRTC3_CRTC_DRR_CONTROL 0x0d3e
+-#define mmCRTC3_CRTC_DRR_CONTROL_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_fmt3_dispdec
+-// base address: 0x1800
+-#define mmFMT3_FMT_CLAMP_COMPONENT_R 0x0d42
+-#define mmFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
+-#define mmFMT3_FMT_CLAMP_COMPONENT_G 0x0d43
+-#define mmFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
+-#define mmFMT3_FMT_CLAMP_COMPONENT_B 0x0d44
+-#define mmFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
+-#define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x0d45
+-#define mmFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
+-#define mmFMT3_FMT_CONTROL 0x0d46
+-#define mmFMT3_FMT_CONTROL_BASE_IDX 2
+-#define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x0d47
+-#define mmFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
+-#define mmFMT3_FMT_DITHER_RAND_R_SEED 0x0d48
+-#define mmFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
+-#define mmFMT3_FMT_DITHER_RAND_G_SEED 0x0d49
+-#define mmFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
+-#define mmFMT3_FMT_DITHER_RAND_B_SEED 0x0d4a
+-#define mmFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
+-#define mmFMT3_FMT_CLAMP_CNTL 0x0d4e
+-#define mmFMT3_FMT_CLAMP_CNTL_BASE_IDX 2
+-#define mmFMT3_FMT_CRC_CNTL 0x0d4f
+-#define mmFMT3_FMT_CRC_CNTL_BASE_IDX 2
+-#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK 0x0d50
+-#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
+-#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x0d51
+-#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
+-#define mmFMT3_FMT_CRC_SIG_RED_GREEN 0x0d52
+-#define mmFMT3_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2
+-#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL 0x0d53
+-#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2
+-#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x0d54
+-#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
+-#define mmFMT3_FMT_420_HBLANK_EARLY_START 0x0d55
+-#define mmFMT3_FMT_420_HBLANK_EARLY_START_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dcp4_dispdec
+-// base address: 0x2000
+-#define mmDCP4_GRPH_ENABLE 0x0d5a
+-#define mmDCP4_GRPH_ENABLE_BASE_IDX 2
+-#define mmDCP4_GRPH_CONTROL 0x0d5b
+-#define mmDCP4_GRPH_CONTROL_BASE_IDX 2
+-#define mmDCP4_GRPH_LUT_10BIT_BYPASS 0x0d5c
+-#define mmDCP4_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2
+-#define mmDCP4_GRPH_SWAP_CNTL 0x0d5d
+-#define mmDCP4_GRPH_SWAP_CNTL_BASE_IDX 2
+-#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS 0x0d5e
+-#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
+-#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS 0x0d5f
+-#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
+-#define mmDCP4_GRPH_PITCH 0x0d60
+-#define mmDCP4_GRPH_PITCH_BASE_IDX 2
+-#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0d61
+-#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+-#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0d62
+-#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+-#define mmDCP4_GRPH_SURFACE_OFFSET_X 0x0d63
+-#define mmDCP4_GRPH_SURFACE_OFFSET_X_BASE_IDX 2
+-#define mmDCP4_GRPH_SURFACE_OFFSET_Y 0x0d64
+-#define mmDCP4_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2
+-#define mmDCP4_GRPH_X_START 0x0d65
+-#define mmDCP4_GRPH_X_START_BASE_IDX 2
+-#define mmDCP4_GRPH_Y_START 0x0d66
+-#define mmDCP4_GRPH_Y_START_BASE_IDX 2
+-#define mmDCP4_GRPH_X_END 0x0d67
+-#define mmDCP4_GRPH_X_END_BASE_IDX 2
+-#define mmDCP4_GRPH_Y_END 0x0d68
+-#define mmDCP4_GRPH_Y_END_BASE_IDX 2
+-#define mmDCP4_INPUT_GAMMA_CONTROL 0x0d69
+-#define mmDCP4_INPUT_GAMMA_CONTROL_BASE_IDX 2
+-#define mmDCP4_GRPH_UPDATE 0x0d6a
+-#define mmDCP4_GRPH_UPDATE_BASE_IDX 2
+-#define mmDCP4_GRPH_FLIP_CONTROL 0x0d6b
+-#define mmDCP4_GRPH_FLIP_CONTROL_BASE_IDX 2
+-#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE 0x0d6c
+-#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2
+-#define mmDCP4_GRPH_DFQ_CONTROL 0x0d6d
+-#define mmDCP4_GRPH_DFQ_CONTROL_BASE_IDX 2
+-#define mmDCP4_GRPH_DFQ_STATUS 0x0d6e
+-#define mmDCP4_GRPH_DFQ_STATUS_BASE_IDX 2
+-#define mmDCP4_GRPH_INTERRUPT_STATUS 0x0d6f
+-#define mmDCP4_GRPH_INTERRUPT_STATUS_BASE_IDX 2
+-#define mmDCP4_GRPH_INTERRUPT_CONTROL 0x0d70
+-#define mmDCP4_GRPH_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0d71
+-#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2
+-#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS 0x0d72
+-#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2
+-#define mmDCP4_GRPH_COMPRESS_PITCH 0x0d73
+-#define mmDCP4_GRPH_COMPRESS_PITCH_BASE_IDX 2
+-#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0d74
+-#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+-#define mmDCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0d75
+-#define mmDCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2
+-#define mmDCP4_PRESCALE_GRPH_CONTROL 0x0d76
+-#define mmDCP4_PRESCALE_GRPH_CONTROL_BASE_IDX 2
+-#define mmDCP4_PRESCALE_VALUES_GRPH_R 0x0d77
+-#define mmDCP4_PRESCALE_VALUES_GRPH_R_BASE_IDX 2
+-#define mmDCP4_PRESCALE_VALUES_GRPH_G 0x0d78
+-#define mmDCP4_PRESCALE_VALUES_GRPH_G_BASE_IDX 2
+-#define mmDCP4_PRESCALE_VALUES_GRPH_B 0x0d79
+-#define mmDCP4_PRESCALE_VALUES_GRPH_B_BASE_IDX 2
+-#define mmDCP4_INPUT_CSC_CONTROL 0x0d7a
+-#define mmDCP4_INPUT_CSC_CONTROL_BASE_IDX 2
+-#define mmDCP4_INPUT_CSC_C11_C12 0x0d7b
+-#define mmDCP4_INPUT_CSC_C11_C12_BASE_IDX 2
+-#define mmDCP4_INPUT_CSC_C13_C14 0x0d7c
+-#define mmDCP4_INPUT_CSC_C13_C14_BASE_IDX 2
+-#define mmDCP4_INPUT_CSC_C21_C22 0x0d7d
+-#define mmDCP4_INPUT_CSC_C21_C22_BASE_IDX 2
+-#define mmDCP4_INPUT_CSC_C23_C24 0x0d7e
+-#define mmDCP4_INPUT_CSC_C23_C24_BASE_IDX 2
+-#define mmDCP4_INPUT_CSC_C31_C32 0x0d7f
+-#define mmDCP4_INPUT_CSC_C31_C32_BASE_IDX 2
+-#define mmDCP4_INPUT_CSC_C33_C34 0x0d80
+-#define mmDCP4_INPUT_CSC_C33_C34_BASE_IDX 2
+-#define mmDCP4_OUTPUT_CSC_CONTROL 0x0d81
+-#define mmDCP4_OUTPUT_CSC_CONTROL_BASE_IDX 2
+-#define mmDCP4_OUTPUT_CSC_C11_C12 0x0d82
+-#define mmDCP4_OUTPUT_CSC_C11_C12_BASE_IDX 2
+-#define mmDCP4_OUTPUT_CSC_C13_C14 0x0d83
+-#define mmDCP4_OUTPUT_CSC_C13_C14_BASE_IDX 2
+-#define mmDCP4_OUTPUT_CSC_C21_C22 0x0d84
+-#define mmDCP4_OUTPUT_CSC_C21_C22_BASE_IDX 2
+-#define mmDCP4_OUTPUT_CSC_C23_C24 0x0d85
+-#define mmDCP4_OUTPUT_CSC_C23_C24_BASE_IDX 2
+-#define mmDCP4_OUTPUT_CSC_C31_C32 0x0d86
+-#define mmDCP4_OUTPUT_CSC_C31_C32_BASE_IDX 2
+-#define mmDCP4_OUTPUT_CSC_C33_C34 0x0d87
+-#define mmDCP4_OUTPUT_CSC_C33_C34_BASE_IDX 2
+-#define mmDCP4_COMM_MATRIXA_TRANS_C11_C12 0x0d88
+-#define mmDCP4_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2
+-#define mmDCP4_COMM_MATRIXA_TRANS_C13_C14 0x0d89
+-#define mmDCP4_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2
+-#define mmDCP4_COMM_MATRIXA_TRANS_C21_C22 0x0d8a
+-#define mmDCP4_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2
+-#define mmDCP4_COMM_MATRIXA_TRANS_C23_C24 0x0d8b
+-#define mmDCP4_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2
+-#define mmDCP4_COMM_MATRIXA_TRANS_C31_C32 0x0d8c
+-#define mmDCP4_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2
+-#define mmDCP4_COMM_MATRIXA_TRANS_C33_C34 0x0d8d
+-#define mmDCP4_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2
+-#define mmDCP4_COMM_MATRIXB_TRANS_C11_C12 0x0d8e
+-#define mmDCP4_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2
+-#define mmDCP4_COMM_MATRIXB_TRANS_C13_C14 0x0d8f
+-#define mmDCP4_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2
+-#define mmDCP4_COMM_MATRIXB_TRANS_C21_C22 0x0d90
+-#define mmDCP4_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2
+-#define mmDCP4_COMM_MATRIXB_TRANS_C23_C24 0x0d91
+-#define mmDCP4_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2
+-#define mmDCP4_COMM_MATRIXB_TRANS_C31_C32 0x0d92
+-#define mmDCP4_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2
+-#define mmDCP4_COMM_MATRIXB_TRANS_C33_C34 0x0d93
+-#define mmDCP4_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2
+-#define mmDCP4_DENORM_CONTROL 0x0d94
+-#define mmDCP4_DENORM_CONTROL_BASE_IDX 2
+-#define mmDCP4_OUT_ROUND_CONTROL 0x0d95
+-#define mmDCP4_OUT_ROUND_CONTROL_BASE_IDX 2
+-#define mmDCP4_OUT_CLAMP_CONTROL_R_CR 0x0d96
+-#define mmDCP4_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2
+-#define mmDCP4_OUT_CLAMP_CONTROL_G_Y 0x0d97
+-#define mmDCP4_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2
+-#define mmDCP4_OUT_CLAMP_CONTROL_B_CB 0x0d98
+-#define mmDCP4_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2
+-#define mmDCP4_KEY_CONTROL 0x0d99
+-#define mmDCP4_KEY_CONTROL_BASE_IDX 2
+-#define mmDCP4_KEY_RANGE_ALPHA 0x0d9a
+-#define mmDCP4_KEY_RANGE_ALPHA_BASE_IDX 2
+-#define mmDCP4_KEY_RANGE_RED 0x0d9b
+-#define mmDCP4_KEY_RANGE_RED_BASE_IDX 2
+-#define mmDCP4_KEY_RANGE_GREEN 0x0d9c
+-#define mmDCP4_KEY_RANGE_GREEN_BASE_IDX 2
+-#define mmDCP4_KEY_RANGE_BLUE 0x0d9d
+-#define mmDCP4_KEY_RANGE_BLUE_BASE_IDX 2
+-#define mmDCP4_DEGAMMA_CONTROL 0x0d9e
+-#define mmDCP4_DEGAMMA_CONTROL_BASE_IDX 2
+-#define mmDCP4_GAMUT_REMAP_CONTROL 0x0d9f
+-#define mmDCP4_GAMUT_REMAP_CONTROL_BASE_IDX 2
+-#define mmDCP4_GAMUT_REMAP_C11_C12 0x0da0
+-#define mmDCP4_GAMUT_REMAP_C11_C12_BASE_IDX 2
+-#define mmDCP4_GAMUT_REMAP_C13_C14 0x0da1
+-#define mmDCP4_GAMUT_REMAP_C13_C14_BASE_IDX 2
+-#define mmDCP4_GAMUT_REMAP_C21_C22 0x0da2
+-#define mmDCP4_GAMUT_REMAP_C21_C22_BASE_IDX 2
+-#define mmDCP4_GAMUT_REMAP_C23_C24 0x0da3
+-#define mmDCP4_GAMUT_REMAP_C23_C24_BASE_IDX 2
+-#define mmDCP4_GAMUT_REMAP_C31_C32 0x0da4
+-#define mmDCP4_GAMUT_REMAP_C31_C32_BASE_IDX 2
+-#define mmDCP4_GAMUT_REMAP_C33_C34 0x0da5
+-#define mmDCP4_GAMUT_REMAP_C33_C34_BASE_IDX 2
+-#define mmDCP4_DCP_SPATIAL_DITHER_CNTL 0x0da6
+-#define mmDCP4_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2
+-#define mmDCP4_DCP_RANDOM_SEEDS 0x0da7
+-#define mmDCP4_DCP_RANDOM_SEEDS_BASE_IDX 2
+-#define mmDCP4_DCP_FP_CONVERTED_FIELD 0x0da8
+-#define mmDCP4_DCP_FP_CONVERTED_FIELD_BASE_IDX 2
+-#define mmDCP4_CUR_CONTROL 0x0da9
+-#define mmDCP4_CUR_CONTROL_BASE_IDX 2
+-#define mmDCP4_CUR_SURFACE_ADDRESS 0x0daa
+-#define mmDCP4_CUR_SURFACE_ADDRESS_BASE_IDX 2
+-#define mmDCP4_CUR_SIZE 0x0dab
+-#define mmDCP4_CUR_SIZE_BASE_IDX 2
+-#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH 0x0dac
+-#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+-#define mmDCP4_CUR_POSITION 0x0dad
+-#define mmDCP4_CUR_POSITION_BASE_IDX 2
+-#define mmDCP4_CUR_HOT_SPOT 0x0dae
+-#define mmDCP4_CUR_HOT_SPOT_BASE_IDX 2
+-#define mmDCP4_CUR_COLOR1 0x0daf
+-#define mmDCP4_CUR_COLOR1_BASE_IDX 2
+-#define mmDCP4_CUR_COLOR2 0x0db0
+-#define mmDCP4_CUR_COLOR2_BASE_IDX 2
+-#define mmDCP4_CUR_UPDATE 0x0db1
+-#define mmDCP4_CUR_UPDATE_BASE_IDX 2
+-#define mmDCP4_CUR_REQUEST_FILTER_CNTL 0x0dbb
+-#define mmDCP4_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2
+-#define mmDCP4_CUR_STEREO_CONTROL 0x0dbc
+-#define mmDCP4_CUR_STEREO_CONTROL_BASE_IDX 2
+-#define mmDCP4_DC_LUT_RW_MODE 0x0dbe
+-#define mmDCP4_DC_LUT_RW_MODE_BASE_IDX 2
+-#define mmDCP4_DC_LUT_RW_INDEX 0x0dbf
+-#define mmDCP4_DC_LUT_RW_INDEX_BASE_IDX 2
+-#define mmDCP4_DC_LUT_SEQ_COLOR 0x0dc0
+-#define mmDCP4_DC_LUT_SEQ_COLOR_BASE_IDX 2
+-#define mmDCP4_DC_LUT_PWL_DATA 0x0dc1
+-#define mmDCP4_DC_LUT_PWL_DATA_BASE_IDX 2
+-#define mmDCP4_DC_LUT_30_COLOR 0x0dc2
+-#define mmDCP4_DC_LUT_30_COLOR_BASE_IDX 2
+-#define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE 0x0dc3
+-#define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2
+-#define mmDCP4_DC_LUT_WRITE_EN_MASK 0x0dc4
+-#define mmDCP4_DC_LUT_WRITE_EN_MASK_BASE_IDX 2
+-#define mmDCP4_DC_LUT_AUTOFILL 0x0dc5
+-#define mmDCP4_DC_LUT_AUTOFILL_BASE_IDX 2
+-#define mmDCP4_DC_LUT_CONTROL 0x0dc6
+-#define mmDCP4_DC_LUT_CONTROL_BASE_IDX 2
+-#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE 0x0dc7
+-#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2
+-#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN 0x0dc8
+-#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2
+-#define mmDCP4_DC_LUT_BLACK_OFFSET_RED 0x0dc9
+-#define mmDCP4_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2
+-#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE 0x0dca
+-#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2
+-#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN 0x0dcb
+-#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2
+-#define mmDCP4_DC_LUT_WHITE_OFFSET_RED 0x0dcc
+-#define mmDCP4_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2
+-#define mmDCP4_DCP_CRC_CONTROL 0x0dcd
+-#define mmDCP4_DCP_CRC_CONTROL_BASE_IDX 2
+-#define mmDCP4_DCP_CRC_MASK 0x0dce
+-#define mmDCP4_DCP_CRC_MASK_BASE_IDX 2
+-#define mmDCP4_DCP_CRC_CURRENT 0x0dcf
+-#define mmDCP4_DCP_CRC_CURRENT_BASE_IDX 2
+-#define mmDCP4_DVMM_PTE_CONTROL 0x0dd0
+-#define mmDCP4_DVMM_PTE_CONTROL_BASE_IDX 2
+-#define mmDCP4_DCP_CRC_LAST 0x0dd1
+-#define mmDCP4_DCP_CRC_LAST_BASE_IDX 2
+-#define mmDCP4_DVMM_PTE_ARB_CONTROL 0x0dd2
+-#define mmDCP4_DVMM_PTE_ARB_CONTROL_BASE_IDX 2
+-#define mmDCP4_GRPH_FLIP_RATE_CNTL 0x0dd4
+-#define mmDCP4_GRPH_FLIP_RATE_CNTL_BASE_IDX 2
+-#define mmDCP4_DCP_GSL_CONTROL 0x0dd5
+-#define mmDCP4_DCP_GSL_CONTROL_BASE_IDX 2
+-#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x0dd6
+-#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2
+-#define mmDCP4_GRPH_STEREOSYNC_FLIP 0x0ddc
+-#define mmDCP4_GRPH_STEREOSYNC_FLIP_BASE_IDX 2
+-#define mmDCP4_HW_ROTATION 0x0dde
+-#define mmDCP4_HW_ROTATION_BASE_IDX 2
+-#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x0ddf
+-#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2
+-#define mmDCP4_REGAMMA_CONTROL 0x0de0
+-#define mmDCP4_REGAMMA_CONTROL_BASE_IDX 2
+-#define mmDCP4_REGAMMA_LUT_INDEX 0x0de1
+-#define mmDCP4_REGAMMA_LUT_INDEX_BASE_IDX 2
+-#define mmDCP4_REGAMMA_LUT_DATA 0x0de2
+-#define mmDCP4_REGAMMA_LUT_DATA_BASE_IDX 2
+-#define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK 0x0de3
+-#define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2
+-#define mmDCP4_REGAMMA_CNTLA_START_CNTL 0x0de4
+-#define mmDCP4_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2
+-#define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL 0x0de5
+-#define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2
+-#define mmDCP4_REGAMMA_CNTLA_END_CNTL1 0x0de6
+-#define mmDCP4_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2
+-#define mmDCP4_REGAMMA_CNTLA_END_CNTL2 0x0de7
+-#define mmDCP4_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2
+-#define mmDCP4_REGAMMA_CNTLA_REGION_0_1 0x0de8
+-#define mmDCP4_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2
+-#define mmDCP4_REGAMMA_CNTLA_REGION_2_3 0x0de9
+-#define mmDCP4_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2
+-#define mmDCP4_REGAMMA_CNTLA_REGION_4_5 0x0dea
+-#define mmDCP4_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2
+-#define mmDCP4_REGAMMA_CNTLA_REGION_6_7 0x0deb
+-#define mmDCP4_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2
+-#define mmDCP4_REGAMMA_CNTLA_REGION_8_9 0x0dec
+-#define mmDCP4_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2
+-#define mmDCP4_REGAMMA_CNTLA_REGION_10_11 0x0ded
+-#define mmDCP4_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2
+-#define mmDCP4_REGAMMA_CNTLA_REGION_12_13 0x0dee
+-#define mmDCP4_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2
+-#define mmDCP4_REGAMMA_CNTLA_REGION_14_15 0x0def
+-#define mmDCP4_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2
+-#define mmDCP4_REGAMMA_CNTLB_START_CNTL 0x0df0
+-#define mmDCP4_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2
+-#define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL 0x0df1
+-#define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2
+-#define mmDCP4_REGAMMA_CNTLB_END_CNTL1 0x0df2
+-#define mmDCP4_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2
+-#define mmDCP4_REGAMMA_CNTLB_END_CNTL2 0x0df3
+-#define mmDCP4_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2
+-#define mmDCP4_REGAMMA_CNTLB_REGION_0_1 0x0df4
+-#define mmDCP4_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2
+-#define mmDCP4_REGAMMA_CNTLB_REGION_2_3 0x0df5
+-#define mmDCP4_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2
+-#define mmDCP4_REGAMMA_CNTLB_REGION_4_5 0x0df6
+-#define mmDCP4_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2
+-#define mmDCP4_REGAMMA_CNTLB_REGION_6_7 0x0df7
+-#define mmDCP4_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2
+-#define mmDCP4_REGAMMA_CNTLB_REGION_8_9 0x0df8
+-#define mmDCP4_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2
+-#define mmDCP4_REGAMMA_CNTLB_REGION_10_11 0x0df9
+-#define mmDCP4_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2
+-#define mmDCP4_REGAMMA_CNTLB_REGION_12_13 0x0dfa
+-#define mmDCP4_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2
+-#define mmDCP4_REGAMMA_CNTLB_REGION_14_15 0x0dfb
+-#define mmDCP4_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2
+-#define mmDCP4_ALPHA_CONTROL 0x0dfc
+-#define mmDCP4_ALPHA_CONTROL_BASE_IDX 2
+-#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x0dfd
+-#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2
+-#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x0dfe
+-#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+-#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x0dff
+-#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2
+-#define mmDCP4_GRPH_XDMA_FLIP_TIMEOUT 0x0e00
+-#define mmDCP4_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2
+-#define mmDCP4_GRPH_XDMA_FLIP_AVG_DELAY 0x0e01
+-#define mmDCP4_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2
+-#define mmDCP4_GRPH_SURFACE_COUNTER_CONTROL 0x0e02
+-#define mmDCP4_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2
+-#define mmDCP4_GRPH_SURFACE_COUNTER_OUTPUT 0x0e03
+-#define mmDCP4_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_lb4_dispdec
+-// base address: 0x2000
+-#define mmLB4_LB_DATA_FORMAT 0x0e1a
+-#define mmLB4_LB_DATA_FORMAT_BASE_IDX 2
+-#define mmLB4_LB_MEMORY_CTRL 0x0e1b
+-#define mmLB4_LB_MEMORY_CTRL_BASE_IDX 2
+-#define mmLB4_LB_MEMORY_SIZE_STATUS 0x0e1c
+-#define mmLB4_LB_MEMORY_SIZE_STATUS_BASE_IDX 2
+-#define mmLB4_LB_DESKTOP_HEIGHT 0x0e1d
+-#define mmLB4_LB_DESKTOP_HEIGHT_BASE_IDX 2
+-#define mmLB4_LB_VLINE_START_END 0x0e1e
+-#define mmLB4_LB_VLINE_START_END_BASE_IDX 2
+-#define mmLB4_LB_VLINE2_START_END 0x0e1f
+-#define mmLB4_LB_VLINE2_START_END_BASE_IDX 2
+-#define mmLB4_LB_V_COUNTER 0x0e20
+-#define mmLB4_LB_V_COUNTER_BASE_IDX 2
+-#define mmLB4_LB_SNAPSHOT_V_COUNTER 0x0e21
+-#define mmLB4_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2
+-#define mmLB4_LB_INTERRUPT_MASK 0x0e22
+-#define mmLB4_LB_INTERRUPT_MASK_BASE_IDX 2
+-#define mmLB4_LB_VLINE_STATUS 0x0e23
+-#define mmLB4_LB_VLINE_STATUS_BASE_IDX 2
+-#define mmLB4_LB_VLINE2_STATUS 0x0e24
+-#define mmLB4_LB_VLINE2_STATUS_BASE_IDX 2
+-#define mmLB4_LB_VBLANK_STATUS 0x0e25
+-#define mmLB4_LB_VBLANK_STATUS_BASE_IDX 2
+-#define mmLB4_LB_SYNC_RESET_SEL 0x0e26
+-#define mmLB4_LB_SYNC_RESET_SEL_BASE_IDX 2
+-#define mmLB4_LB_BLACK_KEYER_R_CR 0x0e27
+-#define mmLB4_LB_BLACK_KEYER_R_CR_BASE_IDX 2
+-#define mmLB4_LB_BLACK_KEYER_G_Y 0x0e28
+-#define mmLB4_LB_BLACK_KEYER_G_Y_BASE_IDX 2
+-#define mmLB4_LB_BLACK_KEYER_B_CB 0x0e29
+-#define mmLB4_LB_BLACK_KEYER_B_CB_BASE_IDX 2
+-#define mmLB4_LB_KEYER_COLOR_CTRL 0x0e2a
+-#define mmLB4_LB_KEYER_COLOR_CTRL_BASE_IDX 2
+-#define mmLB4_LB_KEYER_COLOR_R_CR 0x0e2b
+-#define mmLB4_LB_KEYER_COLOR_R_CR_BASE_IDX 2
+-#define mmLB4_LB_KEYER_COLOR_G_Y 0x0e2c
+-#define mmLB4_LB_KEYER_COLOR_G_Y_BASE_IDX 2
+-#define mmLB4_LB_KEYER_COLOR_B_CB 0x0e2d
+-#define mmLB4_LB_KEYER_COLOR_B_CB_BASE_IDX 2
+-#define mmLB4_LB_KEYER_COLOR_REP_R_CR 0x0e2e
+-#define mmLB4_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2
+-#define mmLB4_LB_KEYER_COLOR_REP_G_Y 0x0e2f
+-#define mmLB4_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2
+-#define mmLB4_LB_KEYER_COLOR_REP_B_CB 0x0e30
+-#define mmLB4_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2
+-#define mmLB4_LB_BUFFER_LEVEL_STATUS 0x0e31
+-#define mmLB4_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2
+-#define mmLB4_LB_BUFFER_URGENCY_CTRL 0x0e32
+-#define mmLB4_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2
+-#define mmLB4_LB_BUFFER_URGENCY_STATUS 0x0e33
+-#define mmLB4_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2
+-#define mmLB4_LB_BUFFER_STATUS 0x0e34
+-#define mmLB4_LB_BUFFER_STATUS_BASE_IDX 2
+-#define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0x0e35
+-#define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2
+-#define mmLB4_MVP_AFR_FLIP_MODE 0x0e36
+-#define mmLB4_MVP_AFR_FLIP_MODE_BASE_IDX 2
+-#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0x0e37
+-#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2
+-#define mmLB4_MVP_FLIP_LINE_NUM_INSERT 0x0e38
+-#define mmLB4_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2
+-#define mmLB4_DC_MVP_LB_CONTROL 0x0e39
+-#define mmLB4_DC_MVP_LB_CONTROL_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dcfe4_dispdec
+-// base address: 0x2000
+-#define mmDCFE4_DCFE_CLOCK_CONTROL 0x0e5a
+-#define mmDCFE4_DCFE_CLOCK_CONTROL_BASE_IDX 2
+-#define mmDCFE4_DCFE_SOFT_RESET 0x0e5b
+-#define mmDCFE4_DCFE_SOFT_RESET_BASE_IDX 2
+-#define mmDCFE4_DCFE_MEM_PWR_CTRL 0x0e5d
+-#define mmDCFE4_DCFE_MEM_PWR_CTRL_BASE_IDX 2
+-#define mmDCFE4_DCFE_MEM_PWR_CTRL2 0x0e5e
+-#define mmDCFE4_DCFE_MEM_PWR_CTRL2_BASE_IDX 2
+-#define mmDCFE4_DCFE_MEM_PWR_STATUS 0x0e5f
+-#define mmDCFE4_DCFE_MEM_PWR_STATUS_BASE_IDX 2
+-#define mmDCFE4_DCFE_MISC 0x0e60
+-#define mmDCFE4_DCFE_MISC_BASE_IDX 2
+-#define mmDCFE4_DCFE_FLUSH 0x0e61
+-#define mmDCFE4_DCFE_FLUSH_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dc_perfmon7_dispdec
+-// base address: 0x3938
+-#define mmDC_PERFMON7_PERFCOUNTER_CNTL 0x0e6e
+-#define mmDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX 2
+-#define mmDC_PERFMON7_PERFCOUNTER_CNTL2 0x0e6f
+-#define mmDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX 2
+-#define mmDC_PERFMON7_PERFCOUNTER_STATE 0x0e70
+-#define mmDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX 2
+-#define mmDC_PERFMON7_PERFMON_CNTL 0x0e71
+-#define mmDC_PERFMON7_PERFMON_CNTL_BASE_IDX 2
+-#define mmDC_PERFMON7_PERFMON_CNTL2 0x0e72
+-#define mmDC_PERFMON7_PERFMON_CNTL2_BASE_IDX 2
+-#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x0e73
+-#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+-#define mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x0e74
+-#define mmDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX 2
+-#define mmDC_PERFMON7_PERFMON_HI 0x0e75
+-#define mmDC_PERFMON7_PERFMON_HI_BASE_IDX 2
+-#define mmDC_PERFMON7_PERFMON_LOW 0x0e76
+-#define mmDC_PERFMON7_PERFMON_LOW_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dmif_pg4_dispdec
+-// base address: 0x2000
+-#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 0x0e7a
+-#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
+-#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 0x0e7b
+-#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
+-#define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 0x0e7c
+-#define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2
+-#define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL 0x0e7d
+-#define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2
+-#define mmDMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL 0x0e7e
+-#define mmDMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2
+-#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL 0x0e7f
+-#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2
+-#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL2 0x0e80
+-#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2
+-#define mmDMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL 0x0e81
+-#define mmDMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2
+-#define mmDMIF_PG4_DPG_REPEATER_PROGRAM 0x0e82
+-#define mmDMIF_PG4_DPG_REPEATER_PROGRAM_BASE_IDX 2
+-#define mmDMIF_PG4_DPG_CHK_PRE_PROC_CNTL 0x0e86
+-#define mmDMIF_PG4_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2
+-#define mmDMIF_PG4_DPG_DVMM_STATUS 0x0e87
+-#define mmDMIF_PG4_DPG_DVMM_STATUS_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_scl4_dispdec
+-// base address: 0x2000
+-#define mmSCL4_SCL_COEF_RAM_SELECT 0x0e9a
+-#define mmSCL4_SCL_COEF_RAM_SELECT_BASE_IDX 2
+-#define mmSCL4_SCL_COEF_RAM_TAP_DATA 0x0e9b
+-#define mmSCL4_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
+-#define mmSCL4_SCL_MODE 0x0e9c
+-#define mmSCL4_SCL_MODE_BASE_IDX 2
+-#define mmSCL4_SCL_TAP_CONTROL 0x0e9d
+-#define mmSCL4_SCL_TAP_CONTROL_BASE_IDX 2
+-#define mmSCL4_SCL_CONTROL 0x0e9e
+-#define mmSCL4_SCL_CONTROL_BASE_IDX 2
+-#define mmSCL4_SCL_BYPASS_CONTROL 0x0e9f
+-#define mmSCL4_SCL_BYPASS_CONTROL_BASE_IDX 2
+-#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x0ea0
+-#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
+-#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL 0x0ea1
+-#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2
+-#define mmSCL4_SCL_HORZ_FILTER_CONTROL 0x0ea2
+-#define mmSCL4_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2
+-#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x0ea3
+-#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
+-#define mmSCL4_SCL_HORZ_FILTER_INIT 0x0ea4
+-#define mmSCL4_SCL_HORZ_FILTER_INIT_BASE_IDX 2
+-#define mmSCL4_SCL_VERT_FILTER_CONTROL 0x0ea5
+-#define mmSCL4_SCL_VERT_FILTER_CONTROL_BASE_IDX 2
+-#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x0ea6
+-#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
+-#define mmSCL4_SCL_VERT_FILTER_INIT 0x0ea7
+-#define mmSCL4_SCL_VERT_FILTER_INIT_BASE_IDX 2
+-#define mmSCL4_SCL_VERT_FILTER_INIT_BOT 0x0ea8
+-#define mmSCL4_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
+-#define mmSCL4_SCL_ROUND_OFFSET 0x0ea9
+-#define mmSCL4_SCL_ROUND_OFFSET_BASE_IDX 2
+-#define mmSCL4_SCL_UPDATE 0x0eaa
+-#define mmSCL4_SCL_UPDATE_BASE_IDX 2
+-#define mmSCL4_SCL_F_SHARP_CONTROL 0x0eab
+-#define mmSCL4_SCL_F_SHARP_CONTROL_BASE_IDX 2
+-#define mmSCL4_SCL_ALU_CONTROL 0x0eac
+-#define mmSCL4_SCL_ALU_CONTROL_BASE_IDX 2
+-#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0x0ead
+-#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
+-#define mmSCL4_VIEWPORT_START_SECONDARY 0x0eae
+-#define mmSCL4_VIEWPORT_START_SECONDARY_BASE_IDX 2
+-#define mmSCL4_VIEWPORT_START 0x0eaf
+-#define mmSCL4_VIEWPORT_START_BASE_IDX 2
+-#define mmSCL4_VIEWPORT_SIZE 0x0eb0
+-#define mmSCL4_VIEWPORT_SIZE_BASE_IDX 2
+-#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT 0x0eb1
+-#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
+-#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM 0x0eb2
+-#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
+-#define mmSCL4_SCL_MODE_CHANGE_DET1 0x0eb3
+-#define mmSCL4_SCL_MODE_CHANGE_DET1_BASE_IDX 2
+-#define mmSCL4_SCL_MODE_CHANGE_DET2 0x0eb4
+-#define mmSCL4_SCL_MODE_CHANGE_DET2_BASE_IDX 2
+-#define mmSCL4_SCL_MODE_CHANGE_DET3 0x0eb5
+-#define mmSCL4_SCL_MODE_CHANGE_DET3_BASE_IDX 2
+-#define mmSCL4_SCL_MODE_CHANGE_MASK 0x0eb6
+-#define mmSCL4_SCL_MODE_CHANGE_MASK_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_blnd4_dispdec
+-// base address: 0x2000
+-#define mmBLND4_BLND_CONTROL 0x0ec7
+-#define mmBLND4_BLND_CONTROL_BASE_IDX 2
+-#define mmBLND4_BLND_SM_CONTROL2 0x0ec8
+-#define mmBLND4_BLND_SM_CONTROL2_BASE_IDX 2
+-#define mmBLND4_BLND_CONTROL2 0x0ec9
+-#define mmBLND4_BLND_CONTROL2_BASE_IDX 2
+-#define mmBLND4_BLND_UPDATE 0x0eca
+-#define mmBLND4_BLND_UPDATE_BASE_IDX 2
+-#define mmBLND4_BLND_UNDERFLOW_INTERRUPT 0x0ecb
+-#define mmBLND4_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2
+-#define mmBLND4_BLND_V_UPDATE_LOCK 0x0ecc
+-#define mmBLND4_BLND_V_UPDATE_LOCK_BASE_IDX 2
+-#define mmBLND4_BLND_REG_UPDATE_STATUS 0x0ecd
+-#define mmBLND4_BLND_REG_UPDATE_STATUS_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_crtc4_dispdec
+-// base address: 0x2000
+-#define mmCRTC4_CRTC_H_BLANK_EARLY_NUM 0x0ed2
+-#define mmCRTC4_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2
+-#define mmCRTC4_CRTC_H_TOTAL 0x0ed3
+-#define mmCRTC4_CRTC_H_TOTAL_BASE_IDX 2
+-#define mmCRTC4_CRTC_H_BLANK_START_END 0x0ed4
+-#define mmCRTC4_CRTC_H_BLANK_START_END_BASE_IDX 2
+-#define mmCRTC4_CRTC_H_SYNC_A 0x0ed5
+-#define mmCRTC4_CRTC_H_SYNC_A_BASE_IDX 2
+-#define mmCRTC4_CRTC_H_SYNC_A_CNTL 0x0ed6
+-#define mmCRTC4_CRTC_H_SYNC_A_CNTL_BASE_IDX 2
+-#define mmCRTC4_CRTC_H_SYNC_B 0x0ed7
+-#define mmCRTC4_CRTC_H_SYNC_B_BASE_IDX 2
+-#define mmCRTC4_CRTC_H_SYNC_B_CNTL 0x0ed8
+-#define mmCRTC4_CRTC_H_SYNC_B_CNTL_BASE_IDX 2
+-#define mmCRTC4_CRTC_VBI_END 0x0ed9
+-#define mmCRTC4_CRTC_VBI_END_BASE_IDX 2
+-#define mmCRTC4_CRTC_V_TOTAL 0x0eda
+-#define mmCRTC4_CRTC_V_TOTAL_BASE_IDX 2
+-#define mmCRTC4_CRTC_V_TOTAL_MIN 0x0edb
+-#define mmCRTC4_CRTC_V_TOTAL_MIN_BASE_IDX 2
+-#define mmCRTC4_CRTC_V_TOTAL_MAX 0x0edc
+-#define mmCRTC4_CRTC_V_TOTAL_MAX_BASE_IDX 2
+-#define mmCRTC4_CRTC_V_TOTAL_CONTROL 0x0edd
+-#define mmCRTC4_CRTC_V_TOTAL_CONTROL_BASE_IDX 2
+-#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS 0x0ede
+-#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2
+-#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS 0x0edf
+-#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2
+-#define mmCRTC4_CRTC_V_BLANK_START_END 0x0ee0
+-#define mmCRTC4_CRTC_V_BLANK_START_END_BASE_IDX 2
+-#define mmCRTC4_CRTC_V_SYNC_A 0x0ee1
+-#define mmCRTC4_CRTC_V_SYNC_A_BASE_IDX 2
+-#define mmCRTC4_CRTC_V_SYNC_A_CNTL 0x0ee2
+-#define mmCRTC4_CRTC_V_SYNC_A_CNTL_BASE_IDX 2
+-#define mmCRTC4_CRTC_V_SYNC_B 0x0ee3
+-#define mmCRTC4_CRTC_V_SYNC_B_BASE_IDX 2
+-#define mmCRTC4_CRTC_V_SYNC_B_CNTL 0x0ee4
+-#define mmCRTC4_CRTC_V_SYNC_B_CNTL_BASE_IDX 2
+-#define mmCRTC4_CRTC_DTMTEST_CNTL 0x0ee5
+-#define mmCRTC4_CRTC_DTMTEST_CNTL_BASE_IDX 2
+-#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION 0x0ee6
+-#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2
+-#define mmCRTC4_CRTC_TRIGA_CNTL 0x0ee7
+-#define mmCRTC4_CRTC_TRIGA_CNTL_BASE_IDX 2
+-#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG 0x0ee8
+-#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2
+-#define mmCRTC4_CRTC_TRIGB_CNTL 0x0ee9
+-#define mmCRTC4_CRTC_TRIGB_CNTL_BASE_IDX 2
+-#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG 0x0eea
+-#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2
+-#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL 0x0eeb
+-#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
+-#define mmCRTC4_CRTC_FLOW_CONTROL 0x0eec
+-#define mmCRTC4_CRTC_FLOW_CONTROL_BASE_IDX 2
+-#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE 0x0eed
+-#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
+-#define mmCRTC4_CRTC_AVSYNC_COUNTER 0x0eee
+-#define mmCRTC4_CRTC_AVSYNC_COUNTER_BASE_IDX 2
+-#define mmCRTC4_CRTC_CONTROL 0x0eef
+-#define mmCRTC4_CRTC_CONTROL_BASE_IDX 2
+-#define mmCRTC4_CRTC_BLANK_CONTROL 0x0ef0
+-#define mmCRTC4_CRTC_BLANK_CONTROL_BASE_IDX 2
+-#define mmCRTC4_CRTC_INTERLACE_CONTROL 0x0ef1
+-#define mmCRTC4_CRTC_INTERLACE_CONTROL_BASE_IDX 2
+-#define mmCRTC4_CRTC_INTERLACE_STATUS 0x0ef2
+-#define mmCRTC4_CRTC_INTERLACE_STATUS_BASE_IDX 2
+-#define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL 0x0ef3
+-#define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2
+-#define mmCRTC4_CRTC_PIXEL_DATA_READBACK0 0x0ef4
+-#define mmCRTC4_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2
+-#define mmCRTC4_CRTC_PIXEL_DATA_READBACK1 0x0ef5
+-#define mmCRTC4_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2
+-#define mmCRTC4_CRTC_STATUS 0x0ef6
+-#define mmCRTC4_CRTC_STATUS_BASE_IDX 2
+-#define mmCRTC4_CRTC_STATUS_POSITION 0x0ef7
+-#define mmCRTC4_CRTC_STATUS_POSITION_BASE_IDX 2
+-#define mmCRTC4_CRTC_NOM_VERT_POSITION 0x0ef8
+-#define mmCRTC4_CRTC_NOM_VERT_POSITION_BASE_IDX 2
+-#define mmCRTC4_CRTC_STATUS_FRAME_COUNT 0x0ef9
+-#define mmCRTC4_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2
+-#define mmCRTC4_CRTC_STATUS_VF_COUNT 0x0efa
+-#define mmCRTC4_CRTC_STATUS_VF_COUNT_BASE_IDX 2
+-#define mmCRTC4_CRTC_STATUS_HV_COUNT 0x0efb
+-#define mmCRTC4_CRTC_STATUS_HV_COUNT_BASE_IDX 2
+-#define mmCRTC4_CRTC_COUNT_CONTROL 0x0efc
+-#define mmCRTC4_CRTC_COUNT_CONTROL_BASE_IDX 2
+-#define mmCRTC4_CRTC_COUNT_RESET 0x0efd
+-#define mmCRTC4_CRTC_COUNT_RESET_BASE_IDX 2
+-#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x0efe
+-#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
+-#define mmCRTC4_CRTC_VERT_SYNC_CONTROL 0x0eff
+-#define mmCRTC4_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2
+-#define mmCRTC4_CRTC_STEREO_STATUS 0x0f00
+-#define mmCRTC4_CRTC_STEREO_STATUS_BASE_IDX 2
+-#define mmCRTC4_CRTC_STEREO_CONTROL 0x0f01
+-#define mmCRTC4_CRTC_STEREO_CONTROL_BASE_IDX 2
+-#define mmCRTC4_CRTC_SNAPSHOT_STATUS 0x0f02
+-#define mmCRTC4_CRTC_SNAPSHOT_STATUS_BASE_IDX 2
+-#define mmCRTC4_CRTC_SNAPSHOT_CONTROL 0x0f03
+-#define mmCRTC4_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2
+-#define mmCRTC4_CRTC_SNAPSHOT_POSITION 0x0f04
+-#define mmCRTC4_CRTC_SNAPSHOT_POSITION_BASE_IDX 2
+-#define mmCRTC4_CRTC_SNAPSHOT_FRAME 0x0f05
+-#define mmCRTC4_CRTC_SNAPSHOT_FRAME_BASE_IDX 2
+-#define mmCRTC4_CRTC_START_LINE_CONTROL 0x0f06
+-#define mmCRTC4_CRTC_START_LINE_CONTROL_BASE_IDX 2
+-#define mmCRTC4_CRTC_INTERRUPT_CONTROL 0x0f07
+-#define mmCRTC4_CRTC_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmCRTC4_CRTC_UPDATE_LOCK 0x0f08
+-#define mmCRTC4_CRTC_UPDATE_LOCK_BASE_IDX 2
+-#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL 0x0f09
+-#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
+-#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x0f0a
+-#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2
+-#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL 0x0f0b
+-#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2
+-#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS 0x0f0c
+-#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2
+-#define mmCRTC4_CRTC_TEST_PATTERN_COLOR 0x0f0d
+-#define mmCRTC4_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2
+-#define mmCRTC4_CRTC_MASTER_UPDATE_LOCK 0x0f0e
+-#define mmCRTC4_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2
+-#define mmCRTC4_CRTC_MASTER_UPDATE_MODE 0x0f0f
+-#define mmCRTC4_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2
+-#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT 0x0f10
+-#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2
+-#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x0f11
+-#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2
+-#define mmCRTC4_CRTC_MVP_STATUS 0x0f12
+-#define mmCRTC4_CRTC_MVP_STATUS_BASE_IDX 2
+-#define mmCRTC4_CRTC_MASTER_EN 0x0f13
+-#define mmCRTC4_CRTC_MASTER_EN_BASE_IDX 2
+-#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT 0x0f14
+-#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2
+-#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS 0x0f15
+-#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2
+-#define mmCRTC4_CRTC_OVERSCAN_COLOR 0x0f17
+-#define mmCRTC4_CRTC_OVERSCAN_COLOR_BASE_IDX 2
+-#define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT 0x0f18
+-#define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2
+-#define mmCRTC4_CRTC_BLANK_DATA_COLOR 0x0f19
+-#define mmCRTC4_CRTC_BLANK_DATA_COLOR_BASE_IDX 2
+-#define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT 0x0f1a
+-#define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2
+-#define mmCRTC4_CRTC_BLACK_COLOR 0x0f1b
+-#define mmCRTC4_CRTC_BLACK_COLOR_BASE_IDX 2
+-#define mmCRTC4_CRTC_BLACK_COLOR_EXT 0x0f1c
+-#define mmCRTC4_CRTC_BLACK_COLOR_EXT_BASE_IDX 2
+-#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION 0x0f1d
+-#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
+-#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x0f1e
+-#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
+-#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION 0x0f1f
+-#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
+-#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x0f20
+-#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
+-#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION 0x0f21
+-#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
+-#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x0f22
+-#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
+-#define mmCRTC4_CRTC_CRC_CNTL 0x0f23
+-#define mmCRTC4_CRTC_CRC_CNTL_BASE_IDX 2
+-#define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL 0x0f24
+-#define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
+-#define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL 0x0f25
+-#define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
+-#define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL 0x0f26
+-#define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
+-#define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL 0x0f27
+-#define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
+-#define mmCRTC4_CRTC_CRC0_DATA_RG 0x0f28
+-#define mmCRTC4_CRTC_CRC0_DATA_RG_BASE_IDX 2
+-#define mmCRTC4_CRTC_CRC0_DATA_B 0x0f29
+-#define mmCRTC4_CRTC_CRC0_DATA_B_BASE_IDX 2
+-#define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL 0x0f2a
+-#define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
+-#define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL 0x0f2b
+-#define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
+-#define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL 0x0f2c
+-#define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
+-#define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL 0x0f2d
+-#define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
+-#define mmCRTC4_CRTC_CRC1_DATA_RG 0x0f2e
+-#define mmCRTC4_CRTC_CRC1_DATA_RG_BASE_IDX 2
+-#define mmCRTC4_CRTC_CRC1_DATA_B 0x0f2f
+-#define mmCRTC4_CRTC_CRC1_DATA_B_BASE_IDX 2
+-#define mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL 0x0f30
+-#define mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2
+-#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x0f31
+-#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2
+-#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x0f32
+-#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2
+-#define mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x0f33
+-#define mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x0f34
+-#define mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x0f35
+-#define mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL 0x0f36
+-#define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2
+-#define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL 0x0f37
+-#define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2
+-#define mmCRTC4_CRTC_GSL_VSYNC_GAP 0x0f38
+-#define mmCRTC4_CRTC_GSL_VSYNC_GAP_BASE_IDX 2
+-#define mmCRTC4_CRTC_GSL_WINDOW 0x0f39
+-#define mmCRTC4_CRTC_GSL_WINDOW_BASE_IDX 2
+-#define mmCRTC4_CRTC_GSL_CONTROL 0x0f3a
+-#define mmCRTC4_CRTC_GSL_CONTROL_BASE_IDX 2
+-#define mmCRTC4_CRTC_RANGE_TIMING_INT_STATUS 0x0f3d
+-#define mmCRTC4_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2
+-#define mmCRTC4_CRTC_DRR_CONTROL 0x0f3e
+-#define mmCRTC4_CRTC_DRR_CONTROL_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_fmt4_dispdec
+-// base address: 0x2000
+-#define mmFMT4_FMT_CLAMP_COMPONENT_R 0x0f42
+-#define mmFMT4_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
+-#define mmFMT4_FMT_CLAMP_COMPONENT_G 0x0f43
+-#define mmFMT4_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
+-#define mmFMT4_FMT_CLAMP_COMPONENT_B 0x0f44
+-#define mmFMT4_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
+-#define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x0f45
+-#define mmFMT4_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
+-#define mmFMT4_FMT_CONTROL 0x0f46
+-#define mmFMT4_FMT_CONTROL_BASE_IDX 2
+-#define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x0f47
+-#define mmFMT4_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
+-#define mmFMT4_FMT_DITHER_RAND_R_SEED 0x0f48
+-#define mmFMT4_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
+-#define mmFMT4_FMT_DITHER_RAND_G_SEED 0x0f49
+-#define mmFMT4_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
+-#define mmFMT4_FMT_DITHER_RAND_B_SEED 0x0f4a
+-#define mmFMT4_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
+-#define mmFMT4_FMT_CLAMP_CNTL 0x0f4e
+-#define mmFMT4_FMT_CLAMP_CNTL_BASE_IDX 2
+-#define mmFMT4_FMT_CRC_CNTL 0x0f4f
+-#define mmFMT4_FMT_CRC_CNTL_BASE_IDX 2
+-#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK 0x0f50
+-#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
+-#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x0f51
+-#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
+-#define mmFMT4_FMT_CRC_SIG_RED_GREEN 0x0f52
+-#define mmFMT4_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2
+-#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL 0x0f53
+-#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2
+-#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x0f54
+-#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
+-#define mmFMT4_FMT_420_HBLANK_EARLY_START 0x0f55
+-#define mmFMT4_FMT_420_HBLANK_EARLY_START_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dcp5_dispdec
+-// base address: 0x2800
+-#define mmDCP5_GRPH_ENABLE 0x0f5a
+-#define mmDCP5_GRPH_ENABLE_BASE_IDX 2
+-#define mmDCP5_GRPH_CONTROL 0x0f5b
+-#define mmDCP5_GRPH_CONTROL_BASE_IDX 2
+-#define mmDCP5_GRPH_LUT_10BIT_BYPASS 0x0f5c
+-#define mmDCP5_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2
+-#define mmDCP5_GRPH_SWAP_CNTL 0x0f5d
+-#define mmDCP5_GRPH_SWAP_CNTL_BASE_IDX 2
+-#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS 0x0f5e
+-#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
+-#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS 0x0f5f
+-#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
+-#define mmDCP5_GRPH_PITCH 0x0f60
+-#define mmDCP5_GRPH_PITCH_BASE_IDX 2
+-#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0f61
+-#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+-#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0f62
+-#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+-#define mmDCP5_GRPH_SURFACE_OFFSET_X 0x0f63
+-#define mmDCP5_GRPH_SURFACE_OFFSET_X_BASE_IDX 2
+-#define mmDCP5_GRPH_SURFACE_OFFSET_Y 0x0f64
+-#define mmDCP5_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2
+-#define mmDCP5_GRPH_X_START 0x0f65
+-#define mmDCP5_GRPH_X_START_BASE_IDX 2
+-#define mmDCP5_GRPH_Y_START 0x0f66
+-#define mmDCP5_GRPH_Y_START_BASE_IDX 2
+-#define mmDCP5_GRPH_X_END 0x0f67
+-#define mmDCP5_GRPH_X_END_BASE_IDX 2
+-#define mmDCP5_GRPH_Y_END 0x0f68
+-#define mmDCP5_GRPH_Y_END_BASE_IDX 2
+-#define mmDCP5_INPUT_GAMMA_CONTROL 0x0f69
+-#define mmDCP5_INPUT_GAMMA_CONTROL_BASE_IDX 2
+-#define mmDCP5_GRPH_UPDATE 0x0f6a
+-#define mmDCP5_GRPH_UPDATE_BASE_IDX 2
+-#define mmDCP5_GRPH_FLIP_CONTROL 0x0f6b
+-#define mmDCP5_GRPH_FLIP_CONTROL_BASE_IDX 2
+-#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE 0x0f6c
+-#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2
+-#define mmDCP5_GRPH_DFQ_CONTROL 0x0f6d
+-#define mmDCP5_GRPH_DFQ_CONTROL_BASE_IDX 2
+-#define mmDCP5_GRPH_DFQ_STATUS 0x0f6e
+-#define mmDCP5_GRPH_DFQ_STATUS_BASE_IDX 2
+-#define mmDCP5_GRPH_INTERRUPT_STATUS 0x0f6f
+-#define mmDCP5_GRPH_INTERRUPT_STATUS_BASE_IDX 2
+-#define mmDCP5_GRPH_INTERRUPT_CONTROL 0x0f70
+-#define mmDCP5_GRPH_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0f71
+-#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2
+-#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS 0x0f72
+-#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2
+-#define mmDCP5_GRPH_COMPRESS_PITCH 0x0f73
+-#define mmDCP5_GRPH_COMPRESS_PITCH_BASE_IDX 2
+-#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0f74
+-#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+-#define mmDCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0f75
+-#define mmDCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2
+-#define mmDCP5_PRESCALE_GRPH_CONTROL 0x0f76
+-#define mmDCP5_PRESCALE_GRPH_CONTROL_BASE_IDX 2
+-#define mmDCP5_PRESCALE_VALUES_GRPH_R 0x0f77
+-#define mmDCP5_PRESCALE_VALUES_GRPH_R_BASE_IDX 2
+-#define mmDCP5_PRESCALE_VALUES_GRPH_G 0x0f78
+-#define mmDCP5_PRESCALE_VALUES_GRPH_G_BASE_IDX 2
+-#define mmDCP5_PRESCALE_VALUES_GRPH_B 0x0f79
+-#define mmDCP5_PRESCALE_VALUES_GRPH_B_BASE_IDX 2
+-#define mmDCP5_INPUT_CSC_CONTROL 0x0f7a
+-#define mmDCP5_INPUT_CSC_CONTROL_BASE_IDX 2
+-#define mmDCP5_INPUT_CSC_C11_C12 0x0f7b
+-#define mmDCP5_INPUT_CSC_C11_C12_BASE_IDX 2
+-#define mmDCP5_INPUT_CSC_C13_C14 0x0f7c
+-#define mmDCP5_INPUT_CSC_C13_C14_BASE_IDX 2
+-#define mmDCP5_INPUT_CSC_C21_C22 0x0f7d
+-#define mmDCP5_INPUT_CSC_C21_C22_BASE_IDX 2
+-#define mmDCP5_INPUT_CSC_C23_C24 0x0f7e
+-#define mmDCP5_INPUT_CSC_C23_C24_BASE_IDX 2
+-#define mmDCP5_INPUT_CSC_C31_C32 0x0f7f
+-#define mmDCP5_INPUT_CSC_C31_C32_BASE_IDX 2
+-#define mmDCP5_INPUT_CSC_C33_C34 0x0f80
+-#define mmDCP5_INPUT_CSC_C33_C34_BASE_IDX 2
+-#define mmDCP5_OUTPUT_CSC_CONTROL 0x0f81
+-#define mmDCP5_OUTPUT_CSC_CONTROL_BASE_IDX 2
+-#define mmDCP5_OUTPUT_CSC_C11_C12 0x0f82
+-#define mmDCP5_OUTPUT_CSC_C11_C12_BASE_IDX 2
+-#define mmDCP5_OUTPUT_CSC_C13_C14 0x0f83
+-#define mmDCP5_OUTPUT_CSC_C13_C14_BASE_IDX 2
+-#define mmDCP5_OUTPUT_CSC_C21_C22 0x0f84
+-#define mmDCP5_OUTPUT_CSC_C21_C22_BASE_IDX 2
+-#define mmDCP5_OUTPUT_CSC_C23_C24 0x0f85
+-#define mmDCP5_OUTPUT_CSC_C23_C24_BASE_IDX 2
+-#define mmDCP5_OUTPUT_CSC_C31_C32 0x0f86
+-#define mmDCP5_OUTPUT_CSC_C31_C32_BASE_IDX 2
+-#define mmDCP5_OUTPUT_CSC_C33_C34 0x0f87
+-#define mmDCP5_OUTPUT_CSC_C33_C34_BASE_IDX 2
+-#define mmDCP5_COMM_MATRIXA_TRANS_C11_C12 0x0f88
+-#define mmDCP5_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2
+-#define mmDCP5_COMM_MATRIXA_TRANS_C13_C14 0x0f89
+-#define mmDCP5_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2
+-#define mmDCP5_COMM_MATRIXA_TRANS_C21_C22 0x0f8a
+-#define mmDCP5_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2
+-#define mmDCP5_COMM_MATRIXA_TRANS_C23_C24 0x0f8b
+-#define mmDCP5_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2
+-#define mmDCP5_COMM_MATRIXA_TRANS_C31_C32 0x0f8c
+-#define mmDCP5_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2
+-#define mmDCP5_COMM_MATRIXA_TRANS_C33_C34 0x0f8d
+-#define mmDCP5_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2
+-#define mmDCP5_COMM_MATRIXB_TRANS_C11_C12 0x0f8e
+-#define mmDCP5_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2
+-#define mmDCP5_COMM_MATRIXB_TRANS_C13_C14 0x0f8f
+-#define mmDCP5_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2
+-#define mmDCP5_COMM_MATRIXB_TRANS_C21_C22 0x0f90
+-#define mmDCP5_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2
+-#define mmDCP5_COMM_MATRIXB_TRANS_C23_C24 0x0f91
+-#define mmDCP5_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2
+-#define mmDCP5_COMM_MATRIXB_TRANS_C31_C32 0x0f92
+-#define mmDCP5_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2
+-#define mmDCP5_COMM_MATRIXB_TRANS_C33_C34 0x0f93
+-#define mmDCP5_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2
+-#define mmDCP5_DENORM_CONTROL 0x0f94
+-#define mmDCP5_DENORM_CONTROL_BASE_IDX 2
+-#define mmDCP5_OUT_ROUND_CONTROL 0x0f95
+-#define mmDCP5_OUT_ROUND_CONTROL_BASE_IDX 2
+-#define mmDCP5_OUT_CLAMP_CONTROL_R_CR 0x0f96
+-#define mmDCP5_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2
+-#define mmDCP5_OUT_CLAMP_CONTROL_G_Y 0x0f97
+-#define mmDCP5_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2
+-#define mmDCP5_OUT_CLAMP_CONTROL_B_CB 0x0f98
+-#define mmDCP5_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2
+-#define mmDCP5_KEY_CONTROL 0x0f99
+-#define mmDCP5_KEY_CONTROL_BASE_IDX 2
+-#define mmDCP5_KEY_RANGE_ALPHA 0x0f9a
+-#define mmDCP5_KEY_RANGE_ALPHA_BASE_IDX 2
+-#define mmDCP5_KEY_RANGE_RED 0x0f9b
+-#define mmDCP5_KEY_RANGE_RED_BASE_IDX 2
+-#define mmDCP5_KEY_RANGE_GREEN 0x0f9c
+-#define mmDCP5_KEY_RANGE_GREEN_BASE_IDX 2
+-#define mmDCP5_KEY_RANGE_BLUE 0x0f9d
+-#define mmDCP5_KEY_RANGE_BLUE_BASE_IDX 2
+-#define mmDCP5_DEGAMMA_CONTROL 0x0f9e
+-#define mmDCP5_DEGAMMA_CONTROL_BASE_IDX 2
+-#define mmDCP5_GAMUT_REMAP_CONTROL 0x0f9f
+-#define mmDCP5_GAMUT_REMAP_CONTROL_BASE_IDX 2
+-#define mmDCP5_GAMUT_REMAP_C11_C12 0x0fa0
+-#define mmDCP5_GAMUT_REMAP_C11_C12_BASE_IDX 2
+-#define mmDCP5_GAMUT_REMAP_C13_C14 0x0fa1
+-#define mmDCP5_GAMUT_REMAP_C13_C14_BASE_IDX 2
+-#define mmDCP5_GAMUT_REMAP_C21_C22 0x0fa2
+-#define mmDCP5_GAMUT_REMAP_C21_C22_BASE_IDX 2
+-#define mmDCP5_GAMUT_REMAP_C23_C24 0x0fa3
+-#define mmDCP5_GAMUT_REMAP_C23_C24_BASE_IDX 2
+-#define mmDCP5_GAMUT_REMAP_C31_C32 0x0fa4
+-#define mmDCP5_GAMUT_REMAP_C31_C32_BASE_IDX 2
+-#define mmDCP5_GAMUT_REMAP_C33_C34 0x0fa5
+-#define mmDCP5_GAMUT_REMAP_C33_C34_BASE_IDX 2
+-#define mmDCP5_DCP_SPATIAL_DITHER_CNTL 0x0fa6
+-#define mmDCP5_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2
+-#define mmDCP5_DCP_RANDOM_SEEDS 0x0fa7
+-#define mmDCP5_DCP_RANDOM_SEEDS_BASE_IDX 2
+-#define mmDCP5_DCP_FP_CONVERTED_FIELD 0x0fa8
+-#define mmDCP5_DCP_FP_CONVERTED_FIELD_BASE_IDX 2
+-#define mmDCP5_CUR_CONTROL 0x0fa9
+-#define mmDCP5_CUR_CONTROL_BASE_IDX 2
+-#define mmDCP5_CUR_SURFACE_ADDRESS 0x0faa
+-#define mmDCP5_CUR_SURFACE_ADDRESS_BASE_IDX 2
+-#define mmDCP5_CUR_SIZE 0x0fab
+-#define mmDCP5_CUR_SIZE_BASE_IDX 2
+-#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH 0x0fac
+-#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+-#define mmDCP5_CUR_POSITION 0x0fad
+-#define mmDCP5_CUR_POSITION_BASE_IDX 2
+-#define mmDCP5_CUR_HOT_SPOT 0x0fae
+-#define mmDCP5_CUR_HOT_SPOT_BASE_IDX 2
+-#define mmDCP5_CUR_COLOR1 0x0faf
+-#define mmDCP5_CUR_COLOR1_BASE_IDX 2
+-#define mmDCP5_CUR_COLOR2 0x0fb0
+-#define mmDCP5_CUR_COLOR2_BASE_IDX 2
+-#define mmDCP5_CUR_UPDATE 0x0fb1
+-#define mmDCP5_CUR_UPDATE_BASE_IDX 2
+-#define mmDCP5_CUR_REQUEST_FILTER_CNTL 0x0fbb
+-#define mmDCP5_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2
+-#define mmDCP5_CUR_STEREO_CONTROL 0x0fbc
+-#define mmDCP5_CUR_STEREO_CONTROL_BASE_IDX 2
+-#define mmDCP5_DC_LUT_RW_MODE 0x0fbe
+-#define mmDCP5_DC_LUT_RW_MODE_BASE_IDX 2
+-#define mmDCP5_DC_LUT_RW_INDEX 0x0fbf
+-#define mmDCP5_DC_LUT_RW_INDEX_BASE_IDX 2
+-#define mmDCP5_DC_LUT_SEQ_COLOR 0x0fc0
+-#define mmDCP5_DC_LUT_SEQ_COLOR_BASE_IDX 2
+-#define mmDCP5_DC_LUT_PWL_DATA 0x0fc1
+-#define mmDCP5_DC_LUT_PWL_DATA_BASE_IDX 2
+-#define mmDCP5_DC_LUT_30_COLOR 0x0fc2
+-#define mmDCP5_DC_LUT_30_COLOR_BASE_IDX 2
+-#define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE 0x0fc3
+-#define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2
+-#define mmDCP5_DC_LUT_WRITE_EN_MASK 0x0fc4
+-#define mmDCP5_DC_LUT_WRITE_EN_MASK_BASE_IDX 2
+-#define mmDCP5_DC_LUT_AUTOFILL 0x0fc5
+-#define mmDCP5_DC_LUT_AUTOFILL_BASE_IDX 2
+-#define mmDCP5_DC_LUT_CONTROL 0x0fc6
+-#define mmDCP5_DC_LUT_CONTROL_BASE_IDX 2
+-#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE 0x0fc7
+-#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2
+-#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN 0x0fc8
+-#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2
+-#define mmDCP5_DC_LUT_BLACK_OFFSET_RED 0x0fc9
+-#define mmDCP5_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2
+-#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE 0x0fca
+-#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2
+-#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN 0x0fcb
+-#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2
+-#define mmDCP5_DC_LUT_WHITE_OFFSET_RED 0x0fcc
+-#define mmDCP5_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2
+-#define mmDCP5_DCP_CRC_CONTROL 0x0fcd
+-#define mmDCP5_DCP_CRC_CONTROL_BASE_IDX 2
+-#define mmDCP5_DCP_CRC_MASK 0x0fce
+-#define mmDCP5_DCP_CRC_MASK_BASE_IDX 2
+-#define mmDCP5_DCP_CRC_CURRENT 0x0fcf
+-#define mmDCP5_DCP_CRC_CURRENT_BASE_IDX 2
+-#define mmDCP5_DVMM_PTE_CONTROL 0x0fd0
+-#define mmDCP5_DVMM_PTE_CONTROL_BASE_IDX 2
+-#define mmDCP5_DCP_CRC_LAST 0x0fd1
+-#define mmDCP5_DCP_CRC_LAST_BASE_IDX 2
+-#define mmDCP5_DVMM_PTE_ARB_CONTROL 0x0fd2
+-#define mmDCP5_DVMM_PTE_ARB_CONTROL_BASE_IDX 2
+-#define mmDCP5_GRPH_FLIP_RATE_CNTL 0x0fd4
+-#define mmDCP5_GRPH_FLIP_RATE_CNTL_BASE_IDX 2
+-#define mmDCP5_DCP_GSL_CONTROL 0x0fd5
+-#define mmDCP5_DCP_GSL_CONTROL_BASE_IDX 2
+-#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x0fd6
+-#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2
+-#define mmDCP5_GRPH_STEREOSYNC_FLIP 0x0fdc
+-#define mmDCP5_GRPH_STEREOSYNC_FLIP_BASE_IDX 2
+-#define mmDCP5_HW_ROTATION 0x0fde
+-#define mmDCP5_HW_ROTATION_BASE_IDX 2
+-#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x0fdf
+-#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2
+-#define mmDCP5_REGAMMA_CONTROL 0x0fe0
+-#define mmDCP5_REGAMMA_CONTROL_BASE_IDX 2
+-#define mmDCP5_REGAMMA_LUT_INDEX 0x0fe1
+-#define mmDCP5_REGAMMA_LUT_INDEX_BASE_IDX 2
+-#define mmDCP5_REGAMMA_LUT_DATA 0x0fe2
+-#define mmDCP5_REGAMMA_LUT_DATA_BASE_IDX 2
+-#define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK 0x0fe3
+-#define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2
+-#define mmDCP5_REGAMMA_CNTLA_START_CNTL 0x0fe4
+-#define mmDCP5_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2
+-#define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL 0x0fe5
+-#define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2
+-#define mmDCP5_REGAMMA_CNTLA_END_CNTL1 0x0fe6
+-#define mmDCP5_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2
+-#define mmDCP5_REGAMMA_CNTLA_END_CNTL2 0x0fe7
+-#define mmDCP5_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2
+-#define mmDCP5_REGAMMA_CNTLA_REGION_0_1 0x0fe8
+-#define mmDCP5_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2
+-#define mmDCP5_REGAMMA_CNTLA_REGION_2_3 0x0fe9
+-#define mmDCP5_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2
+-#define mmDCP5_REGAMMA_CNTLA_REGION_4_5 0x0fea
+-#define mmDCP5_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2
+-#define mmDCP5_REGAMMA_CNTLA_REGION_6_7 0x0feb
+-#define mmDCP5_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2
+-#define mmDCP5_REGAMMA_CNTLA_REGION_8_9 0x0fec
+-#define mmDCP5_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2
+-#define mmDCP5_REGAMMA_CNTLA_REGION_10_11 0x0fed
+-#define mmDCP5_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2
+-#define mmDCP5_REGAMMA_CNTLA_REGION_12_13 0x0fee
+-#define mmDCP5_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2
+-#define mmDCP5_REGAMMA_CNTLA_REGION_14_15 0x0fef
+-#define mmDCP5_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2
+-#define mmDCP5_REGAMMA_CNTLB_START_CNTL 0x0ff0
+-#define mmDCP5_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2
+-#define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL 0x0ff1
+-#define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2
+-#define mmDCP5_REGAMMA_CNTLB_END_CNTL1 0x0ff2
+-#define mmDCP5_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2
+-#define mmDCP5_REGAMMA_CNTLB_END_CNTL2 0x0ff3
+-#define mmDCP5_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2
+-#define mmDCP5_REGAMMA_CNTLB_REGION_0_1 0x0ff4
+-#define mmDCP5_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2
+-#define mmDCP5_REGAMMA_CNTLB_REGION_2_3 0x0ff5
+-#define mmDCP5_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2
+-#define mmDCP5_REGAMMA_CNTLB_REGION_4_5 0x0ff6
+-#define mmDCP5_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2
+-#define mmDCP5_REGAMMA_CNTLB_REGION_6_7 0x0ff7
+-#define mmDCP5_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2
+-#define mmDCP5_REGAMMA_CNTLB_REGION_8_9 0x0ff8
+-#define mmDCP5_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2
+-#define mmDCP5_REGAMMA_CNTLB_REGION_10_11 0x0ff9
+-#define mmDCP5_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2
+-#define mmDCP5_REGAMMA_CNTLB_REGION_12_13 0x0ffa
+-#define mmDCP5_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2
+-#define mmDCP5_REGAMMA_CNTLB_REGION_14_15 0x0ffb
+-#define mmDCP5_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2
+-#define mmDCP5_ALPHA_CONTROL 0x0ffc
+-#define mmDCP5_ALPHA_CONTROL_BASE_IDX 2
+-#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x0ffd
+-#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2
+-#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x0ffe
+-#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+-#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x0fff
+-#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2
+-#define mmDCP5_GRPH_XDMA_FLIP_TIMEOUT 0x1000
+-#define mmDCP5_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2
+-#define mmDCP5_GRPH_XDMA_FLIP_AVG_DELAY 0x1001
+-#define mmDCP5_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2
+-#define mmDCP5_GRPH_SURFACE_COUNTER_CONTROL 0x1002
+-#define mmDCP5_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2
+-#define mmDCP5_GRPH_SURFACE_COUNTER_OUTPUT 0x1003
+-#define mmDCP5_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_lb5_dispdec
+-// base address: 0x2800
+-#define mmLB5_LB_DATA_FORMAT 0x101a
+-#define mmLB5_LB_DATA_FORMAT_BASE_IDX 2
+-#define mmLB5_LB_MEMORY_CTRL 0x101b
+-#define mmLB5_LB_MEMORY_CTRL_BASE_IDX 2
+-#define mmLB5_LB_MEMORY_SIZE_STATUS 0x101c
+-#define mmLB5_LB_MEMORY_SIZE_STATUS_BASE_IDX 2
+-#define mmLB5_LB_DESKTOP_HEIGHT 0x101d
+-#define mmLB5_LB_DESKTOP_HEIGHT_BASE_IDX 2
+-#define mmLB5_LB_VLINE_START_END 0x101e
+-#define mmLB5_LB_VLINE_START_END_BASE_IDX 2
+-#define mmLB5_LB_VLINE2_START_END 0x101f
+-#define mmLB5_LB_VLINE2_START_END_BASE_IDX 2
+-#define mmLB5_LB_V_COUNTER 0x1020
+-#define mmLB5_LB_V_COUNTER_BASE_IDX 2
+-#define mmLB5_LB_SNAPSHOT_V_COUNTER 0x1021
+-#define mmLB5_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2
+-#define mmLB5_LB_INTERRUPT_MASK 0x1022
+-#define mmLB5_LB_INTERRUPT_MASK_BASE_IDX 2
+-#define mmLB5_LB_VLINE_STATUS 0x1023
+-#define mmLB5_LB_VLINE_STATUS_BASE_IDX 2
+-#define mmLB5_LB_VLINE2_STATUS 0x1024
+-#define mmLB5_LB_VLINE2_STATUS_BASE_IDX 2
+-#define mmLB5_LB_VBLANK_STATUS 0x1025
+-#define mmLB5_LB_VBLANK_STATUS_BASE_IDX 2
+-#define mmLB5_LB_SYNC_RESET_SEL 0x1026
+-#define mmLB5_LB_SYNC_RESET_SEL_BASE_IDX 2
+-#define mmLB5_LB_BLACK_KEYER_R_CR 0x1027
+-#define mmLB5_LB_BLACK_KEYER_R_CR_BASE_IDX 2
+-#define mmLB5_LB_BLACK_KEYER_G_Y 0x1028
+-#define mmLB5_LB_BLACK_KEYER_G_Y_BASE_IDX 2
+-#define mmLB5_LB_BLACK_KEYER_B_CB 0x1029
+-#define mmLB5_LB_BLACK_KEYER_B_CB_BASE_IDX 2
+-#define mmLB5_LB_KEYER_COLOR_CTRL 0x102a
+-#define mmLB5_LB_KEYER_COLOR_CTRL_BASE_IDX 2
+-#define mmLB5_LB_KEYER_COLOR_R_CR 0x102b
+-#define mmLB5_LB_KEYER_COLOR_R_CR_BASE_IDX 2
+-#define mmLB5_LB_KEYER_COLOR_G_Y 0x102c
+-#define mmLB5_LB_KEYER_COLOR_G_Y_BASE_IDX 2
+-#define mmLB5_LB_KEYER_COLOR_B_CB 0x102d
+-#define mmLB5_LB_KEYER_COLOR_B_CB_BASE_IDX 2
+-#define mmLB5_LB_KEYER_COLOR_REP_R_CR 0x102e
+-#define mmLB5_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2
+-#define mmLB5_LB_KEYER_COLOR_REP_G_Y 0x102f
+-#define mmLB5_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2
+-#define mmLB5_LB_KEYER_COLOR_REP_B_CB 0x1030
+-#define mmLB5_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2
+-#define mmLB5_LB_BUFFER_LEVEL_STATUS 0x1031
+-#define mmLB5_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2
+-#define mmLB5_LB_BUFFER_URGENCY_CTRL 0x1032
+-#define mmLB5_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2
+-#define mmLB5_LB_BUFFER_URGENCY_STATUS 0x1033
+-#define mmLB5_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2
+-#define mmLB5_LB_BUFFER_STATUS 0x1034
+-#define mmLB5_LB_BUFFER_STATUS_BASE_IDX 2
+-#define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0x1035
+-#define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2
+-#define mmLB5_MVP_AFR_FLIP_MODE 0x1036
+-#define mmLB5_MVP_AFR_FLIP_MODE_BASE_IDX 2
+-#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0x1037
+-#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2
+-#define mmLB5_MVP_FLIP_LINE_NUM_INSERT 0x1038
+-#define mmLB5_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2
+-#define mmLB5_DC_MVP_LB_CONTROL 0x1039
+-#define mmLB5_DC_MVP_LB_CONTROL_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dcfe5_dispdec
+-// base address: 0x2800
+-#define mmDCFE5_DCFE_CLOCK_CONTROL 0x105a
+-#define mmDCFE5_DCFE_CLOCK_CONTROL_BASE_IDX 2
+-#define mmDCFE5_DCFE_SOFT_RESET 0x105b
+-#define mmDCFE5_DCFE_SOFT_RESET_BASE_IDX 2
+-#define mmDCFE5_DCFE_MEM_PWR_CTRL 0x105d
+-#define mmDCFE5_DCFE_MEM_PWR_CTRL_BASE_IDX 2
+-#define mmDCFE5_DCFE_MEM_PWR_CTRL2 0x105e
+-#define mmDCFE5_DCFE_MEM_PWR_CTRL2_BASE_IDX 2
+-#define mmDCFE5_DCFE_MEM_PWR_STATUS 0x105f
+-#define mmDCFE5_DCFE_MEM_PWR_STATUS_BASE_IDX 2
+-#define mmDCFE5_DCFE_MISC 0x1060
+-#define mmDCFE5_DCFE_MISC_BASE_IDX 2
+-#define mmDCFE5_DCFE_FLUSH 0x1061
+-#define mmDCFE5_DCFE_FLUSH_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dc_perfmon8_dispdec
+-// base address: 0x4138
+-#define mmDC_PERFMON8_PERFCOUNTER_CNTL 0x106e
+-#define mmDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX 2
+-#define mmDC_PERFMON8_PERFCOUNTER_CNTL2 0x106f
+-#define mmDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX 2
+-#define mmDC_PERFMON8_PERFCOUNTER_STATE 0x1070
+-#define mmDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX 2
+-#define mmDC_PERFMON8_PERFMON_CNTL 0x1071
+-#define mmDC_PERFMON8_PERFMON_CNTL_BASE_IDX 2
+-#define mmDC_PERFMON8_PERFMON_CNTL2 0x1072
+-#define mmDC_PERFMON8_PERFMON_CNTL2_BASE_IDX 2
+-#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x1073
+-#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+-#define mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x1074
+-#define mmDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX 2
+-#define mmDC_PERFMON8_PERFMON_HI 0x1075
+-#define mmDC_PERFMON8_PERFMON_HI_BASE_IDX 2
+-#define mmDC_PERFMON8_PERFMON_LOW 0x1076
+-#define mmDC_PERFMON8_PERFMON_LOW_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dmif_pg5_dispdec
+-// base address: 0x2800
+-#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 0x107a
+-#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
+-#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 0x107b
+-#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
+-#define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 0x107c
+-#define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2
+-#define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL 0x107d
+-#define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2
+-#define mmDMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL 0x107e
+-#define mmDMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2
+-#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL 0x107f
+-#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2
+-#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL2 0x1080
+-#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2
+-#define mmDMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL 0x1081
+-#define mmDMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2
+-#define mmDMIF_PG5_DPG_REPEATER_PROGRAM 0x1082
+-#define mmDMIF_PG5_DPG_REPEATER_PROGRAM_BASE_IDX 2
+-#define mmDMIF_PG5_DPG_CHK_PRE_PROC_CNTL 0x1086
+-#define mmDMIF_PG5_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2
+-#define mmDMIF_PG5_DPG_DVMM_STATUS 0x1087
+-#define mmDMIF_PG5_DPG_DVMM_STATUS_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_scl5_dispdec
+-// base address: 0x2800
+-#define mmSCL5_SCL_COEF_RAM_SELECT 0x109a
+-#define mmSCL5_SCL_COEF_RAM_SELECT_BASE_IDX 2
+-#define mmSCL5_SCL_COEF_RAM_TAP_DATA 0x109b
+-#define mmSCL5_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
+-#define mmSCL5_SCL_MODE 0x109c
+-#define mmSCL5_SCL_MODE_BASE_IDX 2
+-#define mmSCL5_SCL_TAP_CONTROL 0x109d
+-#define mmSCL5_SCL_TAP_CONTROL_BASE_IDX 2
+-#define mmSCL5_SCL_CONTROL 0x109e
+-#define mmSCL5_SCL_CONTROL_BASE_IDX 2
+-#define mmSCL5_SCL_BYPASS_CONTROL 0x109f
+-#define mmSCL5_SCL_BYPASS_CONTROL_BASE_IDX 2
+-#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x10a0
+-#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
+-#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL 0x10a1
+-#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2
+-#define mmSCL5_SCL_HORZ_FILTER_CONTROL 0x10a2
+-#define mmSCL5_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2
+-#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x10a3
+-#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
+-#define mmSCL5_SCL_HORZ_FILTER_INIT 0x10a4
+-#define mmSCL5_SCL_HORZ_FILTER_INIT_BASE_IDX 2
+-#define mmSCL5_SCL_VERT_FILTER_CONTROL 0x10a5
+-#define mmSCL5_SCL_VERT_FILTER_CONTROL_BASE_IDX 2
+-#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x10a6
+-#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
+-#define mmSCL5_SCL_VERT_FILTER_INIT 0x10a7
+-#define mmSCL5_SCL_VERT_FILTER_INIT_BASE_IDX 2
+-#define mmSCL5_SCL_VERT_FILTER_INIT_BOT 0x10a8
+-#define mmSCL5_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
+-#define mmSCL5_SCL_ROUND_OFFSET 0x10a9
+-#define mmSCL5_SCL_ROUND_OFFSET_BASE_IDX 2
+-#define mmSCL5_SCL_UPDATE 0x10aa
+-#define mmSCL5_SCL_UPDATE_BASE_IDX 2
+-#define mmSCL5_SCL_F_SHARP_CONTROL 0x10ab
+-#define mmSCL5_SCL_F_SHARP_CONTROL_BASE_IDX 2
+-#define mmSCL5_SCL_ALU_CONTROL 0x10ac
+-#define mmSCL5_SCL_ALU_CONTROL_BASE_IDX 2
+-#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0x10ad
+-#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
+-#define mmSCL5_VIEWPORT_START_SECONDARY 0x10ae
+-#define mmSCL5_VIEWPORT_START_SECONDARY_BASE_IDX 2
+-#define mmSCL5_VIEWPORT_START 0x10af
+-#define mmSCL5_VIEWPORT_START_BASE_IDX 2
+-#define mmSCL5_VIEWPORT_SIZE 0x10b0
+-#define mmSCL5_VIEWPORT_SIZE_BASE_IDX 2
+-#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT 0x10b1
+-#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
+-#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM 0x10b2
+-#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
+-#define mmSCL5_SCL_MODE_CHANGE_DET1 0x10b3
+-#define mmSCL5_SCL_MODE_CHANGE_DET1_BASE_IDX 2
+-#define mmSCL5_SCL_MODE_CHANGE_DET2 0x10b4
+-#define mmSCL5_SCL_MODE_CHANGE_DET2_BASE_IDX 2
+-#define mmSCL5_SCL_MODE_CHANGE_DET3 0x10b5
+-#define mmSCL5_SCL_MODE_CHANGE_DET3_BASE_IDX 2
+-#define mmSCL5_SCL_MODE_CHANGE_MASK 0x10b6
+-#define mmSCL5_SCL_MODE_CHANGE_MASK_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_blnd5_dispdec
+-// base address: 0x2800
+-#define mmBLND5_BLND_CONTROL 0x10c7
+-#define mmBLND5_BLND_CONTROL_BASE_IDX 2
+-#define mmBLND5_BLND_SM_CONTROL2 0x10c8
+-#define mmBLND5_BLND_SM_CONTROL2_BASE_IDX 2
+-#define mmBLND5_BLND_CONTROL2 0x10c9
+-#define mmBLND5_BLND_CONTROL2_BASE_IDX 2
+-#define mmBLND5_BLND_UPDATE 0x10ca
+-#define mmBLND5_BLND_UPDATE_BASE_IDX 2
+-#define mmBLND5_BLND_UNDERFLOW_INTERRUPT 0x10cb
+-#define mmBLND5_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2
+-#define mmBLND5_BLND_V_UPDATE_LOCK 0x10cc
+-#define mmBLND5_BLND_V_UPDATE_LOCK_BASE_IDX 2
+-#define mmBLND5_BLND_REG_UPDATE_STATUS 0x10cd
+-#define mmBLND5_BLND_REG_UPDATE_STATUS_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_crtc5_dispdec
+-// base address: 0x2800
+-#define mmCRTC5_CRTC_H_BLANK_EARLY_NUM 0x10d2
+-#define mmCRTC5_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2
+-#define mmCRTC5_CRTC_H_TOTAL 0x10d3
+-#define mmCRTC5_CRTC_H_TOTAL_BASE_IDX 2
+-#define mmCRTC5_CRTC_H_BLANK_START_END 0x10d4
+-#define mmCRTC5_CRTC_H_BLANK_START_END_BASE_IDX 2
+-#define mmCRTC5_CRTC_H_SYNC_A 0x10d5
+-#define mmCRTC5_CRTC_H_SYNC_A_BASE_IDX 2
+-#define mmCRTC5_CRTC_H_SYNC_A_CNTL 0x10d6
+-#define mmCRTC5_CRTC_H_SYNC_A_CNTL_BASE_IDX 2
+-#define mmCRTC5_CRTC_H_SYNC_B 0x10d7
+-#define mmCRTC5_CRTC_H_SYNC_B_BASE_IDX 2
+-#define mmCRTC5_CRTC_H_SYNC_B_CNTL 0x10d8
+-#define mmCRTC5_CRTC_H_SYNC_B_CNTL_BASE_IDX 2
+-#define mmCRTC5_CRTC_VBI_END 0x10d9
+-#define mmCRTC5_CRTC_VBI_END_BASE_IDX 2
+-#define mmCRTC5_CRTC_V_TOTAL 0x10da
+-#define mmCRTC5_CRTC_V_TOTAL_BASE_IDX 2
+-#define mmCRTC5_CRTC_V_TOTAL_MIN 0x10db
+-#define mmCRTC5_CRTC_V_TOTAL_MIN_BASE_IDX 2
+-#define mmCRTC5_CRTC_V_TOTAL_MAX 0x10dc
+-#define mmCRTC5_CRTC_V_TOTAL_MAX_BASE_IDX 2
+-#define mmCRTC5_CRTC_V_TOTAL_CONTROL 0x10dd
+-#define mmCRTC5_CRTC_V_TOTAL_CONTROL_BASE_IDX 2
+-#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS 0x10de
+-#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2
+-#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS 0x10df
+-#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2
+-#define mmCRTC5_CRTC_V_BLANK_START_END 0x10e0
+-#define mmCRTC5_CRTC_V_BLANK_START_END_BASE_IDX 2
+-#define mmCRTC5_CRTC_V_SYNC_A 0x10e1
+-#define mmCRTC5_CRTC_V_SYNC_A_BASE_IDX 2
+-#define mmCRTC5_CRTC_V_SYNC_A_CNTL 0x10e2
+-#define mmCRTC5_CRTC_V_SYNC_A_CNTL_BASE_IDX 2
+-#define mmCRTC5_CRTC_V_SYNC_B 0x10e3
+-#define mmCRTC5_CRTC_V_SYNC_B_BASE_IDX 2
+-#define mmCRTC5_CRTC_V_SYNC_B_CNTL 0x10e4
+-#define mmCRTC5_CRTC_V_SYNC_B_CNTL_BASE_IDX 2
+-#define mmCRTC5_CRTC_DTMTEST_CNTL 0x10e5
+-#define mmCRTC5_CRTC_DTMTEST_CNTL_BASE_IDX 2
+-#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION 0x10e6
+-#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2
+-#define mmCRTC5_CRTC_TRIGA_CNTL 0x10e7
+-#define mmCRTC5_CRTC_TRIGA_CNTL_BASE_IDX 2
+-#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG 0x10e8
+-#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2
+-#define mmCRTC5_CRTC_TRIGB_CNTL 0x10e9
+-#define mmCRTC5_CRTC_TRIGB_CNTL_BASE_IDX 2
+-#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG 0x10ea
+-#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2
+-#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL 0x10eb
+-#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
+-#define mmCRTC5_CRTC_FLOW_CONTROL 0x10ec
+-#define mmCRTC5_CRTC_FLOW_CONTROL_BASE_IDX 2
+-#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE 0x10ed
+-#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
+-#define mmCRTC5_CRTC_AVSYNC_COUNTER 0x10ee
+-#define mmCRTC5_CRTC_AVSYNC_COUNTER_BASE_IDX 2
+-#define mmCRTC5_CRTC_CONTROL 0x10ef
+-#define mmCRTC5_CRTC_CONTROL_BASE_IDX 2
+-#define mmCRTC5_CRTC_BLANK_CONTROL 0x10f0
+-#define mmCRTC5_CRTC_BLANK_CONTROL_BASE_IDX 2
+-#define mmCRTC5_CRTC_INTERLACE_CONTROL 0x10f1
+-#define mmCRTC5_CRTC_INTERLACE_CONTROL_BASE_IDX 2
+-#define mmCRTC5_CRTC_INTERLACE_STATUS 0x10f2
+-#define mmCRTC5_CRTC_INTERLACE_STATUS_BASE_IDX 2
+-#define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL 0x10f3
+-#define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2
+-#define mmCRTC5_CRTC_PIXEL_DATA_READBACK0 0x10f4
+-#define mmCRTC5_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2
+-#define mmCRTC5_CRTC_PIXEL_DATA_READBACK1 0x10f5
+-#define mmCRTC5_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2
+-#define mmCRTC5_CRTC_STATUS 0x10f6
+-#define mmCRTC5_CRTC_STATUS_BASE_IDX 2
+-#define mmCRTC5_CRTC_STATUS_POSITION 0x10f7
+-#define mmCRTC5_CRTC_STATUS_POSITION_BASE_IDX 2
+-#define mmCRTC5_CRTC_NOM_VERT_POSITION 0x10f8
+-#define mmCRTC5_CRTC_NOM_VERT_POSITION_BASE_IDX 2
+-#define mmCRTC5_CRTC_STATUS_FRAME_COUNT 0x10f9
+-#define mmCRTC5_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2
+-#define mmCRTC5_CRTC_STATUS_VF_COUNT 0x10fa
+-#define mmCRTC5_CRTC_STATUS_VF_COUNT_BASE_IDX 2
+-#define mmCRTC5_CRTC_STATUS_HV_COUNT 0x10fb
+-#define mmCRTC5_CRTC_STATUS_HV_COUNT_BASE_IDX 2
+-#define mmCRTC5_CRTC_COUNT_CONTROL 0x10fc
+-#define mmCRTC5_CRTC_COUNT_CONTROL_BASE_IDX 2
+-#define mmCRTC5_CRTC_COUNT_RESET 0x10fd
+-#define mmCRTC5_CRTC_COUNT_RESET_BASE_IDX 2
+-#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x10fe
+-#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
+-#define mmCRTC5_CRTC_VERT_SYNC_CONTROL 0x10ff
+-#define mmCRTC5_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2
+-#define mmCRTC5_CRTC_STEREO_STATUS 0x1100
+-#define mmCRTC5_CRTC_STEREO_STATUS_BASE_IDX 2
+-#define mmCRTC5_CRTC_STEREO_CONTROL 0x1101
+-#define mmCRTC5_CRTC_STEREO_CONTROL_BASE_IDX 2
+-#define mmCRTC5_CRTC_SNAPSHOT_STATUS 0x1102
+-#define mmCRTC5_CRTC_SNAPSHOT_STATUS_BASE_IDX 2
+-#define mmCRTC5_CRTC_SNAPSHOT_CONTROL 0x1103
+-#define mmCRTC5_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2
+-#define mmCRTC5_CRTC_SNAPSHOT_POSITION 0x1104
+-#define mmCRTC5_CRTC_SNAPSHOT_POSITION_BASE_IDX 2
+-#define mmCRTC5_CRTC_SNAPSHOT_FRAME 0x1105
+-#define mmCRTC5_CRTC_SNAPSHOT_FRAME_BASE_IDX 2
+-#define mmCRTC5_CRTC_START_LINE_CONTROL 0x1106
+-#define mmCRTC5_CRTC_START_LINE_CONTROL_BASE_IDX 2
+-#define mmCRTC5_CRTC_INTERRUPT_CONTROL 0x1107
+-#define mmCRTC5_CRTC_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmCRTC5_CRTC_UPDATE_LOCK 0x1108
+-#define mmCRTC5_CRTC_UPDATE_LOCK_BASE_IDX 2
+-#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL 0x1109
+-#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
+-#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x110a
+-#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2
+-#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL 0x110b
+-#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2
+-#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS 0x110c
+-#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2
+-#define mmCRTC5_CRTC_TEST_PATTERN_COLOR 0x110d
+-#define mmCRTC5_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2
+-#define mmCRTC5_CRTC_MASTER_UPDATE_LOCK 0x110e
+-#define mmCRTC5_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2
+-#define mmCRTC5_CRTC_MASTER_UPDATE_MODE 0x110f
+-#define mmCRTC5_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2
+-#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT 0x1110
+-#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2
+-#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1111
+-#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2
+-#define mmCRTC5_CRTC_MVP_STATUS 0x1112
+-#define mmCRTC5_CRTC_MVP_STATUS_BASE_IDX 2
+-#define mmCRTC5_CRTC_MASTER_EN 0x1113
+-#define mmCRTC5_CRTC_MASTER_EN_BASE_IDX 2
+-#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT 0x1114
+-#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2
+-#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS 0x1115
+-#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2
+-#define mmCRTC5_CRTC_OVERSCAN_COLOR 0x1117
+-#define mmCRTC5_CRTC_OVERSCAN_COLOR_BASE_IDX 2
+-#define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT 0x1118
+-#define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2
+-#define mmCRTC5_CRTC_BLANK_DATA_COLOR 0x1119
+-#define mmCRTC5_CRTC_BLANK_DATA_COLOR_BASE_IDX 2
+-#define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT 0x111a
+-#define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2
+-#define mmCRTC5_CRTC_BLACK_COLOR 0x111b
+-#define mmCRTC5_CRTC_BLACK_COLOR_BASE_IDX 2
+-#define mmCRTC5_CRTC_BLACK_COLOR_EXT 0x111c
+-#define mmCRTC5_CRTC_BLACK_COLOR_EXT_BASE_IDX 2
+-#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION 0x111d
+-#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
+-#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x111e
+-#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
+-#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION 0x111f
+-#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
+-#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1120
+-#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
+-#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1121
+-#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
+-#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1122
+-#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
+-#define mmCRTC5_CRTC_CRC_CNTL 0x1123
+-#define mmCRTC5_CRTC_CRC_CNTL_BASE_IDX 2
+-#define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL 0x1124
+-#define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
+-#define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1125
+-#define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
+-#define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL 0x1126
+-#define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
+-#define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1127
+-#define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
+-#define mmCRTC5_CRTC_CRC0_DATA_RG 0x1128
+-#define mmCRTC5_CRTC_CRC0_DATA_RG_BASE_IDX 2
+-#define mmCRTC5_CRTC_CRC0_DATA_B 0x1129
+-#define mmCRTC5_CRTC_CRC0_DATA_B_BASE_IDX 2
+-#define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL 0x112a
+-#define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
+-#define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL 0x112b
+-#define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
+-#define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL 0x112c
+-#define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
+-#define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL 0x112d
+-#define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
+-#define mmCRTC5_CRTC_CRC1_DATA_RG 0x112e
+-#define mmCRTC5_CRTC_CRC1_DATA_RG_BASE_IDX 2
+-#define mmCRTC5_CRTC_CRC1_DATA_B 0x112f
+-#define mmCRTC5_CRTC_CRC1_DATA_B_BASE_IDX 2
+-#define mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL 0x1130
+-#define mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2
+-#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1131
+-#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2
+-#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1132
+-#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2
+-#define mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1133
+-#define mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1134
+-#define mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1135
+-#define mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL 0x1136
+-#define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2
+-#define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL 0x1137
+-#define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2
+-#define mmCRTC5_CRTC_GSL_VSYNC_GAP 0x1138
+-#define mmCRTC5_CRTC_GSL_VSYNC_GAP_BASE_IDX 2
+-#define mmCRTC5_CRTC_GSL_WINDOW 0x1139
+-#define mmCRTC5_CRTC_GSL_WINDOW_BASE_IDX 2
+-#define mmCRTC5_CRTC_GSL_CONTROL 0x113a
+-#define mmCRTC5_CRTC_GSL_CONTROL_BASE_IDX 2
+-#define mmCRTC5_CRTC_RANGE_TIMING_INT_STATUS 0x113d
+-#define mmCRTC5_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2
+-#define mmCRTC5_CRTC_DRR_CONTROL 0x113e
+-#define mmCRTC5_CRTC_DRR_CONTROL_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_fmt5_dispdec
+-// base address: 0x2800
+-#define mmFMT5_FMT_CLAMP_COMPONENT_R 0x1142
+-#define mmFMT5_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
+-#define mmFMT5_FMT_CLAMP_COMPONENT_G 0x1143
+-#define mmFMT5_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
+-#define mmFMT5_FMT_CLAMP_COMPONENT_B 0x1144
+-#define mmFMT5_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
+-#define mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x1145
+-#define mmFMT5_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
+-#define mmFMT5_FMT_CONTROL 0x1146
+-#define mmFMT5_FMT_CONTROL_BASE_IDX 2
+-#define mmFMT5_FMT_BIT_DEPTH_CONTROL 0x1147
+-#define mmFMT5_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
+-#define mmFMT5_FMT_DITHER_RAND_R_SEED 0x1148
+-#define mmFMT5_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
+-#define mmFMT5_FMT_DITHER_RAND_G_SEED 0x1149
+-#define mmFMT5_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
+-#define mmFMT5_FMT_DITHER_RAND_B_SEED 0x114a
+-#define mmFMT5_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
+-#define mmFMT5_FMT_CLAMP_CNTL 0x114e
+-#define mmFMT5_FMT_CLAMP_CNTL_BASE_IDX 2
+-#define mmFMT5_FMT_CRC_CNTL 0x114f
+-#define mmFMT5_FMT_CRC_CNTL_BASE_IDX 2
+-#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK 0x1150
+-#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
+-#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1151
+-#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
+-#define mmFMT5_FMT_CRC_SIG_RED_GREEN 0x1152
+-#define mmFMT5_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2
+-#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL 0x1153
+-#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2
+-#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1154
+-#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
+-#define mmFMT5_FMT_420_HBLANK_EARLY_START 0x1155
+-#define mmFMT5_FMT_420_HBLANK_EARLY_START_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_unp0_dispdec
+-// base address: 0x0
+-#define mmUNP0_UNP_GRPH_ENABLE 0x115a
+-#define mmUNP0_UNP_GRPH_ENABLE_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_CONTROL 0x115b
+-#define mmUNP0_UNP_GRPH_CONTROL_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_CONTROL_C 0x115c
+-#define mmUNP0_UNP_GRPH_CONTROL_C_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_CONTROL_EXP 0x115d
+-#define mmUNP0_UNP_GRPH_CONTROL_EXP_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_SWAP_CNTL 0x115e
+-#define mmUNP0_UNP_GRPH_SWAP_CNTL_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L 0x115f
+-#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C 0x1160
+-#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L 0x1161
+-#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x1162
+-#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L 0x1163
+-#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C 0x1164
+-#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x1165
+-#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x1166
+-#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L 0x1167
+-#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C 0x1168
+-#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L 0x1169
+-#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x116a
+-#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L 0x116b
+-#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C 0x116c
+-#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x116d
+-#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x116e
+-#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_PITCH_L 0x116f
+-#define mmUNP0_UNP_GRPH_PITCH_L_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_PITCH_C 0x1170
+-#define mmUNP0_UNP_GRPH_PITCH_C_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_L 0x1171
+-#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_L_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_C 0x1172
+-#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_C_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_L 0x1173
+-#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_L_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_C 0x1174
+-#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_C_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_X_START_L 0x1175
+-#define mmUNP0_UNP_GRPH_X_START_L_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_X_START_C 0x1176
+-#define mmUNP0_UNP_GRPH_X_START_C_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_Y_START_L 0x1177
+-#define mmUNP0_UNP_GRPH_Y_START_L_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_Y_START_C 0x1178
+-#define mmUNP0_UNP_GRPH_Y_START_C_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_X_END_L 0x1179
+-#define mmUNP0_UNP_GRPH_X_END_L_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_X_END_C 0x117a
+-#define mmUNP0_UNP_GRPH_X_END_C_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_Y_END_L 0x117b
+-#define mmUNP0_UNP_GRPH_Y_END_L_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_Y_END_C 0x117c
+-#define mmUNP0_UNP_GRPH_Y_END_C_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_UPDATE 0x117d
+-#define mmUNP0_UNP_GRPH_UPDATE_BASE_IDX 2
+-#define mmUNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT 0x117e
+-#define mmUNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L 0x117f
+-#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C 0x1180
+-#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L 0x1181
+-#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C 0x1182
+-#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_BASE_IDX 2
+-#define mmUNP0_UNP_DVMM_PTE_CONTROL 0x1183
+-#define mmUNP0_UNP_DVMM_PTE_CONTROL_BASE_IDX 2
+-#define mmUNP0_UNP_DVMM_PTE_CONTROL_C 0x1184
+-#define mmUNP0_UNP_DVMM_PTE_CONTROL_C_BASE_IDX 2
+-#define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL 0x1185
+-#define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL_BASE_IDX 2
+-#define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL_C 0x1186
+-#define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL_C_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_INTERRUPT_STATUS 0x1187
+-#define mmUNP0_UNP_GRPH_INTERRUPT_STATUS_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_INTERRUPT_CONTROL 0x1188
+-#define mmUNP0_UNP_GRPH_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmUNP0_UNP_GRPH_STEREOSYNC_FLIP 0x1189
+-#define mmUNP0_UNP_GRPH_STEREOSYNC_FLIP_BASE_IDX 2
+-#define mmUNP0_UNP_FLIP_CONTROL 0x118a
+-#define mmUNP0_UNP_FLIP_CONTROL_BASE_IDX 2
+-#define mmUNP0_UNP_CRC_CONTROL 0x118b
+-#define mmUNP0_UNP_CRC_CONTROL_BASE_IDX 2
+-#define mmUNP0_UNP_CRC_MASK 0x118c
+-#define mmUNP0_UNP_CRC_MASK_BASE_IDX 2
+-#define mmUNP0_UNP_CRC_CURRENT 0x118d
+-#define mmUNP0_UNP_CRC_CURRENT_BASE_IDX 2
+-#define mmUNP0_UNP_CRC_LAST 0x118e
+-#define mmUNP0_UNP_CRC_LAST_BASE_IDX 2
+-#define mmUNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK 0x118f
+-#define mmUNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2
+-#define mmUNP0_UNP_HW_ROTATION 0x1190
+-#define mmUNP0_UNP_HW_ROTATION_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_lbv0_dispdec
+-// base address: 0x0
+-#define mmLBV0_LBV_DATA_FORMAT 0x1196
+-#define mmLBV0_LBV_DATA_FORMAT_BASE_IDX 2
+-#define mmLBV0_LBV_MEMORY_CTRL 0x1197
+-#define mmLBV0_LBV_MEMORY_CTRL_BASE_IDX 2
+-#define mmLBV0_LBV_MEMORY_SIZE_STATUS 0x1198
+-#define mmLBV0_LBV_MEMORY_SIZE_STATUS_BASE_IDX 2
+-#define mmLBV0_LBV_DESKTOP_HEIGHT 0x1199
+-#define mmLBV0_LBV_DESKTOP_HEIGHT_BASE_IDX 2
+-#define mmLBV0_LBV_VLINE_START_END 0x119a
+-#define mmLBV0_LBV_VLINE_START_END_BASE_IDX 2
+-#define mmLBV0_LBV_VLINE2_START_END 0x119b
+-#define mmLBV0_LBV_VLINE2_START_END_BASE_IDX 2
+-#define mmLBV0_LBV_V_COUNTER 0x119c
+-#define mmLBV0_LBV_V_COUNTER_BASE_IDX 2
+-#define mmLBV0_LBV_SNAPSHOT_V_COUNTER 0x119d
+-#define mmLBV0_LBV_SNAPSHOT_V_COUNTER_BASE_IDX 2
+-#define mmLBV0_LBV_V_COUNTER_CHROMA 0x119e
+-#define mmLBV0_LBV_V_COUNTER_CHROMA_BASE_IDX 2
+-#define mmLBV0_LBV_SNAPSHOT_V_COUNTER_CHROMA 0x119f
+-#define mmLBV0_LBV_SNAPSHOT_V_COUNTER_CHROMA_BASE_IDX 2
+-#define mmLBV0_LBV_INTERRUPT_MASK 0x11a0
+-#define mmLBV0_LBV_INTERRUPT_MASK_BASE_IDX 2
+-#define mmLBV0_LBV_VLINE_STATUS 0x11a1
+-#define mmLBV0_LBV_VLINE_STATUS_BASE_IDX 2
+-#define mmLBV0_LBV_VLINE2_STATUS 0x11a2
+-#define mmLBV0_LBV_VLINE2_STATUS_BASE_IDX 2
+-#define mmLBV0_LBV_VBLANK_STATUS 0x11a3
+-#define mmLBV0_LBV_VBLANK_STATUS_BASE_IDX 2
+-#define mmLBV0_LBV_SYNC_RESET_SEL 0x11a4
+-#define mmLBV0_LBV_SYNC_RESET_SEL_BASE_IDX 2
+-#define mmLBV0_LBV_BLACK_KEYER_R_CR 0x11a5
+-#define mmLBV0_LBV_BLACK_KEYER_R_CR_BASE_IDX 2
+-#define mmLBV0_LBV_BLACK_KEYER_G_Y 0x11a6
+-#define mmLBV0_LBV_BLACK_KEYER_G_Y_BASE_IDX 2
+-#define mmLBV0_LBV_BLACK_KEYER_B_CB 0x11a7
+-#define mmLBV0_LBV_BLACK_KEYER_B_CB_BASE_IDX 2
+-#define mmLBV0_LBV_KEYER_COLOR_CTRL 0x11a8
+-#define mmLBV0_LBV_KEYER_COLOR_CTRL_BASE_IDX 2
+-#define mmLBV0_LBV_KEYER_COLOR_R_CR 0x11a9
+-#define mmLBV0_LBV_KEYER_COLOR_R_CR_BASE_IDX 2
+-#define mmLBV0_LBV_KEYER_COLOR_G_Y 0x11aa
+-#define mmLBV0_LBV_KEYER_COLOR_G_Y_BASE_IDX 2
+-#define mmLBV0_LBV_KEYER_COLOR_B_CB 0x11ab
+-#define mmLBV0_LBV_KEYER_COLOR_B_CB_BASE_IDX 2
+-#define mmLBV0_LBV_KEYER_COLOR_REP_R_CR 0x11ac
+-#define mmLBV0_LBV_KEYER_COLOR_REP_R_CR_BASE_IDX 2
+-#define mmLBV0_LBV_KEYER_COLOR_REP_G_Y 0x11ad
+-#define mmLBV0_LBV_KEYER_COLOR_REP_G_Y_BASE_IDX 2
+-#define mmLBV0_LBV_KEYER_COLOR_REP_B_CB 0x11ae
+-#define mmLBV0_LBV_KEYER_COLOR_REP_B_CB_BASE_IDX 2
+-#define mmLBV0_LBV_BUFFER_LEVEL_STATUS 0x11af
+-#define mmLBV0_LBV_BUFFER_LEVEL_STATUS_BASE_IDX 2
+-#define mmLBV0_LBV_BUFFER_URGENCY_CTRL 0x11b0
+-#define mmLBV0_LBV_BUFFER_URGENCY_CTRL_BASE_IDX 2
+-#define mmLBV0_LBV_BUFFER_URGENCY_STATUS 0x11b1
+-#define mmLBV0_LBV_BUFFER_URGENCY_STATUS_BASE_IDX 2
+-#define mmLBV0_LBV_BUFFER_STATUS 0x11b2
+-#define mmLBV0_LBV_BUFFER_STATUS_BASE_IDX 2
+-#define mmLBV0_LBV_NO_OUTSTANDING_REQ_STATUS 0x11b3
+-#define mmLBV0_LBV_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_sclv0_dispdec
+-// base address: 0x0
+-#define mmSCLV0_SCLV_COEF_RAM_SELECT 0x11ca
+-#define mmSCLV0_SCLV_COEF_RAM_SELECT_BASE_IDX 2
+-#define mmSCLV0_SCLV_COEF_RAM_TAP_DATA 0x11cb
+-#define mmSCLV0_SCLV_COEF_RAM_TAP_DATA_BASE_IDX 2
+-#define mmSCLV0_SCLV_MODE 0x11cc
+-#define mmSCLV0_SCLV_MODE_BASE_IDX 2
+-#define mmSCLV0_SCLV_TAP_CONTROL 0x11cd
+-#define mmSCLV0_SCLV_TAP_CONTROL_BASE_IDX 2
+-#define mmSCLV0_SCLV_CONTROL 0x11ce
+-#define mmSCLV0_SCLV_CONTROL_BASE_IDX 2
+-#define mmSCLV0_SCLV_MANUAL_REPLICATE_CONTROL 0x11cf
+-#define mmSCLV0_SCLV_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
+-#define mmSCLV0_SCLV_AUTOMATIC_MODE_CONTROL 0x11d0
+-#define mmSCLV0_SCLV_AUTOMATIC_MODE_CONTROL_BASE_IDX 2
+-#define mmSCLV0_SCLV_HORZ_FILTER_CONTROL 0x11d1
+-#define mmSCLV0_SCLV_HORZ_FILTER_CONTROL_BASE_IDX 2
+-#define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO 0x11d2
+-#define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
+-#define mmSCLV0_SCLV_HORZ_FILTER_INIT 0x11d3
+-#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BASE_IDX 2
+-#define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_C 0x11d4
+-#define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
+-#define mmSCLV0_SCLV_HORZ_FILTER_INIT_C 0x11d5
+-#define mmSCLV0_SCLV_HORZ_FILTER_INIT_C_BASE_IDX 2
+-#define mmSCLV0_SCLV_VERT_FILTER_CONTROL 0x11d6
+-#define mmSCLV0_SCLV_VERT_FILTER_CONTROL_BASE_IDX 2
+-#define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO 0x11d7
+-#define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
+-#define mmSCLV0_SCLV_VERT_FILTER_INIT 0x11d8
+-#define mmSCLV0_SCLV_VERT_FILTER_INIT_BASE_IDX 2
+-#define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT 0x11d9
+-#define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_BASE_IDX 2
+-#define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_C 0x11da
+-#define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
+-#define mmSCLV0_SCLV_VERT_FILTER_INIT_C 0x11db
+-#define mmSCLV0_SCLV_VERT_FILTER_INIT_C_BASE_IDX 2
+-#define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_C 0x11dc
+-#define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
+-#define mmSCLV0_SCLV_ROUND_OFFSET 0x11dd
+-#define mmSCLV0_SCLV_ROUND_OFFSET_BASE_IDX 2
+-#define mmSCLV0_SCLV_UPDATE 0x11de
+-#define mmSCLV0_SCLV_UPDATE_BASE_IDX 2
+-#define mmSCLV0_SCLV_ALU_CONTROL 0x11df
+-#define mmSCLV0_SCLV_ALU_CONTROL_BASE_IDX 2
+-#define mmSCLV0_SCLV_VIEWPORT_START 0x11e0
+-#define mmSCLV0_SCLV_VIEWPORT_START_BASE_IDX 2
+-#define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY 0x11e1
+-#define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_BASE_IDX 2
+-#define mmSCLV0_SCLV_VIEWPORT_SIZE 0x11e2
+-#define mmSCLV0_SCLV_VIEWPORT_SIZE_BASE_IDX 2
+-#define mmSCLV0_SCLV_VIEWPORT_START_C 0x11e3
+-#define mmSCLV0_SCLV_VIEWPORT_START_C_BASE_IDX 2
+-#define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_C 0x11e4
+-#define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_C_BASE_IDX 2
+-#define mmSCLV0_SCLV_VIEWPORT_SIZE_C 0x11e5
+-#define mmSCLV0_SCLV_VIEWPORT_SIZE_C_BASE_IDX 2
+-#define mmSCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT 0x11e6
+-#define mmSCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
+-#define mmSCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM 0x11e7
+-#define mmSCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
+-#define mmSCLV0_SCLV_MODE_CHANGE_DET1 0x11e8
+-#define mmSCLV0_SCLV_MODE_CHANGE_DET1_BASE_IDX 2
+-#define mmSCLV0_SCLV_MODE_CHANGE_DET2 0x11e9
+-#define mmSCLV0_SCLV_MODE_CHANGE_DET2_BASE_IDX 2
+-#define mmSCLV0_SCLV_MODE_CHANGE_DET3 0x11ea
+-#define mmSCLV0_SCLV_MODE_CHANGE_DET3_BASE_IDX 2
+-#define mmSCLV0_SCLV_MODE_CHANGE_MASK 0x11eb
+-#define mmSCLV0_SCLV_MODE_CHANGE_MASK_BASE_IDX 2
+-#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT 0x11ec
+-#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_BASE_IDX 2
+-#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_C 0x11ed
+-#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_C_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_col_man0_dispdec
+-// base address: 0x0
+-#define mmCOL_MAN0_COL_MAN_UPDATE 0x11fe
+-#define mmCOL_MAN0_COL_MAN_UPDATE_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_INPUT_CSC_CONTROL 0x11ff
+-#define mmCOL_MAN0_COL_MAN_INPUT_CSC_CONTROL_BASE_IDX 2
+-#define mmCOL_MAN0_INPUT_CSC_C11_C12_A 0x1200
+-#define mmCOL_MAN0_INPUT_CSC_C11_C12_A_BASE_IDX 2
+-#define mmCOL_MAN0_INPUT_CSC_C13_C14_A 0x1201
+-#define mmCOL_MAN0_INPUT_CSC_C13_C14_A_BASE_IDX 2
+-#define mmCOL_MAN0_INPUT_CSC_C21_C22_A 0x1202
+-#define mmCOL_MAN0_INPUT_CSC_C21_C22_A_BASE_IDX 2
+-#define mmCOL_MAN0_INPUT_CSC_C23_C24_A 0x1203
+-#define mmCOL_MAN0_INPUT_CSC_C23_C24_A_BASE_IDX 2
+-#define mmCOL_MAN0_INPUT_CSC_C31_C32_A 0x1204
+-#define mmCOL_MAN0_INPUT_CSC_C31_C32_A_BASE_IDX 2
+-#define mmCOL_MAN0_INPUT_CSC_C33_C34_A 0x1205
+-#define mmCOL_MAN0_INPUT_CSC_C33_C34_A_BASE_IDX 2
+-#define mmCOL_MAN0_INPUT_CSC_C11_C12_B 0x1206
+-#define mmCOL_MAN0_INPUT_CSC_C11_C12_B_BASE_IDX 2
+-#define mmCOL_MAN0_INPUT_CSC_C13_C14_B 0x1207
+-#define mmCOL_MAN0_INPUT_CSC_C13_C14_B_BASE_IDX 2
+-#define mmCOL_MAN0_INPUT_CSC_C21_C22_B 0x1208
+-#define mmCOL_MAN0_INPUT_CSC_C21_C22_B_BASE_IDX 2
+-#define mmCOL_MAN0_INPUT_CSC_C23_C24_B 0x1209
+-#define mmCOL_MAN0_INPUT_CSC_C23_C24_B_BASE_IDX 2
+-#define mmCOL_MAN0_INPUT_CSC_C31_C32_B 0x120a
+-#define mmCOL_MAN0_INPUT_CSC_C31_C32_B_BASE_IDX 2
+-#define mmCOL_MAN0_INPUT_CSC_C33_C34_B 0x120b
+-#define mmCOL_MAN0_INPUT_CSC_C33_C34_B_BASE_IDX 2
+-#define mmCOL_MAN0_PRESCALE_CONTROL 0x120c
+-#define mmCOL_MAN0_PRESCALE_CONTROL_BASE_IDX 2
+-#define mmCOL_MAN0_PRESCALE_VALUES_R 0x120d
+-#define mmCOL_MAN0_PRESCALE_VALUES_R_BASE_IDX 2
+-#define mmCOL_MAN0_PRESCALE_VALUES_G 0x120e
+-#define mmCOL_MAN0_PRESCALE_VALUES_G_BASE_IDX 2
+-#define mmCOL_MAN0_PRESCALE_VALUES_B 0x120f
+-#define mmCOL_MAN0_PRESCALE_VALUES_B_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_OUTPUT_CSC_CONTROL 0x1210
+-#define mmCOL_MAN0_COL_MAN_OUTPUT_CSC_CONTROL_BASE_IDX 2
+-#define mmCOL_MAN0_OUTPUT_CSC_C11_C12_A 0x1211
+-#define mmCOL_MAN0_OUTPUT_CSC_C11_C12_A_BASE_IDX 2
+-#define mmCOL_MAN0_OUTPUT_CSC_C13_C14_A 0x1212
+-#define mmCOL_MAN0_OUTPUT_CSC_C13_C14_A_BASE_IDX 2
+-#define mmCOL_MAN0_OUTPUT_CSC_C21_C22_A 0x1213
+-#define mmCOL_MAN0_OUTPUT_CSC_C21_C22_A_BASE_IDX 2
+-#define mmCOL_MAN0_OUTPUT_CSC_C23_C24_A 0x1214
+-#define mmCOL_MAN0_OUTPUT_CSC_C23_C24_A_BASE_IDX 2
+-#define mmCOL_MAN0_OUTPUT_CSC_C31_C32_A 0x1215
+-#define mmCOL_MAN0_OUTPUT_CSC_C31_C32_A_BASE_IDX 2
+-#define mmCOL_MAN0_OUTPUT_CSC_C33_C34_A 0x1216
+-#define mmCOL_MAN0_OUTPUT_CSC_C33_C34_A_BASE_IDX 2
+-#define mmCOL_MAN0_OUTPUT_CSC_C11_C12_B 0x1217
+-#define mmCOL_MAN0_OUTPUT_CSC_C11_C12_B_BASE_IDX 2
+-#define mmCOL_MAN0_OUTPUT_CSC_C13_C14_B 0x1218
+-#define mmCOL_MAN0_OUTPUT_CSC_C13_C14_B_BASE_IDX 2
+-#define mmCOL_MAN0_OUTPUT_CSC_C21_C22_B 0x1219
+-#define mmCOL_MAN0_OUTPUT_CSC_C21_C22_B_BASE_IDX 2
+-#define mmCOL_MAN0_OUTPUT_CSC_C23_C24_B 0x121a
+-#define mmCOL_MAN0_OUTPUT_CSC_C23_C24_B_BASE_IDX 2
+-#define mmCOL_MAN0_OUTPUT_CSC_C31_C32_B 0x121b
+-#define mmCOL_MAN0_OUTPUT_CSC_C31_C32_B_BASE_IDX 2
+-#define mmCOL_MAN0_OUTPUT_CSC_C33_C34_B 0x121c
+-#define mmCOL_MAN0_OUTPUT_CSC_C33_C34_B_BASE_IDX 2
+-#define mmCOL_MAN0_DENORM_CLAMP_CONTROL 0x121d
+-#define mmCOL_MAN0_DENORM_CLAMP_CONTROL_BASE_IDX 2
+-#define mmCOL_MAN0_DENORM_CLAMP_RANGE_R_CR 0x121e
+-#define mmCOL_MAN0_DENORM_CLAMP_RANGE_R_CR_BASE_IDX 2
+-#define mmCOL_MAN0_DENORM_CLAMP_RANGE_G_Y 0x121f
+-#define mmCOL_MAN0_DENORM_CLAMP_RANGE_G_Y_BASE_IDX 2
+-#define mmCOL_MAN0_DENORM_CLAMP_RANGE_B_CB 0x1220
+-#define mmCOL_MAN0_DENORM_CLAMP_RANGE_B_CB_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_FP_CONVERTED_FIELD 0x1221
+-#define mmCOL_MAN0_COL_MAN_FP_CONVERTED_FIELD_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CONTROL 0x1222
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CONTROL_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_INDEX 0x1223
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_INDEX_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_DATA 0x1224
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_DATA_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK 0x1225
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_START_CNTL 0x1226
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL 0x1227
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL1 0x1228
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL2 0x1229
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1 0x122a
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3 0x122b
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5 0x122c
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7 0x122d
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9 0x122e
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11 0x122f
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13 0x1230
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15 0x1231
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_START_CNTL 0x1232
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL 0x1233
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL1 0x1234
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL2 0x1235
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1 0x1236
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3 0x1237
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5 0x1238
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7 0x1239
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9 0x123a
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11 0x123b
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13 0x123c
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15 0x123d
+-#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2
+-#define mmCOL_MAN0_PACK_FIFO_ERROR 0x123e
+-#define mmCOL_MAN0_PACK_FIFO_ERROR_BASE_IDX 2
+-#define mmCOL_MAN0_OUTPUT_FIFO_ERROR 0x123f
+-#define mmCOL_MAN0_OUTPUT_FIFO_ERROR_BASE_IDX 2
+-#define mmCOL_MAN0_INPUT_GAMMA_LUT_AUTOFILL 0x1240
+-#define mmCOL_MAN0_INPUT_GAMMA_LUT_AUTOFILL_BASE_IDX 2
+-#define mmCOL_MAN0_INPUT_GAMMA_LUT_RW_INDEX 0x1241
+-#define mmCOL_MAN0_INPUT_GAMMA_LUT_RW_INDEX_BASE_IDX 2
+-#define mmCOL_MAN0_INPUT_GAMMA_LUT_SEQ_COLOR 0x1242
+-#define mmCOL_MAN0_INPUT_GAMMA_LUT_SEQ_COLOR_BASE_IDX 2
+-#define mmCOL_MAN0_INPUT_GAMMA_LUT_PWL_DATA 0x1243
+-#define mmCOL_MAN0_INPUT_GAMMA_LUT_PWL_DATA_BASE_IDX 2
+-#define mmCOL_MAN0_INPUT_GAMMA_LUT_30_COLOR 0x1244
+-#define mmCOL_MAN0_INPUT_GAMMA_LUT_30_COLOR_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1 0x1245
+-#define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2 0x1246
+-#define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2_BASE_IDX 2
+-#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_B 0x1247
+-#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_B_BASE_IDX 2
+-#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_G 0x1248
+-#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_G_BASE_IDX 2
+-#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_R 0x1249
+-#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_R_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_DEGAMMA_CONTROL 0x124a
+-#define mmCOL_MAN0_COL_MAN_DEGAMMA_CONTROL_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_CONTROL 0x124b
+-#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_CONTROL_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C11_C12 0x124c
+-#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C11_C12_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C13_C14 0x124d
+-#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C13_C14_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C21_C22 0x124e
+-#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C21_C22_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C23_C24 0x124f
+-#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C23_C24_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C31_C32 0x1250
+-#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C31_C32_BASE_IDX 2
+-#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C33_C34 0x1251
+-#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C33_C34_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dcfev0_dispdec
+-// base address: 0x0
+-#define mmDCFEV0_DCFEV_CLOCK_CONTROL 0x127e
+-#define mmDCFEV0_DCFEV_CLOCK_CONTROL_BASE_IDX 2
+-#define mmDCFEV0_DCFEV_SOFT_RESET 0x127f
+-#define mmDCFEV0_DCFEV_SOFT_RESET_BASE_IDX 2
+-#define mmDCFEV0_DCFEV_DMIFV_CLOCK_CONTROL 0x1280
+-#define mmDCFEV0_DCFEV_DMIFV_CLOCK_CONTROL_BASE_IDX 2
+-#define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL 0x1282
+-#define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL_BASE_IDX 2
+-#define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS 0x1283
+-#define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS_BASE_IDX 2
+-#define mmDCFEV0_DCFEV_MEM_PWR_CTRL 0x1284
+-#define mmDCFEV0_DCFEV_MEM_PWR_CTRL_BASE_IDX 2
+-#define mmDCFEV0_DCFEV_MEM_PWR_CTRL2 0x1285
+-#define mmDCFEV0_DCFEV_MEM_PWR_CTRL2_BASE_IDX 2
+-#define mmDCFEV0_DCFEV_MEM_PWR_STATUS 0x1286
+-#define mmDCFEV0_DCFEV_MEM_PWR_STATUS_BASE_IDX 2
+-#define mmDCFEV0_DCFEV_L_FLUSH 0x1287
+-#define mmDCFEV0_DCFEV_L_FLUSH_BASE_IDX 2
+-#define mmDCFEV0_DCFEV_C_FLUSH 0x1288
+-#define mmDCFEV0_DCFEV_C_FLUSH_BASE_IDX 2
+-#define mmDCFEV0_DCFEV_MISC 0x128a
+-#define mmDCFEV0_DCFEV_MISC_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dc_perfmon11_dispdec
+-// base address: 0x49c8
+-#define mmDC_PERFMON11_PERFCOUNTER_CNTL 0x1292
+-#define mmDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX 2
+-#define mmDC_PERFMON11_PERFCOUNTER_CNTL2 0x1293
+-#define mmDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX 2
+-#define mmDC_PERFMON11_PERFCOUNTER_STATE 0x1294
+-#define mmDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX 2
+-#define mmDC_PERFMON11_PERFMON_CNTL 0x1295
+-#define mmDC_PERFMON11_PERFMON_CNTL_BASE_IDX 2
+-#define mmDC_PERFMON11_PERFMON_CNTL2 0x1296
+-#define mmDC_PERFMON11_PERFMON_CNTL2_BASE_IDX 2
+-#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x1297
+-#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+-#define mmDC_PERFMON11_PERFMON_CVALUE_LOW 0x1298
+-#define mmDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX 2
+-#define mmDC_PERFMON11_PERFMON_HI 0x1299
+-#define mmDC_PERFMON11_PERFMON_HI_BASE_IDX 2
+-#define mmDC_PERFMON11_PERFMON_LOW 0x129a
+-#define mmDC_PERFMON11_PERFMON_LOW_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dmifv_pg0_dispdec
+-// base address: 0x0
+-#define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1 0x129e
+-#define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
+-#define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2 0x129f
+-#define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
+-#define mmDMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL 0x12a0
+-#define mmDMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL_BASE_IDX 2
+-#define mmDMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL 0x12a1
+-#define mmDMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL_BASE_IDX 2
+-#define mmDMIFV_PG0_DPGV0_PIPE_DPM_CONTROL 0x12a2
+-#define mmDMIFV_PG0_DPGV0_PIPE_DPM_CONTROL_BASE_IDX 2
+-#define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL 0x12a3
+-#define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_BASE_IDX 2
+-#define mmDMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL 0x12a4
+-#define mmDMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL_BASE_IDX 2
+-#define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH 0x12a5
+-#define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH_BASE_IDX 2
+-#define mmDMIFV_PG0_DPGV0_REPEATER_PROGRAM 0x12a6
+-#define mmDMIFV_PG0_DPGV0_REPEATER_PROGRAM_BASE_IDX 2
+-#define mmDMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL 0x12aa
+-#define mmDMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL_BASE_IDX 2
+-#define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1 0x12ab
+-#define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
+-#define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2 0x12ac
+-#define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
+-#define mmDMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL 0x12ad
+-#define mmDMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL_BASE_IDX 2
+-#define mmDMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL 0x12ae
+-#define mmDMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL_BASE_IDX 2
+-#define mmDMIFV_PG0_DPGV1_PIPE_DPM_CONTROL 0x12af
+-#define mmDMIFV_PG0_DPGV1_PIPE_DPM_CONTROL_BASE_IDX 2
+-#define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL 0x12b0
+-#define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_BASE_IDX 2
+-#define mmDMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL 0x12b1
+-#define mmDMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL_BASE_IDX 2
+-#define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH 0x12b2
+-#define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH_BASE_IDX 2
+-#define mmDMIFV_PG0_DPGV1_REPEATER_PROGRAM 0x12b3
+-#define mmDMIFV_PG0_DPGV1_REPEATER_PROGRAM_BASE_IDX 2
+-#define mmDMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL 0x12b7
+-#define mmDMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_blndv0_dispdec
+-// base address: 0x0
+-#define mmBLNDV0_BLNDV_CONTROL 0x12db
+-#define mmBLNDV0_BLNDV_CONTROL_BASE_IDX 2
+-#define mmBLNDV0_BLNDV_SM_CONTROL2 0x12dc
+-#define mmBLNDV0_BLNDV_SM_CONTROL2_BASE_IDX 2
+-#define mmBLNDV0_BLNDV_CONTROL2 0x12dd
+-#define mmBLNDV0_BLNDV_CONTROL2_BASE_IDX 2
+-#define mmBLNDV0_BLNDV_UPDATE 0x12de
+-#define mmBLNDV0_BLNDV_UPDATE_BASE_IDX 2
+-#define mmBLNDV0_BLNDV_UNDERFLOW_INTERRUPT 0x12df
+-#define mmBLNDV0_BLNDV_UNDERFLOW_INTERRUPT_BASE_IDX 2
+-#define mmBLNDV0_BLNDV_V_UPDATE_LOCK 0x12e0
+-#define mmBLNDV0_BLNDV_V_UPDATE_LOCK_BASE_IDX 2
+-#define mmBLNDV0_BLNDV_REG_UPDATE_STATUS 0x12e1
+-#define mmBLNDV0_BLNDV_REG_UPDATE_STATUS_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_crtcv0_dispdec
+-// base address: 0x0
+-#define mmCRTCV0_CRTCV_H_BLANK_EARLY_NUM 0x12e6
+-#define mmCRTCV0_CRTCV_H_BLANK_EARLY_NUM_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_H_TOTAL 0x12e7
+-#define mmCRTCV0_CRTCV_H_TOTAL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_H_BLANK_START_END 0x12e8
+-#define mmCRTCV0_CRTCV_H_BLANK_START_END_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_H_SYNC_A 0x12e9
+-#define mmCRTCV0_CRTCV_H_SYNC_A_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_H_SYNC_A_CNTL 0x12ea
+-#define mmCRTCV0_CRTCV_H_SYNC_A_CNTL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_H_SYNC_B 0x12eb
+-#define mmCRTCV0_CRTCV_H_SYNC_B_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_H_SYNC_B_CNTL 0x12ec
+-#define mmCRTCV0_CRTCV_H_SYNC_B_CNTL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_VBI_END 0x12ed
+-#define mmCRTCV0_CRTCV_VBI_END_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_V_TOTAL 0x12ee
+-#define mmCRTCV0_CRTCV_V_TOTAL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_V_TOTAL_MIN 0x12ef
+-#define mmCRTCV0_CRTCV_V_TOTAL_MIN_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_V_TOTAL_MAX 0x12f0
+-#define mmCRTCV0_CRTCV_V_TOTAL_MAX_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_V_TOTAL_CONTROL 0x12f1
+-#define mmCRTCV0_CRTCV_V_TOTAL_CONTROL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_V_TOTAL_INT_STATUS 0x12f2
+-#define mmCRTCV0_CRTCV_V_TOTAL_INT_STATUS_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_VSYNC_NOM_INT_STATUS 0x12f3
+-#define mmCRTCV0_CRTCV_VSYNC_NOM_INT_STATUS_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_V_BLANK_START_END 0x12f4
+-#define mmCRTCV0_CRTCV_V_BLANK_START_END_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_V_SYNC_A 0x12f5
+-#define mmCRTCV0_CRTCV_V_SYNC_A_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_V_SYNC_A_CNTL 0x12f6
+-#define mmCRTCV0_CRTCV_V_SYNC_A_CNTL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_V_SYNC_B 0x12f7
+-#define mmCRTCV0_CRTCV_V_SYNC_B_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_V_SYNC_B_CNTL 0x12f8
+-#define mmCRTCV0_CRTCV_V_SYNC_B_CNTL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_DTMTEST_CNTL 0x12f9
+-#define mmCRTCV0_CRTCV_DTMTEST_CNTL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_DTMTEST_STATUS_POSITION 0x12fa
+-#define mmCRTCV0_CRTCV_DTMTEST_STATUS_POSITION_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_TRIGA_CNTL 0x12fb
+-#define mmCRTCV0_CRTCV_TRIGA_CNTL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_TRIGA_MANUAL_TRIG 0x12fc
+-#define mmCRTCV0_CRTCV_TRIGA_MANUAL_TRIG_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_TRIGB_CNTL 0x12fd
+-#define mmCRTCV0_CRTCV_TRIGB_CNTL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_TRIGB_MANUAL_TRIG 0x12fe
+-#define mmCRTCV0_CRTCV_TRIGB_MANUAL_TRIG_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL 0x12ff
+-#define mmCRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_FLOW_CONTROL 0x1300
+-#define mmCRTCV0_CRTCV_FLOW_CONTROL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE 0x1301
+-#define mmCRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_AVSYNC_COUNTER 0x1302
+-#define mmCRTCV0_CRTCV_AVSYNC_COUNTER_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_CONTROL 0x1303
+-#define mmCRTCV0_CRTCV_CONTROL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_BLANK_CONTROL 0x1304
+-#define mmCRTCV0_CRTCV_BLANK_CONTROL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_INTERLACE_CONTROL 0x1305
+-#define mmCRTCV0_CRTCV_INTERLACE_CONTROL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_INTERLACE_STATUS 0x1306
+-#define mmCRTCV0_CRTCV_INTERLACE_STATUS_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_FIELD_INDICATION_CONTROL 0x1307
+-#define mmCRTCV0_CRTCV_FIELD_INDICATION_CONTROL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK0 0x1308
+-#define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK0_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK1 0x1309
+-#define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK1_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_STATUS 0x130a
+-#define mmCRTCV0_CRTCV_STATUS_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_STATUS_POSITION 0x130b
+-#define mmCRTCV0_CRTCV_STATUS_POSITION_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_NOM_VERT_POSITION 0x130c
+-#define mmCRTCV0_CRTCV_NOM_VERT_POSITION_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_STATUS_FRAME_COUNT 0x130d
+-#define mmCRTCV0_CRTCV_STATUS_FRAME_COUNT_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_STATUS_VF_COUNT 0x130e
+-#define mmCRTCV0_CRTCV_STATUS_VF_COUNT_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_STATUS_HV_COUNT 0x130f
+-#define mmCRTCV0_CRTCV_STATUS_HV_COUNT_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_COUNT_CONTROL 0x1310
+-#define mmCRTCV0_CRTCV_COUNT_CONTROL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_COUNT_RESET 0x1311
+-#define mmCRTCV0_CRTCV_COUNT_RESET_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1312
+-#define mmCRTCV0_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_VERT_SYNC_CONTROL 0x1313
+-#define mmCRTCV0_CRTCV_VERT_SYNC_CONTROL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_STEREO_STATUS 0x1314
+-#define mmCRTCV0_CRTCV_STEREO_STATUS_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_STEREO_CONTROL 0x1315
+-#define mmCRTCV0_CRTCV_STEREO_CONTROL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_SNAPSHOT_STATUS 0x1316
+-#define mmCRTCV0_CRTCV_SNAPSHOT_STATUS_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_SNAPSHOT_CONTROL 0x1317
+-#define mmCRTCV0_CRTCV_SNAPSHOT_CONTROL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_SNAPSHOT_POSITION 0x1318
+-#define mmCRTCV0_CRTCV_SNAPSHOT_POSITION_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_SNAPSHOT_FRAME 0x1319
+-#define mmCRTCV0_CRTCV_SNAPSHOT_FRAME_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_START_LINE_CONTROL 0x131a
+-#define mmCRTCV0_CRTCV_START_LINE_CONTROL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_INTERRUPT_CONTROL 0x131b
+-#define mmCRTCV0_CRTCV_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_UPDATE_LOCK 0x131c
+-#define mmCRTCV0_CRTCV_UPDATE_LOCK_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL 0x131d
+-#define mmCRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_VGA_PARAMETER_CAPTURE_MODE 0x131e
+-#define mmCRTCV0_CRTCV_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_TEST_PATTERN_CONTROL 0x131f
+-#define mmCRTCV0_CRTCV_TEST_PATTERN_CONTROL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_TEST_PATTERN_PARAMETERS 0x1320
+-#define mmCRTCV0_CRTCV_TEST_PATTERN_PARAMETERS_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_TEST_PATTERN_COLOR 0x1321
+-#define mmCRTCV0_CRTCV_TEST_PATTERN_COLOR_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_MASTER_UPDATE_LOCK 0x1322
+-#define mmCRTCV0_CRTCV_MASTER_UPDATE_LOCK_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_MASTER_UPDATE_MODE 0x1323
+-#define mmCRTCV0_CRTCV_MASTER_UPDATE_MODE_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT 0x1324
+-#define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER 0x1325
+-#define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_MVP_STATUS 0x1326
+-#define mmCRTCV0_CRTCV_MVP_STATUS_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_MASTER_EN 0x1327
+-#define mmCRTCV0_CRTCV_MASTER_EN_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_ALLOW_STOP_OFF_V_CNT 0x1328
+-#define mmCRTCV0_CRTCV_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_V_UPDATE_INT_STATUS 0x1329
+-#define mmCRTCV0_CRTCV_V_UPDATE_INT_STATUS_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_OVERSCAN_COLOR 0x132b
+-#define mmCRTCV0_CRTCV_OVERSCAN_COLOR_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_OVERSCAN_COLOR_EXT 0x132c
+-#define mmCRTCV0_CRTCV_OVERSCAN_COLOR_EXT_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_BLANK_DATA_COLOR 0x132d
+-#define mmCRTCV0_CRTCV_BLANK_DATA_COLOR_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_BLANK_DATA_COLOR_EXT 0x132e
+-#define mmCRTCV0_CRTCV_BLANK_DATA_COLOR_EXT_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_BLACK_COLOR 0x132f
+-#define mmCRTCV0_CRTCV_BLACK_COLOR_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_BLACK_COLOR_EXT 0x1330
+-#define mmCRTCV0_CRTCV_BLACK_COLOR_EXT_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_POSITION 0x1331
+-#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL 0x1332
+-#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_POSITION 0x1333
+-#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL 0x1334
+-#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_POSITION 0x1335
+-#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL 0x1336
+-#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_CRC_CNTL 0x1337
+-#define mmCRTCV0_CRTCV_CRC_CNTL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL 0x1338
+-#define mmCRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL 0x1339
+-#define mmCRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL 0x133a
+-#define mmCRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL 0x133b
+-#define mmCRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_CRC0_DATA_RG 0x133c
+-#define mmCRTCV0_CRTCV_CRC0_DATA_RG_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_CRC0_DATA_B 0x133d
+-#define mmCRTCV0_CRTCV_CRC0_DATA_B_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL 0x133e
+-#define mmCRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL 0x133f
+-#define mmCRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL 0x1340
+-#define mmCRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL 0x1341
+-#define mmCRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_CRC1_DATA_RG 0x1342
+-#define mmCRTCV0_CRTCV_CRC1_DATA_RG_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_CRC1_DATA_B 0x1343
+-#define mmCRTCV0_CRTCV_CRC1_DATA_B_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL 0x1344
+-#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_START 0x1345
+-#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_END 0x1346
+-#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1347
+-#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1348
+-#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1349
+-#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_STATIC_SCREEN_CONTROL 0x134a
+-#define mmCRTCV0_CRTCV_STATIC_SCREEN_CONTROL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_3D_STRUCTURE_CONTROL 0x134b
+-#define mmCRTCV0_CRTCV_3D_STRUCTURE_CONTROL_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_GSL_VSYNC_GAP 0x134c
+-#define mmCRTCV0_CRTCV_GSL_VSYNC_GAP_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_GSL_WINDOW 0x134d
+-#define mmCRTCV0_CRTCV_GSL_WINDOW_BASE_IDX 2
+-#define mmCRTCV0_CRTCV_GSL_CONTROL 0x134e
+-#define mmCRTCV0_CRTCV_GSL_CONTROL_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_unp1_dispdec
+-// base address: 0x800
+-#define mmUNP1_UNP_GRPH_ENABLE 0x135a
+-#define mmUNP1_UNP_GRPH_ENABLE_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_CONTROL 0x135b
+-#define mmUNP1_UNP_GRPH_CONTROL_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_CONTROL_C 0x135c
+-#define mmUNP1_UNP_GRPH_CONTROL_C_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_CONTROL_EXP 0x135d
+-#define mmUNP1_UNP_GRPH_CONTROL_EXP_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_SWAP_CNTL 0x135e
+-#define mmUNP1_UNP_GRPH_SWAP_CNTL_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L 0x135f
+-#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C 0x1360
+-#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L 0x1361
+-#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x1362
+-#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L 0x1363
+-#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C 0x1364
+-#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x1365
+-#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x1366
+-#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L 0x1367
+-#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C 0x1368
+-#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L 0x1369
+-#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x136a
+-#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L 0x136b
+-#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C 0x136c
+-#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x136d
+-#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x136e
+-#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_PITCH_L 0x136f
+-#define mmUNP1_UNP_GRPH_PITCH_L_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_PITCH_C 0x1370
+-#define mmUNP1_UNP_GRPH_PITCH_C_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_L 0x1371
+-#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_L_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_C 0x1372
+-#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_C_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_L 0x1373
+-#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_L_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_C 0x1374
+-#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_C_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_X_START_L 0x1375
+-#define mmUNP1_UNP_GRPH_X_START_L_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_X_START_C 0x1376
+-#define mmUNP1_UNP_GRPH_X_START_C_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_Y_START_L 0x1377
+-#define mmUNP1_UNP_GRPH_Y_START_L_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_Y_START_C 0x1378
+-#define mmUNP1_UNP_GRPH_Y_START_C_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_X_END_L 0x1379
+-#define mmUNP1_UNP_GRPH_X_END_L_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_X_END_C 0x137a
+-#define mmUNP1_UNP_GRPH_X_END_C_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_Y_END_L 0x137b
+-#define mmUNP1_UNP_GRPH_Y_END_L_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_Y_END_C 0x137c
+-#define mmUNP1_UNP_GRPH_Y_END_C_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_UPDATE 0x137d
+-#define mmUNP1_UNP_GRPH_UPDATE_BASE_IDX 2
+-#define mmUNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT 0x137e
+-#define mmUNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L 0x137f
+-#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C 0x1380
+-#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L 0x1381
+-#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C 0x1382
+-#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_BASE_IDX 2
+-#define mmUNP1_UNP_DVMM_PTE_CONTROL 0x1383
+-#define mmUNP1_UNP_DVMM_PTE_CONTROL_BASE_IDX 2
+-#define mmUNP1_UNP_DVMM_PTE_CONTROL_C 0x1384
+-#define mmUNP1_UNP_DVMM_PTE_CONTROL_C_BASE_IDX 2
+-#define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL 0x1385
+-#define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL_BASE_IDX 2
+-#define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL_C 0x1386
+-#define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL_C_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_INTERRUPT_STATUS 0x1387
+-#define mmUNP1_UNP_GRPH_INTERRUPT_STATUS_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_INTERRUPT_CONTROL 0x1388
+-#define mmUNP1_UNP_GRPH_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmUNP1_UNP_GRPH_STEREOSYNC_FLIP 0x1389
+-#define mmUNP1_UNP_GRPH_STEREOSYNC_FLIP_BASE_IDX 2
+-#define mmUNP1_UNP_FLIP_CONTROL 0x138a
+-#define mmUNP1_UNP_FLIP_CONTROL_BASE_IDX 2
+-#define mmUNP1_UNP_CRC_CONTROL 0x138b
+-#define mmUNP1_UNP_CRC_CONTROL_BASE_IDX 2
+-#define mmUNP1_UNP_CRC_MASK 0x138c
+-#define mmUNP1_UNP_CRC_MASK_BASE_IDX 2
+-#define mmUNP1_UNP_CRC_CURRENT 0x138d
+-#define mmUNP1_UNP_CRC_CURRENT_BASE_IDX 2
+-#define mmUNP1_UNP_CRC_LAST 0x138e
+-#define mmUNP1_UNP_CRC_LAST_BASE_IDX 2
+-#define mmUNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK 0x138f
+-#define mmUNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2
+-#define mmUNP1_UNP_HW_ROTATION 0x1390
+-#define mmUNP1_UNP_HW_ROTATION_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_lbv1_dispdec
+-// base address: 0x800
+-#define mmLBV1_LBV_DATA_FORMAT 0x1396
+-#define mmLBV1_LBV_DATA_FORMAT_BASE_IDX 2
+-#define mmLBV1_LBV_MEMORY_CTRL 0x1397
+-#define mmLBV1_LBV_MEMORY_CTRL_BASE_IDX 2
+-#define mmLBV1_LBV_MEMORY_SIZE_STATUS 0x1398
+-#define mmLBV1_LBV_MEMORY_SIZE_STATUS_BASE_IDX 2
+-#define mmLBV1_LBV_DESKTOP_HEIGHT 0x1399
+-#define mmLBV1_LBV_DESKTOP_HEIGHT_BASE_IDX 2
+-#define mmLBV1_LBV_VLINE_START_END 0x139a
+-#define mmLBV1_LBV_VLINE_START_END_BASE_IDX 2
+-#define mmLBV1_LBV_VLINE2_START_END 0x139b
+-#define mmLBV1_LBV_VLINE2_START_END_BASE_IDX 2
+-#define mmLBV1_LBV_V_COUNTER 0x139c
+-#define mmLBV1_LBV_V_COUNTER_BASE_IDX 2
+-#define mmLBV1_LBV_SNAPSHOT_V_COUNTER 0x139d
+-#define mmLBV1_LBV_SNAPSHOT_V_COUNTER_BASE_IDX 2
+-#define mmLBV1_LBV_V_COUNTER_CHROMA 0x139e
+-#define mmLBV1_LBV_V_COUNTER_CHROMA_BASE_IDX 2
+-#define mmLBV1_LBV_SNAPSHOT_V_COUNTER_CHROMA 0x139f
+-#define mmLBV1_LBV_SNAPSHOT_V_COUNTER_CHROMA_BASE_IDX 2
+-#define mmLBV1_LBV_INTERRUPT_MASK 0x13a0
+-#define mmLBV1_LBV_INTERRUPT_MASK_BASE_IDX 2
+-#define mmLBV1_LBV_VLINE_STATUS 0x13a1
+-#define mmLBV1_LBV_VLINE_STATUS_BASE_IDX 2
+-#define mmLBV1_LBV_VLINE2_STATUS 0x13a2
+-#define mmLBV1_LBV_VLINE2_STATUS_BASE_IDX 2
+-#define mmLBV1_LBV_VBLANK_STATUS 0x13a3
+-#define mmLBV1_LBV_VBLANK_STATUS_BASE_IDX 2
+-#define mmLBV1_LBV_SYNC_RESET_SEL 0x13a4
+-#define mmLBV1_LBV_SYNC_RESET_SEL_BASE_IDX 2
+-#define mmLBV1_LBV_BLACK_KEYER_R_CR 0x13a5
+-#define mmLBV1_LBV_BLACK_KEYER_R_CR_BASE_IDX 2
+-#define mmLBV1_LBV_BLACK_KEYER_G_Y 0x13a6
+-#define mmLBV1_LBV_BLACK_KEYER_G_Y_BASE_IDX 2
+-#define mmLBV1_LBV_BLACK_KEYER_B_CB 0x13a7
+-#define mmLBV1_LBV_BLACK_KEYER_B_CB_BASE_IDX 2
+-#define mmLBV1_LBV_KEYER_COLOR_CTRL 0x13a8
+-#define mmLBV1_LBV_KEYER_COLOR_CTRL_BASE_IDX 2
+-#define mmLBV1_LBV_KEYER_COLOR_R_CR 0x13a9
+-#define mmLBV1_LBV_KEYER_COLOR_R_CR_BASE_IDX 2
+-#define mmLBV1_LBV_KEYER_COLOR_G_Y 0x13aa
+-#define mmLBV1_LBV_KEYER_COLOR_G_Y_BASE_IDX 2
+-#define mmLBV1_LBV_KEYER_COLOR_B_CB 0x13ab
+-#define mmLBV1_LBV_KEYER_COLOR_B_CB_BASE_IDX 2
+-#define mmLBV1_LBV_KEYER_COLOR_REP_R_CR 0x13ac
+-#define mmLBV1_LBV_KEYER_COLOR_REP_R_CR_BASE_IDX 2
+-#define mmLBV1_LBV_KEYER_COLOR_REP_G_Y 0x13ad
+-#define mmLBV1_LBV_KEYER_COLOR_REP_G_Y_BASE_IDX 2
+-#define mmLBV1_LBV_KEYER_COLOR_REP_B_CB 0x13ae
+-#define mmLBV1_LBV_KEYER_COLOR_REP_B_CB_BASE_IDX 2
+-#define mmLBV1_LBV_BUFFER_LEVEL_STATUS 0x13af
+-#define mmLBV1_LBV_BUFFER_LEVEL_STATUS_BASE_IDX 2
+-#define mmLBV1_LBV_BUFFER_URGENCY_CTRL 0x13b0
+-#define mmLBV1_LBV_BUFFER_URGENCY_CTRL_BASE_IDX 2
+-#define mmLBV1_LBV_BUFFER_URGENCY_STATUS 0x13b1
+-#define mmLBV1_LBV_BUFFER_URGENCY_STATUS_BASE_IDX 2
+-#define mmLBV1_LBV_BUFFER_STATUS 0x13b2
+-#define mmLBV1_LBV_BUFFER_STATUS_BASE_IDX 2
+-#define mmLBV1_LBV_NO_OUTSTANDING_REQ_STATUS 0x13b3
+-#define mmLBV1_LBV_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_sclv1_dispdec
+-// base address: 0x800
+-#define mmSCLV1_SCLV_COEF_RAM_SELECT 0x13ca
+-#define mmSCLV1_SCLV_COEF_RAM_SELECT_BASE_IDX 2
+-#define mmSCLV1_SCLV_COEF_RAM_TAP_DATA 0x13cb
+-#define mmSCLV1_SCLV_COEF_RAM_TAP_DATA_BASE_IDX 2
+-#define mmSCLV1_SCLV_MODE 0x13cc
+-#define mmSCLV1_SCLV_MODE_BASE_IDX 2
+-#define mmSCLV1_SCLV_TAP_CONTROL 0x13cd
+-#define mmSCLV1_SCLV_TAP_CONTROL_BASE_IDX 2
+-#define mmSCLV1_SCLV_CONTROL 0x13ce
+-#define mmSCLV1_SCLV_CONTROL_BASE_IDX 2
+-#define mmSCLV1_SCLV_MANUAL_REPLICATE_CONTROL 0x13cf
+-#define mmSCLV1_SCLV_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
+-#define mmSCLV1_SCLV_AUTOMATIC_MODE_CONTROL 0x13d0
+-#define mmSCLV1_SCLV_AUTOMATIC_MODE_CONTROL_BASE_IDX 2
+-#define mmSCLV1_SCLV_HORZ_FILTER_CONTROL 0x13d1
+-#define mmSCLV1_SCLV_HORZ_FILTER_CONTROL_BASE_IDX 2
+-#define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO 0x13d2
+-#define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
+-#define mmSCLV1_SCLV_HORZ_FILTER_INIT 0x13d3
+-#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BASE_IDX 2
+-#define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_C 0x13d4
+-#define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
+-#define mmSCLV1_SCLV_HORZ_FILTER_INIT_C 0x13d5
+-#define mmSCLV1_SCLV_HORZ_FILTER_INIT_C_BASE_IDX 2
+-#define mmSCLV1_SCLV_VERT_FILTER_CONTROL 0x13d6
+-#define mmSCLV1_SCLV_VERT_FILTER_CONTROL_BASE_IDX 2
+-#define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO 0x13d7
+-#define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
+-#define mmSCLV1_SCLV_VERT_FILTER_INIT 0x13d8
+-#define mmSCLV1_SCLV_VERT_FILTER_INIT_BASE_IDX 2
+-#define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT 0x13d9
+-#define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_BASE_IDX 2
+-#define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_C 0x13da
+-#define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
+-#define mmSCLV1_SCLV_VERT_FILTER_INIT_C 0x13db
+-#define mmSCLV1_SCLV_VERT_FILTER_INIT_C_BASE_IDX 2
+-#define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_C 0x13dc
+-#define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
+-#define mmSCLV1_SCLV_ROUND_OFFSET 0x13dd
+-#define mmSCLV1_SCLV_ROUND_OFFSET_BASE_IDX 2
+-#define mmSCLV1_SCLV_UPDATE 0x13de
+-#define mmSCLV1_SCLV_UPDATE_BASE_IDX 2
+-#define mmSCLV1_SCLV_ALU_CONTROL 0x13df
+-#define mmSCLV1_SCLV_ALU_CONTROL_BASE_IDX 2
+-#define mmSCLV1_SCLV_VIEWPORT_START 0x13e0
+-#define mmSCLV1_SCLV_VIEWPORT_START_BASE_IDX 2
+-#define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY 0x13e1
+-#define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_BASE_IDX 2
+-#define mmSCLV1_SCLV_VIEWPORT_SIZE 0x13e2
+-#define mmSCLV1_SCLV_VIEWPORT_SIZE_BASE_IDX 2
+-#define mmSCLV1_SCLV_VIEWPORT_START_C 0x13e3
+-#define mmSCLV1_SCLV_VIEWPORT_START_C_BASE_IDX 2
+-#define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_C 0x13e4
+-#define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_C_BASE_IDX 2
+-#define mmSCLV1_SCLV_VIEWPORT_SIZE_C 0x13e5
+-#define mmSCLV1_SCLV_VIEWPORT_SIZE_C_BASE_IDX 2
+-#define mmSCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT 0x13e6
+-#define mmSCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
+-#define mmSCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM 0x13e7
+-#define mmSCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
+-#define mmSCLV1_SCLV_MODE_CHANGE_DET1 0x13e8
+-#define mmSCLV1_SCLV_MODE_CHANGE_DET1_BASE_IDX 2
+-#define mmSCLV1_SCLV_MODE_CHANGE_DET2 0x13e9
+-#define mmSCLV1_SCLV_MODE_CHANGE_DET2_BASE_IDX 2
+-#define mmSCLV1_SCLV_MODE_CHANGE_DET3 0x13ea
+-#define mmSCLV1_SCLV_MODE_CHANGE_DET3_BASE_IDX 2
+-#define mmSCLV1_SCLV_MODE_CHANGE_MASK 0x13eb
+-#define mmSCLV1_SCLV_MODE_CHANGE_MASK_BASE_IDX 2
+-#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT 0x13ec
+-#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_BASE_IDX 2
+-#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_C 0x13ed
+-#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_C_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_col_man1_dispdec
+-// base address: 0x800
+-#define mmCOL_MAN1_COL_MAN_UPDATE 0x13fe
+-#define mmCOL_MAN1_COL_MAN_UPDATE_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_INPUT_CSC_CONTROL 0x13ff
+-#define mmCOL_MAN1_COL_MAN_INPUT_CSC_CONTROL_BASE_IDX 2
+-#define mmCOL_MAN1_INPUT_CSC_C11_C12_A 0x1400
+-#define mmCOL_MAN1_INPUT_CSC_C11_C12_A_BASE_IDX 2
+-#define mmCOL_MAN1_INPUT_CSC_C13_C14_A 0x1401
+-#define mmCOL_MAN1_INPUT_CSC_C13_C14_A_BASE_IDX 2
+-#define mmCOL_MAN1_INPUT_CSC_C21_C22_A 0x1402
+-#define mmCOL_MAN1_INPUT_CSC_C21_C22_A_BASE_IDX 2
+-#define mmCOL_MAN1_INPUT_CSC_C23_C24_A 0x1403
+-#define mmCOL_MAN1_INPUT_CSC_C23_C24_A_BASE_IDX 2
+-#define mmCOL_MAN1_INPUT_CSC_C31_C32_A 0x1404
+-#define mmCOL_MAN1_INPUT_CSC_C31_C32_A_BASE_IDX 2
+-#define mmCOL_MAN1_INPUT_CSC_C33_C34_A 0x1405
+-#define mmCOL_MAN1_INPUT_CSC_C33_C34_A_BASE_IDX 2
+-#define mmCOL_MAN1_INPUT_CSC_C11_C12_B 0x1406
+-#define mmCOL_MAN1_INPUT_CSC_C11_C12_B_BASE_IDX 2
+-#define mmCOL_MAN1_INPUT_CSC_C13_C14_B 0x1407
+-#define mmCOL_MAN1_INPUT_CSC_C13_C14_B_BASE_IDX 2
+-#define mmCOL_MAN1_INPUT_CSC_C21_C22_B 0x1408
+-#define mmCOL_MAN1_INPUT_CSC_C21_C22_B_BASE_IDX 2
+-#define mmCOL_MAN1_INPUT_CSC_C23_C24_B 0x1409
+-#define mmCOL_MAN1_INPUT_CSC_C23_C24_B_BASE_IDX 2
+-#define mmCOL_MAN1_INPUT_CSC_C31_C32_B 0x140a
+-#define mmCOL_MAN1_INPUT_CSC_C31_C32_B_BASE_IDX 2
+-#define mmCOL_MAN1_INPUT_CSC_C33_C34_B 0x140b
+-#define mmCOL_MAN1_INPUT_CSC_C33_C34_B_BASE_IDX 2
+-#define mmCOL_MAN1_PRESCALE_CONTROL 0x140c
+-#define mmCOL_MAN1_PRESCALE_CONTROL_BASE_IDX 2
+-#define mmCOL_MAN1_PRESCALE_VALUES_R 0x140d
+-#define mmCOL_MAN1_PRESCALE_VALUES_R_BASE_IDX 2
+-#define mmCOL_MAN1_PRESCALE_VALUES_G 0x140e
+-#define mmCOL_MAN1_PRESCALE_VALUES_G_BASE_IDX 2
+-#define mmCOL_MAN1_PRESCALE_VALUES_B 0x140f
+-#define mmCOL_MAN1_PRESCALE_VALUES_B_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_OUTPUT_CSC_CONTROL 0x1410
+-#define mmCOL_MAN1_COL_MAN_OUTPUT_CSC_CONTROL_BASE_IDX 2
+-#define mmCOL_MAN1_OUTPUT_CSC_C11_C12_A 0x1411
+-#define mmCOL_MAN1_OUTPUT_CSC_C11_C12_A_BASE_IDX 2
+-#define mmCOL_MAN1_OUTPUT_CSC_C13_C14_A 0x1412
+-#define mmCOL_MAN1_OUTPUT_CSC_C13_C14_A_BASE_IDX 2
+-#define mmCOL_MAN1_OUTPUT_CSC_C21_C22_A 0x1413
+-#define mmCOL_MAN1_OUTPUT_CSC_C21_C22_A_BASE_IDX 2
+-#define mmCOL_MAN1_OUTPUT_CSC_C23_C24_A 0x1414
+-#define mmCOL_MAN1_OUTPUT_CSC_C23_C24_A_BASE_IDX 2
+-#define mmCOL_MAN1_OUTPUT_CSC_C31_C32_A 0x1415
+-#define mmCOL_MAN1_OUTPUT_CSC_C31_C32_A_BASE_IDX 2
+-#define mmCOL_MAN1_OUTPUT_CSC_C33_C34_A 0x1416
+-#define mmCOL_MAN1_OUTPUT_CSC_C33_C34_A_BASE_IDX 2
+-#define mmCOL_MAN1_OUTPUT_CSC_C11_C12_B 0x1417
+-#define mmCOL_MAN1_OUTPUT_CSC_C11_C12_B_BASE_IDX 2
+-#define mmCOL_MAN1_OUTPUT_CSC_C13_C14_B 0x1418
+-#define mmCOL_MAN1_OUTPUT_CSC_C13_C14_B_BASE_IDX 2
+-#define mmCOL_MAN1_OUTPUT_CSC_C21_C22_B 0x1419
+-#define mmCOL_MAN1_OUTPUT_CSC_C21_C22_B_BASE_IDX 2
+-#define mmCOL_MAN1_OUTPUT_CSC_C23_C24_B 0x141a
+-#define mmCOL_MAN1_OUTPUT_CSC_C23_C24_B_BASE_IDX 2
+-#define mmCOL_MAN1_OUTPUT_CSC_C31_C32_B 0x141b
+-#define mmCOL_MAN1_OUTPUT_CSC_C31_C32_B_BASE_IDX 2
+-#define mmCOL_MAN1_OUTPUT_CSC_C33_C34_B 0x141c
+-#define mmCOL_MAN1_OUTPUT_CSC_C33_C34_B_BASE_IDX 2
+-#define mmCOL_MAN1_DENORM_CLAMP_CONTROL 0x141d
+-#define mmCOL_MAN1_DENORM_CLAMP_CONTROL_BASE_IDX 2
+-#define mmCOL_MAN1_DENORM_CLAMP_RANGE_R_CR 0x141e
+-#define mmCOL_MAN1_DENORM_CLAMP_RANGE_R_CR_BASE_IDX 2
+-#define mmCOL_MAN1_DENORM_CLAMP_RANGE_G_Y 0x141f
+-#define mmCOL_MAN1_DENORM_CLAMP_RANGE_G_Y_BASE_IDX 2
+-#define mmCOL_MAN1_DENORM_CLAMP_RANGE_B_CB 0x1420
+-#define mmCOL_MAN1_DENORM_CLAMP_RANGE_B_CB_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_FP_CONVERTED_FIELD 0x1421
+-#define mmCOL_MAN1_COL_MAN_FP_CONVERTED_FIELD_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CONTROL 0x1422
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CONTROL_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_INDEX 0x1423
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_INDEX_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_DATA 0x1424
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_DATA_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK 0x1425
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_START_CNTL 0x1426
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL 0x1427
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL1 0x1428
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL2 0x1429
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1 0x142a
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3 0x142b
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5 0x142c
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7 0x142d
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9 0x142e
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11 0x142f
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13 0x1430
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15 0x1431
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_START_CNTL 0x1432
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL 0x1433
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL1 0x1434
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL2 0x1435
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1 0x1436
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3 0x1437
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5 0x1438
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7 0x1439
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9 0x143a
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11 0x143b
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13 0x143c
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15 0x143d
+-#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2
+-#define mmCOL_MAN1_PACK_FIFO_ERROR 0x143e
+-#define mmCOL_MAN1_PACK_FIFO_ERROR_BASE_IDX 2
+-#define mmCOL_MAN1_OUTPUT_FIFO_ERROR 0x143f
+-#define mmCOL_MAN1_OUTPUT_FIFO_ERROR_BASE_IDX 2
+-#define mmCOL_MAN1_INPUT_GAMMA_LUT_AUTOFILL 0x1440
+-#define mmCOL_MAN1_INPUT_GAMMA_LUT_AUTOFILL_BASE_IDX 2
+-#define mmCOL_MAN1_INPUT_GAMMA_LUT_RW_INDEX 0x1441
+-#define mmCOL_MAN1_INPUT_GAMMA_LUT_RW_INDEX_BASE_IDX 2
+-#define mmCOL_MAN1_INPUT_GAMMA_LUT_SEQ_COLOR 0x1442
+-#define mmCOL_MAN1_INPUT_GAMMA_LUT_SEQ_COLOR_BASE_IDX 2
+-#define mmCOL_MAN1_INPUT_GAMMA_LUT_PWL_DATA 0x1443
+-#define mmCOL_MAN1_INPUT_GAMMA_LUT_PWL_DATA_BASE_IDX 2
+-#define mmCOL_MAN1_INPUT_GAMMA_LUT_30_COLOR 0x1444
+-#define mmCOL_MAN1_INPUT_GAMMA_LUT_30_COLOR_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1 0x1445
+-#define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2 0x1446
+-#define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2_BASE_IDX 2
+-#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_B 0x1447
+-#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_B_BASE_IDX 2
+-#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_G 0x1448
+-#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_G_BASE_IDX 2
+-#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_R 0x1449
+-#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_R_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_DEGAMMA_CONTROL 0x144a
+-#define mmCOL_MAN1_COL_MAN_DEGAMMA_CONTROL_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_CONTROL 0x144b
+-#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_CONTROL_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C11_C12 0x144c
+-#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C11_C12_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C13_C14 0x144d
+-#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C13_C14_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C21_C22 0x144e
+-#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C21_C22_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C23_C24 0x144f
+-#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C23_C24_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C31_C32 0x1450
+-#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C31_C32_BASE_IDX 2
+-#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C33_C34 0x1451
+-#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C33_C34_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dcfev1_dispdec
+-// base address: 0x800
+-#define mmDCFEV1_DCFEV_CLOCK_CONTROL 0x147e
+-#define mmDCFEV1_DCFEV_CLOCK_CONTROL_BASE_IDX 2
+-#define mmDCFEV1_DCFEV_SOFT_RESET 0x147f
+-#define mmDCFEV1_DCFEV_SOFT_RESET_BASE_IDX 2
+-#define mmDCFEV1_DCFEV_DMIFV_CLOCK_CONTROL 0x1480
+-#define mmDCFEV1_DCFEV_DMIFV_CLOCK_CONTROL_BASE_IDX 2
+-#define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL 0x1482
+-#define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL_BASE_IDX 2
+-#define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS 0x1483
+-#define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS_BASE_IDX 2
+-#define mmDCFEV1_DCFEV_MEM_PWR_CTRL 0x1484
+-#define mmDCFEV1_DCFEV_MEM_PWR_CTRL_BASE_IDX 2
+-#define mmDCFEV1_DCFEV_MEM_PWR_CTRL2 0x1485
+-#define mmDCFEV1_DCFEV_MEM_PWR_CTRL2_BASE_IDX 2
+-#define mmDCFEV1_DCFEV_MEM_PWR_STATUS 0x1486
+-#define mmDCFEV1_DCFEV_MEM_PWR_STATUS_BASE_IDX 2
+-#define mmDCFEV1_DCFEV_L_FLUSH 0x1487
+-#define mmDCFEV1_DCFEV_L_FLUSH_BASE_IDX 2
+-#define mmDCFEV1_DCFEV_C_FLUSH 0x1488
+-#define mmDCFEV1_DCFEV_C_FLUSH_BASE_IDX 2
+-#define mmDCFEV1_DCFEV_MISC 0x148a
+-#define mmDCFEV1_DCFEV_MISC_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dc_perfmon12_dispdec
+-// base address: 0x51c8
+-#define mmDC_PERFMON12_PERFCOUNTER_CNTL 0x1492
+-#define mmDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX 2
+-#define mmDC_PERFMON12_PERFCOUNTER_CNTL2 0x1493
+-#define mmDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX 2
+-#define mmDC_PERFMON12_PERFCOUNTER_STATE 0x1494
+-#define mmDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX 2
+-#define mmDC_PERFMON12_PERFMON_CNTL 0x1495
+-#define mmDC_PERFMON12_PERFMON_CNTL_BASE_IDX 2
+-#define mmDC_PERFMON12_PERFMON_CNTL2 0x1496
+-#define mmDC_PERFMON12_PERFMON_CNTL2_BASE_IDX 2
+-#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0x1497
+-#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+-#define mmDC_PERFMON12_PERFMON_CVALUE_LOW 0x1498
+-#define mmDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX 2
+-#define mmDC_PERFMON12_PERFMON_HI 0x1499
+-#define mmDC_PERFMON12_PERFMON_HI_BASE_IDX 2
+-#define mmDC_PERFMON12_PERFMON_LOW 0x149a
+-#define mmDC_PERFMON12_PERFMON_LOW_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dmifv_pg1_dispdec
+-// base address: 0x800
+-#define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1 0x149e
+-#define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
+-#define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2 0x149f
+-#define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
+-#define mmDMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL 0x14a0
+-#define mmDMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL_BASE_IDX 2
+-#define mmDMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL 0x14a1
+-#define mmDMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL_BASE_IDX 2
+-#define mmDMIFV_PG1_DPGV0_PIPE_DPM_CONTROL 0x14a2
+-#define mmDMIFV_PG1_DPGV0_PIPE_DPM_CONTROL_BASE_IDX 2
+-#define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL 0x14a3
+-#define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_BASE_IDX 2
+-#define mmDMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL 0x14a4
+-#define mmDMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL_BASE_IDX 2
+-#define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH 0x14a5
+-#define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH_BASE_IDX 2
+-#define mmDMIFV_PG1_DPGV0_REPEATER_PROGRAM 0x14a6
+-#define mmDMIFV_PG1_DPGV0_REPEATER_PROGRAM_BASE_IDX 2
+-#define mmDMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL 0x14aa
+-#define mmDMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL_BASE_IDX 2
+-#define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1 0x14ab
+-#define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
+-#define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2 0x14ac
+-#define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
+-#define mmDMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL 0x14ad
+-#define mmDMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL_BASE_IDX 2
+-#define mmDMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL 0x14ae
+-#define mmDMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL_BASE_IDX 2
+-#define mmDMIFV_PG1_DPGV1_PIPE_DPM_CONTROL 0x14af
+-#define mmDMIFV_PG1_DPGV1_PIPE_DPM_CONTROL_BASE_IDX 2
+-#define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL 0x14b0
+-#define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_BASE_IDX 2
+-#define mmDMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL 0x14b1
+-#define mmDMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL_BASE_IDX 2
+-#define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH 0x14b2
+-#define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH_BASE_IDX 2
+-#define mmDMIFV_PG1_DPGV1_REPEATER_PROGRAM 0x14b3
+-#define mmDMIFV_PG1_DPGV1_REPEATER_PROGRAM_BASE_IDX 2
+-#define mmDMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL 0x14b7
+-#define mmDMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_blndv1_dispdec
+-// base address: 0x800
+-#define mmBLNDV1_BLNDV_CONTROL 0x14db
+-#define mmBLNDV1_BLNDV_CONTROL_BASE_IDX 2
+-#define mmBLNDV1_BLNDV_SM_CONTROL2 0x14dc
+-#define mmBLNDV1_BLNDV_SM_CONTROL2_BASE_IDX 2
+-#define mmBLNDV1_BLNDV_CONTROL2 0x14dd
+-#define mmBLNDV1_BLNDV_CONTROL2_BASE_IDX 2
+-#define mmBLNDV1_BLNDV_UPDATE 0x14de
+-#define mmBLNDV1_BLNDV_UPDATE_BASE_IDX 2
+-#define mmBLNDV1_BLNDV_UNDERFLOW_INTERRUPT 0x14df
+-#define mmBLNDV1_BLNDV_UNDERFLOW_INTERRUPT_BASE_IDX 2
+-#define mmBLNDV1_BLNDV_V_UPDATE_LOCK 0x14e0
+-#define mmBLNDV1_BLNDV_V_UPDATE_LOCK_BASE_IDX 2
+-#define mmBLNDV1_BLNDV_REG_UPDATE_STATUS 0x14e1
+-#define mmBLNDV1_BLNDV_REG_UPDATE_STATUS_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_crtcv1_dispdec
+-// base address: 0x800
+-#define mmCRTCV1_CRTCV_H_BLANK_EARLY_NUM 0x14e6
+-#define mmCRTCV1_CRTCV_H_BLANK_EARLY_NUM_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_H_TOTAL 0x14e7
+-#define mmCRTCV1_CRTCV_H_TOTAL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_H_BLANK_START_END 0x14e8
+-#define mmCRTCV1_CRTCV_H_BLANK_START_END_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_H_SYNC_A 0x14e9
+-#define mmCRTCV1_CRTCV_H_SYNC_A_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_H_SYNC_A_CNTL 0x14ea
+-#define mmCRTCV1_CRTCV_H_SYNC_A_CNTL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_H_SYNC_B 0x14eb
+-#define mmCRTCV1_CRTCV_H_SYNC_B_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_H_SYNC_B_CNTL 0x14ec
+-#define mmCRTCV1_CRTCV_H_SYNC_B_CNTL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_VBI_END 0x14ed
+-#define mmCRTCV1_CRTCV_VBI_END_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_V_TOTAL 0x14ee
+-#define mmCRTCV1_CRTCV_V_TOTAL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_V_TOTAL_MIN 0x14ef
+-#define mmCRTCV1_CRTCV_V_TOTAL_MIN_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_V_TOTAL_MAX 0x14f0
+-#define mmCRTCV1_CRTCV_V_TOTAL_MAX_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_V_TOTAL_CONTROL 0x14f1
+-#define mmCRTCV1_CRTCV_V_TOTAL_CONTROL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_V_TOTAL_INT_STATUS 0x14f2
+-#define mmCRTCV1_CRTCV_V_TOTAL_INT_STATUS_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_VSYNC_NOM_INT_STATUS 0x14f3
+-#define mmCRTCV1_CRTCV_VSYNC_NOM_INT_STATUS_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_V_BLANK_START_END 0x14f4
+-#define mmCRTCV1_CRTCV_V_BLANK_START_END_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_V_SYNC_A 0x14f5
+-#define mmCRTCV1_CRTCV_V_SYNC_A_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_V_SYNC_A_CNTL 0x14f6
+-#define mmCRTCV1_CRTCV_V_SYNC_A_CNTL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_V_SYNC_B 0x14f7
+-#define mmCRTCV1_CRTCV_V_SYNC_B_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_V_SYNC_B_CNTL 0x14f8
+-#define mmCRTCV1_CRTCV_V_SYNC_B_CNTL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_DTMTEST_CNTL 0x14f9
+-#define mmCRTCV1_CRTCV_DTMTEST_CNTL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_DTMTEST_STATUS_POSITION 0x14fa
+-#define mmCRTCV1_CRTCV_DTMTEST_STATUS_POSITION_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_TRIGA_CNTL 0x14fb
+-#define mmCRTCV1_CRTCV_TRIGA_CNTL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_TRIGA_MANUAL_TRIG 0x14fc
+-#define mmCRTCV1_CRTCV_TRIGA_MANUAL_TRIG_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_TRIGB_CNTL 0x14fd
+-#define mmCRTCV1_CRTCV_TRIGB_CNTL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_TRIGB_MANUAL_TRIG 0x14fe
+-#define mmCRTCV1_CRTCV_TRIGB_MANUAL_TRIG_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL 0x14ff
+-#define mmCRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_FLOW_CONTROL 0x1500
+-#define mmCRTCV1_CRTCV_FLOW_CONTROL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE 0x1501
+-#define mmCRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_AVSYNC_COUNTER 0x1502
+-#define mmCRTCV1_CRTCV_AVSYNC_COUNTER_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_CONTROL 0x1503
+-#define mmCRTCV1_CRTCV_CONTROL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_BLANK_CONTROL 0x1504
+-#define mmCRTCV1_CRTCV_BLANK_CONTROL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_INTERLACE_CONTROL 0x1505
+-#define mmCRTCV1_CRTCV_INTERLACE_CONTROL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_INTERLACE_STATUS 0x1506
+-#define mmCRTCV1_CRTCV_INTERLACE_STATUS_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_FIELD_INDICATION_CONTROL 0x1507
+-#define mmCRTCV1_CRTCV_FIELD_INDICATION_CONTROL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK0 0x1508
+-#define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK0_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK1 0x1509
+-#define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK1_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_STATUS 0x150a
+-#define mmCRTCV1_CRTCV_STATUS_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_STATUS_POSITION 0x150b
+-#define mmCRTCV1_CRTCV_STATUS_POSITION_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_NOM_VERT_POSITION 0x150c
+-#define mmCRTCV1_CRTCV_NOM_VERT_POSITION_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_STATUS_FRAME_COUNT 0x150d
+-#define mmCRTCV1_CRTCV_STATUS_FRAME_COUNT_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_STATUS_VF_COUNT 0x150e
+-#define mmCRTCV1_CRTCV_STATUS_VF_COUNT_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_STATUS_HV_COUNT 0x150f
+-#define mmCRTCV1_CRTCV_STATUS_HV_COUNT_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_COUNT_CONTROL 0x1510
+-#define mmCRTCV1_CRTCV_COUNT_CONTROL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_COUNT_RESET 0x1511
+-#define mmCRTCV1_CRTCV_COUNT_RESET_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1512
+-#define mmCRTCV1_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_VERT_SYNC_CONTROL 0x1513
+-#define mmCRTCV1_CRTCV_VERT_SYNC_CONTROL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_STEREO_STATUS 0x1514
+-#define mmCRTCV1_CRTCV_STEREO_STATUS_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_STEREO_CONTROL 0x1515
+-#define mmCRTCV1_CRTCV_STEREO_CONTROL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_SNAPSHOT_STATUS 0x1516
+-#define mmCRTCV1_CRTCV_SNAPSHOT_STATUS_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_SNAPSHOT_CONTROL 0x1517
+-#define mmCRTCV1_CRTCV_SNAPSHOT_CONTROL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_SNAPSHOT_POSITION 0x1518
+-#define mmCRTCV1_CRTCV_SNAPSHOT_POSITION_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_SNAPSHOT_FRAME 0x1519
+-#define mmCRTCV1_CRTCV_SNAPSHOT_FRAME_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_START_LINE_CONTROL 0x151a
+-#define mmCRTCV1_CRTCV_START_LINE_CONTROL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_INTERRUPT_CONTROL 0x151b
+-#define mmCRTCV1_CRTCV_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_UPDATE_LOCK 0x151c
+-#define mmCRTCV1_CRTCV_UPDATE_LOCK_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL 0x151d
+-#define mmCRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_VGA_PARAMETER_CAPTURE_MODE 0x151e
+-#define mmCRTCV1_CRTCV_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_TEST_PATTERN_CONTROL 0x151f
+-#define mmCRTCV1_CRTCV_TEST_PATTERN_CONTROL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_TEST_PATTERN_PARAMETERS 0x1520
+-#define mmCRTCV1_CRTCV_TEST_PATTERN_PARAMETERS_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_TEST_PATTERN_COLOR 0x1521
+-#define mmCRTCV1_CRTCV_TEST_PATTERN_COLOR_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_MASTER_UPDATE_LOCK 0x1522
+-#define mmCRTCV1_CRTCV_MASTER_UPDATE_LOCK_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_MASTER_UPDATE_MODE 0x1523
+-#define mmCRTCV1_CRTCV_MASTER_UPDATE_MODE_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT 0x1524
+-#define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER 0x1525
+-#define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_MVP_STATUS 0x1526
+-#define mmCRTCV1_CRTCV_MVP_STATUS_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_MASTER_EN 0x1527
+-#define mmCRTCV1_CRTCV_MASTER_EN_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_ALLOW_STOP_OFF_V_CNT 0x1528
+-#define mmCRTCV1_CRTCV_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_V_UPDATE_INT_STATUS 0x1529
+-#define mmCRTCV1_CRTCV_V_UPDATE_INT_STATUS_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_OVERSCAN_COLOR 0x152b
+-#define mmCRTCV1_CRTCV_OVERSCAN_COLOR_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_OVERSCAN_COLOR_EXT 0x152c
+-#define mmCRTCV1_CRTCV_OVERSCAN_COLOR_EXT_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_BLANK_DATA_COLOR 0x152d
+-#define mmCRTCV1_CRTCV_BLANK_DATA_COLOR_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_BLANK_DATA_COLOR_EXT 0x152e
+-#define mmCRTCV1_CRTCV_BLANK_DATA_COLOR_EXT_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_BLACK_COLOR 0x152f
+-#define mmCRTCV1_CRTCV_BLACK_COLOR_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_BLACK_COLOR_EXT 0x1530
+-#define mmCRTCV1_CRTCV_BLACK_COLOR_EXT_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_POSITION 0x1531
+-#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL 0x1532
+-#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_POSITION 0x1533
+-#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL 0x1534
+-#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_POSITION 0x1535
+-#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL 0x1536
+-#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_CRC_CNTL 0x1537
+-#define mmCRTCV1_CRTCV_CRC_CNTL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL 0x1538
+-#define mmCRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL 0x1539
+-#define mmCRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL 0x153a
+-#define mmCRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL 0x153b
+-#define mmCRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_CRC0_DATA_RG 0x153c
+-#define mmCRTCV1_CRTCV_CRC0_DATA_RG_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_CRC0_DATA_B 0x153d
+-#define mmCRTCV1_CRTCV_CRC0_DATA_B_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL 0x153e
+-#define mmCRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL 0x153f
+-#define mmCRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL 0x1540
+-#define mmCRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL 0x1541
+-#define mmCRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_CRC1_DATA_RG 0x1542
+-#define mmCRTCV1_CRTCV_CRC1_DATA_RG_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_CRC1_DATA_B 0x1543
+-#define mmCRTCV1_CRTCV_CRC1_DATA_B_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL 0x1544
+-#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_START 0x1545
+-#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_END 0x1546
+-#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1547
+-#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1548
+-#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1549
+-#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_STATIC_SCREEN_CONTROL 0x154a
+-#define mmCRTCV1_CRTCV_STATIC_SCREEN_CONTROL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_3D_STRUCTURE_CONTROL 0x154b
+-#define mmCRTCV1_CRTCV_3D_STRUCTURE_CONTROL_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_GSL_VSYNC_GAP 0x154c
+-#define mmCRTCV1_CRTCV_GSL_VSYNC_GAP_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_GSL_WINDOW 0x154d
+-#define mmCRTCV1_CRTCV_GSL_WINDOW_BASE_IDX 2
+-#define mmCRTCV1_CRTCV_GSL_CONTROL 0x154e
+-#define mmCRTCV1_CRTCV_GSL_CONTROL_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_hpd0_dispdec
+-// base address: 0x0
+-#define mmHPD0_DC_HPD_INT_STATUS 0x1600
+-#define mmHPD0_DC_HPD_INT_STATUS_BASE_IDX 2
+-#define mmHPD0_DC_HPD_INT_CONTROL 0x1601
+-#define mmHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2
+-#define mmHPD0_DC_HPD_CONTROL 0x1602
+-#define mmHPD0_DC_HPD_CONTROL_BASE_IDX 2
+-#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0x1603
+-#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
+-#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x1604
+-#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_hpd1_dispdec
+-// base address: 0x20
+-#define mmHPD1_DC_HPD_INT_STATUS 0x1608
+-#define mmHPD1_DC_HPD_INT_STATUS_BASE_IDX 2
+-#define mmHPD1_DC_HPD_INT_CONTROL 0x1609
+-#define mmHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2
+-#define mmHPD1_DC_HPD_CONTROL 0x160a
+-#define mmHPD1_DC_HPD_CONTROL_BASE_IDX 2
+-#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0x160b
+-#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
+-#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x160c
+-#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_hpd2_dispdec
+-// base address: 0x40
+-#define mmHPD2_DC_HPD_INT_STATUS 0x1610
+-#define mmHPD2_DC_HPD_INT_STATUS_BASE_IDX 2
+-#define mmHPD2_DC_HPD_INT_CONTROL 0x1611
+-#define mmHPD2_DC_HPD_INT_CONTROL_BASE_IDX 2
+-#define mmHPD2_DC_HPD_CONTROL 0x1612
+-#define mmHPD2_DC_HPD_CONTROL_BASE_IDX 2
+-#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL 0x1613
+-#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
+-#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x1614
+-#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_hpd3_dispdec
+-// base address: 0x60
+-#define mmHPD3_DC_HPD_INT_STATUS 0x1618
+-#define mmHPD3_DC_HPD_INT_STATUS_BASE_IDX 2
+-#define mmHPD3_DC_HPD_INT_CONTROL 0x1619
+-#define mmHPD3_DC_HPD_INT_CONTROL_BASE_IDX 2
+-#define mmHPD3_DC_HPD_CONTROL 0x161a
+-#define mmHPD3_DC_HPD_CONTROL_BASE_IDX 2
+-#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL 0x161b
+-#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
+-#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x161c
+-#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_hpd4_dispdec
+-// base address: 0x80
+-#define mmHPD4_DC_HPD_INT_STATUS 0x1620
+-#define mmHPD4_DC_HPD_INT_STATUS_BASE_IDX 2
+-#define mmHPD4_DC_HPD_INT_CONTROL 0x1621
+-#define mmHPD4_DC_HPD_INT_CONTROL_BASE_IDX 2
+-#define mmHPD4_DC_HPD_CONTROL 0x1622
+-#define mmHPD4_DC_HPD_CONTROL_BASE_IDX 2
+-#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL 0x1623
+-#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
+-#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x1624
+-#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_hpd5_dispdec
+-// base address: 0xa0
+-#define mmHPD5_DC_HPD_INT_STATUS 0x1628
+-#define mmHPD5_DC_HPD_INT_STATUS_BASE_IDX 2
+-#define mmHPD5_DC_HPD_INT_CONTROL 0x1629
+-#define mmHPD5_DC_HPD_INT_CONTROL_BASE_IDX 2
+-#define mmHPD5_DC_HPD_CONTROL 0x162a
+-#define mmHPD5_DC_HPD_CONTROL_BASE_IDX 2
+-#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL 0x162b
+-#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
+-#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL 0x162c
+-#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dc_perfmon2_dispdec
+-// base address: 0x5840
+-#define mmDC_PERFMON2_PERFCOUNTER_CNTL 0x1630
+-#define mmDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX 2
+-#define mmDC_PERFMON2_PERFCOUNTER_CNTL2 0x1631
+-#define mmDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX 2
+-#define mmDC_PERFMON2_PERFCOUNTER_STATE 0x1632
+-#define mmDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX 2
+-#define mmDC_PERFMON2_PERFMON_CNTL 0x1633
+-#define mmDC_PERFMON2_PERFMON_CNTL_BASE_IDX 2
+-#define mmDC_PERFMON2_PERFMON_CNTL2 0x1634
+-#define mmDC_PERFMON2_PERFMON_CNTL2_BASE_IDX 2
+-#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x1635
+-#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+-#define mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x1636
+-#define mmDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX 2
+-#define mmDC_PERFMON2_PERFMON_HI 0x1637
+-#define mmDC_PERFMON2_PERFMON_HI_BASE_IDX 2
+-#define mmDC_PERFMON2_PERFMON_LOW 0x1638
+-#define mmDC_PERFMON2_PERFMON_LOW_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dp_aux0_dispdec
+-// base address: 0x0
+-#define mmDP_AUX0_AUX_CONTROL 0x1766
+-#define mmDP_AUX0_AUX_CONTROL_BASE_IDX 2
+-#define mmDP_AUX0_AUX_SW_CONTROL 0x1767
+-#define mmDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2
+-#define mmDP_AUX0_AUX_ARB_CONTROL 0x1768
+-#define mmDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2
+-#define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x1769
+-#define mmDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmDP_AUX0_AUX_SW_STATUS 0x176a
+-#define mmDP_AUX0_AUX_SW_STATUS_BASE_IDX 2
+-#define mmDP_AUX0_AUX_LS_STATUS 0x176b
+-#define mmDP_AUX0_AUX_LS_STATUS_BASE_IDX 2
+-#define mmDP_AUX0_AUX_SW_DATA 0x176c
+-#define mmDP_AUX0_AUX_SW_DATA_BASE_IDX 2
+-#define mmDP_AUX0_AUX_LS_DATA 0x176d
+-#define mmDP_AUX0_AUX_LS_DATA_BASE_IDX 2
+-#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x176e
+-#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
+-#define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x176f
+-#define mmDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2
+-#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x1770
+-#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
+-#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x1771
+-#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
+-#define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x1772
+-#define mmDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2
+-#define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x1773
+-#define mmDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2
+-#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x1775
+-#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
+-#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1776
+-#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
+-#define mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x1777
+-#define mmDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dp_aux1_dispdec
+-// base address: 0x70
+-#define mmDP_AUX1_AUX_CONTROL 0x1782
+-#define mmDP_AUX1_AUX_CONTROL_BASE_IDX 2
+-#define mmDP_AUX1_AUX_SW_CONTROL 0x1783
+-#define mmDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2
+-#define mmDP_AUX1_AUX_ARB_CONTROL 0x1784
+-#define mmDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2
+-#define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x1785
+-#define mmDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmDP_AUX1_AUX_SW_STATUS 0x1786
+-#define mmDP_AUX1_AUX_SW_STATUS_BASE_IDX 2
+-#define mmDP_AUX1_AUX_LS_STATUS 0x1787
+-#define mmDP_AUX1_AUX_LS_STATUS_BASE_IDX 2
+-#define mmDP_AUX1_AUX_SW_DATA 0x1788
+-#define mmDP_AUX1_AUX_SW_DATA_BASE_IDX 2
+-#define mmDP_AUX1_AUX_LS_DATA 0x1789
+-#define mmDP_AUX1_AUX_LS_DATA_BASE_IDX 2
+-#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x178a
+-#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
+-#define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x178b
+-#define mmDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2
+-#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x178c
+-#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
+-#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x178d
+-#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
+-#define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x178e
+-#define mmDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2
+-#define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x178f
+-#define mmDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2
+-#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x1791
+-#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
+-#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1792
+-#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
+-#define mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x1793
+-#define mmDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dp_aux2_dispdec
+-// base address: 0xe0
+-#define mmDP_AUX2_AUX_CONTROL 0x179e
+-#define mmDP_AUX2_AUX_CONTROL_BASE_IDX 2
+-#define mmDP_AUX2_AUX_SW_CONTROL 0x179f
+-#define mmDP_AUX2_AUX_SW_CONTROL_BASE_IDX 2
+-#define mmDP_AUX2_AUX_ARB_CONTROL 0x17a0
+-#define mmDP_AUX2_AUX_ARB_CONTROL_BASE_IDX 2
+-#define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x17a1
+-#define mmDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmDP_AUX2_AUX_SW_STATUS 0x17a2
+-#define mmDP_AUX2_AUX_SW_STATUS_BASE_IDX 2
+-#define mmDP_AUX2_AUX_LS_STATUS 0x17a3
+-#define mmDP_AUX2_AUX_LS_STATUS_BASE_IDX 2
+-#define mmDP_AUX2_AUX_SW_DATA 0x17a4
+-#define mmDP_AUX2_AUX_SW_DATA_BASE_IDX 2
+-#define mmDP_AUX2_AUX_LS_DATA 0x17a5
+-#define mmDP_AUX2_AUX_LS_DATA_BASE_IDX 2
+-#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x17a6
+-#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
+-#define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x17a7
+-#define mmDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX 2
+-#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x17a8
+-#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
+-#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x17a9
+-#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
+-#define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x17aa
+-#define mmDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX 2
+-#define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x17ab
+-#define mmDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX 2
+-#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x17ad
+-#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
+-#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x17ae
+-#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
+-#define mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x17af
+-#define mmDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dp_aux3_dispdec
+-// base address: 0x150
+-#define mmDP_AUX3_AUX_CONTROL 0x17ba
+-#define mmDP_AUX3_AUX_CONTROL_BASE_IDX 2
+-#define mmDP_AUX3_AUX_SW_CONTROL 0x17bb
+-#define mmDP_AUX3_AUX_SW_CONTROL_BASE_IDX 2
+-#define mmDP_AUX3_AUX_ARB_CONTROL 0x17bc
+-#define mmDP_AUX3_AUX_ARB_CONTROL_BASE_IDX 2
+-#define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x17bd
+-#define mmDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmDP_AUX3_AUX_SW_STATUS 0x17be
+-#define mmDP_AUX3_AUX_SW_STATUS_BASE_IDX 2
+-#define mmDP_AUX3_AUX_LS_STATUS 0x17bf
+-#define mmDP_AUX3_AUX_LS_STATUS_BASE_IDX 2
+-#define mmDP_AUX3_AUX_SW_DATA 0x17c0
+-#define mmDP_AUX3_AUX_SW_DATA_BASE_IDX 2
+-#define mmDP_AUX3_AUX_LS_DATA 0x17c1
+-#define mmDP_AUX3_AUX_LS_DATA_BASE_IDX 2
+-#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x17c2
+-#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
+-#define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x17c3
+-#define mmDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX 2
+-#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x17c4
+-#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
+-#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x17c5
+-#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
+-#define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x17c6
+-#define mmDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX 2
+-#define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x17c7
+-#define mmDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX 2
+-#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x17c9
+-#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
+-#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x17ca
+-#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
+-#define mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x17cb
+-#define mmDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dp_aux4_dispdec
+-// base address: 0x1c0
+-#define mmDP_AUX4_AUX_CONTROL 0x17d6
+-#define mmDP_AUX4_AUX_CONTROL_BASE_IDX 2
+-#define mmDP_AUX4_AUX_SW_CONTROL 0x17d7
+-#define mmDP_AUX4_AUX_SW_CONTROL_BASE_IDX 2
+-#define mmDP_AUX4_AUX_ARB_CONTROL 0x17d8
+-#define mmDP_AUX4_AUX_ARB_CONTROL_BASE_IDX 2
+-#define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x17d9
+-#define mmDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmDP_AUX4_AUX_SW_STATUS 0x17da
+-#define mmDP_AUX4_AUX_SW_STATUS_BASE_IDX 2
+-#define mmDP_AUX4_AUX_LS_STATUS 0x17db
+-#define mmDP_AUX4_AUX_LS_STATUS_BASE_IDX 2
+-#define mmDP_AUX4_AUX_SW_DATA 0x17dc
+-#define mmDP_AUX4_AUX_SW_DATA_BASE_IDX 2
+-#define mmDP_AUX4_AUX_LS_DATA 0x17dd
+-#define mmDP_AUX4_AUX_LS_DATA_BASE_IDX 2
+-#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x17de
+-#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
+-#define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x17df
+-#define mmDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX 2
+-#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x17e0
+-#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
+-#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x17e1
+-#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
+-#define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x17e2
+-#define mmDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX 2
+-#define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x17e3
+-#define mmDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX 2
+-#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x17e5
+-#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
+-#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x17e6
+-#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
+-#define mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x17e7
+-#define mmDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dp_aux5_dispdec
+-// base address: 0x230
+-#define mmDP_AUX5_AUX_CONTROL 0x17f2
+-#define mmDP_AUX5_AUX_CONTROL_BASE_IDX 2
+-#define mmDP_AUX5_AUX_SW_CONTROL 0x17f3
+-#define mmDP_AUX5_AUX_SW_CONTROL_BASE_IDX 2
+-#define mmDP_AUX5_AUX_ARB_CONTROL 0x17f4
+-#define mmDP_AUX5_AUX_ARB_CONTROL_BASE_IDX 2
+-#define mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x17f5
+-#define mmDP_AUX5_AUX_INTERRUPT_CONTROL_BASE_IDX 2
+-#define mmDP_AUX5_AUX_SW_STATUS 0x17f6
+-#define mmDP_AUX5_AUX_SW_STATUS_BASE_IDX 2
+-#define mmDP_AUX5_AUX_LS_STATUS 0x17f7
+-#define mmDP_AUX5_AUX_LS_STATUS_BASE_IDX 2
+-#define mmDP_AUX5_AUX_SW_DATA 0x17f8
+-#define mmDP_AUX5_AUX_SW_DATA_BASE_IDX 2
+-#define mmDP_AUX5_AUX_LS_DATA 0x17f9
+-#define mmDP_AUX5_AUX_LS_DATA_BASE_IDX 2
+-#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x17fa
+-#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
+-#define mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x17fb
+-#define mmDP_AUX5_AUX_DPHY_TX_CONTROL_BASE_IDX 2
+-#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x17fc
+-#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
+-#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x17fd
+-#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
+-#define mmDP_AUX5_AUX_DPHY_TX_STATUS 0x17fe
+-#define mmDP_AUX5_AUX_DPHY_TX_STATUS_BASE_IDX 2
+-#define mmDP_AUX5_AUX_DPHY_RX_STATUS 0x17ff
+-#define mmDP_AUX5_AUX_DPHY_RX_STATUS_BASE_IDX 2
+-#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0x1801
+-#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
+-#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1802
+-#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
+-#define mmDP_AUX5_AUX_GTC_SYNC_STATUS 0x1803
+-#define mmDP_AUX5_AUX_GTC_SYNC_STATUS_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dig0_dispdec
+-// base address: 0x0
+-#define mmDIG0_DIG_FE_CNTL 0x187e
+-#define mmDIG0_DIG_FE_CNTL_BASE_IDX 2
+-#define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x187f
+-#define mmDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
+-#define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x1880
+-#define mmDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
+-#define mmDIG0_DIG_CLOCK_PATTERN 0x1881
+-#define mmDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2
+-#define mmDIG0_DIG_TEST_PATTERN 0x1882
+-#define mmDIG0_DIG_TEST_PATTERN_BASE_IDX 2
+-#define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x1883
+-#define mmDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
+-#define mmDIG0_DIG_FIFO_STATUS 0x1884
+-#define mmDIG0_DIG_FIFO_STATUS_BASE_IDX 2
+-#define mmDIG0_HDMI_CONTROL 0x1887
+-#define mmDIG0_HDMI_CONTROL_BASE_IDX 2
+-#define mmDIG0_HDMI_STATUS 0x1888
+-#define mmDIG0_HDMI_STATUS_BASE_IDX 2
+-#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x1889
+-#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
+-#define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x188a
+-#define mmDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
+-#define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x188b
+-#define mmDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
+-#define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x188c
+-#define mmDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
+-#define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x188d
+-#define mmDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
+-#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x188e
+-#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
+-#define mmDIG0_AFMT_INTERRUPT_STATUS 0x188f
+-#define mmDIG0_AFMT_INTERRUPT_STATUS_BASE_IDX 2
+-#define mmDIG0_HDMI_GC 0x1891
+-#define mmDIG0_HDMI_GC_BASE_IDX 2
+-#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x1892
+-#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
+-#define mmDIG0_AFMT_ISRC1_0 0x1893
+-#define mmDIG0_AFMT_ISRC1_0_BASE_IDX 2
+-#define mmDIG0_AFMT_ISRC1_1 0x1894
+-#define mmDIG0_AFMT_ISRC1_1_BASE_IDX 2
+-#define mmDIG0_AFMT_ISRC1_2 0x1895
+-#define mmDIG0_AFMT_ISRC1_2_BASE_IDX 2
+-#define mmDIG0_AFMT_ISRC1_3 0x1896
+-#define mmDIG0_AFMT_ISRC1_3_BASE_IDX 2
+-#define mmDIG0_AFMT_ISRC1_4 0x1897
+-#define mmDIG0_AFMT_ISRC1_4_BASE_IDX 2
+-#define mmDIG0_AFMT_ISRC2_0 0x1898
+-#define mmDIG0_AFMT_ISRC2_0_BASE_IDX 2
+-#define mmDIG0_AFMT_ISRC2_1 0x1899
+-#define mmDIG0_AFMT_ISRC2_1_BASE_IDX 2
+-#define mmDIG0_AFMT_ISRC2_2 0x189a
+-#define mmDIG0_AFMT_ISRC2_2_BASE_IDX 2
+-#define mmDIG0_AFMT_ISRC2_3 0x189b
+-#define mmDIG0_AFMT_ISRC2_3_BASE_IDX 2
+-#define mmDIG0_AFMT_AVI_INFO0 0x189c
+-#define mmDIG0_AFMT_AVI_INFO0_BASE_IDX 2
+-#define mmDIG0_AFMT_AVI_INFO1 0x189d
+-#define mmDIG0_AFMT_AVI_INFO1_BASE_IDX 2
+-#define mmDIG0_AFMT_AVI_INFO2 0x189e
+-#define mmDIG0_AFMT_AVI_INFO2_BASE_IDX 2
+-#define mmDIG0_AFMT_AVI_INFO3 0x189f
+-#define mmDIG0_AFMT_AVI_INFO3_BASE_IDX 2
+-#define mmDIG0_AFMT_MPEG_INFO0 0x18a0
+-#define mmDIG0_AFMT_MPEG_INFO0_BASE_IDX 2
+-#define mmDIG0_AFMT_MPEG_INFO1 0x18a1
+-#define mmDIG0_AFMT_MPEG_INFO1_BASE_IDX 2
+-#define mmDIG0_AFMT_GENERIC_HDR 0x18a2
+-#define mmDIG0_AFMT_GENERIC_HDR_BASE_IDX 2
+-#define mmDIG0_AFMT_GENERIC_0 0x18a3
+-#define mmDIG0_AFMT_GENERIC_0_BASE_IDX 2
+-#define mmDIG0_AFMT_GENERIC_1 0x18a4
+-#define mmDIG0_AFMT_GENERIC_1_BASE_IDX 2
+-#define mmDIG0_AFMT_GENERIC_2 0x18a5
+-#define mmDIG0_AFMT_GENERIC_2_BASE_IDX 2
+-#define mmDIG0_AFMT_GENERIC_3 0x18a6
+-#define mmDIG0_AFMT_GENERIC_3_BASE_IDX 2
+-#define mmDIG0_AFMT_GENERIC_4 0x18a7
+-#define mmDIG0_AFMT_GENERIC_4_BASE_IDX 2
+-#define mmDIG0_AFMT_GENERIC_5 0x18a8
+-#define mmDIG0_AFMT_GENERIC_5_BASE_IDX 2
+-#define mmDIG0_AFMT_GENERIC_6 0x18a9
+-#define mmDIG0_AFMT_GENERIC_6_BASE_IDX 2
+-#define mmDIG0_AFMT_GENERIC_7 0x18aa
+-#define mmDIG0_AFMT_GENERIC_7_BASE_IDX 2
+-#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x18ab
+-#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
+-#define mmDIG0_HDMI_ACR_32_0 0x18ac
+-#define mmDIG0_HDMI_ACR_32_0_BASE_IDX 2
+-#define mmDIG0_HDMI_ACR_32_1 0x18ad
+-#define mmDIG0_HDMI_ACR_32_1_BASE_IDX 2
+-#define mmDIG0_HDMI_ACR_44_0 0x18ae
+-#define mmDIG0_HDMI_ACR_44_0_BASE_IDX 2
+-#define mmDIG0_HDMI_ACR_44_1 0x18af
+-#define mmDIG0_HDMI_ACR_44_1_BASE_IDX 2
+-#define mmDIG0_HDMI_ACR_48_0 0x18b0
+-#define mmDIG0_HDMI_ACR_48_0_BASE_IDX 2
+-#define mmDIG0_HDMI_ACR_48_1 0x18b1
+-#define mmDIG0_HDMI_ACR_48_1_BASE_IDX 2
+-#define mmDIG0_HDMI_ACR_STATUS_0 0x18b2
+-#define mmDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2
+-#define mmDIG0_HDMI_ACR_STATUS_1 0x18b3
+-#define mmDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2
+-#define mmDIG0_AFMT_AUDIO_INFO0 0x18b4
+-#define mmDIG0_AFMT_AUDIO_INFO0_BASE_IDX 2
+-#define mmDIG0_AFMT_AUDIO_INFO1 0x18b5
+-#define mmDIG0_AFMT_AUDIO_INFO1_BASE_IDX 2
+-#define mmDIG0_AFMT_60958_0 0x18b6
+-#define mmDIG0_AFMT_60958_0_BASE_IDX 2
+-#define mmDIG0_AFMT_60958_1 0x18b7
+-#define mmDIG0_AFMT_60958_1_BASE_IDX 2
+-#define mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x18b8
+-#define mmDIG0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
+-#define mmDIG0_AFMT_RAMP_CONTROL0 0x18b9
+-#define mmDIG0_AFMT_RAMP_CONTROL0_BASE_IDX 2
+-#define mmDIG0_AFMT_RAMP_CONTROL1 0x18ba
+-#define mmDIG0_AFMT_RAMP_CONTROL1_BASE_IDX 2
+-#define mmDIG0_AFMT_RAMP_CONTROL2 0x18bb
+-#define mmDIG0_AFMT_RAMP_CONTROL2_BASE_IDX 2
+-#define mmDIG0_AFMT_RAMP_CONTROL3 0x18bc
+-#define mmDIG0_AFMT_RAMP_CONTROL3_BASE_IDX 2
+-#define mmDIG0_AFMT_60958_2 0x18bd
+-#define mmDIG0_AFMT_60958_2_BASE_IDX 2
+-#define mmDIG0_AFMT_AUDIO_CRC_RESULT 0x18be
+-#define mmDIG0_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
+-#define mmDIG0_AFMT_STATUS 0x18bf
+-#define mmDIG0_AFMT_STATUS_BASE_IDX 2
+-#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x18c0
+-#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
+-#define mmDIG0_AFMT_VBI_PACKET_CONTROL 0x18c1
+-#define mmDIG0_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
+-#define mmDIG0_AFMT_INFOFRAME_CONTROL0 0x18c2
+-#define mmDIG0_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
+-#define mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x18c3
+-#define mmDIG0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
+-#define mmDIG0_DIG_BE_CNTL 0x18c5
+-#define mmDIG0_DIG_BE_CNTL_BASE_IDX 2
+-#define mmDIG0_DIG_BE_EN_CNTL 0x18c6
+-#define mmDIG0_DIG_BE_EN_CNTL_BASE_IDX 2
+-#define mmDIG0_TMDS_CNTL 0x18e9
+-#define mmDIG0_TMDS_CNTL_BASE_IDX 2
+-#define mmDIG0_TMDS_CONTROL_CHAR 0x18ea
+-#define mmDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2
+-#define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x18eb
+-#define mmDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
+-#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x18ec
+-#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
+-#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x18ed
+-#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
+-#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x18ee
+-#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
+-#define mmDIG0_TMDS_CTL_BITS 0x18f0
+-#define mmDIG0_TMDS_CTL_BITS_BASE_IDX 2
+-#define mmDIG0_TMDS_DCBALANCER_CONTROL 0x18f1
+-#define mmDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
+-#define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x18f3
+-#define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
+-#define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x18f4
+-#define mmDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
+-#define mmDIG0_DIG_VERSION 0x18f6
+-#define mmDIG0_DIG_VERSION_BASE_IDX 2
+-#define mmDIG0_DIG_LANE_ENABLE 0x18f7
+-#define mmDIG0_DIG_LANE_ENABLE_BASE_IDX 2
+-#define mmDIG0_AFMT_CNTL 0x18fc
+-#define mmDIG0_AFMT_CNTL_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dp0_dispdec
+-// base address: 0x0
+-#define mmDP0_DP_LINK_CNTL 0x191e
+-#define mmDP0_DP_LINK_CNTL_BASE_IDX 2
+-#define mmDP0_DP_PIXEL_FORMAT 0x191f
+-#define mmDP0_DP_PIXEL_FORMAT_BASE_IDX 2
+-#define mmDP0_DP_MSA_COLORIMETRY 0x1920
+-#define mmDP0_DP_MSA_COLORIMETRY_BASE_IDX 2
+-#define mmDP0_DP_CONFIG 0x1921
+-#define mmDP0_DP_CONFIG_BASE_IDX 2
+-#define mmDP0_DP_VID_STREAM_CNTL 0x1922
+-#define mmDP0_DP_VID_STREAM_CNTL_BASE_IDX 2
+-#define mmDP0_DP_STEER_FIFO 0x1923
+-#define mmDP0_DP_STEER_FIFO_BASE_IDX 2
+-#define mmDP0_DP_MSA_MISC 0x1924
+-#define mmDP0_DP_MSA_MISC_BASE_IDX 2
+-#define mmDP0_DP_VID_TIMING 0x1926
+-#define mmDP0_DP_VID_TIMING_BASE_IDX 2
+-#define mmDP0_DP_VID_N 0x1927
+-#define mmDP0_DP_VID_N_BASE_IDX 2
+-#define mmDP0_DP_VID_M 0x1928
+-#define mmDP0_DP_VID_M_BASE_IDX 2
+-#define mmDP0_DP_LINK_FRAMING_CNTL 0x1929
+-#define mmDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2
+-#define mmDP0_DP_HBR2_EYE_PATTERN 0x192a
+-#define mmDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2
+-#define mmDP0_DP_VID_MSA_VBID 0x192b
+-#define mmDP0_DP_VID_MSA_VBID_BASE_IDX 2
+-#define mmDP0_DP_VID_INTERRUPT_CNTL 0x192c
+-#define mmDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
+-#define mmDP0_DP_DPHY_CNTL 0x192d
+-#define mmDP0_DP_DPHY_CNTL_BASE_IDX 2
+-#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x192e
+-#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
+-#define mmDP0_DP_DPHY_SYM0 0x192f
+-#define mmDP0_DP_DPHY_SYM0_BASE_IDX 2
+-#define mmDP0_DP_DPHY_SYM1 0x1930
+-#define mmDP0_DP_DPHY_SYM1_BASE_IDX 2
+-#define mmDP0_DP_DPHY_SYM2 0x1931
+-#define mmDP0_DP_DPHY_SYM2_BASE_IDX 2
+-#define mmDP0_DP_DPHY_8B10B_CNTL 0x1932
+-#define mmDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2
+-#define mmDP0_DP_DPHY_PRBS_CNTL 0x1933
+-#define mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2
+-#define mmDP0_DP_DPHY_SCRAM_CNTL 0x1934
+-#define mmDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
+-#define mmDP0_DP_DPHY_CRC_EN 0x1935
+-#define mmDP0_DP_DPHY_CRC_EN_BASE_IDX 2
+-#define mmDP0_DP_DPHY_CRC_CNTL 0x1936
+-#define mmDP0_DP_DPHY_CRC_CNTL_BASE_IDX 2
+-#define mmDP0_DP_DPHY_CRC_RESULT 0x1937
+-#define mmDP0_DP_DPHY_CRC_RESULT_BASE_IDX 2
+-#define mmDP0_DP_DPHY_CRC_MST_CNTL 0x1938
+-#define mmDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
+-#define mmDP0_DP_DPHY_CRC_MST_STATUS 0x1939
+-#define mmDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
+-#define mmDP0_DP_DPHY_FAST_TRAINING 0x193a
+-#define mmDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2
+-#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x193b
+-#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
+-#define mmDP0_DP_MSA_V_TIMING_OVERRIDE1 0x193c
+-#define mmDP0_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2
+-#define mmDP0_DP_MSA_V_TIMING_OVERRIDE2 0x193d
+-#define mmDP0_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2
+-#define mmDP0_DP_SEC_CNTL 0x1941
+-#define mmDP0_DP_SEC_CNTL_BASE_IDX 2
+-#define mmDP0_DP_SEC_CNTL1 0x1942
+-#define mmDP0_DP_SEC_CNTL1_BASE_IDX 2
+-#define mmDP0_DP_SEC_FRAMING1 0x1943
+-#define mmDP0_DP_SEC_FRAMING1_BASE_IDX 2
+-#define mmDP0_DP_SEC_FRAMING2 0x1944
+-#define mmDP0_DP_SEC_FRAMING2_BASE_IDX 2
+-#define mmDP0_DP_SEC_FRAMING3 0x1945
+-#define mmDP0_DP_SEC_FRAMING3_BASE_IDX 2
+-#define mmDP0_DP_SEC_FRAMING4 0x1946
+-#define mmDP0_DP_SEC_FRAMING4_BASE_IDX 2
+-#define mmDP0_DP_SEC_AUD_N 0x1947
+-#define mmDP0_DP_SEC_AUD_N_BASE_IDX 2
+-#define mmDP0_DP_SEC_AUD_N_READBACK 0x1948
+-#define mmDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2
+-#define mmDP0_DP_SEC_AUD_M 0x1949
+-#define mmDP0_DP_SEC_AUD_M_BASE_IDX 2
+-#define mmDP0_DP_SEC_AUD_M_READBACK 0x194a
+-#define mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2
+-#define mmDP0_DP_SEC_TIMESTAMP 0x194b
+-#define mmDP0_DP_SEC_TIMESTAMP_BASE_IDX 2
+-#define mmDP0_DP_SEC_PACKET_CNTL 0x194c
+-#define mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2
+-#define mmDP0_DP_MSE_RATE_CNTL 0x194d
+-#define mmDP0_DP_MSE_RATE_CNTL_BASE_IDX 2
+-#define mmDP0_DP_MSE_RATE_UPDATE 0x194f
+-#define mmDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2
+-#define mmDP0_DP_MSE_SAT0 0x1950
+-#define mmDP0_DP_MSE_SAT0_BASE_IDX 2
+-#define mmDP0_DP_MSE_SAT1 0x1951
+-#define mmDP0_DP_MSE_SAT1_BASE_IDX 2
+-#define mmDP0_DP_MSE_SAT2 0x1952
+-#define mmDP0_DP_MSE_SAT2_BASE_IDX 2
+-#define mmDP0_DP_MSE_SAT_UPDATE 0x1953
+-#define mmDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2
+-#define mmDP0_DP_MSE_LINK_TIMING 0x1954
+-#define mmDP0_DP_MSE_LINK_TIMING_BASE_IDX 2
+-#define mmDP0_DP_MSE_MISC_CNTL 0x1955
+-#define mmDP0_DP_MSE_MISC_CNTL_BASE_IDX 2
+-#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x195a
+-#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
+-#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x195b
+-#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
+-#define mmDP0_DP_MSE_SAT0_STATUS 0x195d
+-#define mmDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2
+-#define mmDP0_DP_MSE_SAT1_STATUS 0x195e
+-#define mmDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2
+-#define mmDP0_DP_MSE_SAT2_STATUS 0x195f
+-#define mmDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dig1_dispdec
+-// base address: 0x400
+-#define mmDIG1_DIG_FE_CNTL 0x197e
+-#define mmDIG1_DIG_FE_CNTL_BASE_IDX 2
+-#define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x197f
+-#define mmDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
+-#define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x1980
+-#define mmDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
+-#define mmDIG1_DIG_CLOCK_PATTERN 0x1981
+-#define mmDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2
+-#define mmDIG1_DIG_TEST_PATTERN 0x1982
+-#define mmDIG1_DIG_TEST_PATTERN_BASE_IDX 2
+-#define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x1983
+-#define mmDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
+-#define mmDIG1_DIG_FIFO_STATUS 0x1984
+-#define mmDIG1_DIG_FIFO_STATUS_BASE_IDX 2
+-#define mmDIG1_HDMI_CONTROL 0x1987
+-#define mmDIG1_HDMI_CONTROL_BASE_IDX 2
+-#define mmDIG1_HDMI_STATUS 0x1988
+-#define mmDIG1_HDMI_STATUS_BASE_IDX 2
+-#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x1989
+-#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
+-#define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x198a
+-#define mmDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
+-#define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x198b
+-#define mmDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
+-#define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x198c
+-#define mmDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
+-#define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x198d
+-#define mmDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
+-#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x198e
+-#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
+-#define mmDIG1_AFMT_INTERRUPT_STATUS 0x198f
+-#define mmDIG1_AFMT_INTERRUPT_STATUS_BASE_IDX 2
+-#define mmDIG1_HDMI_GC 0x1991
+-#define mmDIG1_HDMI_GC_BASE_IDX 2
+-#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x1992
+-#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
+-#define mmDIG1_AFMT_ISRC1_0 0x1993
+-#define mmDIG1_AFMT_ISRC1_0_BASE_IDX 2
+-#define mmDIG1_AFMT_ISRC1_1 0x1994
+-#define mmDIG1_AFMT_ISRC1_1_BASE_IDX 2
+-#define mmDIG1_AFMT_ISRC1_2 0x1995
+-#define mmDIG1_AFMT_ISRC1_2_BASE_IDX 2
+-#define mmDIG1_AFMT_ISRC1_3 0x1996
+-#define mmDIG1_AFMT_ISRC1_3_BASE_IDX 2
+-#define mmDIG1_AFMT_ISRC1_4 0x1997
+-#define mmDIG1_AFMT_ISRC1_4_BASE_IDX 2
+-#define mmDIG1_AFMT_ISRC2_0 0x1998
+-#define mmDIG1_AFMT_ISRC2_0_BASE_IDX 2
+-#define mmDIG1_AFMT_ISRC2_1 0x1999
+-#define mmDIG1_AFMT_ISRC2_1_BASE_IDX 2
+-#define mmDIG1_AFMT_ISRC2_2 0x199a
+-#define mmDIG1_AFMT_ISRC2_2_BASE_IDX 2
+-#define mmDIG1_AFMT_ISRC2_3 0x199b
+-#define mmDIG1_AFMT_ISRC2_3_BASE_IDX 2
+-#define mmDIG1_AFMT_AVI_INFO0 0x199c
+-#define mmDIG1_AFMT_AVI_INFO0_BASE_IDX 2
+-#define mmDIG1_AFMT_AVI_INFO1 0x199d
+-#define mmDIG1_AFMT_AVI_INFO1_BASE_IDX 2
+-#define mmDIG1_AFMT_AVI_INFO2 0x199e
+-#define mmDIG1_AFMT_AVI_INFO2_BASE_IDX 2
+-#define mmDIG1_AFMT_AVI_INFO3 0x199f
+-#define mmDIG1_AFMT_AVI_INFO3_BASE_IDX 2
+-#define mmDIG1_AFMT_MPEG_INFO0 0x19a0
+-#define mmDIG1_AFMT_MPEG_INFO0_BASE_IDX 2
+-#define mmDIG1_AFMT_MPEG_INFO1 0x19a1
+-#define mmDIG1_AFMT_MPEG_INFO1_BASE_IDX 2
+-#define mmDIG1_AFMT_GENERIC_HDR 0x19a2
+-#define mmDIG1_AFMT_GENERIC_HDR_BASE_IDX 2
+-#define mmDIG1_AFMT_GENERIC_0 0x19a3
+-#define mmDIG1_AFMT_GENERIC_0_BASE_IDX 2
+-#define mmDIG1_AFMT_GENERIC_1 0x19a4
+-#define mmDIG1_AFMT_GENERIC_1_BASE_IDX 2
+-#define mmDIG1_AFMT_GENERIC_2 0x19a5
+-#define mmDIG1_AFMT_GENERIC_2_BASE_IDX 2
+-#define mmDIG1_AFMT_GENERIC_3 0x19a6
+-#define mmDIG1_AFMT_GENERIC_3_BASE_IDX 2
+-#define mmDIG1_AFMT_GENERIC_4 0x19a7
+-#define mmDIG1_AFMT_GENERIC_4_BASE_IDX 2
+-#define mmDIG1_AFMT_GENERIC_5 0x19a8
+-#define mmDIG1_AFMT_GENERIC_5_BASE_IDX 2
+-#define mmDIG1_AFMT_GENERIC_6 0x19a9
+-#define mmDIG1_AFMT_GENERIC_6_BASE_IDX 2
+-#define mmDIG1_AFMT_GENERIC_7 0x19aa
+-#define mmDIG1_AFMT_GENERIC_7_BASE_IDX 2
+-#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x19ab
+-#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
+-#define mmDIG1_HDMI_ACR_32_0 0x19ac
+-#define mmDIG1_HDMI_ACR_32_0_BASE_IDX 2
+-#define mmDIG1_HDMI_ACR_32_1 0x19ad
+-#define mmDIG1_HDMI_ACR_32_1_BASE_IDX 2
+-#define mmDIG1_HDMI_ACR_44_0 0x19ae
+-#define mmDIG1_HDMI_ACR_44_0_BASE_IDX 2
+-#define mmDIG1_HDMI_ACR_44_1 0x19af
+-#define mmDIG1_HDMI_ACR_44_1_BASE_IDX 2
+-#define mmDIG1_HDMI_ACR_48_0 0x19b0
+-#define mmDIG1_HDMI_ACR_48_0_BASE_IDX 2
+-#define mmDIG1_HDMI_ACR_48_1 0x19b1
+-#define mmDIG1_HDMI_ACR_48_1_BASE_IDX 2
+-#define mmDIG1_HDMI_ACR_STATUS_0 0x19b2
+-#define mmDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2
+-#define mmDIG1_HDMI_ACR_STATUS_1 0x19b3
+-#define mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2
+-#define mmDIG1_AFMT_AUDIO_INFO0 0x19b4
+-#define mmDIG1_AFMT_AUDIO_INFO0_BASE_IDX 2
+-#define mmDIG1_AFMT_AUDIO_INFO1 0x19b5
+-#define mmDIG1_AFMT_AUDIO_INFO1_BASE_IDX 2
+-#define mmDIG1_AFMT_60958_0 0x19b6
+-#define mmDIG1_AFMT_60958_0_BASE_IDX 2
+-#define mmDIG1_AFMT_60958_1 0x19b7
+-#define mmDIG1_AFMT_60958_1_BASE_IDX 2
+-#define mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x19b8
+-#define mmDIG1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
+-#define mmDIG1_AFMT_RAMP_CONTROL0 0x19b9
+-#define mmDIG1_AFMT_RAMP_CONTROL0_BASE_IDX 2
+-#define mmDIG1_AFMT_RAMP_CONTROL1 0x19ba
+-#define mmDIG1_AFMT_RAMP_CONTROL1_BASE_IDX 2
+-#define mmDIG1_AFMT_RAMP_CONTROL2 0x19bb
+-#define mmDIG1_AFMT_RAMP_CONTROL2_BASE_IDX 2
+-#define mmDIG1_AFMT_RAMP_CONTROL3 0x19bc
+-#define mmDIG1_AFMT_RAMP_CONTROL3_BASE_IDX 2
+-#define mmDIG1_AFMT_60958_2 0x19bd
+-#define mmDIG1_AFMT_60958_2_BASE_IDX 2
+-#define mmDIG1_AFMT_AUDIO_CRC_RESULT 0x19be
+-#define mmDIG1_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
+-#define mmDIG1_AFMT_STATUS 0x19bf
+-#define mmDIG1_AFMT_STATUS_BASE_IDX 2
+-#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x19c0
+-#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
+-#define mmDIG1_AFMT_VBI_PACKET_CONTROL 0x19c1
+-#define mmDIG1_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
+-#define mmDIG1_AFMT_INFOFRAME_CONTROL0 0x19c2
+-#define mmDIG1_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
+-#define mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x19c3
+-#define mmDIG1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
+-#define mmDIG1_DIG_BE_CNTL 0x19c5
+-#define mmDIG1_DIG_BE_CNTL_BASE_IDX 2
+-#define mmDIG1_DIG_BE_EN_CNTL 0x19c6
+-#define mmDIG1_DIG_BE_EN_CNTL_BASE_IDX 2
+-#define mmDIG1_TMDS_CNTL 0x19e9
+-#define mmDIG1_TMDS_CNTL_BASE_IDX 2
+-#define mmDIG1_TMDS_CONTROL_CHAR 0x19ea
+-#define mmDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2
+-#define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x19eb
+-#define mmDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
+-#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x19ec
+-#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
+-#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x19ed
+-#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
+-#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x19ee
+-#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
+-#define mmDIG1_TMDS_CTL_BITS 0x19f0
+-#define mmDIG1_TMDS_CTL_BITS_BASE_IDX 2
+-#define mmDIG1_TMDS_DCBALANCER_CONTROL 0x19f1
+-#define mmDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
+-#define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x19f3
+-#define mmDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
+-#define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x19f4
+-#define mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
+-#define mmDIG1_DIG_VERSION 0x19f6
+-#define mmDIG1_DIG_VERSION_BASE_IDX 2
+-#define mmDIG1_DIG_LANE_ENABLE 0x19f7
+-#define mmDIG1_DIG_LANE_ENABLE_BASE_IDX 2
+-#define mmDIG1_AFMT_CNTL 0x19fc
+-#define mmDIG1_AFMT_CNTL_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dp1_dispdec
+-// base address: 0x400
+-#define mmDP1_DP_LINK_CNTL 0x1a1e
+-#define mmDP1_DP_LINK_CNTL_BASE_IDX 2
+-#define mmDP1_DP_PIXEL_FORMAT 0x1a1f
+-#define mmDP1_DP_PIXEL_FORMAT_BASE_IDX 2
+-#define mmDP1_DP_MSA_COLORIMETRY 0x1a20
+-#define mmDP1_DP_MSA_COLORIMETRY_BASE_IDX 2
+-#define mmDP1_DP_CONFIG 0x1a21
+-#define mmDP1_DP_CONFIG_BASE_IDX 2
+-#define mmDP1_DP_VID_STREAM_CNTL 0x1a22
+-#define mmDP1_DP_VID_STREAM_CNTL_BASE_IDX 2
+-#define mmDP1_DP_STEER_FIFO 0x1a23
+-#define mmDP1_DP_STEER_FIFO_BASE_IDX 2
+-#define mmDP1_DP_MSA_MISC 0x1a24
+-#define mmDP1_DP_MSA_MISC_BASE_IDX 2
+-#define mmDP1_DP_VID_TIMING 0x1a26
+-#define mmDP1_DP_VID_TIMING_BASE_IDX 2
+-#define mmDP1_DP_VID_N 0x1a27
+-#define mmDP1_DP_VID_N_BASE_IDX 2
+-#define mmDP1_DP_VID_M 0x1a28
+-#define mmDP1_DP_VID_M_BASE_IDX 2
+-#define mmDP1_DP_LINK_FRAMING_CNTL 0x1a29
+-#define mmDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2
+-#define mmDP1_DP_HBR2_EYE_PATTERN 0x1a2a
+-#define mmDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2
+-#define mmDP1_DP_VID_MSA_VBID 0x1a2b
+-#define mmDP1_DP_VID_MSA_VBID_BASE_IDX 2
+-#define mmDP1_DP_VID_INTERRUPT_CNTL 0x1a2c
+-#define mmDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
+-#define mmDP1_DP_DPHY_CNTL 0x1a2d
+-#define mmDP1_DP_DPHY_CNTL_BASE_IDX 2
+-#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x1a2e
+-#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
+-#define mmDP1_DP_DPHY_SYM0 0x1a2f
+-#define mmDP1_DP_DPHY_SYM0_BASE_IDX 2
+-#define mmDP1_DP_DPHY_SYM1 0x1a30
+-#define mmDP1_DP_DPHY_SYM1_BASE_IDX 2
+-#define mmDP1_DP_DPHY_SYM2 0x1a31
+-#define mmDP1_DP_DPHY_SYM2_BASE_IDX 2
+-#define mmDP1_DP_DPHY_8B10B_CNTL 0x1a32
+-#define mmDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2
+-#define mmDP1_DP_DPHY_PRBS_CNTL 0x1a33
+-#define mmDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2
+-#define mmDP1_DP_DPHY_SCRAM_CNTL 0x1a34
+-#define mmDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
+-#define mmDP1_DP_DPHY_CRC_EN 0x1a35
+-#define mmDP1_DP_DPHY_CRC_EN_BASE_IDX 2
+-#define mmDP1_DP_DPHY_CRC_CNTL 0x1a36
+-#define mmDP1_DP_DPHY_CRC_CNTL_BASE_IDX 2
+-#define mmDP1_DP_DPHY_CRC_RESULT 0x1a37
+-#define mmDP1_DP_DPHY_CRC_RESULT_BASE_IDX 2
+-#define mmDP1_DP_DPHY_CRC_MST_CNTL 0x1a38
+-#define mmDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
+-#define mmDP1_DP_DPHY_CRC_MST_STATUS 0x1a39
+-#define mmDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
+-#define mmDP1_DP_DPHY_FAST_TRAINING 0x1a3a
+-#define mmDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2
+-#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x1a3b
+-#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
+-#define mmDP1_DP_MSA_V_TIMING_OVERRIDE1 0x1a3c
+-#define mmDP1_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2
+-#define mmDP1_DP_MSA_V_TIMING_OVERRIDE2 0x1a3d
+-#define mmDP1_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2
+-#define mmDP1_DP_SEC_CNTL 0x1a41
+-#define mmDP1_DP_SEC_CNTL_BASE_IDX 2
+-#define mmDP1_DP_SEC_CNTL1 0x1a42
+-#define mmDP1_DP_SEC_CNTL1_BASE_IDX 2
+-#define mmDP1_DP_SEC_FRAMING1 0x1a43
+-#define mmDP1_DP_SEC_FRAMING1_BASE_IDX 2
+-#define mmDP1_DP_SEC_FRAMING2 0x1a44
+-#define mmDP1_DP_SEC_FRAMING2_BASE_IDX 2
+-#define mmDP1_DP_SEC_FRAMING3 0x1a45
+-#define mmDP1_DP_SEC_FRAMING3_BASE_IDX 2
+-#define mmDP1_DP_SEC_FRAMING4 0x1a46
+-#define mmDP1_DP_SEC_FRAMING4_BASE_IDX 2
+-#define mmDP1_DP_SEC_AUD_N 0x1a47
+-#define mmDP1_DP_SEC_AUD_N_BASE_IDX 2
+-#define mmDP1_DP_SEC_AUD_N_READBACK 0x1a48
+-#define mmDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2
+-#define mmDP1_DP_SEC_AUD_M 0x1a49
+-#define mmDP1_DP_SEC_AUD_M_BASE_IDX 2
+-#define mmDP1_DP_SEC_AUD_M_READBACK 0x1a4a
+-#define mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2
+-#define mmDP1_DP_SEC_TIMESTAMP 0x1a4b
+-#define mmDP1_DP_SEC_TIMESTAMP_BASE_IDX 2
+-#define mmDP1_DP_SEC_PACKET_CNTL 0x1a4c
+-#define mmDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2
+-#define mmDP1_DP_MSE_RATE_CNTL 0x1a4d
+-#define mmDP1_DP_MSE_RATE_CNTL_BASE_IDX 2
+-#define mmDP1_DP_MSE_RATE_UPDATE 0x1a4f
+-#define mmDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2
+-#define mmDP1_DP_MSE_SAT0 0x1a50
+-#define mmDP1_DP_MSE_SAT0_BASE_IDX 2
+-#define mmDP1_DP_MSE_SAT1 0x1a51
+-#define mmDP1_DP_MSE_SAT1_BASE_IDX 2
+-#define mmDP1_DP_MSE_SAT2 0x1a52
+-#define mmDP1_DP_MSE_SAT2_BASE_IDX 2
+-#define mmDP1_DP_MSE_SAT_UPDATE 0x1a53
+-#define mmDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2
+-#define mmDP1_DP_MSE_LINK_TIMING 0x1a54
+-#define mmDP1_DP_MSE_LINK_TIMING_BASE_IDX 2
+-#define mmDP1_DP_MSE_MISC_CNTL 0x1a55
+-#define mmDP1_DP_MSE_MISC_CNTL_BASE_IDX 2
+-#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x1a5a
+-#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
+-#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x1a5b
+-#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
+-#define mmDP1_DP_MSE_SAT0_STATUS 0x1a5d
+-#define mmDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2
+-#define mmDP1_DP_MSE_SAT1_STATUS 0x1a5e
+-#define mmDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2
+-#define mmDP1_DP_MSE_SAT2_STATUS 0x1a5f
+-#define mmDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dig2_dispdec
+-// base address: 0x800
+-#define mmDIG2_DIG_FE_CNTL 0x1a7e
+-#define mmDIG2_DIG_FE_CNTL_BASE_IDX 2
+-#define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x1a7f
+-#define mmDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
+-#define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x1a80
+-#define mmDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
+-#define mmDIG2_DIG_CLOCK_PATTERN 0x1a81
+-#define mmDIG2_DIG_CLOCK_PATTERN_BASE_IDX 2
+-#define mmDIG2_DIG_TEST_PATTERN 0x1a82
+-#define mmDIG2_DIG_TEST_PATTERN_BASE_IDX 2
+-#define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x1a83
+-#define mmDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
+-#define mmDIG2_DIG_FIFO_STATUS 0x1a84
+-#define mmDIG2_DIG_FIFO_STATUS_BASE_IDX 2
+-#define mmDIG2_HDMI_CONTROL 0x1a87
+-#define mmDIG2_HDMI_CONTROL_BASE_IDX 2
+-#define mmDIG2_HDMI_STATUS 0x1a88
+-#define mmDIG2_HDMI_STATUS_BASE_IDX 2
+-#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x1a89
+-#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
+-#define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x1a8a
+-#define mmDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
+-#define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x1a8b
+-#define mmDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
+-#define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x1a8c
+-#define mmDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
+-#define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x1a8d
+-#define mmDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
+-#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x1a8e
+-#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
+-#define mmDIG2_AFMT_INTERRUPT_STATUS 0x1a8f
+-#define mmDIG2_AFMT_INTERRUPT_STATUS_BASE_IDX 2
+-#define mmDIG2_HDMI_GC 0x1a91
+-#define mmDIG2_HDMI_GC_BASE_IDX 2
+-#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x1a92
+-#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
+-#define mmDIG2_AFMT_ISRC1_0 0x1a93
+-#define mmDIG2_AFMT_ISRC1_0_BASE_IDX 2
+-#define mmDIG2_AFMT_ISRC1_1 0x1a94
+-#define mmDIG2_AFMT_ISRC1_1_BASE_IDX 2
+-#define mmDIG2_AFMT_ISRC1_2 0x1a95
+-#define mmDIG2_AFMT_ISRC1_2_BASE_IDX 2
+-#define mmDIG2_AFMT_ISRC1_3 0x1a96
+-#define mmDIG2_AFMT_ISRC1_3_BASE_IDX 2
+-#define mmDIG2_AFMT_ISRC1_4 0x1a97
+-#define mmDIG2_AFMT_ISRC1_4_BASE_IDX 2
+-#define mmDIG2_AFMT_ISRC2_0 0x1a98
+-#define mmDIG2_AFMT_ISRC2_0_BASE_IDX 2
+-#define mmDIG2_AFMT_ISRC2_1 0x1a99
+-#define mmDIG2_AFMT_ISRC2_1_BASE_IDX 2
+-#define mmDIG2_AFMT_ISRC2_2 0x1a9a
+-#define mmDIG2_AFMT_ISRC2_2_BASE_IDX 2
+-#define mmDIG2_AFMT_ISRC2_3 0x1a9b
+-#define mmDIG2_AFMT_ISRC2_3_BASE_IDX 2
+-#define mmDIG2_AFMT_AVI_INFO0 0x1a9c
+-#define mmDIG2_AFMT_AVI_INFO0_BASE_IDX 2
+-#define mmDIG2_AFMT_AVI_INFO1 0x1a9d
+-#define mmDIG2_AFMT_AVI_INFO1_BASE_IDX 2
+-#define mmDIG2_AFMT_AVI_INFO2 0x1a9e
+-#define mmDIG2_AFMT_AVI_INFO2_BASE_IDX 2
+-#define mmDIG2_AFMT_AVI_INFO3 0x1a9f
+-#define mmDIG2_AFMT_AVI_INFO3_BASE_IDX 2
+-#define mmDIG2_AFMT_MPEG_INFO0 0x1aa0
+-#define mmDIG2_AFMT_MPEG_INFO0_BASE_IDX 2
+-#define mmDIG2_AFMT_MPEG_INFO1 0x1aa1
+-#define mmDIG2_AFMT_MPEG_INFO1_BASE_IDX 2
+-#define mmDIG2_AFMT_GENERIC_HDR 0x1aa2
+-#define mmDIG2_AFMT_GENERIC_HDR_BASE_IDX 2
+-#define mmDIG2_AFMT_GENERIC_0 0x1aa3
+-#define mmDIG2_AFMT_GENERIC_0_BASE_IDX 2
+-#define mmDIG2_AFMT_GENERIC_1 0x1aa4
+-#define mmDIG2_AFMT_GENERIC_1_BASE_IDX 2
+-#define mmDIG2_AFMT_GENERIC_2 0x1aa5
+-#define mmDIG2_AFMT_GENERIC_2_BASE_IDX 2
+-#define mmDIG2_AFMT_GENERIC_3 0x1aa6
+-#define mmDIG2_AFMT_GENERIC_3_BASE_IDX 2
+-#define mmDIG2_AFMT_GENERIC_4 0x1aa7
+-#define mmDIG2_AFMT_GENERIC_4_BASE_IDX 2
+-#define mmDIG2_AFMT_GENERIC_5 0x1aa8
+-#define mmDIG2_AFMT_GENERIC_5_BASE_IDX 2
+-#define mmDIG2_AFMT_GENERIC_6 0x1aa9
+-#define mmDIG2_AFMT_GENERIC_6_BASE_IDX 2
+-#define mmDIG2_AFMT_GENERIC_7 0x1aaa
+-#define mmDIG2_AFMT_GENERIC_7_BASE_IDX 2
+-#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x1aab
+-#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
+-#define mmDIG2_HDMI_ACR_32_0 0x1aac
+-#define mmDIG2_HDMI_ACR_32_0_BASE_IDX 2
+-#define mmDIG2_HDMI_ACR_32_1 0x1aad
+-#define mmDIG2_HDMI_ACR_32_1_BASE_IDX 2
+-#define mmDIG2_HDMI_ACR_44_0 0x1aae
+-#define mmDIG2_HDMI_ACR_44_0_BASE_IDX 2
+-#define mmDIG2_HDMI_ACR_44_1 0x1aaf
+-#define mmDIG2_HDMI_ACR_44_1_BASE_IDX 2
+-#define mmDIG2_HDMI_ACR_48_0 0x1ab0
+-#define mmDIG2_HDMI_ACR_48_0_BASE_IDX 2
+-#define mmDIG2_HDMI_ACR_48_1 0x1ab1
+-#define mmDIG2_HDMI_ACR_48_1_BASE_IDX 2
+-#define mmDIG2_HDMI_ACR_STATUS_0 0x1ab2
+-#define mmDIG2_HDMI_ACR_STATUS_0_BASE_IDX 2
+-#define mmDIG2_HDMI_ACR_STATUS_1 0x1ab3
+-#define mmDIG2_HDMI_ACR_STATUS_1_BASE_IDX 2
+-#define mmDIG2_AFMT_AUDIO_INFO0 0x1ab4
+-#define mmDIG2_AFMT_AUDIO_INFO0_BASE_IDX 2
+-#define mmDIG2_AFMT_AUDIO_INFO1 0x1ab5
+-#define mmDIG2_AFMT_AUDIO_INFO1_BASE_IDX 2
+-#define mmDIG2_AFMT_60958_0 0x1ab6
+-#define mmDIG2_AFMT_60958_0_BASE_IDX 2
+-#define mmDIG2_AFMT_60958_1 0x1ab7
+-#define mmDIG2_AFMT_60958_1_BASE_IDX 2
+-#define mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x1ab8
+-#define mmDIG2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
+-#define mmDIG2_AFMT_RAMP_CONTROL0 0x1ab9
+-#define mmDIG2_AFMT_RAMP_CONTROL0_BASE_IDX 2
+-#define mmDIG2_AFMT_RAMP_CONTROL1 0x1aba
+-#define mmDIG2_AFMT_RAMP_CONTROL1_BASE_IDX 2
+-#define mmDIG2_AFMT_RAMP_CONTROL2 0x1abb
+-#define mmDIG2_AFMT_RAMP_CONTROL2_BASE_IDX 2
+-#define mmDIG2_AFMT_RAMP_CONTROL3 0x1abc
+-#define mmDIG2_AFMT_RAMP_CONTROL3_BASE_IDX 2
+-#define mmDIG2_AFMT_60958_2 0x1abd
+-#define mmDIG2_AFMT_60958_2_BASE_IDX 2
+-#define mmDIG2_AFMT_AUDIO_CRC_RESULT 0x1abe
+-#define mmDIG2_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
+-#define mmDIG2_AFMT_STATUS 0x1abf
+-#define mmDIG2_AFMT_STATUS_BASE_IDX 2
+-#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x1ac0
+-#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
+-#define mmDIG2_AFMT_VBI_PACKET_CONTROL 0x1ac1
+-#define mmDIG2_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
+-#define mmDIG2_AFMT_INFOFRAME_CONTROL0 0x1ac2
+-#define mmDIG2_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
+-#define mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x1ac3
+-#define mmDIG2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
+-#define mmDIG2_DIG_BE_CNTL 0x1ac5
+-#define mmDIG2_DIG_BE_CNTL_BASE_IDX 2
+-#define mmDIG2_DIG_BE_EN_CNTL 0x1ac6
+-#define mmDIG2_DIG_BE_EN_CNTL_BASE_IDX 2
+-#define mmDIG2_TMDS_CNTL 0x1ae9
+-#define mmDIG2_TMDS_CNTL_BASE_IDX 2
+-#define mmDIG2_TMDS_CONTROL_CHAR 0x1aea
+-#define mmDIG2_TMDS_CONTROL_CHAR_BASE_IDX 2
+-#define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x1aeb
+-#define mmDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
+-#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x1aec
+-#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
+-#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x1aed
+-#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
+-#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x1aee
+-#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
+-#define mmDIG2_TMDS_CTL_BITS 0x1af0
+-#define mmDIG2_TMDS_CTL_BITS_BASE_IDX 2
+-#define mmDIG2_TMDS_DCBALANCER_CONTROL 0x1af1
+-#define mmDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
+-#define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x1af3
+-#define mmDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
+-#define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x1af4
+-#define mmDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
+-#define mmDIG2_DIG_VERSION 0x1af6
+-#define mmDIG2_DIG_VERSION_BASE_IDX 2
+-#define mmDIG2_DIG_LANE_ENABLE 0x1af7
+-#define mmDIG2_DIG_LANE_ENABLE_BASE_IDX 2
+-#define mmDIG2_AFMT_CNTL 0x1afc
+-#define mmDIG2_AFMT_CNTL_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dp2_dispdec
+-// base address: 0x800
+-#define mmDP2_DP_LINK_CNTL 0x1b1e
+-#define mmDP2_DP_LINK_CNTL_BASE_IDX 2
+-#define mmDP2_DP_PIXEL_FORMAT 0x1b1f
+-#define mmDP2_DP_PIXEL_FORMAT_BASE_IDX 2
+-#define mmDP2_DP_MSA_COLORIMETRY 0x1b20
+-#define mmDP2_DP_MSA_COLORIMETRY_BASE_IDX 2
+-#define mmDP2_DP_CONFIG 0x1b21
+-#define mmDP2_DP_CONFIG_BASE_IDX 2
+-#define mmDP2_DP_VID_STREAM_CNTL 0x1b22
+-#define mmDP2_DP_VID_STREAM_CNTL_BASE_IDX 2
+-#define mmDP2_DP_STEER_FIFO 0x1b23
+-#define mmDP2_DP_STEER_FIFO_BASE_IDX 2
+-#define mmDP2_DP_MSA_MISC 0x1b24
+-#define mmDP2_DP_MSA_MISC_BASE_IDX 2
+-#define mmDP2_DP_VID_TIMING 0x1b26
+-#define mmDP2_DP_VID_TIMING_BASE_IDX 2
+-#define mmDP2_DP_VID_N 0x1b27
+-#define mmDP2_DP_VID_N_BASE_IDX 2
+-#define mmDP2_DP_VID_M 0x1b28
+-#define mmDP2_DP_VID_M_BASE_IDX 2
+-#define mmDP2_DP_LINK_FRAMING_CNTL 0x1b29
+-#define mmDP2_DP_LINK_FRAMING_CNTL_BASE_IDX 2
+-#define mmDP2_DP_HBR2_EYE_PATTERN 0x1b2a
+-#define mmDP2_DP_HBR2_EYE_PATTERN_BASE_IDX 2
+-#define mmDP2_DP_VID_MSA_VBID 0x1b2b
+-#define mmDP2_DP_VID_MSA_VBID_BASE_IDX 2
+-#define mmDP2_DP_VID_INTERRUPT_CNTL 0x1b2c
+-#define mmDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
+-#define mmDP2_DP_DPHY_CNTL 0x1b2d
+-#define mmDP2_DP_DPHY_CNTL_BASE_IDX 2
+-#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x1b2e
+-#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
+-#define mmDP2_DP_DPHY_SYM0 0x1b2f
+-#define mmDP2_DP_DPHY_SYM0_BASE_IDX 2
+-#define mmDP2_DP_DPHY_SYM1 0x1b30
+-#define mmDP2_DP_DPHY_SYM1_BASE_IDX 2
+-#define mmDP2_DP_DPHY_SYM2 0x1b31
+-#define mmDP2_DP_DPHY_SYM2_BASE_IDX 2
+-#define mmDP2_DP_DPHY_8B10B_CNTL 0x1b32
+-#define mmDP2_DP_DPHY_8B10B_CNTL_BASE_IDX 2
+-#define mmDP2_DP_DPHY_PRBS_CNTL 0x1b33
+-#define mmDP2_DP_DPHY_PRBS_CNTL_BASE_IDX 2
+-#define mmDP2_DP_DPHY_SCRAM_CNTL 0x1b34
+-#define mmDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
+-#define mmDP2_DP_DPHY_CRC_EN 0x1b35
+-#define mmDP2_DP_DPHY_CRC_EN_BASE_IDX 2
+-#define mmDP2_DP_DPHY_CRC_CNTL 0x1b36
+-#define mmDP2_DP_DPHY_CRC_CNTL_BASE_IDX 2
+-#define mmDP2_DP_DPHY_CRC_RESULT 0x1b37
+-#define mmDP2_DP_DPHY_CRC_RESULT_BASE_IDX 2
+-#define mmDP2_DP_DPHY_CRC_MST_CNTL 0x1b38
+-#define mmDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
+-#define mmDP2_DP_DPHY_CRC_MST_STATUS 0x1b39
+-#define mmDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
+-#define mmDP2_DP_DPHY_FAST_TRAINING 0x1b3a
+-#define mmDP2_DP_DPHY_FAST_TRAINING_BASE_IDX 2
+-#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x1b3b
+-#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
+-#define mmDP2_DP_MSA_V_TIMING_OVERRIDE1 0x1b3c
+-#define mmDP2_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2
+-#define mmDP2_DP_MSA_V_TIMING_OVERRIDE2 0x1b3d
+-#define mmDP2_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2
+-#define mmDP2_DP_SEC_CNTL 0x1b41
+-#define mmDP2_DP_SEC_CNTL_BASE_IDX 2
+-#define mmDP2_DP_SEC_CNTL1 0x1b42
+-#define mmDP2_DP_SEC_CNTL1_BASE_IDX 2
+-#define mmDP2_DP_SEC_FRAMING1 0x1b43
+-#define mmDP2_DP_SEC_FRAMING1_BASE_IDX 2
+-#define mmDP2_DP_SEC_FRAMING2 0x1b44
+-#define mmDP2_DP_SEC_FRAMING2_BASE_IDX 2
+-#define mmDP2_DP_SEC_FRAMING3 0x1b45
+-#define mmDP2_DP_SEC_FRAMING3_BASE_IDX 2
+-#define mmDP2_DP_SEC_FRAMING4 0x1b46
+-#define mmDP2_DP_SEC_FRAMING4_BASE_IDX 2
+-#define mmDP2_DP_SEC_AUD_N 0x1b47
+-#define mmDP2_DP_SEC_AUD_N_BASE_IDX 2
+-#define mmDP2_DP_SEC_AUD_N_READBACK 0x1b48
+-#define mmDP2_DP_SEC_AUD_N_READBACK_BASE_IDX 2
+-#define mmDP2_DP_SEC_AUD_M 0x1b49
+-#define mmDP2_DP_SEC_AUD_M_BASE_IDX 2
+-#define mmDP2_DP_SEC_AUD_M_READBACK 0x1b4a
+-#define mmDP2_DP_SEC_AUD_M_READBACK_BASE_IDX 2
+-#define mmDP2_DP_SEC_TIMESTAMP 0x1b4b
+-#define mmDP2_DP_SEC_TIMESTAMP_BASE_IDX 2
+-#define mmDP2_DP_SEC_PACKET_CNTL 0x1b4c
+-#define mmDP2_DP_SEC_PACKET_CNTL_BASE_IDX 2
+-#define mmDP2_DP_MSE_RATE_CNTL 0x1b4d
+-#define mmDP2_DP_MSE_RATE_CNTL_BASE_IDX 2
+-#define mmDP2_DP_MSE_RATE_UPDATE 0x1b4f
+-#define mmDP2_DP_MSE_RATE_UPDATE_BASE_IDX 2
+-#define mmDP2_DP_MSE_SAT0 0x1b50
+-#define mmDP2_DP_MSE_SAT0_BASE_IDX 2
+-#define mmDP2_DP_MSE_SAT1 0x1b51
+-#define mmDP2_DP_MSE_SAT1_BASE_IDX 2
+-#define mmDP2_DP_MSE_SAT2 0x1b52
+-#define mmDP2_DP_MSE_SAT2_BASE_IDX 2
+-#define mmDP2_DP_MSE_SAT_UPDATE 0x1b53
+-#define mmDP2_DP_MSE_SAT_UPDATE_BASE_IDX 2
+-#define mmDP2_DP_MSE_LINK_TIMING 0x1b54
+-#define mmDP2_DP_MSE_LINK_TIMING_BASE_IDX 2
+-#define mmDP2_DP_MSE_MISC_CNTL 0x1b55
+-#define mmDP2_DP_MSE_MISC_CNTL_BASE_IDX 2
+-#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x1b5a
+-#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
+-#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x1b5b
+-#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
+-#define mmDP2_DP_MSE_SAT0_STATUS 0x1b5d
+-#define mmDP2_DP_MSE_SAT0_STATUS_BASE_IDX 2
+-#define mmDP2_DP_MSE_SAT1_STATUS 0x1b5e
+-#define mmDP2_DP_MSE_SAT1_STATUS_BASE_IDX 2
+-#define mmDP2_DP_MSE_SAT2_STATUS 0x1b5f
+-#define mmDP2_DP_MSE_SAT2_STATUS_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dig3_dispdec
+-// base address: 0xc00
+-#define mmDIG3_DIG_FE_CNTL 0x1b7e
+-#define mmDIG3_DIG_FE_CNTL_BASE_IDX 2
+-#define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x1b7f
+-#define mmDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
+-#define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x1b80
+-#define mmDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
+-#define mmDIG3_DIG_CLOCK_PATTERN 0x1b81
+-#define mmDIG3_DIG_CLOCK_PATTERN_BASE_IDX 2
+-#define mmDIG3_DIG_TEST_PATTERN 0x1b82
+-#define mmDIG3_DIG_TEST_PATTERN_BASE_IDX 2
+-#define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x1b83
+-#define mmDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
+-#define mmDIG3_DIG_FIFO_STATUS 0x1b84
+-#define mmDIG3_DIG_FIFO_STATUS_BASE_IDX 2
+-#define mmDIG3_HDMI_CONTROL 0x1b87
+-#define mmDIG3_HDMI_CONTROL_BASE_IDX 2
+-#define mmDIG3_HDMI_STATUS 0x1b88
+-#define mmDIG3_HDMI_STATUS_BASE_IDX 2
+-#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x1b89
+-#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
+-#define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x1b8a
+-#define mmDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
+-#define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x1b8b
+-#define mmDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
+-#define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x1b8c
+-#define mmDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
+-#define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x1b8d
+-#define mmDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
+-#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x1b8e
+-#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
+-#define mmDIG3_AFMT_INTERRUPT_STATUS 0x1b8f
+-#define mmDIG3_AFMT_INTERRUPT_STATUS_BASE_IDX 2
+-#define mmDIG3_HDMI_GC 0x1b91
+-#define mmDIG3_HDMI_GC_BASE_IDX 2
+-#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x1b92
+-#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
+-#define mmDIG3_AFMT_ISRC1_0 0x1b93
+-#define mmDIG3_AFMT_ISRC1_0_BASE_IDX 2
+-#define mmDIG3_AFMT_ISRC1_1 0x1b94
+-#define mmDIG3_AFMT_ISRC1_1_BASE_IDX 2
+-#define mmDIG3_AFMT_ISRC1_2 0x1b95
+-#define mmDIG3_AFMT_ISRC1_2_BASE_IDX 2
+-#define mmDIG3_AFMT_ISRC1_3 0x1b96
+-#define mmDIG3_AFMT_ISRC1_3_BASE_IDX 2
+-#define mmDIG3_AFMT_ISRC1_4 0x1b97
+-#define mmDIG3_AFMT_ISRC1_4_BASE_IDX 2
+-#define mmDIG3_AFMT_ISRC2_0 0x1b98
+-#define mmDIG3_AFMT_ISRC2_0_BASE_IDX 2
+-#define mmDIG3_AFMT_ISRC2_1 0x1b99
+-#define mmDIG3_AFMT_ISRC2_1_BASE_IDX 2
+-#define mmDIG3_AFMT_ISRC2_2 0x1b9a
+-#define mmDIG3_AFMT_ISRC2_2_BASE_IDX 2
+-#define mmDIG3_AFMT_ISRC2_3 0x1b9b
+-#define mmDIG3_AFMT_ISRC2_3_BASE_IDX 2
+-#define mmDIG3_AFMT_AVI_INFO0 0x1b9c
+-#define mmDIG3_AFMT_AVI_INFO0_BASE_IDX 2
+-#define mmDIG3_AFMT_AVI_INFO1 0x1b9d
+-#define mmDIG3_AFMT_AVI_INFO1_BASE_IDX 2
+-#define mmDIG3_AFMT_AVI_INFO2 0x1b9e
+-#define mmDIG3_AFMT_AVI_INFO2_BASE_IDX 2
+-#define mmDIG3_AFMT_AVI_INFO3 0x1b9f
+-#define mmDIG3_AFMT_AVI_INFO3_BASE_IDX 2
+-#define mmDIG3_AFMT_MPEG_INFO0 0x1ba0
+-#define mmDIG3_AFMT_MPEG_INFO0_BASE_IDX 2
+-#define mmDIG3_AFMT_MPEG_INFO1 0x1ba1
+-#define mmDIG3_AFMT_MPEG_INFO1_BASE_IDX 2
+-#define mmDIG3_AFMT_GENERIC_HDR 0x1ba2
+-#define mmDIG3_AFMT_GENERIC_HDR_BASE_IDX 2
+-#define mmDIG3_AFMT_GENERIC_0 0x1ba3
+-#define mmDIG3_AFMT_GENERIC_0_BASE_IDX 2
+-#define mmDIG3_AFMT_GENERIC_1 0x1ba4
+-#define mmDIG3_AFMT_GENERIC_1_BASE_IDX 2
+-#define mmDIG3_AFMT_GENERIC_2 0x1ba5
+-#define mmDIG3_AFMT_GENERIC_2_BASE_IDX 2
+-#define mmDIG3_AFMT_GENERIC_3 0x1ba6
+-#define mmDIG3_AFMT_GENERIC_3_BASE_IDX 2
+-#define mmDIG3_AFMT_GENERIC_4 0x1ba7
+-#define mmDIG3_AFMT_GENERIC_4_BASE_IDX 2
+-#define mmDIG3_AFMT_GENERIC_5 0x1ba8
+-#define mmDIG3_AFMT_GENERIC_5_BASE_IDX 2
+-#define mmDIG3_AFMT_GENERIC_6 0x1ba9
+-#define mmDIG3_AFMT_GENERIC_6_BASE_IDX 2
+-#define mmDIG3_AFMT_GENERIC_7 0x1baa
+-#define mmDIG3_AFMT_GENERIC_7_BASE_IDX 2
+-#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x1bab
+-#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
+-#define mmDIG3_HDMI_ACR_32_0 0x1bac
+-#define mmDIG3_HDMI_ACR_32_0_BASE_IDX 2
+-#define mmDIG3_HDMI_ACR_32_1 0x1bad
+-#define mmDIG3_HDMI_ACR_32_1_BASE_IDX 2
+-#define mmDIG3_HDMI_ACR_44_0 0x1bae
+-#define mmDIG3_HDMI_ACR_44_0_BASE_IDX 2
+-#define mmDIG3_HDMI_ACR_44_1 0x1baf
+-#define mmDIG3_HDMI_ACR_44_1_BASE_IDX 2
+-#define mmDIG3_HDMI_ACR_48_0 0x1bb0
+-#define mmDIG3_HDMI_ACR_48_0_BASE_IDX 2
+-#define mmDIG3_HDMI_ACR_48_1 0x1bb1
+-#define mmDIG3_HDMI_ACR_48_1_BASE_IDX 2
+-#define mmDIG3_HDMI_ACR_STATUS_0 0x1bb2
+-#define mmDIG3_HDMI_ACR_STATUS_0_BASE_IDX 2
+-#define mmDIG3_HDMI_ACR_STATUS_1 0x1bb3
+-#define mmDIG3_HDMI_ACR_STATUS_1_BASE_IDX 2
+-#define mmDIG3_AFMT_AUDIO_INFO0 0x1bb4
+-#define mmDIG3_AFMT_AUDIO_INFO0_BASE_IDX 2
+-#define mmDIG3_AFMT_AUDIO_INFO1 0x1bb5
+-#define mmDIG3_AFMT_AUDIO_INFO1_BASE_IDX 2
+-#define mmDIG3_AFMT_60958_0 0x1bb6
+-#define mmDIG3_AFMT_60958_0_BASE_IDX 2
+-#define mmDIG3_AFMT_60958_1 0x1bb7
+-#define mmDIG3_AFMT_60958_1_BASE_IDX 2
+-#define mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x1bb8
+-#define mmDIG3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
+-#define mmDIG3_AFMT_RAMP_CONTROL0 0x1bb9
+-#define mmDIG3_AFMT_RAMP_CONTROL0_BASE_IDX 2
+-#define mmDIG3_AFMT_RAMP_CONTROL1 0x1bba
+-#define mmDIG3_AFMT_RAMP_CONTROL1_BASE_IDX 2
+-#define mmDIG3_AFMT_RAMP_CONTROL2 0x1bbb
+-#define mmDIG3_AFMT_RAMP_CONTROL2_BASE_IDX 2
+-#define mmDIG3_AFMT_RAMP_CONTROL3 0x1bbc
+-#define mmDIG3_AFMT_RAMP_CONTROL3_BASE_IDX 2
+-#define mmDIG3_AFMT_60958_2 0x1bbd
+-#define mmDIG3_AFMT_60958_2_BASE_IDX 2
+-#define mmDIG3_AFMT_AUDIO_CRC_RESULT 0x1bbe
+-#define mmDIG3_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
+-#define mmDIG3_AFMT_STATUS 0x1bbf
+-#define mmDIG3_AFMT_STATUS_BASE_IDX 2
+-#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x1bc0
+-#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
+-#define mmDIG3_AFMT_VBI_PACKET_CONTROL 0x1bc1
+-#define mmDIG3_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
+-#define mmDIG3_AFMT_INFOFRAME_CONTROL0 0x1bc2
+-#define mmDIG3_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
+-#define mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x1bc3
+-#define mmDIG3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
+-#define mmDIG3_DIG_BE_CNTL 0x1bc5
+-#define mmDIG3_DIG_BE_CNTL_BASE_IDX 2
+-#define mmDIG3_DIG_BE_EN_CNTL 0x1bc6
+-#define mmDIG3_DIG_BE_EN_CNTL_BASE_IDX 2
+-#define mmDIG3_TMDS_CNTL 0x1be9
+-#define mmDIG3_TMDS_CNTL_BASE_IDX 2
+-#define mmDIG3_TMDS_CONTROL_CHAR 0x1bea
+-#define mmDIG3_TMDS_CONTROL_CHAR_BASE_IDX 2
+-#define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x1beb
+-#define mmDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
+-#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x1bec
+-#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
+-#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x1bed
+-#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
+-#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x1bee
+-#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
+-#define mmDIG3_TMDS_CTL_BITS 0x1bf0
+-#define mmDIG3_TMDS_CTL_BITS_BASE_IDX 2
+-#define mmDIG3_TMDS_DCBALANCER_CONTROL 0x1bf1
+-#define mmDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
+-#define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x1bf3
+-#define mmDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
+-#define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x1bf4
+-#define mmDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
+-#define mmDIG3_DIG_VERSION 0x1bf6
+-#define mmDIG3_DIG_VERSION_BASE_IDX 2
+-#define mmDIG3_DIG_LANE_ENABLE 0x1bf7
+-#define mmDIG3_DIG_LANE_ENABLE_BASE_IDX 2
+-#define mmDIG3_AFMT_CNTL 0x1bfc
+-#define mmDIG3_AFMT_CNTL_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dp3_dispdec
+-// base address: 0xc00
+-#define mmDP3_DP_LINK_CNTL 0x1c1e
+-#define mmDP3_DP_LINK_CNTL_BASE_IDX 2
+-#define mmDP3_DP_PIXEL_FORMAT 0x1c1f
+-#define mmDP3_DP_PIXEL_FORMAT_BASE_IDX 2
+-#define mmDP3_DP_MSA_COLORIMETRY 0x1c20
+-#define mmDP3_DP_MSA_COLORIMETRY_BASE_IDX 2
+-#define mmDP3_DP_CONFIG 0x1c21
+-#define mmDP3_DP_CONFIG_BASE_IDX 2
+-#define mmDP3_DP_VID_STREAM_CNTL 0x1c22
+-#define mmDP3_DP_VID_STREAM_CNTL_BASE_IDX 2
+-#define mmDP3_DP_STEER_FIFO 0x1c23
+-#define mmDP3_DP_STEER_FIFO_BASE_IDX 2
+-#define mmDP3_DP_MSA_MISC 0x1c24
+-#define mmDP3_DP_MSA_MISC_BASE_IDX 2
+-#define mmDP3_DP_VID_TIMING 0x1c26
+-#define mmDP3_DP_VID_TIMING_BASE_IDX 2
+-#define mmDP3_DP_VID_N 0x1c27
+-#define mmDP3_DP_VID_N_BASE_IDX 2
+-#define mmDP3_DP_VID_M 0x1c28
+-#define mmDP3_DP_VID_M_BASE_IDX 2
+-#define mmDP3_DP_LINK_FRAMING_CNTL 0x1c29
+-#define mmDP3_DP_LINK_FRAMING_CNTL_BASE_IDX 2
+-#define mmDP3_DP_HBR2_EYE_PATTERN 0x1c2a
+-#define mmDP3_DP_HBR2_EYE_PATTERN_BASE_IDX 2
+-#define mmDP3_DP_VID_MSA_VBID 0x1c2b
+-#define mmDP3_DP_VID_MSA_VBID_BASE_IDX 2
+-#define mmDP3_DP_VID_INTERRUPT_CNTL 0x1c2c
+-#define mmDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
+-#define mmDP3_DP_DPHY_CNTL 0x1c2d
+-#define mmDP3_DP_DPHY_CNTL_BASE_IDX 2
+-#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x1c2e
+-#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
+-#define mmDP3_DP_DPHY_SYM0 0x1c2f
+-#define mmDP3_DP_DPHY_SYM0_BASE_IDX 2
+-#define mmDP3_DP_DPHY_SYM1 0x1c30
+-#define mmDP3_DP_DPHY_SYM1_BASE_IDX 2
+-#define mmDP3_DP_DPHY_SYM2 0x1c31
+-#define mmDP3_DP_DPHY_SYM2_BASE_IDX 2
+-#define mmDP3_DP_DPHY_8B10B_CNTL 0x1c32
+-#define mmDP3_DP_DPHY_8B10B_CNTL_BASE_IDX 2
+-#define mmDP3_DP_DPHY_PRBS_CNTL 0x1c33
+-#define mmDP3_DP_DPHY_PRBS_CNTL_BASE_IDX 2
+-#define mmDP3_DP_DPHY_SCRAM_CNTL 0x1c34
+-#define mmDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
+-#define mmDP3_DP_DPHY_CRC_EN 0x1c35
+-#define mmDP3_DP_DPHY_CRC_EN_BASE_IDX 2
+-#define mmDP3_DP_DPHY_CRC_CNTL 0x1c36
+-#define mmDP3_DP_DPHY_CRC_CNTL_BASE_IDX 2
+-#define mmDP3_DP_DPHY_CRC_RESULT 0x1c37
+-#define mmDP3_DP_DPHY_CRC_RESULT_BASE_IDX 2
+-#define mmDP3_DP_DPHY_CRC_MST_CNTL 0x1c38
+-#define mmDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
+-#define mmDP3_DP_DPHY_CRC_MST_STATUS 0x1c39
+-#define mmDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
+-#define mmDP3_DP_DPHY_FAST_TRAINING 0x1c3a
+-#define mmDP3_DP_DPHY_FAST_TRAINING_BASE_IDX 2
+-#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x1c3b
+-#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
+-#define mmDP3_DP_MSA_V_TIMING_OVERRIDE1 0x1c3c
+-#define mmDP3_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2
+-#define mmDP3_DP_MSA_V_TIMING_OVERRIDE2 0x1c3d
+-#define mmDP3_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2
+-#define mmDP3_DP_SEC_CNTL 0x1c41
+-#define mmDP3_DP_SEC_CNTL_BASE_IDX 2
+-#define mmDP3_DP_SEC_CNTL1 0x1c42
+-#define mmDP3_DP_SEC_CNTL1_BASE_IDX 2
+-#define mmDP3_DP_SEC_FRAMING1 0x1c43
+-#define mmDP3_DP_SEC_FRAMING1_BASE_IDX 2
+-#define mmDP3_DP_SEC_FRAMING2 0x1c44
+-#define mmDP3_DP_SEC_FRAMING2_BASE_IDX 2
+-#define mmDP3_DP_SEC_FRAMING3 0x1c45
+-#define mmDP3_DP_SEC_FRAMING3_BASE_IDX 2
+-#define mmDP3_DP_SEC_FRAMING4 0x1c46
+-#define mmDP3_DP_SEC_FRAMING4_BASE_IDX 2
+-#define mmDP3_DP_SEC_AUD_N 0x1c47
+-#define mmDP3_DP_SEC_AUD_N_BASE_IDX 2
+-#define mmDP3_DP_SEC_AUD_N_READBACK 0x1c48
+-#define mmDP3_DP_SEC_AUD_N_READBACK_BASE_IDX 2
+-#define mmDP3_DP_SEC_AUD_M 0x1c49
+-#define mmDP3_DP_SEC_AUD_M_BASE_IDX 2
+-#define mmDP3_DP_SEC_AUD_M_READBACK 0x1c4a
+-#define mmDP3_DP_SEC_AUD_M_READBACK_BASE_IDX 2
+-#define mmDP3_DP_SEC_TIMESTAMP 0x1c4b
+-#define mmDP3_DP_SEC_TIMESTAMP_BASE_IDX 2
+-#define mmDP3_DP_SEC_PACKET_CNTL 0x1c4c
+-#define mmDP3_DP_SEC_PACKET_CNTL_BASE_IDX 2
+-#define mmDP3_DP_MSE_RATE_CNTL 0x1c4d
+-#define mmDP3_DP_MSE_RATE_CNTL_BASE_IDX 2
+-#define mmDP3_DP_MSE_RATE_UPDATE 0x1c4f
+-#define mmDP3_DP_MSE_RATE_UPDATE_BASE_IDX 2
+-#define mmDP3_DP_MSE_SAT0 0x1c50
+-#define mmDP3_DP_MSE_SAT0_BASE_IDX 2
+-#define mmDP3_DP_MSE_SAT1 0x1c51
+-#define mmDP3_DP_MSE_SAT1_BASE_IDX 2
+-#define mmDP3_DP_MSE_SAT2 0x1c52
+-#define mmDP3_DP_MSE_SAT2_BASE_IDX 2
+-#define mmDP3_DP_MSE_SAT_UPDATE 0x1c53
+-#define mmDP3_DP_MSE_SAT_UPDATE_BASE_IDX 2
+-#define mmDP3_DP_MSE_LINK_TIMING 0x1c54
+-#define mmDP3_DP_MSE_LINK_TIMING_BASE_IDX 2
+-#define mmDP3_DP_MSE_MISC_CNTL 0x1c55
+-#define mmDP3_DP_MSE_MISC_CNTL_BASE_IDX 2
+-#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x1c5a
+-#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
+-#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x1c5b
+-#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
+-#define mmDP3_DP_MSE_SAT0_STATUS 0x1c5d
+-#define mmDP3_DP_MSE_SAT0_STATUS_BASE_IDX 2
+-#define mmDP3_DP_MSE_SAT1_STATUS 0x1c5e
+-#define mmDP3_DP_MSE_SAT1_STATUS_BASE_IDX 2
+-#define mmDP3_DP_MSE_SAT2_STATUS 0x1c5f
+-#define mmDP3_DP_MSE_SAT2_STATUS_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dig4_dispdec
+-// base address: 0x1000
+-#define mmDIG4_DIG_FE_CNTL 0x1c7e
+-#define mmDIG4_DIG_FE_CNTL_BASE_IDX 2
+-#define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x1c7f
+-#define mmDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
+-#define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x1c80
+-#define mmDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
+-#define mmDIG4_DIG_CLOCK_PATTERN 0x1c81
+-#define mmDIG4_DIG_CLOCK_PATTERN_BASE_IDX 2
+-#define mmDIG4_DIG_TEST_PATTERN 0x1c82
+-#define mmDIG4_DIG_TEST_PATTERN_BASE_IDX 2
+-#define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x1c83
+-#define mmDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
+-#define mmDIG4_DIG_FIFO_STATUS 0x1c84
+-#define mmDIG4_DIG_FIFO_STATUS_BASE_IDX 2
+-#define mmDIG4_HDMI_CONTROL 0x1c87
+-#define mmDIG4_HDMI_CONTROL_BASE_IDX 2
+-#define mmDIG4_HDMI_STATUS 0x1c88
+-#define mmDIG4_HDMI_STATUS_BASE_IDX 2
+-#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x1c89
+-#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
+-#define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x1c8a
+-#define mmDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
+-#define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x1c8b
+-#define mmDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
+-#define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x1c8c
+-#define mmDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
+-#define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x1c8d
+-#define mmDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
+-#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x1c8e
+-#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
+-#define mmDIG4_AFMT_INTERRUPT_STATUS 0x1c8f
+-#define mmDIG4_AFMT_INTERRUPT_STATUS_BASE_IDX 2
+-#define mmDIG4_HDMI_GC 0x1c91
+-#define mmDIG4_HDMI_GC_BASE_IDX 2
+-#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x1c92
+-#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
+-#define mmDIG4_AFMT_ISRC1_0 0x1c93
+-#define mmDIG4_AFMT_ISRC1_0_BASE_IDX 2
+-#define mmDIG4_AFMT_ISRC1_1 0x1c94
+-#define mmDIG4_AFMT_ISRC1_1_BASE_IDX 2
+-#define mmDIG4_AFMT_ISRC1_2 0x1c95
+-#define mmDIG4_AFMT_ISRC1_2_BASE_IDX 2
+-#define mmDIG4_AFMT_ISRC1_3 0x1c96
+-#define mmDIG4_AFMT_ISRC1_3_BASE_IDX 2
+-#define mmDIG4_AFMT_ISRC1_4 0x1c97
+-#define mmDIG4_AFMT_ISRC1_4_BASE_IDX 2
+-#define mmDIG4_AFMT_ISRC2_0 0x1c98
+-#define mmDIG4_AFMT_ISRC2_0_BASE_IDX 2
+-#define mmDIG4_AFMT_ISRC2_1 0x1c99
+-#define mmDIG4_AFMT_ISRC2_1_BASE_IDX 2
+-#define mmDIG4_AFMT_ISRC2_2 0x1c9a
+-#define mmDIG4_AFMT_ISRC2_2_BASE_IDX 2
+-#define mmDIG4_AFMT_ISRC2_3 0x1c9b
+-#define mmDIG4_AFMT_ISRC2_3_BASE_IDX 2
+-#define mmDIG4_AFMT_AVI_INFO0 0x1c9c
+-#define mmDIG4_AFMT_AVI_INFO0_BASE_IDX 2
+-#define mmDIG4_AFMT_AVI_INFO1 0x1c9d
+-#define mmDIG4_AFMT_AVI_INFO1_BASE_IDX 2
+-#define mmDIG4_AFMT_AVI_INFO2 0x1c9e
+-#define mmDIG4_AFMT_AVI_INFO2_BASE_IDX 2
+-#define mmDIG4_AFMT_AVI_INFO3 0x1c9f
+-#define mmDIG4_AFMT_AVI_INFO3_BASE_IDX 2
+-#define mmDIG4_AFMT_MPEG_INFO0 0x1ca0
+-#define mmDIG4_AFMT_MPEG_INFO0_BASE_IDX 2
+-#define mmDIG4_AFMT_MPEG_INFO1 0x1ca1
+-#define mmDIG4_AFMT_MPEG_INFO1_BASE_IDX 2
+-#define mmDIG4_AFMT_GENERIC_HDR 0x1ca2
+-#define mmDIG4_AFMT_GENERIC_HDR_BASE_IDX 2
+-#define mmDIG4_AFMT_GENERIC_0 0x1ca3
+-#define mmDIG4_AFMT_GENERIC_0_BASE_IDX 2
+-#define mmDIG4_AFMT_GENERIC_1 0x1ca4
+-#define mmDIG4_AFMT_GENERIC_1_BASE_IDX 2
+-#define mmDIG4_AFMT_GENERIC_2 0x1ca5
+-#define mmDIG4_AFMT_GENERIC_2_BASE_IDX 2
+-#define mmDIG4_AFMT_GENERIC_3 0x1ca6
+-#define mmDIG4_AFMT_GENERIC_3_BASE_IDX 2
+-#define mmDIG4_AFMT_GENERIC_4 0x1ca7
+-#define mmDIG4_AFMT_GENERIC_4_BASE_IDX 2
+-#define mmDIG4_AFMT_GENERIC_5 0x1ca8
+-#define mmDIG4_AFMT_GENERIC_5_BASE_IDX 2
+-#define mmDIG4_AFMT_GENERIC_6 0x1ca9
+-#define mmDIG4_AFMT_GENERIC_6_BASE_IDX 2
+-#define mmDIG4_AFMT_GENERIC_7 0x1caa
+-#define mmDIG4_AFMT_GENERIC_7_BASE_IDX 2
+-#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x1cab
+-#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
+-#define mmDIG4_HDMI_ACR_32_0 0x1cac
+-#define mmDIG4_HDMI_ACR_32_0_BASE_IDX 2
+-#define mmDIG4_HDMI_ACR_32_1 0x1cad
+-#define mmDIG4_HDMI_ACR_32_1_BASE_IDX 2
+-#define mmDIG4_HDMI_ACR_44_0 0x1cae
+-#define mmDIG4_HDMI_ACR_44_0_BASE_IDX 2
+-#define mmDIG4_HDMI_ACR_44_1 0x1caf
+-#define mmDIG4_HDMI_ACR_44_1_BASE_IDX 2
+-#define mmDIG4_HDMI_ACR_48_0 0x1cb0
+-#define mmDIG4_HDMI_ACR_48_0_BASE_IDX 2
+-#define mmDIG4_HDMI_ACR_48_1 0x1cb1
+-#define mmDIG4_HDMI_ACR_48_1_BASE_IDX 2
+-#define mmDIG4_HDMI_ACR_STATUS_0 0x1cb2
+-#define mmDIG4_HDMI_ACR_STATUS_0_BASE_IDX 2
+-#define mmDIG4_HDMI_ACR_STATUS_1 0x1cb3
+-#define mmDIG4_HDMI_ACR_STATUS_1_BASE_IDX 2
+-#define mmDIG4_AFMT_AUDIO_INFO0 0x1cb4
+-#define mmDIG4_AFMT_AUDIO_INFO0_BASE_IDX 2
+-#define mmDIG4_AFMT_AUDIO_INFO1 0x1cb5
+-#define mmDIG4_AFMT_AUDIO_INFO1_BASE_IDX 2
+-#define mmDIG4_AFMT_60958_0 0x1cb6
+-#define mmDIG4_AFMT_60958_0_BASE_IDX 2
+-#define mmDIG4_AFMT_60958_1 0x1cb7
+-#define mmDIG4_AFMT_60958_1_BASE_IDX 2
+-#define mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x1cb8
+-#define mmDIG4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
+-#define mmDIG4_AFMT_RAMP_CONTROL0 0x1cb9
+-#define mmDIG4_AFMT_RAMP_CONTROL0_BASE_IDX 2
+-#define mmDIG4_AFMT_RAMP_CONTROL1 0x1cba
+-#define mmDIG4_AFMT_RAMP_CONTROL1_BASE_IDX 2
+-#define mmDIG4_AFMT_RAMP_CONTROL2 0x1cbb
+-#define mmDIG4_AFMT_RAMP_CONTROL2_BASE_IDX 2
+-#define mmDIG4_AFMT_RAMP_CONTROL3 0x1cbc
+-#define mmDIG4_AFMT_RAMP_CONTROL3_BASE_IDX 2
+-#define mmDIG4_AFMT_60958_2 0x1cbd
+-#define mmDIG4_AFMT_60958_2_BASE_IDX 2
+-#define mmDIG4_AFMT_AUDIO_CRC_RESULT 0x1cbe
+-#define mmDIG4_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
+-#define mmDIG4_AFMT_STATUS 0x1cbf
+-#define mmDIG4_AFMT_STATUS_BASE_IDX 2
+-#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x1cc0
+-#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
+-#define mmDIG4_AFMT_VBI_PACKET_CONTROL 0x1cc1
+-#define mmDIG4_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
+-#define mmDIG4_AFMT_INFOFRAME_CONTROL0 0x1cc2
+-#define mmDIG4_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
+-#define mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x1cc3
+-#define mmDIG4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
+-#define mmDIG4_DIG_BE_CNTL 0x1cc5
+-#define mmDIG4_DIG_BE_CNTL_BASE_IDX 2
+-#define mmDIG4_DIG_BE_EN_CNTL 0x1cc6
+-#define mmDIG4_DIG_BE_EN_CNTL_BASE_IDX 2
+-#define mmDIG4_TMDS_CNTL 0x1ce9
+-#define mmDIG4_TMDS_CNTL_BASE_IDX 2
+-#define mmDIG4_TMDS_CONTROL_CHAR 0x1cea
+-#define mmDIG4_TMDS_CONTROL_CHAR_BASE_IDX 2
+-#define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x1ceb
+-#define mmDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
+-#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x1cec
+-#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
+-#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x1ced
+-#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
+-#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x1cee
+-#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
+-#define mmDIG4_TMDS_CTL_BITS 0x1cf0
+-#define mmDIG4_TMDS_CTL_BITS_BASE_IDX 2
+-#define mmDIG4_TMDS_DCBALANCER_CONTROL 0x1cf1
+-#define mmDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
+-#define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x1cf3
+-#define mmDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
+-#define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x1cf4
+-#define mmDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
+-#define mmDIG4_DIG_VERSION 0x1cf6
+-#define mmDIG4_DIG_VERSION_BASE_IDX 2
+-#define mmDIG4_DIG_LANE_ENABLE 0x1cf7
+-#define mmDIG4_DIG_LANE_ENABLE_BASE_IDX 2
+-#define mmDIG4_AFMT_CNTL 0x1cfc
+-#define mmDIG4_AFMT_CNTL_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dp4_dispdec
+-// base address: 0x1000
+-#define mmDP4_DP_LINK_CNTL 0x1d1e
+-#define mmDP4_DP_LINK_CNTL_BASE_IDX 2
+-#define mmDP4_DP_PIXEL_FORMAT 0x1d1f
+-#define mmDP4_DP_PIXEL_FORMAT_BASE_IDX 2
+-#define mmDP4_DP_MSA_COLORIMETRY 0x1d20
+-#define mmDP4_DP_MSA_COLORIMETRY_BASE_IDX 2
+-#define mmDP4_DP_CONFIG 0x1d21
+-#define mmDP4_DP_CONFIG_BASE_IDX 2
+-#define mmDP4_DP_VID_STREAM_CNTL 0x1d22
+-#define mmDP4_DP_VID_STREAM_CNTL_BASE_IDX 2
+-#define mmDP4_DP_STEER_FIFO 0x1d23
+-#define mmDP4_DP_STEER_FIFO_BASE_IDX 2
+-#define mmDP4_DP_MSA_MISC 0x1d24
+-#define mmDP4_DP_MSA_MISC_BASE_IDX 2
+-#define mmDP4_DP_VID_TIMING 0x1d26
+-#define mmDP4_DP_VID_TIMING_BASE_IDX 2
+-#define mmDP4_DP_VID_N 0x1d27
+-#define mmDP4_DP_VID_N_BASE_IDX 2
+-#define mmDP4_DP_VID_M 0x1d28
+-#define mmDP4_DP_VID_M_BASE_IDX 2
+-#define mmDP4_DP_LINK_FRAMING_CNTL 0x1d29
+-#define mmDP4_DP_LINK_FRAMING_CNTL_BASE_IDX 2
+-#define mmDP4_DP_HBR2_EYE_PATTERN 0x1d2a
+-#define mmDP4_DP_HBR2_EYE_PATTERN_BASE_IDX 2
+-#define mmDP4_DP_VID_MSA_VBID 0x1d2b
+-#define mmDP4_DP_VID_MSA_VBID_BASE_IDX 2
+-#define mmDP4_DP_VID_INTERRUPT_CNTL 0x1d2c
+-#define mmDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
+-#define mmDP4_DP_DPHY_CNTL 0x1d2d
+-#define mmDP4_DP_DPHY_CNTL_BASE_IDX 2
+-#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x1d2e
+-#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
+-#define mmDP4_DP_DPHY_SYM0 0x1d2f
+-#define mmDP4_DP_DPHY_SYM0_BASE_IDX 2
+-#define mmDP4_DP_DPHY_SYM1 0x1d30
+-#define mmDP4_DP_DPHY_SYM1_BASE_IDX 2
+-#define mmDP4_DP_DPHY_SYM2 0x1d31
+-#define mmDP4_DP_DPHY_SYM2_BASE_IDX 2
+-#define mmDP4_DP_DPHY_8B10B_CNTL 0x1d32
+-#define mmDP4_DP_DPHY_8B10B_CNTL_BASE_IDX 2
+-#define mmDP4_DP_DPHY_PRBS_CNTL 0x1d33
+-#define mmDP4_DP_DPHY_PRBS_CNTL_BASE_IDX 2
+-#define mmDP4_DP_DPHY_SCRAM_CNTL 0x1d34
+-#define mmDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
+-#define mmDP4_DP_DPHY_CRC_EN 0x1d35
+-#define mmDP4_DP_DPHY_CRC_EN_BASE_IDX 2
+-#define mmDP4_DP_DPHY_CRC_CNTL 0x1d36
+-#define mmDP4_DP_DPHY_CRC_CNTL_BASE_IDX 2
+-#define mmDP4_DP_DPHY_CRC_RESULT 0x1d37
+-#define mmDP4_DP_DPHY_CRC_RESULT_BASE_IDX 2
+-#define mmDP4_DP_DPHY_CRC_MST_CNTL 0x1d38
+-#define mmDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
+-#define mmDP4_DP_DPHY_CRC_MST_STATUS 0x1d39
+-#define mmDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
+-#define mmDP4_DP_DPHY_FAST_TRAINING 0x1d3a
+-#define mmDP4_DP_DPHY_FAST_TRAINING_BASE_IDX 2
+-#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x1d3b
+-#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
+-#define mmDP4_DP_MSA_V_TIMING_OVERRIDE1 0x1d3c
+-#define mmDP4_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2
+-#define mmDP4_DP_MSA_V_TIMING_OVERRIDE2 0x1d3d
+-#define mmDP4_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2
+-#define mmDP4_DP_SEC_CNTL 0x1d41
+-#define mmDP4_DP_SEC_CNTL_BASE_IDX 2
+-#define mmDP4_DP_SEC_CNTL1 0x1d42
+-#define mmDP4_DP_SEC_CNTL1_BASE_IDX 2
+-#define mmDP4_DP_SEC_FRAMING1 0x1d43
+-#define mmDP4_DP_SEC_FRAMING1_BASE_IDX 2
+-#define mmDP4_DP_SEC_FRAMING2 0x1d44
+-#define mmDP4_DP_SEC_FRAMING2_BASE_IDX 2
+-#define mmDP4_DP_SEC_FRAMING3 0x1d45
+-#define mmDP4_DP_SEC_FRAMING3_BASE_IDX 2
+-#define mmDP4_DP_SEC_FRAMING4 0x1d46
+-#define mmDP4_DP_SEC_FRAMING4_BASE_IDX 2
+-#define mmDP4_DP_SEC_AUD_N 0x1d47
+-#define mmDP4_DP_SEC_AUD_N_BASE_IDX 2
+-#define mmDP4_DP_SEC_AUD_N_READBACK 0x1d48
+-#define mmDP4_DP_SEC_AUD_N_READBACK_BASE_IDX 2
+-#define mmDP4_DP_SEC_AUD_M 0x1d49
+-#define mmDP4_DP_SEC_AUD_M_BASE_IDX 2
+-#define mmDP4_DP_SEC_AUD_M_READBACK 0x1d4a
+-#define mmDP4_DP_SEC_AUD_M_READBACK_BASE_IDX 2
+-#define mmDP4_DP_SEC_TIMESTAMP 0x1d4b
+-#define mmDP4_DP_SEC_TIMESTAMP_BASE_IDX 2
+-#define mmDP4_DP_SEC_PACKET_CNTL 0x1d4c
+-#define mmDP4_DP_SEC_PACKET_CNTL_BASE_IDX 2
+-#define mmDP4_DP_MSE_RATE_CNTL 0x1d4d
+-#define mmDP4_DP_MSE_RATE_CNTL_BASE_IDX 2
+-#define mmDP4_DP_MSE_RATE_UPDATE 0x1d4f
+-#define mmDP4_DP_MSE_RATE_UPDATE_BASE_IDX 2
+-#define mmDP4_DP_MSE_SAT0 0x1d50
+-#define mmDP4_DP_MSE_SAT0_BASE_IDX 2
+-#define mmDP4_DP_MSE_SAT1 0x1d51
+-#define mmDP4_DP_MSE_SAT1_BASE_IDX 2
+-#define mmDP4_DP_MSE_SAT2 0x1d52
+-#define mmDP4_DP_MSE_SAT2_BASE_IDX 2
+-#define mmDP4_DP_MSE_SAT_UPDATE 0x1d53
+-#define mmDP4_DP_MSE_SAT_UPDATE_BASE_IDX 2
+-#define mmDP4_DP_MSE_LINK_TIMING 0x1d54
+-#define mmDP4_DP_MSE_LINK_TIMING_BASE_IDX 2
+-#define mmDP4_DP_MSE_MISC_CNTL 0x1d55
+-#define mmDP4_DP_MSE_MISC_CNTL_BASE_IDX 2
+-#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x1d5a
+-#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
+-#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x1d5b
+-#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
+-#define mmDP4_DP_MSE_SAT0_STATUS 0x1d5d
+-#define mmDP4_DP_MSE_SAT0_STATUS_BASE_IDX 2
+-#define mmDP4_DP_MSE_SAT1_STATUS 0x1d5e
+-#define mmDP4_DP_MSE_SAT1_STATUS_BASE_IDX 2
+-#define mmDP4_DP_MSE_SAT2_STATUS 0x1d5f
+-#define mmDP4_DP_MSE_SAT2_STATUS_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dig5_dispdec
+-// base address: 0x1400
+-#define mmDIG5_DIG_FE_CNTL 0x1d7e
+-#define mmDIG5_DIG_FE_CNTL_BASE_IDX 2
+-#define mmDIG5_DIG_OUTPUT_CRC_CNTL 0x1d7f
+-#define mmDIG5_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
+-#define mmDIG5_DIG_OUTPUT_CRC_RESULT 0x1d80
+-#define mmDIG5_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
+-#define mmDIG5_DIG_CLOCK_PATTERN 0x1d81
+-#define mmDIG5_DIG_CLOCK_PATTERN_BASE_IDX 2
+-#define mmDIG5_DIG_TEST_PATTERN 0x1d82
+-#define mmDIG5_DIG_TEST_PATTERN_BASE_IDX 2
+-#define mmDIG5_DIG_RANDOM_PATTERN_SEED 0x1d83
+-#define mmDIG5_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
+-#define mmDIG5_DIG_FIFO_STATUS 0x1d84
+-#define mmDIG5_DIG_FIFO_STATUS_BASE_IDX 2
+-#define mmDIG5_HDMI_CONTROL 0x1d87
+-#define mmDIG5_HDMI_CONTROL_BASE_IDX 2
+-#define mmDIG5_HDMI_STATUS 0x1d88
+-#define mmDIG5_HDMI_STATUS_BASE_IDX 2
+-#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x1d89
+-#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
+-#define mmDIG5_HDMI_ACR_PACKET_CONTROL 0x1d8a
+-#define mmDIG5_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
+-#define mmDIG5_HDMI_VBI_PACKET_CONTROL 0x1d8b
+-#define mmDIG5_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
+-#define mmDIG5_HDMI_INFOFRAME_CONTROL0 0x1d8c
+-#define mmDIG5_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
+-#define mmDIG5_HDMI_INFOFRAME_CONTROL1 0x1d8d
+-#define mmDIG5_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
+-#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x1d8e
+-#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
+-#define mmDIG5_AFMT_INTERRUPT_STATUS 0x1d8f
+-#define mmDIG5_AFMT_INTERRUPT_STATUS_BASE_IDX 2
+-#define mmDIG5_HDMI_GC 0x1d91
+-#define mmDIG5_HDMI_GC_BASE_IDX 2
+-#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x1d92
+-#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
+-#define mmDIG5_AFMT_ISRC1_0 0x1d93
+-#define mmDIG5_AFMT_ISRC1_0_BASE_IDX 2
+-#define mmDIG5_AFMT_ISRC1_1 0x1d94
+-#define mmDIG5_AFMT_ISRC1_1_BASE_IDX 2
+-#define mmDIG5_AFMT_ISRC1_2 0x1d95
+-#define mmDIG5_AFMT_ISRC1_2_BASE_IDX 2
+-#define mmDIG5_AFMT_ISRC1_3 0x1d96
+-#define mmDIG5_AFMT_ISRC1_3_BASE_IDX 2
+-#define mmDIG5_AFMT_ISRC1_4 0x1d97
+-#define mmDIG5_AFMT_ISRC1_4_BASE_IDX 2
+-#define mmDIG5_AFMT_ISRC2_0 0x1d98
+-#define mmDIG5_AFMT_ISRC2_0_BASE_IDX 2
+-#define mmDIG5_AFMT_ISRC2_1 0x1d99
+-#define mmDIG5_AFMT_ISRC2_1_BASE_IDX 2
+-#define mmDIG5_AFMT_ISRC2_2 0x1d9a
+-#define mmDIG5_AFMT_ISRC2_2_BASE_IDX 2
+-#define mmDIG5_AFMT_ISRC2_3 0x1d9b
+-#define mmDIG5_AFMT_ISRC2_3_BASE_IDX 2
+-#define mmDIG5_AFMT_AVI_INFO0 0x1d9c
+-#define mmDIG5_AFMT_AVI_INFO0_BASE_IDX 2
+-#define mmDIG5_AFMT_AVI_INFO1 0x1d9d
+-#define mmDIG5_AFMT_AVI_INFO1_BASE_IDX 2
+-#define mmDIG5_AFMT_AVI_INFO2 0x1d9e
+-#define mmDIG5_AFMT_AVI_INFO2_BASE_IDX 2
+-#define mmDIG5_AFMT_AVI_INFO3 0x1d9f
+-#define mmDIG5_AFMT_AVI_INFO3_BASE_IDX 2
+-#define mmDIG5_AFMT_MPEG_INFO0 0x1da0
+-#define mmDIG5_AFMT_MPEG_INFO0_BASE_IDX 2
+-#define mmDIG5_AFMT_MPEG_INFO1 0x1da1
+-#define mmDIG5_AFMT_MPEG_INFO1_BASE_IDX 2
+-#define mmDIG5_AFMT_GENERIC_HDR 0x1da2
+-#define mmDIG5_AFMT_GENERIC_HDR_BASE_IDX 2
+-#define mmDIG5_AFMT_GENERIC_0 0x1da3
+-#define mmDIG5_AFMT_GENERIC_0_BASE_IDX 2
+-#define mmDIG5_AFMT_GENERIC_1 0x1da4
+-#define mmDIG5_AFMT_GENERIC_1_BASE_IDX 2
+-#define mmDIG5_AFMT_GENERIC_2 0x1da5
+-#define mmDIG5_AFMT_GENERIC_2_BASE_IDX 2
+-#define mmDIG5_AFMT_GENERIC_3 0x1da6
+-#define mmDIG5_AFMT_GENERIC_3_BASE_IDX 2
+-#define mmDIG5_AFMT_GENERIC_4 0x1da7
+-#define mmDIG5_AFMT_GENERIC_4_BASE_IDX 2
+-#define mmDIG5_AFMT_GENERIC_5 0x1da8
+-#define mmDIG5_AFMT_GENERIC_5_BASE_IDX 2
+-#define mmDIG5_AFMT_GENERIC_6 0x1da9
+-#define mmDIG5_AFMT_GENERIC_6_BASE_IDX 2
+-#define mmDIG5_AFMT_GENERIC_7 0x1daa
+-#define mmDIG5_AFMT_GENERIC_7_BASE_IDX 2
+-#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x1dab
+-#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
+-#define mmDIG5_HDMI_ACR_32_0 0x1dac
+-#define mmDIG5_HDMI_ACR_32_0_BASE_IDX 2
+-#define mmDIG5_HDMI_ACR_32_1 0x1dad
+-#define mmDIG5_HDMI_ACR_32_1_BASE_IDX 2
+-#define mmDIG5_HDMI_ACR_44_0 0x1dae
+-#define mmDIG5_HDMI_ACR_44_0_BASE_IDX 2
+-#define mmDIG5_HDMI_ACR_44_1 0x1daf
+-#define mmDIG5_HDMI_ACR_44_1_BASE_IDX 2
+-#define mmDIG5_HDMI_ACR_48_0 0x1db0
+-#define mmDIG5_HDMI_ACR_48_0_BASE_IDX 2
+-#define mmDIG5_HDMI_ACR_48_1 0x1db1
+-#define mmDIG5_HDMI_ACR_48_1_BASE_IDX 2
+-#define mmDIG5_HDMI_ACR_STATUS_0 0x1db2
+-#define mmDIG5_HDMI_ACR_STATUS_0_BASE_IDX 2
+-#define mmDIG5_HDMI_ACR_STATUS_1 0x1db3
+-#define mmDIG5_HDMI_ACR_STATUS_1_BASE_IDX 2
+-#define mmDIG5_AFMT_AUDIO_INFO0 0x1db4
+-#define mmDIG5_AFMT_AUDIO_INFO0_BASE_IDX 2
+-#define mmDIG5_AFMT_AUDIO_INFO1 0x1db5
+-#define mmDIG5_AFMT_AUDIO_INFO1_BASE_IDX 2
+-#define mmDIG5_AFMT_60958_0 0x1db6
+-#define mmDIG5_AFMT_60958_0_BASE_IDX 2
+-#define mmDIG5_AFMT_60958_1 0x1db7
+-#define mmDIG5_AFMT_60958_1_BASE_IDX 2
+-#define mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x1db8
+-#define mmDIG5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
+-#define mmDIG5_AFMT_RAMP_CONTROL0 0x1db9
+-#define mmDIG5_AFMT_RAMP_CONTROL0_BASE_IDX 2
+-#define mmDIG5_AFMT_RAMP_CONTROL1 0x1dba
+-#define mmDIG5_AFMT_RAMP_CONTROL1_BASE_IDX 2
+-#define mmDIG5_AFMT_RAMP_CONTROL2 0x1dbb
+-#define mmDIG5_AFMT_RAMP_CONTROL2_BASE_IDX 2
+-#define mmDIG5_AFMT_RAMP_CONTROL3 0x1dbc
+-#define mmDIG5_AFMT_RAMP_CONTROL3_BASE_IDX 2
+-#define mmDIG5_AFMT_60958_2 0x1dbd
+-#define mmDIG5_AFMT_60958_2_BASE_IDX 2
+-#define mmDIG5_AFMT_AUDIO_CRC_RESULT 0x1dbe
+-#define mmDIG5_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
+-#define mmDIG5_AFMT_STATUS 0x1dbf
+-#define mmDIG5_AFMT_STATUS_BASE_IDX 2
+-#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x1dc0
+-#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
+-#define mmDIG5_AFMT_VBI_PACKET_CONTROL 0x1dc1
+-#define mmDIG5_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
+-#define mmDIG5_AFMT_INFOFRAME_CONTROL0 0x1dc2
+-#define mmDIG5_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
+-#define mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x1dc3
+-#define mmDIG5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
+-#define mmDIG5_DIG_BE_CNTL 0x1dc5
+-#define mmDIG5_DIG_BE_CNTL_BASE_IDX 2
+-#define mmDIG5_DIG_BE_EN_CNTL 0x1dc6
+-#define mmDIG5_DIG_BE_EN_CNTL_BASE_IDX 2
+-#define mmDIG5_TMDS_CNTL 0x1de9
+-#define mmDIG5_TMDS_CNTL_BASE_IDX 2
+-#define mmDIG5_TMDS_CONTROL_CHAR 0x1dea
+-#define mmDIG5_TMDS_CONTROL_CHAR_BASE_IDX 2
+-#define mmDIG5_TMDS_CONTROL0_FEEDBACK 0x1deb
+-#define mmDIG5_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
+-#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x1dec
+-#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
+-#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x1ded
+-#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
+-#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x1dee
+-#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
+-#define mmDIG5_TMDS_CTL_BITS 0x1df0
+-#define mmDIG5_TMDS_CTL_BITS_BASE_IDX 2
+-#define mmDIG5_TMDS_DCBALANCER_CONTROL 0x1df1
+-#define mmDIG5_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
+-#define mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x1df3
+-#define mmDIG5_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
+-#define mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x1df4
+-#define mmDIG5_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
+-#define mmDIG5_DIG_VERSION 0x1df6
+-#define mmDIG5_DIG_VERSION_BASE_IDX 2
+-#define mmDIG5_DIG_LANE_ENABLE 0x1df7
+-#define mmDIG5_DIG_LANE_ENABLE_BASE_IDX 2
+-#define mmDIG5_AFMT_CNTL 0x1dfc
+-#define mmDIG5_AFMT_CNTL_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dp5_dispdec
+-// base address: 0x1400
+-#define mmDP5_DP_LINK_CNTL 0x1e1e
+-#define mmDP5_DP_LINK_CNTL_BASE_IDX 2
+-#define mmDP5_DP_PIXEL_FORMAT 0x1e1f
+-#define mmDP5_DP_PIXEL_FORMAT_BASE_IDX 2
+-#define mmDP5_DP_MSA_COLORIMETRY 0x1e20
+-#define mmDP5_DP_MSA_COLORIMETRY_BASE_IDX 2
+-#define mmDP5_DP_CONFIG 0x1e21
+-#define mmDP5_DP_CONFIG_BASE_IDX 2
+-#define mmDP5_DP_VID_STREAM_CNTL 0x1e22
+-#define mmDP5_DP_VID_STREAM_CNTL_BASE_IDX 2
+-#define mmDP5_DP_STEER_FIFO 0x1e23
+-#define mmDP5_DP_STEER_FIFO_BASE_IDX 2
+-#define mmDP5_DP_MSA_MISC 0x1e24
+-#define mmDP5_DP_MSA_MISC_BASE_IDX 2
+-#define mmDP5_DP_VID_TIMING 0x1e26
+-#define mmDP5_DP_VID_TIMING_BASE_IDX 2
+-#define mmDP5_DP_VID_N 0x1e27
+-#define mmDP5_DP_VID_N_BASE_IDX 2
+-#define mmDP5_DP_VID_M 0x1e28
+-#define mmDP5_DP_VID_M_BASE_IDX 2
+-#define mmDP5_DP_LINK_FRAMING_CNTL 0x1e29
+-#define mmDP5_DP_LINK_FRAMING_CNTL_BASE_IDX 2
+-#define mmDP5_DP_HBR2_EYE_PATTERN 0x1e2a
+-#define mmDP5_DP_HBR2_EYE_PATTERN_BASE_IDX 2
+-#define mmDP5_DP_VID_MSA_VBID 0x1e2b
+-#define mmDP5_DP_VID_MSA_VBID_BASE_IDX 2
+-#define mmDP5_DP_VID_INTERRUPT_CNTL 0x1e2c
+-#define mmDP5_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
+-#define mmDP5_DP_DPHY_CNTL 0x1e2d
+-#define mmDP5_DP_DPHY_CNTL_BASE_IDX 2
+-#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x1e2e
+-#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
+-#define mmDP5_DP_DPHY_SYM0 0x1e2f
+-#define mmDP5_DP_DPHY_SYM0_BASE_IDX 2
+-#define mmDP5_DP_DPHY_SYM1 0x1e30
+-#define mmDP5_DP_DPHY_SYM1_BASE_IDX 2
+-#define mmDP5_DP_DPHY_SYM2 0x1e31
+-#define mmDP5_DP_DPHY_SYM2_BASE_IDX 2
+-#define mmDP5_DP_DPHY_8B10B_CNTL 0x1e32
+-#define mmDP5_DP_DPHY_8B10B_CNTL_BASE_IDX 2
+-#define mmDP5_DP_DPHY_PRBS_CNTL 0x1e33
+-#define mmDP5_DP_DPHY_PRBS_CNTL_BASE_IDX 2
+-#define mmDP5_DP_DPHY_SCRAM_CNTL 0x1e34
+-#define mmDP5_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
+-#define mmDP5_DP_DPHY_CRC_EN 0x1e35
+-#define mmDP5_DP_DPHY_CRC_EN_BASE_IDX 2
+-#define mmDP5_DP_DPHY_CRC_CNTL 0x1e36
+-#define mmDP5_DP_DPHY_CRC_CNTL_BASE_IDX 2
+-#define mmDP5_DP_DPHY_CRC_RESULT 0x1e37
+-#define mmDP5_DP_DPHY_CRC_RESULT_BASE_IDX 2
+-#define mmDP5_DP_DPHY_CRC_MST_CNTL 0x1e38
+-#define mmDP5_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
+-#define mmDP5_DP_DPHY_CRC_MST_STATUS 0x1e39
+-#define mmDP5_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
+-#define mmDP5_DP_DPHY_FAST_TRAINING 0x1e3a
+-#define mmDP5_DP_DPHY_FAST_TRAINING_BASE_IDX 2
+-#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x1e3b
+-#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
+-#define mmDP5_DP_MSA_V_TIMING_OVERRIDE1 0x1e3c
+-#define mmDP5_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2
+-#define mmDP5_DP_MSA_V_TIMING_OVERRIDE2 0x1e3d
+-#define mmDP5_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2
+-#define mmDP5_DP_SEC_CNTL 0x1e41
+-#define mmDP5_DP_SEC_CNTL_BASE_IDX 2
+-#define mmDP5_DP_SEC_CNTL1 0x1e42
+-#define mmDP5_DP_SEC_CNTL1_BASE_IDX 2
+-#define mmDP5_DP_SEC_FRAMING1 0x1e43
+-#define mmDP5_DP_SEC_FRAMING1_BASE_IDX 2
+-#define mmDP5_DP_SEC_FRAMING2 0x1e44
+-#define mmDP5_DP_SEC_FRAMING2_BASE_IDX 2
+-#define mmDP5_DP_SEC_FRAMING3 0x1e45
+-#define mmDP5_DP_SEC_FRAMING3_BASE_IDX 2
+-#define mmDP5_DP_SEC_FRAMING4 0x1e46
+-#define mmDP5_DP_SEC_FRAMING4_BASE_IDX 2
+-#define mmDP5_DP_SEC_AUD_N 0x1e47
+-#define mmDP5_DP_SEC_AUD_N_BASE_IDX 2
+-#define mmDP5_DP_SEC_AUD_N_READBACK 0x1e48
+-#define mmDP5_DP_SEC_AUD_N_READBACK_BASE_IDX 2
+-#define mmDP5_DP_SEC_AUD_M 0x1e49
+-#define mmDP5_DP_SEC_AUD_M_BASE_IDX 2
+-#define mmDP5_DP_SEC_AUD_M_READBACK 0x1e4a
+-#define mmDP5_DP_SEC_AUD_M_READBACK_BASE_IDX 2
+-#define mmDP5_DP_SEC_TIMESTAMP 0x1e4b
+-#define mmDP5_DP_SEC_TIMESTAMP_BASE_IDX 2
+-#define mmDP5_DP_SEC_PACKET_CNTL 0x1e4c
+-#define mmDP5_DP_SEC_PACKET_CNTL_BASE_IDX 2
+-#define mmDP5_DP_MSE_RATE_CNTL 0x1e4d
+-#define mmDP5_DP_MSE_RATE_CNTL_BASE_IDX 2
+-#define mmDP5_DP_MSE_RATE_UPDATE 0x1e4f
+-#define mmDP5_DP_MSE_RATE_UPDATE_BASE_IDX 2
+-#define mmDP5_DP_MSE_SAT0 0x1e50
+-#define mmDP5_DP_MSE_SAT0_BASE_IDX 2
+-#define mmDP5_DP_MSE_SAT1 0x1e51
+-#define mmDP5_DP_MSE_SAT1_BASE_IDX 2
+-#define mmDP5_DP_MSE_SAT2 0x1e52
+-#define mmDP5_DP_MSE_SAT2_BASE_IDX 2
+-#define mmDP5_DP_MSE_SAT_UPDATE 0x1e53
+-#define mmDP5_DP_MSE_SAT_UPDATE_BASE_IDX 2
+-#define mmDP5_DP_MSE_LINK_TIMING 0x1e54
+-#define mmDP5_DP_MSE_LINK_TIMING_BASE_IDX 2
+-#define mmDP5_DP_MSE_MISC_CNTL 0x1e55
+-#define mmDP5_DP_MSE_MISC_CNTL_BASE_IDX 2
+-#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x1e5a
+-#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
+-#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL 0x1e5b
+-#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
+-#define mmDP5_DP_MSE_SAT0_STATUS 0x1e5d
+-#define mmDP5_DP_MSE_SAT0_STATUS_BASE_IDX 2
+-#define mmDP5_DP_MSE_SAT1_STATUS 0x1e5e
+-#define mmDP5_DP_MSE_SAT1_STATUS_BASE_IDX 2
+-#define mmDP5_DP_MSE_SAT2_STATUS 0x1e5f
+-#define mmDP5_DP_MSE_SAT2_STATUS_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dig6_dispdec
+-// base address: 0x1800
+-#define mmDIG6_DIG_FE_CNTL 0x1e7e
+-#define mmDIG6_DIG_FE_CNTL_BASE_IDX 2
+-#define mmDIG6_DIG_OUTPUT_CRC_CNTL 0x1e7f
+-#define mmDIG6_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
+-#define mmDIG6_DIG_OUTPUT_CRC_RESULT 0x1e80
+-#define mmDIG6_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
+-#define mmDIG6_DIG_CLOCK_PATTERN 0x1e81
+-#define mmDIG6_DIG_CLOCK_PATTERN_BASE_IDX 2
+-#define mmDIG6_DIG_TEST_PATTERN 0x1e82
+-#define mmDIG6_DIG_TEST_PATTERN_BASE_IDX 2
+-#define mmDIG6_DIG_RANDOM_PATTERN_SEED 0x1e83
+-#define mmDIG6_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
+-#define mmDIG6_DIG_FIFO_STATUS 0x1e84
+-#define mmDIG6_DIG_FIFO_STATUS_BASE_IDX 2
+-#define mmDIG6_HDMI_CONTROL 0x1e87
+-#define mmDIG6_HDMI_CONTROL_BASE_IDX 2
+-#define mmDIG6_HDMI_STATUS 0x1e88
+-#define mmDIG6_HDMI_STATUS_BASE_IDX 2
+-#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL 0x1e89
+-#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
+-#define mmDIG6_HDMI_ACR_PACKET_CONTROL 0x1e8a
+-#define mmDIG6_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
+-#define mmDIG6_HDMI_VBI_PACKET_CONTROL 0x1e8b
+-#define mmDIG6_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
+-#define mmDIG6_HDMI_INFOFRAME_CONTROL0 0x1e8c
+-#define mmDIG6_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
+-#define mmDIG6_HDMI_INFOFRAME_CONTROL1 0x1e8d
+-#define mmDIG6_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
+-#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 0x1e8e
+-#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
+-#define mmDIG6_AFMT_INTERRUPT_STATUS 0x1e8f
+-#define mmDIG6_AFMT_INTERRUPT_STATUS_BASE_IDX 2
+-#define mmDIG6_HDMI_GC 0x1e91
+-#define mmDIG6_HDMI_GC_BASE_IDX 2
+-#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 0x1e92
+-#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
+-#define mmDIG6_AFMT_ISRC1_0 0x1e93
+-#define mmDIG6_AFMT_ISRC1_0_BASE_IDX 2
+-#define mmDIG6_AFMT_ISRC1_1 0x1e94
+-#define mmDIG6_AFMT_ISRC1_1_BASE_IDX 2
+-#define mmDIG6_AFMT_ISRC1_2 0x1e95
+-#define mmDIG6_AFMT_ISRC1_2_BASE_IDX 2
+-#define mmDIG6_AFMT_ISRC1_3 0x1e96
+-#define mmDIG6_AFMT_ISRC1_3_BASE_IDX 2
+-#define mmDIG6_AFMT_ISRC1_4 0x1e97
+-#define mmDIG6_AFMT_ISRC1_4_BASE_IDX 2
+-#define mmDIG6_AFMT_ISRC2_0 0x1e98
+-#define mmDIG6_AFMT_ISRC2_0_BASE_IDX 2
+-#define mmDIG6_AFMT_ISRC2_1 0x1e99
+-#define mmDIG6_AFMT_ISRC2_1_BASE_IDX 2
+-#define mmDIG6_AFMT_ISRC2_2 0x1e9a
+-#define mmDIG6_AFMT_ISRC2_2_BASE_IDX 2
+-#define mmDIG6_AFMT_ISRC2_3 0x1e9b
+-#define mmDIG6_AFMT_ISRC2_3_BASE_IDX 2
+-#define mmDIG6_AFMT_AVI_INFO0 0x1e9c
+-#define mmDIG6_AFMT_AVI_INFO0_BASE_IDX 2
+-#define mmDIG6_AFMT_AVI_INFO1 0x1e9d
+-#define mmDIG6_AFMT_AVI_INFO1_BASE_IDX 2
+-#define mmDIG6_AFMT_AVI_INFO2 0x1e9e
+-#define mmDIG6_AFMT_AVI_INFO2_BASE_IDX 2
+-#define mmDIG6_AFMT_AVI_INFO3 0x1e9f
+-#define mmDIG6_AFMT_AVI_INFO3_BASE_IDX 2
+-#define mmDIG6_AFMT_MPEG_INFO0 0x1ea0
+-#define mmDIG6_AFMT_MPEG_INFO0_BASE_IDX 2
+-#define mmDIG6_AFMT_MPEG_INFO1 0x1ea1
+-#define mmDIG6_AFMT_MPEG_INFO1_BASE_IDX 2
+-#define mmDIG6_AFMT_GENERIC_HDR 0x1ea2
+-#define mmDIG6_AFMT_GENERIC_HDR_BASE_IDX 2
+-#define mmDIG6_AFMT_GENERIC_0 0x1ea3
+-#define mmDIG6_AFMT_GENERIC_0_BASE_IDX 2
+-#define mmDIG6_AFMT_GENERIC_1 0x1ea4
+-#define mmDIG6_AFMT_GENERIC_1_BASE_IDX 2
+-#define mmDIG6_AFMT_GENERIC_2 0x1ea5
+-#define mmDIG6_AFMT_GENERIC_2_BASE_IDX 2
+-#define mmDIG6_AFMT_GENERIC_3 0x1ea6
+-#define mmDIG6_AFMT_GENERIC_3_BASE_IDX 2
+-#define mmDIG6_AFMT_GENERIC_4 0x1ea7
+-#define mmDIG6_AFMT_GENERIC_4_BASE_IDX 2
+-#define mmDIG6_AFMT_GENERIC_5 0x1ea8
+-#define mmDIG6_AFMT_GENERIC_5_BASE_IDX 2
+-#define mmDIG6_AFMT_GENERIC_6 0x1ea9
+-#define mmDIG6_AFMT_GENERIC_6_BASE_IDX 2
+-#define mmDIG6_AFMT_GENERIC_7 0x1eaa
+-#define mmDIG6_AFMT_GENERIC_7_BASE_IDX 2
+-#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 0x1eab
+-#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
+-#define mmDIG6_HDMI_ACR_32_0 0x1eac
+-#define mmDIG6_HDMI_ACR_32_0_BASE_IDX 2
+-#define mmDIG6_HDMI_ACR_32_1 0x1ead
+-#define mmDIG6_HDMI_ACR_32_1_BASE_IDX 2
+-#define mmDIG6_HDMI_ACR_44_0 0x1eae
+-#define mmDIG6_HDMI_ACR_44_0_BASE_IDX 2
+-#define mmDIG6_HDMI_ACR_44_1 0x1eaf
+-#define mmDIG6_HDMI_ACR_44_1_BASE_IDX 2
+-#define mmDIG6_HDMI_ACR_48_0 0x1eb0
+-#define mmDIG6_HDMI_ACR_48_0_BASE_IDX 2
+-#define mmDIG6_HDMI_ACR_48_1 0x1eb1
+-#define mmDIG6_HDMI_ACR_48_1_BASE_IDX 2
+-#define mmDIG6_HDMI_ACR_STATUS_0 0x1eb2
+-#define mmDIG6_HDMI_ACR_STATUS_0_BASE_IDX 2
+-#define mmDIG6_HDMI_ACR_STATUS_1 0x1eb3
+-#define mmDIG6_HDMI_ACR_STATUS_1_BASE_IDX 2
+-#define mmDIG6_AFMT_AUDIO_INFO0 0x1eb4
+-#define mmDIG6_AFMT_AUDIO_INFO0_BASE_IDX 2
+-#define mmDIG6_AFMT_AUDIO_INFO1 0x1eb5
+-#define mmDIG6_AFMT_AUDIO_INFO1_BASE_IDX 2
+-#define mmDIG6_AFMT_60958_0 0x1eb6
+-#define mmDIG6_AFMT_60958_0_BASE_IDX 2
+-#define mmDIG6_AFMT_60958_1 0x1eb7
+-#define mmDIG6_AFMT_60958_1_BASE_IDX 2
+-#define mmDIG6_AFMT_AUDIO_CRC_CONTROL 0x1eb8
+-#define mmDIG6_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
+-#define mmDIG6_AFMT_RAMP_CONTROL0 0x1eb9
+-#define mmDIG6_AFMT_RAMP_CONTROL0_BASE_IDX 2
+-#define mmDIG6_AFMT_RAMP_CONTROL1 0x1eba
+-#define mmDIG6_AFMT_RAMP_CONTROL1_BASE_IDX 2
+-#define mmDIG6_AFMT_RAMP_CONTROL2 0x1ebb
+-#define mmDIG6_AFMT_RAMP_CONTROL2_BASE_IDX 2
+-#define mmDIG6_AFMT_RAMP_CONTROL3 0x1ebc
+-#define mmDIG6_AFMT_RAMP_CONTROL3_BASE_IDX 2
+-#define mmDIG6_AFMT_60958_2 0x1ebd
+-#define mmDIG6_AFMT_60958_2_BASE_IDX 2
+-#define mmDIG6_AFMT_AUDIO_CRC_RESULT 0x1ebe
+-#define mmDIG6_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
+-#define mmDIG6_AFMT_STATUS 0x1ebf
+-#define mmDIG6_AFMT_STATUS_BASE_IDX 2
+-#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL 0x1ec0
+-#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
+-#define mmDIG6_AFMT_VBI_PACKET_CONTROL 0x1ec1
+-#define mmDIG6_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
+-#define mmDIG6_AFMT_INFOFRAME_CONTROL0 0x1ec2
+-#define mmDIG6_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
+-#define mmDIG6_AFMT_AUDIO_SRC_CONTROL 0x1ec3
+-#define mmDIG6_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
+-#define mmDIG6_DIG_BE_CNTL 0x1ec5
+-#define mmDIG6_DIG_BE_CNTL_BASE_IDX 2
+-#define mmDIG6_DIG_BE_EN_CNTL 0x1ec6
+-#define mmDIG6_DIG_BE_EN_CNTL_BASE_IDX 2
+-#define mmDIG6_TMDS_CNTL 0x1ee9
+-#define mmDIG6_TMDS_CNTL_BASE_IDX 2
+-#define mmDIG6_TMDS_CONTROL_CHAR 0x1eea
+-#define mmDIG6_TMDS_CONTROL_CHAR_BASE_IDX 2
+-#define mmDIG6_TMDS_CONTROL0_FEEDBACK 0x1eeb
+-#define mmDIG6_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
+-#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL 0x1eec
+-#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
+-#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 0x1eed
+-#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
+-#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 0x1eee
+-#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
+-#define mmDIG6_TMDS_CTL_BITS 0x1ef0
+-#define mmDIG6_TMDS_CTL_BITS_BASE_IDX 2
+-#define mmDIG6_TMDS_DCBALANCER_CONTROL 0x1ef1
+-#define mmDIG6_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
+-#define mmDIG6_TMDS_CTL0_1_GEN_CNTL 0x1ef3
+-#define mmDIG6_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
+-#define mmDIG6_TMDS_CTL2_3_GEN_CNTL 0x1ef4
+-#define mmDIG6_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
+-#define mmDIG6_DIG_VERSION 0x1ef6
+-#define mmDIG6_DIG_VERSION_BASE_IDX 2
+-#define mmDIG6_DIG_LANE_ENABLE 0x1ef7
+-#define mmDIG6_DIG_LANE_ENABLE_BASE_IDX 2
+-#define mmDIG6_AFMT_CNTL 0x1efc
+-#define mmDIG6_AFMT_CNTL_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dp6_dispdec
+-// base address: 0x1800
+-#define mmDP6_DP_LINK_CNTL 0x1f1e
+-#define mmDP6_DP_LINK_CNTL_BASE_IDX 2
+-#define mmDP6_DP_PIXEL_FORMAT 0x1f1f
+-#define mmDP6_DP_PIXEL_FORMAT_BASE_IDX 2
+-#define mmDP6_DP_MSA_COLORIMETRY 0x1f20
+-#define mmDP6_DP_MSA_COLORIMETRY_BASE_IDX 2
+-#define mmDP6_DP_CONFIG 0x1f21
+-#define mmDP6_DP_CONFIG_BASE_IDX 2
+-#define mmDP6_DP_VID_STREAM_CNTL 0x1f22
+-#define mmDP6_DP_VID_STREAM_CNTL_BASE_IDX 2
+-#define mmDP6_DP_STEER_FIFO 0x1f23
+-#define mmDP6_DP_STEER_FIFO_BASE_IDX 2
+-#define mmDP6_DP_MSA_MISC 0x1f24
+-#define mmDP6_DP_MSA_MISC_BASE_IDX 2
+-#define mmDP6_DP_VID_TIMING 0x1f26
+-#define mmDP6_DP_VID_TIMING_BASE_IDX 2
+-#define mmDP6_DP_VID_N 0x1f27
+-#define mmDP6_DP_VID_N_BASE_IDX 2
+-#define mmDP6_DP_VID_M 0x1f28
+-#define mmDP6_DP_VID_M_BASE_IDX 2
+-#define mmDP6_DP_LINK_FRAMING_CNTL 0x1f29
+-#define mmDP6_DP_LINK_FRAMING_CNTL_BASE_IDX 2
+-#define mmDP6_DP_HBR2_EYE_PATTERN 0x1f2a
+-#define mmDP6_DP_HBR2_EYE_PATTERN_BASE_IDX 2
+-#define mmDP6_DP_VID_MSA_VBID 0x1f2b
+-#define mmDP6_DP_VID_MSA_VBID_BASE_IDX 2
+-#define mmDP6_DP_VID_INTERRUPT_CNTL 0x1f2c
+-#define mmDP6_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
+-#define mmDP6_DP_DPHY_CNTL 0x1f2d
+-#define mmDP6_DP_DPHY_CNTL_BASE_IDX 2
+-#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL 0x1f2e
+-#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
+-#define mmDP6_DP_DPHY_SYM0 0x1f2f
+-#define mmDP6_DP_DPHY_SYM0_BASE_IDX 2
+-#define mmDP6_DP_DPHY_SYM1 0x1f30
+-#define mmDP6_DP_DPHY_SYM1_BASE_IDX 2
+-#define mmDP6_DP_DPHY_SYM2 0x1f31
+-#define mmDP6_DP_DPHY_SYM2_BASE_IDX 2
+-#define mmDP6_DP_DPHY_8B10B_CNTL 0x1f32
+-#define mmDP6_DP_DPHY_8B10B_CNTL_BASE_IDX 2
+-#define mmDP6_DP_DPHY_PRBS_CNTL 0x1f33
+-#define mmDP6_DP_DPHY_PRBS_CNTL_BASE_IDX 2
+-#define mmDP6_DP_DPHY_SCRAM_CNTL 0x1f34
+-#define mmDP6_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
+-#define mmDP6_DP_DPHY_CRC_EN 0x1f35
+-#define mmDP6_DP_DPHY_CRC_EN_BASE_IDX 2
+-#define mmDP6_DP_DPHY_CRC_CNTL 0x1f36
+-#define mmDP6_DP_DPHY_CRC_CNTL_BASE_IDX 2
+-#define mmDP6_DP_DPHY_CRC_RESULT 0x1f37
+-#define mmDP6_DP_DPHY_CRC_RESULT_BASE_IDX 2
+-#define mmDP6_DP_DPHY_CRC_MST_CNTL 0x1f38
+-#define mmDP6_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
+-#define mmDP6_DP_DPHY_CRC_MST_STATUS 0x1f39
+-#define mmDP6_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
+-#define mmDP6_DP_DPHY_FAST_TRAINING 0x1f3a
+-#define mmDP6_DP_DPHY_FAST_TRAINING_BASE_IDX 2
+-#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS 0x1f3b
+-#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
+-#define mmDP6_DP_MSA_V_TIMING_OVERRIDE1 0x1f3c
+-#define mmDP6_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2
+-#define mmDP6_DP_MSA_V_TIMING_OVERRIDE2 0x1f3d
+-#define mmDP6_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2
+-#define mmDP6_DP_SEC_CNTL 0x1f41
+-#define mmDP6_DP_SEC_CNTL_BASE_IDX 2
+-#define mmDP6_DP_SEC_CNTL1 0x1f42
+-#define mmDP6_DP_SEC_CNTL1_BASE_IDX 2
+-#define mmDP6_DP_SEC_FRAMING1 0x1f43
+-#define mmDP6_DP_SEC_FRAMING1_BASE_IDX 2
+-#define mmDP6_DP_SEC_FRAMING2 0x1f44
+-#define mmDP6_DP_SEC_FRAMING2_BASE_IDX 2
+-#define mmDP6_DP_SEC_FRAMING3 0x1f45
+-#define mmDP6_DP_SEC_FRAMING3_BASE_IDX 2
+-#define mmDP6_DP_SEC_FRAMING4 0x1f46
+-#define mmDP6_DP_SEC_FRAMING4_BASE_IDX 2
+-#define mmDP6_DP_SEC_AUD_N 0x1f47
+-#define mmDP6_DP_SEC_AUD_N_BASE_IDX 2
+-#define mmDP6_DP_SEC_AUD_N_READBACK 0x1f48
+-#define mmDP6_DP_SEC_AUD_N_READBACK_BASE_IDX 2
+-#define mmDP6_DP_SEC_AUD_M 0x1f49
+-#define mmDP6_DP_SEC_AUD_M_BASE_IDX 2
+-#define mmDP6_DP_SEC_AUD_M_READBACK 0x1f4a
+-#define mmDP6_DP_SEC_AUD_M_READBACK_BASE_IDX 2
+-#define mmDP6_DP_SEC_TIMESTAMP 0x1f4b
+-#define mmDP6_DP_SEC_TIMESTAMP_BASE_IDX 2
+-#define mmDP6_DP_SEC_PACKET_CNTL 0x1f4c
+-#define mmDP6_DP_SEC_PACKET_CNTL_BASE_IDX 2
+-#define mmDP6_DP_MSE_RATE_CNTL 0x1f4d
+-#define mmDP6_DP_MSE_RATE_CNTL_BASE_IDX 2
+-#define mmDP6_DP_MSE_RATE_UPDATE 0x1f4f
+-#define mmDP6_DP_MSE_RATE_UPDATE_BASE_IDX 2
+-#define mmDP6_DP_MSE_SAT0 0x1f50
+-#define mmDP6_DP_MSE_SAT0_BASE_IDX 2
+-#define mmDP6_DP_MSE_SAT1 0x1f51
+-#define mmDP6_DP_MSE_SAT1_BASE_IDX 2
+-#define mmDP6_DP_MSE_SAT2 0x1f52
+-#define mmDP6_DP_MSE_SAT2_BASE_IDX 2
+-#define mmDP6_DP_MSE_SAT_UPDATE 0x1f53
+-#define mmDP6_DP_MSE_SAT_UPDATE_BASE_IDX 2
+-#define mmDP6_DP_MSE_LINK_TIMING 0x1f54
+-#define mmDP6_DP_MSE_LINK_TIMING_BASE_IDX 2
+-#define mmDP6_DP_MSE_MISC_CNTL 0x1f55
+-#define mmDP6_DP_MSE_MISC_CNTL_BASE_IDX 2
+-#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x1f5a
+-#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
+-#define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL 0x1f5b
+-#define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
+-#define mmDP6_DP_MSE_SAT0_STATUS 0x1f5d
+-#define mmDP6_DP_MSE_SAT0_STATUS_BASE_IDX 2
+-#define mmDP6_DP_MSE_SAT1_STATUS 0x1f5e
+-#define mmDP6_DP_MSE_SAT1_STATUS_BASE_IDX 2
+-#define mmDP6_DP_MSE_SAT2_STATUS 0x1f5f
+-#define mmDP6_DP_MSE_SAT2_STATUS_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dcio_uniphy0_dispdec
+-// base address: 0x0
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 0x213e
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 0x213f
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 0x2140
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 0x2141
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 0x2142
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 0x2143
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 0x2144
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 0x2145
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 0x2146
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 0x2147
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 0x2148
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 0x2149
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 0x214a
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 0x214b
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 0x214c
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 0x214d
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 0x214e
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 0x214f
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 0x2150
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 0x2151
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 0x2152
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 0x2153
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 0x2154
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 0x2155
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 0x2156
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 0x2157
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 0x2158
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 0x2159
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 0x215a
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 0x215b
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 0x215c
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 0x215d
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32 0x215e
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33 0x215f
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34 0x2160
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35 0x2161
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36 0x2162
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37 0x2163
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38 0x2164
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39 0x2165
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40 0x2166
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41 0x2167
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42 0x2168
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43 0x2169
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44 0x216a
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45 0x216b
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46 0x216c
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47 0x216d
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48 0x216e
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49 0x216f
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50 0x2170
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51 0x2171
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52 0x2172
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53 0x2173
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54 0x2174
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55 0x2175
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56 0x2176
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57 0x2177
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58 0x2178
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59 0x2179
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60 0x217a
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61 0x217b
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62 0x217c
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63 0x217d
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64 0x217e
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65 0x217f
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66 0x2180
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67 0x2181
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68 0x2182
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69 0x2183
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70 0x2184
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71 0x2185
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72 0x2186
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73 0x2187
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74 0x2188
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75 0x2189
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76 0x218a
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77 0x218b
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78 0x218c
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79 0x218d
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80 0x218e
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81 0x218f
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82 0x2190
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83 0x2191
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84 0x2192
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85 0x2193
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86 0x2194
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87 0x2195
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88 0x2196
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89 0x2197
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90 0x2198
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91 0x2199
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92 0x219a
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93 0x219b
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94 0x219c
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95 0x219d
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96 0x219e
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97 0x219f
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98 0x21a0
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99 0x21a1
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100 0x21a2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101 0x21a3
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102 0x21a4
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103 0x21a5
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104 0x21a6
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105 0x21a7
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106 0x21a8
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107 0x21a9
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108 0x21aa
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109 0x21ab
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110 0x21ac
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111 0x21ad
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112 0x21ae
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113 0x21af
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114 0x21b0
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115 0x21b1
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116 0x21b2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117 0x21b3
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118 0x21b4
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119 0x21b5
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120 0x21b6
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121 0x21b7
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122 0x21b8
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123 0x21b9
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124 0x21ba
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125 0x21bb
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126 0x21bc
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127 0x21bd
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128 0x21be
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129 0x21bf
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130 0x21c0
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131 0x21c1
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132 0x21c2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133 0x21c3
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134 0x21c4
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135 0x21c5
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136 0x21c6
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137 0x21c7
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138 0x21c8
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139 0x21c9
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140 0x21ca
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141 0x21cb
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142 0x21cc
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143 0x21cd
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144 0x21ce
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145 0x21cf
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146 0x21d0
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147 0x21d1
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148 0x21d2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149 0x21d3
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150 0x21d4
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151 0x21d5
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152 0x21d6
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153 0x21d7
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154 0x21d8
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155 0x21d9
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156 0x21da
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157 0x21db
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158 0x21dc
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159 0x21dd
+-#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dc_combophycmregs0_dispdec
+-// base address: 0x0
+-#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE1 0x213e
+-#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE1_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE2 0x213f
+-#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE2_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE3 0x2140
+-#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE3_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM 0x2141
+-#define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT 0x2142
+-#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL 0x2143
+-#define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS0_COMMON_TMDP 0x2144
+-#define mmDC_COMBOPHYCMREGS0_COMMON_TMDP_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS 0x2145
+-#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL 0x2146
+-#define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1 0x2147
+-#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2 0x2148
+-#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3 0x2149
+-#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4 0x214a
+-#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5 0x214b
+-#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6 0x214c
+-#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7 0x214d
+-#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dc_combophytxregs0_dispdec
+-// base address: 0x0
+-#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0 0x215e
+-#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0 0x215f
+-#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2160
+-#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0 0x2161
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0 0x2162
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0 0x2163
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0 0x2164
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0 0x2165
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0 0x2166
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0 0x2167
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0 0x2168
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0 0x2169
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0 0x216a
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0 0x216b
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0 0x216c
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0 0x216d
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1 0x216e
+-#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1 0x216f
+-#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2170
+-#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1 0x2171
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1 0x2172
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1 0x2173
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1 0x2174
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1 0x2175
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1 0x2176
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1 0x2177
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1 0x2178
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1 0x2179
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1 0x217a
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1 0x217b
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1 0x217c
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1 0x217d
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2 0x217e
+-#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2 0x217f
+-#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2180
+-#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2 0x2181
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2 0x2182
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2 0x2183
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2 0x2184
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2 0x2185
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2 0x2186
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2 0x2187
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2 0x2188
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2 0x2189
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2 0x218a
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2 0x218b
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2 0x218c
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2 0x218d
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3 0x218e
+-#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3 0x218f
+-#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2190
+-#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3 0x2191
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3 0x2192
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3 0x2193
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3 0x2194
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3 0x2195
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3 0x2196
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3 0x2197
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3 0x2198
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3 0x2199
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3 0x219a
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3 0x219b
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3 0x219c
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3 0x219d
+-#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dc_combophypllregs0_dispdec
+-// base address: 0x0
+-#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0 0x219e
+-#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1 0x219f
+-#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2 0x21a0
+-#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3 0x21a1
+-#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE 0x21a2
+-#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE 0x21a3
+-#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS0_CAL_CTRL 0x21a4
+-#define mmDC_COMBOPHYPLLREGS0_CAL_CTRL_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL 0x21a5
+-#define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS0_VREG_CFG 0x21a7
+-#define mmDC_COMBOPHYPLLREGS0_VREG_CFG_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS0_OBSERVE0 0x21a8
+-#define mmDC_COMBOPHYPLLREGS0_OBSERVE0_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS0_OBSERVE1 0x21a9
+-#define mmDC_COMBOPHYPLLREGS0_OBSERVE1_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS0_DFT_OUT 0x21aa
+-#define mmDC_COMBOPHYPLLREGS0_DFT_OUT_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dcio_uniphy1_dispdec
+-// base address: 0x320
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x2206
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x2207
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x2208
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x2209
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x220a
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x220b
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x220c
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x220d
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x220e
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x220f
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x2210
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x2211
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x2212
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x2213
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x2214
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x2215
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x2216
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x2217
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x2218
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x2219
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x221a
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x221b
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x221c
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x221d
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x221e
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x221f
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x2220
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x2221
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x2222
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x2223
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x2224
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x2225
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 0x2226
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 0x2227
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 0x2228
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 0x2229
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 0x222a
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 0x222b
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 0x222c
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 0x222d
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 0x222e
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 0x222f
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 0x2230
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 0x2231
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 0x2232
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 0x2233
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 0x2234
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 0x2235
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 0x2236
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 0x2237
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 0x2238
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 0x2239
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 0x223a
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 0x223b
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 0x223c
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 0x223d
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 0x223e
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 0x223f
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58 0x2240
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59 0x2241
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60 0x2242
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61 0x2243
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62 0x2244
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63 0x2245
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64 0x2246
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65 0x2247
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66 0x2248
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67 0x2249
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68 0x224a
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69 0x224b
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70 0x224c
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71 0x224d
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72 0x224e
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73 0x224f
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74 0x2250
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75 0x2251
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76 0x2252
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77 0x2253
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78 0x2254
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79 0x2255
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80 0x2256
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81 0x2257
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82 0x2258
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83 0x2259
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84 0x225a
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85 0x225b
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86 0x225c
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87 0x225d
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88 0x225e
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89 0x225f
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90 0x2260
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91 0x2261
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92 0x2262
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93 0x2263
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94 0x2264
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95 0x2265
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96 0x2266
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97 0x2267
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98 0x2268
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99 0x2269
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100 0x226a
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101 0x226b
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102 0x226c
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103 0x226d
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104 0x226e
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105 0x226f
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106 0x2270
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107 0x2271
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108 0x2272
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109 0x2273
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110 0x2274
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111 0x2275
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112 0x2276
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113 0x2277
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114 0x2278
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115 0x2279
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116 0x227a
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117 0x227b
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118 0x227c
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119 0x227d
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120 0x227e
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121 0x227f
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122 0x2280
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123 0x2281
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124 0x2282
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125 0x2283
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126 0x2284
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127 0x2285
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128 0x2286
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129 0x2287
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130 0x2288
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131 0x2289
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132 0x228a
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133 0x228b
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134 0x228c
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135 0x228d
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136 0x228e
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137 0x228f
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138 0x2290
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139 0x2291
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140 0x2292
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141 0x2293
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142 0x2294
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143 0x2295
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144 0x2296
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145 0x2297
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146 0x2298
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147 0x2299
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148 0x229a
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149 0x229b
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150 0x229c
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151 0x229d
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152 0x229e
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153 0x229f
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154 0x22a0
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155 0x22a1
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156 0x22a2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157 0x22a3
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158 0x22a4
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159 0x22a5
+-#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dc_combophycmregs1_dispdec
+-// base address: 0x320
+-#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE1 0x2206
+-#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE1_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE2 0x2207
+-#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE2_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE3 0x2208
+-#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE3_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM 0x2209
+-#define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT 0x220a
+-#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL 0x220b
+-#define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS1_COMMON_TMDP 0x220c
+-#define mmDC_COMBOPHYCMREGS1_COMMON_TMDP_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS 0x220d
+-#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL 0x220e
+-#define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1 0x220f
+-#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2 0x2210
+-#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3 0x2211
+-#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4 0x2212
+-#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5 0x2213
+-#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6 0x2214
+-#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7 0x2215
+-#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dc_combophytxregs1_dispdec
+-// base address: 0x320
+-#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0 0x2226
+-#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0 0x2227
+-#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2228
+-#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0 0x2229
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0 0x222a
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0 0x222b
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0 0x222c
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0 0x222d
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0 0x222e
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0 0x222f
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0 0x2230
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0 0x2231
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0 0x2232
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0 0x2233
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0 0x2234
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0 0x2235
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1 0x2236
+-#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1 0x2237
+-#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2238
+-#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1 0x2239
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1 0x223a
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1 0x223b
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1 0x223c
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1 0x223d
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1 0x223e
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1 0x223f
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1 0x2240
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1 0x2241
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1 0x2242
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1 0x2243
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1 0x2244
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1 0x2245
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2 0x2246
+-#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2 0x2247
+-#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2248
+-#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2 0x2249
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2 0x224a
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2 0x224b
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2 0x224c
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2 0x224d
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2 0x224e
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2 0x224f
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2 0x2250
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2 0x2251
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2 0x2252
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2 0x2253
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2 0x2254
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2 0x2255
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3 0x2256
+-#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3 0x2257
+-#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2258
+-#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3 0x2259
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3 0x225a
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3 0x225b
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3 0x225c
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3 0x225d
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3 0x225e
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3 0x225f
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3 0x2260
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3 0x2261
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3 0x2262
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3 0x2263
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3 0x2264
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3 0x2265
+-#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dc_combophypllregs1_dispdec
+-// base address: 0x320
+-#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0 0x2266
+-#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1 0x2267
+-#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2 0x2268
+-#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3 0x2269
+-#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE 0x226a
+-#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE 0x226b
+-#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS1_CAL_CTRL 0x226c
+-#define mmDC_COMBOPHYPLLREGS1_CAL_CTRL_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL 0x226d
+-#define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS1_VREG_CFG 0x226f
+-#define mmDC_COMBOPHYPLLREGS1_VREG_CFG_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS1_OBSERVE0 0x2270
+-#define mmDC_COMBOPHYPLLREGS1_OBSERVE0_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS1_OBSERVE1 0x2271
+-#define mmDC_COMBOPHYPLLREGS1_OBSERVE1_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS1_DFT_OUT 0x2272
+-#define mmDC_COMBOPHYPLLREGS1_DFT_OUT_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dcio_uniphy2_dispdec
+-// base address: 0x640
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x22ce
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x22cf
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x22d0
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x22d1
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x22d2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x22d3
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x22d4
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x22d5
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x22d6
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x22d7
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x22d8
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x22d9
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x22da
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x22db
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x22dc
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x22dd
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x22de
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x22df
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x22e0
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x22e1
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x22e2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x22e3
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x22e4
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x22e5
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x22e6
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x22e7
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x22e8
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x22e9
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x22ea
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x22eb
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x22ec
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x22ed
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 0x22ee
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 0x22ef
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 0x22f0
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 0x22f1
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 0x22f2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 0x22f3
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 0x22f4
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 0x22f5
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 0x22f6
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 0x22f7
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 0x22f8
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 0x22f9
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 0x22fa
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 0x22fb
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 0x22fc
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 0x22fd
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 0x22fe
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 0x22ff
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 0x2300
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 0x2301
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 0x2302
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 0x2303
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 0x2304
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 0x2305
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 0x2306
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 0x2307
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58 0x2308
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59 0x2309
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60 0x230a
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61 0x230b
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62 0x230c
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63 0x230d
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64 0x230e
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65 0x230f
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66 0x2310
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67 0x2311
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68 0x2312
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69 0x2313
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70 0x2314
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71 0x2315
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72 0x2316
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73 0x2317
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74 0x2318
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75 0x2319
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76 0x231a
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77 0x231b
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78 0x231c
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79 0x231d
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80 0x231e
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81 0x231f
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82 0x2320
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83 0x2321
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84 0x2322
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85 0x2323
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86 0x2324
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87 0x2325
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88 0x2326
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89 0x2327
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90 0x2328
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91 0x2329
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92 0x232a
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93 0x232b
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94 0x232c
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95 0x232d
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96 0x232e
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97 0x232f
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98 0x2330
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99 0x2331
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100 0x2332
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101 0x2333
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102 0x2334
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103 0x2335
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104 0x2336
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105 0x2337
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106 0x2338
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107 0x2339
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108 0x233a
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109 0x233b
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110 0x233c
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111 0x233d
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112 0x233e
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113 0x233f
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114 0x2340
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115 0x2341
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116 0x2342
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117 0x2343
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118 0x2344
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119 0x2345
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120 0x2346
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121 0x2347
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122 0x2348
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123 0x2349
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124 0x234a
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125 0x234b
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126 0x234c
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127 0x234d
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128 0x234e
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129 0x234f
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130 0x2350
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131 0x2351
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132 0x2352
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133 0x2353
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134 0x2354
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135 0x2355
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136 0x2356
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137 0x2357
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138 0x2358
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139 0x2359
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140 0x235a
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141 0x235b
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142 0x235c
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143 0x235d
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144 0x235e
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145 0x235f
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146 0x2360
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147 0x2361
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148 0x2362
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149 0x2363
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150 0x2364
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151 0x2365
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152 0x2366
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153 0x2367
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154 0x2368
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155 0x2369
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156 0x236a
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157 0x236b
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158 0x236c
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159 0x236d
+-#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dc_combophycmregs2_dispdec
+-// base address: 0x640
+-#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE1 0x22ce
+-#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE1_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE2 0x22cf
+-#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE2_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE3 0x22d0
+-#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE3_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM 0x22d1
+-#define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT 0x22d2
+-#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL 0x22d3
+-#define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS2_COMMON_TMDP 0x22d4
+-#define mmDC_COMBOPHYCMREGS2_COMMON_TMDP_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS 0x22d5
+-#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL 0x22d6
+-#define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1 0x22d7
+-#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2 0x22d8
+-#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3 0x22d9
+-#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4 0x22da
+-#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5 0x22db
+-#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6 0x22dc
+-#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7 0x22dd
+-#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dc_combophytxregs2_dispdec
+-// base address: 0x640
+-#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0 0x22ee
+-#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0 0x22ef
+-#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x22f0
+-#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0 0x22f1
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0 0x22f2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0 0x22f3
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0 0x22f4
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0 0x22f5
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0 0x22f6
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0 0x22f7
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0 0x22f8
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0 0x22f9
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0 0x22fa
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0 0x22fb
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0 0x22fc
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0 0x22fd
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1 0x22fe
+-#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1 0x22ff
+-#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2300
+-#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1 0x2301
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1 0x2302
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1 0x2303
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1 0x2304
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1 0x2305
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1 0x2306
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1 0x2307
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1 0x2308
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1 0x2309
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1 0x230a
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1 0x230b
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1 0x230c
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1 0x230d
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2 0x230e
+-#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2 0x230f
+-#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2310
+-#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2 0x2311
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2 0x2312
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2 0x2313
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2 0x2314
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2 0x2315
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2 0x2316
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2 0x2317
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2 0x2318
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2 0x2319
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2 0x231a
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2 0x231b
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2 0x231c
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2 0x231d
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3 0x231e
+-#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3 0x231f
+-#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2320
+-#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3 0x2321
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3 0x2322
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3 0x2323
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3 0x2324
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3 0x2325
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3 0x2326
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3 0x2327
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3 0x2328
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3 0x2329
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3 0x232a
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3 0x232b
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3 0x232c
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3 0x232d
+-#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dc_combophypllregs2_dispdec
+-// base address: 0x640
+-#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0 0x232e
+-#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1 0x232f
+-#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2 0x2330
+-#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3 0x2331
+-#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE 0x2332
+-#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE 0x2333
+-#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS2_CAL_CTRL 0x2334
+-#define mmDC_COMBOPHYPLLREGS2_CAL_CTRL_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL 0x2335
+-#define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS2_VREG_CFG 0x2337
+-#define mmDC_COMBOPHYPLLREGS2_VREG_CFG_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS2_OBSERVE0 0x2338
+-#define mmDC_COMBOPHYPLLREGS2_OBSERVE0_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS2_OBSERVE1 0x2339
+-#define mmDC_COMBOPHYPLLREGS2_OBSERVE1_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS2_DFT_OUT 0x233a
+-#define mmDC_COMBOPHYPLLREGS2_DFT_OUT_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dcio_uniphy3_dispdec
+-// base address: 0x960
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x2396
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x2397
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x2398
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x2399
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x239a
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x239b
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x239c
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x239d
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x239e
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x239f
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x23a0
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x23a1
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x23a2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x23a3
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x23a4
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x23a5
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x23a6
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x23a7
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x23a8
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x23a9
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x23aa
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x23ab
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x23ac
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x23ad
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x23ae
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x23af
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x23b0
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x23b1
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x23b2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x23b3
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x23b4
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x23b5
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 0x23b6
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 0x23b7
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 0x23b8
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 0x23b9
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 0x23ba
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 0x23bb
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 0x23bc
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 0x23bd
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 0x23be
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 0x23bf
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 0x23c0
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 0x23c1
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 0x23c2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 0x23c3
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 0x23c4
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 0x23c5
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 0x23c6
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 0x23c7
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 0x23c8
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 0x23c9
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 0x23ca
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 0x23cb
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 0x23cc
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 0x23cd
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 0x23ce
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 0x23cf
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58 0x23d0
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59 0x23d1
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60 0x23d2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61 0x23d3
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62 0x23d4
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63 0x23d5
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64 0x23d6
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65 0x23d7
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66 0x23d8
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67 0x23d9
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68 0x23da
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69 0x23db
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70 0x23dc
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71 0x23dd
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72 0x23de
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73 0x23df
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74 0x23e0
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75 0x23e1
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76 0x23e2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77 0x23e3
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78 0x23e4
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79 0x23e5
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80 0x23e6
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81 0x23e7
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82 0x23e8
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83 0x23e9
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84 0x23ea
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85 0x23eb
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86 0x23ec
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87 0x23ed
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88 0x23ee
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89 0x23ef
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90 0x23f0
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91 0x23f1
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92 0x23f2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93 0x23f3
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94 0x23f4
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95 0x23f5
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96 0x23f6
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97 0x23f7
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98 0x23f8
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99 0x23f9
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100 0x23fa
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101 0x23fb
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102 0x23fc
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103 0x23fd
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104 0x23fe
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105 0x23ff
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106 0x2400
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107 0x2401
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108 0x2402
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109 0x2403
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110 0x2404
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111 0x2405
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112 0x2406
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113 0x2407
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114 0x2408
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115 0x2409
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116 0x240a
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117 0x240b
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118 0x240c
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119 0x240d
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120 0x240e
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121 0x240f
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122 0x2410
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123 0x2411
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124 0x2412
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125 0x2413
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126 0x2414
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127 0x2415
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128 0x2416
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129 0x2417
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130 0x2418
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131 0x2419
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132 0x241a
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133 0x241b
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134 0x241c
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135 0x241d
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136 0x241e
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137 0x241f
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138 0x2420
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139 0x2421
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140 0x2422
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141 0x2423
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142 0x2424
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143 0x2425
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144 0x2426
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145 0x2427
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146 0x2428
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147 0x2429
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148 0x242a
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149 0x242b
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150 0x242c
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151 0x242d
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152 0x242e
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153 0x242f
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154 0x2430
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155 0x2431
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156 0x2432
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157 0x2433
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158 0x2434
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159 0x2435
+-#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dc_combophycmregs3_dispdec
+-// base address: 0x960
+-#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE1 0x2396
+-#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE1_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE2 0x2397
+-#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE2_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE3 0x2398
+-#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE3_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM 0x2399
+-#define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT 0x239a
+-#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL 0x239b
+-#define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS3_COMMON_TMDP 0x239c
+-#define mmDC_COMBOPHYCMREGS3_COMMON_TMDP_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS 0x239d
+-#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL 0x239e
+-#define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1 0x239f
+-#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2 0x23a0
+-#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3 0x23a1
+-#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4 0x23a2
+-#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5 0x23a3
+-#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6 0x23a4
+-#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7 0x23a5
+-#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dc_combophytxregs3_dispdec
+-// base address: 0x960
+-#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0 0x23b6
+-#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0 0x23b7
+-#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x23b8
+-#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0 0x23b9
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0 0x23ba
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0 0x23bb
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0 0x23bc
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0 0x23bd
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0 0x23be
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0 0x23bf
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0 0x23c0
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0 0x23c1
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0 0x23c2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0 0x23c3
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0 0x23c4
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0 0x23c5
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1 0x23c6
+-#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1 0x23c7
+-#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x23c8
+-#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1 0x23c9
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1 0x23ca
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1 0x23cb
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1 0x23cc
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1 0x23cd
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1 0x23ce
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1 0x23cf
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1 0x23d0
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1 0x23d1
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1 0x23d2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1 0x23d3
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1 0x23d4
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1 0x23d5
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2 0x23d6
+-#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2 0x23d7
+-#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x23d8
+-#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2 0x23d9
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2 0x23da
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2 0x23db
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2 0x23dc
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2 0x23dd
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2 0x23de
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2 0x23df
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2 0x23e0
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2 0x23e1
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2 0x23e2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2 0x23e3
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2 0x23e4
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2 0x23e5
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3 0x23e6
+-#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3 0x23e7
+-#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x23e8
+-#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3 0x23e9
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3 0x23ea
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3 0x23eb
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3 0x23ec
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3 0x23ed
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3 0x23ee
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3 0x23ef
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3 0x23f0
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3 0x23f1
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3 0x23f2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3 0x23f3
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3 0x23f4
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3 0x23f5
+-#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dc_combophypllregs3_dispdec
+-// base address: 0x960
+-#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0 0x23f6
+-#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1 0x23f7
+-#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2 0x23f8
+-#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3 0x23f9
+-#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE 0x23fa
+-#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE 0x23fb
+-#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS3_CAL_CTRL 0x23fc
+-#define mmDC_COMBOPHYPLLREGS3_CAL_CTRL_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL 0x23fd
+-#define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS3_VREG_CFG 0x23ff
+-#define mmDC_COMBOPHYPLLREGS3_VREG_CFG_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS3_OBSERVE0 0x2400
+-#define mmDC_COMBOPHYPLLREGS3_OBSERVE0_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS3_OBSERVE1 0x2401
+-#define mmDC_COMBOPHYPLLREGS3_OBSERVE1_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS3_DFT_OUT 0x2402
+-#define mmDC_COMBOPHYPLLREGS3_DFT_OUT_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dcio_uniphy4_dispdec
+-// base address: 0xc80
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0x245e
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0x245f
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0x2460
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0x2461
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0x2462
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0x2463
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0x2464
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0x2465
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0x2466
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0x2467
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0x2468
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0x2469
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0x246a
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0x246b
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0x246c
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0x246d
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0x246e
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0x246f
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0x2470
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0x2471
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0x2472
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0x2473
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0x2474
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0x2475
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0x2476
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0x2477
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0x2478
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0x2479
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0x247a
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0x247b
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0x247c
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0x247d
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32 0x247e
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33 0x247f
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34 0x2480
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35 0x2481
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36 0x2482
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37 0x2483
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38 0x2484
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39 0x2485
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40 0x2486
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41 0x2487
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42 0x2488
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43 0x2489
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44 0x248a
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45 0x248b
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46 0x248c
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47 0x248d
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48 0x248e
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49 0x248f
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50 0x2490
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51 0x2491
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52 0x2492
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53 0x2493
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54 0x2494
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55 0x2495
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56 0x2496
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57 0x2497
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58 0x2498
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59 0x2499
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60 0x249a
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61 0x249b
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62 0x249c
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63 0x249d
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64 0x249e
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65 0x249f
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66 0x24a0
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67 0x24a1
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68 0x24a2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69 0x24a3
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70 0x24a4
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71 0x24a5
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72 0x24a6
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73 0x24a7
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74 0x24a8
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75 0x24a9
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76 0x24aa
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77 0x24ab
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78 0x24ac
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79 0x24ad
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80 0x24ae
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81 0x24af
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82 0x24b0
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83 0x24b1
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84 0x24b2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85 0x24b3
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86 0x24b4
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87 0x24b5
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88 0x24b6
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89 0x24b7
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90 0x24b8
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91 0x24b9
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92 0x24ba
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93 0x24bb
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94 0x24bc
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95 0x24bd
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96 0x24be
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97 0x24bf
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98 0x24c0
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99 0x24c1
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100 0x24c2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101 0x24c3
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102 0x24c4
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103 0x24c5
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104 0x24c6
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105 0x24c7
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106 0x24c8
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107 0x24c9
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108 0x24ca
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109 0x24cb
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110 0x24cc
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111 0x24cd
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112 0x24ce
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113 0x24cf
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114 0x24d0
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115 0x24d1
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116 0x24d2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117 0x24d3
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118 0x24d4
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119 0x24d5
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120 0x24d6
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121 0x24d7
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122 0x24d8
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123 0x24d9
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124 0x24da
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125 0x24db
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126 0x24dc
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127 0x24dd
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128 0x24de
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129 0x24df
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130 0x24e0
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131 0x24e1
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132 0x24e2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133 0x24e3
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134 0x24e4
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135 0x24e5
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136 0x24e6
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137 0x24e7
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138 0x24e8
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139 0x24e9
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140 0x24ea
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141 0x24eb
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142 0x24ec
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143 0x24ed
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144 0x24ee
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145 0x24ef
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146 0x24f0
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147 0x24f1
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148 0x24f2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149 0x24f3
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150 0x24f4
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151 0x24f5
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152 0x24f6
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153 0x24f7
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154 0x24f8
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155 0x24f9
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156 0x24fa
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157 0x24fb
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158 0x24fc
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159 0x24fd
+-#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dc_combophycmregs4_dispdec
+-// base address: 0xc80
+-#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE1 0x245e
+-#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE1_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE2 0x245f
+-#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE2_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE3 0x2460
+-#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE3_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM 0x2461
+-#define mmDC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT 0x2462
+-#define mmDC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS4_COMMON_TXCNTRL 0x2463
+-#define mmDC_COMBOPHYCMREGS4_COMMON_TXCNTRL_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS4_COMMON_TMDP 0x2464
+-#define mmDC_COMBOPHYCMREGS4_COMMON_TMDP_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS4_COMMON_LANE_RESETS 0x2465
+-#define mmDC_COMBOPHYCMREGS4_COMMON_LANE_RESETS_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL 0x2466
+-#define mmDC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU1 0x2467
+-#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU1_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU2 0x2468
+-#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU2_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU3 0x2469
+-#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU3_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU4 0x246a
+-#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU4_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU5 0x246b
+-#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU5_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU6 0x246c
+-#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU6_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU7 0x246d
+-#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU7_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dc_combophytxregs4_dispdec
+-// base address: 0xc80
+-#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0 0x247e
+-#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0 0x247f
+-#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2480
+-#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0 0x2481
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0 0x2482
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0 0x2483
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0 0x2484
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0 0x2485
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0 0x2486
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0 0x2487
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0 0x2488
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0 0x2489
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0 0x248a
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0 0x248b
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0 0x248c
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0 0x248d
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1 0x248e
+-#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1 0x248f
+-#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2490
+-#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1 0x2491
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1 0x2492
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1 0x2493
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1 0x2494
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1 0x2495
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1 0x2496
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1 0x2497
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1 0x2498
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1 0x2499
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1 0x249a
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1 0x249b
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1 0x249c
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1 0x249d
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2 0x249e
+-#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2 0x249f
+-#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x24a0
+-#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2 0x24a1
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2 0x24a2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2 0x24a3
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2 0x24a4
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2 0x24a5
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2 0x24a6
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2 0x24a7
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2 0x24a8
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2 0x24a9
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2 0x24aa
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2 0x24ab
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2 0x24ac
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2 0x24ad
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3 0x24ae
+-#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3 0x24af
+-#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x24b0
+-#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3 0x24b1
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3 0x24b2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3 0x24b3
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3 0x24b4
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3 0x24b5
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3 0x24b6
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3 0x24b7
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3 0x24b8
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3 0x24b9
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3 0x24ba
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3 0x24bb
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3 0x24bc
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3 0x24bd
+-#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dc_combophypllregs4_dispdec
+-// base address: 0xc80
+-#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL0 0x24be
+-#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL0_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL1 0x24bf
+-#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL1_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL2 0x24c0
+-#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL2_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL3 0x24c1
+-#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL3_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS4_BW_CTRL_COARSE 0x24c2
+-#define mmDC_COMBOPHYPLLREGS4_BW_CTRL_COARSE_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS4_BW_CTRL_FINE 0x24c3
+-#define mmDC_COMBOPHYPLLREGS4_BW_CTRL_FINE_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS4_CAL_CTRL 0x24c4
+-#define mmDC_COMBOPHYPLLREGS4_CAL_CTRL_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS4_LOOP_CTRL 0x24c5
+-#define mmDC_COMBOPHYPLLREGS4_LOOP_CTRL_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS4_VREG_CFG 0x24c7
+-#define mmDC_COMBOPHYPLLREGS4_VREG_CFG_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS4_OBSERVE0 0x24c8
+-#define mmDC_COMBOPHYPLLREGS4_OBSERVE0_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS4_OBSERVE1 0x24c9
+-#define mmDC_COMBOPHYPLLREGS4_OBSERVE1_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS4_DFT_OUT 0x24ca
+-#define mmDC_COMBOPHYPLLREGS4_DFT_OUT_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dcio_uniphy5_dispdec
+-// base address: 0xfa0
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0 0x2526
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1 0x2527
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2 0x2528
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3 0x2529
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4 0x252a
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5 0x252b
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6 0x252c
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7 0x252d
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8 0x252e
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9 0x252f
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10 0x2530
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11 0x2531
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12 0x2532
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13 0x2533
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14 0x2534
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15 0x2535
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16 0x2536
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17 0x2537
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18 0x2538
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19 0x2539
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20 0x253a
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21 0x253b
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22 0x253c
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23 0x253d
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24 0x253e
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25 0x253f
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26 0x2540
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27 0x2541
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28 0x2542
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29 0x2543
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30 0x2544
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31 0x2545
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32 0x2546
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33 0x2547
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34 0x2548
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35 0x2549
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36 0x254a
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37 0x254b
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38 0x254c
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39 0x254d
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40 0x254e
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41 0x254f
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42 0x2550
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43 0x2551
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44 0x2552
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45 0x2553
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46 0x2554
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47 0x2555
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48 0x2556
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49 0x2557
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50 0x2558
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51 0x2559
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52 0x255a
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53 0x255b
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54 0x255c
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55 0x255d
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56 0x255e
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57 0x255f
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58 0x2560
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59 0x2561
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60 0x2562
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61 0x2563
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62 0x2564
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63 0x2565
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64 0x2566
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65 0x2567
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66 0x2568
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67 0x2569
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68 0x256a
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69 0x256b
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70 0x256c
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71 0x256d
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72 0x256e
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73 0x256f
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74 0x2570
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75 0x2571
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76 0x2572
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77 0x2573
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78 0x2574
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79 0x2575
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80 0x2576
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81 0x2577
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82 0x2578
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83 0x2579
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84 0x257a
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85 0x257b
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86 0x257c
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87 0x257d
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88 0x257e
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89 0x257f
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90 0x2580
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91 0x2581
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92 0x2582
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93 0x2583
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94 0x2584
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95 0x2585
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96 0x2586
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97 0x2587
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98 0x2588
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99 0x2589
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100 0x258a
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101 0x258b
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102 0x258c
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103 0x258d
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104 0x258e
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105 0x258f
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106 0x2590
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107 0x2591
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108 0x2592
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109 0x2593
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110 0x2594
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111 0x2595
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112 0x2596
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113 0x2597
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114 0x2598
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115 0x2599
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116 0x259a
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117 0x259b
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118 0x259c
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119 0x259d
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120 0x259e
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121 0x259f
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122 0x25a0
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123 0x25a1
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124 0x25a2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125 0x25a3
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126 0x25a4
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127 0x25a5
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128 0x25a6
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129 0x25a7
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130 0x25a8
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131 0x25a9
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132 0x25aa
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133 0x25ab
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134 0x25ac
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135 0x25ad
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136 0x25ae
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137 0x25af
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138 0x25b0
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139 0x25b1
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140 0x25b2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141 0x25b3
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142 0x25b4
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143 0x25b5
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144 0x25b6
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145 0x25b7
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146 0x25b8
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147 0x25b9
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148 0x25ba
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149 0x25bb
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150 0x25bc
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151 0x25bd
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152 0x25be
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153 0x25bf
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154 0x25c0
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155 0x25c1
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156 0x25c2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157 0x25c3
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158 0x25c4
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159 0x25c5
+-#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dc_combophycmregs5_dispdec
+-// base address: 0xfa0
+-#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE1 0x2526
+-#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE1_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE2 0x2527
+-#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE2_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE3 0x2528
+-#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE3_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM 0x2529
+-#define mmDC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT 0x252a
+-#define mmDC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS5_COMMON_TXCNTRL 0x252b
+-#define mmDC_COMBOPHYCMREGS5_COMMON_TXCNTRL_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS5_COMMON_TMDP 0x252c
+-#define mmDC_COMBOPHYCMREGS5_COMMON_TMDP_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS5_COMMON_LANE_RESETS 0x252d
+-#define mmDC_COMBOPHYCMREGS5_COMMON_LANE_RESETS_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL 0x252e
+-#define mmDC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU1 0x252f
+-#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU1_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU2 0x2530
+-#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU2_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU3 0x2531
+-#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU3_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU4 0x2532
+-#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU4_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU5 0x2533
+-#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU5_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU6 0x2534
+-#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU6_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU7 0x2535
+-#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU7_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dc_combophytxregs5_dispdec
+-// base address: 0xfa0
+-#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0 0x2546
+-#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0 0x2547
+-#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2548
+-#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0 0x2549
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0 0x254a
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0 0x254b
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0 0x254c
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0 0x254d
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0 0x254e
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0 0x254f
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0 0x2550
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0 0x2551
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0 0x2552
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0 0x2553
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0 0x2554
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0 0x2555
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1 0x2556
+-#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1 0x2557
+-#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2558
+-#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1 0x2559
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1 0x255a
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1 0x255b
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1 0x255c
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1 0x255d
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1 0x255e
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1 0x255f
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1 0x2560
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1 0x2561
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1 0x2562
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1 0x2563
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1 0x2564
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1 0x2565
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2 0x2566
+-#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2 0x2567
+-#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2568
+-#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2 0x2569
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2 0x256a
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2 0x256b
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2 0x256c
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2 0x256d
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2 0x256e
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2 0x256f
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2 0x2570
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2 0x2571
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2 0x2572
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2 0x2573
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2 0x2574
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2 0x2575
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3 0x2576
+-#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3 0x2577
+-#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2578
+-#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3 0x2579
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3 0x257a
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3 0x257b
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3 0x257c
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3 0x257d
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3 0x257e
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3 0x257f
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3 0x2580
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3 0x2581
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3 0x2582
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3 0x2583
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3 0x2584
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3 0x2585
+-#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dc_combophypllregs5_dispdec
+-// base address: 0xfa0
+-#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL0 0x2586
+-#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL0_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL1 0x2587
+-#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL1_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL2 0x2588
+-#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL2_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL3 0x2589
+-#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL3_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS5_BW_CTRL_COARSE 0x258a
+-#define mmDC_COMBOPHYPLLREGS5_BW_CTRL_COARSE_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS5_BW_CTRL_FINE 0x258b
+-#define mmDC_COMBOPHYPLLREGS5_BW_CTRL_FINE_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS5_CAL_CTRL 0x258c
+-#define mmDC_COMBOPHYPLLREGS5_CAL_CTRL_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS5_LOOP_CTRL 0x258d
+-#define mmDC_COMBOPHYPLLREGS5_LOOP_CTRL_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS5_VREG_CFG 0x258f
+-#define mmDC_COMBOPHYPLLREGS5_VREG_CFG_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS5_OBSERVE0 0x2590
+-#define mmDC_COMBOPHYPLLREGS5_OBSERVE0_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS5_OBSERVE1 0x2591
+-#define mmDC_COMBOPHYPLLREGS5_OBSERVE1_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS5_DFT_OUT 0x2592
+-#define mmDC_COMBOPHYPLLREGS5_DFT_OUT_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dcio_uniphy6_dispdec
+-// base address: 0x12c0
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0 0x25ee
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1 0x25ef
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2 0x25f0
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3 0x25f1
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4 0x25f2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5 0x25f3
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6 0x25f4
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7 0x25f5
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8 0x25f6
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9 0x25f7
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10 0x25f8
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11 0x25f9
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12 0x25fa
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13 0x25fb
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14 0x25fc
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15 0x25fd
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16 0x25fe
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17 0x25ff
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18 0x2600
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19 0x2601
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20 0x2602
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21 0x2603
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22 0x2604
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23 0x2605
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24 0x2606
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25 0x2607
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26 0x2608
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27 0x2609
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28 0x260a
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29 0x260b
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30 0x260c
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31 0x260d
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32 0x260e
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33 0x260f
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34 0x2610
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35 0x2611
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36 0x2612
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37 0x2613
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38 0x2614
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39 0x2615
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40 0x2616
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41 0x2617
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42 0x2618
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43 0x2619
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44 0x261a
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45 0x261b
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46 0x261c
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47 0x261d
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48 0x261e
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49 0x261f
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50 0x2620
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51 0x2621
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52 0x2622
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53 0x2623
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54 0x2624
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55 0x2625
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56 0x2626
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57 0x2627
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED58 0x2628
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED59 0x2629
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED60 0x262a
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED61 0x262b
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED62 0x262c
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED63 0x262d
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED64 0x262e
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED65 0x262f
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED66 0x2630
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED67 0x2631
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED68 0x2632
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED69 0x2633
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED70 0x2634
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED71 0x2635
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED72 0x2636
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED73 0x2637
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED74 0x2638
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED75 0x2639
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED76 0x263a
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED77 0x263b
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED78 0x263c
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED79 0x263d
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED80 0x263e
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED81 0x263f
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED82 0x2640
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED83 0x2641
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED84 0x2642
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED85 0x2643
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED86 0x2644
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED87 0x2645
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED88 0x2646
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED89 0x2647
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED90 0x2648
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED91 0x2649
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED92 0x264a
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED93 0x264b
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED94 0x264c
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED95 0x264d
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED96 0x264e
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED97 0x264f
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED98 0x2650
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED99 0x2651
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED100 0x2652
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED101 0x2653
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED102 0x2654
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED103 0x2655
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED104 0x2656
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED105 0x2657
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED106 0x2658
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED107 0x2659
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED108 0x265a
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED109 0x265b
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED110 0x265c
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED111 0x265d
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED112 0x265e
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED113 0x265f
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED114 0x2660
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED115 0x2661
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED116 0x2662
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED117 0x2663
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED118 0x2664
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED119 0x2665
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED120 0x2666
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED121 0x2667
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED122 0x2668
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED123 0x2669
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED124 0x266a
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED125 0x266b
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED126 0x266c
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED127 0x266d
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED128 0x266e
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED129 0x266f
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED130 0x2670
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED131 0x2671
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED132 0x2672
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED133 0x2673
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED134 0x2674
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED135 0x2675
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED136 0x2676
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED137 0x2677
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED138 0x2678
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED139 0x2679
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED140 0x267a
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED141 0x267b
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED142 0x267c
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED143 0x267d
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED144 0x267e
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED145 0x267f
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED146 0x2680
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED147 0x2681
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED148 0x2682
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED149 0x2683
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED150 0x2684
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED151 0x2685
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED152 0x2686
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED153 0x2687
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED154 0x2688
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED155 0x2689
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED156 0x268a
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED157 0x268b
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED158 0x268c
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED159 0x268d
+-#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dc_combophycmregs6_dispdec
+-// base address: 0x12c0
+-#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE1 0x25ee
+-#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE1_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE2 0x25ef
+-#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE2_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE3 0x25f0
+-#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE3_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM 0x25f1
+-#define mmDC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT 0x25f2
+-#define mmDC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS6_COMMON_TXCNTRL 0x25f3
+-#define mmDC_COMBOPHYCMREGS6_COMMON_TXCNTRL_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS6_COMMON_TMDP 0x25f4
+-#define mmDC_COMBOPHYCMREGS6_COMMON_TMDP_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS6_COMMON_LANE_RESETS 0x25f5
+-#define mmDC_COMBOPHYCMREGS6_COMMON_LANE_RESETS_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL 0x25f6
+-#define mmDC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU1 0x25f7
+-#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU1_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU2 0x25f8
+-#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU2_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU3 0x25f9
+-#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU3_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU4 0x25fa
+-#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU4_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU5 0x25fb
+-#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU5_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU6 0x25fc
+-#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU6_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU7 0x25fd
+-#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU7_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dc_combophytxregs6_dispdec
+-// base address: 0x12c0
+-#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0 0x260e
+-#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0 0x260f
+-#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2610
+-#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE0 0x2611
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE0 0x2612
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE0 0x2613
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE0 0x2614
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE0 0x2615
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE0 0x2616
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE0 0x2617
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE0 0x2618
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE0 0x2619
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE0 0x261a
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE0 0x261b
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE0 0x261c
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE0 0x261d
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1 0x261e
+-#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1 0x261f
+-#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2620
+-#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE1 0x2621
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE1 0x2622
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE1 0x2623
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE1 0x2624
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE1 0x2625
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE1 0x2626
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE1 0x2627
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE1 0x2628
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE1 0x2629
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE1 0x262a
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE1 0x262b
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE1 0x262c
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE1 0x262d
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2 0x262e
+-#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2 0x262f
+-#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2630
+-#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE2 0x2631
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE2 0x2632
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE2 0x2633
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE2 0x2634
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE2 0x2635
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE2 0x2636
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE2 0x2637
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE2 0x2638
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE2 0x2639
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE2 0x263a
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE2 0x263b
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE2 0x263c
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE2 0x263d
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3 0x263e
+-#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3 0x263f
+-#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2640
+-#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE3 0x2641
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE3 0x2642
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE3 0x2643
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE3 0x2644
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE3 0x2645
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE3 0x2646
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE3 0x2647
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE3 0x2648
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE3 0x2649
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE3 0x264a
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE3 0x264b
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE3 0x264c
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE3 0x264d
+-#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE3_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dc_combophypllregs6_dispdec
+-// base address: 0x12c0
+-#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL0 0x264e
+-#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL0_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL1 0x264f
+-#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL1_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL2 0x2650
+-#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL2_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL3 0x2651
+-#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL3_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS6_BW_CTRL_COARSE 0x2652
+-#define mmDC_COMBOPHYPLLREGS6_BW_CTRL_COARSE_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS6_BW_CTRL_FINE 0x2653
+-#define mmDC_COMBOPHYPLLREGS6_BW_CTRL_FINE_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS6_CAL_CTRL 0x2654
+-#define mmDC_COMBOPHYPLLREGS6_CAL_CTRL_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS6_LOOP_CTRL 0x2655
+-#define mmDC_COMBOPHYPLLREGS6_LOOP_CTRL_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS6_VREG_CFG 0x2657
+-#define mmDC_COMBOPHYPLLREGS6_VREG_CFG_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS6_OBSERVE0 0x2658
+-#define mmDC_COMBOPHYPLLREGS6_OBSERVE0_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS6_OBSERVE1 0x2659
+-#define mmDC_COMBOPHYPLLREGS6_OBSERVE1_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS6_DFT_OUT 0x265a
+-#define mmDC_COMBOPHYPLLREGS6_DFT_OUT_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dcio_uniphy8_dispdec
+-// base address: 0x15e0
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0 0x26b6
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1 0x26b7
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2 0x26b8
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3 0x26b9
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4 0x26ba
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5 0x26bb
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6 0x26bc
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7 0x26bd
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8 0x26be
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9 0x26bf
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10 0x26c0
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11 0x26c1
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12 0x26c2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13 0x26c3
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14 0x26c4
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15 0x26c5
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16 0x26c6
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17 0x26c7
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18 0x26c8
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19 0x26c9
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20 0x26ca
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21 0x26cb
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22 0x26cc
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23 0x26cd
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24 0x26ce
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25 0x26cf
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26 0x26d0
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27 0x26d1
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28 0x26d2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29 0x26d3
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30 0x26d4
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31 0x26d5
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED32 0x26d6
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED33 0x26d7
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED34 0x26d8
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED35 0x26d9
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED36 0x26da
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED37 0x26db
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED38 0x26dc
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED39 0x26dd
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED40 0x26de
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED41 0x26df
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED42 0x26e0
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED43 0x26e1
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED44 0x26e2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED45 0x26e3
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED46 0x26e4
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED47 0x26e5
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED48 0x26e6
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED49 0x26e7
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED50 0x26e8
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED51 0x26e9
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED52 0x26ea
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED53 0x26eb
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED54 0x26ec
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED55 0x26ed
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED56 0x26ee
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED57 0x26ef
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED58 0x26f0
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED59 0x26f1
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED60 0x26f2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED61 0x26f3
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED62 0x26f4
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED63 0x26f5
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED64 0x26f6
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED65 0x26f7
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED66 0x26f8
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED67 0x26f9
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED68 0x26fa
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED69 0x26fb
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED70 0x26fc
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED71 0x26fd
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED72 0x26fe
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED73 0x26ff
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED74 0x2700
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED75 0x2701
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED76 0x2702
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED77 0x2703
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED78 0x2704
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED79 0x2705
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED80 0x2706
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED81 0x2707
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED82 0x2708
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED83 0x2709
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED84 0x270a
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED85 0x270b
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED86 0x270c
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED87 0x270d
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED88 0x270e
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED89 0x270f
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED90 0x2710
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED91 0x2711
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED92 0x2712
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED93 0x2713
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED94 0x2714
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED95 0x2715
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED96 0x2716
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED97 0x2717
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED98 0x2718
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED99 0x2719
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED100 0x271a
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED101 0x271b
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED102 0x271c
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED103 0x271d
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED104 0x271e
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED105 0x271f
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED106 0x2720
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED107 0x2721
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED108 0x2722
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED109 0x2723
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED110 0x2724
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED111 0x2725
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED112 0x2726
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED113 0x2727
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED114 0x2728
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED115 0x2729
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED116 0x272a
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED117 0x272b
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED118 0x272c
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED119 0x272d
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED120 0x272e
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED121 0x272f
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED122 0x2730
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED123 0x2731
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED124 0x2732
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED125 0x2733
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED126 0x2734
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED127 0x2735
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED128 0x2736
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED129 0x2737
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED130 0x2738
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED131 0x2739
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED132 0x273a
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED133 0x273b
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED134 0x273c
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED135 0x273d
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED136 0x273e
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED137 0x273f
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED138 0x2740
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED139 0x2741
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED140 0x2742
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED141 0x2743
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED142 0x2744
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED143 0x2745
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED144 0x2746
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED145 0x2747
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED146 0x2748
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED147 0x2749
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED148 0x274a
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED149 0x274b
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED150 0x274c
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED151 0x274d
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED152 0x274e
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED153 0x274f
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED154 0x2750
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED155 0x2751
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED156 0x2752
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED157 0x2753
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED158 0x2754
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED159 0x2755
+-#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dc_combophycmregs8_dispdec
+-// base address: 0x15e0
+-#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE1 0x26b6
+-#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE1_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE2 0x26b7
+-#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE2_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE3 0x26b8
+-#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE3_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM 0x26b9
+-#define mmDC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT 0x26ba
+-#define mmDC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS8_COMMON_TXCNTRL 0x26bb
+-#define mmDC_COMBOPHYCMREGS8_COMMON_TXCNTRL_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS8_COMMON_TMDP 0x26bc
+-#define mmDC_COMBOPHYCMREGS8_COMMON_TMDP_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS8_COMMON_LANE_RESETS 0x26bd
+-#define mmDC_COMBOPHYCMREGS8_COMMON_LANE_RESETS_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL 0x26be
+-#define mmDC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU1 0x26bf
+-#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU1_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU2 0x26c0
+-#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU2_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU3 0x26c1
+-#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU3_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU4 0x26c2
+-#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU4_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU5 0x26c3
+-#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU5_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU6 0x26c4
+-#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU6_BASE_IDX 2
+-#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU7 0x26c5
+-#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU7_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dc_combophytxregs8_dispdec
+-// base address: 0x15e0
+-#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0 0x26d6
+-#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0 0x26d7
+-#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x26d8
+-#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE0 0x26d9
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE0 0x26da
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE0 0x26db
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE0 0x26dc
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE0 0x26dd
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE0 0x26de
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE0 0x26df
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE0 0x26e0
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE0 0x26e1
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE0 0x26e2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE0 0x26e3
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE0 0x26e4
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE0 0x26e5
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE0_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1 0x26e6
+-#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1 0x26e7
+-#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x26e8
+-#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE1 0x26e9
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE1 0x26ea
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE1 0x26eb
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE1 0x26ec
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE1 0x26ed
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE1 0x26ee
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE1 0x26ef
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE1 0x26f0
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE1 0x26f1
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE1 0x26f2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE1 0x26f3
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE1 0x26f4
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE1 0x26f5
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE1_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2 0x26f6
+-#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2 0x26f7
+-#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x26f8
+-#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE2 0x26f9
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE2 0x26fa
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE2 0x26fb
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE2 0x26fc
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE2 0x26fd
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE2 0x26fe
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE2 0x26ff
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE2 0x2700
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE2 0x2701
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE2 0x2702
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE2 0x2703
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE2 0x2704
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE2 0x2705
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE2_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3 0x2706
+-#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3 0x2707
+-#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2708
+-#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE3 0x2709
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE3 0x270a
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE3 0x270b
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE3 0x270c
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE3 0x270d
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE3 0x270e
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE3 0x270f
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE3 0x2710
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE3 0x2711
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE3 0x2712
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE3 0x2713
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE3 0x2714
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE3_BASE_IDX 2
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE3 0x2715
+-#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE3_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dc_combophypllregs8_dispdec
+-// base address: 0x15e0
+-#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL0 0x2716
+-#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL0_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL1 0x2717
+-#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL1_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL2 0x2718
+-#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL2_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL3 0x2719
+-#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL3_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS8_BW_CTRL_COARSE 0x271a
+-#define mmDC_COMBOPHYPLLREGS8_BW_CTRL_COARSE_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS8_BW_CTRL_FINE 0x271b
+-#define mmDC_COMBOPHYPLLREGS8_BW_CTRL_FINE_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS8_CAL_CTRL 0x271c
+-#define mmDC_COMBOPHYPLLREGS8_CAL_CTRL_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS8_LOOP_CTRL 0x271d
+-#define mmDC_COMBOPHYPLLREGS8_LOOP_CTRL_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS8_VREG_CFG 0x271f
+-#define mmDC_COMBOPHYPLLREGS8_VREG_CFG_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS8_OBSERVE0 0x2720
+-#define mmDC_COMBOPHYPLLREGS8_OBSERVE0_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS8_OBSERVE1 0x2721
+-#define mmDC_COMBOPHYPLLREGS8_OBSERVE1_BASE_IDX 2
+-#define mmDC_COMBOPHYPLLREGS8_DFT_OUT 0x2722
+-#define mmDC_COMBOPHYPLLREGS8_DFT_OUT_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dsi0_dispdec
+-// base address: 0x0
+-#define mmDSI0_DISP_DSI_CTRL 0x27be
+-#define mmDSI0_DISP_DSI_CTRL_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_STATUS 0x27bf
+-#define mmDSI0_DISP_DSI_STATUS_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_VIDEO_MODE_CTRL 0x27c0
+-#define mmDSI0_DISP_DSI_VIDEO_MODE_CTRL_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE 0x27c1
+-#define mmDSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD 0x27c2
+-#define mmDSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD 0x27c3
+-#define mmDSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE 0x27c4
+-#define mmDSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE 0x27c5
+-#define mmDSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL 0x27c6
+-#define mmDSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_COMMAND_MODE_CTRL 0x27c7
+-#define mmDSI0_DISP_DSI_COMMAND_MODE_CTRL_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL 0x27c8
+-#define mmDSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL 0x27c9
+-#define mmDSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_DMA_CMD_OFFSET 0x27ca
+-#define mmDSI0_DISP_DSI_DMA_CMD_OFFSET_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_DMA_CMD_LENGTH 0x27cb
+-#define mmDSI0_DISP_DSI_DMA_CMD_LENGTH_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_DMA_DATA_OFFSET_0 0x27cc
+-#define mmDSI0_DISP_DSI_DMA_DATA_OFFSET_0_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_DMA_DATA_OFFSET_1 0x27cd
+-#define mmDSI0_DISP_DSI_DMA_DATA_OFFSET_1_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_DMA_DATA_PITCH 0x27ce
+-#define mmDSI0_DISP_DSI_DMA_DATA_PITCH_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_DMA_DATA_WIDTH 0x27cf
+-#define mmDSI0_DISP_DSI_DMA_DATA_WIDTH_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_DMA_DATA_HEIGHT 0x27d0
+-#define mmDSI0_DISP_DSI_DMA_DATA_HEIGHT_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_DMA_FIFO_CTRL 0x27d1
+-#define mmDSI0_DISP_DSI_DMA_FIFO_CTRL_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_DMA_NULL_PACKET_DATA 0x27d2
+-#define mmDSI0_DISP_DSI_DMA_NULL_PACKET_DATA_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_DENG_DATA_LENGTH 0x27d3
+-#define mmDSI0_DISP_DSI_DENG_DATA_LENGTH_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_ACK_ERROR_REPORT 0x27d4
+-#define mmDSI0_DISP_DSI_ACK_ERROR_REPORT_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_RDBK_DATA0 0x27d5
+-#define mmDSI0_DISP_DSI_RDBK_DATA0_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_RDBK_DATA1 0x27d6
+-#define mmDSI0_DISP_DSI_RDBK_DATA1_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_RDBK_DATA2 0x27d7
+-#define mmDSI0_DISP_DSI_RDBK_DATA2_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_RDBK_DATA3 0x27d8
+-#define mmDSI0_DISP_DSI_RDBK_DATA3_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_RDBK_DATATYPE0 0x27d9
+-#define mmDSI0_DISP_DSI_RDBK_DATATYPE0_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_RDBK_DATATYPE1 0x27da
+-#define mmDSI0_DISP_DSI_RDBK_DATATYPE1_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_TRIG_CTRL 0x27db
+-#define mmDSI0_DISP_DSI_TRIG_CTRL_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_EXT_MUX 0x27dc
+-#define mmDSI0_DISP_DSI_EXT_MUX_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL 0x27dd
+-#define mmDSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER 0x27de
+-#define mmDSI0_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER 0x27df
+-#define mmDSI0_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER 0x27e0
+-#define mmDSI0_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_RESET_SW_TRIGGER 0x27e1
+-#define mmDSI0_DISP_DSI_RESET_SW_TRIGGER_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_EXT_RESET 0x27e2
+-#define mmDSI0_DISP_DSI_EXT_RESET_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_LANE_CRC_HS_MODE 0x27e3
+-#define mmDSI0_DISP_DSI_LANE_CRC_HS_MODE_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_LANE_CRC_LP_MODE 0x27e4
+-#define mmDSI0_DISP_DSI_LANE_CRC_LP_MODE_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_LANE_CRC_CTRL 0x27e5
+-#define mmDSI0_DISP_DSI_LANE_CRC_CTRL_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_PIXEL_CRC_CTRL 0x27e6
+-#define mmDSI0_DISP_DSI_PIXEL_CRC_CTRL_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_LANE_CTRL 0x27e7
+-#define mmDSI0_DISP_DSI_LANE_CTRL_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_DLN0_PHY_ERROR 0x27e8
+-#define mmDSI0_DISP_DSI_DLN0_PHY_ERROR_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_LP_TIMER_CTRL 0x27e9
+-#define mmDSI0_DISP_DSI_LP_TIMER_CTRL_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_HS_TIMER_CTRL 0x27ea
+-#define mmDSI0_DISP_DSI_HS_TIMER_CTRL_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_TIMEOUT_STATUS 0x27eb
+-#define mmDSI0_DISP_DSI_TIMEOUT_STATUS_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL 0x27ec
+-#define mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2 0x27ed
+-#define mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_EOT_PACKET 0x27ee
+-#define mmDSI0_DISP_DSI_EOT_PACKET_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_EOT_PACKET_CTRL 0x27ef
+-#define mmDSI0_DISP_DSI_EOT_PACKET_CTRL_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER 0x27f0
+-#define mmDSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_MIPI_BIST_CTRL 0x27f1
+-#define mmDSI0_DISP_DSI_MIPI_BIST_CTRL_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE 0x27f2
+-#define mmDSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE 0x27f3
+-#define mmDSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG 0x27f4
+-#define mmDSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL 0x27f5
+-#define mmDSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_MIPI_BIST_LSFR_INIT 0x27f6
+-#define mmDSI0_DISP_DSI_MIPI_BIST_LSFR_INIT_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_MIPI_BIST_START 0x27f7
+-#define mmDSI0_DISP_DSI_MIPI_BIST_START_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_MIPI_BIST_STATUS 0x27f8
+-#define mmDSI0_DISP_DSI_MIPI_BIST_STATUS_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_ERROR_INTERRUPT_MASK 0x27f9
+-#define mmDSI0_DISP_DSI_ERROR_INTERRUPT_MASK_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_INTERRUPT_CTRL 0x27fa
+-#define mmDSI0_DISP_DSI_INTERRUPT_CTRL_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_CLK_CTRL 0x27fb
+-#define mmDSI0_DISP_DSI_CLK_CTRL_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_CLK_STATUS 0x27fc
+-#define mmDSI0_DISP_DSI_CLK_STATUS_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_DENG_FIFO_STATUS 0x27fd
+-#define mmDSI0_DISP_DSI_DENG_FIFO_STATUS_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_DENG_FIFO_CTRL 0x27fe
+-#define mmDSI0_DISP_DSI_DENG_FIFO_CTRL_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_CMD_FIFO_DATA 0x27ff
+-#define mmDSI0_DISP_DSI_CMD_FIFO_DATA_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_CMD_FIFO_CTRL 0x2800
+-#define mmDSI0_DISP_DSI_CMD_FIFO_CTRL_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_TE_CTRL 0x2801
+-#define mmDSI0_DISP_DSI_TE_CTRL_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_LANE_STATUS 0x2805
+-#define mmDSI0_DISP_DSI_LANE_STATUS_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_PERF_CTRL 0x2806
+-#define mmDSI0_DISP_DSI_PERF_CTRL_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_HSYNC_LENGTH 0x2807
+-#define mmDSI0_DISP_DSI_HSYNC_LENGTH_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_RDBK_NUM 0x2808
+-#define mmDSI0_DISP_DSI_RDBK_NUM_BASE_IDX 2
+-#define mmDSI0_DISP_DSI_CMD_MEM_PWR_CTRL 0x2809
+-#define mmDSI0_DISP_DSI_CMD_MEM_PWR_CTRL_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dsi1_dispdec
+-// base address: 0x400
+-#define mmDSI1_DISP_DSI_CTRL 0x28be
+-#define mmDSI1_DISP_DSI_CTRL_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_STATUS 0x28bf
+-#define mmDSI1_DISP_DSI_STATUS_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_VIDEO_MODE_CTRL 0x28c0
+-#define mmDSI1_DISP_DSI_VIDEO_MODE_CTRL_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE 0x28c1
+-#define mmDSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD 0x28c2
+-#define mmDSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD 0x28c3
+-#define mmDSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE 0x28c4
+-#define mmDSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE 0x28c5
+-#define mmDSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL 0x28c6
+-#define mmDSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_COMMAND_MODE_CTRL 0x28c7
+-#define mmDSI1_DISP_DSI_COMMAND_MODE_CTRL_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL 0x28c8
+-#define mmDSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL 0x28c9
+-#define mmDSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_DMA_CMD_OFFSET 0x28ca
+-#define mmDSI1_DISP_DSI_DMA_CMD_OFFSET_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_DMA_CMD_LENGTH 0x28cb
+-#define mmDSI1_DISP_DSI_DMA_CMD_LENGTH_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_DMA_DATA_OFFSET_0 0x28cc
+-#define mmDSI1_DISP_DSI_DMA_DATA_OFFSET_0_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_DMA_DATA_OFFSET_1 0x28cd
+-#define mmDSI1_DISP_DSI_DMA_DATA_OFFSET_1_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_DMA_DATA_PITCH 0x28ce
+-#define mmDSI1_DISP_DSI_DMA_DATA_PITCH_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_DMA_DATA_WIDTH 0x28cf
+-#define mmDSI1_DISP_DSI_DMA_DATA_WIDTH_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_DMA_DATA_HEIGHT 0x28d0
+-#define mmDSI1_DISP_DSI_DMA_DATA_HEIGHT_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_DMA_FIFO_CTRL 0x28d1
+-#define mmDSI1_DISP_DSI_DMA_FIFO_CTRL_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_DMA_NULL_PACKET_DATA 0x28d2
+-#define mmDSI1_DISP_DSI_DMA_NULL_PACKET_DATA_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_DENG_DATA_LENGTH 0x28d3
+-#define mmDSI1_DISP_DSI_DENG_DATA_LENGTH_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_ACK_ERROR_REPORT 0x28d4
+-#define mmDSI1_DISP_DSI_ACK_ERROR_REPORT_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_RDBK_DATA0 0x28d5
+-#define mmDSI1_DISP_DSI_RDBK_DATA0_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_RDBK_DATA1 0x28d6
+-#define mmDSI1_DISP_DSI_RDBK_DATA1_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_RDBK_DATA2 0x28d7
+-#define mmDSI1_DISP_DSI_RDBK_DATA2_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_RDBK_DATA3 0x28d8
+-#define mmDSI1_DISP_DSI_RDBK_DATA3_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_RDBK_DATATYPE0 0x28d9
+-#define mmDSI1_DISP_DSI_RDBK_DATATYPE0_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_RDBK_DATATYPE1 0x28da
+-#define mmDSI1_DISP_DSI_RDBK_DATATYPE1_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_TRIG_CTRL 0x28db
+-#define mmDSI1_DISP_DSI_TRIG_CTRL_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_EXT_MUX 0x28dc
+-#define mmDSI1_DISP_DSI_EXT_MUX_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL 0x28dd
+-#define mmDSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER 0x28de
+-#define mmDSI1_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER 0x28df
+-#define mmDSI1_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER 0x28e0
+-#define mmDSI1_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_RESET_SW_TRIGGER 0x28e1
+-#define mmDSI1_DISP_DSI_RESET_SW_TRIGGER_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_EXT_RESET 0x28e2
+-#define mmDSI1_DISP_DSI_EXT_RESET_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_LANE_CRC_HS_MODE 0x28e3
+-#define mmDSI1_DISP_DSI_LANE_CRC_HS_MODE_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_LANE_CRC_LP_MODE 0x28e4
+-#define mmDSI1_DISP_DSI_LANE_CRC_LP_MODE_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_LANE_CRC_CTRL 0x28e5
+-#define mmDSI1_DISP_DSI_LANE_CRC_CTRL_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_PIXEL_CRC_CTRL 0x28e6
+-#define mmDSI1_DISP_DSI_PIXEL_CRC_CTRL_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_LANE_CTRL 0x28e7
+-#define mmDSI1_DISP_DSI_LANE_CTRL_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_DLN0_PHY_ERROR 0x28e8
+-#define mmDSI1_DISP_DSI_DLN0_PHY_ERROR_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_LP_TIMER_CTRL 0x28e9
+-#define mmDSI1_DISP_DSI_LP_TIMER_CTRL_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_HS_TIMER_CTRL 0x28ea
+-#define mmDSI1_DISP_DSI_HS_TIMER_CTRL_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_TIMEOUT_STATUS 0x28eb
+-#define mmDSI1_DISP_DSI_TIMEOUT_STATUS_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL 0x28ec
+-#define mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2 0x28ed
+-#define mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_EOT_PACKET 0x28ee
+-#define mmDSI1_DISP_DSI_EOT_PACKET_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_EOT_PACKET_CTRL 0x28ef
+-#define mmDSI1_DISP_DSI_EOT_PACKET_CTRL_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER 0x28f0
+-#define mmDSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_MIPI_BIST_CTRL 0x28f1
+-#define mmDSI1_DISP_DSI_MIPI_BIST_CTRL_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE 0x28f2
+-#define mmDSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE 0x28f3
+-#define mmDSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG 0x28f4
+-#define mmDSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL 0x28f5
+-#define mmDSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_MIPI_BIST_LSFR_INIT 0x28f6
+-#define mmDSI1_DISP_DSI_MIPI_BIST_LSFR_INIT_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_MIPI_BIST_START 0x28f7
+-#define mmDSI1_DISP_DSI_MIPI_BIST_START_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_MIPI_BIST_STATUS 0x28f8
+-#define mmDSI1_DISP_DSI_MIPI_BIST_STATUS_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_ERROR_INTERRUPT_MASK 0x28f9
+-#define mmDSI1_DISP_DSI_ERROR_INTERRUPT_MASK_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_INTERRUPT_CTRL 0x28fa
+-#define mmDSI1_DISP_DSI_INTERRUPT_CTRL_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_CLK_CTRL 0x28fb
+-#define mmDSI1_DISP_DSI_CLK_CTRL_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_CLK_STATUS 0x28fc
+-#define mmDSI1_DISP_DSI_CLK_STATUS_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_DENG_FIFO_STATUS 0x28fd
+-#define mmDSI1_DISP_DSI_DENG_FIFO_STATUS_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_DENG_FIFO_CTRL 0x28fe
+-#define mmDSI1_DISP_DSI_DENG_FIFO_CTRL_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_CMD_FIFO_DATA 0x28ff
+-#define mmDSI1_DISP_DSI_CMD_FIFO_DATA_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_CMD_FIFO_CTRL 0x2900
+-#define mmDSI1_DISP_DSI_CMD_FIFO_CTRL_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_TE_CTRL 0x2901
+-#define mmDSI1_DISP_DSI_TE_CTRL_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_LANE_STATUS 0x2905
+-#define mmDSI1_DISP_DSI_LANE_STATUS_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_PERF_CTRL 0x2906
+-#define mmDSI1_DISP_DSI_PERF_CTRL_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_HSYNC_LENGTH 0x2907
+-#define mmDSI1_DISP_DSI_HSYNC_LENGTH_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_RDBK_NUM 0x2908
+-#define mmDSI1_DISP_DSI_RDBK_NUM_BASE_IDX 2
+-#define mmDSI1_DISP_DSI_CMD_MEM_PWR_CTRL 0x2909
+-#define mmDSI1_DISP_DSI_CMD_MEM_PWR_CTRL_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dprx_sd0_dispdec
+-// base address: 0x0
+-#define mmDPRX_SD0_DPRX_SD_CONTROL 0x29be
+-#define mmDPRX_SD0_DPRX_SD_CONTROL_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_STREAM_ENABLE 0x29bf
+-#define mmDPRX_SD0_DPRX_SD_STREAM_ENABLE_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_MSA0 0x29c0
+-#define mmDPRX_SD0_DPRX_SD_MSA0_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_MSA1 0x29c1
+-#define mmDPRX_SD0_DPRX_SD_MSA1_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_MSA2 0x29c2
+-#define mmDPRX_SD0_DPRX_SD_MSA2_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_MSA3 0x29c3
+-#define mmDPRX_SD0_DPRX_SD_MSA3_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_MSA4 0x29c4
+-#define mmDPRX_SD0_DPRX_SD_MSA4_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_MSA5 0x29c5
+-#define mmDPRX_SD0_DPRX_SD_MSA5_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_MSA6 0x29c6
+-#define mmDPRX_SD0_DPRX_SD_MSA6_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_MSA7 0x29c7
+-#define mmDPRX_SD0_DPRX_SD_MSA7_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_MSA8 0x29c8
+-#define mmDPRX_SD0_DPRX_SD_MSA8_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_VBID 0x29c9
+-#define mmDPRX_SD0_DPRX_SD_VBID_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_CURRENT_LINE 0x29ca
+-#define mmDPRX_SD0_DPRX_SD_CURRENT_LINE_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_SNAPSHOT 0x29cb
+-#define mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_SNAPSHOT_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE 0x29cc
+-#define mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_MSE_SAT 0x29ce
+-#define mmDPRX_SD0_DPRX_SD_MSE_SAT_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_MSE_FORCE_UPDATE 0x29cf
+-#define mmDPRX_SD0_DPRX_SD_MSE_FORCE_UPDATE_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE 0x29d0
+-#define mmDPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_V_PARAMETER 0x29d1
+-#define mmDPRX_SD0_DPRX_SD_V_PARAMETER_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_PIXEL_FORMAT 0x29d2
+-#define mmDPRX_SD0_DPRX_SD_PIXEL_FORMAT_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS 0x29d3
+-#define mmDPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED 0x29d4
+-#define mmDPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS 0x29d5
+-#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_CONTROL 0x29d6
+-#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_CONTROL_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS 0x29d7
+-#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_CONTROL 0x29d8
+-#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_CONTROL_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR 0x29d9
+-#define mmDPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE 0x29da
+-#define mmDPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR 0x29db
+-#define mmDPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_VCPF_PHASE_LOCKED 0x29dc
+-#define mmDPRX_SD0_DPRX_SD_VCPF_PHASE_LOCKED_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR 0x29dd
+-#define mmDPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR 0x29de
+-#define mmDPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_PIXEL_FIFO_ERROR 0x29df
+-#define mmDPRX_SD0_DPRX_SD_PIXEL_FIFO_ERROR_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH 0x29e1
+-#define mmDPRX_SD0_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_SDP_STEER 0x29e3
+-#define mmDPRX_SD0_DPRX_SD_SDP_STEER_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS 0x29e4
+-#define mmDPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_SDP_LEVEL 0x29e5
+-#define mmDPRX_SD0_DPRX_SD_SDP_LEVEL_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_SDP_DATA 0x29e6
+-#define mmDPRX_SD0_DPRX_SD_SDP_DATA_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_SDP_ERROR 0x29e7
+-#define mmDPRX_SD0_DPRX_SD_SDP_ERROR_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_AUDIO_HEADER 0x29e8
+-#define mmDPRX_SD0_DPRX_SD_AUDIO_HEADER_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_AUDIO_FIFO_ERROR 0x29e9
+-#define mmDPRX_SD0_DPRX_SD_AUDIO_FIFO_ERROR_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_SDP_CONTROL 0x29ea
+-#define mmDPRX_SD0_DPRX_SD_SDP_CONTROL_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_V_TOTAL_MEASURED 0x29eb
+-#define mmDPRX_SD0_DPRX_SD_V_TOTAL_MEASURED_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_H_TOTAL_MEASURED 0x29ec
+-#define mmDPRX_SD0_DPRX_SD_H_TOTAL_MEASURED_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_BS_COUNTER 0x29ed
+-#define mmDPRX_SD0_DPRX_SD_BS_COUNTER_BASE_IDX 2
+-#define mmDPRX_SD0_DPRX_SD_MSE_ACT_HANDLED 0x29ee
+-#define mmDPRX_SD0_DPRX_SD_MSE_ACT_HANDLED_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dprx_sd1_dispdec
+-// base address: 0x180
+-#define mmDPRX_SD1_DPRX_SD_CONTROL 0x2a1e
+-#define mmDPRX_SD1_DPRX_SD_CONTROL_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_STREAM_ENABLE 0x2a1f
+-#define mmDPRX_SD1_DPRX_SD_STREAM_ENABLE_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_MSA0 0x2a20
+-#define mmDPRX_SD1_DPRX_SD_MSA0_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_MSA1 0x2a21
+-#define mmDPRX_SD1_DPRX_SD_MSA1_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_MSA2 0x2a22
+-#define mmDPRX_SD1_DPRX_SD_MSA2_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_MSA3 0x2a23
+-#define mmDPRX_SD1_DPRX_SD_MSA3_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_MSA4 0x2a24
+-#define mmDPRX_SD1_DPRX_SD_MSA4_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_MSA5 0x2a25
+-#define mmDPRX_SD1_DPRX_SD_MSA5_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_MSA6 0x2a26
+-#define mmDPRX_SD1_DPRX_SD_MSA6_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_MSA7 0x2a27
+-#define mmDPRX_SD1_DPRX_SD_MSA7_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_MSA8 0x2a28
+-#define mmDPRX_SD1_DPRX_SD_MSA8_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_VBID 0x2a29
+-#define mmDPRX_SD1_DPRX_SD_VBID_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_CURRENT_LINE 0x2a2a
+-#define mmDPRX_SD1_DPRX_SD_CURRENT_LINE_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_SNAPSHOT 0x2a2b
+-#define mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_SNAPSHOT_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE 0x2a2c
+-#define mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_MSE_SAT 0x2a2e
+-#define mmDPRX_SD1_DPRX_SD_MSE_SAT_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_MSE_FORCE_UPDATE 0x2a2f
+-#define mmDPRX_SD1_DPRX_SD_MSE_FORCE_UPDATE_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE 0x2a30
+-#define mmDPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_V_PARAMETER 0x2a31
+-#define mmDPRX_SD1_DPRX_SD_V_PARAMETER_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_PIXEL_FORMAT 0x2a32
+-#define mmDPRX_SD1_DPRX_SD_PIXEL_FORMAT_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS 0x2a33
+-#define mmDPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED 0x2a34
+-#define mmDPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS 0x2a35
+-#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_CONTROL 0x2a36
+-#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_CONTROL_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS 0x2a37
+-#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_CONTROL 0x2a38
+-#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_CONTROL_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR 0x2a39
+-#define mmDPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE 0x2a3a
+-#define mmDPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR 0x2a3b
+-#define mmDPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_VCPF_PHASE_LOCKED 0x2a3c
+-#define mmDPRX_SD1_DPRX_SD_VCPF_PHASE_LOCKED_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR 0x2a3d
+-#define mmDPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR 0x2a3e
+-#define mmDPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_PIXEL_FIFO_ERROR 0x2a3f
+-#define mmDPRX_SD1_DPRX_SD_PIXEL_FIFO_ERROR_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH 0x2a41
+-#define mmDPRX_SD1_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_SDP_STEER 0x2a43
+-#define mmDPRX_SD1_DPRX_SD_SDP_STEER_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS 0x2a44
+-#define mmDPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_SDP_LEVEL 0x2a45
+-#define mmDPRX_SD1_DPRX_SD_SDP_LEVEL_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_SDP_DATA 0x2a46
+-#define mmDPRX_SD1_DPRX_SD_SDP_DATA_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_SDP_ERROR 0x2a47
+-#define mmDPRX_SD1_DPRX_SD_SDP_ERROR_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_AUDIO_HEADER 0x2a48
+-#define mmDPRX_SD1_DPRX_SD_AUDIO_HEADER_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_AUDIO_FIFO_ERROR 0x2a49
+-#define mmDPRX_SD1_DPRX_SD_AUDIO_FIFO_ERROR_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_SDP_CONTROL 0x2a4a
+-#define mmDPRX_SD1_DPRX_SD_SDP_CONTROL_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_V_TOTAL_MEASURED 0x2a4b
+-#define mmDPRX_SD1_DPRX_SD_V_TOTAL_MEASURED_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_H_TOTAL_MEASURED 0x2a4c
+-#define mmDPRX_SD1_DPRX_SD_H_TOTAL_MEASURED_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_BS_COUNTER 0x2a4d
+-#define mmDPRX_SD1_DPRX_SD_BS_COUNTER_BASE_IDX 2
+-#define mmDPRX_SD1_DPRX_SD_MSE_ACT_HANDLED 0x2a4e
+-#define mmDPRX_SD1_DPRX_SD_MSE_ACT_HANDLED_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dc_perfmon10_dispdec
+-// base address: 0xacf8
+-#define mmDC_PERFMON10_PERFCOUNTER_CNTL 0x2b5e
+-#define mmDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX 2
+-#define mmDC_PERFMON10_PERFCOUNTER_CNTL2 0x2b5f
+-#define mmDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX 2
+-#define mmDC_PERFMON10_PERFCOUNTER_STATE 0x2b60
+-#define mmDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX 2
+-#define mmDC_PERFMON10_PERFMON_CNTL 0x2b61
+-#define mmDC_PERFMON10_PERFMON_CNTL_BASE_IDX 2
+-#define mmDC_PERFMON10_PERFMON_CNTL2 0x2b62
+-#define mmDC_PERFMON10_PERFMON_CNTL2_BASE_IDX 2
+-#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x2b63
+-#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+-#define mmDC_PERFMON10_PERFMON_CVALUE_LOW 0x2b64
+-#define mmDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX 2
+-#define mmDC_PERFMON10_PERFMON_HI 0x2b65
+-#define mmDC_PERFMON10_PERFMON_HI_BASE_IDX 2
+-#define mmDC_PERFMON10_PERFMON_LOW 0x2b66
+-#define mmDC_PERFMON10_PERFMON_LOW_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dc_zcalregs_dispdec
+-// base address: 0x0
+-#define mmCOMP_EN_CTL 0x2d96
+-#define mmCOMP_EN_CTL_BASE_IDX 2
+-#define mmCOMP_EN_DFX 0x2d97
+-#define mmCOMP_EN_DFX_BASE_IDX 2
+-#define mmZCAL_FUSES 0x2d98
+-#define mmZCAL_FUSES_BASE_IDX 2
+-
+-
+-// addressBlock: dce_dc_dispdec_VGA_MEM_WRITE_PAGE_ADDR
+-// base address: 0x48
+-//#define mmVGA_dispdec_VGA_MEM_WRITE_PAGE_ADDR 0x0012
+-
+-
+-// addressBlock: dce_dc_dispdec_VGA_MEM_READ_PAGE_ADDR
+-// base address: 0x4c
+-//#define mmVGA_dispdec_VGA_MEM_READ_PAGE_ADDR 0x0014
+-
+-
+-// addressBlock: dce_dc_dispdec[948..986]
+-// base address: 0x3b4
+-//#define mmVGA_CRTC8_IDX 0x002d
+-//#define mmVGA_CRTC8_DATA 0x002d
+-//#define mmVGA_GENFC_WT 0x002e
+-//#define mmVGA_GENS1 0x002e
+-//#define mmVGA_ATTRDW 0x0030
+-//#define mmVGA_ATTRX 0x0030
+-//#define mmVGA_ATTRDR 0x0030
+-//#define mmVGA_GENMO_WT 0x0030
+-//#define mmVGA_GENS0 0x0030
+-//#define mmVGA_GENENB 0x0030
+-//#define mmVGA_SEQ8_IDX 0x0031
+-//#define mmVGA_SEQ8_DATA 0x0031
+-//#define mmVGA_DAC_MASK 0x0031
+-//#define mmVGA_DAC_R_INDEX 0x0031
+-//#define mmVGA_DAC_W_INDEX 0x0032
+-//#define mmVGA_DAC_DATA 0x0032
+-//#define mmVGA_GENFC_RD 0x0032
+-//#define mmVGA_GENMO_RD 0x0033
+-//#define mmVGA_GRPH8_IDX 0x0033
+-//#define mmVGA_GRPH8_DATA 0x0033
+-//#define mmVGA_CRTC8_IDX_1 0x0035
+-//#define mmVGA_CRTC8_DATA_1 0x0035
+-//#define mmVGA_GENFC_WT_1 0x0036
+-//#define mmVGA_GENS1_1 0x0036
+-
+-
+-// addressBlock: dce_dc_azdec
+-// base address: 0x0
+-#define mmCORB_WRITE_POINTER 0x0000
+-#define mmCORB_WRITE_POINTER_BASE_IDX 0
+-#define mmCORB_READ_POINTER 0x0000
+-#define mmCORB_READ_POINTER_BASE_IDX 0
+-#define mmCORB_CONTROL 0x0001
+-#define mmCORB_CONTROL_BASE_IDX 0
+-#define mmCORB_STATUS 0x0001
+-#define mmCORB_STATUS_BASE_IDX 0
+-#define mmCORB_SIZE 0x0001
+-#define mmCORB_SIZE_BASE_IDX 0
+-#define mmRIRB_LOWER_BASE_ADDRESS 0x0002
+-#define mmRIRB_LOWER_BASE_ADDRESS_BASE_IDX 0
+-#define mmRIRB_UPPER_BASE_ADDRESS 0x0003
+-#define mmRIRB_UPPER_BASE_ADDRESS_BASE_IDX 0
+-#define mmRIRB_WRITE_POINTER 0x0004
+-#define mmRIRB_WRITE_POINTER_BASE_IDX 0
+-#define mmRESPONSE_INTERRUPT_COUNT 0x0004
+-#define mmRESPONSE_INTERRUPT_COUNT_BASE_IDX 0
+-#define mmRIRB_CONTROL 0x0005
+-#define mmRIRB_CONTROL_BASE_IDX 0
+-#define mmRIRB_STATUS 0x0005
+-#define mmRIRB_STATUS_BASE_IDX 0
+-#define mmRIRB_SIZE 0x0005
+-#define mmRIRB_SIZE_BASE_IDX 0
+-#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x0006
+-#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 0
+-#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x0006
+-#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 0
+-#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
+-#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
+-#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
+-#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
+-#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
+-#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
+-#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
+-#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
+-#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006
+-#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0
+-#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
+-#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
+-#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
+-#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
+-#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007
+-#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0
+-#define mmIMMEDIATE_COMMAND_STATUS 0x0008
+-#define mmIMMEDIATE_COMMAND_STATUS_BASE_IDX 0
+-#define mmDMA_POSITION_LOWER_BASE_ADDRESS 0x000a
+-#define mmDMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0
+-#define mmDMA_POSITION_UPPER_BASE_ADDRESS 0x000b
+-#define mmDMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0
+-#define mmWALL_CLOCK_COUNTER_ALIAS 0x074c
+-#define mmWALL_CLOCK_COUNTER_ALIAS_BASE_IDX 1
+-
+-
+-// addressBlock: dce_dc_azstream0_azdec
+-// base address: 0x0
+-#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x000e
+-#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
+-#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x000f
+-#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
+-#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0010
+-#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
+-#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0011
+-#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
+-#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0012
+-#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
+-#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0012
+-#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
+-#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0014
+-#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
+-#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0015
+-#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
+-#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0761
+-#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
+-
+-
+-// addressBlock: dce_dc_azstream1_azdec
+-// base address: 0x20
+-#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0016
+-#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
+-#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0017
+-#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
+-#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0018
+-#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
+-#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0019
+-#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
+-#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x001a
+-#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
+-#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x001a
+-#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
+-#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x001c
+-#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
+-#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x001d
+-#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
+-#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0769
+-#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
+-
+-
+-// addressBlock: dce_dc_azstream2_azdec
+-// base address: 0x40
+-#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x001e
+-#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
+-#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x001f
+-#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
+-#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0020
+-#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
+-#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0021
+-#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
+-#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0022
+-#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
+-#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0022
+-#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
+-#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0024
+-#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
+-#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0025
+-#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
+-#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0771
+-#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
+-
+-
+-// addressBlock: dce_dc_azstream3_azdec
+-// base address: 0x60
+-#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0026
+-#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
+-#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0027
+-#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
+-#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0028
+-#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
+-#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0029
+-#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
+-#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x002a
+-#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
+-#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x002a
+-#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
+-#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x002c
+-#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
+-#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x002d
+-#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
+-#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0779
+-#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
+-
+-
+-// addressBlock: dce_dc_azstream4_azdec
+-// base address: 0x80
+-#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x002e
+-#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
+-#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x002f
+-#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
+-#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0030
+-#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
+-#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0031
+-#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
+-#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0032
+-#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
+-#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0032
+-#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
+-#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0034
+-#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
+-#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0035
+-#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
+-#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0781
+-#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
+-
+-
+-// addressBlock: dce_dc_azstream5_azdec
+-// base address: 0xa0
+-#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0036
+-#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
+-#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0037
+-#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
+-#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0038
+-#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
+-#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0039
+-#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
+-#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x003a
+-#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
+-#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x003a
+-#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
+-#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x003c
+-#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
+-#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x003d
+-#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
+-#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0789
+-#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
+-
+-
+-// addressBlock: dce_dc_azstream6_azdec
+-// base address: 0xc0
+-#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x003e
+-#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
+-#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x003f
+-#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
+-#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0040
+-#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
+-#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0041
+-#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
+-#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0042
+-#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
+-#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0042
+-#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
+-#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0044
+-#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
+-#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0045
+-#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
+-#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0791
+-#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
+-
+-
+-// addressBlock: dce_dc_azstream7_azdec
+-// base address: 0xe0
+-#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0046
+-#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
+-#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0047
+-#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
+-#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0048
+-#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
+-#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0049
+-#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
+-#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x004a
+-#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
+-#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x004a
+-#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
+-#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x004c
+-#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
+-#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x004d
+-#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
+-#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0799
+-#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
+-
+-
+-// addressBlock: azf0stream0_streamind
+-// base address: 0x0
+-#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 0x0000
+-#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+-#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+-#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+-#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+-
+-
+-// addressBlock: azf0stream1_streamind
+-// base address: 0x0
+-#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 0x0000
+-#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+-#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+-#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+-#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+-
+-
+-// addressBlock: azf0stream2_streamind
+-// base address: 0x0
+-#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 0x0000
+-#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+-#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+-#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+-#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+-
+-
+-// addressBlock: azf0stream3_streamind
+-// base address: 0x0
+-#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 0x0000
+-#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+-#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+-#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+-#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+-
+-
+-// addressBlock: azf0stream4_streamind
+-// base address: 0x0
+-#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 0x0000
+-#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+-#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+-#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+-#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+-
+-
+-// addressBlock: azf0stream5_streamind
+-// base address: 0x0
+-#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 0x0000
+-#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+-#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+-#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+-#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+-
+-
+-// addressBlock: azf0stream6_streamind
+-// base address: 0x0
+-#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 0x0000
+-#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+-#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+-#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+-#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+-
+-
+-// addressBlock: azf0stream7_streamind
+-// base address: 0x0
+-#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 0x0000
+-#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+-#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+-#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+-#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+-
+-
+-// addressBlock: azf0stream8_streamind
+-// base address: 0x0
+-#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 0x0000
+-#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+-#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+-#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+-#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+-
+-
+-// addressBlock: azf0stream9_streamind
+-// base address: 0x0
+-#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 0x0000
+-#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+-#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+-#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+-#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+-
+-
+-// addressBlock: azf0stream10_streamind
+-// base address: 0x0
+-#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 0x0000
+-#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+-#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+-#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+-#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+-
+-
+-// addressBlock: azf0stream11_streamind
+-// base address: 0x0
+-#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 0x0000
+-#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+-#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+-#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+-#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+-
+-
+-// addressBlock: azf0stream12_streamind
+-// base address: 0x0
+-#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 0x0000
+-#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+-#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+-#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+-#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+-
+-
+-// addressBlock: azf0stream13_streamind
+-// base address: 0x0
+-#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 0x0000
+-#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+-#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+-#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+-#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+-
+-
+-// addressBlock: azf0stream14_streamind
+-// base address: 0x0
+-#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 0x0000
+-#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+-#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+-#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+-#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+-
+-
+-// addressBlock: azf0stream15_streamind
+-// base address: 0x0
+-#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 0x0000
+-#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+-#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+-#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+-#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+-
+-
+-// addressBlock: azf0endpoint0_endpointind
+-// base address: 0x0
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
+-#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
+-#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
+-#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
+-#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
+-#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
+-#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
+-#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
+-#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
+-#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
+-#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
+-#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
+-#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
+-#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
+-#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
+-
+-
+-// addressBlock: azf0endpoint1_endpointind
+-// base address: 0x0
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
+-#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
+-#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
+-#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
+-#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
+-#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
+-#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
+-#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
+-#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
+-#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
+-#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
+-#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
+-#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
+-#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
+-#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
+-
+-
+-// addressBlock: azf0endpoint2_endpointind
+-// base address: 0x0
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
+-#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
+-#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
+-#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
+-#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
+-#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
+-#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
+-#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
+-#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
+-#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
+-#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
+-#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
+-#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
+-#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
+-#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
+-
+-
+-// addressBlock: azf0endpoint3_endpointind
+-// base address: 0x0
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
+-#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
+-#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
+-#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
+-#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
+-#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
+-#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
+-#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
+-#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
+-#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
+-#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
+-#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
+-#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
+-#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
+-#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
+-
+-
+-// addressBlock: azf0endpoint4_endpointind
+-// base address: 0x0
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
+-#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
+-#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
+-#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
+-#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
+-#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
+-#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
+-#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
+-#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
+-#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
+-#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
+-#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
+-#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
+-#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
+-#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
+-
+-
+-// addressBlock: azf0endpoint5_endpointind
+-// base address: 0x0
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
+-#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
+-#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
+-#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
+-#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
+-#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
+-#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
+-#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
+-#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
+-#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
+-#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
+-#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
+-#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
+-#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
+-#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
+-
+-
+-// addressBlock: azf0endpoint6_endpointind
+-// base address: 0x0
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
+-#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
+-#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
+-#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
+-#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
+-#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
+-#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
+-#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
+-#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
+-#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
+-#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
+-#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
+-#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
+-#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
+-#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
+-
+-
+-// addressBlock: azf0endpoint7_endpointind
+-// base address: 0x0
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
+-#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
+-#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
+-#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
+-#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
+-#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
+-#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
+-#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
+-#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
+-#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
+-#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
+-#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
+-#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
+-#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
+-#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
+-
+-
+-// addressBlock: azf0inputendpoint0_inputendpointind
+-// base address: 0x0
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
+-#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
+-
+-
+-// addressBlock: azf0inputendpoint1_inputendpointind
+-// base address: 0x0
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
+-#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
+-
+-
+-// addressBlock: azf0inputendpoint2_inputendpointind
+-// base address: 0x0
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
+-#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
+-
+-
+-// addressBlock: azf0inputendpoint3_inputendpointind
+-// base address: 0x0
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
+-#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
+-
+-
+-// addressBlock: azf0inputendpoint4_inputendpointind
+-// base address: 0x0
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
+-#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
+-
+-
+-// addressBlock: azf0inputendpoint5_inputendpointind
+-// base address: 0x0
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
+-#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
+-
+-
+-// addressBlock: azf0inputendpoint6_inputendpointind
+-// base address: 0x0
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
+-#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
+-
+-
+-// addressBlock: azf0inputendpoint7_inputendpointind
+-// base address: 0x0
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
+-#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
+-
+-
+-// addressBlock: f2codecind
+-// base address: 0x0
+-#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0f00
+-#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0f02
+-#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0f04
+-#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705
+-#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720
+-#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721
+-#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722
+-#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723
+-#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770
+-#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff
+-#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04
+-#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05
+-#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a
+-#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b
+-#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f
+-#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200
+-#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706
+-#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d
+-#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e
+-#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724
+-#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e
+-#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770
+-#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771
+-#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09
+-#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a
+-#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789
+-#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a
+-#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b
+-#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c
+-#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d
+-#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e
+-#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f
+-#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790
+-#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791
+-#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792
+-#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e
+-#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09
+-#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c
+-#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e
+-#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200
+-#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706
+-#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d
+-#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09
+-#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a
+-#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09
+-#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c
+-
+-
+-// addressBlock: descriptorind
+-// base address: 0x0
+-#define ixAUDIO_DESCRIPTOR0 0x0001
+-#define ixAUDIO_DESCRIPTOR1 0x0002
+-#define ixAUDIO_DESCRIPTOR2 0x0003
+-#define ixAUDIO_DESCRIPTOR3 0x0004
+-#define ixAUDIO_DESCRIPTOR4 0x0005
+-#define ixAUDIO_DESCRIPTOR5 0x0006
+-#define ixAUDIO_DESCRIPTOR6 0x0007
+-#define ixAUDIO_DESCRIPTOR7 0x0008
+-#define ixAUDIO_DESCRIPTOR8 0x0009
+-#define ixAUDIO_DESCRIPTOR9 0x000a
+-#define ixAUDIO_DESCRIPTOR10 0x000b
+-#define ixAUDIO_DESCRIPTOR11 0x000c
+-#define ixAUDIO_DESCRIPTOR12 0x000d
+-#define ixAUDIO_DESCRIPTOR13 0x000e
+-
+-
+-// addressBlock: sinkinfoind
+-// base address: 0x0
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003
+-#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004
+-#define ixSINK_DESCRIPTION0 0x0005
+-#define ixSINK_DESCRIPTION1 0x0006
+-#define ixSINK_DESCRIPTION2 0x0007
+-#define ixSINK_DESCRIPTION3 0x0008
+-#define ixSINK_DESCRIPTION4 0x0009
+-#define ixSINK_DESCRIPTION5 0x000a
+-#define ixSINK_DESCRIPTION6 0x000b
+-#define ixSINK_DESCRIPTION7 0x000c
+-#define ixSINK_DESCRIPTION8 0x000d
+-#define ixSINK_DESCRIPTION9 0x000e
+-#define ixSINK_DESCRIPTION10 0x000f
+-#define ixSINK_DESCRIPTION11 0x0010
+-#define ixSINK_DESCRIPTION12 0x0011
+-#define ixSINK_DESCRIPTION13 0x0012
+-#define ixSINK_DESCRIPTION14 0x0013
+-#define ixSINK_DESCRIPTION15 0x0014
+-#define ixSINK_DESCRIPTION16 0x0015
+-#define ixSINK_DESCRIPTION17 0x0016
+-
+-
+-// addressBlock: azinputcrc0resultind
+-// base address: 0x0
+-#define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0000
+-#define ixAZALIA_INPUT_CRC0_CHANNEL1 0x0001
+-#define ixAZALIA_INPUT_CRC0_CHANNEL2 0x0002
+-#define ixAZALIA_INPUT_CRC0_CHANNEL3 0x0003
+-#define ixAZALIA_INPUT_CRC0_CHANNEL4 0x0004
+-#define ixAZALIA_INPUT_CRC0_CHANNEL5 0x0005
+-#define ixAZALIA_INPUT_CRC0_CHANNEL6 0x0006
+-#define ixAZALIA_INPUT_CRC0_CHANNEL7 0x0007
+-
+-
+-// addressBlock: azinputcrc1resultind
+-// base address: 0x0
+-#define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0000
+-#define ixAZALIA_INPUT_CRC1_CHANNEL1 0x0001
+-#define ixAZALIA_INPUT_CRC1_CHANNEL2 0x0002
+-#define ixAZALIA_INPUT_CRC1_CHANNEL3 0x0003
+-#define ixAZALIA_INPUT_CRC1_CHANNEL4 0x0004
+-#define ixAZALIA_INPUT_CRC1_CHANNEL5 0x0005
+-#define ixAZALIA_INPUT_CRC1_CHANNEL6 0x0006
+-#define ixAZALIA_INPUT_CRC1_CHANNEL7 0x0007
+-
+-
+-// addressBlock: azcrc0resultind
+-// base address: 0x0
+-#define ixAZALIA_CRC0_CHANNEL0 0x0000
+-#define ixAZALIA_CRC0_CHANNEL1 0x0001
+-#define ixAZALIA_CRC0_CHANNEL2 0x0002
+-#define ixAZALIA_CRC0_CHANNEL3 0x0003
+-#define ixAZALIA_CRC0_CHANNEL4 0x0004
+-#define ixAZALIA_CRC0_CHANNEL5 0x0005
+-#define ixAZALIA_CRC0_CHANNEL6 0x0006
+-#define ixAZALIA_CRC0_CHANNEL7 0x0007
+-
+-
+-// addressBlock: azcrc1resultind
+-// base address: 0x0
+-#define ixAZALIA_CRC1_CHANNEL0 0x0000
+-#define ixAZALIA_CRC1_CHANNEL1 0x0001
+-#define ixAZALIA_CRC1_CHANNEL2 0x0002
+-#define ixAZALIA_CRC1_CHANNEL3 0x0003
+-#define ixAZALIA_CRC1_CHANNEL4 0x0004
+-#define ixAZALIA_CRC1_CHANNEL5 0x0005
+-#define ixAZALIA_CRC1_CHANNEL6 0x0006
+-#define ixAZALIA_CRC1_CHANNEL7 0x0007
+-
+-
+-// addressBlock: vgaseqind
+-// base address: 0x0
+-#define ixSEQ00 0x0000
+-#define ixSEQ01 0x0001
+-#define ixSEQ02 0x0002
+-#define ixSEQ03 0x0003
+-#define ixSEQ04 0x0004
+-
+-
+-// addressBlock: vgacrtind
+-// base address: 0x0
+-#define ixCRT00 0x0000
+-#define ixCRT01 0x0001
+-#define ixCRT02 0x0002
+-#define ixCRT03 0x0003
+-#define ixCRT04 0x0004
+-#define ixCRT05 0x0005
+-#define ixCRT06 0x0006
+-#define ixCRT07 0x0007
+-#define ixCRT08 0x0008
+-#define ixCRT09 0x0009
+-#define ixCRT0A 0x000a
+-#define ixCRT0B 0x000b
+-#define ixCRT0C 0x000c
+-#define ixCRT0D 0x000d
+-#define ixCRT0E 0x000e
+-#define ixCRT0F 0x000f
+-#define ixCRT10 0x0010
+-#define ixCRT11 0x0011
+-#define ixCRT12 0x0012
+-#define ixCRT13 0x0013
+-#define ixCRT14 0x0014
+-#define ixCRT15 0x0015
+-#define ixCRT16 0x0016
+-#define ixCRT17 0x0017
+-#define ixCRT18 0x0018
+-#define ixCRT1E 0x001e
+-#define ixCRT1F 0x001f
+-#define ixCRT22 0x0022
+-
+-
+-// addressBlock: vgagrphind
+-// base address: 0x0
+-#define ixGRA00 0x0000
+-#define ixGRA01 0x0001
+-#define ixGRA02 0x0002
+-#define ixGRA03 0x0003
+-#define ixGRA04 0x0004
+-#define ixGRA05 0x0005
+-#define ixGRA06 0x0006
+-#define ixGRA07 0x0007
+-#define ixGRA08 0x0008
+-
+-
+-// addressBlock: vgaattrind
+-// base address: 0x0
+-#define ixATTR00 0x0000
+-#define ixATTR01 0x0001
+-#define ixATTR02 0x0002
+-#define ixATTR03 0x0003
+-#define ixATTR04 0x0004
+-#define ixATTR05 0x0005
+-#define ixATTR06 0x0006
+-#define ixATTR07 0x0007
+-#define ixATTR08 0x0008
+-#define ixATTR09 0x0009
+-#define ixATTR0A 0x000a
+-#define ixATTR0B 0x000b
+-#define ixATTR0C 0x000c
+-#define ixATTR0D 0x000d
+-#define ixATTR0E 0x000e
+-#define ixATTR0F 0x000f
+-#define ixATTR10 0x0010
+-#define ixATTR11 0x0011
+-#define ixATTR12 0x0012
+-#define ixATTR13 0x0013
+-#define ixATTR14 0x0014
+-
+-
+-#endif
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_sh_mask.h
+deleted file mode 100644
+index d8ad862..0000000
+--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_sh_mask.h
++++ /dev/null
+@@ -1,64636 +0,0 @@
+-/*
+- * Copyright (C) 2017 Advanced Micro Devices, Inc.
+- *
+- * Permission is hereby granted, free of charge, to any person obtaining a
+- * copy of this software and associated documentation files (the "Software"),
+- * to deal in the Software without restriction, including without limitation
+- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+- * and/or sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following conditions:
+- *
+- * The above copyright notice and this permission notice shall be included
+- * in all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+- */
+-#ifndef _dce_12_0_SH_MASK_HEADER
+-#define _dce_12_0_SH_MASK_HEADER
+-
+-
+-// addressBlock: dce_dc_dispdec_VGA_MEM_WRITE_PAGE_ADDR
+-//dispdec_VGA_MEM_WRITE_PAGE_ADDR
+-#define dispdec_VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0
+-#define dispdec_VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10
+-#define dispdec_VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x000003FFL
+-#define dispdec_VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x03FF0000L
+-
+-
+-// addressBlock: dce_dc_dispdec_VGA_MEM_READ_PAGE_ADDR
+-//dispdec_VGA_MEM_READ_PAGE_ADDR
+-#define dispdec_VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0
+-#define dispdec_VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10
+-#define dispdec_VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x000003FFL
+-#define dispdec_VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x03FF0000L
+-
+-
+-// addressBlock: dce_dc_dc_perfmon0_dispdec
+-//DC_PERFMON0_PERFCOUNTER_CNTL
+-#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+-#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+-#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+-#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+-#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+-#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
+-#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+-#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+-#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+-#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+-#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+-#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
+-#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+-#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+-#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+-#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+-#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+-#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+-#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
+-#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+-#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+-#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+-#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+-#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+-#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
+-#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+-//DC_PERFMON0_PERFCOUNTER_CNTL2
+-#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+-#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+-#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+-#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+-#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+-#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+-#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+-#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+-//DC_PERFMON0_PERFCOUNTER_STATE
+-#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+-#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+-#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+-#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+-#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+-#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+-#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+-#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+-#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+-#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+-#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+-#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+-#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+-#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+-#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+-#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+-#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+-#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+-#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+-#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+-#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+-#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+-#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+-#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+-#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+-#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+-#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+-#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+-#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+-#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+-#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+-#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+-//DC_PERFMON0_PERFMON_CNTL
+-#define DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+-#define DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+-#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+-#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+-#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+-#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+-#define DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+-#define DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+-#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+-#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+-#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+-#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+-//DC_PERFMON0_PERFMON_CNTL2
+-#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+-#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+-#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+-#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+-#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+-#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+-#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+-#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+-//DC_PERFMON0_PERFMON_CVALUE_INT_MISC
+-#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+-#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+-#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+-#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+-#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+-#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+-#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+-#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+-#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+-#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+-#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+-#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+-#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+-#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+-#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+-#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+-#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+-#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+-#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+-#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+-#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+-#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+-#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+-#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+-#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+-#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+-#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+-#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+-#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+-#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+-#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+-#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+-#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+-#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+-//DC_PERFMON0_PERFMON_CVALUE_LOW
+-#define DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+-#define DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+-//DC_PERFMON0_PERFMON_HI
+-#define DC_PERFMON0_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+-#define DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+-#define DC_PERFMON0_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+-#define DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+-//DC_PERFMON0_PERFMON_LOW
+-#define DC_PERFMON0_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+-#define DC_PERFMON0_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dc_perfmon13_dispdec
+-//DC_PERFMON13_PERFCOUNTER_CNTL
+-#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+-#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+-#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+-#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+-#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+-#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
+-#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+-#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+-#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+-#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+-#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+-#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
+-#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+-#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+-#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+-#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+-#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+-#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+-#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
+-#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+-#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+-#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+-#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+-#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+-#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
+-#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+-//DC_PERFMON13_PERFCOUNTER_CNTL2
+-#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+-#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+-#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+-#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+-#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+-#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+-#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+-#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+-//DC_PERFMON13_PERFCOUNTER_STATE
+-#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+-#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+-#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+-#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+-#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+-#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+-#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+-#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+-#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+-#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+-#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+-#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+-#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+-#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+-#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+-#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+-#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+-#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+-#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+-#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+-#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+-#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+-#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+-#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+-#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+-#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+-#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+-#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+-#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+-#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+-#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+-#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+-//DC_PERFMON13_PERFMON_CNTL
+-#define DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+-#define DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+-#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+-#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+-#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+-#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+-#define DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+-#define DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+-#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+-#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+-#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+-#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+-//DC_PERFMON13_PERFMON_CNTL2
+-#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+-#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+-#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+-#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+-#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+-#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+-#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+-#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+-//DC_PERFMON13_PERFMON_CVALUE_INT_MISC
+-#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+-#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+-#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+-#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+-#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+-#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+-#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+-#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+-#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+-#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+-#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+-#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+-#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+-#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+-#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+-#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+-#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+-#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+-#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+-#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+-#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+-#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+-#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+-#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+-#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+-#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+-#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+-#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+-#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+-#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+-#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+-#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+-#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+-#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+-//DC_PERFMON13_PERFMON_CVALUE_LOW
+-#define DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+-#define DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+-//DC_PERFMON13_PERFMON_HI
+-#define DC_PERFMON13_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+-#define DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+-#define DC_PERFMON13_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+-#define DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+-//DC_PERFMON13_PERFMON_LOW
+-#define DC_PERFMON13_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+-#define DC_PERFMON13_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dc_displaypllregs_dispdec
+-//PPLL_VREG_CFG
+-#define PPLL_VREG_CFG__pw_pc_bleeder_ac__SHIFT 0x0
+-#define PPLL_VREG_CFG__pw_pc_bleeder_en__SHIFT 0x1
+-#define PPLL_VREG_CFG__pw_pc_is_1p2__SHIFT 0x2
+-#define PPLL_VREG_CFG__pw_pc_reg_obs_sel__SHIFT 0x3
+-#define PPLL_VREG_CFG__pw_pc_reg_on_mode__SHIFT 0x5
+-#define PPLL_VREG_CFG__pw_pc_rlad_tap_sel__SHIFT 0x7
+-#define PPLL_VREG_CFG__pw_pc_reg_off_hi__SHIFT 0xb
+-#define PPLL_VREG_CFG__pw_pc_reg_off_lo__SHIFT 0xc
+-#define PPLL_VREG_CFG__pw_pc_scale_driver__SHIFT 0xd
+-#define PPLL_VREG_CFG__pw_pc_sel_bump__SHIFT 0xf
+-#define PPLL_VREG_CFG__pw_pc_sel_rladder_x__SHIFT 0x10
+-#define PPLL_VREG_CFG__pw_pc_short_rc_filt_x__SHIFT 0x11
+-#define PPLL_VREG_CFG__pw_pc_vref_pwr_on__SHIFT 0x12
+-#define PPLL_VREG_CFG__pw_pc_dpll_cfg_2__SHIFT 0x14
+-#define PPLL_VREG_CFG__pw_pc_bleeder_ac_MASK 0x00000001L
+-#define PPLL_VREG_CFG__pw_pc_bleeder_en_MASK 0x00000002L
+-#define PPLL_VREG_CFG__pw_pc_is_1p2_MASK 0x00000004L
+-#define PPLL_VREG_CFG__pw_pc_reg_obs_sel_MASK 0x00000018L
+-#define PPLL_VREG_CFG__pw_pc_reg_on_mode_MASK 0x00000060L
+-#define PPLL_VREG_CFG__pw_pc_rlad_tap_sel_MASK 0x00000780L
+-#define PPLL_VREG_CFG__pw_pc_reg_off_hi_MASK 0x00000800L
+-#define PPLL_VREG_CFG__pw_pc_reg_off_lo_MASK 0x00001000L
+-#define PPLL_VREG_CFG__pw_pc_scale_driver_MASK 0x00006000L
+-#define PPLL_VREG_CFG__pw_pc_sel_bump_MASK 0x00008000L
+-#define PPLL_VREG_CFG__pw_pc_sel_rladder_x_MASK 0x00010000L
+-#define PPLL_VREG_CFG__pw_pc_short_rc_filt_x_MASK 0x00020000L
+-#define PPLL_VREG_CFG__pw_pc_vref_pwr_on_MASK 0x00040000L
+-#define PPLL_VREG_CFG__pw_pc_dpll_cfg_2_MASK 0x0FF00000L
+-//PPLL_MODE_CNTL
+-#define PPLL_MODE_CNTL__pw_pc_refclk_gate_dis__SHIFT 0x0
+-#define PPLL_MODE_CNTL__pw_pc_multi_phase_en__SHIFT 0x8
+-#define PPLL_MODE_CNTL__reg_tmg_pwr_state__SHIFT 0x10
+-#define PPLL_MODE_CNTL__pw_pc_refclk_gate_dis_MASK 0x00000001L
+-#define PPLL_MODE_CNTL__pw_pc_multi_phase_en_MASK 0x00000F00L
+-#define PPLL_MODE_CNTL__reg_tmg_pwr_state_MASK 0x00030000L
+-//PPLL_FREQ_CTRL0
+-#define PPLL_FREQ_CTRL0__reg_tmg_fcw0_frac__SHIFT 0x0
+-#define PPLL_FREQ_CTRL0__reg_tmg_fcw0_int__SHIFT 0x10
+-#define PPLL_FREQ_CTRL0__reg_tmg_fcw0_frac_MASK 0x0000FFFFL
+-#define PPLL_FREQ_CTRL0__reg_tmg_fcw0_int_MASK 0x01FF0000L
+-//PPLL_FREQ_CTRL1
+-#define PPLL_FREQ_CTRL1__reg_tmg_fcw1_frac__SHIFT 0x0
+-#define PPLL_FREQ_CTRL1__reg_tmg_fcw1_int__SHIFT 0x10
+-#define PPLL_FREQ_CTRL1__reg_tmg_fcw1_frac_MASK 0x0000FFFFL
+-#define PPLL_FREQ_CTRL1__reg_tmg_fcw1_int_MASK 0x01FF0000L
+-//PPLL_FREQ_CTRL2
+-#define PPLL_FREQ_CTRL2__reg_tmg_fcw_denom__SHIFT 0x0
+-#define PPLL_FREQ_CTRL2__reg_tmg_fcw_slew_frac__SHIFT 0x10
+-#define PPLL_FREQ_CTRL2__reg_tmg_fcw_denom_MASK 0x0000FFFFL
+-#define PPLL_FREQ_CTRL2__reg_tmg_fcw_slew_frac_MASK 0xFFFF0000L
+-//PPLL_FREQ_CTRL3
+-#define PPLL_FREQ_CTRL3__reg_tmg_refclk_div__SHIFT 0x0
+-#define PPLL_FREQ_CTRL3__reg_tmg_vco_pre_div__SHIFT 0x3
+-#define PPLL_FREQ_CTRL3__reg_tmg_fracn_en__SHIFT 0x6
+-#define PPLL_FREQ_CTRL3__reg_tmg_ssc_en__SHIFT 0x8
+-#define PPLL_FREQ_CTRL3__reg_tmg_fcw_sel__SHIFT 0xa
+-#define PPLL_FREQ_CTRL3__reg_tmg_freq_jump_en__SHIFT 0xc
+-#define PPLL_FREQ_CTRL3__reg_tmg_tdc_resol__SHIFT 0x10
+-#define PPLL_FREQ_CTRL3__pw_pc_dpll_cfg_1__SHIFT 0x18
+-#define PPLL_FREQ_CTRL3__reg_tmg_refclk_div_MASK 0x00000003L
+-#define PPLL_FREQ_CTRL3__reg_tmg_vco_pre_div_MASK 0x00000018L
+-#define PPLL_FREQ_CTRL3__reg_tmg_fracn_en_MASK 0x00000040L
+-#define PPLL_FREQ_CTRL3__reg_tmg_ssc_en_MASK 0x00000100L
+-#define PPLL_FREQ_CTRL3__reg_tmg_fcw_sel_MASK 0x00000400L
+-#define PPLL_FREQ_CTRL3__reg_tmg_freq_jump_en_MASK 0x00001000L
+-#define PPLL_FREQ_CTRL3__reg_tmg_tdc_resol_MASK 0x00FF0000L
+-#define PPLL_FREQ_CTRL3__pw_pc_dpll_cfg_1_MASK 0xFF000000L
+-//PPLL_BW_CTRL_COARSE
+-#define PPLL_BW_CTRL_COARSE__reg_tmg_gi_crse_mant__SHIFT 0x0
+-#define PPLL_BW_CTRL_COARSE__reg_tmg_gi_crse_exp__SHIFT 0x2
+-#define PPLL_BW_CTRL_COARSE__reg_tmg_gp_crse_mant__SHIFT 0x7
+-#define PPLL_BW_CTRL_COARSE__reg_tmg_gp_crse_exp__SHIFT 0xc
+-#define PPLL_BW_CTRL_COARSE__reg_tmg_nctl_crse_res__SHIFT 0x11
+-#define PPLL_BW_CTRL_COARSE__reg_tmg_nctl_crse_frac_res__SHIFT 0x18
+-#define PPLL_BW_CTRL_COARSE__reg_tmg_gi_crse_mant_MASK 0x00000003L
+-#define PPLL_BW_CTRL_COARSE__reg_tmg_gi_crse_exp_MASK 0x0000003CL
+-#define PPLL_BW_CTRL_COARSE__reg_tmg_gp_crse_mant_MASK 0x00000780L
+-#define PPLL_BW_CTRL_COARSE__reg_tmg_gp_crse_exp_MASK 0x0000F000L
+-#define PPLL_BW_CTRL_COARSE__reg_tmg_nctl_crse_res_MASK 0x007E0000L
+-#define PPLL_BW_CTRL_COARSE__reg_tmg_nctl_crse_frac_res_MASK 0x03000000L
+-//PPLL_BW_CTRL_FINE
+-#define PPLL_BW_CTRL_FINE__pw_pc_dpll_cfg_3__SHIFT 0x0
+-#define PPLL_BW_CTRL_FINE__pw_pc_dpll_cfg_3_MASK 0x000003FFL
+-//PPLL_CAL_CTRL
+-#define PPLL_CAL_CTRL__pw_pc_bypass_freq_lock__SHIFT 0x0
+-#define PPLL_CAL_CTRL__pw_pc_tdc_cal_en__SHIFT 0x1
+-#define PPLL_CAL_CTRL__pw_pc_tdc_cal_ctrl__SHIFT 0x3
+-#define PPLL_CAL_CTRL__pw_pc_meas_win_sel__SHIFT 0x9
+-#define PPLL_CAL_CTRL__pw_pc_kdco_cal_dis__SHIFT 0xb
+-#define PPLL_CAL_CTRL__pw_pc_kdco_ratio__SHIFT 0xd
+-#define PPLL_CAL_CTRL__pw_pc_kdco_incr_cal_dis__SHIFT 0x16
+-#define PPLL_CAL_CTRL__pw_pc_nctl_adj_dis__SHIFT 0x17
+-#define PPLL_CAL_CTRL__pw_pc_refclk_rate__SHIFT 0x18
+-#define PPLL_CAL_CTRL__pw_pc_bypass_freq_lock_MASK 0x00000001L
+-#define PPLL_CAL_CTRL__pw_pc_tdc_cal_en_MASK 0x00000002L
+-#define PPLL_CAL_CTRL__pw_pc_tdc_cal_ctrl_MASK 0x000001F8L
+-#define PPLL_CAL_CTRL__pw_pc_meas_win_sel_MASK 0x00000600L
+-#define PPLL_CAL_CTRL__pw_pc_kdco_cal_dis_MASK 0x00000800L
+-#define PPLL_CAL_CTRL__pw_pc_kdco_ratio_MASK 0x001FE000L
+-#define PPLL_CAL_CTRL__pw_pc_kdco_incr_cal_dis_MASK 0x00400000L
+-#define PPLL_CAL_CTRL__pw_pc_nctl_adj_dis_MASK 0x00800000L
+-#define PPLL_CAL_CTRL__pw_pc_refclk_rate_MASK 0xFF000000L
+-//PPLL_LOOP_CTRL
+-#define PPLL_LOOP_CTRL__pw_pc_fbdiv_mask_en__SHIFT 0x0
+-#define PPLL_LOOP_CTRL__pw_pc_fb_slip_dis__SHIFT 0x2
+-#define PPLL_LOOP_CTRL__pw_pc_clk_tdc_sel__SHIFT 0x4
+-#define PPLL_LOOP_CTRL__pw_pc_clk_nctl_sel__SHIFT 0x7
+-#define PPLL_LOOP_CTRL__pw_pc_sig_del_patt_sel__SHIFT 0xa
+-#define PPLL_LOOP_CTRL__pw_pc_nctl_sig_del_dis__SHIFT 0xc
+-#define PPLL_LOOP_CTRL__pw_pc_fbclk_track_refclk__SHIFT 0xe
+-#define PPLL_LOOP_CTRL__pw_pc_prbs_en__SHIFT 0x10
+-#define PPLL_LOOP_CTRL__pw_pc_tdc_clk_gate_en__SHIFT 0x12
+-#define PPLL_LOOP_CTRL__pw_pc_phase_offset__SHIFT 0x14
+-#define PPLL_LOOP_CTRL__pw_pc_fbdiv_mask_en_MASK 0x00000001L
+-#define PPLL_LOOP_CTRL__pw_pc_fb_slip_dis_MASK 0x00000004L
+-#define PPLL_LOOP_CTRL__pw_pc_clk_tdc_sel_MASK 0x00000030L
+-#define PPLL_LOOP_CTRL__pw_pc_clk_nctl_sel_MASK 0x00000180L
+-#define PPLL_LOOP_CTRL__pw_pc_sig_del_patt_sel_MASK 0x00000400L
+-#define PPLL_LOOP_CTRL__pw_pc_nctl_sig_del_dis_MASK 0x00001000L
+-#define PPLL_LOOP_CTRL__pw_pc_fbclk_track_refclk_MASK 0x00004000L
+-#define PPLL_LOOP_CTRL__pw_pc_prbs_en_MASK 0x00010000L
+-#define PPLL_LOOP_CTRL__pw_pc_tdc_clk_gate_en_MASK 0x00040000L
+-#define PPLL_LOOP_CTRL__pw_pc_phase_offset_MASK 0x07F00000L
+-//PPLL_REFCLK_CNTL
+-#define PPLL_REFCLK_CNTL__regs_pw_refclk0_recv_en__SHIFT 0x0
+-#define PPLL_REFCLK_CNTL__regs_pw_refclk1_recv_en__SHIFT 0x1
+-#define PPLL_REFCLK_CNTL__regs_pw_refclk2_recv_en__SHIFT 0x2
+-#define PPLL_REFCLK_CNTL__regs_pw_refclk3_recv_en__SHIFT 0x3
+-#define PPLL_REFCLK_CNTL__regs_pw_refclk0_recv_sel__SHIFT 0x8
+-#define PPLL_REFCLK_CNTL__regs_pw_refclk1_recv_sel__SHIFT 0x9
+-#define PPLL_REFCLK_CNTL__regs_pw_refclk2_recv_sel__SHIFT 0xa
+-#define PPLL_REFCLK_CNTL__regs_pw_refclk3_recv_sel__SHIFT 0xb
+-#define PPLL_REFCLK_CNTL__regs_pw_refdivsrc__SHIFT 0xe
+-#define PPLL_REFCLK_CNTL__regs_pw_ref2core_sel__SHIFT 0x10
+-#define PPLL_REFCLK_CNTL__regs_pw_refclk0_recv_en_MASK 0x00000001L
+-#define PPLL_REFCLK_CNTL__regs_pw_refclk1_recv_en_MASK 0x00000002L
+-#define PPLL_REFCLK_CNTL__regs_pw_refclk2_recv_en_MASK 0x00000004L
+-#define PPLL_REFCLK_CNTL__regs_pw_refclk3_recv_en_MASK 0x00000008L
+-#define PPLL_REFCLK_CNTL__regs_pw_refclk0_recv_sel_MASK 0x00000100L
+-#define PPLL_REFCLK_CNTL__regs_pw_refclk1_recv_sel_MASK 0x00000200L
+-#define PPLL_REFCLK_CNTL__regs_pw_refclk2_recv_sel_MASK 0x00000400L
+-#define PPLL_REFCLK_CNTL__regs_pw_refclk3_recv_sel_MASK 0x00000800L
+-#define PPLL_REFCLK_CNTL__regs_pw_refdivsrc_MASK 0x0000C000L
+-#define PPLL_REFCLK_CNTL__regs_pw_ref2core_sel_MASK 0x00010000L
+-//PPLL_CLKOUT_CNTL
+-#define PPLL_CLKOUT_CNTL__regs_pw_pixclk_pre_pdivsel__SHIFT 0x8
+-#define PPLL_CLKOUT_CNTL__regs_pw_pixclk_pdivsel__SHIFT 0x9
+-#define PPLL_CLKOUT_CNTL__regs_pw_dvoclk_pre_pdivsel__SHIFT 0xa
+-#define PPLL_CLKOUT_CNTL__regs_pw_dvoclk_pdivsel__SHIFT 0xb
+-#define PPLL_CLKOUT_CNTL__regs_pw_idclk_en__SHIFT 0xc
+-#define PPLL_CLKOUT_CNTL__regs_pw_idclk_pre_pdivsel__SHIFT 0xd
+-#define PPLL_CLKOUT_CNTL__regs_pw_idclk_pdivsel__SHIFT 0xe
+-#define PPLL_CLKOUT_CNTL__regs_pw_idclk_obs_sel__SHIFT 0xf
+-#define PPLL_CLKOUT_CNTL__regs_pw_refclk_sel__SHIFT 0x10
+-#define PPLL_CLKOUT_CNTL__regs_cc_resetb__SHIFT 0x14
+-#define PPLL_CLKOUT_CNTL__regs_pw_pixclk_pre_pdivsel_MASK 0x00000100L
+-#define PPLL_CLKOUT_CNTL__regs_pw_pixclk_pdivsel_MASK 0x00000200L
+-#define PPLL_CLKOUT_CNTL__regs_pw_dvoclk_pre_pdivsel_MASK 0x00000400L
+-#define PPLL_CLKOUT_CNTL__regs_pw_dvoclk_pdivsel_MASK 0x00000800L
+-#define PPLL_CLKOUT_CNTL__regs_pw_idclk_en_MASK 0x00001000L
+-#define PPLL_CLKOUT_CNTL__regs_pw_idclk_pre_pdivsel_MASK 0x00002000L
+-#define PPLL_CLKOUT_CNTL__regs_pw_idclk_pdivsel_MASK 0x00004000L
+-#define PPLL_CLKOUT_CNTL__regs_pw_idclk_obs_sel_MASK 0x00008000L
+-#define PPLL_CLKOUT_CNTL__regs_pw_refclk_sel_MASK 0x00030000L
+-#define PPLL_CLKOUT_CNTL__regs_cc_resetb_MASK 0x00100000L
+-//PPLL_DFT_CNTL
+-#define PPLL_DFT_CNTL__regs_pw_obs_en__SHIFT 0x0
+-#define PPLL_DFT_CNTL__regs_pw_obs_div_sel_1__SHIFT 0x1
+-#define PPLL_DFT_CNTL__regs_pw_obs_clk_sel_1__SHIFT 0x4
+-#define PPLL_DFT_CNTL__regs_pw_obs_clk_sel_2__SHIFT 0x8
+-#define PPLL_DFT_CNTL__regs_pw_obs_sel__SHIFT 0xc
+-#define PPLL_DFT_CNTL__regs_pw_obs_en_MASK 0x00000001L
+-#define PPLL_DFT_CNTL__regs_pw_obs_div_sel_1_MASK 0x00000006L
+-#define PPLL_DFT_CNTL__regs_pw_obs_clk_sel_1_MASK 0x000000F0L
+-#define PPLL_DFT_CNTL__regs_pw_obs_clk_sel_2_MASK 0x00000F00L
+-#define PPLL_DFT_CNTL__regs_pw_obs_sel_MASK 0x00003000L
+-//PPLL_ANALOG_CNTL
+-#define PPLL_ANALOG_CNTL__regs_pw_spare__SHIFT 0x0
+-#define PPLL_ANALOG_CNTL__regs_pw_spare_MASK 0x000000FFL
+-//PPLL_POSTDIV
+-#define PPLL_POSTDIV__reg_tmg_postdiv__SHIFT 0x8
+-#define PPLL_POSTDIV__reg_tmg_pixclk_pdiv2__SHIFT 0xc
+-#define PPLL_POSTDIV__reg_tmg_postdiv_MASK 0x00000F00L
+-#define PPLL_POSTDIV__reg_tmg_pixclk_pdiv2_MASK 0x00001000L
+-//PPLL_OBSERVE0
+-#define PPLL_OBSERVE0__pw_pc_lock_det_tdc_steps__SHIFT 0x0
+-#define PPLL_OBSERVE0__pw_pc_clear_sticky_lock__SHIFT 0x6
+-#define PPLL_OBSERVE0__pw_pc_lock_det_dis__SHIFT 0x8
+-#define PPLL_OBSERVE0__pw_pc_dco_cfg__SHIFT 0xa
+-#define PPLL_OBSERVE0__pw_pc_anaobs_sel__SHIFT 0x15
+-#define PPLL_OBSERVE0__pw_pc_lock_det_tdc_steps_MASK 0x0000001FL
+-#define PPLL_OBSERVE0__pw_pc_clear_sticky_lock_MASK 0x00000040L
+-#define PPLL_OBSERVE0__pw_pc_lock_det_dis_MASK 0x00000100L
+-#define PPLL_OBSERVE0__pw_pc_dco_cfg_MASK 0x0003FC00L
+-#define PPLL_OBSERVE0__pw_pc_anaobs_sel_MASK 0x00E00000L
+-//PPLL_OBSERVE1
+-#define PPLL_OBSERVE1__pw_pc_digobs_sel__SHIFT 0x0
+-#define PPLL_OBSERVE1__pw_pc_digobs_trig_sel__SHIFT 0x5
+-#define PPLL_OBSERVE1__pw_pc_digobs_div__SHIFT 0xa
+-#define PPLL_OBSERVE1__pw_pc_digobs_trig_div__SHIFT 0xc
+-#define PPLL_OBSERVE1__reg_tmg_lock_timer__SHIFT 0x10
+-#define PPLL_OBSERVE1__pw_pc_digobs_sel_MASK 0x0000000FL
+-#define PPLL_OBSERVE1__pw_pc_digobs_trig_sel_MASK 0x000001E0L
+-#define PPLL_OBSERVE1__pw_pc_digobs_div_MASK 0x00000C00L
+-#define PPLL_OBSERVE1__pw_pc_digobs_trig_div_MASK 0x00003000L
+-#define PPLL_OBSERVE1__reg_tmg_lock_timer_MASK 0x3FFF0000L
+-//PPLL_UPDATE_CNTL
+-#define PPLL_UPDATE_CNTL__reg_tmg_PLL_UPDATE_LOCK__SHIFT 0x2
+-#define PPLL_UPDATE_CNTL__reg_tmg_PLL_UPDATE_POINT__SHIFT 0x3
+-#define PPLL_UPDATE_CNTL__tmg_reg_UPDATE_PENDING__SHIFT 0x8
+-#define PPLL_UPDATE_CNTL__pc_pw_pll_rdy__SHIFT 0x9
+-#define PPLL_UPDATE_CNTL__TieLow1__SHIFT 0x10
+-#define PPLL_UPDATE_CNTL__reg_tmg_PLL_UPDATE_LOCK_MASK 0x00000004L
+-#define PPLL_UPDATE_CNTL__reg_tmg_PLL_UPDATE_POINT_MASK 0x00000008L
+-#define PPLL_UPDATE_CNTL__tmg_reg_UPDATE_PENDING_MASK 0x00000100L
+-#define PPLL_UPDATE_CNTL__pc_pw_pll_rdy_MASK 0x00000200L
+-#define PPLL_UPDATE_CNTL__TieLow1_MASK 0x00010000L
+-//PPLL_OBSERVE0_OUT
+-#define PPLL_OBSERVE0_OUT__disppll_core_obsout__SHIFT 0x0
+-#define PPLL_OBSERVE0_OUT__disppll_core_obsout_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dccg_pll0_dispdec
+-//PLL_MACRO_CNTL_RESERVED0
+-#define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED1
+-#define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED2
+-#define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED3
+-#define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED4
+-#define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED5
+-#define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED6
+-#define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED7
+-#define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED8
+-#define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED9
+-#define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED10
+-#define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED11
+-#define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED12
+-#define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED13
+-#define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED14
+-#define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED15
+-#define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED16
+-#define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED17
+-#define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED18
+-#define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED19
+-#define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED20
+-#define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED21
+-#define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED22
+-#define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED23
+-#define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED24
+-#define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED25
+-#define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED26
+-#define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED27
+-#define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED28
+-#define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED29
+-#define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED30
+-#define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED31
+-#define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED32
+-#define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED33
+-#define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED34
+-#define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED35
+-#define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED36
+-#define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED37
+-#define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED38
+-#define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED39
+-#define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED40
+-#define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//PLL_MACRO_CNTL_RESERVED41
+-#define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dc_perfmon1_dispdec
+-//DC_PERFMON1_PERFCOUNTER_CNTL
+-#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+-#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+-#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+-#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+-#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+-#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
+-#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+-#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+-#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+-#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+-#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+-#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
+-#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+-#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+-#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+-#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+-#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+-#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+-#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
+-#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+-#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+-#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+-#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+-#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+-#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
+-#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+-//DC_PERFMON1_PERFCOUNTER_CNTL2
+-#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+-#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+-#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+-#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+-#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+-#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+-#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+-#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+-//DC_PERFMON1_PERFCOUNTER_STATE
+-#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+-#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+-#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+-#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+-#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+-#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+-#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+-#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+-#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+-#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+-#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+-#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+-#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+-#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+-#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+-#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+-#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+-#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+-#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+-#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+-#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+-#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+-#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+-#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+-#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+-#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+-#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+-#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+-#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+-#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+-#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+-#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+-//DC_PERFMON1_PERFMON_CNTL
+-#define DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+-#define DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+-#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+-#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+-#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+-#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+-#define DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+-#define DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+-#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+-#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+-#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+-#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+-//DC_PERFMON1_PERFMON_CNTL2
+-#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+-#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+-#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+-#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+-#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+-#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+-#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+-#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+-//DC_PERFMON1_PERFMON_CVALUE_INT_MISC
+-#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+-#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+-#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+-#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+-#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+-#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+-#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+-#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+-#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+-#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+-#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+-#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+-#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+-#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+-#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+-#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+-#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+-#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+-#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+-#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+-#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+-#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+-#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+-#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+-#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+-#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+-#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+-#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+-#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+-#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+-#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+-#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+-#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+-#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+-//DC_PERFMON1_PERFMON_CVALUE_LOW
+-#define DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+-#define DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+-//DC_PERFMON1_PERFMON_HI
+-#define DC_PERFMON1_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+-#define DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+-#define DC_PERFMON1_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+-#define DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+-//DC_PERFMON1_PERFMON_LOW
+-#define DC_PERFMON1_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+-#define DC_PERFMON1_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_mcif_wb0_dispdec
+-//MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL
+-#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT 0x0
+-#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ__SHIFT 0x1
+-#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT 0x4
+-#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT 0x5
+-#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6
+-#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT 0x7
+-#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT 0x8
+-#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID__SHIFT 0x10
+-#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT 0x18
+-#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK 0x00000001L
+-#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ_MASK 0x00000002L
+-#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK 0x00000010L
+-#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK 0x00000020L
+-#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK 0x00000040L
+-#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK 0x00000080L
+-#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK 0x00000F00L
+-#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID_MASK 0x000F0000L
+-#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK 0x01000000L
+-//MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R
+-#define MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R__SHIFT 0x0
+-#define MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R_MASK 0x00001FFFL
+-//MCIF_WB0_MCIF_WB_BUFMGR_STATUS
+-#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT 0x0
+-#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT 0x1
+-#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT 0x2
+-#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT 0x4
+-#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT 0x7
+-#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT 0x8
+-#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT 0xc
+-#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT 0x1c
+-#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK 0x00000001L
+-#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK 0x00000002L
+-#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK 0x00000004L
+-#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK 0x00000070L
+-#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK 0x00000080L
+-#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK 0x00000F00L
+-#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK 0x01FFF000L
+-#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK 0x70000000L
+-//MCIF_WB0_MCIF_WB_BUF_PITCH
+-#define MCIF_WB0_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT 0x8
+-#define MCIF_WB0_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT 0x18
+-#define MCIF_WB0_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK 0x0000FF00L
+-#define MCIF_WB0_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK 0xFF000000L
+-//MCIF_WB0_MCIF_WB_BUF_1_STATUS
+-#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT 0x0
+-#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT 0x1
+-#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT 0x2
+-#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT 0x3
+-#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT 0x4
+-#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT 0x5
+-#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT 0x8
+-#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT 0xc
+-#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD__SHIFT 0xf
+-#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT 0x10
+-#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR__SHIFT 0x1d
+-#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR__SHIFT 0x1e
+-#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR__SHIFT 0x1f
+-#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK 0x00000001L
+-#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK 0x00000002L
+-#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK 0x00000004L
+-#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK 0x00000008L
+-#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK 0x00000010L
+-#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK 0x000000E0L
+-#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK 0x00000F00L
+-#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK 0x00007000L
+-#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD_MASK 0x00008000L
+-#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK 0x1FFF0000L
+-#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR_MASK 0x20000000L
+-#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR_MASK 0x40000000L
+-#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR_MASK 0x80000000L
+-//MCIF_WB0_MCIF_WB_BUF_1_STATUS2
+-#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R__SHIFT 0x0
+-#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT 0xd
+-#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT 0xe
+-#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT 0x11
+-#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT 0x12
+-#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R_MASK 0x00001FFFL
+-#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK 0x00002000L
+-#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK 0x00004000L
+-#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK 0x00020000L
+-#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK 0x00040000L
+-//MCIF_WB0_MCIF_WB_BUF_2_STATUS
+-#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT 0x0
+-#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT 0x1
+-#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT 0x2
+-#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT 0x3
+-#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT 0x4
+-#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT 0x5
+-#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT 0x8
+-#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT 0xc
+-#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD__SHIFT 0xf
+-#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT 0x10
+-#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR__SHIFT 0x1d
+-#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR__SHIFT 0x1e
+-#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR__SHIFT 0x1f
+-#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK 0x00000001L
+-#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK 0x00000002L
+-#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK 0x00000004L
+-#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK 0x00000008L
+-#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK 0x00000010L
+-#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK 0x000000E0L
+-#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK 0x00000F00L
+-#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK 0x00007000L
+-#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD_MASK 0x00008000L
+-#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK 0x1FFF0000L
+-#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR_MASK 0x20000000L
+-#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR_MASK 0x40000000L
+-#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR_MASK 0x80000000L
+-//MCIF_WB0_MCIF_WB_BUF_2_STATUS2
+-#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R__SHIFT 0x0
+-#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT 0xd
+-#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT 0xe
+-#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT 0x11
+-#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT 0x12
+-#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R_MASK 0x00001FFFL
+-#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK 0x00002000L
+-#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK 0x00004000L
+-#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK 0x00020000L
+-#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK 0x00040000L
+-//MCIF_WB0_MCIF_WB_BUF_3_STATUS
+-#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT 0x0
+-#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT 0x1
+-#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT 0x2
+-#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT 0x3
+-#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT 0x4
+-#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT 0x5
+-#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT 0x8
+-#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT 0xc
+-#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD__SHIFT 0xf
+-#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT 0x10
+-#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR__SHIFT 0x1d
+-#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR__SHIFT 0x1e
+-#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR__SHIFT 0x1f
+-#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK 0x00000001L
+-#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK 0x00000002L
+-#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK 0x00000004L
+-#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK 0x00000008L
+-#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK 0x00000010L
+-#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK 0x000000E0L
+-#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK 0x00000F00L
+-#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK 0x00007000L
+-#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD_MASK 0x00008000L
+-#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK 0x1FFF0000L
+-#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR_MASK 0x20000000L
+-#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR_MASK 0x40000000L
+-#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR_MASK 0x80000000L
+-//MCIF_WB0_MCIF_WB_BUF_3_STATUS2
+-#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R__SHIFT 0x0
+-#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT 0xd
+-#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT 0xe
+-#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT 0x11
+-#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT 0x12
+-#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R_MASK 0x00001FFFL
+-#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK 0x00002000L
+-#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK 0x00004000L
+-#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK 0x00020000L
+-#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK 0x00040000L
+-//MCIF_WB0_MCIF_WB_BUF_4_STATUS
+-#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT 0x0
+-#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT 0x1
+-#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT 0x2
+-#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT 0x3
+-#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT 0x4
+-#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT 0x5
+-#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT 0x8
+-#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT 0xc
+-#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD__SHIFT 0xf
+-#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT 0x10
+-#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR__SHIFT 0x1d
+-#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR__SHIFT 0x1e
+-#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR__SHIFT 0x1f
+-#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK 0x00000001L
+-#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK 0x00000002L
+-#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK 0x00000004L
+-#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK 0x00000008L
+-#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK 0x00000010L
+-#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK 0x000000E0L
+-#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK 0x00000F00L
+-#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK 0x00007000L
+-#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD_MASK 0x00008000L
+-#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK 0x1FFF0000L
+-#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR_MASK 0x20000000L
+-#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR_MASK 0x40000000L
+-#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR_MASK 0x80000000L
+-//MCIF_WB0_MCIF_WB_BUF_4_STATUS2
+-#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R__SHIFT 0x0
+-#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT 0xd
+-#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT 0xe
+-#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT 0x11
+-#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT 0x12
+-#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R_MASK 0x00001FFFL
+-#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK 0x00002000L
+-#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK 0x00004000L
+-#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK 0x00020000L
+-#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK 0x00040000L
+-//MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL
+-#define MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT 0x0
+-#define MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT 0x16
+-#define MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK 0x00000003L
+-#define MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK 0xFFC00000L
+-//MCIF_WB0_MCIF_WB_SCLK_CHANGE
+-#define MCIF_WB0_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT 0x0
+-#define MCIF_WB0_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK__SHIFT 0x1
+-#define MCIF_WB0_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK 0x00000001L
+-#define MCIF_WB0_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK_MASK 0x0000000EL
+-//MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y
+-#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT 0x0
+-#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK 0xFFFFFFFFL
+-//MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET
+-#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET__SHIFT 0x0
+-#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET_MASK 0x0003FFFFL
+-//MCIF_WB0_MCIF_WB_BUF_1_ADDR_C
+-#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT 0x0
+-#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK 0xFFFFFFFFL
+-//MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET
+-#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET__SHIFT 0x0
+-#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET_MASK 0x0003FFFFL
+-//MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y
+-#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT 0x0
+-#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK 0xFFFFFFFFL
+-//MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET
+-#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET__SHIFT 0x0
+-#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET_MASK 0x0003FFFFL
+-//MCIF_WB0_MCIF_WB_BUF_2_ADDR_C
+-#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT 0x0
+-#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK 0xFFFFFFFFL
+-//MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET
+-#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET__SHIFT 0x0
+-#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET_MASK 0x0003FFFFL
+-//MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y
+-#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT 0x0
+-#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK 0xFFFFFFFFL
+-//MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET
+-#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET__SHIFT 0x0
+-#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET_MASK 0x0003FFFFL
+-//MCIF_WB0_MCIF_WB_BUF_3_ADDR_C
+-#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT 0x0
+-#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK 0xFFFFFFFFL
+-//MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET
+-#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET__SHIFT 0x0
+-#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET_MASK 0x0003FFFFL
+-//MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y
+-#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT 0x0
+-#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK 0xFFFFFFFFL
+-//MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET
+-#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET__SHIFT 0x0
+-#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET_MASK 0x0003FFFFL
+-//MCIF_WB0_MCIF_WB_BUF_4_ADDR_C
+-#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT 0x0
+-#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK 0xFFFFFFFFL
+-//MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET
+-#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET__SHIFT 0x0
+-#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET_MASK 0x0003FFFFL
+-//MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL
+-#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT 0x0
+-#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT 0x4
+-#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT 0x5
+-#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT 0x6
+-#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT 0x8
+-#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT 0x10
+-#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK 0x00000001L
+-#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK 0x00000010L
+-#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK 0x00000020L
+-#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK 0x00000040L
+-#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK 0x00000F00L
+-#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK 0x1FFF0000L
+-//MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK
+-#define MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT 0x0
+-#define MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK 0x0001FFFFL
+-//MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL
+-#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x0
+-#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x1
+-#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0x2
+-#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x4
+-#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000001L
+-#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000002L
+-#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000004L
+-#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00000070L
+-//MCIF_WB0_MCIF_WB_WATERMARK
+-#define MCIF_WB0_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT 0x0
+-#define MCIF_WB0_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK 0x0000FFFFL
+-//MCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL
+-#define MCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT 0x0
+-#define MCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK 0x00000001L
+-//MCIF_WB0_MCIF_WB_WARM_UP_CNTL
+-#define MCIF_WB0_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP__SHIFT 0x8
+-#define MCIF_WB0_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP_MASK 0x0000FF00L
+-//MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL
+-#define MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ__SHIFT 0x0
+-#define MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT 0x1
+-#define MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ_MASK 0x00000001L
+-#define MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK 0x00000002L
+-//MCIF_WB0_MULTI_LEVEL_QOS_CTRL
+-#define MCIF_WB0_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT 0x0
+-#define MCIF_WB0_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK 0x003FFFFFL
+-//MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE
+-#define MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT 0x0
+-#define MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK 0x000FFFFFL
+-//MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE
+-#define MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT 0x0
+-#define MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK 0x000FFFFFL
+-
+-
+-// addressBlock: dce_dc_mcif_wb1_dispdec
+-//MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL
+-#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT 0x0
+-#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ__SHIFT 0x1
+-#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT 0x4
+-#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT 0x5
+-#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6
+-#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT 0x7
+-#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT 0x8
+-#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID__SHIFT 0x10
+-#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT 0x18
+-#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK 0x00000001L
+-#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ_MASK 0x00000002L
+-#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK 0x00000010L
+-#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK 0x00000020L
+-#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK 0x00000040L
+-#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK 0x00000080L
+-#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK 0x00000F00L
+-#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID_MASK 0x000F0000L
+-#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK 0x01000000L
+-//MCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R
+-#define MCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R__SHIFT 0x0
+-#define MCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R_MASK 0x00001FFFL
+-//MCIF_WB1_MCIF_WB_BUFMGR_STATUS
+-#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT 0x0
+-#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT 0x1
+-#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT 0x2
+-#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT 0x4
+-#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT 0x7
+-#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT 0x8
+-#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT 0xc
+-#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT 0x1c
+-#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK 0x00000001L
+-#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK 0x00000002L
+-#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK 0x00000004L
+-#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK 0x00000070L
+-#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK 0x00000080L
+-#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK 0x00000F00L
+-#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK 0x01FFF000L
+-#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK 0x70000000L
+-//MCIF_WB1_MCIF_WB_BUF_PITCH
+-#define MCIF_WB1_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT 0x8
+-#define MCIF_WB1_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT 0x18
+-#define MCIF_WB1_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK 0x0000FF00L
+-#define MCIF_WB1_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK 0xFF000000L
+-//MCIF_WB1_MCIF_WB_BUF_1_STATUS
+-#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT 0x0
+-#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT 0x1
+-#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT 0x2
+-#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT 0x3
+-#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT 0x4
+-#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT 0x5
+-#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT 0x8
+-#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT 0xc
+-#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD__SHIFT 0xf
+-#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT 0x10
+-#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR__SHIFT 0x1d
+-#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR__SHIFT 0x1e
+-#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR__SHIFT 0x1f
+-#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK 0x00000001L
+-#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK 0x00000002L
+-#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK 0x00000004L
+-#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK 0x00000008L
+-#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK 0x00000010L
+-#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK 0x000000E0L
+-#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK 0x00000F00L
+-#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK 0x00007000L
+-#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD_MASK 0x00008000L
+-#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK 0x1FFF0000L
+-#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR_MASK 0x20000000L
+-#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR_MASK 0x40000000L
+-#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR_MASK 0x80000000L
+-//MCIF_WB1_MCIF_WB_BUF_1_STATUS2
+-#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R__SHIFT 0x0
+-#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT 0xd
+-#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT 0xe
+-#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT 0x11
+-#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT 0x12
+-#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R_MASK 0x00001FFFL
+-#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK 0x00002000L
+-#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK 0x00004000L
+-#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK 0x00020000L
+-#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK 0x00040000L
+-//MCIF_WB1_MCIF_WB_BUF_2_STATUS
+-#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT 0x0
+-#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT 0x1
+-#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT 0x2
+-#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT 0x3
+-#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT 0x4
+-#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT 0x5
+-#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT 0x8
+-#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT 0xc
+-#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD__SHIFT 0xf
+-#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT 0x10
+-#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR__SHIFT 0x1d
+-#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR__SHIFT 0x1e
+-#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR__SHIFT 0x1f
+-#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK 0x00000001L
+-#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK 0x00000002L
+-#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK 0x00000004L
+-#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK 0x00000008L
+-#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK 0x00000010L
+-#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK 0x000000E0L
+-#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK 0x00000F00L
+-#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK 0x00007000L
+-#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD_MASK 0x00008000L
+-#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK 0x1FFF0000L
+-#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR_MASK 0x20000000L
+-#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR_MASK 0x40000000L
+-#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR_MASK 0x80000000L
+-//MCIF_WB1_MCIF_WB_BUF_2_STATUS2
+-#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R__SHIFT 0x0
+-#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT 0xd
+-#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT 0xe
+-#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT 0x11
+-#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT 0x12
+-#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R_MASK 0x00001FFFL
+-#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK 0x00002000L
+-#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK 0x00004000L
+-#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK 0x00020000L
+-#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK 0x00040000L
+-//MCIF_WB1_MCIF_WB_BUF_3_STATUS
+-#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT 0x0
+-#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT 0x1
+-#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT 0x2
+-#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT 0x3
+-#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT 0x4
+-#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT 0x5
+-#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT 0x8
+-#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT 0xc
+-#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD__SHIFT 0xf
+-#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT 0x10
+-#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR__SHIFT 0x1d
+-#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR__SHIFT 0x1e
+-#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR__SHIFT 0x1f
+-#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK 0x00000001L
+-#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK 0x00000002L
+-#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK 0x00000004L
+-#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK 0x00000008L
+-#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK 0x00000010L
+-#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK 0x000000E0L
+-#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK 0x00000F00L
+-#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK 0x00007000L
+-#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD_MASK 0x00008000L
+-#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK 0x1FFF0000L
+-#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR_MASK 0x20000000L
+-#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR_MASK 0x40000000L
+-#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR_MASK 0x80000000L
+-//MCIF_WB1_MCIF_WB_BUF_3_STATUS2
+-#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R__SHIFT 0x0
+-#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT 0xd
+-#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT 0xe
+-#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT 0x11
+-#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT 0x12
+-#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R_MASK 0x00001FFFL
+-#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK 0x00002000L
+-#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK 0x00004000L
+-#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK 0x00020000L
+-#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK 0x00040000L
+-//MCIF_WB1_MCIF_WB_BUF_4_STATUS
+-#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT 0x0
+-#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT 0x1
+-#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT 0x2
+-#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT 0x3
+-#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT 0x4
+-#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT 0x5
+-#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT 0x8
+-#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT 0xc
+-#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD__SHIFT 0xf
+-#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT 0x10
+-#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR__SHIFT 0x1d
+-#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR__SHIFT 0x1e
+-#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR__SHIFT 0x1f
+-#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK 0x00000001L
+-#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK 0x00000002L
+-#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK 0x00000004L
+-#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK 0x00000008L
+-#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK 0x00000010L
+-#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK 0x000000E0L
+-#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK 0x00000F00L
+-#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK 0x00007000L
+-#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD_MASK 0x00008000L
+-#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK 0x1FFF0000L
+-#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR_MASK 0x20000000L
+-#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR_MASK 0x40000000L
+-#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR_MASK 0x80000000L
+-//MCIF_WB1_MCIF_WB_BUF_4_STATUS2
+-#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R__SHIFT 0x0
+-#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT 0xd
+-#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT 0xe
+-#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT 0x11
+-#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT 0x12
+-#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R_MASK 0x00001FFFL
+-#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK 0x00002000L
+-#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK 0x00004000L
+-#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK 0x00020000L
+-#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK 0x00040000L
+-//MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL
+-#define MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT 0x0
+-#define MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT 0x16
+-#define MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK 0x00000003L
+-#define MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK 0xFFC00000L
+-//MCIF_WB1_MCIF_WB_SCLK_CHANGE
+-#define MCIF_WB1_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT 0x0
+-#define MCIF_WB1_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK__SHIFT 0x1
+-#define MCIF_WB1_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK 0x00000001L
+-#define MCIF_WB1_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK_MASK 0x0000000EL
+-//MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y
+-#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT 0x0
+-#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK 0xFFFFFFFFL
+-//MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET
+-#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET__SHIFT 0x0
+-#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET_MASK 0x0003FFFFL
+-//MCIF_WB1_MCIF_WB_BUF_1_ADDR_C
+-#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT 0x0
+-#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK 0xFFFFFFFFL
+-//MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET
+-#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET__SHIFT 0x0
+-#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET_MASK 0x0003FFFFL
+-//MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y
+-#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT 0x0
+-#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK 0xFFFFFFFFL
+-//MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET
+-#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET__SHIFT 0x0
+-#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET_MASK 0x0003FFFFL
+-//MCIF_WB1_MCIF_WB_BUF_2_ADDR_C
+-#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT 0x0
+-#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK 0xFFFFFFFFL
+-//MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET
+-#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET__SHIFT 0x0
+-#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET_MASK 0x0003FFFFL
+-//MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y
+-#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT 0x0
+-#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK 0xFFFFFFFFL
+-//MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET
+-#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET__SHIFT 0x0
+-#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET_MASK 0x0003FFFFL
+-//MCIF_WB1_MCIF_WB_BUF_3_ADDR_C
+-#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT 0x0
+-#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK 0xFFFFFFFFL
+-//MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET
+-#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET__SHIFT 0x0
+-#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET_MASK 0x0003FFFFL
+-//MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y
+-#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT 0x0
+-#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK 0xFFFFFFFFL
+-//MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET
+-#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET__SHIFT 0x0
+-#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET_MASK 0x0003FFFFL
+-//MCIF_WB1_MCIF_WB_BUF_4_ADDR_C
+-#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT 0x0
+-#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK 0xFFFFFFFFL
+-//MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET
+-#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET__SHIFT 0x0
+-#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET_MASK 0x0003FFFFL
+-//MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL
+-#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT 0x0
+-#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT 0x4
+-#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT 0x5
+-#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT 0x6
+-#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT 0x8
+-#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT 0x10
+-#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK 0x00000001L
+-#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK 0x00000010L
+-#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK 0x00000020L
+-#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK 0x00000040L
+-#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK 0x00000F00L
+-#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK 0x1FFF0000L
+-//MCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK
+-#define MCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT 0x0
+-#define MCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK 0x0001FFFFL
+-//MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL
+-#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x0
+-#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x1
+-#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0x2
+-#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x4
+-#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000001L
+-#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000002L
+-#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000004L
+-#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00000070L
+-//MCIF_WB1_MCIF_WB_WATERMARK
+-#define MCIF_WB1_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT 0x0
+-#define MCIF_WB1_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK 0x0000FFFFL
+-//MCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL
+-#define MCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT 0x0
+-#define MCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK 0x00000001L
+-//MCIF_WB1_MCIF_WB_WARM_UP_CNTL
+-#define MCIF_WB1_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP__SHIFT 0x8
+-#define MCIF_WB1_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP_MASK 0x0000FF00L
+-//MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL
+-#define MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ__SHIFT 0x0
+-#define MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT 0x1
+-#define MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ_MASK 0x00000001L
+-#define MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK 0x00000002L
+-//MCIF_WB1_MULTI_LEVEL_QOS_CTRL
+-#define MCIF_WB1_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT 0x0
+-#define MCIF_WB1_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK 0x003FFFFFL
+-//MCIF_WB1_MCIF_WB_BUF_LUMA_SIZE
+-#define MCIF_WB1_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT 0x0
+-#define MCIF_WB1_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK 0x000FFFFFL
+-//MCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE
+-#define MCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT 0x0
+-#define MCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK 0x000FFFFFL
+-
+-
+-// addressBlock: dce_dc_mcif_wb2_dispdec
+-//MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL
+-#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT 0x0
+-#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ__SHIFT 0x1
+-#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT 0x4
+-#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT 0x5
+-#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6
+-#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT 0x7
+-#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT 0x8
+-#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID__SHIFT 0x10
+-#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT 0x18
+-#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK 0x00000001L
+-#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ_MASK 0x00000002L
+-#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK 0x00000010L
+-#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK 0x00000020L
+-#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK 0x00000040L
+-#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK 0x00000080L
+-#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK 0x00000F00L
+-#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID_MASK 0x000F0000L
+-#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK 0x01000000L
+-//MCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R
+-#define MCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R__SHIFT 0x0
+-#define MCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R_MASK 0x00001FFFL
+-//MCIF_WB2_MCIF_WB_BUFMGR_STATUS
+-#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT 0x0
+-#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT 0x1
+-#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT 0x2
+-#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT 0x4
+-#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT 0x7
+-#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT 0x8
+-#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT 0xc
+-#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT 0x1c
+-#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK 0x00000001L
+-#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK 0x00000002L
+-#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK 0x00000004L
+-#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK 0x00000070L
+-#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK 0x00000080L
+-#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK 0x00000F00L
+-#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK 0x01FFF000L
+-#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK 0x70000000L
+-//MCIF_WB2_MCIF_WB_BUF_PITCH
+-#define MCIF_WB2_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT 0x8
+-#define MCIF_WB2_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT 0x18
+-#define MCIF_WB2_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK 0x0000FF00L
+-#define MCIF_WB2_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK 0xFF000000L
+-//MCIF_WB2_MCIF_WB_BUF_1_STATUS
+-#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT 0x0
+-#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT 0x1
+-#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT 0x2
+-#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT 0x3
+-#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT 0x4
+-#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT 0x5
+-#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT 0x8
+-#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT 0xc
+-#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD__SHIFT 0xf
+-#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT 0x10
+-#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR__SHIFT 0x1d
+-#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR__SHIFT 0x1e
+-#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR__SHIFT 0x1f
+-#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK 0x00000001L
+-#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK 0x00000002L
+-#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK 0x00000004L
+-#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK 0x00000008L
+-#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK 0x00000010L
+-#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK 0x000000E0L
+-#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK 0x00000F00L
+-#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK 0x00007000L
+-#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD_MASK 0x00008000L
+-#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK 0x1FFF0000L
+-#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR_MASK 0x20000000L
+-#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR_MASK 0x40000000L
+-#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR_MASK 0x80000000L
+-//MCIF_WB2_MCIF_WB_BUF_1_STATUS2
+-#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R__SHIFT 0x0
+-#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT 0xd
+-#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT 0xe
+-#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT 0x11
+-#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT 0x12
+-#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R_MASK 0x00001FFFL
+-#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK 0x00002000L
+-#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK 0x00004000L
+-#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK 0x00020000L
+-#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK 0x00040000L
+-//MCIF_WB2_MCIF_WB_BUF_2_STATUS
+-#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT 0x0
+-#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT 0x1
+-#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT 0x2
+-#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT 0x3
+-#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT 0x4
+-#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT 0x5
+-#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT 0x8
+-#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT 0xc
+-#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD__SHIFT 0xf
+-#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT 0x10
+-#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR__SHIFT 0x1d
+-#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR__SHIFT 0x1e
+-#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR__SHIFT 0x1f
+-#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK 0x00000001L
+-#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK 0x00000002L
+-#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK 0x00000004L
+-#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK 0x00000008L
+-#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK 0x00000010L
+-#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK 0x000000E0L
+-#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK 0x00000F00L
+-#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK 0x00007000L
+-#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD_MASK 0x00008000L
+-#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK 0x1FFF0000L
+-#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR_MASK 0x20000000L
+-#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR_MASK 0x40000000L
+-#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR_MASK 0x80000000L
+-//MCIF_WB2_MCIF_WB_BUF_2_STATUS2
+-#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R__SHIFT 0x0
+-#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT 0xd
+-#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT 0xe
+-#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT 0x11
+-#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT 0x12
+-#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R_MASK 0x00001FFFL
+-#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK 0x00002000L
+-#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK 0x00004000L
+-#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK 0x00020000L
+-#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK 0x00040000L
+-//MCIF_WB2_MCIF_WB_BUF_3_STATUS
+-#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT 0x0
+-#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT 0x1
+-#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT 0x2
+-#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT 0x3
+-#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT 0x4
+-#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT 0x5
+-#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT 0x8
+-#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT 0xc
+-#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD__SHIFT 0xf
+-#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT 0x10
+-#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR__SHIFT 0x1d
+-#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR__SHIFT 0x1e
+-#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR__SHIFT 0x1f
+-#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK 0x00000001L
+-#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK 0x00000002L
+-#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK 0x00000004L
+-#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK 0x00000008L
+-#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK 0x00000010L
+-#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK 0x000000E0L
+-#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK 0x00000F00L
+-#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK 0x00007000L
+-#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD_MASK 0x00008000L
+-#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK 0x1FFF0000L
+-#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR_MASK 0x20000000L
+-#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR_MASK 0x40000000L
+-#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR_MASK 0x80000000L
+-//MCIF_WB2_MCIF_WB_BUF_3_STATUS2
+-#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R__SHIFT 0x0
+-#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT 0xd
+-#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT 0xe
+-#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT 0x11
+-#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT 0x12
+-#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R_MASK 0x00001FFFL
+-#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK 0x00002000L
+-#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK 0x00004000L
+-#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK 0x00020000L
+-#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK 0x00040000L
+-//MCIF_WB2_MCIF_WB_BUF_4_STATUS
+-#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT 0x0
+-#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT 0x1
+-#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT 0x2
+-#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT 0x3
+-#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT 0x4
+-#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT 0x5
+-#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT 0x8
+-#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT 0xc
+-#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD__SHIFT 0xf
+-#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT 0x10
+-#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR__SHIFT 0x1d
+-#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR__SHIFT 0x1e
+-#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR__SHIFT 0x1f
+-#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK 0x00000001L
+-#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK 0x00000002L
+-#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK 0x00000004L
+-#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK 0x00000008L
+-#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK 0x00000010L
+-#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK 0x000000E0L
+-#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK 0x00000F00L
+-#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK 0x00007000L
+-#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD_MASK 0x00008000L
+-#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK 0x1FFF0000L
+-#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR_MASK 0x20000000L
+-#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR_MASK 0x40000000L
+-#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR_MASK 0x80000000L
+-//MCIF_WB2_MCIF_WB_BUF_4_STATUS2
+-#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R__SHIFT 0x0
+-#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT 0xd
+-#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT 0xe
+-#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT 0x11
+-#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT 0x12
+-#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R_MASK 0x00001FFFL
+-#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK 0x00002000L
+-#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK 0x00004000L
+-#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK 0x00020000L
+-#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK 0x00040000L
+-//MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL
+-#define MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT 0x0
+-#define MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT 0x16
+-#define MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK 0x00000003L
+-#define MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK 0xFFC00000L
+-//MCIF_WB2_MCIF_WB_SCLK_CHANGE
+-#define MCIF_WB2_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT 0x0
+-#define MCIF_WB2_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK__SHIFT 0x1
+-#define MCIF_WB2_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK 0x00000001L
+-#define MCIF_WB2_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK_MASK 0x0000000EL
+-//MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y
+-#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT 0x0
+-#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK 0xFFFFFFFFL
+-//MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET
+-#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET__SHIFT 0x0
+-#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET_MASK 0x0003FFFFL
+-//MCIF_WB2_MCIF_WB_BUF_1_ADDR_C
+-#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT 0x0
+-#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK 0xFFFFFFFFL
+-//MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET
+-#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET__SHIFT 0x0
+-#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET_MASK 0x0003FFFFL
+-//MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y
+-#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT 0x0
+-#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK 0xFFFFFFFFL
+-//MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET
+-#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET__SHIFT 0x0
+-#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET_MASK 0x0003FFFFL
+-//MCIF_WB2_MCIF_WB_BUF_2_ADDR_C
+-#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT 0x0
+-#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK 0xFFFFFFFFL
+-//MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET
+-#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET__SHIFT 0x0
+-#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET_MASK 0x0003FFFFL
+-//MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y
+-#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT 0x0
+-#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK 0xFFFFFFFFL
+-//MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET
+-#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET__SHIFT 0x0
+-#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET_MASK 0x0003FFFFL
+-//MCIF_WB2_MCIF_WB_BUF_3_ADDR_C
+-#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT 0x0
+-#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK 0xFFFFFFFFL
+-//MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET
+-#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET__SHIFT 0x0
+-#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET_MASK 0x0003FFFFL
+-//MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y
+-#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT 0x0
+-#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK 0xFFFFFFFFL
+-//MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET
+-#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET__SHIFT 0x0
+-#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET_MASK 0x0003FFFFL
+-//MCIF_WB2_MCIF_WB_BUF_4_ADDR_C
+-#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT 0x0
+-#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK 0xFFFFFFFFL
+-//MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET
+-#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET__SHIFT 0x0
+-#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET_MASK 0x0003FFFFL
+-//MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL
+-#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT 0x0
+-#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT 0x4
+-#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT 0x5
+-#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT 0x6
+-#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT 0x8
+-#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT 0x10
+-#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK 0x00000001L
+-#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK 0x00000010L
+-#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK 0x00000020L
+-#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK 0x00000040L
+-#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK 0x00000F00L
+-#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK 0x1FFF0000L
+-//MCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK
+-#define MCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT 0x0
+-#define MCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK 0x0001FFFFL
+-//MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL
+-#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x0
+-#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x1
+-#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0x2
+-#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x4
+-#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000001L
+-#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000002L
+-#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000004L
+-#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00000070L
+-//MCIF_WB2_MCIF_WB_WATERMARK
+-#define MCIF_WB2_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT 0x0
+-#define MCIF_WB2_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK 0x0000FFFFL
+-//MCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL
+-#define MCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT 0x0
+-#define MCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK 0x00000001L
+-//MCIF_WB2_MCIF_WB_WARM_UP_CNTL
+-#define MCIF_WB2_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP__SHIFT 0x8
+-#define MCIF_WB2_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP_MASK 0x0000FF00L
+-//MCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL
+-#define MCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ__SHIFT 0x0
+-#define MCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT 0x1
+-#define MCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ_MASK 0x00000001L
+-#define MCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK 0x00000002L
+-//MCIF_WB2_MULTI_LEVEL_QOS_CTRL
+-#define MCIF_WB2_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT 0x0
+-#define MCIF_WB2_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK 0x003FFFFFL
+-//MCIF_WB2_MCIF_WB_BUF_LUMA_SIZE
+-#define MCIF_WB2_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT 0x0
+-#define MCIF_WB2_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK 0x000FFFFFL
+-//MCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE
+-#define MCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT 0x0
+-#define MCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK 0x000FFFFFL
+-
+-
+-// addressBlock: dce_dc_cwb0_dispdec
+-//CWB0_CWB_CTRL
+-#define CWB0_CWB_CTRL__CWB_EN__SHIFT 0x0
+-#define CWB0_CWB_CTRL__CWB_OUTPUT_COLOR_DEPTH__SHIFT 0x2
+-#define CWB0_CWB_CTRL__CWB_ZERO_PADDING_MODE__SHIFT 0x4
+-#define CWB0_CWB_CTRL__CWB_CB_CR_SWAP__SHIFT 0x6
+-#define CWB0_CWB_CTRL__CWB_422MODE_LUMA_CHROMA_SWAP__SHIFT 0x7
+-#define CWB0_CWB_CTRL__CWB_444MODE_ROUNDING_EN__SHIFT 0x8
+-#define CWB0_CWB_CTRL__CWB_PACK_FMT_SEL__SHIFT 0xa
+-#define CWB0_CWB_CTRL__CWB_EN_MASK 0x00000001L
+-#define CWB0_CWB_CTRL__CWB_OUTPUT_COLOR_DEPTH_MASK 0x0000000CL
+-#define CWB0_CWB_CTRL__CWB_ZERO_PADDING_MODE_MASK 0x00000010L
+-#define CWB0_CWB_CTRL__CWB_CB_CR_SWAP_MASK 0x00000040L
+-#define CWB0_CWB_CTRL__CWB_422MODE_LUMA_CHROMA_SWAP_MASK 0x00000080L
+-#define CWB0_CWB_CTRL__CWB_444MODE_ROUNDING_EN_MASK 0x00000100L
+-#define CWB0_CWB_CTRL__CWB_PACK_FMT_SEL_MASK 0x00000400L
+-//CWB0_CWB_FENCE_PAR0
+-#define CWB0_CWB_FENCE_PAR0__CWB_OUTPUT_LINE_WIDTH__SHIFT 0x0
+-#define CWB0_CWB_FENCE_PAR0__CWB_ERROR_LINE_WIDTH__SHIFT 0x10
+-#define CWB0_CWB_FENCE_PAR0__CWB_OUTPUT_LINE_WIDTH_MASK 0x00001FFFL
+-#define CWB0_CWB_FENCE_PAR0__CWB_ERROR_LINE_WIDTH_MASK 0x1FFF0000L
+-//CWB0_CWB_FENCE_PAR1
+-#define CWB0_CWB_FENCE_PAR1__CWB_OUTPUT_LINES_PER_FRAME__SHIFT 0x0
+-#define CWB0_CWB_FENCE_PAR1__CWB_EOF_TO_SOF_SPACING__SHIFT 0x10
+-#define CWB0_CWB_FENCE_PAR1__CWB_OUTPUT_LINES_PER_FRAME_MASK 0x00001FFFL
+-#define CWB0_CWB_FENCE_PAR1__CWB_EOF_TO_SOF_SPACING_MASK 0x003F0000L
+-//CWB0_CWB_CRC_CTRL
+-#define CWB0_CWB_CRC_CTRL__CWB_CRC_EN__SHIFT 0x0
+-#define CWB0_CWB_CRC_CTRL__CWB_CRC_CONT_EN__SHIFT 0x2
+-#define CWB0_CWB_CRC_CTRL__CWB_CRC_SRC_SEL__SHIFT 0x6
+-#define CWB0_CWB_CRC_CTRL__CWB_CRC_EN_MASK 0x00000001L
+-#define CWB0_CWB_CRC_CTRL__CWB_CRC_CONT_EN_MASK 0x00000004L
+-#define CWB0_CWB_CRC_CTRL__CWB_CRC_SRC_SEL_MASK 0x00000040L
+-//CWB0_CWB_CRC_RED_GREEN_MASK
+-#define CWB0_CWB_CRC_RED_GREEN_MASK__CWB_CRC_RED_MASK__SHIFT 0x0
+-#define CWB0_CWB_CRC_RED_GREEN_MASK__CWB_CRC_GREEN_MASK__SHIFT 0x10
+-#define CWB0_CWB_CRC_RED_GREEN_MASK__CWB_CRC_RED_MASK_MASK 0x0000FFFFL
+-#define CWB0_CWB_CRC_RED_GREEN_MASK__CWB_CRC_GREEN_MASK_MASK 0xFFFF0000L
+-//CWB0_CWB_CRC_BLUE_MASK
+-#define CWB0_CWB_CRC_BLUE_MASK__CWB_CRC_BLUE_MASK__SHIFT 0x0
+-#define CWB0_CWB_CRC_BLUE_MASK__CWB_CRC_BLUE_MASK_MASK 0x0000FFFFL
+-//CWB0_CWB_CRC_RED_GREEN_RESULT
+-#define CWB0_CWB_CRC_RED_GREEN_RESULT__CWB_CRC_RED_RESULT__SHIFT 0x0
+-#define CWB0_CWB_CRC_RED_GREEN_RESULT__CWB_CRC_GREEN_RESULT__SHIFT 0x10
+-#define CWB0_CWB_CRC_RED_GREEN_RESULT__CWB_CRC_RED_RESULT_MASK 0x0000FFFFL
+-#define CWB0_CWB_CRC_RED_GREEN_RESULT__CWB_CRC_GREEN_RESULT_MASK 0xFFFF0000L
+-//CWB0_CWB_CRC_BLUE_RESULT
+-#define CWB0_CWB_CRC_BLUE_RESULT__CWB_CRC_BLUE_RESULT__SHIFT 0x0
+-#define CWB0_CWB_CRC_BLUE_RESULT__CWB_CRC_COUNT__SHIFT 0x10
+-#define CWB0_CWB_CRC_BLUE_RESULT__CWB_CRC_BLUE_RESULT_MASK 0x0000FFFFL
+-#define CWB0_CWB_CRC_BLUE_RESULT__CWB_CRC_COUNT_MASK 0x000F0000L
+-
+-
+-// addressBlock: dce_dc_cwb1_dispdec
+-//CWB1_CWB_CTRL
+-#define CWB1_CWB_CTRL__CWB_EN__SHIFT 0x0
+-#define CWB1_CWB_CTRL__CWB_OUTPUT_COLOR_DEPTH__SHIFT 0x2
+-#define CWB1_CWB_CTRL__CWB_ZERO_PADDING_MODE__SHIFT 0x4
+-#define CWB1_CWB_CTRL__CWB_CB_CR_SWAP__SHIFT 0x6
+-#define CWB1_CWB_CTRL__CWB_422MODE_LUMA_CHROMA_SWAP__SHIFT 0x7
+-#define CWB1_CWB_CTRL__CWB_444MODE_ROUNDING_EN__SHIFT 0x8
+-#define CWB1_CWB_CTRL__CWB_PACK_FMT_SEL__SHIFT 0xa
+-#define CWB1_CWB_CTRL__CWB_EN_MASK 0x00000001L
+-#define CWB1_CWB_CTRL__CWB_OUTPUT_COLOR_DEPTH_MASK 0x0000000CL
+-#define CWB1_CWB_CTRL__CWB_ZERO_PADDING_MODE_MASK 0x00000010L
+-#define CWB1_CWB_CTRL__CWB_CB_CR_SWAP_MASK 0x00000040L
+-#define CWB1_CWB_CTRL__CWB_422MODE_LUMA_CHROMA_SWAP_MASK 0x00000080L
+-#define CWB1_CWB_CTRL__CWB_444MODE_ROUNDING_EN_MASK 0x00000100L
+-#define CWB1_CWB_CTRL__CWB_PACK_FMT_SEL_MASK 0x00000400L
+-//CWB1_CWB_FENCE_PAR0
+-#define CWB1_CWB_FENCE_PAR0__CWB_OUTPUT_LINE_WIDTH__SHIFT 0x0
+-#define CWB1_CWB_FENCE_PAR0__CWB_ERROR_LINE_WIDTH__SHIFT 0x10
+-#define CWB1_CWB_FENCE_PAR0__CWB_OUTPUT_LINE_WIDTH_MASK 0x00001FFFL
+-#define CWB1_CWB_FENCE_PAR0__CWB_ERROR_LINE_WIDTH_MASK 0x1FFF0000L
+-//CWB1_CWB_FENCE_PAR1
+-#define CWB1_CWB_FENCE_PAR1__CWB_OUTPUT_LINES_PER_FRAME__SHIFT 0x0
+-#define CWB1_CWB_FENCE_PAR1__CWB_EOF_TO_SOF_SPACING__SHIFT 0x10
+-#define CWB1_CWB_FENCE_PAR1__CWB_OUTPUT_LINES_PER_FRAME_MASK 0x00001FFFL
+-#define CWB1_CWB_FENCE_PAR1__CWB_EOF_TO_SOF_SPACING_MASK 0x003F0000L
+-//CWB1_CWB_CRC_CTRL
+-#define CWB1_CWB_CRC_CTRL__CWB_CRC_EN__SHIFT 0x0
+-#define CWB1_CWB_CRC_CTRL__CWB_CRC_CONT_EN__SHIFT 0x2
+-#define CWB1_CWB_CRC_CTRL__CWB_CRC_SRC_SEL__SHIFT 0x6
+-#define CWB1_CWB_CRC_CTRL__CWB_CRC_EN_MASK 0x00000001L
+-#define CWB1_CWB_CRC_CTRL__CWB_CRC_CONT_EN_MASK 0x00000004L
+-#define CWB1_CWB_CRC_CTRL__CWB_CRC_SRC_SEL_MASK 0x00000040L
+-//CWB1_CWB_CRC_RED_GREEN_MASK
+-#define CWB1_CWB_CRC_RED_GREEN_MASK__CWB_CRC_RED_MASK__SHIFT 0x0
+-#define CWB1_CWB_CRC_RED_GREEN_MASK__CWB_CRC_GREEN_MASK__SHIFT 0x10
+-#define CWB1_CWB_CRC_RED_GREEN_MASK__CWB_CRC_RED_MASK_MASK 0x0000FFFFL
+-#define CWB1_CWB_CRC_RED_GREEN_MASK__CWB_CRC_GREEN_MASK_MASK 0xFFFF0000L
+-//CWB1_CWB_CRC_BLUE_MASK
+-#define CWB1_CWB_CRC_BLUE_MASK__CWB_CRC_BLUE_MASK__SHIFT 0x0
+-#define CWB1_CWB_CRC_BLUE_MASK__CWB_CRC_BLUE_MASK_MASK 0x0000FFFFL
+-//CWB1_CWB_CRC_RED_GREEN_RESULT
+-#define CWB1_CWB_CRC_RED_GREEN_RESULT__CWB_CRC_RED_RESULT__SHIFT 0x0
+-#define CWB1_CWB_CRC_RED_GREEN_RESULT__CWB_CRC_GREEN_RESULT__SHIFT 0x10
+-#define CWB1_CWB_CRC_RED_GREEN_RESULT__CWB_CRC_RED_RESULT_MASK 0x0000FFFFL
+-#define CWB1_CWB_CRC_RED_GREEN_RESULT__CWB_CRC_GREEN_RESULT_MASK 0xFFFF0000L
+-//CWB1_CWB_CRC_BLUE_RESULT
+-#define CWB1_CWB_CRC_BLUE_RESULT__CWB_CRC_BLUE_RESULT__SHIFT 0x0
+-#define CWB1_CWB_CRC_BLUE_RESULT__CWB_CRC_COUNT__SHIFT 0x10
+-#define CWB1_CWB_CRC_BLUE_RESULT__CWB_CRC_BLUE_RESULT_MASK 0x0000FFFFL
+-#define CWB1_CWB_CRC_BLUE_RESULT__CWB_CRC_COUNT_MASK 0x000F0000L
+-
+-
+-// addressBlock: dce_dc_dc_perfmon9_dispdec
+-//DC_PERFMON9_PERFCOUNTER_CNTL
+-#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+-#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+-#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+-#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+-#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+-#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
+-#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+-#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+-#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+-#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+-#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+-#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
+-#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+-#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+-#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+-#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+-#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+-#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+-#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
+-#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+-#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+-#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+-#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+-#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+-#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
+-#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+-//DC_PERFMON9_PERFCOUNTER_CNTL2
+-#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+-#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+-#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+-#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+-#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+-#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+-#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+-#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+-//DC_PERFMON9_PERFCOUNTER_STATE
+-#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+-#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+-#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+-#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+-#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+-#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+-#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+-#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+-#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+-#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+-#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+-#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+-#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+-#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+-#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+-#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+-#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+-#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+-#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+-#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+-#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+-#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+-#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+-#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+-#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+-#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+-#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+-#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+-#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+-#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+-#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+-#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+-//DC_PERFMON9_PERFMON_CNTL
+-#define DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+-#define DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+-#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+-#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+-#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+-#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+-#define DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+-#define DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+-#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+-#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+-#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+-#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+-//DC_PERFMON9_PERFMON_CNTL2
+-#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+-#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+-#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+-#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+-#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+-#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+-#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+-#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+-//DC_PERFMON9_PERFMON_CVALUE_INT_MISC
+-#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+-#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+-#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+-#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+-#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+-#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+-#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+-#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+-#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+-#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+-#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+-#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+-#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+-#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+-#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+-#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+-#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+-#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+-#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+-#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+-#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+-#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+-#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+-#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+-#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+-#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+-#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+-#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+-#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+-#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+-#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+-#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+-#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+-#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+-//DC_PERFMON9_PERFMON_CVALUE_LOW
+-#define DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+-#define DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+-//DC_PERFMON9_PERFMON_HI
+-#define DC_PERFMON9_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+-#define DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+-#define DC_PERFMON9_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+-#define DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+-//DC_PERFMON9_PERFMON_LOW
+-#define DC_PERFMON9_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+-#define DC_PERFMON9_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dispdec
+-//VGA_MEM_WRITE_PAGE_ADDR
+-#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0
+-#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10
+-#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x000003FFL
+-#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x03FF0000L
+-//VGA_MEM_READ_PAGE_ADDR
+-#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0
+-#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10
+-#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x000003FFL
+-#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x03FF0000L
+-//VGA_RENDER_CONTROL
+-#define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0
+-#define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5
+-#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT 0x7
+-#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT 0x8
+-#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT 0x10
+-#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT 0x18
+-#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT 0x19
+-#define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK 0x0000001FL
+-#define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK 0x00000060L
+-#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK 0x00000080L
+-#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK 0x00000100L
+-#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK 0x00030000L
+-#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK 0x01000000L
+-#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK 0x02000000L
+-//VGA_SEQUENCER_RESET_CONTROL
+-#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x0
+-#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x1
+-#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x2
+-#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x3
+-#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x4
+-#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x5
+-#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x8
+-#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x9
+-#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xa
+-#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xb
+-#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xc
+-#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xd
+-#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT 0x10
+-#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT 0x11
+-#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT 0x12
+-#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000001L
+-#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000002L
+-#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000004L
+-#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000008L
+-#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000010L
+-#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000020L
+-#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000100L
+-#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000200L
+-#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000400L
+-#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000800L
+-#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00001000L
+-#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00002000L
+-#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK 0x00010000L
+-#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK 0x00020000L
+-#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK 0x00FC0000L
+-//VGA_MODE_CONTROL
+-#define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT 0x0
+-#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT 0x4
+-#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT 0x8
+-#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT 0x10
+-#define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT__SHIFT 0x18
+-#define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK 0x00000001L
+-#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK 0x00000030L
+-#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK 0x00000100L
+-#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK 0x00010000L
+-#define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT_MASK 0x01000000L
+-//VGA_SURFACE_PITCH_SELECT
+-#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT 0x0
+-#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT 0x8
+-#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK 0x00000003L
+-#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK 0x00000300L
+-//VGA_MEMORY_BASE_ADDRESS
+-#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT 0x0
+-#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK 0xFFFFFFFFL
+-//VGA_DISPBUF1_SURFACE_ADDR
+-#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT 0x0
+-#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK 0x01FFFFFFL
+-//VGA_DISPBUF2_SURFACE_ADDR
+-#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT 0x0
+-#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK 0x01FFFFFFL
+-//VGA_MEMORY_BASE_ADDRESS_HIGH
+-#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT 0x0
+-#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK 0x000000FFL
+-//VGA_HDP_CONTROL
+-#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT 0x0
+-#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT 0x4
+-#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT 0x8
+-#define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT 0x10
+-#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 0x18
+-#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK 0x00000001L
+-#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK 0x00000010L
+-#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK 0x00000100L
+-#define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK 0x00010000L
+-#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK 0x01000000L
+-//VGA_CACHE_CONTROL
+-#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT 0x0
+-#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT 0x8
+-#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT 0x10
+-#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT 0x14
+-#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT 0x18
+-#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK 0x00000001L
+-#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK 0x00000100L
+-#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK 0x00010000L
+-#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK 0x00100000L
+-#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK 0x3F000000L
+-//D1VGA_CONTROL
+-#define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT 0x0
+-#define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT 0x8
+-#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
+-#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
+-#define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT 0x18
+-#define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK 0x00000001L
+-#define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK 0x00000100L
+-#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L
+-#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L
+-#define D1VGA_CONTROL__D1VGA_ROTATE_MASK 0x03000000L
+-//D2VGA_CONTROL
+-#define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT 0x0
+-#define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT 0x8
+-#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
+-#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
+-#define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT 0x18
+-#define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK 0x00000001L
+-#define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x00000100L
+-#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L
+-#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L
+-#define D2VGA_CONTROL__D2VGA_ROTATE_MASK 0x03000000L
+-//VGA_STATUS
+-#define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT 0x0
+-#define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT 0x1
+-#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT 0x2
+-#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT 0x3
+-#define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK 0x00000001L
+-#define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK 0x00000002L
+-#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK 0x00000004L
+-#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK 0x00000008L
+-//VGA_INTERRUPT_CONTROL
+-#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT 0x0
+-#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT 0x8
+-#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT 0x10
+-#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT 0x18
+-#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK 0x00000001L
+-#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK 0x00000100L
+-#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK 0x00010000L
+-#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK 0x01000000L
+-//VGA_STATUS_CLEAR
+-#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT 0x0
+-#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT 0x8
+-#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT 0x10
+-#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT 0x18
+-#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK 0x00000001L
+-#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK 0x00000100L
+-#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK 0x00010000L
+-#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK 0x01000000L
+-//VGA_INTERRUPT_STATUS
+-#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT 0x0
+-#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT 0x1
+-#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT 0x2
+-#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT 0x3
+-#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK 0x00000001L
+-#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK 0x00000002L
+-#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK 0x00000004L
+-#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK 0x00000008L
+-//VGA_MAIN_CONTROL
+-#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT 0x0
+-#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT 0x3
+-#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT 0x5
+-#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT 0x8
+-#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY__SHIFT 0xc
+-#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT 0x10
+-#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT 0x18
+-#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT 0x1a
+-#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT 0x1d
+-#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT 0x1f
+-#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK 0x00000003L
+-#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK 0x00000018L
+-#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK 0x000000E0L
+-#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK 0x00000300L
+-#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY_MASK 0x0000F000L
+-#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK 0x00030000L
+-#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK 0x03000000L
+-#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK 0x04000000L
+-#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK 0x20000000L
+-#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK 0x80000000L
+-//VGA_TEST_CONTROL
+-#define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT 0x0
+-#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT 0x8
+-#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT 0x10
+-#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT 0x18
+-#define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK 0x00000001L
+-#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK 0x00000100L
+-#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK 0x00010000L
+-#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK 0x01000000L
+-//VGA_QOS_CTRL
+-#define VGA_QOS_CTRL__VGA_READ_QOS__SHIFT 0x0
+-#define VGA_QOS_CTRL__VGA_WRITE_QOS__SHIFT 0x4
+-#define VGA_QOS_CTRL__VGA_READ_QOS_MASK 0x0000000FL
+-#define VGA_QOS_CTRL__VGA_WRITE_QOS_MASK 0x000000F0L
+-//CRTC8_IDX
+-#define CRTC8_IDX__VCRTC_IDX__SHIFT 0x0
+-#define CRTC8_IDX__VCRTC_IDX_MASK 0x3FL
+-//CRTC8_DATA
+-#define CRTC8_DATA__VCRTC_DATA__SHIFT 0x0
+-#define CRTC8_DATA__VCRTC_DATA_MASK 0xFFL
+-//GENFC_WT
+-#define GENFC_WT__VSYNC_SEL_W__SHIFT 0x3
+-#define GENFC_WT__VSYNC_SEL_W_MASK 0x08L
+-//GENS1
+-#define GENS1__NO_DISPLAY__SHIFT 0x0
+-#define GENS1__VGA_VSTATUS__SHIFT 0x3
+-#define GENS1__PIXEL_READ_BACK__SHIFT 0x4
+-#define GENS1__NO_DISPLAY_MASK 0x01L
+-#define GENS1__VGA_VSTATUS_MASK 0x08L
+-#define GENS1__PIXEL_READ_BACK_MASK 0x30L
+-//ATTRDW
+-#define ATTRDW__ATTR_DATA__SHIFT 0x0
+-#define ATTRDW__ATTR_DATA_MASK 0xFFL
+-//ATTRX
+-#define ATTRX__ATTR_IDX__SHIFT 0x0
+-#define ATTRX__ATTR_PAL_RW_ENB__SHIFT 0x5
+-#define ATTRX__ATTR_IDX_MASK 0x1FL
+-#define ATTRX__ATTR_PAL_RW_ENB_MASK 0x20L
+-//ATTRDR
+-#define ATTRDR__ATTR_DATA__SHIFT 0x0
+-#define ATTRDR__ATTR_DATA_MASK 0xFFL
+-//GENMO_WT
+-#define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT 0x0
+-#define GENMO_WT__VGA_RAM_EN__SHIFT 0x1
+-#define GENMO_WT__VGA_CKSEL__SHIFT 0x2
+-#define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT 0x5
+-#define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x6
+-#define GENMO_WT__VGA_VSYNC_POL__SHIFT 0x7
+-#define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK 0x01L
+-#define GENMO_WT__VGA_RAM_EN_MASK 0x02L
+-#define GENMO_WT__VGA_CKSEL_MASK 0x0CL
+-#define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK 0x20L
+-#define GENMO_WT__VGA_HSYNC_POL_MASK 0x40L
+-#define GENMO_WT__VGA_VSYNC_POL_MASK 0x80L
+-//GENS0
+-#define GENS0__SENSE_SWITCH__SHIFT 0x4
+-#define GENS0__CRT_INTR__SHIFT 0x7
+-#define GENS0__SENSE_SWITCH_MASK 0x10L
+-#define GENS0__CRT_INTR_MASK 0x80L
+-//GENENB
+-#define GENENB__BLK_IO_BASE__SHIFT 0x0
+-#define GENENB__BLK_IO_BASE_MASK 0xFFL
+-//SEQ8_IDX
+-#define SEQ8_IDX__SEQ_IDX__SHIFT 0x0
+-#define SEQ8_IDX__SEQ_IDX_MASK 0x07L
+-//SEQ8_DATA
+-#define SEQ8_DATA__SEQ_DATA__SHIFT 0x0
+-#define SEQ8_DATA__SEQ_DATA_MASK 0xFFL
+-//DAC_MASK
+-#define DAC_MASK__DAC_MASK__SHIFT 0x0
+-#define DAC_MASK__DAC_MASK_MASK 0xFFL
+-//DAC_R_INDEX
+-#define DAC_R_INDEX__DAC_R_INDEX__SHIFT 0x0
+-#define DAC_R_INDEX__DAC_R_INDEX_MASK 0xFFL
+-//DAC_W_INDEX
+-#define DAC_W_INDEX__DAC_W_INDEX__SHIFT 0x0
+-#define DAC_W_INDEX__DAC_W_INDEX_MASK 0xFFL
+-//DAC_DATA
+-#define DAC_DATA__DAC_DATA__SHIFT 0x0
+-#define DAC_DATA__DAC_DATA_MASK 0x3FL
+-//GENFC_RD
+-#define GENFC_RD__VSYNC_SEL_R__SHIFT 0x3
+-#define GENFC_RD__VSYNC_SEL_R_MASK 0x08L
+-//GENMO_RD
+-#define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT 0x0
+-#define GENMO_RD__VGA_RAM_EN__SHIFT 0x1
+-#define GENMO_RD__VGA_CKSEL__SHIFT 0x2
+-#define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT 0x5
+-#define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x6
+-#define GENMO_RD__VGA_VSYNC_POL__SHIFT 0x7
+-#define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK 0x01L
+-#define GENMO_RD__VGA_RAM_EN_MASK 0x02L
+-#define GENMO_RD__VGA_CKSEL_MASK 0x0CL
+-#define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK 0x20L
+-#define GENMO_RD__VGA_HSYNC_POL_MASK 0x40L
+-#define GENMO_RD__VGA_VSYNC_POL_MASK 0x80L
+-//GRPH8_IDX
+-#define GRPH8_IDX__GRPH_IDX__SHIFT 0x0
+-#define GRPH8_IDX__GRPH_IDX_MASK 0x0FL
+-//GRPH8_DATA
+-#define GRPH8_DATA__GRPH_DATA__SHIFT 0x0
+-#define GRPH8_DATA__GRPH_DATA_MASK 0xFFL
+-//CRTC8_IDX_1
+-#define CRTC8_IDX_1__VCRTC_IDX__SHIFT 0x0
+-#define CRTC8_IDX_1__VCRTC_IDX_MASK 0x3FL
+-//CRTC8_DATA_1
+-#define CRTC8_DATA_1__VCRTC_DATA__SHIFT 0x0
+-#define CRTC8_DATA_1__VCRTC_DATA_MASK 0xFFL
+-//GENFC_WT_1
+-#define GENFC_WT_1__VSYNC_SEL_W__SHIFT 0x3
+-#define GENFC_WT_1__VSYNC_SEL_W_MASK 0x08L
+-//GENS1_1
+-#define GENS1_1__NO_DISPLAY__SHIFT 0x0
+-#define GENS1_1__VGA_VSTATUS__SHIFT 0x3
+-#define GENS1_1__PIXEL_READ_BACK__SHIFT 0x4
+-#define GENS1_1__NO_DISPLAY_MASK 0x01L
+-#define GENS1_1__VGA_VSTATUS_MASK 0x08L
+-#define GENS1_1__PIXEL_READ_BACK_MASK 0x30L
+-//D3VGA_CONTROL
+-#define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT 0x0
+-#define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT 0x8
+-#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
+-#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
+-#define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT 0x18
+-#define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK 0x00000001L
+-#define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK 0x00000100L
+-#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L
+-#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L
+-#define D3VGA_CONTROL__D3VGA_ROTATE_MASK 0x03000000L
+-//D4VGA_CONTROL
+-#define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT 0x0
+-#define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT 0x8
+-#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
+-#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
+-#define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT 0x18
+-#define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK 0x00000001L
+-#define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK 0x00000100L
+-#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L
+-#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L
+-#define D4VGA_CONTROL__D4VGA_ROTATE_MASK 0x03000000L
+-//D5VGA_CONTROL
+-#define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT 0x0
+-#define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT 0x8
+-#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
+-#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
+-#define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT 0x18
+-#define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK 0x00000001L
+-#define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK 0x00000100L
+-#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L
+-#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L
+-#define D5VGA_CONTROL__D5VGA_ROTATE_MASK 0x03000000L
+-//D6VGA_CONTROL
+-#define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT 0x0
+-#define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT 0x8
+-#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
+-#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
+-#define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT 0x18
+-#define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK 0x00000001L
+-#define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK 0x00000100L
+-#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L
+-#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L
+-#define D6VGA_CONTROL__D6VGA_ROTATE_MASK 0x03000000L
+-//VGA_SOURCE_SELECT
+-#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT 0x0
+-#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT 0x8
+-#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK 0x00000007L
+-#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK 0x00000700L
+-//PHYPLLA_PIXCLK_RESYNC_CNTL
+-#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
+-#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
+-#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE__SHIFT 0x8
+-#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
+-#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
+-#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
+-#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE_MASK 0x00000100L
+-#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
+-//PHYPLLB_PIXCLK_RESYNC_CNTL
+-#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
+-#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
+-#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE__SHIFT 0x8
+-#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
+-#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
+-#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
+-#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK 0x00000100L
+-#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
+-//PHYPLLC_PIXCLK_RESYNC_CNTL
+-#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
+-#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
+-#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE__SHIFT 0x8
+-#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
+-#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
+-#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
+-#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE_MASK 0x00000100L
+-#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
+-//PHYPLLD_PIXCLK_RESYNC_CNTL
+-#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
+-#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
+-#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE__SHIFT 0x8
+-#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
+-#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
+-#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
+-#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE_MASK 0x00000100L
+-#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
+-//DCFEV0_CRTC_PIXEL_RATE_CNTL
+-#define DCFEV0_CRTC_PIXEL_RATE_CNTL__DCFEV0_CRTC_PIXEL_RATE_SOURCE__SHIFT 0x0
+-#define DCFEV0_CRTC_PIXEL_RATE_CNTL__DCFEV0_CRTC_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x8
+-#define DCFEV0_CRTC_PIXEL_RATE_CNTL__DCFEV0_CRTC_PIXEL_RATE_PLL_SOURCE__SHIFT 0xf
+-#define DCFEV0_CRTC_PIXEL_RATE_CNTL__DCFEV0_CRTC_PIXEL_RATE_SOURCE_MASK 0x00000003L
+-#define DCFEV0_CRTC_PIXEL_RATE_CNTL__DCFEV0_CRTC_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000700L
+-#define DCFEV0_CRTC_PIXEL_RATE_CNTL__DCFEV0_CRTC_PIXEL_RATE_PLL_SOURCE_MASK 0x00008000L
+-//DCFEV1_CRTC_PIXEL_RATE_CNTL
+-#define DCFEV1_CRTC_PIXEL_RATE_CNTL__DCFEV1_CRTC_PIXEL_RATE_SOURCE__SHIFT 0x0
+-#define DCFEV1_CRTC_PIXEL_RATE_CNTL__DCFEV1_CRTC_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x8
+-#define DCFEV1_CRTC_PIXEL_RATE_CNTL__DCFEV1_CRTC_PIXEL_RATE_PLL_SOURCE__SHIFT 0xf
+-#define DCFEV1_CRTC_PIXEL_RATE_CNTL__DCFEV1_CRTC_PIXEL_RATE_SOURCE_MASK 0x00000003L
+-#define DCFEV1_CRTC_PIXEL_RATE_CNTL__DCFEV1_CRTC_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000700L
+-#define DCFEV1_CRTC_PIXEL_RATE_CNTL__DCFEV1_CRTC_PIXEL_RATE_PLL_SOURCE_MASK 0x00008000L
+-//SYMCLKLPA_CLOCK_ENABLE
+-#define SYMCLKLPA_CLOCK_ENABLE__SYMCLKLPA_CLOCK_ENABLE__SHIFT 0x0
+-#define SYMCLKLPA_CLOCK_ENABLE__SYMCLKLPA_FE_FORCE_EN__SHIFT 0x4
+-#define SYMCLKLPA_CLOCK_ENABLE__SYMCLKLPA_FE_FORCE_SRC__SHIFT 0x8
+-#define SYMCLKLPA_CLOCK_ENABLE__SYMCLKLPA_CLOCK_ENABLE_MASK 0x00000001L
+-#define SYMCLKLPA_CLOCK_ENABLE__SYMCLKLPA_FE_FORCE_EN_MASK 0x00000010L
+-#define SYMCLKLPA_CLOCK_ENABLE__SYMCLKLPA_FE_FORCE_SRC_MASK 0x00000700L
+-//SYMCLKLPB_CLOCK_ENABLE
+-#define SYMCLKLPB_CLOCK_ENABLE__SYMCLKLPB_CLOCK_ENABLE__SHIFT 0x0
+-#define SYMCLKLPB_CLOCK_ENABLE__SYMCLKLPB_FE_FORCE_EN__SHIFT 0x4
+-#define SYMCLKLPB_CLOCK_ENABLE__SYMCLKLPB_FE_FORCE_SRC__SHIFT 0x8
+-#define SYMCLKLPB_CLOCK_ENABLE__SYMCLKLPB_CLOCK_ENABLE_MASK 0x00000001L
+-#define SYMCLKLPB_CLOCK_ENABLE__SYMCLKLPB_FE_FORCE_EN_MASK 0x00000010L
+-#define SYMCLKLPB_CLOCK_ENABLE__SYMCLKLPB_FE_FORCE_SRC_MASK 0x00000700L
+-//DPREFCLK_CGTT_BLK_CTRL_REG
+-#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY__SHIFT 0x0
+-#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY__SHIFT 0x4
+-#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY_MASK 0x0000000FL
+-#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY_MASK 0x00000FF0L
+-//REFCLK_CNTL
+-#define REFCLK_CNTL__REFCLK_CLOCK_EN__SHIFT 0x0
+-#define REFCLK_CNTL__REFCLK_SRC_SEL__SHIFT 0x1
+-#define REFCLK_CNTL__REFCLK_CLOCK_EN_MASK 0x00000001L
+-#define REFCLK_CNTL__REFCLK_SRC_SEL_MASK 0x00000002L
+-//MIPI_CLK_CNTL
+-#define MIPI_CLK_CNTL__DSICLK_CLOCK_ENABLE__SHIFT 0x0
+-#define MIPI_CLK_CNTL__BYTECLK_CLOCK_ENABLE__SHIFT 0x1
+-#define MIPI_CLK_CNTL__ESCCLK_CLOCK_ENABLE__SHIFT 0x2
+-#define MIPI_CLK_CNTL__DSICLK_CLOCK_ENABLE_MASK 0x00000001L
+-#define MIPI_CLK_CNTL__BYTECLK_CLOCK_ENABLE_MASK 0x00000002L
+-#define MIPI_CLK_CNTL__ESCCLK_CLOCK_ENABLE_MASK 0x00000004L
+-//REFCLK_CGTT_BLK_CTRL_REG
+-#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY__SHIFT 0x0
+-#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY__SHIFT 0x4
+-#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY_MASK 0x0000000FL
+-#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY_MASK 0x00000FF0L
+-//PHYPLLE_PIXCLK_RESYNC_CNTL
+-#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
+-#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
+-#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE__SHIFT 0x8
+-#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
+-#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
+-#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
+-#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE_MASK 0x00000100L
+-#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
+-//DCCG_PERFMON_CNTL2
+-#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE__SHIFT 0x0
+-#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE__SHIFT 0x1
+-#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE__SHIFT 0x2
+-#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE__SHIFT 0x3
+-#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE__SHIFT 0x4
+-#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE__SHIFT 0x5
+-#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE__SHIFT 0x6
+-#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE__SHIFT 0x7
+-#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE__SHIFT 0x8
+-#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE_MASK 0x00000001L
+-#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE_MASK 0x00000002L
+-#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE_MASK 0x00000004L
+-#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE_MASK 0x00000008L
+-#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE_MASK 0x00000010L
+-#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE_MASK 0x00000020L
+-#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE_MASK 0x00000040L
+-#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE_MASK 0x00000080L
+-#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE_MASK 0x00000100L
+-//DSICLK_CGTT_BLK_CTRL_REG
+-#define DSICLK_CGTT_BLK_CTRL_REG__DSICLK_TURN_ON_DELAY__SHIFT 0x0
+-#define DSICLK_CGTT_BLK_CTRL_REG__DSICLK_TURN_OFF_DELAY__SHIFT 0x4
+-#define DSICLK_CGTT_BLK_CTRL_REG__DSICLK_TURN_ON_DELAY_MASK 0x0000000FL
+-#define DSICLK_CGTT_BLK_CTRL_REG__DSICLK_TURN_OFF_DELAY_MASK 0x00000FF0L
+-//DCCG_CBUS_WRCMD_DELAY
+-#define DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY__SHIFT 0x0
+-#define DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY_MASK 0x0000000FL
+-//DCCG_DS_DTO_INCR
+-#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT 0x0
+-#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK 0xFFFFFFFFL
+-//DCCG_DS_DTO_MODULO
+-#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT 0x0
+-#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK 0xFFFFFFFFL
+-//DCCG_DS_CNTL
+-#define DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT 0x0
+-#define DCCG_DS_CNTL__DCCG_DS_REF_SRC__SHIFT 0x4
+-#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT 0x8
+-#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT 0x9
+-#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT 0x10
+-#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT 0x18
+-#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT 0x19
+-#define DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK 0x00000001L
+-#define DCCG_DS_CNTL__DCCG_DS_REF_SRC_MASK 0x00000030L
+-#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK 0x00000100L
+-#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK 0x00000200L
+-#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK 0x00030000L
+-#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK 0x01000000L
+-#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK 0x02000000L
+-//DCCG_DS_HW_CAL_INTERVAL
+-#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT 0x0
+-#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK 0xFFFFFFFFL
+-//SYMCLKG_CLOCK_ENABLE
+-#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_CLOCK_ENABLE__SHIFT 0x0
+-#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_EN__SHIFT 0x4
+-#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_SRC__SHIFT 0x8
+-#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_CLOCK_ENABLE_MASK 0x00000001L
+-#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_EN_MASK 0x00000010L
+-#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_SRC_MASK 0x00000700L
+-//DPREFCLK_CNTL
+-#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT 0x0
+-#define DPREFCLK_CNTL__UNB_DB_CLK_ENABLE__SHIFT 0x8
+-#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK 0x00000007L
+-#define DPREFCLK_CNTL__UNB_DB_CLK_ENABLE_MASK 0x00000100L
+-//AOMCLK0_CNTL
+-#define AOMCLK0_CNTL__AOMCLK0_CLOCK_EN__SHIFT 0x0
+-#define AOMCLK0_CNTL__AOMCLK0_CLOCK_EN_MASK 0x00000001L
+-//AOMCLK1_CNTL
+-#define AOMCLK1_CNTL__AOMCLK1_CLOCK_EN__SHIFT 0x0
+-#define AOMCLK1_CNTL__AOMCLK1_CLOCK_EN_MASK 0x00000001L
+-//AOMCLK2_CNTL
+-#define AOMCLK2_CNTL__AOMCLK2_CLOCK_EN__SHIFT 0x0
+-#define AOMCLK2_CNTL__AOMCLK2_CLOCK_EN_MASK 0x00000001L
+-//DCCG_AUDIO_DTO2_PHASE
+-#define DCCG_AUDIO_DTO2_PHASE__DCCG_AUDIO_DTO2_PHASE__SHIFT 0x0
+-#define DCCG_AUDIO_DTO2_PHASE__DCCG_AUDIO_DTO2_PHASE_MASK 0xFFFFFFFFL
+-//DCCG_AUDIO_DTO2_MODULO
+-#define DCCG_AUDIO_DTO2_MODULO__DCCG_AUDIO_DTO2_MODULO__SHIFT 0x0
+-#define DCCG_AUDIO_DTO2_MODULO__DCCG_AUDIO_DTO2_MODULO_MASK 0xFFFFFFFFL
+-//DCE_VERSION
+-#define DCE_VERSION__MAJOR_VERSION__SHIFT 0x0
+-#define DCE_VERSION__MINOR_VERSION__SHIFT 0x8
+-#define DCE_VERSION__MAJOR_VERSION_MASK 0x000000FFL
+-#define DCE_VERSION__MINOR_VERSION_MASK 0x0000FF00L
+-//PHYPLLG_PIXCLK_RESYNC_CNTL
+-#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
+-#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
+-#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_ENABLE__SHIFT 0x8
+-#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
+-#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
+-#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
+-#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_ENABLE_MASK 0x00000100L
+-#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
+-//DCCG_GTC_CNTL
+-#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT 0x0
+-#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK 0x00000001L
+-//DCCG_GTC_DTO_INCR
+-#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT 0x0
+-#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK 0xFFFFFFFFL
+-//DCCG_GTC_DTO_MODULO
+-#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT 0x0
+-#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK 0xFFFFFFFFL
+-//DCCG_GTC_CURRENT
+-#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT 0x0
+-#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK 0xFFFFFFFFL
+-//DENTIST_DISPCLK_CNTL
+-#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0
+-#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8
+-#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0xf
+-#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x11
+-#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x12
+-#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13
+-#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE__SHIFT 0x14
+-#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG__SHIFT 0x15
+-#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG__SHIFT 0x16
+-#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER__SHIFT 0x18
+-#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x0000007FL
+-#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x00007F00L
+-#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK 0x00018000L
+-#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK 0x00020000L
+-#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK 0x00040000L
+-#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x00080000L
+-#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE_MASK 0x00100000L
+-#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG_MASK 0x00200000L
+-#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG_MASK 0x00400000L
+-#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER_MASK 0x7F000000L
+-//MIPI_DTO_CNTL
+-#define MIPI_DTO_CNTL__MIPI_DTO_ENABLE__SHIFT 0x0
+-#define MIPI_DTO_CNTL__MIPI_DTO_ENABLE_MASK 0x00000001L
+-//MIPI_DTO_PHASE
+-#define MIPI_DTO_PHASE__MIPI_DTO_PHASE__SHIFT 0x0
+-#define MIPI_DTO_PHASE__MIPI_DTO_PHASE_MASK 0xFFFFFFFFL
+-//MIPI_DTO_MODULO
+-#define MIPI_DTO_MODULO__MIPI_DTO_MODULO__SHIFT 0x0
+-#define MIPI_DTO_MODULO__MIPI_DTO_MODULO_MASK 0xFFFFFFFFL
+-//DAC_CLK_ENABLE
+-#define DAC_CLK_ENABLE__DACA_CLK_ENABLE__SHIFT 0x0
+-#define DAC_CLK_ENABLE__DACB_CLK_ENABLE__SHIFT 0x4
+-#define DAC_CLK_ENABLE__DACA_CLK_ENABLE_MASK 0x00000001L
+-#define DAC_CLK_ENABLE__DACB_CLK_ENABLE_MASK 0x00000010L
+-//DVO_CLK_ENABLE
+-#define DVO_CLK_ENABLE__DVO_CLK_ENABLE__SHIFT 0x0
+-#define DVO_CLK_ENABLE__DVO_CLK_ENABLE_MASK 0x00000001L
+-//AVSYNC_COUNTER_WRITE
+-#define AVSYNC_COUNTER_WRITE__AVSYNC_COUNTER_WRVALUE__SHIFT 0x0
+-#define AVSYNC_COUNTER_WRITE__AVSYNC_COUNTER_WRVALUE_MASK 0xFFFFFFFFL
+-//AVSYNC_COUNTER_CONTROL
+-#define AVSYNC_COUNTER_CONTROL__AVSYNC_COUNTER_ENABLE__SHIFT 0x0
+-#define AVSYNC_COUNTER_CONTROL__AVSYNC_COUNTER_ENABLE_MASK 0x00000001L
+-//DMCU_SMU_INTERRUPT_CNTL
+-#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT__SHIFT 0x0
+-#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS__SHIFT 0x10
+-#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT_MASK 0x00000001L
+-#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS_MASK 0xFFFF0000L
+-//SMU_CONTROL
+-#define SMU_CONTROL__DISPLAY0_FORCE_VBI__SHIFT 0x0
+-#define SMU_CONTROL__DISPLAY1_FORCE_VBI__SHIFT 0x1
+-#define SMU_CONTROL__DISPLAY2_FORCE_VBI__SHIFT 0x2
+-#define SMU_CONTROL__DISPLAY3_FORCE_VBI__SHIFT 0x3
+-#define SMU_CONTROL__DISPLAY4_FORCE_VBI__SHIFT 0x4
+-#define SMU_CONTROL__DISPLAY5_FORCE_VBI__SHIFT 0x5
+-#define SMU_CONTROL__DISPLAY_V0_FORCE_VBI__SHIFT 0x6
+-#define SMU_CONTROL__DISPLAY_V1_FORCE_VBI__SHIFT 0x7
+-#define SMU_CONTROL__MCIF_WB_FORCE_VBI__SHIFT 0x8
+-#define SMU_CONTROL__DISPLAY0_FORCE_VBI_MASK 0x00000001L
+-#define SMU_CONTROL__DISPLAY1_FORCE_VBI_MASK 0x00000002L
+-#define SMU_CONTROL__DISPLAY2_FORCE_VBI_MASK 0x00000004L
+-#define SMU_CONTROL__DISPLAY3_FORCE_VBI_MASK 0x00000008L
+-#define SMU_CONTROL__DISPLAY4_FORCE_VBI_MASK 0x00000010L
+-#define SMU_CONTROL__DISPLAY5_FORCE_VBI_MASK 0x00000020L
+-#define SMU_CONTROL__DISPLAY_V0_FORCE_VBI_MASK 0x00000040L
+-#define SMU_CONTROL__DISPLAY_V1_FORCE_VBI_MASK 0x00000080L
+-#define SMU_CONTROL__MCIF_WB_FORCE_VBI_MASK 0x00000100L
+-//SMU_INTERRUPT_CONTROL
+-#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT 0x0
+-#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT 0x4
+-#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT 0x10
+-#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK 0x00000001L
+-#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK 0x00000010L
+-#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK 0xFFFF0000L
+-//AVSYNC_COUNTER_READ
+-#define AVSYNC_COUNTER_READ__AVSYNC_COUNTER_RDVALUE__SHIFT 0x0
+-#define AVSYNC_COUNTER_READ__AVSYNC_COUNTER_RDVALUE_MASK 0xFFFFFFFFL
+-//MILLISECOND_TIME_BASE_DIV
+-#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT 0x0
+-#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14
+-#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK 0x0001FFFFL
+-#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L
+-//DISPCLK_FREQ_CHANGE_CNTL
+-#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT 0x0
+-#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT 0x10
+-#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT 0x14
+-#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT 0x19
+-#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT 0x1c
+-#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT 0x1d
+-#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT 0x1e
+-#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT 0x1f
+-#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK 0x00003FFFL
+-#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK 0x000F0000L
+-#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK 0x00100000L
+-#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK 0x0E000000L
+-#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK 0x10000000L
+-#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK 0x20000000L
+-#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK 0x40000000L
+-#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK 0x80000000L
+-//DC_MEM_GLOBAL_PWR_REQ_CNTL
+-#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS__SHIFT 0x0
+-#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS_MASK 0x00000001L
+-//DCCG_PERFMON_CNTL
+-#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT 0x0
+-#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT 0x1
+-#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE__SHIFT 0x2
+-#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE__SHIFT 0x3
+-#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT 0x4
+-#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT 0x5
+-#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT 0x6
+-#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT 0x7
+-#define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL__SHIFT 0x8
+-#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV__SHIFT 0xb
+-#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK 0x00000001L
+-#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK 0x00000002L
+-#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE_MASK 0x00000004L
+-#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE_MASK 0x00000008L
+-#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK 0x00000010L
+-#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK 0x00000020L
+-#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK 0x00000040L
+-#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK 0x00000080L
+-#define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL_MASK 0x00000700L
+-#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV_MASK 0xFFFFF800L
+-//DCCG_GATE_DISABLE_CNTL
+-#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT 0x0
+-#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT 0x1
+-#define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE__SHIFT 0x2
+-#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT 0x3
+-#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT 0x4
+-#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE__SHIFT 0x5
+-#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT 0x6
+-#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE__SHIFT 0x8
+-#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT 0x11
+-#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT 0x12
+-#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT 0x13
+-#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE__SHIFT 0x15
+-#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT 0x16
+-#define DCCG_GATE_DISABLE_CNTL__UNB_DB_CLK_GATE_DISABLE__SHIFT 0x17
+-#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE__SHIFT 0x1a
+-#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE__SHIFT 0x1b
+-#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE__SHIFT 0x1c
+-#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE__SHIFT 0x1d
+-#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE__SHIFT 0x1e
+-#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK 0x00000001L
+-#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK 0x00000002L
+-#define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE_MASK 0x00000004L
+-#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK 0x00000008L
+-#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK 0x00000010L
+-#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE_MASK 0x00000020L
+-#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK 0x00000040L
+-#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE_MASK 0x00000100L
+-#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK 0x00020000L
+-#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK 0x00040000L
+-#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK 0x00080000L
+-#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE_MASK 0x00200000L
+-#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK 0x00400000L
+-#define DCCG_GATE_DISABLE_CNTL__UNB_DB_CLK_GATE_DISABLE_MASK 0x00800000L
+-#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE_MASK 0x04000000L
+-#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE_MASK 0x08000000L
+-#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE_MASK 0x10000000L
+-#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE_MASK 0x20000000L
+-#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE_MASK 0x40000000L
+-//DISPCLK_CGTT_BLK_CTRL_REG
+-#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT 0x0
+-#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT 0x4
+-#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK 0x0000000FL
+-#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK 0x00000FF0L
+-//SCLK_CGTT_BLK_CTRL_REG
+-#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY__SHIFT 0x0
+-#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY__SHIFT 0x4
+-#define SCLK_CGTT_BLK_CTRL_REG__CGTT_SCLK_OVERRIDE__SHIFT 0xc
+-#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY_MASK 0x0000000FL
+-#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY_MASK 0x00000FF0L
+-#define SCLK_CGTT_BLK_CTRL_REG__CGTT_SCLK_OVERRIDE_MASK 0x00001000L
+-//DCCG_CAC_STATUS
+-#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT 0x0
+-#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK 0xFFFFFFFFL
+-//PIXCLK1_RESYNC_CNTL
+-#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE__SHIFT 0x0
+-#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1__SHIFT 0x4
+-#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE_MASK 0x00000001L
+-#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1_MASK 0x00000030L
+-//PIXCLK2_RESYNC_CNTL
+-#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE__SHIFT 0x0
+-#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2__SHIFT 0x4
+-#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE_MASK 0x00000001L
+-#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2_MASK 0x00000030L
+-//PIXCLK0_RESYNC_CNTL
+-#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE__SHIFT 0x0
+-#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0__SHIFT 0x4
+-#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE_MASK 0x00000001L
+-#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0_MASK 0x00000030L
+-//MICROSECOND_TIME_BASE_DIV
+-#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT 0x0
+-#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x8
+-#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT 0x10
+-#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT 0x11
+-#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14
+-#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK 0x0000007FL
+-#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK 0x00007F00L
+-#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK 0x00010000L
+-#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK 0x00020000L
+-#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L
+-//DCCG_GATE_DISABLE_CNTL2
+-#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE__SHIFT 0x0
+-#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE__SHIFT 0x1
+-#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE__SHIFT 0x2
+-#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE__SHIFT 0x3
+-#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE__SHIFT 0x4
+-#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE__SHIFT 0x5
+-#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE__SHIFT 0x6
+-#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPA_FE_GATE_DISABLE__SHIFT 0x8
+-#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_FE_GATE_DISABLE__SHIFT 0x9
+-#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE__SHIFT 0x10
+-#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE__SHIFT 0x11
+-#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE__SHIFT 0x12
+-#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE__SHIFT 0x13
+-#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE__SHIFT 0x14
+-#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE__SHIFT 0x15
+-#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE__SHIFT 0x16
+-#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPA_GATE_DISABLE__SHIFT 0x18
+-#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_GATE_DISABLE__SHIFT 0x19
+-#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE_MASK 0x00000001L
+-#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE_MASK 0x00000002L
+-#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE_MASK 0x00000004L
+-#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE_MASK 0x00000008L
+-#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE_MASK 0x00000010L
+-#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE_MASK 0x00000020L
+-#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE_MASK 0x00000040L
+-#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPA_FE_GATE_DISABLE_MASK 0x00000100L
+-#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_FE_GATE_DISABLE_MASK 0x00000200L
+-#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE_MASK 0x00010000L
+-#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE_MASK 0x00020000L
+-#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE_MASK 0x00040000L
+-#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE_MASK 0x00080000L
+-#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE_MASK 0x00100000L
+-#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE_MASK 0x00200000L
+-#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE_MASK 0x00400000L
+-#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPA_GATE_DISABLE_MASK 0x01000000L
+-#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_GATE_DISABLE_MASK 0x02000000L
+-//SYMCLK_CGTT_BLK_CTRL_REG
+-#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY__SHIFT 0x0
+-#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY__SHIFT 0x4
+-#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY_MASK 0x0000000FL
+-#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY_MASK 0x00000FF0L
+-//PHYPLLF_PIXCLK_RESYNC_CNTL
+-#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
+-#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
+-#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE__SHIFT 0x8
+-#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
+-#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
+-#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
+-#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE_MASK 0x00000100L
+-#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
+-//DCCG_DISP_CNTL_REG
+-#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT 0x8
+-#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK 0x00000100L
+-//CRTC0_PIXEL_RATE_CNTL
+-#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE__SHIFT 0x0
+-#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT 0x4
+-#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT 0x5
+-#define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL__SHIFT 0x8
+-#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL__SHIFT 0x9
+-#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_HALF_RATE_EN__SHIFT 0xb
+-#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR__SHIFT 0xe
+-#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT__SHIFT 0x10
+-#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE_MASK 0x00000003L
+-#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK 0x00000010L
+-#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK 0x00000020L
+-#define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL_MASK 0x00000100L
+-#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL_MASK 0x00000200L
+-#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_HALF_RATE_EN_MASK 0x00000800L
+-#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR_MASK 0x0000C000L
+-#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT_MASK 0x0FFF0000L
+-//DP_DTO0_PHASE
+-#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT 0x0
+-#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK 0xFFFFFFFFL
+-//DP_DTO0_MODULO
+-#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT 0x0
+-#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK 0xFFFFFFFFL
+-//CRTC0_PHYPLL_PIXEL_RATE_CNTL
+-#define CRTC0_PHYPLL_PIXEL_RATE_CNTL__CRTC0_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0
+-#define CRTC0_PHYPLL_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4
+-#define CRTC0_PHYPLL_PIXEL_RATE_CNTL__CRTC0_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L
+-#define CRTC0_PHYPLL_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L
+-//CRTC1_PIXEL_RATE_CNTL
+-#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE__SHIFT 0x0
+-#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT 0x4
+-#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT 0x5
+-#define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL__SHIFT 0x8
+-#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL__SHIFT 0x9
+-#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_HALF_RATE_EN__SHIFT 0xb
+-#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR__SHIFT 0xe
+-#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT__SHIFT 0x10
+-#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE_MASK 0x00000003L
+-#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK 0x00000010L
+-#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK 0x00000020L
+-#define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL_MASK 0x00000100L
+-#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL_MASK 0x00000200L
+-#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_HALF_RATE_EN_MASK 0x00000800L
+-#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR_MASK 0x0000C000L
+-#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT_MASK 0x0FFF0000L
+-//DP_DTO1_PHASE
+-#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT 0x0
+-#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK 0xFFFFFFFFL
+-//DP_DTO1_MODULO
+-#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT 0x0
+-#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK 0xFFFFFFFFL
+-//CRTC1_PHYPLL_PIXEL_RATE_CNTL
+-#define CRTC1_PHYPLL_PIXEL_RATE_CNTL__CRTC1_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0
+-#define CRTC1_PHYPLL_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4
+-#define CRTC1_PHYPLL_PIXEL_RATE_CNTL__CRTC1_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L
+-#define CRTC1_PHYPLL_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L
+-//CRTC2_PIXEL_RATE_CNTL
+-#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE__SHIFT 0x0
+-#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT 0x4
+-#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT 0x5
+-#define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL__SHIFT 0x8
+-#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL__SHIFT 0x9
+-#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_HALF_RATE_EN__SHIFT 0xb
+-#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR__SHIFT 0xe
+-#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT__SHIFT 0x10
+-#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE_MASK 0x00000003L
+-#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK 0x00000010L
+-#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK 0x00000020L
+-#define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL_MASK 0x00000100L
+-#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL_MASK 0x00000200L
+-#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_HALF_RATE_EN_MASK 0x00000800L
+-#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR_MASK 0x0000C000L
+-#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT_MASK 0x0FFF0000L
+-//DP_DTO2_PHASE
+-#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT 0x0
+-#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK 0xFFFFFFFFL
+-//DP_DTO2_MODULO
+-#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT 0x0
+-#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK 0xFFFFFFFFL
+-//CRTC2_PHYPLL_PIXEL_RATE_CNTL
+-#define CRTC2_PHYPLL_PIXEL_RATE_CNTL__CRTC2_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0
+-#define CRTC2_PHYPLL_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4
+-#define CRTC2_PHYPLL_PIXEL_RATE_CNTL__CRTC2_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L
+-#define CRTC2_PHYPLL_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L
+-//CRTC3_PIXEL_RATE_CNTL
+-#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE__SHIFT 0x0
+-#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT 0x4
+-#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT 0x5
+-#define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL__SHIFT 0x8
+-#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL__SHIFT 0x9
+-#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_HALF_RATE_EN__SHIFT 0xb
+-#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR__SHIFT 0xe
+-#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT__SHIFT 0x10
+-#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE_MASK 0x00000003L
+-#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK 0x00000010L
+-#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK 0x00000020L
+-#define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL_MASK 0x00000100L
+-#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL_MASK 0x00000200L
+-#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_HALF_RATE_EN_MASK 0x00000800L
+-#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR_MASK 0x0000C000L
+-#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT_MASK 0x0FFF0000L
+-//DP_DTO3_PHASE
+-#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT 0x0
+-#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK 0xFFFFFFFFL
+-//DP_DTO3_MODULO
+-#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT 0x0
+-#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK 0xFFFFFFFFL
+-//CRTC3_PHYPLL_PIXEL_RATE_CNTL
+-#define CRTC3_PHYPLL_PIXEL_RATE_CNTL__CRTC3_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0
+-#define CRTC3_PHYPLL_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4
+-#define CRTC3_PHYPLL_PIXEL_RATE_CNTL__CRTC3_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L
+-#define CRTC3_PHYPLL_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L
+-//CRTC4_PIXEL_RATE_CNTL
+-#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE__SHIFT 0x0
+-#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE__SHIFT 0x4
+-#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE__SHIFT 0x5
+-#define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL__SHIFT 0x8
+-#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL__SHIFT 0x9
+-#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_HALF_RATE_EN__SHIFT 0xb
+-#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR__SHIFT 0xe
+-#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT__SHIFT 0x10
+-#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE_MASK 0x00000003L
+-#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE_MASK 0x00000010L
+-#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE_MASK 0x00000020L
+-#define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL_MASK 0x00000100L
+-#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL_MASK 0x00000200L
+-#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_HALF_RATE_EN_MASK 0x00000800L
+-#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR_MASK 0x0000C000L
+-#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT_MASK 0x0FFF0000L
+-//DP_DTO4_PHASE
+-#define DP_DTO4_PHASE__DP_DTO4_PHASE__SHIFT 0x0
+-#define DP_DTO4_PHASE__DP_DTO4_PHASE_MASK 0xFFFFFFFFL
+-//DP_DTO4_MODULO
+-#define DP_DTO4_MODULO__DP_DTO4_MODULO__SHIFT 0x0
+-#define DP_DTO4_MODULO__DP_DTO4_MODULO_MASK 0xFFFFFFFFL
+-//CRTC4_PHYPLL_PIXEL_RATE_CNTL
+-#define CRTC4_PHYPLL_PIXEL_RATE_CNTL__CRTC4_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0
+-#define CRTC4_PHYPLL_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4
+-#define CRTC4_PHYPLL_PIXEL_RATE_CNTL__CRTC4_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L
+-#define CRTC4_PHYPLL_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L
+-//CRTC5_PIXEL_RATE_CNTL
+-#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE__SHIFT 0x0
+-#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE__SHIFT 0x4
+-#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE__SHIFT 0x5
+-#define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL__SHIFT 0x8
+-#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL__SHIFT 0x9
+-#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_HALF_RATE_EN__SHIFT 0xb
+-#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR__SHIFT 0xe
+-#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT__SHIFT 0x10
+-#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE_MASK 0x00000003L
+-#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE_MASK 0x00000010L
+-#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE_MASK 0x00000020L
+-#define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL_MASK 0x00000100L
+-#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL_MASK 0x00000200L
+-#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_HALF_RATE_EN_MASK 0x00000800L
+-#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR_MASK 0x0000C000L
+-#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT_MASK 0x0FFF0000L
+-//DP_DTO5_PHASE
+-#define DP_DTO5_PHASE__DP_DTO5_PHASE__SHIFT 0x0
+-#define DP_DTO5_PHASE__DP_DTO5_PHASE_MASK 0xFFFFFFFFL
+-//DP_DTO5_MODULO
+-#define DP_DTO5_MODULO__DP_DTO5_MODULO__SHIFT 0x0
+-#define DP_DTO5_MODULO__DP_DTO5_MODULO_MASK 0xFFFFFFFFL
+-//CRTC5_PHYPLL_PIXEL_RATE_CNTL
+-#define CRTC5_PHYPLL_PIXEL_RATE_CNTL__CRTC5_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0
+-#define CRTC5_PHYPLL_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4
+-#define CRTC5_PHYPLL_PIXEL_RATE_CNTL__CRTC5_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L
+-#define CRTC5_PHYPLL_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L
+-//DCCG_SOFT_RESET
+-#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT 0x0
+-#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET__SHIFT 0x1
+-#define DCCG_SOFT_RESET__SOFT_RESET_DVO__SHIFT 0x2
+-#define DCCG_SOFT_RESET__DVO_ENABLE_RST__SHIFT 0x3
+-#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT 0x4
+-#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT 0x8
+-#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT 0xc
+-#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT 0xd
+-#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET__SHIFT 0xe
+-#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET__SHIFT 0xf
+-#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET__SHIFT 0x10
+-#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET__SHIFT 0x11
+-#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET__SHIFT 0x12
+-#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET__SHIFT 0x13
+-#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET__SHIFT 0x14
+-#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET__SHIFT 0x15
+-#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK 0x00000001L
+-#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET_MASK 0x00000002L
+-#define DCCG_SOFT_RESET__SOFT_RESET_DVO_MASK 0x00000004L
+-#define DCCG_SOFT_RESET__DVO_ENABLE_RST_MASK 0x00000008L
+-#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK 0x00000010L
+-#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK 0x00000100L
+-#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK 0x00001000L
+-#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK 0x00002000L
+-#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET_MASK 0x00004000L
+-#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET_MASK 0x00008000L
+-#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET_MASK 0x00010000L
+-#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET_MASK 0x00020000L
+-#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET_MASK 0x00040000L
+-#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET_MASK 0x00080000L
+-#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET_MASK 0x00100000L
+-#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET_MASK 0x00200000L
+-//SYMCLKA_CLOCK_ENABLE
+-#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT 0x0
+-#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT 0x4
+-#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT 0x8
+-#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK 0x00000001L
+-#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK 0x00000010L
+-#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK 0x00000700L
+-//SYMCLKB_CLOCK_ENABLE
+-#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT 0x0
+-#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT 0x4
+-#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT 0x8
+-#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK 0x00000001L
+-#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK 0x00000010L
+-#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK 0x00000700L
+-//SYMCLKC_CLOCK_ENABLE
+-#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT 0x0
+-#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT 0x4
+-#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT 0x8
+-#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK 0x00000001L
+-#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK 0x00000010L
+-#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK 0x00000700L
+-//SYMCLKD_CLOCK_ENABLE
+-#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT 0x0
+-#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT 0x4
+-#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT 0x8
+-#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK 0x00000001L
+-#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK 0x00000010L
+-#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK 0x00000700L
+-//SYMCLKE_CLOCK_ENABLE
+-#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT 0x0
+-#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT 0x4
+-#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT 0x8
+-#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK 0x00000001L
+-#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK 0x00000010L
+-#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK 0x00000700L
+-//SYMCLKF_CLOCK_ENABLE
+-#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE__SHIFT 0x0
+-#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN__SHIFT 0x4
+-#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC__SHIFT 0x8
+-#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE_MASK 0x00000001L
+-#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN_MASK 0x00000010L
+-#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC_MASK 0x00000700L
+-//DVOACLKD_CNTL
+-#define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL__SHIFT 0x0
+-#define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL__SHIFT 0x8
+-#define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN__SHIFT 0x10
+-#define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN__SHIFT 0x11
+-#define DVOACLKD_CNTL__DVOACLKD_IN_PHASE__SHIFT 0x12
+-#define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL_MASK 0x00000007L
+-#define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL_MASK 0x00001F00L
+-#define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN_MASK 0x00010000L
+-#define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN_MASK 0x00020000L
+-#define DVOACLKD_CNTL__DVOACLKD_IN_PHASE_MASK 0x00040000L
+-//DVOACLKC_MVP_CNTL
+-#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL__SHIFT 0x0
+-#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL__SHIFT 0x8
+-#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN__SHIFT 0x10
+-#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN__SHIFT 0x11
+-#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE__SHIFT 0x12
+-#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE__SHIFT 0x14
+-#define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL__SHIFT 0x18
+-#define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL__SHIFT 0x1c
+-#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL_MASK 0x00000007L
+-#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL_MASK 0x00001F00L
+-#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN_MASK 0x00010000L
+-#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN_MASK 0x00020000L
+-#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE_MASK 0x00040000L
+-#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_MASK 0x00100000L
+-#define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL_MASK 0x03000000L
+-#define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL_MASK 0x30000000L
+-//DVOACLKC_CNTL
+-#define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL__SHIFT 0x0
+-#define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL__SHIFT 0x8
+-#define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN__SHIFT 0x10
+-#define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN__SHIFT 0x11
+-#define DVOACLKC_CNTL__DVOACLKC_IN_PHASE__SHIFT 0x12
+-#define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL_MASK 0x00000007L
+-#define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL_MASK 0x00001F00L
+-#define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN_MASK 0x00010000L
+-#define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN_MASK 0x00020000L
+-#define DVOACLKC_CNTL__DVOACLKC_IN_PHASE_MASK 0x00040000L
+-//DCCG_AUDIO_DTO_SOURCE
+-#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT 0x0
+-#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT 0x4
+-#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL__SHIFT 0xc
+-#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN__SHIFT 0x10
+-#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT 0x14
+-#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT 0x18
+-#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT 0x1c
+-#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK 0x00000007L
+-#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK 0x00000030L
+-#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL_MASK 0x00003000L
+-#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN_MASK 0x00010000L
+-#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK 0x00100000L
+-#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK 0x01000000L
+-#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK 0x10000000L
+-//DCCG_AUDIO_DTO0_PHASE
+-#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT 0x0
+-#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK 0xFFFFFFFFL
+-//DCCG_AUDIO_DTO0_MODULE
+-#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT 0x0
+-#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK 0xFFFFFFFFL
+-//DCCG_AUDIO_DTO1_PHASE
+-#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT 0x0
+-#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK 0xFFFFFFFFL
+-//DCCG_AUDIO_DTO1_MODULE
+-#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT 0x0
+-#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK 0xFFFFFFFFL
+-//DCCG_TEST_CLK_SEL
+-#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT 0x0
+-#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT 0xc
+-#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT 0x10
+-#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT 0x1c
+-#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK 0x000001FFL
+-#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK 0x00001000L
+-#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK 0x01FF0000L
+-#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK 0x10000000L
+-//FBC_CNTL
+-#define FBC_CNTL__FBC_GRPH_COMP_EN__SHIFT 0x0
+-#define FBC_CNTL__FBC_SRC_SEL__SHIFT 0x1
+-#define FBC_CNTL__FBC_COMP_CLK_GATE_EN__SHIFT 0x8
+-#define FBC_CNTL__FBC_DECOMP_CLK_GATE_EN__SHIFT 0xa
+-#define FBC_CNTL__FBC_COHERENCY_MODE__SHIFT 0x10
+-#define FBC_CNTL__FBC_DS_ALLOW_DIS__SHIFT 0x18
+-#define FBC_CNTL__FBC_SOFT_COMPRESS_EN__SHIFT 0x19
+-#define FBC_CNTL__FBC_QOS_LEVEL__SHIFT 0x1a
+-#define FBC_CNTL__FBC_EN__SHIFT 0x1f
+-#define FBC_CNTL__FBC_GRPH_COMP_EN_MASK 0x00000001L
+-#define FBC_CNTL__FBC_SRC_SEL_MASK 0x0000000EL
+-#define FBC_CNTL__FBC_COMP_CLK_GATE_EN_MASK 0x00000100L
+-#define FBC_CNTL__FBC_DECOMP_CLK_GATE_EN_MASK 0x00000400L
+-#define FBC_CNTL__FBC_COHERENCY_MODE_MASK 0x00030000L
+-#define FBC_CNTL__FBC_DS_ALLOW_DIS_MASK 0x01000000L
+-#define FBC_CNTL__FBC_SOFT_COMPRESS_EN_MASK 0x02000000L
+-#define FBC_CNTL__FBC_QOS_LEVEL_MASK 0x3C000000L
+-#define FBC_CNTL__FBC_EN_MASK 0x80000000L
+-//FBC_IDLE_FORCE_CLEAR_MASK
+-#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK__SHIFT 0x0
+-#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK_MASK 0xFFFFFFFFL
+-//FBC_START_STOP_DELAY
+-#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY__SHIFT 0x0
+-#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY__SHIFT 0x7
+-#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY__SHIFT 0x8
+-#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY_MASK 0x0000001FL
+-#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY_MASK 0x00000080L
+-#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY_MASK 0x00001F00L
+-//FBC_COMP_CNTL
+-#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION__SHIFT 0x0
+-#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN__SHIFT 0x10
+-#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN__SHIFT 0x11
+-#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN__SHIFT 0x12
+-#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN__SHIFT 0x13
+-#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN__SHIFT 0x14
+-#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION_MASK 0x0000000FL
+-#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN_MASK 0x00010000L
+-#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN_MASK 0x00020000L
+-#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN_MASK 0x00040000L
+-#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN_MASK 0x00080000L
+-#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN_MASK 0x00100000L
+-//FBC_COMP_MODE
+-#define FBC_COMP_MODE__FBC_RLE_EN__SHIFT 0x0
+-#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN__SHIFT 0x8
+-#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN__SHIFT 0x9
+-#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN__SHIFT 0xa
+-#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN__SHIFT 0xb
+-#define FBC_COMP_MODE__FBC_IND_EN__SHIFT 0x10
+-#define FBC_COMP_MODE__FBC_RLE_EN_MASK 0x00000001L
+-#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN_MASK 0x00000100L
+-#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN_MASK 0x00000200L
+-#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN_MASK 0x00000400L
+-#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN_MASK 0x00000800L
+-#define FBC_COMP_MODE__FBC_IND_EN_MASK 0x00010000L
+-//FBC_IND_LUT0
+-#define FBC_IND_LUT0__FBC_IND_LUT0__SHIFT 0x0
+-#define FBC_IND_LUT0__FBC_IND_LUT0_MASK 0xFFFFFFFFL
+-//FBC_IND_LUT1
+-#define FBC_IND_LUT1__FBC_IND_LUT1__SHIFT 0x0
+-#define FBC_IND_LUT1__FBC_IND_LUT1_MASK 0xFFFFFFFFL
+-//FBC_IND_LUT2
+-#define FBC_IND_LUT2__FBC_IND_LUT2__SHIFT 0x0
+-#define FBC_IND_LUT2__FBC_IND_LUT2_MASK 0xFFFFFFFFL
+-//FBC_IND_LUT3
+-#define FBC_IND_LUT3__FBC_IND_LUT3__SHIFT 0x0
+-#define FBC_IND_LUT3__FBC_IND_LUT3_MASK 0xFFFFFFFFL
+-//FBC_IND_LUT4
+-#define FBC_IND_LUT4__FBC_IND_LUT4__SHIFT 0x0
+-#define FBC_IND_LUT4__FBC_IND_LUT4_MASK 0xFFFFFFFFL
+-//FBC_IND_LUT5
+-#define FBC_IND_LUT5__FBC_IND_LUT5__SHIFT 0x0
+-#define FBC_IND_LUT5__FBC_IND_LUT5_MASK 0xFFFFFFFFL
+-//FBC_IND_LUT6
+-#define FBC_IND_LUT6__FBC_IND_LUT6__SHIFT 0x0
+-#define FBC_IND_LUT6__FBC_IND_LUT6_MASK 0xFFFFFFFFL
+-//FBC_IND_LUT7
+-#define FBC_IND_LUT7__FBC_IND_LUT7__SHIFT 0x0
+-#define FBC_IND_LUT7__FBC_IND_LUT7_MASK 0xFFFFFFFFL
+-//FBC_IND_LUT8
+-#define FBC_IND_LUT8__FBC_IND_LUT8__SHIFT 0x0
+-#define FBC_IND_LUT8__FBC_IND_LUT8_MASK 0xFFFFFFFFL
+-//FBC_IND_LUT9
+-#define FBC_IND_LUT9__FBC_IND_LUT9__SHIFT 0x0
+-#define FBC_IND_LUT9__FBC_IND_LUT9_MASK 0xFFFFFFFFL
+-//FBC_IND_LUT10
+-#define FBC_IND_LUT10__FBC_IND_LUT10__SHIFT 0x0
+-#define FBC_IND_LUT10__FBC_IND_LUT10_MASK 0xFFFFFFFFL
+-//FBC_IND_LUT11
+-#define FBC_IND_LUT11__FBC_IND_LUT11__SHIFT 0x0
+-#define FBC_IND_LUT11__FBC_IND_LUT11_MASK 0xFFFFFFFFL
+-//FBC_IND_LUT12
+-#define FBC_IND_LUT12__FBC_IND_LUT12__SHIFT 0x0
+-#define FBC_IND_LUT12__FBC_IND_LUT12_MASK 0xFFFFFFFFL
+-//FBC_IND_LUT13
+-#define FBC_IND_LUT13__FBC_IND_LUT13__SHIFT 0x0
+-#define FBC_IND_LUT13__FBC_IND_LUT13_MASK 0xFFFFFFFFL
+-//FBC_IND_LUT14
+-#define FBC_IND_LUT14__FBC_IND_LUT14__SHIFT 0x0
+-#define FBC_IND_LUT14__FBC_IND_LUT14_MASK 0xFFFFFFFFL
+-//FBC_IND_LUT15
+-#define FBC_IND_LUT15__FBC_IND_LUT15__SHIFT 0x0
+-#define FBC_IND_LUT15__FBC_IND_LUT15_MASK 0xFFFFFFFFL
+-//FBC_CSM_REGION_OFFSET_01
+-#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0__SHIFT 0x0
+-#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1__SHIFT 0x10
+-#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0_MASK 0x00000FFFL
+-#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1_MASK 0x0FFF0000L
+-//FBC_CSM_REGION_OFFSET_23
+-#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2__SHIFT 0x0
+-#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3__SHIFT 0x10
+-#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2_MASK 0x00000FFFL
+-#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3_MASK 0x0FFF0000L
+-//FBC_CLIENT_REGION_MASK
+-#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK__SHIFT 0x10
+-#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK_MASK 0x000F0000L
+-//FBC_DEBUG_COMP
+-#define FBC_DEBUG_COMP__FBC_COMP_SWAP__SHIFT 0x0
+-#define FBC_DEBUG_COMP__FBC_COMP_RSIZE__SHIFT 0x3
+-#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS__SHIFT 0x4
+-#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL__SHIFT 0x8
+-#define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE__SHIFT 0xa
+-#define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE__SHIFT 0xb
+-#define FBC_DEBUG_COMP__FBC_COMP_SWAP_MASK 0x00000003L
+-#define FBC_DEBUG_COMP__FBC_COMP_RSIZE_MASK 0x00000008L
+-#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS_MASK 0x000000F0L
+-#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL_MASK 0x00000300L
+-#define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE_MASK 0x00000400L
+-#define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE_MASK 0x00000800L
+-//FBC_MISC
+-#define FBC_MISC__FBC_DECOMPRESS_ERROR__SHIFT 0x0
+-#define FBC_MISC__FBC_STOP_ON_ERROR__SHIFT 0x2
+-#define FBC_MISC__FBC_INVALIDATE_ON_ERROR__SHIFT 0x3
+-#define FBC_MISC__FBC_ERROR_PIXEL__SHIFT 0x4
+-#define FBC_MISC__FBC_DIVIDE_X__SHIFT 0x8
+-#define FBC_MISC__FBC_DIVIDE_Y__SHIFT 0xa
+-#define FBC_MISC__FBC_RSM_WRITE_VALUE__SHIFT 0xb
+-#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY__SHIFT 0xc
+-#define FBC_MISC__FBC_STOP_ON_HFLIP_EVENT__SHIFT 0xd
+-#define FBC_MISC__FBC_STOP_COMP_ON_INVALIDATE__SHIFT 0xe
+-#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR__SHIFT 0x10
+-#define FBC_MISC__FBC_RESET_AT_ENABLE__SHIFT 0x14
+-#define FBC_MISC__FBC_RESET_AT_DISABLE__SHIFT 0x15
+-#define FBC_MISC__FBC_SLOW_REQ_INTERVAL__SHIFT 0x18
+-#define FBC_MISC__FBC_FORCE_DECOMPRESSOR_EN__SHIFT 0x1f
+-#define FBC_MISC__FBC_DECOMPRESS_ERROR_MASK 0x00000003L
+-#define FBC_MISC__FBC_STOP_ON_ERROR_MASK 0x00000004L
+-#define FBC_MISC__FBC_INVALIDATE_ON_ERROR_MASK 0x00000008L
+-#define FBC_MISC__FBC_ERROR_PIXEL_MASK 0x000000F0L
+-#define FBC_MISC__FBC_DIVIDE_X_MASK 0x00000300L
+-#define FBC_MISC__FBC_DIVIDE_Y_MASK 0x00000400L
+-#define FBC_MISC__FBC_RSM_WRITE_VALUE_MASK 0x00000800L
+-#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY_MASK 0x00001000L
+-#define FBC_MISC__FBC_STOP_ON_HFLIP_EVENT_MASK 0x00002000L
+-#define FBC_MISC__FBC_STOP_COMP_ON_INVALIDATE_MASK 0x00004000L
+-#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR_MASK 0x00010000L
+-#define FBC_MISC__FBC_RESET_AT_ENABLE_MASK 0x00100000L
+-#define FBC_MISC__FBC_RESET_AT_DISABLE_MASK 0x00200000L
+-#define FBC_MISC__FBC_SLOW_REQ_INTERVAL_MASK 0x1F000000L
+-#define FBC_MISC__FBC_FORCE_DECOMPRESSOR_EN_MASK 0x80000000L
+-//FBC_STATUS
+-#define FBC_STATUS__FBC_ENABLE_STATUS__SHIFT 0x0
+-#define FBC_STATUS__FBC_ENABLE_STATUS_SW__SHIFT 0x4
+-#define FBC_STATUS__FBC_COMPRESSION_ENABLE_STATUS__SHIFT 0x8
+-#define FBC_STATUS__FBC_DECOMPRESSION_ENABLE_STATUS__SHIFT 0xc
+-#define FBC_STATUS__FBC_ENABLE_STATUS_MASK 0x00000001L
+-#define FBC_STATUS__FBC_ENABLE_STATUS_SW_MASK 0x00000010L
+-#define FBC_STATUS__FBC_COMPRESSION_ENABLE_STATUS_MASK 0x00000100L
+-#define FBC_STATUS__FBC_DECOMPRESSION_ENABLE_STATUS_MASK 0x00001000L
+-//FBC_ALPHA_CNTL
+-#define FBC_ALPHA_CNTL__FBC_ALPHA_COMP_EN__SHIFT 0x0
+-#define FBC_ALPHA_CNTL__FBC_FORCE_COPY_TO_COMP_BUF__SHIFT 0x4
+-#define FBC_ALPHA_CNTL__FBC_ZERO_ALPHA_CHUNK_SKIP_EN__SHIFT 0x8
+-#define FBC_ALPHA_CNTL__FBC_ALPHA_COMP_EN_MASK 0x00000001L
+-#define FBC_ALPHA_CNTL__FBC_FORCE_COPY_TO_COMP_BUF_MASK 0x00000010L
+-#define FBC_ALPHA_CNTL__FBC_ZERO_ALPHA_CHUNK_SKIP_EN_MASK 0x00000100L
+-//FBC_ALPHA_RGB_OVERRIDE
+-#define FBC_ALPHA_RGB_OVERRIDE__FBC_ZERO_ALPHA_R_VAL__SHIFT 0x0
+-#define FBC_ALPHA_RGB_OVERRIDE__FBC_ZERO_ALPHA_G_VAL__SHIFT 0xc
+-#define FBC_ALPHA_RGB_OVERRIDE__FBC_ZERO_ALPHA_B_VAL__SHIFT 0x18
+-#define FBC_ALPHA_RGB_OVERRIDE__FBC_ZERO_ALPHA_R_VAL_MASK 0x000000FFL
+-#define FBC_ALPHA_RGB_OVERRIDE__FBC_ZERO_ALPHA_G_VAL_MASK 0x000FF000L
+-#define FBC_ALPHA_RGB_OVERRIDE__FBC_ZERO_ALPHA_B_VAL_MASK 0xFF000000L
+-//PIPE0_PG_CONFIG
+-#define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0
+-#define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x00000001L
+-//PIPE0_PG_ENABLE
+-#define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0
+-#define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x00000001L
+-//PIPE0_PG_STATUS
+-#define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
+-#define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS__SHIFT 0x1e
+-#define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000L
+-#define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS_MASK 0xC0000000L
+-//PIPE1_PG_CONFIG
+-#define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON__SHIFT 0x0
+-#define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON_MASK 0x00000001L
+-//PIPE1_PG_ENABLE
+-#define PIPE1_PG_ENABLE__PIPE1_POWER_GATE__SHIFT 0x0
+-#define PIPE1_PG_ENABLE__PIPE1_POWER_GATE_MASK 0x00000001L
+-//PIPE1_PG_STATUS
+-#define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE__SHIFT 0x1c
+-#define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS__SHIFT 0x1e
+-#define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE_MASK 0x10000000L
+-#define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS_MASK 0xC0000000L
+-//PIPE2_PG_CONFIG
+-#define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON__SHIFT 0x0
+-#define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON_MASK 0x00000001L
+-//PIPE2_PG_ENABLE
+-#define PIPE2_PG_ENABLE__PIPE2_POWER_GATE__SHIFT 0x0
+-#define PIPE2_PG_ENABLE__PIPE2_POWER_GATE_MASK 0x00000001L
+-//PIPE2_PG_STATUS
+-#define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE__SHIFT 0x1c
+-#define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS__SHIFT 0x1e
+-#define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE_MASK 0x10000000L
+-#define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS_MASK 0xC0000000L
+-//PIPE3_PG_CONFIG
+-#define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON__SHIFT 0x0
+-#define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON_MASK 0x00000001L
+-//PIPE3_PG_ENABLE
+-#define PIPE3_PG_ENABLE__PIPE3_POWER_GATE__SHIFT 0x0
+-#define PIPE3_PG_ENABLE__PIPE3_POWER_GATE_MASK 0x00000001L
+-//PIPE3_PG_STATUS
+-#define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE__SHIFT 0x1c
+-#define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS__SHIFT 0x1e
+-#define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE_MASK 0x10000000L
+-#define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS_MASK 0xC0000000L
+-//PIPE4_PG_CONFIG
+-#define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON__SHIFT 0x0
+-#define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON_MASK 0x00000001L
+-//PIPE4_PG_ENABLE
+-#define PIPE4_PG_ENABLE__PIPE4_POWER_GATE__SHIFT 0x0
+-#define PIPE4_PG_ENABLE__PIPE4_POWER_GATE_MASK 0x00000001L
+-//PIPE4_PG_STATUS
+-#define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE__SHIFT 0x1c
+-#define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS__SHIFT 0x1e
+-#define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE_MASK 0x10000000L
+-#define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS_MASK 0xC0000000L
+-//PIPE5_PG_CONFIG
+-#define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON__SHIFT 0x0
+-#define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON_MASK 0x00000001L
+-//PIPE5_PG_ENABLE
+-#define PIPE5_PG_ENABLE__PIPE5_POWER_GATE__SHIFT 0x0
+-#define PIPE5_PG_ENABLE__PIPE5_POWER_GATE_MASK 0x00000001L
+-//PIPE5_PG_STATUS
+-#define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE__SHIFT 0x1c
+-#define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS__SHIFT 0x1e
+-#define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE_MASK 0x10000000L
+-#define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS_MASK 0xC0000000L
+-//DSI_PG_CONFIG
+-#define DSI_PG_CONFIG__DSI_POWER_FORCEON__SHIFT 0x0
+-#define DSI_PG_CONFIG__DSI_POWER_FORCEON_MASK 0x00000001L
+-//DSI_PG_ENABLE
+-#define DSI_PG_ENABLE__DSI_POWER_GATE__SHIFT 0x0
+-#define DSI_PG_ENABLE__DSI_POWER_GATE_MASK 0x00000001L
+-//DSI_PG_STATUS
+-#define DSI_PG_STATUS__DSI_DESIRED_PWR_STATE__SHIFT 0x1c
+-#define DSI_PG_STATUS__DSI_PGFSM_PWR_STATUS__SHIFT 0x1e
+-#define DSI_PG_STATUS__DSI_DESIRED_PWR_STATE_MASK 0x10000000L
+-#define DSI_PG_STATUS__DSI_PGFSM_PWR_STATUS_MASK 0xC0000000L
+-//DCFEV0_PG_CONFIG
+-#define DCFEV0_PG_CONFIG__DCFEV0_POWER_FORCEON__SHIFT 0x0
+-#define DCFEV0_PG_CONFIG__DCFEV0_POWER_FORCEON_MASK 0x00000001L
+-//DCFEV0_PG_ENABLE
+-#define DCFEV0_PG_ENABLE__DCFEV0_POWER_GATE__SHIFT 0x0
+-#define DCFEV0_PG_ENABLE__DCFEV0_POWER_GATE_MASK 0x00000001L
+-//DCFEV0_PG_STATUS
+-#define DCFEV0_PG_STATUS__DCFEV0_DESIRED_PWR_STATE__SHIFT 0x1c
+-#define DCFEV0_PG_STATUS__DCFEV0_PGFSM_PWR_STATUS__SHIFT 0x1e
+-#define DCFEV0_PG_STATUS__DCFEV0_DESIRED_PWR_STATE_MASK 0x10000000L
+-#define DCFEV0_PG_STATUS__DCFEV0_PGFSM_PWR_STATUS_MASK 0xC0000000L
+-//DCPG_INTERRUPT_STATUS
+-#define DCPG_INTERRUPT_STATUS__DCFE0_POWER_UP_INT_OCCURRED__SHIFT 0x0
+-#define DCPG_INTERRUPT_STATUS__DCFE0_POWER_DOWN_INT_OCCURRED__SHIFT 0x1
+-#define DCPG_INTERRUPT_STATUS__DCFE1_POWER_UP_INT_OCCURRED__SHIFT 0x2
+-#define DCPG_INTERRUPT_STATUS__DCFE1_POWER_DOWN_INT_OCCURRED__SHIFT 0x3
+-#define DCPG_INTERRUPT_STATUS__DCFE2_POWER_UP_INT_OCCURRED__SHIFT 0x4
+-#define DCPG_INTERRUPT_STATUS__DCFE2_POWER_DOWN_INT_OCCURRED__SHIFT 0x5
+-#define DCPG_INTERRUPT_STATUS__DCFE3_POWER_UP_INT_OCCURRED__SHIFT 0x6
+-#define DCPG_INTERRUPT_STATUS__DCFE3_POWER_DOWN_INT_OCCURRED__SHIFT 0x7
+-#define DCPG_INTERRUPT_STATUS__DCFE4_POWER_UP_INT_OCCURRED__SHIFT 0x8
+-#define DCPG_INTERRUPT_STATUS__DCFE4_POWER_DOWN_INT_OCCURRED__SHIFT 0x9
+-#define DCPG_INTERRUPT_STATUS__DCFE5_POWER_UP_INT_OCCURRED__SHIFT 0xa
+-#define DCPG_INTERRUPT_STATUS__DCFE5_POWER_DOWN_INT_OCCURRED__SHIFT 0xb
+-#define DCPG_INTERRUPT_STATUS__DCFEV0_POWER_UP_INT_OCCURRED__SHIFT 0xc
+-#define DCPG_INTERRUPT_STATUS__DCFEV0_POWER_DOWN_INT_OCCURRED__SHIFT 0xd
+-#define DCPG_INTERRUPT_STATUS__DSI_POWER_UP_INT_OCCURRED__SHIFT 0xe
+-#define DCPG_INTERRUPT_STATUS__DSI_POWER_DOWN_INT_OCCURRED__SHIFT 0xf
+-#define DCPG_INTERRUPT_STATUS__DCFEV1_POWER_UP_INT_OCCURRED__SHIFT 0x10
+-#define DCPG_INTERRUPT_STATUS__DCFEV1_POWER_DOWN_INT_OCCURRED__SHIFT 0x11
+-#define DCPG_INTERRUPT_STATUS__DCFE0_POWER_UP_INT_OCCURRED_MASK 0x00000001L
+-#define DCPG_INTERRUPT_STATUS__DCFE0_POWER_DOWN_INT_OCCURRED_MASK 0x00000002L
+-#define DCPG_INTERRUPT_STATUS__DCFE1_POWER_UP_INT_OCCURRED_MASK 0x00000004L
+-#define DCPG_INTERRUPT_STATUS__DCFE1_POWER_DOWN_INT_OCCURRED_MASK 0x00000008L
+-#define DCPG_INTERRUPT_STATUS__DCFE2_POWER_UP_INT_OCCURRED_MASK 0x00000010L
+-#define DCPG_INTERRUPT_STATUS__DCFE2_POWER_DOWN_INT_OCCURRED_MASK 0x00000020L
+-#define DCPG_INTERRUPT_STATUS__DCFE3_POWER_UP_INT_OCCURRED_MASK 0x00000040L
+-#define DCPG_INTERRUPT_STATUS__DCFE3_POWER_DOWN_INT_OCCURRED_MASK 0x00000080L
+-#define DCPG_INTERRUPT_STATUS__DCFE4_POWER_UP_INT_OCCURRED_MASK 0x00000100L
+-#define DCPG_INTERRUPT_STATUS__DCFE4_POWER_DOWN_INT_OCCURRED_MASK 0x00000200L
+-#define DCPG_INTERRUPT_STATUS__DCFE5_POWER_UP_INT_OCCURRED_MASK 0x00000400L
+-#define DCPG_INTERRUPT_STATUS__DCFE5_POWER_DOWN_INT_OCCURRED_MASK 0x00000800L
+-#define DCPG_INTERRUPT_STATUS__DCFEV0_POWER_UP_INT_OCCURRED_MASK 0x00001000L
+-#define DCPG_INTERRUPT_STATUS__DCFEV0_POWER_DOWN_INT_OCCURRED_MASK 0x00002000L
+-#define DCPG_INTERRUPT_STATUS__DSI_POWER_UP_INT_OCCURRED_MASK 0x00004000L
+-#define DCPG_INTERRUPT_STATUS__DSI_POWER_DOWN_INT_OCCURRED_MASK 0x00008000L
+-#define DCPG_INTERRUPT_STATUS__DCFEV1_POWER_UP_INT_OCCURRED_MASK 0x00010000L
+-#define DCPG_INTERRUPT_STATUS__DCFEV1_POWER_DOWN_INT_OCCURRED_MASK 0x00020000L
+-//DCPG_INTERRUPT_CONTROL
+-#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_UP_INT_MASK__SHIFT 0x0
+-#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_UP_INT_CLEAR__SHIFT 0x1
+-#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_MASK__SHIFT 0x2
+-#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_CLEAR__SHIFT 0x3
+-#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_MASK__SHIFT 0x4
+-#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_CLEAR__SHIFT 0x5
+-#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_DOWN_INT_MASK__SHIFT 0x6
+-#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_DOWN_INT_CLEAR__SHIFT 0x7
+-#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_MASK__SHIFT 0x8
+-#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_CLEAR__SHIFT 0x9
+-#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_MASK__SHIFT 0xa
+-#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_CLEAR__SHIFT 0xb
+-#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_UP_INT_MASK__SHIFT 0xc
+-#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_UP_INT_CLEAR__SHIFT 0xd
+-#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_DOWN_INT_MASK__SHIFT 0xe
+-#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_DOWN_INT_CLEAR__SHIFT 0xf
+-#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_MASK__SHIFT 0x10
+-#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_CLEAR__SHIFT 0x11
+-#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_DOWN_INT_MASK__SHIFT 0x12
+-#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_DOWN_INT_CLEAR__SHIFT 0x13
+-#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_UP_INT_MASK__SHIFT 0x14
+-#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_UP_INT_CLEAR__SHIFT 0x15
+-#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_DOWN_INT_MASK__SHIFT 0x16
+-#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_DOWN_INT_CLEAR__SHIFT 0x17
+-#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_UP_INT_MASK__SHIFT 0x18
+-#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_UP_INT_CLEAR__SHIFT 0x19
+-#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_DOWN_INT_MASK__SHIFT 0x1a
+-#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_DOWN_INT_CLEAR__SHIFT 0x1b
+-#define DCPG_INTERRUPT_CONTROL__DSI_POWER_UP_INT_MASK__SHIFT 0x1c
+-#define DCPG_INTERRUPT_CONTROL__DSI_POWER_UP_INT_CLEAR__SHIFT 0x1d
+-#define DCPG_INTERRUPT_CONTROL__DSI_POWER_DOWN_INT_MASK__SHIFT 0x1e
+-#define DCPG_INTERRUPT_CONTROL__DSI_POWER_DOWN_INT_CLEAR__SHIFT 0x1f
+-#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_UP_INT_MASK_MASK 0x00000001L
+-#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_UP_INT_CLEAR_MASK 0x00000002L
+-#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_MASK_MASK 0x00000004L
+-#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_CLEAR_MASK 0x00000008L
+-#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_MASK_MASK 0x00000010L
+-#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_CLEAR_MASK 0x00000020L
+-#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_DOWN_INT_MASK_MASK 0x00000040L
+-#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_DOWN_INT_CLEAR_MASK 0x00000080L
+-#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_MASK_MASK 0x00000100L
+-#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_CLEAR_MASK 0x00000200L
+-#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_MASK_MASK 0x00000400L
+-#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_CLEAR_MASK 0x00000800L
+-#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_UP_INT_MASK_MASK 0x00001000L
+-#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_UP_INT_CLEAR_MASK 0x00002000L
+-#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_DOWN_INT_MASK_MASK 0x00004000L
+-#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_DOWN_INT_CLEAR_MASK 0x00008000L
+-#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_MASK_MASK 0x00010000L
+-#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_CLEAR_MASK 0x00020000L
+-#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_DOWN_INT_MASK_MASK 0x00040000L
+-#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_DOWN_INT_CLEAR_MASK 0x00080000L
+-#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_UP_INT_MASK_MASK 0x00100000L
+-#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_UP_INT_CLEAR_MASK 0x00200000L
+-#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_DOWN_INT_MASK_MASK 0x00400000L
+-#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_DOWN_INT_CLEAR_MASK 0x00800000L
+-#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_UP_INT_MASK_MASK 0x01000000L
+-#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_UP_INT_CLEAR_MASK 0x02000000L
+-#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_DOWN_INT_MASK_MASK 0x04000000L
+-#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_DOWN_INT_CLEAR_MASK 0x08000000L
+-#define DCPG_INTERRUPT_CONTROL__DSI_POWER_UP_INT_MASK_MASK 0x10000000L
+-#define DCPG_INTERRUPT_CONTROL__DSI_POWER_UP_INT_CLEAR_MASK 0x20000000L
+-#define DCPG_INTERRUPT_CONTROL__DSI_POWER_DOWN_INT_MASK_MASK 0x40000000L
+-#define DCPG_INTERRUPT_CONTROL__DSI_POWER_DOWN_INT_CLEAR_MASK 0x80000000L
+-//DCPG_INTERRUPT_CONTROL2
+-#define DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_UP_INT_MASK__SHIFT 0x18
+-#define DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_UP_INT_CLEAR__SHIFT 0x19
+-#define DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_DOWN_INT_MASK__SHIFT 0x1a
+-#define DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_DOWN_INT_CLEAR__SHIFT 0x1b
+-#define DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_UP_INT_MASK_MASK 0x01000000L
+-#define DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_UP_INT_CLEAR_MASK 0x02000000L
+-#define DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_DOWN_INT_MASK_MASK 0x04000000L
+-#define DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_DOWN_INT_CLEAR_MASK 0x08000000L
+-//DCFEV1_PG_CONFIG
+-#define DCFEV1_PG_CONFIG__DCFEV1_POWER_FORCEON__SHIFT 0x0
+-#define DCFEV1_PG_CONFIG__DCFEV1_POWER_FORCEON_MASK 0x00000001L
+-//DCFEV1_PG_ENABLE
+-#define DCFEV1_PG_ENABLE__DCFEV1_POWER_GATE__SHIFT 0x0
+-#define DCFEV1_PG_ENABLE__DCFEV1_POWER_GATE_MASK 0x00000001L
+-//DCFEV1_PG_STATUS
+-#define DCFEV1_PG_STATUS__DCFEV1_DESIRED_PWR_STATE__SHIFT 0x1c
+-#define DCFEV1_PG_STATUS__DCFEV1_PGFSM_PWR_STATUS__SHIFT 0x1e
+-#define DCFEV1_PG_STATUS__DCFEV1_DESIRED_PWR_STATE_MASK 0x10000000L
+-#define DCFEV1_PG_STATUS__DCFEV1_PGFSM_PWR_STATUS_MASK 0xC0000000L
+-//DC_IP_REQUEST_CNTL
+-#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT 0x0
+-#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK 0x00000001L
+-//DC_PGCNTL_STATUS_REG
+-//DMIFV_STATUS
+-#define DMIFV_STATUS__DMIFV_MC_SEND_ON_IDLE__SHIFT 0x0
+-#define DMIFV_STATUS__DMIFV_CLEAR_MC_SEND_ON_IDLE__SHIFT 0x8
+-#define DMIFV_STATUS__DMIFV_MC_SEND_ON_IDLE_MASK 0x0000000FL
+-#define DMIFV_STATUS__DMIFV_CLEAR_MC_SEND_ON_IDLE_MASK 0x00000F00L
+-//DMIF_CONTROL
+-#define DMIF_CONTROL__DMIF_BUFF_SIZE__SHIFT 0x0
+-#define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK__SHIFT 0x2
+-#define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT__SHIFT 0x4
+-#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE__SHIFT 0x8
+-#define DMIF_CONTROL__DMIF_UNDERFLOW_RECOVERY_EN__SHIFT 0xb
+-#define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE__SHIFT 0xc
+-#define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS__SHIFT 0x11
+-#define DMIF_CONTROL__DMIF_DELAY_ARBITRATION__SHIFT 0x18
+-#define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN__SHIFT 0x1d
+-#define DMIF_CONTROL__DMIF_PSTATE_URGENT_DISABLE__SHIFT 0x1f
+-#define DMIF_CONTROL__DMIF_BUFF_SIZE_MASK 0x00000003L
+-#define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK_MASK 0x00000004L
+-#define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT_MASK 0x00000010L
+-#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE_MASK 0x00000700L
+-#define DMIF_CONTROL__DMIF_UNDERFLOW_RECOVERY_EN_MASK 0x00000800L
+-#define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE_MASK 0x0001F000L
+-#define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS_MASK 0x007E0000L
+-#define DMIF_CONTROL__DMIF_DELAY_ARBITRATION_MASK 0x1F000000L
+-#define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN_MASK 0x60000000L
+-#define DMIF_CONTROL__DMIF_PSTATE_URGENT_DISABLE_MASK 0x80000000L
+-//DMIF_STATUS
+-#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE__SHIFT 0x0
+-#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE__SHIFT 0x8
+-#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0xf
+-#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x10
+-#define DMIF_STATUS__DMIF_PIPE_EN_FBC_CHUNK_TRACKER__SHIFT 0x11
+-#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT__SHIFT 0x14
+-#define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT__SHIFT 0x18
+-#define DMIF_STATUS__DMIF_UNDERFLOW__SHIFT 0x1c
+-#define DMIF_STATUS__DMIF_MC_LATENCY_TAP_POINT__SHIFT 0x1d
+-#define DMIF_STATUS__DMIF_MC_LATENCY_REQ_TYPE__SHIFT 0x1f
+-#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE_MASK 0x0000003FL
+-#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE_MASK 0x00003F00L
+-#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x00008000L
+-#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x00010000L
+-#define DMIF_STATUS__DMIF_PIPE_EN_FBC_CHUNK_TRACKER_MASK 0x000E0000L
+-#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT_MASK 0x00F00000L
+-#define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT_MASK 0x0F000000L
+-#define DMIF_STATUS__DMIF_UNDERFLOW_MASK 0x10000000L
+-#define DMIF_STATUS__DMIF_MC_LATENCY_TAP_POINT_MASK 0x60000000L
+-#define DMIF_STATUS__DMIF_MC_LATENCY_REQ_TYPE_MASK 0x80000000L
+-//DMIF_ARBITRATION_CONTROL
+-#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD__SHIFT 0x0
+-#define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT__SHIFT 0x10
+-#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD_MASK 0x0000FFFFL
+-#define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT_MASK 0xFFFF0000L
+-//PIPE0_ARBITRATION_CONTROL3
+-#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
+-#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000FFFFL
+-//PIPE1_ARBITRATION_CONTROL3
+-#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
+-#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000FFFFL
+-//PIPE2_ARBITRATION_CONTROL3
+-#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
+-#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000FFFFL
+-//PIPE3_ARBITRATION_CONTROL3
+-#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
+-#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000FFFFL
+-//PIPE4_ARBITRATION_CONTROL3
+-#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
+-#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000FFFFL
+-//PIPE5_ARBITRATION_CONTROL3
+-#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
+-#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000FFFFL
+-//DMIF_P_VMID
+-#define DMIF_P_VMID__P_VMID_PIPE0__SHIFT 0x0
+-#define DMIF_P_VMID__P_VMID_PIPE1__SHIFT 0x4
+-#define DMIF_P_VMID__P_VMID_PIPE2__SHIFT 0x8
+-#define DMIF_P_VMID__P_VMID_PIPE3__SHIFT 0xc
+-#define DMIF_P_VMID__P_VMID_PIPE4__SHIFT 0x10
+-#define DMIF_P_VMID__P_VMID_PIPE5__SHIFT 0x14
+-#define DMIF_P_VMID__P_VMID_PIPE6__SHIFT 0x18
+-#define DMIF_P_VMID__P_VMID_PIPE7__SHIFT 0x1c
+-#define DMIF_P_VMID__P_VMID_PIPE0_MASK 0x0000000FL
+-#define DMIF_P_VMID__P_VMID_PIPE1_MASK 0x000000F0L
+-#define DMIF_P_VMID__P_VMID_PIPE2_MASK 0x00000F00L
+-#define DMIF_P_VMID__P_VMID_PIPE3_MASK 0x0000F000L
+-#define DMIF_P_VMID__P_VMID_PIPE4_MASK 0x000F0000L
+-#define DMIF_P_VMID__P_VMID_PIPE5_MASK 0x00F00000L
+-#define DMIF_P_VMID__P_VMID_PIPE6_MASK 0x0F000000L
+-#define DMIF_P_VMID__P_VMID_PIPE7_MASK 0xF0000000L
+-//DMIF_ADDR_CALC
+-#define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE__SHIFT 0x3
+-#define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE__SHIFT 0x1c
+-#define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
+-#define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE_MASK 0x30000000L
+-//DMIF_STATUS2
+-#define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS__SHIFT 0x0
+-#define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS__SHIFT 0x1
+-#define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS__SHIFT 0x2
+-#define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS__SHIFT 0x3
+-#define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS__SHIFT 0x4
+-#define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS__SHIFT 0x5
+-#define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS__SHIFT 0x8
+-#define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS__SHIFT 0x9
+-#define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS_MASK 0x00000001L
+-#define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS_MASK 0x00000002L
+-#define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS_MASK 0x00000004L
+-#define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS_MASK 0x00000008L
+-#define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS_MASK 0x00000010L
+-#define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS_MASK 0x00000020L
+-#define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS_MASK 0x00000100L
+-#define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS_MASK 0x00000200L
+-//PIPE0_MAX_REQUESTS
+-#define PIPE0_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
+-#define PIPE0_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003FFL
+-//PIPE1_MAX_REQUESTS
+-#define PIPE1_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
+-#define PIPE1_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003FFL
+-//PIPE2_MAX_REQUESTS
+-#define PIPE2_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
+-#define PIPE2_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003FFL
+-//PIPE3_MAX_REQUESTS
+-#define PIPE3_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
+-#define PIPE3_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003FFL
+-//PIPE4_MAX_REQUESTS
+-#define PIPE4_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
+-#define PIPE4_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003FFL
+-//PIPE5_MAX_REQUESTS
+-#define PIPE5_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
+-#define PIPE5_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003FFL
+-//LOW_POWER_TILING_CONTROL
+-#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE__SHIFT 0x0
+-#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE__SHIFT 0x3
+-#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES__SHIFT 0x5
+-#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS__SHIFT 0x8
+-#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE__SHIFT 0xb
+-#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE__SHIFT 0xc
+-#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN__SHIFT 0x10
+-#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE_MASK 0x00000001L
+-#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE_MASK 0x00000018L
+-#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES_MASK 0x000000E0L
+-#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS_MASK 0x00000700L
+-#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE_MASK 0x00000800L
+-#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE_MASK 0x00007000L
+-#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN_MASK 0x0FFF0000L
+-//MCIF_CONTROL
+-#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x1e
+-#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x1f
+-#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x40000000L
+-#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x80000000L
+-//MCIF_WRITE_COMBINE_CONTROL
+-#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT 0x0
+-#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK 0x000003FFL
+-//MCIF_PHASE0_OUTSTANDING_COUNTER
+-#define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER__SHIFT 0x0
+-#define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL
+-//CC_DC_PIPE_DIS
+-#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT 0x1
+-#define CC_DC_PIPE_DIS__DC_UNDERLAY_PIPE_DIS__SHIFT 0x10
+-#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK 0x0000007EL
+-#define CC_DC_PIPE_DIS__DC_UNDERLAY_PIPE_DIS_MASK 0x003F0000L
+-//SMU_WM_CONTROL
+-#define SMU_WM_CONTROL__DMIF_WM_CHG_SEL__SHIFT 0x0
+-#define SMU_WM_CONTROL__DMIF_WM_CHG_REQ__SHIFT 0x2
+-#define SMU_WM_CONTROL__DMIF_WM_CHG_ACK_INT_DIS__SHIFT 0x10
+-#define SMU_WM_CONTROL__DMIF_WM_CHG_ACK_INT_STATUS__SHIFT 0x11
+-#define SMU_WM_CONTROL__MCIF_WB_WM_CHG_SEL__SHIFT 0x14
+-#define SMU_WM_CONTROL__MCIF_WB_WM_CHG_REQ__SHIFT 0x16
+-#define SMU_WM_CONTROL__MCIF_WB_WM_CHG_ACK_INT_DIS__SHIFT 0x18
+-#define SMU_WM_CONTROL__MCIF_WB_WM_CHG_ACK_INT_STATUS__SHIFT 0x19
+-#define SMU_WM_CONTROL__DMIF_WM_CHG_SEL_MASK 0x00000003L
+-#define SMU_WM_CONTROL__DMIF_WM_CHG_REQ_MASK 0x00000004L
+-#define SMU_WM_CONTROL__DMIF_WM_CHG_ACK_INT_DIS_MASK 0x00010000L
+-#define SMU_WM_CONTROL__DMIF_WM_CHG_ACK_INT_STATUS_MASK 0x00020000L
+-#define SMU_WM_CONTROL__MCIF_WB_WM_CHG_SEL_MASK 0x00300000L
+-#define SMU_WM_CONTROL__MCIF_WB_WM_CHG_REQ_MASK 0x00400000L
+-#define SMU_WM_CONTROL__MCIF_WB_WM_CHG_ACK_INT_DIS_MASK 0x01000000L
+-#define SMU_WM_CONTROL__MCIF_WB_WM_CHG_ACK_INT_STATUS_MASK 0x02000000L
+-//RBBMIF_TIMEOUT
+-#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT 0x0
+-#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD__SHIFT 0x14
+-#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK 0x000FFFFFL
+-#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD_MASK 0xFFF00000L
+-//RBBMIF_STATUS
+-#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT 0x0
+-#define RBBMIF_STATUS__RBBMIF_TIMEOUT_OP__SHIFT 0x1c
+-#define RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT 0x1d
+-#define RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT 0x1e
+-#define RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT 0x1f
+-#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK 0x0000FFFFL
+-#define RBBMIF_STATUS__RBBMIF_TIMEOUT_OP_MASK 0x10000000L
+-#define RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK 0x20000000L
+-#define RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK_MASK 0x40000000L
+-#define RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK_MASK 0x80000000L
+-//RBBMIF_TIMEOUT_DIS
+-#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT 0x0
+-#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT 0x1
+-#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT 0x2
+-#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT 0x3
+-#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS__SHIFT 0x4
+-#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS__SHIFT 0x5
+-#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS__SHIFT 0x6
+-#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS__SHIFT 0x7
+-#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS__SHIFT 0x8
+-#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS__SHIFT 0x9
+-#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS__SHIFT 0xa
+-#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS__SHIFT 0xb
+-#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS__SHIFT 0xc
+-#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS__SHIFT 0xd
+-#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS__SHIFT 0xe
+-#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS__SHIFT 0xf
+-#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK 0x00000001L
+-#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK 0x00000002L
+-#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK 0x00000004L
+-#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK 0x00000008L
+-#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS_MASK 0x00000010L
+-#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS_MASK 0x00000020L
+-#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS_MASK 0x00000040L
+-#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS_MASK 0x00000080L
+-#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS_MASK 0x00000100L
+-#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS_MASK 0x00000200L
+-#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS_MASK 0x00000400L
+-#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK 0x00000800L
+-#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS_MASK 0x00001000L
+-#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS_MASK 0x00002000L
+-#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS_MASK 0x00004000L
+-#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS_MASK 0x00008000L
+-//DCI_MEM_PWR_STATUS
+-#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM1_PWR_STATE__SHIFT 0x0
+-#define DCI_MEM_PWR_STATUS__VGA_MEM_PWR_STATE__SHIFT 0x8
+-#define DCI_MEM_PWR_STATUS__DMCU_ERAM_MEM_PWR_STATE__SHIFT 0x9
+-#define DCI_MEM_PWR_STATUS__DMCU_IRAM_MEM_PWR_STATE__SHIFT 0xb
+-#define DCI_MEM_PWR_STATUS__FBC_MEM_PWR_STATE__SHIFT 0xc
+-#define DCI_MEM_PWR_STATUS__DMIF_CURSOR_MEM_PWR_STATE__SHIFT 0x10
+-#define DCI_MEM_PWR_STATUS__DMIF_CURSOR_RD_REQ_MEM_PWR_STATE__SHIFT 0x12
+-#define DCI_MEM_PWR_STATUS__VIP_MEM_PWR_STATE__SHIFT 0x16
+-#define DCI_MEM_PWR_STATUS__DMIF0_ASYNC_MEM_PWR_STATE__SHIFT 0x18
+-#define DCI_MEM_PWR_STATUS__DMIF0_DATA_MEM_PWR_STATE__SHIFT 0x1a
+-#define DCI_MEM_PWR_STATUS__DMIF0_CHUNK_MEM_PWR_STATE__SHIFT 0x1c
+-#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM1_PWR_STATE_MASK 0x00000003L
+-#define DCI_MEM_PWR_STATUS__VGA_MEM_PWR_STATE_MASK 0x00000100L
+-#define DCI_MEM_PWR_STATUS__DMCU_ERAM_MEM_PWR_STATE_MASK 0x00000600L
+-#define DCI_MEM_PWR_STATUS__DMCU_IRAM_MEM_PWR_STATE_MASK 0x00000800L
+-#define DCI_MEM_PWR_STATUS__FBC_MEM_PWR_STATE_MASK 0x00003000L
+-#define DCI_MEM_PWR_STATUS__DMIF_CURSOR_MEM_PWR_STATE_MASK 0x00030000L
+-#define DCI_MEM_PWR_STATUS__DMIF_CURSOR_RD_REQ_MEM_PWR_STATE_MASK 0x000C0000L
+-#define DCI_MEM_PWR_STATUS__VIP_MEM_PWR_STATE_MASK 0x00400000L
+-#define DCI_MEM_PWR_STATUS__DMIF0_ASYNC_MEM_PWR_STATE_MASK 0x03000000L
+-#define DCI_MEM_PWR_STATUS__DMIF0_DATA_MEM_PWR_STATE_MASK 0x0C000000L
+-#define DCI_MEM_PWR_STATUS__DMIF0_CHUNK_MEM_PWR_STATE_MASK 0x10000000L
+-//DCI_MEM_PWR_STATUS2
+-#define DCI_MEM_PWR_STATUS2__DMIF1_ASYNC_MEM_PWR_STATE__SHIFT 0x0
+-#define DCI_MEM_PWR_STATUS2__DMIF1_DATA_MEM_PWR_STATE__SHIFT 0x2
+-#define DCI_MEM_PWR_STATUS2__DMIF1_CHUNK_MEM_PWR_STATE__SHIFT 0x4
+-#define DCI_MEM_PWR_STATUS2__DMIF2_ASYNC_MEM_PWR_STATE__SHIFT 0x5
+-#define DCI_MEM_PWR_STATUS2__DMIF2_DATA_MEM_PWR_STATE__SHIFT 0x7
+-#define DCI_MEM_PWR_STATUS2__DMIF2_CHUNK_MEM_PWR_STATE__SHIFT 0x9
+-#define DCI_MEM_PWR_STATUS2__DMIF3_ASYNC_MEM_PWR_STATE__SHIFT 0xa
+-#define DCI_MEM_PWR_STATUS2__DMIF3_DATA_MEM_PWR_STATE__SHIFT 0xc
+-#define DCI_MEM_PWR_STATUS2__DMIF3_CHUNK_MEM_PWR_STATE__SHIFT 0xe
+-#define DCI_MEM_PWR_STATUS2__DMIF4_ASYNC_MEM_PWR_STATE__SHIFT 0xf
+-#define DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE__SHIFT 0x11
+-#define DCI_MEM_PWR_STATUS2__DMIF4_CHUNK_MEM_PWR_STATE__SHIFT 0x13
+-#define DCI_MEM_PWR_STATUS2__DMIF5_ASYNC_MEM_PWR_STATE__SHIFT 0x14
+-#define DCI_MEM_PWR_STATUS2__DMIF5_DATA_MEM_PWR_STATE__SHIFT 0x16
+-#define DCI_MEM_PWR_STATUS2__DMIF5_CHUNK_MEM_PWR_STATE__SHIFT 0x18
+-#define DCI_MEM_PWR_STATUS2__DMIF1_ASYNC_MEM_PWR_STATE_MASK 0x00000003L
+-#define DCI_MEM_PWR_STATUS2__DMIF1_DATA_MEM_PWR_STATE_MASK 0x0000000CL
+-#define DCI_MEM_PWR_STATUS2__DMIF1_CHUNK_MEM_PWR_STATE_MASK 0x00000010L
+-#define DCI_MEM_PWR_STATUS2__DMIF2_ASYNC_MEM_PWR_STATE_MASK 0x00000060L
+-#define DCI_MEM_PWR_STATUS2__DMIF2_DATA_MEM_PWR_STATE_MASK 0x00000180L
+-#define DCI_MEM_PWR_STATUS2__DMIF2_CHUNK_MEM_PWR_STATE_MASK 0x00000200L
+-#define DCI_MEM_PWR_STATUS2__DMIF3_ASYNC_MEM_PWR_STATE_MASK 0x00000C00L
+-#define DCI_MEM_PWR_STATUS2__DMIF3_DATA_MEM_PWR_STATE_MASK 0x00003000L
+-#define DCI_MEM_PWR_STATUS2__DMIF3_CHUNK_MEM_PWR_STATE_MASK 0x00004000L
+-#define DCI_MEM_PWR_STATUS2__DMIF4_ASYNC_MEM_PWR_STATE_MASK 0x00018000L
+-#define DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE_MASK 0x00060000L
+-#define DCI_MEM_PWR_STATUS2__DMIF4_CHUNK_MEM_PWR_STATE_MASK 0x00080000L
+-#define DCI_MEM_PWR_STATUS2__DMIF5_ASYNC_MEM_PWR_STATE_MASK 0x00300000L
+-#define DCI_MEM_PWR_STATUS2__DMIF5_DATA_MEM_PWR_STATE_MASK 0x00C00000L
+-#define DCI_MEM_PWR_STATUS2__DMIF5_CHUNK_MEM_PWR_STATE_MASK 0x01000000L
+-//DCI_CLK_CNTL
+-#define DCI_CLK_CNTL__DCI_TEST_CLK_SEL__SHIFT 0x0
+-#define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS__SHIFT 0x5
+-#define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS__SHIFT 0x6
+-#define DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT 0x7
+-#define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT 0x8
+-#define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS__SHIFT 0x9
+-#define DCI_CLK_CNTL__DISPCLK_G_DMIFV1_L_GATE_DIS__SHIFT 0xa
+-#define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT 0xb
+-#define DCI_CLK_CNTL__DISPCLK_G_DMIFV1_C_GATE_DIS__SHIFT 0xc
+-#define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS__SHIFT 0xd
+-#define DCI_CLK_CNTL__VPCLK_POL__SHIFT 0xe
+-#define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT 0xf
+-#define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS__SHIFT 0x10
+-#define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS__SHIFT 0x11
+-#define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS__SHIFT 0x12
+-#define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS__SHIFT 0x13
+-#define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS__SHIFT 0x14
+-#define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS__SHIFT 0x15
+-#define DCI_CLK_CNTL__DCEFCLK_G_DMIF_FBCTRK_GATE_DIS__SHIFT 0x16
+-#define DCI_CLK_CNTL__DCEFCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x17
+-#define DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT 0x18
+-#define DCI_CLK_CNTL__DISPCLK_G_DMIFV0_L_GATE_DIS__SHIFT 0x19
+-#define DCI_CLK_CNTL__DISPCLK_G_DMIFV0_C_GATE_DIS__SHIFT 0x1a
+-#define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL__SHIFT 0x1b
+-#define DCI_CLK_CNTL__DCI_TEST_CLK_SEL_MASK 0x0000001FL
+-#define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS_MASK 0x00000020L
+-#define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS_MASK 0x00000040L
+-#define DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK 0x00000080L
+-#define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS_MASK 0x00000100L
+-#define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS_MASK 0x00000200L
+-#define DCI_CLK_CNTL__DISPCLK_G_DMIFV1_L_GATE_DIS_MASK 0x00000400L
+-#define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x00000800L
+-#define DCI_CLK_CNTL__DISPCLK_G_DMIFV1_C_GATE_DIS_MASK 0x00001000L
+-#define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS_MASK 0x00002000L
+-#define DCI_CLK_CNTL__VPCLK_POL_MASK 0x00004000L
+-#define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK 0x00008000L
+-#define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS_MASK 0x00010000L
+-#define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS_MASK 0x00020000L
+-#define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS_MASK 0x00040000L
+-#define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS_MASK 0x00080000L
+-#define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS_MASK 0x00100000L
+-#define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS_MASK 0x00200000L
+-#define DCI_CLK_CNTL__DCEFCLK_G_DMIF_FBCTRK_GATE_DIS_MASK 0x00400000L
+-#define DCI_CLK_CNTL__DCEFCLK_G_DMIFTRK_GATE_DIS_MASK 0x00800000L
+-#define DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK 0x01000000L
+-#define DCI_CLK_CNTL__DISPCLK_G_DMIFV0_L_GATE_DIS_MASK 0x02000000L
+-#define DCI_CLK_CNTL__DISPCLK_G_DMIFV0_C_GATE_DIS_MASK 0x04000000L
+-#define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL_MASK 0xF8000000L
+-//DCI_CLK_CNTL2
+-#define DCI_CLK_CNTL2__DISPCLK_G_MCIF_DWB_GATE_DIS__SHIFT 0x0
+-#define DCI_CLK_CNTL2__SCLK_G_MCIF_DWB_GATE_DIS__SHIFT 0x1
+-#define DCI_CLK_CNTL2__DISPCLK_G_MCIF_CWB0_GATE_DIS__SHIFT 0x2
+-#define DCI_CLK_CNTL2__SCLK_G_MCIF_CWB0_GATE_DIS__SHIFT 0x3
+-#define DCI_CLK_CNTL2__DISPCLK_G_MCIF_CWB1_GATE_DIS__SHIFT 0x4
+-#define DCI_CLK_CNTL2__DCEFCLK_GATE_DIS__SHIFT 0x5
+-#define DCI_CLK_CNTL2__DCEFCLK_TURN_ON_DELAY__SHIFT 0x8
+-#define DCI_CLK_CNTL2__DCEFCLK_TURN_OFF_DELAY__SHIFT 0xc
+-#define DCI_CLK_CNTL2__CGTT_DCEFCLK_OVERRIDE__SHIFT 0x14
+-#define DCI_CLK_CNTL2__SCLK_G_MCIF_CWB1_GATE_DIS__SHIFT 0x1f
+-#define DCI_CLK_CNTL2__DISPCLK_G_MCIF_DWB_GATE_DIS_MASK 0x00000001L
+-#define DCI_CLK_CNTL2__SCLK_G_MCIF_DWB_GATE_DIS_MASK 0x00000002L
+-#define DCI_CLK_CNTL2__DISPCLK_G_MCIF_CWB0_GATE_DIS_MASK 0x00000004L
+-#define DCI_CLK_CNTL2__SCLK_G_MCIF_CWB0_GATE_DIS_MASK 0x00000008L
+-#define DCI_CLK_CNTL2__DISPCLK_G_MCIF_CWB1_GATE_DIS_MASK 0x00000010L
+-#define DCI_CLK_CNTL2__DCEFCLK_GATE_DIS_MASK 0x00000020L
+-#define DCI_CLK_CNTL2__DCEFCLK_TURN_ON_DELAY_MASK 0x00000F00L
+-#define DCI_CLK_CNTL2__DCEFCLK_TURN_OFF_DELAY_MASK 0x000FF000L
+-#define DCI_CLK_CNTL2__CGTT_DCEFCLK_OVERRIDE_MASK 0x00100000L
+-#define DCI_CLK_CNTL2__SCLK_G_MCIF_CWB1_GATE_DIS_MASK 0x80000000L
+-//DCI_MEM_PWR_CNTL
+-#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_FORCE__SHIFT 0x0
+-#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_DIS__SHIFT 0x2
+-#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE__SHIFT 0x7
+-#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_DIS__SHIFT 0x8
+-#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE__SHIFT 0x9
+-#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS__SHIFT 0xb
+-#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE__SHIFT 0xc
+-#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS__SHIFT 0xd
+-#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_FORCE__SHIFT 0xe
+-#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_DIS__SHIFT 0x10
+-#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_FORCE__SHIFT 0x14
+-#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_DIS__SHIFT 0x16
+-#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_FORCE__SHIFT 0x17
+-#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_DIS__SHIFT 0x19
+-#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_FORCE__SHIFT 0x1a
+-#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_DIS__SHIFT 0x1c
+-#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_FORCE__SHIFT 0x1d
+-#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_DIS__SHIFT 0x1e
+-#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_FORCE_MASK 0x00000003L
+-#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_DIS_MASK 0x00000004L
+-#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE_MASK 0x00000080L
+-#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_DIS_MASK 0x00000100L
+-#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE_MASK 0x00000600L
+-#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS_MASK 0x00000800L
+-#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE_MASK 0x00001000L
+-#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS_MASK 0x00002000L
+-#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_FORCE_MASK 0x0000C000L
+-#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_DIS_MASK 0x00010000L
+-#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_FORCE_MASK 0x00300000L
+-#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_DIS_MASK 0x00400000L
+-#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_FORCE_MASK 0x01800000L
+-#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_DIS_MASK 0x02000000L
+-#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_FORCE_MASK 0x0C000000L
+-#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_DIS_MASK 0x10000000L
+-#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_FORCE_MASK 0x20000000L
+-#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_DIS_MASK 0x40000000L
+-//DCI_MEM_PWR_CNTL2
+-#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_FORCE__SHIFT 0x0
+-#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_DIS__SHIFT 0x2
+-#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_FORCE__SHIFT 0x3
+-#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_DIS__SHIFT 0x5
+-#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_FORCE__SHIFT 0x6
+-#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_DIS__SHIFT 0x7
+-#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_FORCE__SHIFT 0x8
+-#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_DIS__SHIFT 0xa
+-#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_FORCE__SHIFT 0xb
+-#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_DIS__SHIFT 0xd
+-#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_FORCE__SHIFT 0xe
+-#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_DIS__SHIFT 0xf
+-#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_FORCE__SHIFT 0x10
+-#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_DIS__SHIFT 0x12
+-#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_FORCE__SHIFT 0x13
+-#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_DIS__SHIFT 0x15
+-#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_FORCE__SHIFT 0x16
+-#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_DIS__SHIFT 0x17
+-#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_FORCE__SHIFT 0x18
+-#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_DIS__SHIFT 0x1a
+-#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_FORCE__SHIFT 0x1b
+-#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_DIS__SHIFT 0x1d
+-#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_FORCE__SHIFT 0x1e
+-#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_DIS__SHIFT 0x1f
+-#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_FORCE_MASK 0x00000003L
+-#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_DIS_MASK 0x00000004L
+-#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_FORCE_MASK 0x00000018L
+-#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_DIS_MASK 0x00000020L
+-#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_FORCE_MASK 0x00000040L
+-#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_DIS_MASK 0x00000080L
+-#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_FORCE_MASK 0x00000300L
+-#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_DIS_MASK 0x00000400L
+-#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_FORCE_MASK 0x00001800L
+-#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_DIS_MASK 0x00002000L
+-#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_FORCE_MASK 0x00004000L
+-#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_DIS_MASK 0x00008000L
+-#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_FORCE_MASK 0x00030000L
+-#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_DIS_MASK 0x00040000L
+-#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_FORCE_MASK 0x00180000L
+-#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_DIS_MASK 0x00200000L
+-#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_FORCE_MASK 0x00400000L
+-#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_DIS_MASK 0x00800000L
+-#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_FORCE_MASK 0x03000000L
+-#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_DIS_MASK 0x04000000L
+-#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_FORCE_MASK 0x18000000L
+-#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_DIS_MASK 0x20000000L
+-#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_FORCE_MASK 0x40000000L
+-#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_DIS_MASK 0x80000000L
+-//DCI_MEM_PWR_CNTL3
+-#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_FORCE__SHIFT 0x0
+-#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_DIS__SHIFT 0x2
+-#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_FORCE__SHIFT 0x3
+-#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_DIS__SHIFT 0x5
+-#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_FORCE__SHIFT 0x6
+-#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_DIS__SHIFT 0x7
+-#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_FORCE__SHIFT 0x8
+-#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_DIS__SHIFT 0xa
+-#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_FORCE__SHIFT 0xb
+-#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_DIS__SHIFT 0xd
+-#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_FORCE__SHIFT 0xe
+-#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_DIS__SHIFT 0xf
+-#define DCI_MEM_PWR_CNTL3__DMIF_RDREQ_MEM_PWR_MODE_SEL__SHIFT 0x10
+-#define DCI_MEM_PWR_CNTL3__DMIF_ASYNC_MEM_PWR_MODE_SEL__SHIFT 0x12
+-#define DCI_MEM_PWR_CNTL3__DMIF_DATA_MEM_PWR_MODE_SEL__SHIFT 0x14
+-#define DCI_MEM_PWR_CNTL3__DMCU_ERAM_MEM_PWR_MODE_SEL__SHIFT 0x16
+-#define DCI_MEM_PWR_CNTL3__FBC_MEM_PWR_MODE_SEL__SHIFT 0x17
+-#define DCI_MEM_PWR_CNTL3__MCIF_CWB0_MEM_PWR_MODE_SEL__SHIFT 0x19
+-#define DCI_MEM_PWR_CNTL3__MCIF_CWB1_MEM_PWR_MODE_SEL__SHIFT 0x1b
+-#define DCI_MEM_PWR_CNTL3__MCIF_DWB_MEM_PWR_MODE_SEL__SHIFT 0x1d
+-#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_FORCE_MASK 0x00000003L
+-#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_DIS_MASK 0x00000004L
+-#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_FORCE_MASK 0x00000018L
+-#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_DIS_MASK 0x00000020L
+-#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_FORCE_MASK 0x00000040L
+-#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_DIS_MASK 0x00000080L
+-#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_FORCE_MASK 0x00000300L
+-#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_DIS_MASK 0x00000400L
+-#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_FORCE_MASK 0x00001800L
+-#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_DIS_MASK 0x00002000L
+-#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_FORCE_MASK 0x00004000L
+-#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_DIS_MASK 0x00008000L
+-#define DCI_MEM_PWR_CNTL3__DMIF_RDREQ_MEM_PWR_MODE_SEL_MASK 0x00030000L
+-#define DCI_MEM_PWR_CNTL3__DMIF_ASYNC_MEM_PWR_MODE_SEL_MASK 0x000C0000L
+-#define DCI_MEM_PWR_CNTL3__DMIF_DATA_MEM_PWR_MODE_SEL_MASK 0x00300000L
+-#define DCI_MEM_PWR_CNTL3__DMCU_ERAM_MEM_PWR_MODE_SEL_MASK 0x00400000L
+-#define DCI_MEM_PWR_CNTL3__FBC_MEM_PWR_MODE_SEL_MASK 0x01800000L
+-#define DCI_MEM_PWR_CNTL3__MCIF_CWB0_MEM_PWR_MODE_SEL_MASK 0x06000000L
+-#define DCI_MEM_PWR_CNTL3__MCIF_CWB1_MEM_PWR_MODE_SEL_MASK 0x18000000L
+-#define DCI_MEM_PWR_CNTL3__MCIF_DWB_MEM_PWR_MODE_SEL_MASK 0x60000000L
+-//PIPE0_DMIF_BUFFER_CONTROL
+-#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
+-#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
+-#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L
+-#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L
+-//PIPE1_DMIF_BUFFER_CONTROL
+-#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
+-#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
+-#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L
+-#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L
+-//PIPE2_DMIF_BUFFER_CONTROL
+-#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
+-#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
+-#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L
+-#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L
+-//PIPE3_DMIF_BUFFER_CONTROL
+-#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
+-#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
+-#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L
+-#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L
+-//PIPE4_DMIF_BUFFER_CONTROL
+-#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
+-#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
+-#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L
+-#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L
+-//PIPE5_DMIF_BUFFER_CONTROL
+-#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
+-#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
+-#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L
+-#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L
+-//RBBMIF_STATUS_FLAG
+-#define RBBMIF_STATUS_FLAG__RBBMIF_STATE__SHIFT 0x0
+-#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT__SHIFT 0x4
+-#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY__SHIFT 0x5
+-#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL__SHIFT 0x6
+-#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG__SHIFT 0x8
+-#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE__SHIFT 0x9
+-#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR__SHIFT 0x10
+-#define RBBMIF_STATUS_FLAG__RBBMIF_STATE_MASK 0x00000003L
+-#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT_MASK 0x00000010L
+-#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY_MASK 0x00000020L
+-#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL_MASK 0x00000040L
+-#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG_MASK 0x00000100L
+-#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE_MASK 0x00000E00L
+-#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR_MASK 0xFFFF0000L
+-//DCI_SOFT_RESET
+-#define DCI_SOFT_RESET__VGA_SOFT_RESET__SHIFT 0x0
+-#define DCI_SOFT_RESET__VIP_SOFT_RESET__SHIFT 0x1
+-#define DCI_SOFT_RESET__MCIF_SOFT_RESET__SHIFT 0x2
+-#define DCI_SOFT_RESET__FBC_SOFT_RESET__SHIFT 0x3
+-#define DCI_SOFT_RESET__DMIF0_SOFT_RESET__SHIFT 0x4
+-#define DCI_SOFT_RESET__DMIF1_SOFT_RESET__SHIFT 0x5
+-#define DCI_SOFT_RESET__DMIF2_SOFT_RESET__SHIFT 0x6
+-#define DCI_SOFT_RESET__DMIF3_SOFT_RESET__SHIFT 0x7
+-#define DCI_SOFT_RESET__DMIF4_SOFT_RESET__SHIFT 0x8
+-#define DCI_SOFT_RESET__DMIF5_SOFT_RESET__SHIFT 0x9
+-#define DCI_SOFT_RESET__DCFEV0_L_SOFT_RESET__SHIFT 0xa
+-#define DCI_SOFT_RESET__DCFEV0_C_SOFT_RESET__SHIFT 0xb
+-#define DCI_SOFT_RESET__DCFEV1_L_SOFT_RESET__SHIFT 0xc
+-#define DCI_SOFT_RESET__DCFEV1_C_SOFT_RESET__SHIFT 0xd
+-#define DCI_SOFT_RESET__DMIFARB_SOFT_RESET__SHIFT 0xe
+-#define DCI_SOFT_RESET__DCHUB_SOFT_RESET__SHIFT 0xf
+-#define DCI_SOFT_RESET__MCIF_DWB_SOFT_RESET__SHIFT 0x10
+-#define DCI_SOFT_RESET__MCIF_CWB0_SOFT_RESET__SHIFT 0x11
+-#define DCI_SOFT_RESET__MCIF_CWB1_SOFT_RESET__SHIFT 0x12
+-#define DCI_SOFT_RESET__MCIF_WB_SOFT_RESET__SHIFT 0x13
+-#define DCI_SOFT_RESET__VGA_SOFT_RESET_MASK 0x00000001L
+-#define DCI_SOFT_RESET__VIP_SOFT_RESET_MASK 0x00000002L
+-#define DCI_SOFT_RESET__MCIF_SOFT_RESET_MASK 0x00000004L
+-#define DCI_SOFT_RESET__FBC_SOFT_RESET_MASK 0x00000008L
+-#define DCI_SOFT_RESET__DMIF0_SOFT_RESET_MASK 0x00000010L
+-#define DCI_SOFT_RESET__DMIF1_SOFT_RESET_MASK 0x00000020L
+-#define DCI_SOFT_RESET__DMIF2_SOFT_RESET_MASK 0x00000040L
+-#define DCI_SOFT_RESET__DMIF3_SOFT_RESET_MASK 0x00000080L
+-#define DCI_SOFT_RESET__DMIF4_SOFT_RESET_MASK 0x00000100L
+-#define DCI_SOFT_RESET__DMIF5_SOFT_RESET_MASK 0x00000200L
+-#define DCI_SOFT_RESET__DCFEV0_L_SOFT_RESET_MASK 0x00000400L
+-#define DCI_SOFT_RESET__DCFEV0_C_SOFT_RESET_MASK 0x00000800L
+-#define DCI_SOFT_RESET__DCFEV1_L_SOFT_RESET_MASK 0x00001000L
+-#define DCI_SOFT_RESET__DCFEV1_C_SOFT_RESET_MASK 0x00002000L
+-#define DCI_SOFT_RESET__DMIFARB_SOFT_RESET_MASK 0x00004000L
+-#define DCI_SOFT_RESET__DCHUB_SOFT_RESET_MASK 0x00008000L
+-#define DCI_SOFT_RESET__MCIF_DWB_SOFT_RESET_MASK 0x00010000L
+-#define DCI_SOFT_RESET__MCIF_CWB0_SOFT_RESET_MASK 0x00020000L
+-#define DCI_SOFT_RESET__MCIF_CWB1_SOFT_RESET_MASK 0x00040000L
+-#define DCI_SOFT_RESET__MCIF_WB_SOFT_RESET_MASK 0x00080000L
+-//DMIF_URG_OVERRIDE
+-#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_EN__SHIFT 0x0
+-#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_LEVEL__SHIFT 0x4
+-#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_EN_MASK 0x00000001L
+-#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_LEVEL_MASK 0x000000F0L
+-//PIPE6_ARBITRATION_CONTROL3
+-#define PIPE6_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
+-#define PIPE6_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000FFFFL
+-//PIPE7_ARBITRATION_CONTROL3
+-#define PIPE7_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
+-#define PIPE7_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000FFFFL
+-//PIPE6_MAX_REQUESTS
+-#define PIPE6_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
+-#define PIPE6_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003FFL
+-//PIPE7_MAX_REQUESTS
+-#define PIPE7_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
+-#define PIPE7_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003FFL
+-//DVMM_REG_RD_STATUS
+-#define DVMM_REG_RD_STATUS__DVMM_REG_RD_STATUS__SHIFT 0x0
+-#define DVMM_REG_RD_STATUS__DVMM_REG_RD_STATUS_MASK 0x00000001L
+-//DVMM_REG_RD_DATA
+-#define DVMM_REG_RD_DATA__DVMM_REG_RD_DATA__SHIFT 0x0
+-#define DVMM_REG_RD_DATA__DVMM_REG_RD_DATA_MASK 0xFFFFFFFFL
+-//DVMM_PTE_REQ
+-#define DVMM_PTE_REQ__MAX_PTEREQ_TO_ISSUE__SHIFT 0x0
+-#define DVMM_PTE_REQ__HFLIP_PTEREQ_PER_CHUNK_INT__SHIFT 0x8
+-#define DVMM_PTE_REQ__HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER__SHIFT 0x10
+-#define DVMM_PTE_REQ__MAX_PTEREQ_TO_ISSUE_MASK 0x000000FFL
+-#define DVMM_PTE_REQ__HFLIP_PTEREQ_PER_CHUNK_INT_MASK 0x0000FF00L
+-#define DVMM_PTE_REQ__HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER_MASK 0x003F0000L
+-//DVMM_CNTL
+-#define DVMM_CNTL__PDE_CACHE_INVALIDATE_CNTL__SHIFT 0x0
+-#define DVMM_CNTL__FORCE_SYSTEM_ACCESS_MODE__SHIFT 0x7
+-#define DVMM_CNTL__OVERRIDE_SNOOP__SHIFT 0x11
+-#define DVMM_CNTL__ENABLE_PDE_INVALIDATE__SHIFT 0x12
+-#define DVMM_CNTL__PDE_CACHE_INVALIDATE_CNTL_MASK 0x00000003L
+-#define DVMM_CNTL__FORCE_SYSTEM_ACCESS_MODE_MASK 0x00000080L
+-#define DVMM_CNTL__OVERRIDE_SNOOP_MASK 0x00020000L
+-#define DVMM_CNTL__ENABLE_PDE_INVALIDATE_MASK 0x00040000L
+-//DVMM_FAULT_STATUS
+-#define DVMM_FAULT_STATUS__DVMM_FAULT_STATUS__SHIFT 0x0
+-#define DVMM_FAULT_STATUS__DVMM_FAULT_STATUS_MASK 0xFFFFFFFFL
+-//DVMM_FAULT_ADDR
+-#define DVMM_FAULT_ADDR__DVMM_FAULT_ADDR__SHIFT 0x0
+-#define DVMM_FAULT_ADDR__DVMM_FAULT_ADDR_MASK 0xFFFFFFFFL
+-//FMON_CTRL
+-#define FMON_CTRL__FMON_START__SHIFT 0x0
+-#define FMON_CTRL__FMON_MODE__SHIFT 0x1
+-#define FMON_CTRL__FMON_PSTATE_IGNORE__SHIFT 0x4
+-#define FMON_CTRL__FMON_STATUS_IGNORE__SHIFT 0x5
+-#define FMON_CTRL__FMON_URG_MODE_GREATER__SHIFT 0x6
+-#define FMON_CTRL__FMON_FILTER_UID_EN__SHIFT 0x7
+-#define FMON_CTRL__FMON_STATE__SHIFT 0x8
+-#define FMON_CTRL__FMON_URG_THRESHOLD__SHIFT 0xc
+-#define FMON_CTRL__FMON_FILTER_UID__SHIFT 0x10
+-#define FMON_CTRL__FMON_SOF_SEL__SHIFT 0x18
+-#define FMON_CTRL__FMON_START_MASK 0x00000001L
+-#define FMON_CTRL__FMON_MODE_MASK 0x00000006L
+-#define FMON_CTRL__FMON_PSTATE_IGNORE_MASK 0x00000010L
+-#define FMON_CTRL__FMON_STATUS_IGNORE_MASK 0x00000020L
+-#define FMON_CTRL__FMON_URG_MODE_GREATER_MASK 0x00000040L
+-#define FMON_CTRL__FMON_FILTER_UID_EN_MASK 0x00000080L
+-#define FMON_CTRL__FMON_STATE_MASK 0x00000300L
+-#define FMON_CTRL__FMON_URG_THRESHOLD_MASK 0x0000F000L
+-#define FMON_CTRL__FMON_FILTER_UID_MASK 0x001F0000L
+-#define FMON_CTRL__FMON_SOF_SEL_MASK 0x07000000L
+-//DVMM_PTE_PGMEM_CONTROL
+-#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE0_MEM_PWR_FORCE__SHIFT 0x0
+-#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE0_MEM_PWR_DIS__SHIFT 0x2
+-#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE1_MEM_PWR_FORCE__SHIFT 0x3
+-#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE1_MEM_PWR_DIS__SHIFT 0x5
+-#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE2_MEM_PWR_FORCE__SHIFT 0x6
+-#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE2_MEM_PWR_DIS__SHIFT 0x8
+-#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE3_MEM_PWR_FORCE__SHIFT 0x9
+-#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE3_MEM_PWR_DIS__SHIFT 0xb
+-#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE4_MEM_PWR_FORCE__SHIFT 0xc
+-#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE4_MEM_PWR_DIS__SHIFT 0xe
+-#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE5_MEM_PWR_FORCE__SHIFT 0xf
+-#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE5_MEM_PWR_DIS__SHIFT 0x11
+-#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE6_MEM_PWR_FORCE__SHIFT 0x12
+-#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE6_MEM_PWR_DIS__SHIFT 0x14
+-#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE7_MEM_PWR_FORCE__SHIFT 0x15
+-#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE7_MEM_PWR_DIS__SHIFT 0x17
+-#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE_MEM_PWR_MODE_SEL__SHIFT 0x18
+-#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE0_MEM_PWR_FORCE_MASK 0x00000003L
+-#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE0_MEM_PWR_DIS_MASK 0x00000004L
+-#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE1_MEM_PWR_FORCE_MASK 0x00000018L
+-#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE1_MEM_PWR_DIS_MASK 0x00000020L
+-#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE2_MEM_PWR_FORCE_MASK 0x000000C0L
+-#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE2_MEM_PWR_DIS_MASK 0x00000100L
+-#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE3_MEM_PWR_FORCE_MASK 0x00000600L
+-#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE3_MEM_PWR_DIS_MASK 0x00000800L
+-#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE4_MEM_PWR_FORCE_MASK 0x00003000L
+-#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE4_MEM_PWR_DIS_MASK 0x00004000L
+-#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE5_MEM_PWR_FORCE_MASK 0x00018000L
+-#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE5_MEM_PWR_DIS_MASK 0x00020000L
+-#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE6_MEM_PWR_FORCE_MASK 0x000C0000L
+-#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE6_MEM_PWR_DIS_MASK 0x00100000L
+-#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE7_MEM_PWR_FORCE_MASK 0x00600000L
+-#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE7_MEM_PWR_DIS_MASK 0x00800000L
+-#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE_MEM_PWR_MODE_SEL_MASK 0x03000000L
+-//DVMM_PTE_PGMEM_STATE
+-#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE0_PTE_PGMEM_STATE__SHIFT 0x0
+-#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE1_PTE_PGMEM_STATE__SHIFT 0x2
+-#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE2_PTE_PGMEM_STATE__SHIFT 0x4
+-#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE3_PTE_PGMEM_STATE__SHIFT 0x6
+-#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE4_PTE_PGMEM_STATE__SHIFT 0x8
+-#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE5_PTE_PGMEM_STATE__SHIFT 0xa
+-#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE6_PTE_PGMEM_STATE__SHIFT 0xc
+-#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE7_PTE_PGMEM_STATE__SHIFT 0xe
+-#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE0_PTE_PGMEM_STATE_MASK 0x00000003L
+-#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE1_PTE_PGMEM_STATE_MASK 0x0000000CL
+-#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE2_PTE_PGMEM_STATE_MASK 0x00000030L
+-#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE3_PTE_PGMEM_STATE_MASK 0x000000C0L
+-#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE4_PTE_PGMEM_STATE_MASK 0x00000300L
+-#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE5_PTE_PGMEM_STATE_MASK 0x00000C00L
+-#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE6_PTE_PGMEM_STATE_MASK 0x00003000L
+-#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE7_PTE_PGMEM_STATE_MASK 0x0000C000L
+-//MCIF_PHASE1_OUTSTANDING_COUNTER
+-#define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER__SHIFT 0x0
+-#define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL
+-//MCIF_PHASE2_OUTSTANDING_COUNTER
+-#define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER__SHIFT 0x0
+-#define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL
+-//MCIF_WB_PHASE0_OUTSTANDING_COUNTER
+-#define MCIF_WB_PHASE0_OUTSTANDING_COUNTER__MCIF_WB_PHASE0_OUTSTANDING_COUNTER__SHIFT 0x0
+-#define MCIF_WB_PHASE0_OUTSTANDING_COUNTER__MCIF_WB_PHASE0_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL
+-//MCIF_WB_PHASE1_OUTSTANDING_COUNTER
+-#define MCIF_WB_PHASE1_OUTSTANDING_COUNTER__MCIF_WB_PHASE1_OUTSTANDING_COUNTER__SHIFT 0x0
+-#define MCIF_WB_PHASE1_OUTSTANDING_COUNTER__MCIF_WB_PHASE1_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL
+-//DCI_MEM_PWR_CNTL4
+-#define DCI_MEM_PWR_CNTL4__MCIF_DWB_LUMA_MEM_EN_NUM__SHIFT 0x0
+-#define DCI_MEM_PWR_CNTL4__MCIF_DWB_CHROMA_MEM_EN_NUM__SHIFT 0x1
+-#define DCI_MEM_PWR_CNTL4__MCIF_CWB0_LUMA_MEM_EN_NUM__SHIFT 0x2
+-#define DCI_MEM_PWR_CNTL4__MCIF_CWB0_CHROMA_MEM_EN_NUM__SHIFT 0x3
+-#define DCI_MEM_PWR_CNTL4__MCIF_CWB1_LUMA_MEM_EN_NUM__SHIFT 0x4
+-#define DCI_MEM_PWR_CNTL4__MCIF_CWB1_CHROMA_MEM_EN_NUM__SHIFT 0x5
+-#define DCI_MEM_PWR_CNTL4__DMIF_CURSOR_MEM_PWR_FORCE__SHIFT 0x6
+-#define DCI_MEM_PWR_CNTL4__DMIF_CURSOR_MEM_PWR_DIS__SHIFT 0x8
+-#define DCI_MEM_PWR_CNTL4__DMIF_CURSOR_RD_REQ_MEM_PWR_FORCE__SHIFT 0x9
+-#define DCI_MEM_PWR_CNTL4__DMIF_CURSOR_RD_REQ_MEM_PWR_DIS__SHIFT 0xb
+-#define DCI_MEM_PWR_CNTL4__DMIF_CURSOR_RD_REQ_MEM_PWR_MODE_SEL__SHIFT 0xc
+-#define DCI_MEM_PWR_CNTL4__MCIF_DWB_LUMA_MEM_EN_NUM_MASK 0x00000001L
+-#define DCI_MEM_PWR_CNTL4__MCIF_DWB_CHROMA_MEM_EN_NUM_MASK 0x00000002L
+-#define DCI_MEM_PWR_CNTL4__MCIF_CWB0_LUMA_MEM_EN_NUM_MASK 0x00000004L
+-#define DCI_MEM_PWR_CNTL4__MCIF_CWB0_CHROMA_MEM_EN_NUM_MASK 0x00000008L
+-#define DCI_MEM_PWR_CNTL4__MCIF_CWB1_LUMA_MEM_EN_NUM_MASK 0x00000010L
+-#define DCI_MEM_PWR_CNTL4__MCIF_CWB1_CHROMA_MEM_EN_NUM_MASK 0x00000020L
+-#define DCI_MEM_PWR_CNTL4__DMIF_CURSOR_MEM_PWR_FORCE_MASK 0x000000C0L
+-#define DCI_MEM_PWR_CNTL4__DMIF_CURSOR_MEM_PWR_DIS_MASK 0x00000100L
+-#define DCI_MEM_PWR_CNTL4__DMIF_CURSOR_RD_REQ_MEM_PWR_FORCE_MASK 0x00000600L
+-#define DCI_MEM_PWR_CNTL4__DMIF_CURSOR_RD_REQ_MEM_PWR_DIS_MASK 0x00000800L
+-#define DCI_MEM_PWR_CNTL4__DMIF_CURSOR_RD_REQ_MEM_PWR_MODE_SEL_MASK 0x00003000L
+-//MCIF_WB_MISC_CTRL
+-#define MCIF_WB_MISC_CTRL__MCIFWB_WR_COMBINE_TIMEOUT_THRESH__SHIFT 0x0
+-#define MCIF_WB_MISC_CTRL__MCIF_WB_SOCCLK_DS_ENABLE__SHIFT 0x10
+-#define MCIF_WB_MISC_CTRL__MCIFWB_WR_COMBINE_TIMEOUT_THRESH_MASK 0x000003FFL
+-#define MCIF_WB_MISC_CTRL__MCIF_WB_SOCCLK_DS_ENABLE_MASK 0x00010000L
+-//DCI_MEM_PWR_STATUS3
+-#define DCI_MEM_PWR_STATUS3__MCIF_DWB_LUMA_MEM0_PWR_STATE__SHIFT 0x0
+-#define DCI_MEM_PWR_STATUS3__MCIF_DWB_LUMA_MEM1_PWR_STATE__SHIFT 0x2
+-#define DCI_MEM_PWR_STATUS3__MCIF_DWB_CHROMA_MEM0_PWR_STATE__SHIFT 0x4
+-#define DCI_MEM_PWR_STATUS3__MCIF_DWB_CHROMA_MEM1_PWR_STATE__SHIFT 0x6
+-#define DCI_MEM_PWR_STATUS3__MCIF_CWB0_LUMA_MEM0_PWR_STATE__SHIFT 0x8
+-#define DCI_MEM_PWR_STATUS3__MCIF_CWB0_LUMA_MEM1_PWR_STATE__SHIFT 0xa
+-#define DCI_MEM_PWR_STATUS3__MCIF_CWB0_CHROMA_MEM0_PWR_STATE__SHIFT 0xc
+-#define DCI_MEM_PWR_STATUS3__MCIF_CWB0_CHROMA_MEM1_PWR_STATE__SHIFT 0xe
+-#define DCI_MEM_PWR_STATUS3__MCIF_CWB1_LUMA_MEM0_PWR_STATE__SHIFT 0x10
+-#define DCI_MEM_PWR_STATUS3__MCIF_CWB1_LUMA_MEM1_PWR_STATE__SHIFT 0x12
+-#define DCI_MEM_PWR_STATUS3__MCIF_CWB1_CHROMA_MEM0_PWR_STATE__SHIFT 0x14
+-#define DCI_MEM_PWR_STATUS3__MCIF_CWB1_CHROMA_MEM1_PWR_STATE__SHIFT 0x16
+-#define DCI_MEM_PWR_STATUS3__MCIF_DWB_LUMA_MEM0_PWR_STATE_MASK 0x00000003L
+-#define DCI_MEM_PWR_STATUS3__MCIF_DWB_LUMA_MEM1_PWR_STATE_MASK 0x0000000CL
+-#define DCI_MEM_PWR_STATUS3__MCIF_DWB_CHROMA_MEM0_PWR_STATE_MASK 0x00000030L
+-#define DCI_MEM_PWR_STATUS3__MCIF_DWB_CHROMA_MEM1_PWR_STATE_MASK 0x000000C0L
+-#define DCI_MEM_PWR_STATUS3__MCIF_CWB0_LUMA_MEM0_PWR_STATE_MASK 0x00000300L
+-#define DCI_MEM_PWR_STATUS3__MCIF_CWB0_LUMA_MEM1_PWR_STATE_MASK 0x00000C00L
+-#define DCI_MEM_PWR_STATUS3__MCIF_CWB0_CHROMA_MEM0_PWR_STATE_MASK 0x00003000L
+-#define DCI_MEM_PWR_STATUS3__MCIF_CWB0_CHROMA_MEM1_PWR_STATE_MASK 0x0000C000L
+-#define DCI_MEM_PWR_STATUS3__MCIF_CWB1_LUMA_MEM0_PWR_STATE_MASK 0x00030000L
+-#define DCI_MEM_PWR_STATUS3__MCIF_CWB1_LUMA_MEM1_PWR_STATE_MASK 0x000C0000L
+-#define DCI_MEM_PWR_STATUS3__MCIF_CWB1_CHROMA_MEM0_PWR_STATE_MASK 0x00300000L
+-#define DCI_MEM_PWR_STATUS3__MCIF_CWB1_CHROMA_MEM1_PWR_STATE_MASK 0x00C00000L
+-//DMIF_CURSOR_CONTROL
+-#define DMIF_CURSOR_CONTROL__ADDRESS_TRANSLATION_ENABLE__SHIFT 0x4
+-#define DMIF_CURSOR_CONTROL__PRIVILEGED_ACCESS_ENABLE__SHIFT 0x8
+-#define DMIF_CURSOR_CONTROL__LOW_READ_URG_LEVEL__SHIFT 0x10
+-#define DMIF_CURSOR_CONTROL__DMIF_CURSOR_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x1e
+-#define DMIF_CURSOR_CONTROL__DMIF_CURSOR_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x1f
+-#define DMIF_CURSOR_CONTROL__ADDRESS_TRANSLATION_ENABLE_MASK 0x00000010L
+-#define DMIF_CURSOR_CONTROL__PRIVILEGED_ACCESS_ENABLE_MASK 0x00000100L
+-#define DMIF_CURSOR_CONTROL__LOW_READ_URG_LEVEL_MASK 0x00FF0000L
+-#define DMIF_CURSOR_CONTROL__DMIF_CURSOR_MC_LATENCY_COUNTER_ENABLE_MASK 0x40000000L
+-#define DMIF_CURSOR_CONTROL__DMIF_CURSOR_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x80000000L
+-//DMIF_CURSOR_MEM_CONTROL
+-#define DMIF_CURSOR_MEM_CONTROL__DMIF_CURSOR_MEM_CACHE_MODE_DIS__SHIFT 0x0
+-#define DMIF_CURSOR_MEM_CONTROL__DMIF_CURSOR_MEM_CACHE_MODE__SHIFT 0x4
+-#define DMIF_CURSOR_MEM_CONTROL__DMIF_CURSOR_MEM_CACHE_SIZE__SHIFT 0x8
+-#define DMIF_CURSOR_MEM_CONTROL__DMIF_CURSOR_MEM_CACHE_PIPE__SHIFT 0x10
+-#define DMIF_CURSOR_MEM_CONTROL__DMIF_CURSOR_MEM_CACHE_TYPE__SHIFT 0x13
+-#define DMIF_CURSOR_MEM_CONTROL__DMIF_CURSOR_MEM_CACHE_MODE_DIS_MASK 0x00000001L
+-#define DMIF_CURSOR_MEM_CONTROL__DMIF_CURSOR_MEM_CACHE_MODE_MASK 0x00000030L
+-#define DMIF_CURSOR_MEM_CONTROL__DMIF_CURSOR_MEM_CACHE_SIZE_MASK 0x0000FF00L
+-#define DMIF_CURSOR_MEM_CONTROL__DMIF_CURSOR_MEM_CACHE_PIPE_MASK 0x00070000L
+-#define DMIF_CURSOR_MEM_CONTROL__DMIF_CURSOR_MEM_CACHE_TYPE_MASK 0x00180000L
+-//DCHUB_FB_LOCATION
+-#define DCHUB_FB_LOCATION__FB_BASE__SHIFT 0x0
+-#define DCHUB_FB_LOCATION__FB_TOP__SHIFT 0x10
+-#define DCHUB_FB_LOCATION__FB_BASE_MASK 0x0000FFFFL
+-#define DCHUB_FB_LOCATION__FB_TOP_MASK 0xFFFF0000L
+-//DCHUB_FB_OFFSET
+-#define DCHUB_FB_OFFSET__FB_OFFSET__SHIFT 0x0
+-#define DCHUB_FB_OFFSET__FB_OFFSET_MASK 0x003FFFFFL
+-//DCHUB_AGP_BASE
+-#define DCHUB_AGP_BASE__AGP_BASE__SHIFT 0x0
+-#define DCHUB_AGP_BASE__AGP_BASE_MASK 0x003FFFFFL
+-//DCHUB_AGP_BOT
+-#define DCHUB_AGP_BOT__AGP_BOT__SHIFT 0x0
+-#define DCHUB_AGP_BOT__AGP_BOT_MASK 0x0003FFFFL
+-//DCHUB_AGP_TOP
+-#define DCHUB_AGP_TOP__AGP_TOP__SHIFT 0x0
+-#define DCHUB_AGP_TOP__AGP_TOP_MASK 0x0003FFFFL
+-//DCHUB_DRAM_APER_BASE
+-#define DCHUB_DRAM_APER_BASE__BASE__SHIFT 0x0
+-#define DCHUB_DRAM_APER_BASE__LOCK_DCHUB_DRAM_REGS__SHIFT 0x1c
+-#define DCHUB_DRAM_APER_BASE__BASE_MASK 0x00FFFFFFL
+-#define DCHUB_DRAM_APER_BASE__LOCK_DCHUB_DRAM_REGS_MASK 0x10000000L
+-//DCHUB_DRAM_APER_DEF
+-#define DCHUB_DRAM_APER_DEF__DEF__SHIFT 0x0
+-#define DCHUB_DRAM_APER_DEF__DEF_MASK 0xFFFFFFFFL
+-//DCHUB_DRAM_APER_TOP
+-#define DCHUB_DRAM_APER_TOP__TOP__SHIFT 0x0
+-#define DCHUB_DRAM_APER_TOP__TOP_MASK 0x00FFFFFFL
+-//DCHUB_CONTROL_STATUS
+-#define DCHUB_CONTROL_STATUS__NO_OUTSTANDING_REQ__SHIFT 0x0
+-#define DCHUB_CONTROL_STATUS__SDP_PORT_STATUS__SHIFT 0x4
+-#define DCHUB_CONTROL_STATUS__SDP_DATA_RESPONSE_STATUS__SHIFT 0x6
+-#define DCHUB_CONTROL_STATUS__SDP_REQ_CREDIT_ERROR__SHIFT 0x9
+-#define DCHUB_CONTROL_STATUS__SDP_DATA_RESPONSE_STATUS_CLEAR__SHIFT 0xc
+-#define DCHUB_CONTROL_STATUS__SDP_REQ_CREDIT_ERROR_CLEAR__SHIFT 0xd
+-#define DCHUB_CONTROL_STATUS__FLUSH_REQ_CREDIT_EN__SHIFT 0x10
+-#define DCHUB_CONTROL_STATUS__REQ_CREDIT_EN__SHIFT 0x11
+-#define DCHUB_CONTROL_STATUS__DCE_PORT_CONTROL__SHIFT 0x12
+-#define DCHUB_CONTROL_STATUS__SDP_CREDIT_DISCONNECT_DELAY__SHIFT 0x14
+-#define DCHUB_CONTROL_STATUS__NO_OUTSTANDING_REQ_MASK 0x00000001L
+-#define DCHUB_CONTROL_STATUS__SDP_PORT_STATUS_MASK 0x00000030L
+-#define DCHUB_CONTROL_STATUS__SDP_DATA_RESPONSE_STATUS_MASK 0x000001C0L
+-#define DCHUB_CONTROL_STATUS__SDP_REQ_CREDIT_ERROR_MASK 0x00000200L
+-#define DCHUB_CONTROL_STATUS__SDP_DATA_RESPONSE_STATUS_CLEAR_MASK 0x00001000L
+-#define DCHUB_CONTROL_STATUS__SDP_REQ_CREDIT_ERROR_CLEAR_MASK 0x00002000L
+-#define DCHUB_CONTROL_STATUS__FLUSH_REQ_CREDIT_EN_MASK 0x00010000L
+-#define DCHUB_CONTROL_STATUS__REQ_CREDIT_EN_MASK 0x00020000L
+-#define DCHUB_CONTROL_STATUS__DCE_PORT_CONTROL_MASK 0x00040000L
+-#define DCHUB_CONTROL_STATUS__SDP_CREDIT_DISCONNECT_DELAY_MASK 0x03F00000L
+-//WB_ENABLE
+-#define WB_ENABLE__WB_ENABLE__SHIFT 0x0
+-#define WB_ENABLE__WB_ENABLE_MASK 0x00000001L
+-//WB_EC_CONFIG
+-#define WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS__SHIFT 0x0
+-#define WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS__SHIFT 0x1
+-#define WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS__SHIFT 0x2
+-#define WB_EC_CONFIG__WB_TEST_CLK_SEL__SHIFT 0x3
+-#define WB_EC_CONFIG__WB_LB_LS_DIS__SHIFT 0x7
+-#define WB_EC_CONFIG__WB_LB_SD_DIS__SHIFT 0x8
+-#define WB_EC_CONFIG__WB_LUT_LS_DIS__SHIFT 0x9
+-#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL__SHIFT 0xc
+-#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS__SHIFT 0xe
+-#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE__SHIFT 0xf
+-#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_SM__SHIFT 0x11
+-#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_BG__SHIFT 0x13
+-#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE__SHIFT 0x15
+-#define WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE__SHIFT 0x17
+-#define WB_EC_CONFIG__LB_MEM_PWR_STATE_SM__SHIFT 0x18
+-#define WB_EC_CONFIG__LB_MEM_PWR_STATE_BG__SHIFT 0x1a
+-#define WB_EC_CONFIG__LB_MEM_PWR_STATE__SHIFT 0x1c
+-#define WB_EC_CONFIG__LUT_MEM_PWR_STATE__SHIFT 0x1e
+-#define WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS_MASK 0x00000001L
+-#define WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS_MASK 0x00000002L
+-#define WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS_MASK 0x00000004L
+-#define WB_EC_CONFIG__WB_TEST_CLK_SEL_MASK 0x00000078L
+-#define WB_EC_CONFIG__WB_LB_LS_DIS_MASK 0x00000080L
+-#define WB_EC_CONFIG__WB_LB_SD_DIS_MASK 0x00000100L
+-#define WB_EC_CONFIG__WB_LUT_LS_DIS_MASK 0x00000200L
+-#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL_MASK 0x00003000L
+-#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS_MASK 0x00004000L
+-#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE_MASK 0x00018000L
+-#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_SM_MASK 0x00060000L
+-#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_BG_MASK 0x00180000L
+-#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_MASK 0x00600000L
+-#define WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE_MASK 0x00800000L
+-#define WB_EC_CONFIG__LB_MEM_PWR_STATE_SM_MASK 0x03000000L
+-#define WB_EC_CONFIG__LB_MEM_PWR_STATE_BG_MASK 0x0C000000L
+-#define WB_EC_CONFIG__LB_MEM_PWR_STATE_MASK 0x30000000L
+-#define WB_EC_CONFIG__LUT_MEM_PWR_STATE_MASK 0xC0000000L
+-//CNV_MODE
+-#define CNV_MODE__CNV_FRAME_CAPTURE_RATE__SHIFT 0x8
+-#define CNV_MODE__CNV_WINDOW_CROP_EN__SHIFT 0xc
+-#define CNV_MODE__CNV_STEREO_TYPE__SHIFT 0xd
+-#define CNV_MODE__CNV_INTERLACED_MODE__SHIFT 0xf
+-#define CNV_MODE__CNV_EYE_SELECTION__SHIFT 0x10
+-#define CNV_MODE__CNV_STEREO_POLARITY__SHIFT 0x12
+-#define CNV_MODE__CNV_INTERLACED_FIELD_ORDER__SHIFT 0x13
+-#define CNV_MODE__CNV_STEREO_SPLIT__SHIFT 0x14
+-#define CNV_MODE__CNV_NEW_CONTENT__SHIFT 0x18
+-#define CNV_MODE__CNV_FRAME_CAPTURE_EN__SHIFT 0x1f
+-#define CNV_MODE__CNV_FRAME_CAPTURE_RATE_MASK 0x00000300L
+-#define CNV_MODE__CNV_WINDOW_CROP_EN_MASK 0x00001000L
+-#define CNV_MODE__CNV_STEREO_TYPE_MASK 0x00006000L
+-#define CNV_MODE__CNV_INTERLACED_MODE_MASK 0x00008000L
+-#define CNV_MODE__CNV_EYE_SELECTION_MASK 0x00030000L
+-#define CNV_MODE__CNV_STEREO_POLARITY_MASK 0x00040000L
+-#define CNV_MODE__CNV_INTERLACED_FIELD_ORDER_MASK 0x00080000L
+-#define CNV_MODE__CNV_STEREO_SPLIT_MASK 0x00100000L
+-#define CNV_MODE__CNV_NEW_CONTENT_MASK 0x01000000L
+-#define CNV_MODE__CNV_FRAME_CAPTURE_EN_MASK 0x80000000L
+-//CNV_WINDOW_START
+-#define CNV_WINDOW_START__CNV_WINDOW_START_X__SHIFT 0x0
+-#define CNV_WINDOW_START__CNV_WINDOW_START_Y__SHIFT 0x10
+-#define CNV_WINDOW_START__CNV_WINDOW_START_X_MASK 0x00000FFFL
+-#define CNV_WINDOW_START__CNV_WINDOW_START_Y_MASK 0x0FFF0000L
+-//CNV_WINDOW_SIZE
+-#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH__SHIFT 0x0
+-#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT__SHIFT 0x10
+-#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH_MASK 0x00000FFFL
+-#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT_MASK 0x0FFF0000L
+-//CNV_UPDATE
+-#define CNV_UPDATE__CNV_UPDATE_PENDING__SHIFT 0x0
+-#define CNV_UPDATE__CNV_UPDATE_TAKEN__SHIFT 0x8
+-#define CNV_UPDATE__CNV_UPDATE_LOCK__SHIFT 0x10
+-#define CNV_UPDATE__CNV_UPDATE_PENDING_MASK 0x00000001L
+-#define CNV_UPDATE__CNV_UPDATE_TAKEN_MASK 0x00000100L
+-#define CNV_UPDATE__CNV_UPDATE_LOCK_MASK 0x00010000L
+-//CNV_SOURCE_SIZE
+-#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH__SHIFT 0x0
+-#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT__SHIFT 0x10
+-#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH_MASK 0x00007FFFL
+-#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT_MASK 0x7FFF0000L
+-//CNV_CSC_CONTROL
+-#define CNV_CSC_CONTROL__CNV_CSC_BYPASS__SHIFT 0x0
+-#define CNV_CSC_CONTROL__CNV_CSC_BYPASS_MASK 0x00000001L
+-//CNV_CSC_C11_C12
+-#define CNV_CSC_C11_C12__CNV_CSC_C11__SHIFT 0x0
+-#define CNV_CSC_C11_C12__CNV_CSC_C12__SHIFT 0x10
+-#define CNV_CSC_C11_C12__CNV_CSC_C11_MASK 0x00001FFFL
+-#define CNV_CSC_C11_C12__CNV_CSC_C12_MASK 0x1FFF0000L
+-//CNV_CSC_C13_C14
+-#define CNV_CSC_C13_C14__CNV_CSC_C13__SHIFT 0x0
+-#define CNV_CSC_C13_C14__CNV_CSC_C14__SHIFT 0x10
+-#define CNV_CSC_C13_C14__CNV_CSC_C13_MASK 0x00001FFFL
+-#define CNV_CSC_C13_C14__CNV_CSC_C14_MASK 0x7FFF0000L
+-//CNV_CSC_C21_C22
+-#define CNV_CSC_C21_C22__CNV_CSC_C21__SHIFT 0x0
+-#define CNV_CSC_C21_C22__CNV_CSC_C22__SHIFT 0x10
+-#define CNV_CSC_C21_C22__CNV_CSC_C21_MASK 0x00001FFFL
+-#define CNV_CSC_C21_C22__CNV_CSC_C22_MASK 0x1FFF0000L
+-//CNV_CSC_C23_C24
+-#define CNV_CSC_C23_C24__CNV_CSC_C23__SHIFT 0x0
+-#define CNV_CSC_C23_C24__CNV_CSC_C24__SHIFT 0x10
+-#define CNV_CSC_C23_C24__CNV_CSC_C23_MASK 0x00001FFFL
+-#define CNV_CSC_C23_C24__CNV_CSC_C24_MASK 0x7FFF0000L
+-//CNV_CSC_C31_C32
+-#define CNV_CSC_C31_C32__CNV_CSC_C31__SHIFT 0x0
+-#define CNV_CSC_C31_C32__CNV_CSC_C32__SHIFT 0x10
+-#define CNV_CSC_C31_C32__CNV_CSC_C31_MASK 0x00001FFFL
+-#define CNV_CSC_C31_C32__CNV_CSC_C32_MASK 0x1FFF0000L
+-//CNV_CSC_C33_C34
+-#define CNV_CSC_C33_C34__CNV_CSC_C33__SHIFT 0x0
+-#define CNV_CSC_C33_C34__CNV_CSC_C34__SHIFT 0x10
+-#define CNV_CSC_C33_C34__CNV_CSC_C33_MASK 0x00001FFFL
+-#define CNV_CSC_C33_C34__CNV_CSC_C34_MASK 0x7FFF0000L
+-//CNV_CSC_ROUND_OFFSET_R
+-#define CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R__SHIFT 0x0
+-#define CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R_MASK 0x0000FFFFL
+-//CNV_CSC_ROUND_OFFSET_G
+-#define CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G__SHIFT 0x0
+-#define CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G_MASK 0x0000FFFFL
+-//CNV_CSC_ROUND_OFFSET_B
+-#define CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B__SHIFT 0x0
+-#define CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B_MASK 0x0000FFFFL
+-//CNV_CSC_CLAMP_R
+-#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R__SHIFT 0x0
+-#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R__SHIFT 0x10
+-#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R_MASK 0x0000FFFFL
+-#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R_MASK 0xFFFF0000L
+-//CNV_CSC_CLAMP_G
+-#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G__SHIFT 0x0
+-#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G__SHIFT 0x10
+-#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G_MASK 0x0000FFFFL
+-#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G_MASK 0xFFFF0000L
+-//CNV_CSC_CLAMP_B
+-#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B__SHIFT 0x0
+-#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B__SHIFT 0x10
+-#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B_MASK 0x0000FFFFL
+-#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B_MASK 0xFFFF0000L
+-//CNV_TEST_CNTL
+-#define CNV_TEST_CNTL__CNV_TEST_CRC_EN__SHIFT 0x4
+-#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN__SHIFT 0x8
+-#define CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY__SHIFT 0x10
+-#define CNV_TEST_CNTL__CNV_TEST_CRC_EN_MASK 0x00000010L
+-#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN_MASK 0x00000100L
+-#define CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY_MASK 0x00010000L
+-//CNV_TEST_CRC_RED
+-#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK__SHIFT 0x4
+-#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED__SHIFT 0x10
+-#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK_MASK 0x0000FFF0L
+-#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED_MASK 0xFFFF0000L
+-//CNV_TEST_CRC_GREEN
+-#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK__SHIFT 0x4
+-#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN__SHIFT 0x10
+-#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK_MASK 0x0000FFF0L
+-#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN_MASK 0xFFFF0000L
+-//CNV_TEST_CRC_BLUE
+-#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK__SHIFT 0x4
+-#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE__SHIFT 0x10
+-#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK_MASK 0x0000FFF0L
+-#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE_MASK 0xFFFF0000L
+-//CNV_INPUT_SELECT
+-#define CNV_INPUT_SELECT__CNV_INPUT_SRC_SELECT__SHIFT 0x0
+-#define CNV_INPUT_SELECT__CNV_INPUT_PIPE_SELECT__SHIFT 0x2
+-#define CNV_INPUT_SELECT__CNV_INPUT_SRC_SELECT_MASK 0x00000003L
+-#define CNV_INPUT_SELECT__CNV_INPUT_PIPE_SELECT_MASK 0x0000001CL
+-//WB_SOFT_RESET
+-#define WB_SOFT_RESET__WB_SOFT_RESET__SHIFT 0x0
+-#define WB_SOFT_RESET__WB_SOFT_RESET_MASK 0x00000001L
+-//WB_WARM_UP_MODE_CTL1
+-#define WB_WARM_UP_MODE_CTL1__WIDTH_WARMUP__SHIFT 0x0
+-#define WB_WARM_UP_MODE_CTL1__HEIGHT_WARMUP__SHIFT 0x10
+-#define WB_WARM_UP_MODE_CTL1__GMC_WARM_UP_ENABLE__SHIFT 0x1f
+-#define WB_WARM_UP_MODE_CTL1__WIDTH_WARMUP_MASK 0x00007FFFL
+-#define WB_WARM_UP_MODE_CTL1__HEIGHT_WARMUP_MASK 0x7FFF0000L
+-#define WB_WARM_UP_MODE_CTL1__GMC_WARM_UP_ENABLE_MASK 0x80000000L
+-//WB_WARM_UP_MODE_CTL2
+-#define WB_WARM_UP_MODE_CTL2__DATA_VALUE_WARMUP__SHIFT 0x0
+-#define WB_WARM_UP_MODE_CTL2__MODE_WARMUP__SHIFT 0x8
+-#define WB_WARM_UP_MODE_CTL2__DATA_VALUE_WARMUP_MASK 0x000000FFL
+-#define WB_WARM_UP_MODE_CTL2__MODE_WARMUP_MASK 0x00000100L
+-//WBSCL_COEF_RAM_SELECT
+-#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0
+-#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_PHASE__SHIFT 0x8
+-#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10
+-#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000007L
+-#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_PHASE_MASK 0x00000F00L
+-#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_FILTER_TYPE_MASK 0x00030000L
+-//WBSCL_COEF_RAM_TAP_DATA
+-#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0
+-#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
+-#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10
+-#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
+-#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL
+-#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L
+-#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L
+-#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L
+-//WBSCL_MODE
+-#define WBSCL_MODE__WBSCL_MODE__SHIFT 0x0
+-#define WBSCL_MODE__WBSCL_MODE_MASK 0x00000003L
+-//WBSCL_TAP_CONTROL
+-#define WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_Y_RGB__SHIFT 0x0
+-#define WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_CBCR__SHIFT 0x4
+-#define WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_Y_RGB__SHIFT 0x8
+-#define WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_CBCR__SHIFT 0xc
+-#define WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_Y_RGB_MASK 0x0000000FL
+-#define WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_CBCR_MASK 0x000000F0L
+-#define WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_Y_RGB_MASK 0x00000F00L
+-#define WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_CBCR_MASK 0x0000F000L
+-//WBSCL_DEST_SIZE
+-#define WBSCL_DEST_SIZE__WBSCL_DEST_HEIGHT__SHIFT 0x0
+-#define WBSCL_DEST_SIZE__WBSCL_DEST_WIDTH__SHIFT 0x10
+-#define WBSCL_DEST_SIZE__WBSCL_DEST_HEIGHT_MASK 0x00007FFFL
+-#define WBSCL_DEST_SIZE__WBSCL_DEST_WIDTH_MASK 0x7FFF0000L
+-//WBSCL_HORZ_FILTER_SCALE_RATIO
+-#define WBSCL_HORZ_FILTER_SCALE_RATIO__WBSCL_H_SCALE_RATIO__SHIFT 0x0
+-#define WBSCL_HORZ_FILTER_SCALE_RATIO__WBSCL_H_SCALE_RATIO_MASK 0x07FFFFFFL
+-//WBSCL_HORZ_FILTER_INIT_Y_RGB
+-#define WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_FRAC_Y_RGB__SHIFT 0x0
+-#define WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_INT_Y_RGB__SHIFT 0x18
+-#define WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_FRAC_Y_RGB_MASK 0x00FFFFFFL
+-#define WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_INT_Y_RGB_MASK 0x1F000000L
+-//WBSCL_HORZ_FILTER_INIT_CBCR
+-#define WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_FRAC_CBCR__SHIFT 0x0
+-#define WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_INT_CBCR__SHIFT 0x18
+-#define WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_FRAC_CBCR_MASK 0x00FFFFFFL
+-#define WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_INT_CBCR_MASK 0x1F000000L
+-//WBSCL_VERT_FILTER_SCALE_RATIO
+-#define WBSCL_VERT_FILTER_SCALE_RATIO__WBSCL_V_SCALE_RATIO__SHIFT 0x0
+-#define WBSCL_VERT_FILTER_SCALE_RATIO__WBSCL_V_SCALE_RATIO_MASK 0x07FFFFFFL
+-//WBSCL_VERT_FILTER_INIT_Y_RGB
+-#define WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_FRAC_Y_RGB__SHIFT 0x0
+-#define WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_INT_Y_RGB__SHIFT 0x18
+-#define WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_FRAC_Y_RGB_MASK 0x00FFFFFFL
+-#define WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_INT_Y_RGB_MASK 0x1F000000L
+-//WBSCL_VERT_FILTER_INIT_CBCR
+-#define WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_FRAC_CBCR__SHIFT 0x0
+-#define WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_INT_CBCR__SHIFT 0x18
+-#define WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_FRAC_CBCR_MASK 0x00FFFFFFL
+-#define WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_INT_CBCR_MASK 0x1F000000L
+-//WBSCL_ROUND_OFFSET
+-#define WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_Y_RGB__SHIFT 0x0
+-#define WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_CBCR__SHIFT 0x10
+-#define WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_Y_RGB_MASK 0x0000FFFFL
+-#define WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_CBCR_MASK 0xFFFF0000L
+-//WBSCL_CLAMP
+-#define WBSCL_CLAMP__WBSCL_CLAMP_UPPER_Y_RGB__SHIFT 0x0
+-#define WBSCL_CLAMP__WBSCL_CLAMP_LOWER_Y_RGB__SHIFT 0x8
+-#define WBSCL_CLAMP__WBSCL_CLAMP_UPPER_CBCR__SHIFT 0x10
+-#define WBSCL_CLAMP__WBSCL_CLAMP_LOWER_CBCR__SHIFT 0x18
+-#define WBSCL_CLAMP__WBSCL_CLAMP_UPPER_Y_RGB_MASK 0x000000FFL
+-#define WBSCL_CLAMP__WBSCL_CLAMP_LOWER_Y_RGB_MASK 0x0000FF00L
+-#define WBSCL_CLAMP__WBSCL_CLAMP_UPPER_CBCR_MASK 0x00FF0000L
+-#define WBSCL_CLAMP__WBSCL_CLAMP_LOWER_CBCR_MASK 0xFF000000L
+-//WBSCL_OVERFLOW_STATUS
+-#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_FLAG__SHIFT 0x0
+-#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_ACK__SHIFT 0x8
+-#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_MASK__SHIFT 0xc
+-#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_STATUS__SHIFT 0x10
+-#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_TYPE__SHIFT 0x14
+-#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_FLAG_MASK 0x00000001L
+-#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_ACK_MASK 0x00000100L
+-#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_MASK_MASK 0x00001000L
+-#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_STATUS_MASK 0x00010000L
+-#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_TYPE_MASK 0x00100000L
+-//WBSCL_COEF_RAM_CONFLICT_STATUS
+-#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_FLAG__SHIFT 0x0
+-#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_ACK__SHIFT 0x8
+-#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_MASK__SHIFT 0xc
+-#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10
+-#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_TYPE__SHIFT 0x14
+-#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_FLAG_MASK 0x00000001L
+-#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_ACK_MASK 0x00000100L
+-#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_MASK_MASK 0x00001000L
+-#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_STATUS_MASK 0x00010000L
+-#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_TYPE_MASK 0x00100000L
+-//WBSCL_OUTSIDE_PIX_STRATEGY
+-#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_OUTSIDE_PIX_STRATEGY__SHIFT 0x0
+-#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_B_CB__SHIFT 0x8
+-#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_G_Y__SHIFT 0x10
+-#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_R_CR__SHIFT 0x18
+-#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_OUTSIDE_PIX_STRATEGY_MASK 0x00000001L
+-#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_B_CB_MASK 0x0000FF00L
+-#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_G_Y_MASK 0x00FF0000L
+-#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_R_CR_MASK 0xFF000000L
+-//WBSCL_TEST_CNTL
+-#define WBSCL_TEST_CNTL__WBSCL_TEST_CRC_EN__SHIFT 0x4
+-#define WBSCL_TEST_CNTL__WBSCL_TEST_CRC_CONT_EN__SHIFT 0x8
+-#define WBSCL_TEST_CNTL__WBSCL_TEST_CRC_DE_ONLY__SHIFT 0x10
+-#define WBSCL_TEST_CNTL__WBSCL_TEST_CRC_EN_MASK 0x00000010L
+-#define WBSCL_TEST_CNTL__WBSCL_TEST_CRC_CONT_EN_MASK 0x00000100L
+-#define WBSCL_TEST_CNTL__WBSCL_TEST_CRC_DE_ONLY_MASK 0x00010000L
+-//WBSCL_TEST_CRC_RED
+-#define WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_RED_MASK__SHIFT 0x8
+-#define WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_SIG_RED__SHIFT 0x10
+-#define WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_RED_MASK_MASK 0x0000FF00L
+-#define WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_SIG_RED_MASK 0xFFFF0000L
+-//WBSCL_TEST_CRC_GREEN
+-#define WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_GREEN_MASK__SHIFT 0x0
+-#define WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_SIG_GREEN__SHIFT 0x10
+-#define WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_GREEN_MASK_MASK 0x0000FFFFL
+-#define WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_SIG_GREEN_MASK 0xFFFF0000L
+-//WBSCL_TEST_CRC_BLUE
+-#define WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_BLUE_MASK__SHIFT 0x8
+-#define WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_SIG_BLUE__SHIFT 0x10
+-#define WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_BLUE_MASK_MASK 0x0000FF00L
+-#define WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_SIG_BLUE_MASK 0xFFFF0000L
+-//WBSCL_BACKPRESSURE_CNT_EN
+-#define WBSCL_BACKPRESSURE_CNT_EN__WBSCL_BACKPRESSURE_CNT_EN__SHIFT 0x0
+-#define WBSCL_BACKPRESSURE_CNT_EN__WBSCL_BACKPRESSURE_CNT_EN_MASK 0x00000001L
+-//WB_MCIF_BACKPRESSURE_CNT
+-#define WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_Y_MAX_BACKPRESSURE__SHIFT 0x0
+-#define WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_C_MAX_BACKPRESSURE__SHIFT 0x10
+-#define WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_Y_MAX_BACKPRESSURE_MASK 0x0000FFFFL
+-#define WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_C_MAX_BACKPRESSURE_MASK 0xFFFF0000L
+-//WBSCL_RAM_SHUTDOWN
+-#define WBSCL_RAM_SHUTDOWN__WBSCL_RAM_SHUTDOWN_SEL__SHIFT 0x0
+-#define WBSCL_RAM_SHUTDOWN__WBSCL_RAM_SHUTDOWN_SEL_MASK 0x00000003L
+-//DMCU_CTRL
+-#define DMCU_CTRL__RESET_UC__SHIFT 0x0
+-#define DMCU_CTRL__IGNORE_PWRMGT__SHIFT 0x1
+-#define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT 0x2
+-#define DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT 0x3
+-#define DMCU_CTRL__DMCU_ENABLE__SHIFT 0x4
+-#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN__SHIFT 0x8
+-#define DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT 0x10
+-#define DMCU_CTRL__RESET_UC_MASK 0x00000001L
+-#define DMCU_CTRL__IGNORE_PWRMGT_MASK 0x00000002L
+-#define DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK 0x00000004L
+-#define DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK 0x00000008L
+-#define DMCU_CTRL__DMCU_ENABLE_MASK 0x00000010L
+-#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN_MASK 0x00000100L
+-#define DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK 0xFFFF0000L
+-//DMCU_STATUS
+-#define DMCU_STATUS__UC_IN_RESET__SHIFT 0x0
+-#define DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT 0x1
+-#define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT 0x2
+-#define DMCU_STATUS__UC_IN_RESET_MASK 0x00000001L
+-#define DMCU_STATUS__UC_IN_WAIT_MODE_MASK 0x00000002L
+-#define DMCU_STATUS__UC_IN_STOP_MODE_MASK 0x00000004L
+-//DMCU_PC_START_ADDR
+-#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT 0x0
+-#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT 0x8
+-#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK 0x000000FFL
+-#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK 0x0000FF00L
+-//DMCU_FW_START_ADDR
+-#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT 0x0
+-#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT 0x8
+-#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK 0x000000FFL
+-#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK 0x0000FF00L
+-//DMCU_FW_END_ADDR
+-#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT 0x0
+-#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT 0x8
+-#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK 0x000000FFL
+-#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK 0x0000FF00L
+-//DMCU_FW_ISR_START_ADDR
+-#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT 0x0
+-#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT 0x8
+-#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK 0x000000FFL
+-#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK 0x0000FF00L
+-//DMCU_FW_CS_HI
+-#define DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT 0x0
+-#define DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK 0xFFFFFFFFL
+-//DMCU_FW_CS_LO
+-#define DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT 0x0
+-#define DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK 0xFFFFFFFFL
+-//DMCU_RAM_ACCESS_CTRL
+-#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT 0x0
+-#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT 0x1
+-#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT 0x2
+-#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT 0x3
+-#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN__SHIFT 0x4
+-#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT 0x5
+-#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK 0x00000001L
+-#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK 0x00000002L
+-#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK 0x00000004L
+-#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK 0x00000008L
+-#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN_MASK 0x00000010L
+-#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK 0x00000020L
+-//DMCU_ERAM_WR_CTRL
+-#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT 0x0
+-#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT 0x10
+-#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT 0x14
+-#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK 0x0000FFFFL
+-#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK 0x000F0000L
+-#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK 0x00100000L
+-//DMCU_ERAM_WR_DATA
+-#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT 0x0
+-#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK 0xFFFFFFFFL
+-//DMCU_ERAM_RD_CTRL
+-#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT 0x0
+-#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT 0x10
+-#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT 0x14
+-#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK 0x0000FFFFL
+-#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK 0x000F0000L
+-#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK 0x00100000L
+-//DMCU_ERAM_RD_DATA
+-#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT 0x0
+-#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK 0xFFFFFFFFL
+-//DMCU_IRAM_WR_CTRL
+-#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT 0x0
+-#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK 0x000003FFL
+-//DMCU_IRAM_WR_DATA
+-#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT 0x0
+-#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK 0x000000FFL
+-//DMCU_IRAM_RD_CTRL
+-#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT 0x0
+-#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK 0x000003FFL
+-//DMCU_IRAM_RD_DATA
+-#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT 0x0
+-#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK 0x000000FFL
+-//DMCU_EVENT_TRIGGER
+-#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC__SHIFT 0x0
+-#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT 0x10
+-#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST__SHIFT 0x17
+-#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC_MASK 0x00000001L
+-#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK 0x007F0000L
+-#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST_MASK 0x00800000L
+-//DMCU_UC_INTERNAL_INT_STATUS
+-#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT 0x0
+-#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT 0x1
+-#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT 0x2
+-#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT 0x3
+-#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT 0x4
+-#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT 0x5
+-#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT 0x6
+-#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT 0x7
+-#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT 0x8
+-#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT 0x9
+-#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT 0xa
+-#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT 0xb
+-#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT 0xc
+-#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT 0xd
+-#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT 0xe
+-#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT 0xf
+-#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK 0x00000001L
+-#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK 0x00000002L
+-#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK 0x00000004L
+-#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK 0x00000008L
+-#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK 0x00000010L
+-#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK 0x00000020L
+-#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK 0x00000040L
+-#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK 0x00000080L
+-#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK 0x00000100L
+-#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK 0x00000200L
+-#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK 0x00000400L
+-#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK 0x00000800L
+-#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK 0x00001000L
+-#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK 0x00002000L
+-#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK 0x00004000L
+-#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK 0x00008000L
+-//DMCU_SS_INTERRUPT_CNTL_STATUS
+-#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS__SHIFT 0xd
+-#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED__SHIFT 0xe
+-#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR__SHIFT 0xe
+-#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS__SHIFT 0xf
+-#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED__SHIFT 0x10
+-#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR__SHIFT 0x10
+-#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS__SHIFT 0x11
+-#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED__SHIFT 0x12
+-#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR__SHIFT 0x12
+-#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS__SHIFT 0x13
+-#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED__SHIFT 0x14
+-#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR__SHIFT 0x14
+-#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS__SHIFT 0x15
+-#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED__SHIFT 0x16
+-#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR__SHIFT 0x16
+-#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS__SHIFT 0x17
+-#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED__SHIFT 0x18
+-#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR__SHIFT 0x18
+-#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS_MASK 0x00002000L
+-#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED_MASK 0x00004000L
+-#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR_MASK 0x00004000L
+-#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS_MASK 0x00008000L
+-#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED_MASK 0x00010000L
+-#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR_MASK 0x00010000L
+-#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS_MASK 0x00020000L
+-#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED_MASK 0x00040000L
+-#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR_MASK 0x00040000L
+-#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS_MASK 0x00080000L
+-#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED_MASK 0x00100000L
+-#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR_MASK 0x00100000L
+-#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS_MASK 0x00200000L
+-#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED_MASK 0x00400000L
+-#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR_MASK 0x00400000L
+-#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS_MASK 0x00800000L
+-#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED_MASK 0x01000000L
+-#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR_MASK 0x01000000L
+-//DMCU_INTERRUPT_STATUS
+-#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT 0x0
+-#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT 0x0
+-#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT 0x1
+-#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT 0x1
+-#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT 0x2
+-#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT 0x2
+-#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT 0x3
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_OCCURRED__SHIFT 0x4
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_CLEAR__SHIFT 0x4
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_OCCURRED__SHIFT 0x5
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_CLEAR__SHIFT 0x5
+-#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT 0x8
+-#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT 0x8
+-#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT 0x9
+-#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT 0xa
+-#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT 0xa
+-#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT 0xb
+-#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT 0xb
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED__SHIFT 0xc
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR__SHIFT 0xc
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED__SHIFT 0xd
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR__SHIFT 0xd
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED__SHIFT 0xe
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR__SHIFT 0xe
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED__SHIFT 0xf
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR__SHIFT 0xf
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED__SHIFT 0x10
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR__SHIFT 0x10
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED__SHIFT 0x11
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR__SHIFT 0x11
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED__SHIFT 0x12
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR__SHIFT 0x12
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED__SHIFT 0x13
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR__SHIFT 0x13
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED__SHIFT 0x14
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR__SHIFT 0x14
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED__SHIFT 0x15
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR__SHIFT 0x15
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED__SHIFT 0x16
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR__SHIFT 0x16
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED__SHIFT 0x17
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR__SHIFT 0x17
+-#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT 0x18
+-#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT 0x18
+-#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT 0x19
+-#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT 0x19
+-#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED__SHIFT 0x1a
+-#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR__SHIFT 0x1a
+-#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED__SHIFT 0x1b
+-#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT 0x1b
+-#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED__SHIFT 0x1c
+-#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR__SHIFT 0x1c
+-#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED__SHIFT 0x1d
+-#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR__SHIFT 0x1d
+-#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK 0x00000001L
+-#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK 0x00000001L
+-#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK 0x00000002L
+-#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK 0x00000002L
+-#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK 0x00000004L
+-#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK 0x00000004L
+-#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK 0x00000008L
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_OCCURRED_MASK 0x00000010L
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_CLEAR_MASK 0x00000010L
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_OCCURRED_MASK 0x00000020L
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_CLEAR_MASK 0x00000020L
+-#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK 0x00000100L
+-#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK 0x00000100L
+-#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK 0x00000200L
+-#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK 0x00000400L
+-#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK 0x00000400L
+-#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK 0x00000800L
+-#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK 0x00000800L
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED_MASK 0x00001000L
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR_MASK 0x00001000L
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED_MASK 0x00002000L
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR_MASK 0x00002000L
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED_MASK 0x00004000L
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR_MASK 0x00004000L
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED_MASK 0x00008000L
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR_MASK 0x00008000L
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED_MASK 0x00010000L
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR_MASK 0x00010000L
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED_MASK 0x00020000L
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR_MASK 0x00020000L
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED_MASK 0x00040000L
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR_MASK 0x00040000L
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED_MASK 0x00080000L
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR_MASK 0x00080000L
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED_MASK 0x00100000L
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR_MASK 0x00100000L
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED_MASK 0x00200000L
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR_MASK 0x00200000L
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED_MASK 0x00400000L
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR_MASK 0x00400000L
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED_MASK 0x00800000L
+-#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR_MASK 0x00800000L
+-#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x01000000L
+-#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK 0x01000000L
+-#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK 0x02000000L
+-#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK 0x02000000L
+-#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK 0x04000000L
+-#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x04000000L
+-#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED_MASK 0x08000000L
+-#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR_MASK 0x08000000L
+-#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK 0x10000000L
+-#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR_MASK 0x10000000L
+-#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED_MASK 0x20000000L
+-#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR_MASK 0x20000000L
+-//DMCU_INTERRUPT_TO_HOST_EN_MASK
+-#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT 0x0
+-#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT 0x1
+-#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT 0x2
+-#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT 0x9
+-#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT 0xa
+-#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT 0xb
+-#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK 0x00000001L
+-#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK 0x00000002L
+-#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK 0x00000004L
+-#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK 0x00000200L
+-#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK 0x00000400L
+-#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK 0x00000800L
+-//DMCU_INTERRUPT_TO_UC_EN_MASK
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT 0x0
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT 0x1
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x2
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT 0x3
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_TO_UC_EN__SHIFT 0x4
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x5
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN__SHIFT 0x6
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN__SHIFT 0x7
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT 0x8
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN__SHIFT 0x9
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN__SHIFT 0xa
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN__SHIFT 0xb
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN__SHIFT 0xc
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN__SHIFT 0xd
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN__SHIFT 0xe
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN__SHIFT 0xf
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN__SHIFT 0x10
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN__SHIFT 0x11
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x12
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x13
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x14
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x15
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x16
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x17
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT 0x18
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT 0x19
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN__SHIFT 0x1a
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN__SHIFT 0x1b
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN__SHIFT 0x1c
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN__SHIFT 0x1d
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN__SHIFT 0x1e
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK 0x00000001L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK 0x00000002L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK 0x00000004L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK 0x00000008L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_TO_UC_EN_MASK 0x00000010L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000020L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN_MASK 0x00000040L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN_MASK 0x00000080L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK 0x00000100L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN_MASK 0x00000200L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN_MASK 0x00000400L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN_MASK 0x00000800L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN_MASK 0x00001000L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN_MASK 0x00002000L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN_MASK 0x00004000L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN_MASK 0x00008000L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN_MASK 0x00010000L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN_MASK 0x00020000L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN_MASK 0x00040000L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN_MASK 0x00080000L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN_MASK 0x00100000L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN_MASK 0x00200000L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN_MASK 0x00400000L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN_MASK 0x00800000L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK 0x01000000L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK 0x02000000L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN_MASK 0x04000000L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN_MASK 0x08000000L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN_MASK 0x10000000L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN_MASK 0x20000000L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN_MASK 0x40000000L
+-//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x2
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT 0x3
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x5
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL__SHIFT 0x7
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT 0x8
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL__SHIFT 0x9
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL__SHIFT 0xa
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL__SHIFT 0xb
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xc
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xd
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xe
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xf
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x10
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x11
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x12
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x13
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x14
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x15
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x16
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x17
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT 0x18
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT 0x19
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL__SHIFT 0x1b
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL__SHIFT 0x1c
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL__SHIFT 0x1d
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL__SHIFT 0x1e
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x00000001L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x00000002L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000004L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK 0x00000008L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000010L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000020L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL_MASK 0x00000040L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL_MASK 0x00000080L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x00000100L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL_MASK 0x00000200L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL_MASK 0x00000400L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL_MASK 0x00000800L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00001000L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00002000L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00004000L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00008000L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00010000L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00020000L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00040000L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00080000L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00100000L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00200000L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00400000L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00800000L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK 0x01000000L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK 0x02000000L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL_MASK 0x04000000L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL_MASK 0x08000000L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL_MASK 0x10000000L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL_MASK 0x20000000L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL_MASK 0x40000000L
+-//DC_DMCU_SCRATCH
+-#define DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT 0x0
+-#define DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK 0xFFFFFFFFL
+-//DMCU_INT_CNT
+-#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT 0x0
+-#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT 0x8
+-#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT 0x10
+-#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK 0x000000FFL
+-#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK 0x0000FF00L
+-#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK 0x00FF0000L
+-//DMCU_FW_CHECKSUM_SMPL_BYTE_POS
+-#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT 0x0
+-#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT 0x2
+-#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK 0x00000003L
+-#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK 0x0000000CL
+-//DMCU_UC_CLK_GATING_CNTL
+-#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY__SHIFT 0x0
+-#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY__SHIFT 0x8
+-#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN__SHIFT 0x10
+-#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY_MASK 0x00000007L
+-#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY_MASK 0x00000700L
+-#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN_MASK 0x00010000L
+-//MASTER_COMM_DATA_REG1
+-#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0__SHIFT 0x0
+-#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1__SHIFT 0x8
+-#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2__SHIFT 0x10
+-#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3__SHIFT 0x18
+-#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0_MASK 0x000000FFL
+-#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1_MASK 0x0000FF00L
+-#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2_MASK 0x00FF0000L
+-#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3_MASK 0xFF000000L
+-//MASTER_COMM_DATA_REG2
+-#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0__SHIFT 0x0
+-#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1__SHIFT 0x8
+-#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2__SHIFT 0x10
+-#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3__SHIFT 0x18
+-#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0_MASK 0x000000FFL
+-#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1_MASK 0x0000FF00L
+-#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2_MASK 0x00FF0000L
+-#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3_MASK 0xFF000000L
+-//MASTER_COMM_DATA_REG3
+-#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0__SHIFT 0x0
+-#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1__SHIFT 0x8
+-#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2__SHIFT 0x10
+-#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3__SHIFT 0x18
+-#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0_MASK 0x000000FFL
+-#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1_MASK 0x0000FF00L
+-#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2_MASK 0x00FF0000L
+-#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3_MASK 0xFF000000L
+-//MASTER_COMM_CMD_REG
+-#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0__SHIFT 0x0
+-#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1__SHIFT 0x8
+-#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT 0x10
+-#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT 0x18
+-#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0_MASK 0x000000FFL
+-#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1_MASK 0x0000FF00L
+-#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2_MASK 0x00FF0000L
+-#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3_MASK 0xFF000000L
+-//MASTER_COMM_CNTL_REG
+-#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT 0x0
+-#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L
+-//SLAVE_COMM_DATA_REG1
+-#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0__SHIFT 0x0
+-#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1__SHIFT 0x8
+-#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2__SHIFT 0x10
+-#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3__SHIFT 0x18
+-#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0_MASK 0x000000FFL
+-#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1_MASK 0x0000FF00L
+-#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2_MASK 0x00FF0000L
+-#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3_MASK 0xFF000000L
+-//SLAVE_COMM_DATA_REG2
+-#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0__SHIFT 0x0
+-#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1__SHIFT 0x8
+-#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2__SHIFT 0x10
+-#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3__SHIFT 0x18
+-#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0_MASK 0x000000FFL
+-#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1_MASK 0x0000FF00L
+-#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2_MASK 0x00FF0000L
+-#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3_MASK 0xFF000000L
+-//SLAVE_COMM_DATA_REG3
+-#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0__SHIFT 0x0
+-#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1__SHIFT 0x8
+-#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2__SHIFT 0x10
+-#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3__SHIFT 0x18
+-#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0_MASK 0x000000FFL
+-#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1_MASK 0x0000FF00L
+-#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2_MASK 0x00FF0000L
+-#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3_MASK 0xFF000000L
+-//SLAVE_COMM_CMD_REG
+-#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0__SHIFT 0x0
+-#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1__SHIFT 0x8
+-#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2__SHIFT 0x10
+-#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3__SHIFT 0x18
+-#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0_MASK 0x000000FFL
+-#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1_MASK 0x0000FF00L
+-#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2_MASK 0x00FF0000L
+-#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3_MASK 0xFF000000L
+-//SLAVE_COMM_CNTL_REG
+-#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT__SHIFT 0x0
+-#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS__SHIFT 0x8
+-#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT_MASK 0x00000001L
+-#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS_MASK 0x00000100L
+-//BL1_PWM_AMBIENT_LIGHT_LEVEL
+-#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0
+-#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x0001FFFFL
+-//BL1_PWM_USER_LEVEL
+-#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0
+-#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x0001FFFFL
+-//BL1_PWM_TARGET_ABM_LEVEL
+-#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0
+-#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x0001FFFFL
+-//BL1_PWM_CURRENT_ABM_LEVEL
+-#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0
+-#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x0001FFFFL
+-//BL1_PWM_FINAL_DUTY_CYCLE
+-#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0
+-#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x0001FFFFL
+-//BL1_PWM_MINIMUM_DUTY_CYCLE
+-#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0
+-#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x0001FFFFL
+-//BL1_PWM_ABM_CNTL
+-#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0
+-#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1
+-#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2
+-#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3
+-#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10
+-#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x00000001L
+-#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x00000002L
+-#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x00000004L
+-#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x00000008L
+-#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xFFFF0000L
+-//BL1_PWM_BL_UPDATE_SAMPLE_RATE
+-#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0
+-#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1
+-#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8
+-#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10
+-#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
+-#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L
+-#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L
+-#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L
+-#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L
+-#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L
+-//BL1_PWM_GRP2_REG_LOCK
+-#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x0
+-#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8
+-#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10
+-#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x11
+-#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x18
+-#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f
+-#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x00000001L
+-#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x00000100L
+-#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x00010000L
+-#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0x000E0000L
+-#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L
+-#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L
+-//DMCU_INTERRUPT_TO_UC_EN_MASK_1
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV0_POWER_UP_INT_TO_UC_EN__SHIFT 0x0
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x1
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCFEV0_VBLANK_INT_TO_UC_EN__SHIFT 0x2
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV1_POWER_UP_INT_TO_UC_EN__SHIFT 0x3
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x4
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCFEV1_VBLANK_INT_TO_UC_EN__SHIFT 0x5
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC0_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0x6
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC1_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0x7
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC2_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0x8
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC3_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0x9
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC4_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0xa
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC5_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0xb
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DMCU_GENERIC_INT_TO_UC_EN__SHIFT 0xd
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV0_POWER_UP_INT_TO_UC_EN_MASK 0x00000001L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000002L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCFEV0_VBLANK_INT_TO_UC_EN_MASK 0x00000004L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV1_POWER_UP_INT_TO_UC_EN_MASK 0x00000008L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000010L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCFEV1_VBLANK_INT_TO_UC_EN_MASK 0x00000020L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC0_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000040L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC1_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000080L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC2_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000100L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC3_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000200L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC4_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000400L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC5_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000800L
+-#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DMCU_GENERIC_INT_TO_UC_EN_MASK 0x00002000L
+-//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCFEV0_VBLANK_INT_XIRQ_IRQ_SEL__SHIFT 0x2
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x3
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCFEV1_VBLANK_INT_XIRQ_IRQ_SEL__SHIFT 0x5
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x7
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x8
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x9
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0xa
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0xb
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DMCU_GENERIC_INT_XIRQ_IRQ_SEL__SHIFT 0xd
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000001L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000002L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCFEV0_VBLANK_INT_XIRQ_IRQ_SEL_MASK 0x00000004L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000008L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000010L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCFEV1_VBLANK_INT_XIRQ_IRQ_SEL_MASK 0x00000020L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000040L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000080L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000100L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000200L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000400L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000800L
+-#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DMCU_GENERIC_INT_XIRQ_IRQ_SEL_MASK 0x00002000L
+-//DMCU_INTERRUPT_STATUS_1
+-#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_UP_INT_OCCURRED__SHIFT 0x0
+-#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_UP_INT_CLEAR__SHIFT 0x0
+-#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_UP_INT_OCCURRED__SHIFT 0x1
+-#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_UP_INT_CLEAR__SHIFT 0x1
+-#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_OCCURRED__SHIFT 0x2
+-#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_CLEAR__SHIFT 0x2
+-#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_OCCURRED__SHIFT 0x3
+-#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_CLEAR__SHIFT 0x3
+-#define DMCU_INTERRUPT_STATUS_1__DCFEV0_VBLANK_INT_OCCURRED__SHIFT 0x4
+-#define DMCU_INTERRUPT_STATUS_1__DCFEV0_VBLANK_INT_CLEAR__SHIFT 0x4
+-#define DMCU_INTERRUPT_STATUS_1__DCFEV1_VBLANK_INT_OCCURRED__SHIFT 0x5
+-#define DMCU_INTERRUPT_STATUS_1__DCFEV1_VBLANK_INT_CLEAR__SHIFT 0x5
+-#define DMCU_INTERRUPT_STATUS_1__CRTC0_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x6
+-#define DMCU_INTERRUPT_STATUS_1__CRTC0_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0x6
+-#define DMCU_INTERRUPT_STATUS_1__CRTC1_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x7
+-#define DMCU_INTERRUPT_STATUS_1__CRTC1_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0x7
+-#define DMCU_INTERRUPT_STATUS_1__CRTC2_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x8
+-#define DMCU_INTERRUPT_STATUS_1__CRTC2_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0x8
+-#define DMCU_INTERRUPT_STATUS_1__CRTC3_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x9
+-#define DMCU_INTERRUPT_STATUS_1__CRTC3_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0x9
+-#define DMCU_INTERRUPT_STATUS_1__CRTC4_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0xa
+-#define DMCU_INTERRUPT_STATUS_1__CRTC4_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0xa
+-#define DMCU_INTERRUPT_STATUS_1__CRTC5_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0xb
+-#define DMCU_INTERRUPT_STATUS_1__CRTC5_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0xb
+-#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_OCCURRED__SHIFT 0xd
+-#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_CLEAR__SHIFT 0xd
+-#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_UP_INT_OCCURRED_MASK 0x00000001L
+-#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_UP_INT_CLEAR_MASK 0x00000001L
+-#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_UP_INT_OCCURRED_MASK 0x00000002L
+-#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_UP_INT_CLEAR_MASK 0x00000002L
+-#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_OCCURRED_MASK 0x00000004L
+-#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_CLEAR_MASK 0x00000004L
+-#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_OCCURRED_MASK 0x00000008L
+-#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_CLEAR_MASK 0x00000008L
+-#define DMCU_INTERRUPT_STATUS_1__DCFEV0_VBLANK_INT_OCCURRED_MASK 0x00000010L
+-#define DMCU_INTERRUPT_STATUS_1__DCFEV0_VBLANK_INT_CLEAR_MASK 0x00000010L
+-#define DMCU_INTERRUPT_STATUS_1__DCFEV1_VBLANK_INT_OCCURRED_MASK 0x00000020L
+-#define DMCU_INTERRUPT_STATUS_1__DCFEV1_VBLANK_INT_CLEAR_MASK 0x00000020L
+-#define DMCU_INTERRUPT_STATUS_1__CRTC0_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000040L
+-#define DMCU_INTERRUPT_STATUS_1__CRTC0_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000040L
+-#define DMCU_INTERRUPT_STATUS_1__CRTC1_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000080L
+-#define DMCU_INTERRUPT_STATUS_1__CRTC1_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000080L
+-#define DMCU_INTERRUPT_STATUS_1__CRTC2_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000100L
+-#define DMCU_INTERRUPT_STATUS_1__CRTC2_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000100L
+-#define DMCU_INTERRUPT_STATUS_1__CRTC3_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000200L
+-#define DMCU_INTERRUPT_STATUS_1__CRTC3_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000200L
+-#define DMCU_INTERRUPT_STATUS_1__CRTC4_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000400L
+-#define DMCU_INTERRUPT_STATUS_1__CRTC4_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000400L
+-#define DMCU_INTERRUPT_STATUS_1__CRTC5_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000800L
+-#define DMCU_INTERRUPT_STATUS_1__CRTC5_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000800L
+-#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_OCCURRED_MASK 0x00002000L
+-#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_CLEAR_MASK 0x00002000L
+-//DMCU_DPRX_INTERRUPT_STATUS1
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED__SHIFT 0x0
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR__SHIFT 0x0
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT 0x1
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT 0x1
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED__SHIFT 0x2
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR__SHIFT 0x2
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED__SHIFT 0x3
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR__SHIFT 0x3
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED__SHIFT 0x4
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR__SHIFT 0x4
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED__SHIFT 0x5
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR__SHIFT 0x5
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT 0x6
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT 0x6
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED__SHIFT 0x7
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR__SHIFT 0x7
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED__SHIFT 0x8
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR__SHIFT 0x8
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED__SHIFT 0x9
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR__SHIFT 0x9
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xa
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xa
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xb
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xb
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xc
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xc
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xd
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xd
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xe
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xe
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xf
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xf
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0x10
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0x10
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED__SHIFT 0x11
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR__SHIFT 0x11
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED__SHIFT 0x12
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR__SHIFT 0x12
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED__SHIFT 0x13
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR__SHIFT 0x13
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED__SHIFT 0x14
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR__SHIFT 0x14
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED__SHIFT 0x15
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR__SHIFT 0x15
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED__SHIFT 0x16
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR__SHIFT 0x16
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED__SHIFT 0x17
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR__SHIFT 0x17
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED__SHIFT 0x18
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR__SHIFT 0x18
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED__SHIFT 0x19
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR__SHIFT 0x19
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED__SHIFT 0x1a
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR__SHIFT 0x1a
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED__SHIFT 0x1b
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR__SHIFT 0x1b
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED__SHIFT 0x1c
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR__SHIFT 0x1c
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED_MASK 0x00000001L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR_MASK 0x00000001L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK 0x00000002L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK 0x00000002L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED_MASK 0x00000004L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR_MASK 0x00000004L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED_MASK 0x00000008L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR_MASK 0x00000008L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED_MASK 0x00000010L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR_MASK 0x00000010L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED_MASK 0x00000020L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR_MASK 0x00000020L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK 0x00000040L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK 0x00000040L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED_MASK 0x00000080L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR_MASK 0x00000080L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED_MASK 0x00000100L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR_MASK 0x00000100L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED_MASK 0x00000200L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR_MASK 0x00000200L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00000400L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00000400L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00000800L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00000800L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00001000L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00001000L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00002000L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00002000L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00004000L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00004000L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00008000L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00008000L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00010000L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00010000L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED_MASK 0x00020000L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR_MASK 0x00020000L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED_MASK 0x00040000L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR_MASK 0x00040000L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED_MASK 0x00080000L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR_MASK 0x00080000L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED_MASK 0x00100000L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR_MASK 0x00100000L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED_MASK 0x00200000L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR_MASK 0x00200000L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED_MASK 0x00400000L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR_MASK 0x00400000L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED_MASK 0x00800000L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR_MASK 0x00800000L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED_MASK 0x01000000L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR_MASK 0x01000000L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED_MASK 0x02000000L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR_MASK 0x02000000L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED_MASK 0x04000000L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR_MASK 0x04000000L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED_MASK 0x08000000L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR_MASK 0x08000000L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED_MASK 0x10000000L
+-#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR_MASK 0x10000000L
+-//DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT 0x0
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT 0x1
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN__SHIFT 0x2
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN__SHIFT 0x3
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT 0x4
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT 0x5
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT 0x6
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN__SHIFT 0x7
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN__SHIFT 0x8
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT 0x9
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xa
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xb
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xc
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xd
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xe
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xf
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0x10
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN__SHIFT 0x11
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN__SHIFT 0x12
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN__SHIFT 0x13
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN__SHIFT 0x14
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN__SHIFT 0x15
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN__SHIFT 0x16
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN__SHIFT 0x17
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN__SHIFT 0x18
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN__SHIFT 0x19
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1a
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1b
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1c
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN_MASK 0x00000001L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK 0x00000002L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN_MASK 0x00000004L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN_MASK 0x00000008L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN_MASK 0x00000010L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN_MASK 0x00000020L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK 0x00000040L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN_MASK 0x00000080L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN_MASK 0x00000100L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN_MASK 0x00000200L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00000400L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00000800L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00001000L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00002000L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00004000L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00008000L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00010000L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN_MASK 0x00020000L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN_MASK 0x00040000L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN_MASK 0x00080000L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN_MASK 0x00100000L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN_MASK 0x00200000L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN_MASK 0x00400000L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN_MASK 0x00800000L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN_MASK 0x01000000L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN_MASK 0x02000000L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN_MASK 0x04000000L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN_MASK 0x08000000L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN_MASK 0x10000000L
+-//DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT 0x2
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT 0x3
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x5
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT 0x7
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT 0x8
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x9
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xa
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xb
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xc
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xd
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xe
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xf
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0x10
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL__SHIFT 0x11
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL__SHIFT 0x12
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL__SHIFT 0x13
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL__SHIFT 0x14
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL__SHIFT 0x15
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL__SHIFT 0x16
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL__SHIFT 0x17
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL__SHIFT 0x18
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x19
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1b
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1c
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x00000001L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK 0x00000002L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK 0x00000004L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK 0x00000008L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x00000010L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x00000020L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK 0x00000040L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK 0x00000080L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK 0x00000100L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x00000200L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00000400L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00000800L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00001000L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00002000L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00004000L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00008000L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00010000L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL_MASK 0x00020000L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL_MASK 0x00040000L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL_MASK 0x00080000L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL_MASK 0x00100000L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL_MASK 0x00200000L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL_MASK 0x00400000L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL_MASK 0x00800000L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL_MASK 0x01000000L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x02000000L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x04000000L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x08000000L
+-#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x10000000L
+-//DC_ABM1_CNTL
+-#define DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0
+-#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT 0x8
+-#define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE__SHIFT 0x1f
+-#define DC_ABM1_CNTL__ABM1_EN_MASK 0x00000001L
+-#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT_MASK 0x00000700L
+-#define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE_MASK 0x80000000L
+-//DC_ABM1_IPCSC_COEFF_SEL
+-#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0
+-#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8
+-#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10
+-#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
+-#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0x0000000FL
+-#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0x00000F00L
+-#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0x000F0000L
+-#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L
+-//DC_ABM1_ACE_OFFSET_SLOPE_0
+-#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x0
+-#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10
+-#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x1f
+-#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x00007FFFL
+-#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x07FF0000L
+-#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000L
+-//DC_ABM1_ACE_OFFSET_SLOPE_1
+-#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x0
+-#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10
+-#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x1f
+-#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x00007FFFL
+-#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x07FF0000L
+-#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000L
+-//DC_ABM1_ACE_OFFSET_SLOPE_2
+-#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x0
+-#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10
+-#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x1f
+-#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x00007FFFL
+-#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x07FF0000L
+-#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000L
+-//DC_ABM1_ACE_OFFSET_SLOPE_3
+-#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x0
+-#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10
+-#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x1f
+-#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x00007FFFL
+-#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x07FF0000L
+-#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000L
+-//DC_ABM1_ACE_OFFSET_SLOPE_4
+-#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x0
+-#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10
+-#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x1f
+-#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x00007FFFL
+-#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x07FF0000L
+-#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000L
+-//DC_ABM1_ACE_THRES_12
+-#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x0
+-#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x10
+-#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x1f
+-#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x000003FFL
+-#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x03FF0000L
+-#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000L
+-//DC_ABM1_ACE_THRES_34
+-#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x0
+-#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x10
+-#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c
+-#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d
+-#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e
+-#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x1f
+-#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x000003FFL
+-#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x03FF0000L
+-#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000L
+-#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000L
+-#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000L
+-#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000L
+-//DC_ABM1_ACE_CNTL_MISC
+-#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0
+-#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8
+-#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x00000001L
+-#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x00000100L
+-//DMCU_PERFMON_INTERRUPT_STATUS5
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x10
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x10
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x11
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x11
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x00000001L
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER0_INT_CLEAR_MASK 0x00000001L
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x00000002L
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER1_INT_CLEAR_MASK 0x00000002L
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x00000004L
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER2_INT_CLEAR_MASK 0x00000004L
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x00000008L
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER3_INT_CLEAR_MASK 0x00000008L
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x00000010L
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER4_INT_CLEAR_MASK 0x00000010L
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x00000020L
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER5_INT_CLEAR_MASK 0x00000020L
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x00000040L
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER6_INT_CLEAR_MASK 0x00000040L
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x00000080L
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER7_INT_CLEAR_MASK 0x00000080L
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x00000100L
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER0_INT_CLEAR_MASK 0x00000100L
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x00000200L
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER1_INT_CLEAR_MASK 0x00000200L
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x00000400L
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER2_INT_CLEAR_MASK 0x00000400L
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x00000800L
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER3_INT_CLEAR_MASK 0x00000800L
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x00001000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER4_INT_CLEAR_MASK 0x00001000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x00002000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER5_INT_CLEAR_MASK 0x00002000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x00004000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER6_INT_CLEAR_MASK 0x00004000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x00008000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER7_INT_CLEAR_MASK 0x00008000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x00010000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x00010000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x00020000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x00020000L
+-//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x8
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x9
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0xa
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xb
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xc
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xd
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xe
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xf
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x10
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x11
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x00000001L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x00000002L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x00000004L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x00000008L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x00000010L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x00000020L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x00000040L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x00000080L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x00000100L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x00000200L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x00000400L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x00000800L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x00001000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x00002000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x00004000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x00008000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x00010000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x00020000L
+-//DMCU_PERFMON_INTERRUPT_STATUS1
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x00000001L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_CLEAR_MASK 0x00000001L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x00000002L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR_MASK 0x00000002L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x00000004L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR_MASK 0x00000004L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x00000008L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_CLEAR_MASK 0x00000008L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x00000010L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_CLEAR_MASK 0x00000010L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x00000020L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_CLEAR_MASK 0x00000020L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x00000040L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_CLEAR_MASK 0x00000040L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x00000080L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_CLEAR_MASK 0x00000080L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x00000100L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_CLEAR_MASK 0x00000100L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x00000200L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_CLEAR_MASK 0x00000200L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x00000400L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_CLEAR_MASK 0x00000400L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x00000800L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_CLEAR_MASK 0x00000800L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x00001000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_CLEAR_MASK 0x00001000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x00002000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_CLEAR_MASK 0x00002000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x00004000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_CLEAR_MASK 0x00004000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x00008000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_CLEAR_MASK 0x00008000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x00010000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_CLEAR_MASK 0x00010000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x00020000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_CLEAR_MASK 0x00020000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x00040000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_CLEAR_MASK 0x00040000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x00080000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_CLEAR_MASK 0x00080000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x00100000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_CLEAR_MASK 0x00100000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x00200000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_CLEAR_MASK 0x00200000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x00400000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_CLEAR_MASK 0x00400000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x00800000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_CLEAR_MASK 0x00800000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x01000000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x01000000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x02000000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x02000000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x04000000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x04000000L
+-//DMCU_PERFMON_INTERRUPT_STATUS2
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x00000001L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_CLEAR_MASK 0x00000001L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x00000002L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR_MASK 0x00000002L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x00000004L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR_MASK 0x00000004L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x00000008L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_CLEAR_MASK 0x00000008L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x00000010L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_CLEAR_MASK 0x00000010L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x00000020L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_CLEAR_MASK 0x00000020L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x00000040L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_CLEAR_MASK 0x00000040L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x00000080L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_CLEAR_MASK 0x00000080L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x00000100L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_CLEAR_MASK 0x00000100L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x00000200L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_CLEAR_MASK 0x00000200L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x00000400L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_CLEAR_MASK 0x00000400L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x00000800L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_CLEAR_MASK 0x00000800L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x00001000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_CLEAR_MASK 0x00001000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x00002000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_CLEAR_MASK 0x00002000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x00004000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_CLEAR_MASK 0x00004000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x00008000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_CLEAR_MASK 0x00008000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x00010000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_CLEAR_MASK 0x00010000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x00020000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_CLEAR_MASK 0x00020000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x00040000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_CLEAR_MASK 0x00040000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x00080000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_CLEAR_MASK 0x00080000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x00100000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_CLEAR_MASK 0x00100000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x00200000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_CLEAR_MASK 0x00200000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x00400000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_CLEAR_MASK 0x00400000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x00800000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_CLEAR_MASK 0x00800000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x01000000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x01000000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x02000000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x02000000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x04000000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x04000000L
+-//DMCU_PERFMON_INTERRUPT_STATUS3
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x00000001L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_CLEAR_MASK 0x00000001L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x00000002L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR_MASK 0x00000002L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x00000004L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR_MASK 0x00000004L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x00000008L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_CLEAR_MASK 0x00000008L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x00000010L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_CLEAR_MASK 0x00000010L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x00000020L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_CLEAR_MASK 0x00000020L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x00000040L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_CLEAR_MASK 0x00000040L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x00000080L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_CLEAR_MASK 0x00000080L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x00000100L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_CLEAR_MASK 0x00000100L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x00000200L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_CLEAR_MASK 0x00000200L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x00000400L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_CLEAR_MASK 0x00000400L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x00000800L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_CLEAR_MASK 0x00000800L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x00001000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_CLEAR_MASK 0x00001000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x00002000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_CLEAR_MASK 0x00002000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x00004000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_CLEAR_MASK 0x00004000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x00008000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_CLEAR_MASK 0x00008000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x00010000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_CLEAR_MASK 0x00010000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x00020000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_CLEAR_MASK 0x00020000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x00040000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_CLEAR_MASK 0x00040000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x00080000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_CLEAR_MASK 0x00080000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x00100000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_CLEAR_MASK 0x00100000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x00200000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_CLEAR_MASK 0x00200000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x00400000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_CLEAR_MASK 0x00400000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x00800000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_CLEAR_MASK 0x00800000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x01000000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x01000000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x02000000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x02000000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x04000000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x04000000L
+-//DMCU_PERFMON_INTERRUPT_STATUS4
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER0_INT_OCCURRED__SHIFT 0x10
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER0_INT_CLEAR__SHIFT 0x10
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER1_INT_OCCURRED__SHIFT 0x11
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER1_INT_CLEAR__SHIFT 0x11
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER2_INT_OCCURRED__SHIFT 0x12
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER2_INT_CLEAR__SHIFT 0x12
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER3_INT_OCCURRED__SHIFT 0x13
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER3_INT_CLEAR__SHIFT 0x13
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER4_INT_OCCURRED__SHIFT 0x14
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER4_INT_CLEAR__SHIFT 0x14
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER5_INT_OCCURRED__SHIFT 0x15
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER5_INT_CLEAR__SHIFT 0x15
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER6_INT_OCCURRED__SHIFT 0x16
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER6_INT_CLEAR__SHIFT 0x16
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER7_INT_OCCURRED__SHIFT 0x17
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER7_INT_CLEAR__SHIFT 0x17
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x00000001L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_CLEAR_MASK 0x00000001L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x00000002L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_CLEAR_MASK 0x00000002L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x00000004L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_CLEAR_MASK 0x00000004L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x00000008L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_CLEAR_MASK 0x00000008L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x00000010L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_CLEAR_MASK 0x00000010L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x00000020L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_CLEAR_MASK 0x00000020L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x00000040L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_CLEAR_MASK 0x00000040L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x00000080L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_CLEAR_MASK 0x00000080L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x00000100L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_CLEAR_MASK 0x00000100L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x00000200L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_CLEAR_MASK 0x00000200L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x00000400L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_CLEAR_MASK 0x00000400L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x00000800L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_CLEAR_MASK 0x00000800L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x00001000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_CLEAR_MASK 0x00001000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x00002000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_CLEAR_MASK 0x00002000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x00004000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_CLEAR_MASK 0x00004000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x00008000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_CLEAR_MASK 0x00008000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER0_INT_OCCURRED_MASK 0x00010000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER0_INT_CLEAR_MASK 0x00010000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER1_INT_OCCURRED_MASK 0x00020000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER1_INT_CLEAR_MASK 0x00020000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER2_INT_OCCURRED_MASK 0x00040000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER2_INT_CLEAR_MASK 0x00040000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER3_INT_OCCURRED_MASK 0x00080000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER3_INT_CLEAR_MASK 0x00080000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER4_INT_OCCURRED_MASK 0x00100000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER4_INT_CLEAR_MASK 0x00100000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER5_INT_OCCURRED_MASK 0x00200000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER5_INT_CLEAR_MASK 0x00200000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER6_INT_OCCURRED_MASK 0x00400000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER6_INT_CLEAR_MASK 0x00400000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER7_INT_OCCURRED_MASK 0x00800000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER7_INT_CLEAR_MASK 0x00800000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x01000000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x01000000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x02000000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x02000000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_OFF_INT_OCCURRED_MASK 0x04000000L
+-#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_OFF_INT_CLEAR_MASK 0x04000000L
+-//DC_ABM1_HGLS_REG_READ_PROGRESS
+-#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0
+-#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1
+-#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2
+-#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8
+-#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9
+-#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa
+-#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10
+-#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18
+-#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f
+-#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x00000001L
+-#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x00000002L
+-#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x00000004L
+-#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x00000100L
+-#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x00000200L
+-#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x00000400L
+-#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x00010000L
+-#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x01000000L
+-#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000L
+-//DC_ABM1_HG_MISC_CTRL
+-#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0
+-#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8
+-#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0xc
+-#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10
+-#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14
+-#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x17
+-#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x18
+-#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x1c
+-#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x1d
+-#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x1e
+-#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
+-#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x00000003L
+-#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x00000100L
+-#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x00001000L
+-#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x00030000L
+-#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x00100000L
+-#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x00800000L
+-#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x07000000L
+-#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000L
+-#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000L
+-#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000L
+-#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L
+-//DC_ABM1_LS_SUM_OF_LUMA
+-#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0
+-#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xFFFFFFFFL
+-//DC_ABM1_LS_MIN_MAX_LUMA
+-#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0
+-#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10
+-#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x000003FFL
+-#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x03FF0000L
+-//DC_ABM1_LS_FILTERED_MIN_MAX_LUMA
+-#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0
+-#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10
+-#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x000003FFL
+-#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x03FF0000L
+-//DC_ABM1_LS_PIXEL_COUNT
+-#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0
+-#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0x00FFFFFFL
+-//DC_ABM1_LS_OVR_SCAN_BIN
+-#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN__SHIFT 0x0
+-#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN_MASK 0x00FFFFFFL
+-//DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
+-#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0
+-#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10
+-#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
+-#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x000003FFL
+-#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x03FF0000L
+-#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000L
+-//DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT
+-#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0
+-#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL
+-//DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT
+-#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0
+-#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL
+-//DC_ABM1_HG_SAMPLE_RATE
+-#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0
+-#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1
+-#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8
+-#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10
+-#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
+-#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L
+-#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L
+-#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L
+-#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L
+-#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L
+-//DC_ABM1_LS_SAMPLE_RATE
+-#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0
+-#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1
+-#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8
+-#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10
+-#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
+-#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L
+-#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L
+-#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L
+-#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L
+-#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L
+-//DC_ABM1_HG_BIN_1_32_SHIFT_FLAG
+-#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0
+-#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xFFFFFFFFL
+-//DC_ABM1_HG_BIN_1_8_SHIFT_INDEX
+-#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0
+-#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xFFFFFFFFL
+-//DC_ABM1_HG_BIN_9_16_SHIFT_INDEX
+-#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0
+-#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xFFFFFFFFL
+-//DC_ABM1_HG_BIN_17_24_SHIFT_INDEX
+-#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0
+-#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xFFFFFFFFL
+-//DC_ABM1_HG_BIN_25_32_SHIFT_INDEX
+-#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0
+-#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xFFFFFFFFL
+-//DC_ABM1_HG_RESULT_1
+-#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x0
+-#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xFFFFFFFFL
+-//DC_ABM1_HG_RESULT_2
+-#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x0
+-#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xFFFFFFFFL
+-//DC_ABM1_HG_RESULT_3
+-#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x0
+-#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xFFFFFFFFL
+-//DC_ABM1_HG_RESULT_4
+-#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x0
+-#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xFFFFFFFFL
+-//DC_ABM1_HG_RESULT_5
+-#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x0
+-#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xFFFFFFFFL
+-//DC_ABM1_HG_RESULT_6
+-#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x0
+-#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xFFFFFFFFL
+-//DC_ABM1_HG_RESULT_7
+-#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x0
+-#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xFFFFFFFFL
+-//DC_ABM1_HG_RESULT_8
+-#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x0
+-#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xFFFFFFFFL
+-//DC_ABM1_HG_RESULT_9
+-#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x0
+-#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xFFFFFFFFL
+-//DC_ABM1_HG_RESULT_10
+-#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x0
+-#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xFFFFFFFFL
+-//DC_ABM1_HG_RESULT_11
+-#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x0
+-#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xFFFFFFFFL
+-//DC_ABM1_HG_RESULT_12
+-#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x0
+-#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xFFFFFFFFL
+-//DC_ABM1_HG_RESULT_13
+-#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x0
+-#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xFFFFFFFFL
+-//DC_ABM1_HG_RESULT_14
+-#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x0
+-#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xFFFFFFFFL
+-//DC_ABM1_HG_RESULT_15
+-#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x0
+-#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xFFFFFFFFL
+-//DC_ABM1_HG_RESULT_16
+-#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x0
+-#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xFFFFFFFFL
+-//DC_ABM1_HG_RESULT_17
+-#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x0
+-#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xFFFFFFFFL
+-//DC_ABM1_HG_RESULT_18
+-#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x0
+-#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xFFFFFFFFL
+-//DC_ABM1_HG_RESULT_19
+-#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x0
+-#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xFFFFFFFFL
+-//DC_ABM1_HG_RESULT_20
+-#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x0
+-#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xFFFFFFFFL
+-//DC_ABM1_HG_RESULT_21
+-#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x0
+-#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xFFFFFFFFL
+-//DC_ABM1_HG_RESULT_22
+-#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x0
+-#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xFFFFFFFFL
+-//DC_ABM1_HG_RESULT_23
+-#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x0
+-#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xFFFFFFFFL
+-//DC_ABM1_HG_RESULT_24
+-#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x0
+-#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xFFFFFFFFL
+-//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x8
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x9
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0xa
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xb
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xc
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xd
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xe
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xf
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x10
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x11
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00000001L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00000002L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00000004L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00000008L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00000010L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00000020L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00000040L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00000080L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x00000100L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00000200L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00000400L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00000800L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00001000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00002000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00004000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00008000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00010000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x00020000L
+-//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x00000001L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x00000002L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x00000004L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x00000008L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x00000010L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x00000020L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x00000040L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x00000080L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x00000100L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x00000200L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x00000400L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x00000800L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x00001000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x00002000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x00004000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x00008000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x00010000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x00020000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x00040000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x00080000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x00100000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x00200000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x00400000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x00800000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x01000000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x02000000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x04000000L
+-//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x00000001L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x00000002L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x00000004L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x00000008L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x00000010L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x00000020L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x00000040L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x00000080L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x00000100L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x00000200L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x00000400L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x00000800L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x00001000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x00002000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x00004000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x00008000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x00010000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x00020000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x00040000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x00080000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x00100000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x00200000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x00400000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x00800000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x01000000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x02000000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x04000000L
+-//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x00000001L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x00000002L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x00000004L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x00000008L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x00000010L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x00000020L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x00000040L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x00000080L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x00000100L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x00000200L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x00000400L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x00000800L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x00001000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x00002000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x00004000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x00008000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x00010000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x00020000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x00040000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x00080000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x00100000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x00200000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x00400000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x00800000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x01000000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x02000000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x04000000L
+-//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER0_INT_TO_UC_EN__SHIFT 0x10
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER1_INT_TO_UC_EN__SHIFT 0x11
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER2_INT_TO_UC_EN__SHIFT 0x12
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER3_INT_TO_UC_EN__SHIFT 0x13
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER4_INT_TO_UC_EN__SHIFT 0x14
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER5_INT_TO_UC_EN__SHIFT 0x15
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER6_INT_TO_UC_EN__SHIFT 0x16
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER7_INT_TO_UC_EN__SHIFT 0x17
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x00000001L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x00000002L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x00000004L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x00000008L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x00000010L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x00000020L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x00000040L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x00000080L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x00000100L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x00000200L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x00000400L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x00000800L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x00001000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x00002000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x00004000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x00008000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER0_INT_TO_UC_EN_MASK 0x00010000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER1_INT_TO_UC_EN_MASK 0x00020000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER2_INT_TO_UC_EN_MASK 0x00040000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER3_INT_TO_UC_EN_MASK 0x00080000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER4_INT_TO_UC_EN_MASK 0x00100000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER5_INT_TO_UC_EN_MASK 0x00200000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER6_INT_TO_UC_EN_MASK 0x00400000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER7_INT_TO_UC_EN_MASK 0x00800000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x01000000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x02000000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER_OFF_INT_TO_UC_EN_MASK 0x04000000L
+-//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00000001L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00000002L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00000004L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00000008L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00000010L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00000020L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00000040L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00000080L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00000100L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00000200L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00000400L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00000800L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00001000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00002000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00004000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00008000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00010000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00020000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00040000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00080000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00100000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00200000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00400000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00800000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x01000000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x02000000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x04000000L
+-//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00000001L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00000002L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00000004L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00000008L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00000010L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00000020L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00000040L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00000080L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00000100L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00000200L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00000400L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00000800L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00001000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00002000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00004000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00008000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00010000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00020000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00040000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00080000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00100000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00200000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00400000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00800000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x01000000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x02000000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x04000000L
+-//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00000001L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00000002L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00000004L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00000008L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00000010L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00000020L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00000040L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00000080L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00000100L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00000200L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00000400L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00000800L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00001000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00002000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00004000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00008000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00010000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00020000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00040000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00080000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00100000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00200000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00400000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00800000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x01000000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x02000000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x04000000L
+-//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00000001L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00000002L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00000004L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00000008L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00000010L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00000020L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00000040L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00000080L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00000100L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00000200L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00000400L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00000800L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00001000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00002000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00004000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00008000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00010000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00020000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00040000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00080000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00100000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00200000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00400000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00800000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x01000000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x02000000L
+-#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x04000000L
+-//DC_ABM1_OVERSCAN_PIXEL_VALUE
+-#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE__SHIFT 0x0
+-#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE__SHIFT 0xa
+-#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE__SHIFT 0x14
+-#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE_MASK 0x000003FFL
+-#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE_MASK 0x000FFC00L
+-#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE_MASK 0x3FF00000L
+-//DC_ABM1_BL_MASTER_LOCK
+-#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f
+-#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L
+-//AZALIA_CONTROLLER_CLOCK_GATING
+-#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT 0x0
+-#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT 0x4
+-#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK 0x00000001L
+-#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK 0x00000010L
+-//AZALIA_AUDIO_DTO
+-#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT 0x0
+-#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT 0x10
+-#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK 0x0000FFFFL
+-#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK 0xFFFF0000L
+-//AZALIA_AUDIO_DTO_CONTROL
+-#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT 0x8
+-#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK 0x00000300L
+-//AZALIA_SOCCLK_CONTROL
+-#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN__SHIFT 0x1
+-#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN_MASK 0x00000002L
+-//AZALIA_UNDERFLOW_FILLER_SAMPLE
+-#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT 0x0
+-#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK 0xFFFFFFFFL
+-//AZALIA_DATA_DMA_CONTROL
+-#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT 0x0
+-#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP__SHIFT 0x2
+-#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT 0x4
+-#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS__SHIFT 0x6
+-#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT 0x10
+-#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT 0x11
+-#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK 0x00000003L
+-#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP_MASK 0x0000000CL
+-#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK 0x00000030L
+-#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS_MASK 0x000000C0L
+-#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK 0x00010000L
+-#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK 0x00020000L
+-//AZALIA_BDL_DMA_CONTROL
+-#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT 0x0
+-#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP__SHIFT 0x2
+-#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT 0x4
+-#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS__SHIFT 0x6
+-#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK 0x00000003L
+-#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP_MASK 0x0000000CL
+-#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK 0x00000030L
+-#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS_MASK 0x000000C0L
+-//AZALIA_RIRB_AND_DP_CONTROL
+-#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT 0x0
+-#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT 0x4
+-#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER__SHIFT 0x5
+-#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK 0x00000001L
+-#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK 0x00000010L
+-#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER_MASK 0x000001E0L
+-//AZALIA_CORB_DMA_CONTROL
+-#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT 0x0
+-#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT 0x4
+-#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK 0x00000001L
+-#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK 0x00000010L
+-//AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER
+-#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT 0x0
+-#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK 0xFFFFFFFFL
+-//AZALIA_CYCLIC_BUFFER_SYNC
+-#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT 0x0
+-#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK 0x00000001L
+-//AZALIA_GLOBAL_CAPABILITIES
+-#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1
+-#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x00000006L
+-//AZALIA_OUTPUT_PAYLOAD_CAPABILITY
+-#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0
+-#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x10
+-#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0x0000FFFFL
+-#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xFFFF0000L
+-//AZALIA_OUTPUT_STREAM_ARBITER_CONTROL
+-#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT 0x0
+-#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT 0x8
+-#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL__SHIFT 0x10
+-#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK 0x000000FFL
+-#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK 0x00000100L
+-#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL_MASK 0x00FF0000L
+-//AZALIA_INPUT_PAYLOAD_CAPABILITY
+-#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0
+-#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT 0x10
+-#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0x0000FFFFL
+-#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY_MASK 0xFFFF0000L
+-//AZALIA_INPUT_CRC0_CONTROL0
+-#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN__SHIFT 0x0
+-#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4
+-#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8
+-#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN_MASK 0x00000001L
+-#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x00000010L
+-#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x00000700L
+-//AZALIA_INPUT_CRC0_CONTROL1
+-#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0
+-#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL
+-//AZALIA_INPUT_CRC0_CONTROL2
+-#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0
+-#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0x0000FFFFL
+-//AZALIA_INPUT_CRC0_CONTROL3
+-#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0
+-#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4
+-#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8
+-#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x00000001L
+-#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L
+-#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L
+-//AZALIA_INPUT_CRC0_RESULT
+-#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT__SHIFT 0x0
+-#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT_MASK 0xFFFFFFFFL
+-//AZALIA_INPUT_CRC1_CONTROL0
+-#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN__SHIFT 0x0
+-#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4
+-#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8
+-#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN_MASK 0x00000001L
+-#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x00000010L
+-#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x00000700L
+-//AZALIA_INPUT_CRC1_CONTROL1
+-#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0
+-#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL
+-//AZALIA_INPUT_CRC1_CONTROL2
+-#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0
+-#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0x0000FFFFL
+-//AZALIA_INPUT_CRC1_CONTROL3
+-#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0
+-#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4
+-#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8
+-#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x00000001L
+-#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L
+-#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L
+-//AZALIA_INPUT_CRC1_RESULT
+-#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT__SHIFT 0x0
+-#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT_MASK 0xFFFFFFFFL
+-//AZALIA_CRC0_CONTROL0
+-#define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT 0x0
+-#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4
+-#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8
+-#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc
+-#define AZALIA_CRC0_CONTROL0__CRC_EN_MASK 0x00000001L
+-#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK 0x00000010L
+-#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK 0x00000700L
+-#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK 0x00001000L
+-//AZALIA_CRC0_CONTROL1
+-#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0
+-#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL
+-//AZALIA_CRC0_CONTROL2
+-#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0
+-#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK 0x0000FFFFL
+-//AZALIA_CRC0_CONTROL3
+-#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT 0x0
+-#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4
+-#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8
+-#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK 0x00000001L
+-#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L
+-#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L
+-//AZALIA_CRC0_RESULT
+-#define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT 0x0
+-#define AZALIA_CRC0_RESULT__CRC_RESULT_MASK 0xFFFFFFFFL
+-//AZALIA_CRC1_CONTROL0
+-#define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT 0x0
+-#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4
+-#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8
+-#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc
+-#define AZALIA_CRC1_CONTROL0__CRC_EN_MASK 0x00000001L
+-#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK 0x00000010L
+-#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK 0x00000700L
+-#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK 0x00001000L
+-//AZALIA_CRC1_CONTROL1
+-#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0
+-#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL
+-//AZALIA_CRC1_CONTROL2
+-#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0
+-#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK 0x0000FFFFL
+-//AZALIA_CRC1_CONTROL3
+-#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT 0x0
+-#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4
+-#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8
+-#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK 0x00000001L
+-#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L
+-#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L
+-//AZALIA_CRC1_RESULT
+-#define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT 0x0
+-#define AZALIA_CRC1_RESULT__CRC_RESULT_MASK 0xFFFFFFFFL
+-//AZALIA_MEM_PWR_CTRL
+-#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE__SHIFT 0x0
+-#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS__SHIFT 0x2
+-#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE__SHIFT 0x3
+-#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS__SHIFT 0x5
+-#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE__SHIFT 0x6
+-#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS__SHIFT 0x8
+-#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE__SHIFT 0x9
+-#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS__SHIFT 0xb
+-#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE__SHIFT 0xc
+-#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS__SHIFT 0xe
+-#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE__SHIFT 0xf
+-#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS__SHIFT 0x11
+-#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE__SHIFT 0x12
+-#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS__SHIFT 0x14
+-#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL__SHIFT 0x1c
+-#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE_MASK 0x00000003L
+-#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS_MASK 0x00000004L
+-#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE_MASK 0x00000018L
+-#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS_MASK 0x00000020L
+-#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE_MASK 0x000000C0L
+-#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS_MASK 0x00000100L
+-#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE_MASK 0x00000600L
+-#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS_MASK 0x00000800L
+-#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE_MASK 0x00003000L
+-#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS_MASK 0x00004000L
+-#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE_MASK 0x00018000L
+-#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS_MASK 0x00020000L
+-#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE_MASK 0x000C0000L
+-#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS_MASK 0x00100000L
+-#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL_MASK 0x30000000L
+-//AZALIA_MEM_PWR_STATUS
+-#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE__SHIFT 0x0
+-#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE__SHIFT 0x2
+-#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE__SHIFT 0x4
+-#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE__SHIFT 0x6
+-#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE__SHIFT 0x8
+-#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE__SHIFT 0xa
+-#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE__SHIFT 0xc
+-#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE_MASK 0x00000003L
+-#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE_MASK 0x0000000CL
+-#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE_MASK 0x00000030L
+-#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE_MASK 0x000000C0L
+-#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE_MASK 0x00000300L
+-#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE_MASK 0x00000C00L
+-#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE_MASK 0x00003000L
+-//AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID
+-#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0
+-#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xFFFFFFFFL
+-//AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID
+-#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0
+-#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xFFFFFFFFL
+-//AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL
+-#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT 0x0
+-#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT 0x4
+-#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK 0x00000007L
+-#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK 0x00000070L
+-//AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL
+-#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT 0x0
+-#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK 0x0000003FL
+-//AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE
+-#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0
+-#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xFFFFFFFFL
+-//AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
+-#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+-#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+-#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+-#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+-//AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
+-#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0
+-#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xFFFFFFFFL
+-//AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES
+-#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0
+-#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e
+-#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f
+-#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3FFFFFFFL
+-#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L
+-#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L
+-//AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE
+-#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0
+-#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4
+-#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9
+-#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa
+-#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000FL
+-#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000F0L
+-#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L
+-#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L
+-//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET
+-#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0
+-#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L
+-//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID
+-#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0
+-#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8
+-#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10
+-#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18
+-#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000FFL
+-#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000FF00L
+-#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00FF0000L
+-#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xFF000000L
+-//AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION
+-#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0
+-#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x000000FFL
+-//CC_RCU_DC_AUDIO_PORT_CONNECTIVITY
+-#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT 0x0
+-#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4
+-#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK 0x00000007L
+-#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L
+-//CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY
+-#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY__SHIFT 0x0
+-#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4
+-#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_MASK 0x00000007L
+-#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L
+-//AZALIA_F0_GTC_GROUP_OFFSET0
+-#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0__SHIFT 0x0
+-#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0_MASK 0xFFFFFFFFL
+-//AZALIA_F0_GTC_GROUP_OFFSET1
+-#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1__SHIFT 0x0
+-#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1_MASK 0xFFFFFFFFL
+-//AZALIA_F0_GTC_GROUP_OFFSET2
+-#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2__SHIFT 0x0
+-#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2_MASK 0xFFFFFFFFL
+-//AZALIA_F0_GTC_GROUP_OFFSET3
+-#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3__SHIFT 0x0
+-#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3_MASK 0xFFFFFFFFL
+-//AZALIA_F0_GTC_GROUP_OFFSET4
+-#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4__SHIFT 0x0
+-#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4_MASK 0xFFFFFFFFL
+-//AZALIA_F0_GTC_GROUP_OFFSET5
+-#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5__SHIFT 0x0
+-#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5_MASK 0xFFFFFFFFL
+-//AZALIA_F0_GTC_GROUP_OFFSET6
+-#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6__SHIFT 0x0
+-#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6_MASK 0xFFFFFFFFL
+-//REG_DC_AUDIO_PORT_CONNECTIVITY
+-#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY__SHIFT 0x0
+-#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4
+-#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_MASK 0x00000007L
+-#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L
+-//REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY
+-#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY__SHIFT 0x0
+-#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4
+-#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_MASK 0x00000007L
+-#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L
+-//DAC_ENABLE
+-#define DAC_ENABLE__DAC_ENABLE__SHIFT 0x0
+-#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE__SHIFT 0x1
+-#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW__SHIFT 0x2
+-#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR__SHIFT 0x4
+-#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK__SHIFT 0x5
+-#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM__SHIFT 0x8
+-#define DAC_ENABLE__DAC_ENABLE_MASK 0x00000001L
+-#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE_MASK 0x00000002L
+-#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW_MASK 0x0000000CL
+-#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_MASK 0x00000010L
+-#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK_MASK 0x00000020L
+-#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM_MASK 0x00000100L
+-//DAC_SOURCE_SELECT
+-#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT__SHIFT 0x0
+-#define DAC_SOURCE_SELECT__DAC_TV_SELECT__SHIFT 0x3
+-#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT_MASK 0x00000007L
+-#define DAC_SOURCE_SELECT__DAC_TV_SELECT_MASK 0x00000008L
+-//DAC_CRC_EN
+-#define DAC_CRC_EN__DAC_CRC_EN__SHIFT 0x0
+-#define DAC_CRC_EN__DAC_CRC_CONT_EN__SHIFT 0x10
+-#define DAC_CRC_EN__DAC_CRC_EN_MASK 0x00000001L
+-#define DAC_CRC_EN__DAC_CRC_CONT_EN_MASK 0x00010000L
+-//DAC_CRC_CONTROL
+-#define DAC_CRC_CONTROL__DAC_CRC_FIELD__SHIFT 0x0
+-#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKB__SHIFT 0x8
+-#define DAC_CRC_CONTROL__DAC_CRC_FIELD_MASK 0x00000001L
+-#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKB_MASK 0x00000100L
+-//DAC_CRC_SIG_RGB_MASK
+-#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK__SHIFT 0x0
+-#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK__SHIFT 0xa
+-#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK__SHIFT 0x14
+-#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK_MASK 0x000003FFL
+-#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK_MASK 0x000FFC00L
+-#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK_MASK 0x3FF00000L
+-//DAC_CRC_SIG_CONTROL_MASK
+-#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK__SHIFT 0x0
+-#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK_MASK 0x0000003FL
+-//DAC_CRC_SIG_RGB
+-#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE__SHIFT 0x0
+-#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN__SHIFT 0xa
+-#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED__SHIFT 0x14
+-#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE_MASK 0x000003FFL
+-#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN_MASK 0x000FFC00L
+-#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED_MASK 0x3FF00000L
+-//DAC_CRC_SIG_CONTROL
+-#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL__SHIFT 0x0
+-#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL_MASK 0x0000003FL
+-//DAC_SYNC_TRISTATE_CONTROL
+-#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE__SHIFT 0x0
+-#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE__SHIFT 0x8
+-#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE__SHIFT 0x10
+-#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE_MASK 0x00000001L
+-#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE_MASK 0x00000100L
+-#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE_MASK 0x00010000L
+-//DAC_STEREOSYNC_SELECT
+-#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT__SHIFT 0x0
+-#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT_MASK 0x00000007L
+-//DAC_AUTODETECT_CONTROL
+-#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE__SHIFT 0x0
+-#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER__SHIFT 0x8
+-#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK__SHIFT 0x10
+-#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE_MASK 0x00000003L
+-#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER_MASK 0x0000FF00L
+-#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK_MASK 0x00070000L
+-//DAC_AUTODETECT_CONTROL2
+-#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER__SHIFT 0x0
+-#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE__SHIFT 0x8
+-#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER_MASK 0x000000FFL
+-#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE_MASK 0x00000100L
+-//DAC_AUTODETECT_CONTROL3
+-#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY__SHIFT 0x0
+-#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY__SHIFT 0x8
+-#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY_MASK 0x000000FFL
+-#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY_MASK 0x0000FF00L
+-//DAC_AUTODETECT_STATUS
+-#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS__SHIFT 0x0
+-#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT__SHIFT 0x4
+-#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE__SHIFT 0x8
+-#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE__SHIFT 0x10
+-#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE__SHIFT 0x18
+-#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS_MASK 0x00000001L
+-#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT_MASK 0x00000010L
+-#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE_MASK 0x00000300L
+-#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE_MASK 0x00030000L
+-#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE_MASK 0x03000000L
+-//DAC_AUTODETECT_INT_CONTROL
+-#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK__SHIFT 0x0
+-#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE__SHIFT 0x10
+-#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK_MASK 0x00000001L
+-#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE_MASK 0x00010000L
+-//DAC_FORCE_OUTPUT_CNTL
+-#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN__SHIFT 0x0
+-#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL__SHIFT 0x8
+-#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKB_ONLY__SHIFT 0x18
+-#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN_MASK 0x00000001L
+-#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL_MASK 0x00000700L
+-#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKB_ONLY_MASK 0x01000000L
+-//DAC_FORCE_DATA
+-#define DAC_FORCE_DATA__DAC_FORCE_DATA__SHIFT 0x0
+-#define DAC_FORCE_DATA__DAC_FORCE_DATA_MASK 0x000003FFL
+-//DAC_POWERDOWN
+-#define DAC_POWERDOWN__DAC_POWERDOWN__SHIFT 0x0
+-#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE__SHIFT 0x8
+-#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN__SHIFT 0x10
+-#define DAC_POWERDOWN__DAC_POWERDOWN_RED__SHIFT 0x18
+-#define DAC_POWERDOWN__DAC_POWERDOWN_MASK 0x00000001L
+-#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE_MASK 0x00000100L
+-#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN_MASK 0x00010000L
+-#define DAC_POWERDOWN__DAC_POWERDOWN_RED_MASK 0x01000000L
+-//DAC_CONTROL
+-#define DAC_CONTROL__DAC_DFORCE_EN__SHIFT 0x0
+-#define DAC_CONTROL__DAC_TV_ENABLE__SHIFT 0x8
+-#define DAC_CONTROL__DAC_ZSCALE_SHIFT__SHIFT 0x10
+-#define DAC_CONTROL__DAC_DFORCE_EN_MASK 0x00000001L
+-#define DAC_CONTROL__DAC_TV_ENABLE_MASK 0x00000100L
+-#define DAC_CONTROL__DAC_ZSCALE_SHIFT_MASK 0x00010000L
+-//DAC_COMPARATOR_ENABLE
+-#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN__SHIFT 0x0
+-#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN__SHIFT 0x8
+-#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE__SHIFT 0x10
+-#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE__SHIFT 0x11
+-#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE__SHIFT 0x12
+-#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN_MASK 0x00000001L
+-#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN_MASK 0x00000100L
+-#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE_MASK 0x00010000L
+-#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE_MASK 0x00020000L
+-#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE_MASK 0x00040000L
+-//DAC_COMPARATOR_OUTPUT
+-#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT__SHIFT 0x0
+-#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE__SHIFT 0x1
+-#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN__SHIFT 0x2
+-#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED__SHIFT 0x3
+-#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_MASK 0x00000001L
+-#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE_MASK 0x00000002L
+-#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN_MASK 0x00000004L
+-#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED_MASK 0x00000008L
+-//DAC_PWR_CNTL
+-#define DAC_PWR_CNTL__DAC_BG_MODE__SHIFT 0x0
+-#define DAC_PWR_CNTL__DAC_PWRCNTL__SHIFT 0x10
+-#define DAC_PWR_CNTL__DAC_BG_MODE_MASK 0x00000003L
+-#define DAC_PWR_CNTL__DAC_PWRCNTL_MASK 0x00030000L
+-//DAC_DFT_CONFIG
+-#define DAC_DFT_CONFIG__DAC_DFT_CONFIG__SHIFT 0x0
+-#define DAC_DFT_CONFIG__DAC_DFT_CONFIG_MASK 0xFFFFFFFFL
+-//DAC_FIFO_STATUS
+-#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
+-#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
+-#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
+-#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
+-#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL__SHIFT 0x16
+-#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED__SHIFT 0x1d
+-#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
+-#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
+-#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L
+-#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL
+-#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L
+-#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL_MASK 0x000F0000L
+-#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L
+-#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED_MASK 0x20000000L
+-#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L
+-#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L
+-//DC_I2C_CONTROL
+-#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT 0x0
+-#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT 0x1
+-#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT 0x2
+-#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT 0x3
+-#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT 0x8
+-#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT 0x14
+-#define DC_I2C_CONTROL__DC_I2C_GO_MASK 0x00000001L
+-#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK 0x00000002L
+-#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK 0x00000004L
+-#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK 0x00000008L
+-#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK 0x00000700L
+-#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK 0x00300000L
+-//DC_I2C_ARBITRATION
+-#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT 0x0
+-#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT 0x2
+-#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT 0x4
+-#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT 0x8
+-#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT 0xc
+-#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT 0x14
+-#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT 0x15
+-#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT 0x18
+-#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT 0x19
+-#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK 0x00000003L
+-#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK 0x0000000CL
+-#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK 0x00000010L
+-#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK 0x00000100L
+-#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK 0x00001000L
+-#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK 0x00100000L
+-#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK 0x00200000L
+-#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK 0x01000000L
+-#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK 0x02000000L
+-//DC_I2C_INTERRUPT_CONTROL
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT 0x0
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT 0x1
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT 0x2
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT 0x4
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT 0x5
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT 0x6
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT 0x8
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT 0x9
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT 0xa
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT 0xc
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT 0xd
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT 0xe
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT 0x10
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT 0x11
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT 0x12
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT 0x14
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT 0x15
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT 0x16
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT 0x18
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT 0x19
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT 0x1a
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT 0x1b
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT 0x1c
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT 0x1d
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK 0x00000001L
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK 0x00000002L
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK 0x00000004L
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK 0x00000010L
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK 0x00000020L
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK 0x00000040L
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK 0x00000100L
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK 0x00000200L
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK 0x00000400L
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK 0x00001000L
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK 0x00002000L
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK 0x00004000L
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK 0x00010000L
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK 0x00020000L
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK 0x00040000L
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK 0x00100000L
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK 0x00200000L
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK 0x00400000L
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK 0x01000000L
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK 0x02000000L
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK 0x04000000L
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK 0x08000000L
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK 0x10000000L
+-#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK 0x20000000L
+-//DC_I2C_SW_STATUS
+-#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT 0x0
+-#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT 0x2
+-#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT 0x4
+-#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT 0x5
+-#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT 0x6
+-#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT 0x7
+-#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT 0x8
+-#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT 0xc
+-#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT 0xd
+-#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT 0xe
+-#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT 0xf
+-#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT 0x12
+-#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK 0x00000003L
+-#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK 0x00000004L
+-#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK 0x00000010L
+-#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK 0x00000020L
+-#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK 0x00000040L
+-#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK 0x00000080L
+-#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK 0x00000100L
+-#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK 0x00001000L
+-#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK 0x00002000L
+-#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK 0x00004000L
+-#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK 0x00008000L
+-#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK 0x00040000L
+-//DC_I2C_DDC1_HW_STATUS
+-#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT 0x0
+-#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT 0x3
+-#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT 0x10
+-#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT 0x11
+-#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT 0x14
+-#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+-#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT 0x1c
+-#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK 0x00000003L
+-#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK 0x00000008L
+-#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK 0x00010000L
+-#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK 0x00020000L
+-#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK 0x00100000L
+-#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L
+-#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK 0x70000000L
+-//DC_I2C_DDC2_HW_STATUS
+-#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT 0x0
+-#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT 0x3
+-#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT 0x10
+-#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT 0x11
+-#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT 0x14
+-#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+-#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT 0x1c
+-#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK 0x00000003L
+-#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK 0x00000008L
+-#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK 0x00010000L
+-#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK 0x00020000L
+-#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK 0x00100000L
+-#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L
+-#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK 0x70000000L
+-//DC_I2C_DDC3_HW_STATUS
+-#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT 0x0
+-#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT 0x3
+-#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT 0x10
+-#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT 0x11
+-#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT 0x14
+-#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+-#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT 0x1c
+-#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK 0x00000003L
+-#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK 0x00000008L
+-#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK 0x00010000L
+-#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK 0x00020000L
+-#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK 0x00100000L
+-#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L
+-#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK 0x70000000L
+-//DC_I2C_DDC4_HW_STATUS
+-#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT 0x0
+-#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT 0x3
+-#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT 0x10
+-#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT 0x11
+-#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT 0x14
+-#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+-#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT 0x1c
+-#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK 0x00000003L
+-#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK 0x00000008L
+-#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK 0x00010000L
+-#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK 0x00020000L
+-#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK 0x00100000L
+-#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L
+-#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK 0x70000000L
+-//DC_I2C_DDC5_HW_STATUS
+-#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT 0x0
+-#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT 0x3
+-#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT 0x10
+-#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT 0x11
+-#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT 0x14
+-#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+-#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT 0x1c
+-#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK 0x00000003L
+-#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK 0x00000008L
+-#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK 0x00010000L
+-#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK 0x00020000L
+-#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK 0x00100000L
+-#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L
+-#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK 0x70000000L
+-//DC_I2C_DDC6_HW_STATUS
+-#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS__SHIFT 0x0
+-#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE__SHIFT 0x3
+-#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ__SHIFT 0x10
+-#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG__SHIFT 0x11
+-#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS__SHIFT 0x14
+-#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+-#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE__SHIFT 0x1c
+-#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS_MASK 0x00000003L
+-#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE_MASK 0x00000008L
+-#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ_MASK 0x00010000L
+-#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG_MASK 0x00020000L
+-#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS_MASK 0x00100000L
+-#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L
+-#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE_MASK 0x70000000L
+-//DC_I2C_DDC1_SPEED
+-#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT 0x0
+-#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+-#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL__SHIFT 0x8
+-#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT 0x10
+-#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK 0x00000003L
+-#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L
+-#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL_MASK 0x00000300L
+-#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK 0xFFFF0000L
+-//DC_I2C_DDC1_SETUP
+-#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT 0x0
+-#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT 0x1
+-#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT 0x4
+-#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT 0x5
+-#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT 0x6
+-#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT 0x7
+-#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT 0x8
+-#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+-#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT 0x18
+-#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK 0x00000001L
+-#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK 0x00000002L
+-#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK 0x00000010L
+-#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK 0x00000020L
+-#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK 0x00000040L
+-#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK 0x00000080L
+-#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK 0x0000FF00L
+-#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L
+-#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK 0xFF000000L
+-//DC_I2C_DDC2_SPEED
+-#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT 0x0
+-#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+-#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL__SHIFT 0x8
+-#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT 0x10
+-#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK 0x00000003L
+-#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L
+-#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL_MASK 0x00000300L
+-#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK 0xFFFF0000L
+-//DC_I2C_DDC2_SETUP
+-#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT 0x0
+-#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT 0x1
+-#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT 0x4
+-#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT 0x5
+-#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT 0x6
+-#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT 0x7
+-#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT 0x8
+-#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+-#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT 0x18
+-#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK 0x00000001L
+-#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK 0x00000002L
+-#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK 0x00000010L
+-#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK 0x00000020L
+-#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK 0x00000040L
+-#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK 0x00000080L
+-#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK 0x0000FF00L
+-#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L
+-#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK 0xFF000000L
+-//DC_I2C_DDC3_SPEED
+-#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT 0x0
+-#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+-#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL__SHIFT 0x8
+-#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT 0x10
+-#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK 0x00000003L
+-#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L
+-#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL_MASK 0x00000300L
+-#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK 0xFFFF0000L
+-//DC_I2C_DDC3_SETUP
+-#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT 0x0
+-#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT 0x1
+-#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT 0x4
+-#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT 0x5
+-#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT 0x6
+-#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT 0x7
+-#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT 0x8
+-#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+-#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT 0x18
+-#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK 0x00000001L
+-#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK 0x00000002L
+-#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK 0x00000010L
+-#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK 0x00000020L
+-#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK 0x00000040L
+-#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK 0x00000080L
+-#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK 0x0000FF00L
+-#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L
+-#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK 0xFF000000L
+-//DC_I2C_DDC4_SPEED
+-#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT 0x0
+-#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+-#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL__SHIFT 0x8
+-#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT 0x10
+-#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK 0x00000003L
+-#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L
+-#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL_MASK 0x00000300L
+-#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK 0xFFFF0000L
+-//DC_I2C_DDC4_SETUP
+-#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT 0x0
+-#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT 0x1
+-#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT 0x4
+-#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT 0x5
+-#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT 0x6
+-#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT 0x7
+-#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT 0x8
+-#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+-#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT 0x18
+-#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK 0x00000001L
+-#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK 0x00000002L
+-#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK 0x00000010L
+-#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK 0x00000020L
+-#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK 0x00000040L
+-#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK 0x00000080L
+-#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK 0x0000FF00L
+-#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L
+-#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK 0xFF000000L
+-//DC_I2C_DDC5_SPEED
+-#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT 0x0
+-#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+-#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL__SHIFT 0x8
+-#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT 0x10
+-#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK 0x00000003L
+-#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L
+-#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL_MASK 0x00000300L
+-#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK 0xFFFF0000L
+-//DC_I2C_DDC5_SETUP
+-#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT 0x0
+-#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT 0x1
+-#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT 0x4
+-#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT 0x5
+-#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT 0x6
+-#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT 0x7
+-#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT 0x8
+-#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+-#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT 0x18
+-#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK 0x00000001L
+-#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK 0x00000002L
+-#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK 0x00000010L
+-#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK 0x00000020L
+-#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK 0x00000040L
+-#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK 0x00000080L
+-#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK 0x0000FF00L
+-#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L
+-#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK 0xFF000000L
+-//DC_I2C_DDC6_SPEED
+-#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD__SHIFT 0x0
+-#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+-#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_START_STOP_TIMING_CNTL__SHIFT 0x8
+-#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE__SHIFT 0x10
+-#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD_MASK 0x00000003L
+-#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L
+-#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_START_STOP_TIMING_CNTL_MASK 0x00000300L
+-#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE_MASK 0xFFFF0000L
+-//DC_I2C_DDC6_SETUP
+-#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN__SHIFT 0x0
+-#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL__SHIFT 0x1
+-#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE__SHIFT 0x4
+-#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE__SHIFT 0x5
+-#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE__SHIFT 0x6
+-#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN__SHIFT 0x7
+-#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY__SHIFT 0x8
+-#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+-#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT__SHIFT 0x18
+-#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN_MASK 0x00000001L
+-#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL_MASK 0x00000002L
+-#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE_MASK 0x00000010L
+-#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE_MASK 0x00000020L
+-#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE_MASK 0x00000040L
+-#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN_MASK 0x00000080L
+-#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY_MASK 0x0000FF00L
+-#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L
+-#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT_MASK 0xFF000000L
+-//DC_I2C_TRANSACTION0
+-#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT 0x0
+-#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT 0x8
+-#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT 0xc
+-#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT 0xd
+-#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT 0x10
+-#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK 0x00000001L
+-#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK 0x00000100L
+-#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK 0x00001000L
+-#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK 0x00002000L
+-#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK 0x03FF0000L
+-//DC_I2C_TRANSACTION1
+-#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT 0x0
+-#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT 0x8
+-#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT 0xc
+-#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT 0xd
+-#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT 0x10
+-#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK 0x00000001L
+-#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK 0x00000100L
+-#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK 0x00001000L
+-#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK 0x00002000L
+-#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK 0x03FF0000L
+-//DC_I2C_TRANSACTION2
+-#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT 0x0
+-#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT 0x8
+-#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT 0xc
+-#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT 0xd
+-#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT 0x10
+-#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK 0x00000001L
+-#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK 0x00000100L
+-#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK 0x00001000L
+-#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK 0x00002000L
+-#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK 0x03FF0000L
+-//DC_I2C_TRANSACTION3
+-#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT 0x0
+-#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT 0x8
+-#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT 0xc
+-#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT 0xd
+-#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT 0x10
+-#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK 0x00000001L
+-#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK 0x00000100L
+-#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK 0x00001000L
+-#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK 0x00002000L
+-#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK 0x03FF0000L
+-//DC_I2C_DATA
+-#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT 0x0
+-#define DC_I2C_DATA__DC_I2C_DATA__SHIFT 0x8
+-#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT 0x10
+-#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT 0x1f
+-#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK 0x00000001L
+-#define DC_I2C_DATA__DC_I2C_DATA_MASK 0x0000FF00L
+-#define DC_I2C_DATA__DC_I2C_INDEX_MASK 0x03FF0000L
+-#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK 0x80000000L
+-//DC_I2C_DDCVGA_HW_STATUS
+-#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS__SHIFT 0x0
+-#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE__SHIFT 0x3
+-#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ__SHIFT 0x10
+-#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG__SHIFT 0x11
+-#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS__SHIFT 0x14
+-#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+-#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE__SHIFT 0x1c
+-#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS_MASK 0x00000003L
+-#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE_MASK 0x00000008L
+-#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ_MASK 0x00010000L
+-#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG_MASK 0x00020000L
+-#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS_MASK 0x00100000L
+-#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L
+-#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE_MASK 0x70000000L
+-//DC_I2C_DDCVGA_SPEED
+-#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD__SHIFT 0x0
+-#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+-#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_START_STOP_TIMING_CNTL__SHIFT 0x8
+-#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE__SHIFT 0x10
+-#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD_MASK 0x00000003L
+-#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L
+-#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_START_STOP_TIMING_CNTL_MASK 0x00000300L
+-#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE_MASK 0xFFFF0000L
+-//DC_I2C_DDCVGA_SETUP
+-#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN__SHIFT 0x0
+-#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL__SHIFT 0x1
+-#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE__SHIFT 0x4
+-#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE__SHIFT 0x5
+-#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE__SHIFT 0x6
+-#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN__SHIFT 0x7
+-#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY__SHIFT 0x8
+-#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+-#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT__SHIFT 0x18
+-#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN_MASK 0x00000001L
+-#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL_MASK 0x00000002L
+-#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE_MASK 0x00000010L
+-#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE_MASK 0x00000020L
+-#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE_MASK 0x00000040L
+-#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN_MASK 0x00000080L
+-#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY_MASK 0x0000FF00L
+-#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L
+-#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT_MASK 0xFF000000L
+-//DC_I2C_EDID_DETECT_CTRL
+-#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT 0x0
+-#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT 0x14
+-#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT 0x1c
+-#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK 0x0000FFFFL
+-#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK 0x00F00000L
+-#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK 0x10000000L
+-//DC_I2C_READ_REQUEST_INTERRUPT
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED__SHIFT 0x0
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT__SHIFT 0x1
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK__SHIFT 0x2
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK__SHIFT 0x3
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED__SHIFT 0x4
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT__SHIFT 0x5
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK__SHIFT 0x6
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK__SHIFT 0x7
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED__SHIFT 0x8
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT__SHIFT 0x9
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK__SHIFT 0xa
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK__SHIFT 0xb
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED__SHIFT 0xc
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT__SHIFT 0xd
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK__SHIFT 0xe
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK__SHIFT 0xf
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED__SHIFT 0x10
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT__SHIFT 0x11
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK__SHIFT 0x12
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK__SHIFT 0x13
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED__SHIFT 0x14
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT__SHIFT 0x15
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK__SHIFT 0x16
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK__SHIFT 0x17
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED__SHIFT 0x18
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT__SHIFT 0x19
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK__SHIFT 0x1a
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK__SHIFT 0x1b
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE__SHIFT 0x1e
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT 0x1f
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED_MASK 0x00000001L
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT_MASK 0x00000002L
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK_MASK 0x00000004L
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK_MASK 0x00000008L
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED_MASK 0x00000010L
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT_MASK 0x00000020L
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK_MASK 0x00000040L
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK_MASK 0x00000080L
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED_MASK 0x00000100L
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT_MASK 0x00000200L
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK_MASK 0x00000400L
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK_MASK 0x00000800L
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED_MASK 0x00001000L
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT_MASK 0x00002000L
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK_MASK 0x00004000L
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK_MASK 0x00008000L
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED_MASK 0x00010000L
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT_MASK 0x00020000L
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK_MASK 0x00040000L
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK_MASK 0x00080000L
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED_MASK 0x00100000L
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT_MASK 0x00200000L
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK_MASK 0x00400000L
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK_MASK 0x00800000L
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED_MASK 0x01000000L
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT_MASK 0x02000000L
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK_MASK 0x04000000L
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK_MASK 0x08000000L
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE_MASK 0x40000000L
+-#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK 0x80000000L
+-//GENERIC_I2C_CONTROL
+-#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO__SHIFT 0x0
+-#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET__SHIFT 0x1
+-#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET__SHIFT 0x2
+-#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE__SHIFT 0x3
+-#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO_MASK 0x00000001L
+-#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET_MASK 0x00000002L
+-#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET_MASK 0x00000004L
+-#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE_MASK 0x00000008L
+-//GENERIC_I2C_INTERRUPT_CONTROL
+-#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT__SHIFT 0x0
+-#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK__SHIFT 0x1
+-#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK__SHIFT 0x2
+-#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT_MASK 0x00000001L
+-#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK_MASK 0x00000002L
+-#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK_MASK 0x00000004L
+-//GENERIC_I2C_STATUS
+-#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS__SHIFT 0x0
+-#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE__SHIFT 0x4
+-#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED__SHIFT 0x5
+-#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT__SHIFT 0x6
+-#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK__SHIFT 0x9
+-#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK__SHIFT 0xa
+-#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS_MASK 0x0000000FL
+-#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE_MASK 0x00000010L
+-#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED_MASK 0x00000020L
+-#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT_MASK 0x00000040L
+-#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK_MASK 0x00000200L
+-#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK_MASK 0x00000400L
+-//GENERIC_I2C_SPEED
+-#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD__SHIFT 0x0
+-#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+-#define GENERIC_I2C_SPEED__GENERIC_I2C_START_STOP_TIMING_CNTL__SHIFT 0x8
+-#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE__SHIFT 0x10
+-#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD_MASK 0x00000003L
+-#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L
+-#define GENERIC_I2C_SPEED__GENERIC_I2C_START_STOP_TIMING_CNTL_MASK 0x00000300L
+-#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE_MASK 0xFFFF0000L
+-//GENERIC_I2C_SETUP
+-#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN__SHIFT 0x0
+-#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL__SHIFT 0x1
+-#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN__SHIFT 0x7
+-#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY__SHIFT 0x8
+-#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT__SHIFT 0x18
+-#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN_MASK 0x00000001L
+-#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL_MASK 0x00000002L
+-#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN_MASK 0x00000080L
+-#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY_MASK 0x0000FF00L
+-#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT_MASK 0xFF000000L
+-//GENERIC_I2C_TRANSACTION
+-#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW__SHIFT 0x0
+-#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK__SHIFT 0x8
+-#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ__SHIFT 0x9
+-#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START__SHIFT 0xc
+-#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP__SHIFT 0xd
+-#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT__SHIFT 0x10
+-#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW_MASK 0x00000001L
+-#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK_MASK 0x00000100L
+-#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ_MASK 0x00000200L
+-#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START_MASK 0x00001000L
+-#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_MASK 0x00002000L
+-#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT_MASK 0x000F0000L
+-//GENERIC_I2C_DATA
+-#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW__SHIFT 0x0
+-#define GENERIC_I2C_DATA__GENERIC_I2C_DATA__SHIFT 0x8
+-#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX__SHIFT 0x10
+-#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE__SHIFT 0x1f
+-#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW_MASK 0x00000001L
+-#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_MASK 0x0000FF00L
+-#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_MASK 0x000F0000L
+-#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE_MASK 0x80000000L
+-//GENERIC_I2C_PIN_SELECTION
+-#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL__SHIFT 0x0
+-#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL__SHIFT 0x8
+-#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL_MASK 0x0000007FL
+-#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL_MASK 0x00007F00L
+-//DCO_SCRATCH0
+-#define DCO_SCRATCH0__DCO_SCRATCH0__SHIFT 0x0
+-#define DCO_SCRATCH0__DCO_SCRATCH0_MASK 0xFFFFFFFFL
+-//DCO_SCRATCH1
+-#define DCO_SCRATCH1__DCO_SCRATCH1__SHIFT 0x0
+-#define DCO_SCRATCH1__DCO_SCRATCH1_MASK 0xFFFFFFFFL
+-//DCO_SCRATCH2
+-#define DCO_SCRATCH2__DCO_SCRATCH2__SHIFT 0x0
+-#define DCO_SCRATCH2__DCO_SCRATCH2_MASK 0xFFFFFFFFL
+-//DCO_SCRATCH3
+-#define DCO_SCRATCH3__DCO_SCRATCH3__SHIFT 0x0
+-#define DCO_SCRATCH3__DCO_SCRATCH3_MASK 0xFFFFFFFFL
+-//DCO_SCRATCH4
+-#define DCO_SCRATCH4__DCO_SCRATCH4__SHIFT 0x0
+-#define DCO_SCRATCH4__DCO_SCRATCH4_MASK 0xFFFFFFFFL
+-//DCO_SCRATCH5
+-#define DCO_SCRATCH5__DCO_SCRATCH5__SHIFT 0x0
+-#define DCO_SCRATCH5__DCO_SCRATCH5_MASK 0xFFFFFFFFL
+-//DCO_SCRATCH6
+-#define DCO_SCRATCH6__DCO_SCRATCH6__SHIFT 0x0
+-#define DCO_SCRATCH6__DCO_SCRATCH6_MASK 0xFFFFFFFFL
+-//DCO_SCRATCH7
+-#define DCO_SCRATCH7__DCO_SCRATCH7__SHIFT 0x0
+-#define DCO_SCRATCH7__DCO_SCRATCH7_MASK 0xFFFFFFFFL
+-//DCE_VCE_CONTROL
+-#define DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT__SHIFT 0x0
+-#define DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT__SHIFT 0x4
+-#define DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT_MASK 0x00000007L
+-#define DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT_MASK 0x00000070L
+-//DISP_INTERRUPT_STATUS
+-#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT__SHIFT 0x0
+-#define DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
+-#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT__SHIFT 0x2
+-#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT__SHIFT 0x3
+-#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT__SHIFT 0x4
+-#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
+-#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
+-#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT__SHIFT 0x7
+-#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT__SHIFT 0x8
+-#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT__SHIFT 0x9
+-#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
+-#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+-#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+-#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT 0x11
+-#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x12
+-#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT 0x13
+-#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT 0x14
+-#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT__SHIFT 0x16
+-#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT__SHIFT 0x17
+-#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT 0x18
+-#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT__SHIFT 0x19
+-#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT 0x1a
+-#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT 0x1c
+-#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT 0x1d
+-#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT 0x1e
+-#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT 0x1f
+-#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT_MASK 0x00000001L
+-#define DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L
+-#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK 0x00000004L
+-#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK 0x00000008L
+-#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT_MASK 0x00000010L
+-#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L
+-#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L
+-#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT_MASK 0x00000080L
+-#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT_MASK 0x00000100L
+-#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT_MASK 0x00000200L
+-#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L
+-#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L
+-#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L
+-#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x00020000L
+-#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK 0x00040000L
+-#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK 0x00080000L
+-#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK 0x00100000L
+-#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT_MASK 0x00400000L
+-#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT_MASK 0x00800000L
+-#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK 0x01000000L
+-#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT_MASK 0x02000000L
+-#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK 0x04000000L
+-#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK 0x10000000L
+-#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK 0x20000000L
+-#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK 0x40000000L
+-#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK 0x80000000L
+-//DISP_INTERRUPT_STATUS_CONTINUE
+-#define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT__SHIFT 0x0
+-#define DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
+-#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT__SHIFT 0x2
+-#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT__SHIFT 0x3
+-#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT__SHIFT 0x4
+-#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
+-#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
+-#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT__SHIFT 0x7
+-#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT__SHIFT 0x8
+-#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT__SHIFT 0x9
+-#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
+-#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+-#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+-#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT 0x11
+-#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT 0x12
+-#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT 0x13
+-#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT 0x14
+-#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D1_VLINE2_INTERRUPT__SHIFT 0x15
+-#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE2_INTERRUPT__SHIFT 0x16
+-#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D3_VLINE2_INTERRUPT__SHIFT 0x17
+-#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
+-#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
+-#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
+-#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT0__SHIFT 0x1c
+-#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT1__SHIFT 0x1d
+-#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT2__SHIFT 0x1e
+-#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT 0x1f
+-#define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT_MASK 0x00000001L
+-#define DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L
+-#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK 0x00000004L
+-#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK 0x00000008L
+-#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT_MASK 0x00000010L
+-#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L
+-#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L
+-#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT_MASK 0x00000080L
+-#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT_MASK 0x00000100L
+-#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT_MASK 0x00000200L
+-#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L
+-#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x00020000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK 0x00040000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK 0x00080000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK 0x00100000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D1_VLINE2_INTERRUPT_MASK 0x00200000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE2_INTERRUPT_MASK 0x00400000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D3_VLINE2_INTERRUPT_MASK 0x00800000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x02000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_INTERRUPT_MASK 0x04000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x08000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT0_MASK 0x10000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT1_MASK 0x20000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT2_MASK 0x40000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK 0x80000000L
+-//DISP_INTERRUPT_STATUS_CONTINUE2
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT__SHIFT 0x0
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT__SHIFT 0x2
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT__SHIFT 0x3
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT__SHIFT 0x4
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT__SHIFT 0x7
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT__SHIFT 0x8
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT__SHIFT 0x9
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT 0x11
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT 0x12
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT 0x13
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT 0x14
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D4_VLINE2_INTERRUPT__SHIFT 0x15
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D5_VLINE2_INTERRUPT__SHIFT 0x16
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D6_VLINE2_INTERRUPT__SHIFT 0x17
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT0__SHIFT 0x1c
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT1__SHIFT 0x1d
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT2__SHIFT 0x1e
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT 0x1f
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT_MASK 0x00000001L
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK 0x00000004L
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK 0x00000008L
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT_MASK 0x00000010L
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT_MASK 0x00000080L
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT_MASK 0x00000100L
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT_MASK 0x00000200L
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x00020000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK 0x00040000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK 0x00080000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK 0x00100000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D4_VLINE2_INTERRUPT_MASK 0x00200000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D5_VLINE2_INTERRUPT_MASK 0x00400000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D6_VLINE2_INTERRUPT_MASK 0x00800000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x02000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_INTERRUPT_MASK 0x04000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x08000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT0_MASK 0x10000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT1_MASK 0x20000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT2_MASK 0x40000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK 0x80000000L
+-//DISP_INTERRUPT_STATUS_CONTINUE3
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT__SHIFT 0x0
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT__SHIFT 0x2
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT__SHIFT 0x3
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT__SHIFT 0x4
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT__SHIFT 0x7
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT__SHIFT 0x8
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT__SHIFT 0x9
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT 0x11
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT 0x12
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT 0x13
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT 0x14
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__BUFMGR_IHIF_INTERRUPT__SHIFT 0x15
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_HOST_CONFLICT_INTERRUPT__SHIFT 0x16
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_DATA_OVERFLOW_INTERRUPT__SHIFT 0x17
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT0__SHIFT 0x1c
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT1__SHIFT 0x1d
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT2__SHIFT 0x1e
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT 0x1f
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT_MASK 0x00000001L
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK 0x00000004L
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK 0x00000008L
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT_MASK 0x00000010L
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT_MASK 0x00000080L
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT_MASK 0x00000100L
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT_MASK 0x00000200L
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x00020000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK 0x00040000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK 0x00080000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK 0x00100000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__BUFMGR_IHIF_INTERRUPT_MASK 0x00200000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_HOST_CONFLICT_INTERRUPT_MASK 0x00400000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_DATA_OVERFLOW_INTERRUPT_MASK 0x00800000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x02000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_INTERRUPT_MASK 0x04000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x08000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT0_MASK 0x10000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT1_MASK 0x20000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT2_MASK 0x40000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK 0x80000000L
+-//DISP_INTERRUPT_STATUS_CONTINUE4
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT__SHIFT 0x0
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT__SHIFT 0x2
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT__SHIFT 0x3
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT__SHIFT 0x4
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT__SHIFT 0x7
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT__SHIFT 0x8
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT__SHIFT 0x9
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT 0x11
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT 0x12
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT 0x13
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT 0x14
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT0__SHIFT 0x1c
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT1__SHIFT 0x1d
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT2__SHIFT 0x1e
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT 0x1f
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT_MASK 0x00000001L
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK 0x00000004L
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK 0x00000008L
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT_MASK 0x00000010L
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT_MASK 0x00000080L
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT_MASK 0x00000100L
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT_MASK 0x00000200L
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x00020000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK 0x00040000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK 0x00080000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK 0x00100000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x00400000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_INTERRUPT_MASK 0x00800000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x01000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x02000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_INTERRUPT_MASK 0x04000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x08000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT0_MASK 0x10000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT1_MASK 0x20000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT2_MASK 0x40000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK 0x80000000L
+-//DISP_INTERRUPT_STATUS_CONTINUE5
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT__SHIFT 0x0
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT__SHIFT 0x2
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT__SHIFT 0x3
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT__SHIFT 0x4
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT__SHIFT 0x7
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT__SHIFT 0x8
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT__SHIFT 0x9
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT 0x11
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT 0x12
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT 0x13
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT 0x14
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT0__SHIFT 0x19
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT1__SHIFT 0x1a
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT2__SHIFT 0x1b
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT0__SHIFT 0x1c
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT1__SHIFT 0x1d
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT2__SHIFT 0x1e
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT 0x1f
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT_MASK 0x00000001L
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK 0x00000004L
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK 0x00000008L
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT_MASK 0x00000010L
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT_MASK 0x00000080L
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT_MASK 0x00000100L
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT_MASK 0x00000200L
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x00020000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK 0x00040000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK 0x00080000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK 0x00100000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x00400000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_INTERRUPT_MASK 0x00800000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x01000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT0_MASK 0x02000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT1_MASK 0x04000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT2_MASK 0x08000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT0_MASK 0x10000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT1_MASK 0x20000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT2_MASK 0x40000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK 0x80000000L
+-//DISP_INTERRUPT_STATUS_CONTINUE6
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB0_IHIF_INTERRUPT__SHIFT 0x9
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB1_IHIF_INTERRUPT__SHIFT 0xa
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x11
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x12
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x13
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x14
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x15
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x16
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x17
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x18
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x19
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1a
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x1b
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1c
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT 0x1f
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER2_INTERRUPT_MASK 0x00000004L
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER3_INTERRUPT_MASK 0x00000008L
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER4_INTERRUPT_MASK 0x00000010L
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER5_INTERRUPT_MASK 0x00000020L
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER6_INTERRUPT_MASK 0x00000040L
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER7_INTERRUPT_MASK 0x00000080L
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x00000100L
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB0_IHIF_INTERRUPT_MASK 0x00000200L
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB1_IHIF_INTERRUPT_MASK 0x00000400L
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00020000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT_MASK 0x00040000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00080000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT_MASK 0x00100000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00200000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT_MASK 0x00400000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00800000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT_MASK 0x01000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x02000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT_MASK 0x04000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x08000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT_MASK 0x10000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK 0x80000000L
+-//DISP_INTERRUPT_STATUS_CONTINUE7
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x1b
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1c
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x1d
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x1e
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT 0x1f
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT_MASK 0x00000004L
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER3_INTERRUPT_MASK 0x00000008L
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER4_INTERRUPT_MASK 0x00000010L
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER5_INTERRUPT_MASK 0x00000020L
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER6_INTERRUPT_MASK 0x00000040L
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER7_INTERRUPT_MASK 0x00000080L
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x00000100L
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER2_INTERRUPT_MASK 0x00000800L
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER3_INTERRUPT_MASK 0x00001000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER4_INTERRUPT_MASK 0x00002000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER5_INTERRUPT_MASK 0x00004000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER6_INTERRUPT_MASK 0x00008000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER7_INTERRUPT_MASK 0x00010000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x00020000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER2_INTERRUPT_MASK 0x00100000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER3_INTERRUPT_MASK 0x00200000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER4_INTERRUPT_MASK 0x00400000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER5_INTERRUPT_MASK 0x00800000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER6_INTERRUPT_MASK 0x01000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER7_INTERRUPT_MASK 0x02000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x04000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER0_INTERRUPT_MASK 0x08000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER1_INTERRUPT_MASK 0x10000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER2_INTERRUPT_MASK 0x20000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER3_INTERRUPT_MASK 0x40000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK 0x80000000L
+-//DISP_INTERRUPT_STATUS_CONTINUE8
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x1b
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x1c
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x1d
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x1e
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT 0x1f
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT_MASK 0x00000004L
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER3_INTERRUPT_MASK 0x00000008L
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER4_INTERRUPT_MASK 0x00000010L
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER5_INTERRUPT_MASK 0x00000020L
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER6_INTERRUPT_MASK 0x00000040L
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER7_INTERRUPT_MASK 0x00000080L
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x00000100L
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER2_INTERRUPT_MASK 0x00000800L
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER3_INTERRUPT_MASK 0x00001000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER4_INTERRUPT_MASK 0x00002000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER5_INTERRUPT_MASK 0x00004000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER6_INTERRUPT_MASK 0x00008000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER7_INTERRUPT_MASK 0x00010000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x00020000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER2_INTERRUPT_MASK 0x00100000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER3_INTERRUPT_MASK 0x00200000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER4_INTERRUPT_MASK 0x00400000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER5_INTERRUPT_MASK 0x00800000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER6_INTERRUPT_MASK 0x01000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER7_INTERRUPT_MASK 0x02000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x04000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER4_INTERRUPT_MASK 0x08000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER5_INTERRUPT_MASK 0x10000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER6_INTERRUPT_MASK 0x20000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER7_INTERRUPT_MASK 0x40000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK 0x80000000L
+-//DISP_INTERRUPT_STATUS_CONTINUE9
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__WB_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1b
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10__SHIFT 0x1f
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT_MASK 0x00000004L
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER3_INTERRUPT_MASK 0x00000008L
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER4_INTERRUPT_MASK 0x00000010L
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER5_INTERRUPT_MASK 0x00000020L
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER6_INTERRUPT_MASK 0x00000040L
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER7_INTERRUPT_MASK 0x00000080L
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x00000100L
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER2_INTERRUPT_MASK 0x00000800L
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER3_INTERRUPT_MASK 0x00001000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER4_INTERRUPT_MASK 0x00002000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER5_INTERRUPT_MASK 0x00004000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER6_INTERRUPT_MASK 0x00008000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER7_INTERRUPT_MASK 0x00010000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x00020000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER2_INTERRUPT_MASK 0x00100000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER3_INTERRUPT_MASK 0x00200000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER4_INTERRUPT_MASK 0x00400000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER5_INTERRUPT_MASK 0x00800000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER6_INTERRUPT_MASK 0x01000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER7_INTERRUPT_MASK 0x02000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x04000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__WB_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x08000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10_MASK 0x80000000L
+-//DCO_MEM_PWR_STATUS
+-#define DCO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE__SHIFT 0x0
+-#define DCO_MEM_PWR_STATUS__MVP_MEM_PWR_STATE__SHIFT 0x2
+-#define DCO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE__SHIFT 0x3
+-#define DCO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE__SHIFT 0x4
+-#define DCO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE__SHIFT 0x5
+-#define DCO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE__SHIFT 0x6
+-#define DCO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE__SHIFT 0x7
+-#define DCO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE__SHIFT 0x8
+-#define DCO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE__SHIFT 0x9
+-#define DCO_MEM_PWR_STATUS__HDMI0_MEM_PWR_STATE__SHIFT 0xa
+-#define DCO_MEM_PWR_STATUS__HDMI1_MEM_PWR_STATE__SHIFT 0xc
+-#define DCO_MEM_PWR_STATUS__HDMI2_MEM_PWR_STATE__SHIFT 0xe
+-#define DCO_MEM_PWR_STATUS__HDMI3_MEM_PWR_STATE__SHIFT 0x10
+-#define DCO_MEM_PWR_STATUS__HDMI4_MEM_PWR_STATE__SHIFT 0x12
+-#define DCO_MEM_PWR_STATUS__HDMI5_MEM_PWR_STATE__SHIFT 0x14
+-#define DCO_MEM_PWR_STATUS__HDMI6_MEM_PWR_STATE__SHIFT 0x16
+-#define DCO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE_MASK 0x00000001L
+-#define DCO_MEM_PWR_STATUS__MVP_MEM_PWR_STATE_MASK 0x00000004L
+-#define DCO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE_MASK 0x00000008L
+-#define DCO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE_MASK 0x00000010L
+-#define DCO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE_MASK 0x00000020L
+-#define DCO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE_MASK 0x00000040L
+-#define DCO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE_MASK 0x00000080L
+-#define DCO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE_MASK 0x00000100L
+-#define DCO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE_MASK 0x00000200L
+-#define DCO_MEM_PWR_STATUS__HDMI0_MEM_PWR_STATE_MASK 0x00000C00L
+-#define DCO_MEM_PWR_STATUS__HDMI1_MEM_PWR_STATE_MASK 0x00003000L
+-#define DCO_MEM_PWR_STATUS__HDMI2_MEM_PWR_STATE_MASK 0x0000C000L
+-#define DCO_MEM_PWR_STATUS__HDMI3_MEM_PWR_STATE_MASK 0x00030000L
+-#define DCO_MEM_PWR_STATUS__HDMI4_MEM_PWR_STATE_MASK 0x000C0000L
+-#define DCO_MEM_PWR_STATUS__HDMI5_MEM_PWR_STATE_MASK 0x00300000L
+-#define DCO_MEM_PWR_STATUS__HDMI6_MEM_PWR_STATE_MASK 0x00C00000L
+-//DCO_MEM_PWR_CTRL
+-#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE__SHIFT 0x0
+-#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS__SHIFT 0x1
+-#define DCO_MEM_PWR_CTRL__MVP_LIGHT_SLEEP_DIS__SHIFT 0x3
+-#define DCO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS__SHIFT 0x4
+-#define DCO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS__SHIFT 0x5
+-#define DCO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS__SHIFT 0x6
+-#define DCO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS__SHIFT 0x7
+-#define DCO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS__SHIFT 0x8
+-#define DCO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS__SHIFT 0x9
+-#define DCO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS__SHIFT 0xa
+-#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_FORCE__SHIFT 0xb
+-#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_DIS__SHIFT 0xd
+-#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_FORCE__SHIFT 0xe
+-#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_DIS__SHIFT 0x10
+-#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_FORCE__SHIFT 0x11
+-#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_DIS__SHIFT 0x13
+-#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_FORCE__SHIFT 0x14
+-#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_DIS__SHIFT 0x16
+-#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_FORCE__SHIFT 0x17
+-#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_DIS__SHIFT 0x19
+-#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE__SHIFT 0x1a
+-#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_DIS__SHIFT 0x1c
+-#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE__SHIFT 0x1d
+-#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_DIS__SHIFT 0x1f
+-#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE_MASK 0x00000001L
+-#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS_MASK 0x00000002L
+-#define DCO_MEM_PWR_CTRL__MVP_LIGHT_SLEEP_DIS_MASK 0x00000008L
+-#define DCO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS_MASK 0x00000010L
+-#define DCO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS_MASK 0x00000020L
+-#define DCO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS_MASK 0x00000040L
+-#define DCO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS_MASK 0x00000080L
+-#define DCO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS_MASK 0x00000100L
+-#define DCO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS_MASK 0x00000200L
+-#define DCO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS_MASK 0x00000400L
+-#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_FORCE_MASK 0x00001800L
+-#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_DIS_MASK 0x00002000L
+-#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_FORCE_MASK 0x0000C000L
+-#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_DIS_MASK 0x00010000L
+-#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_FORCE_MASK 0x00060000L
+-#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_DIS_MASK 0x00080000L
+-#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_FORCE_MASK 0x00300000L
+-#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_DIS_MASK 0x00400000L
+-#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_FORCE_MASK 0x01800000L
+-#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_DIS_MASK 0x02000000L
+-#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE_MASK 0x0C000000L
+-#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_DIS_MASK 0x10000000L
+-#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE_MASK 0x60000000L
+-#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_DIS_MASK 0x80000000L
+-//DCO_MEM_PWR_CTRL2
+-#define DCO_MEM_PWR_CTRL2__HDMI_MEM_PWR_MODE_SEL__SHIFT 0x0
+-#define DCO_MEM_PWR_CTRL2__DPLPA_LIGHT_SLEEP_DIS__SHIFT 0x2
+-#define DCO_MEM_PWR_CTRL2__DPLPB_LIGHT_SLEEP_DIS__SHIFT 0x3
+-#define DCO_MEM_PWR_CTRL2__HDMILP0_MEM_PWR_FORCE__SHIFT 0x10
+-#define DCO_MEM_PWR_CTRL2__HDMILP0_MEM_PWR_DIS__SHIFT 0x12
+-#define DCO_MEM_PWR_CTRL2__HDMILP1_MEM_PWR_FORCE__SHIFT 0x13
+-#define DCO_MEM_PWR_CTRL2__HDMILP1_MEM_PWR_DIS__SHIFT 0x15
+-#define DCO_MEM_PWR_CTRL2__HDMI_MEM_PWR_MODE_SEL_MASK 0x00000003L
+-#define DCO_MEM_PWR_CTRL2__DPLPA_LIGHT_SLEEP_DIS_MASK 0x00000004L
+-#define DCO_MEM_PWR_CTRL2__DPLPB_LIGHT_SLEEP_DIS_MASK 0x00000008L
+-#define DCO_MEM_PWR_CTRL2__HDMILP0_MEM_PWR_FORCE_MASK 0x00030000L
+-#define DCO_MEM_PWR_CTRL2__HDMILP0_MEM_PWR_DIS_MASK 0x00040000L
+-#define DCO_MEM_PWR_CTRL2__HDMILP1_MEM_PWR_FORCE_MASK 0x00180000L
+-#define DCO_MEM_PWR_CTRL2__HDMILP1_MEM_PWR_DIS_MASK 0x00200000L
+-//DCO_CLK_CNTL
+-#define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS__SHIFT 0x5
+-#define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS__SHIFT 0x6
+-#define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS__SHIFT 0x7
+-#define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS__SHIFT 0x8
+-#define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS__SHIFT 0x9
+-#define DCO_CLK_CNTL__REFCLK_R_DCO_GATE_DIS__SHIFT 0xa
+-#define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS__SHIFT 0x10
+-#define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS__SHIFT 0x11
+-#define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS__SHIFT 0x12
+-#define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS__SHIFT 0x13
+-#define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS__SHIFT 0x14
+-#define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS__SHIFT 0x15
+-#define DCO_CLK_CNTL__DISPCLK_G_DIGLPA_GATE_DIS__SHIFT 0x16
+-#define DCO_CLK_CNTL__DISPCLK_G_DIGLPB_GATE_DIS__SHIFT 0x17
+-#define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT 0x18
+-#define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT 0x19
+-#define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT 0x1a
+-#define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT 0x1b
+-#define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT 0x1c
+-#define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT 0x1d
+-#define DCO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS__SHIFT 0x1e
+-#define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS_MASK 0x00000020L
+-#define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS_MASK 0x00000040L
+-#define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS_MASK 0x00000080L
+-#define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS_MASK 0x00000100L
+-#define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS_MASK 0x00000200L
+-#define DCO_CLK_CNTL__REFCLK_R_DCO_GATE_DIS_MASK 0x00000400L
+-#define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS_MASK 0x00010000L
+-#define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS_MASK 0x00020000L
+-#define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS_MASK 0x00040000L
+-#define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS_MASK 0x00080000L
+-#define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS_MASK 0x00100000L
+-#define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS_MASK 0x00200000L
+-#define DCO_CLK_CNTL__DISPCLK_G_DIGLPA_GATE_DIS_MASK 0x00400000L
+-#define DCO_CLK_CNTL__DISPCLK_G_DIGLPB_GATE_DIS_MASK 0x00800000L
+-#define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK 0x01000000L
+-#define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK 0x02000000L
+-#define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK 0x04000000L
+-#define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK 0x08000000L
+-#define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK 0x10000000L
+-#define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK 0x20000000L
+-#define DCO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS_MASK 0x40000000L
+-//DCO_POWER_MANAGEMENT_CNTL
+-#define DCO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT 0x0
+-#define DCO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT 0x8
+-#define DCO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK 0x00000001L
+-#define DCO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK 0x00000100L
+-//DIG_SOFT_RESET_2
+-#define DIG_SOFT_RESET_2__DIGLPA_FE_SOFT_RESET__SHIFT 0x0
+-#define DIG_SOFT_RESET_2__DIGLPA_BE_SOFT_RESET__SHIFT 0x1
+-#define DIG_SOFT_RESET_2__DIGLPB_FE_SOFT_RESET__SHIFT 0x4
+-#define DIG_SOFT_RESET_2__DIGLPB_BE_SOFT_RESET__SHIFT 0x5
+-#define DIG_SOFT_RESET_2__DIGLPA_FE_SOFT_RESET_MASK 0x00000001L
+-#define DIG_SOFT_RESET_2__DIGLPA_BE_SOFT_RESET_MASK 0x00000002L
+-#define DIG_SOFT_RESET_2__DIGLPB_FE_SOFT_RESET_MASK 0x00000010L
+-#define DIG_SOFT_RESET_2__DIGLPB_BE_SOFT_RESET_MASK 0x00000020L
+-//DCO_STEREOSYNC_SEL
+-#define DCO_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL__SHIFT 0x0
+-#define DCO_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL__SHIFT 0x10
+-#define DCO_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL_MASK 0x00000007L
+-#define DCO_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL_MASK 0x00070000L
+-//DCO_SOFT_RESET
+-#define DCO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x0
+-#define DCO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET__SHIFT 0x4
+-#define DCO_SOFT_RESET__I2S1_SOFT_RESET__SHIFT 0x5
+-#define DCO_SOFT_RESET__SPDIF1_SOFT_RESET__SHIFT 0x6
+-#define DCO_SOFT_RESET__DB_CLK_SOFT_RESET__SHIFT 0xc
+-#define DCO_SOFT_RESET__FMT0_SOFT_RESET__SHIFT 0x10
+-#define DCO_SOFT_RESET__FMT1_SOFT_RESET__SHIFT 0x11
+-#define DCO_SOFT_RESET__FMT2_SOFT_RESET__SHIFT 0x12
+-#define DCO_SOFT_RESET__FMT3_SOFT_RESET__SHIFT 0x13
+-#define DCO_SOFT_RESET__FMT4_SOFT_RESET__SHIFT 0x14
+-#define DCO_SOFT_RESET__FMT5_SOFT_RESET__SHIFT 0x15
+-#define DCO_SOFT_RESET__MVP_SOFT_RESET__SHIFT 0x18
+-#define DCO_SOFT_RESET__ABM_SOFT_RESET__SHIFT 0x19
+-#define DCO_SOFT_RESET__DVO_SOFT_RESET__SHIFT 0x1b
+-#define DCO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x00000001L
+-#define DCO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET_MASK 0x00000010L
+-#define DCO_SOFT_RESET__I2S1_SOFT_RESET_MASK 0x00000020L
+-#define DCO_SOFT_RESET__SPDIF1_SOFT_RESET_MASK 0x00000040L
+-#define DCO_SOFT_RESET__DB_CLK_SOFT_RESET_MASK 0x00001000L
+-#define DCO_SOFT_RESET__FMT0_SOFT_RESET_MASK 0x00010000L
+-#define DCO_SOFT_RESET__FMT1_SOFT_RESET_MASK 0x00020000L
+-#define DCO_SOFT_RESET__FMT2_SOFT_RESET_MASK 0x00040000L
+-#define DCO_SOFT_RESET__FMT3_SOFT_RESET_MASK 0x00080000L
+-#define DCO_SOFT_RESET__FMT4_SOFT_RESET_MASK 0x00100000L
+-#define DCO_SOFT_RESET__FMT5_SOFT_RESET_MASK 0x00200000L
+-#define DCO_SOFT_RESET__MVP_SOFT_RESET_MASK 0x01000000L
+-#define DCO_SOFT_RESET__ABM_SOFT_RESET_MASK 0x02000000L
+-#define DCO_SOFT_RESET__DVO_SOFT_RESET_MASK 0x08000000L
+-//DIG_SOFT_RESET
+-#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT 0x0
+-#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT 0x1
+-#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT 0x4
+-#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT 0x5
+-#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT 0x8
+-#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT 0x9
+-#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT 0xc
+-#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT 0xd
+-#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT 0x10
+-#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT 0x11
+-#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT 0x14
+-#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT 0x15
+-#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET__SHIFT 0x18
+-#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET__SHIFT 0x19
+-#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK 0x00000001L
+-#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK 0x00000002L
+-#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK 0x00000010L
+-#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK 0x00000020L
+-#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK 0x00000100L
+-#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK 0x00000200L
+-#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK 0x00001000L
+-#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK 0x00002000L
+-#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK 0x00010000L
+-#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK 0x00020000L
+-#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK 0x00100000L
+-#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK 0x00200000L
+-#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET_MASK 0x01000000L
+-#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET_MASK 0x02000000L
+-//DCO_MEM_PWR_STATUS1
+-#define DCO_MEM_PWR_STATUS1__DPLPA_MEM_PWR_STATE__SHIFT 0x0
+-#define DCO_MEM_PWR_STATUS1__DPLPB_MEM_PWR_STATE__SHIFT 0x1
+-#define DCO_MEM_PWR_STATUS1__HDMILP0_MEM_PWR_STATE__SHIFT 0xa
+-#define DCO_MEM_PWR_STATUS1__HDMILP1_MEM_PWR_STATE__SHIFT 0xc
+-#define DCO_MEM_PWR_STATUS1__DPLPA_MEM_PWR_STATE_MASK 0x00000001L
+-#define DCO_MEM_PWR_STATUS1__DPLPB_MEM_PWR_STATE_MASK 0x00000002L
+-#define DCO_MEM_PWR_STATUS1__HDMILP0_MEM_PWR_STATE_MASK 0x00000C00L
+-#define DCO_MEM_PWR_STATUS1__HDMILP1_MEM_PWR_STATE_MASK 0x00003000L
+-//DISP_INTERRUPT_STATUS_CONTINUE10
+-#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x4
+-#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x5
+-#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xa
+-#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0xb
+-#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT__SHIFT 0xc
+-#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT__SHIFT 0xd
+-#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER2_INTERRUPT__SHIFT 0xe
+-#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER3_INTERRUPT__SHIFT 0xf
+-#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER4_INTERRUPT__SHIFT 0x10
+-#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER5_INTERRUPT__SHIFT 0x11
+-#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER6_INTERRUPT__SHIFT 0x12
+-#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER7_INTERRUPT__SHIFT 0x13
+-#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER_OFF_INTERRUPT__SHIFT 0x14
+-#define DISP_INTERRUPT_STATUS_CONTINUE10__CRTC1_RANGE_TIMING_UPDATE__SHIFT 0x16
+-#define DISP_INTERRUPT_STATUS_CONTINUE10__CRTC2_RANGE_TIMING_UPDATE__SHIFT 0x17
+-#define DISP_INTERRUPT_STATUS_CONTINUE10__CRTC3_RANGE_TIMING_UPDATE__SHIFT 0x18
+-#define DISP_INTERRUPT_STATUS_CONTINUE10__CRTC4_RANGE_TIMING_UPDATE__SHIFT 0x19
+-#define DISP_INTERRUPT_STATUS_CONTINUE10__CRTC5_RANGE_TIMING_UPDATE__SHIFT 0x1a
+-#define DISP_INTERRUPT_STATUS_CONTINUE10__CRTC6_RANGE_TIMING_UPDATE__SHIFT 0x1b
+-#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11__SHIFT 0x1f
+-#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00000010L
+-#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00000020L
+-#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00000400L
+-#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00000800L
+-#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT_MASK 0x00001000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT_MASK 0x00002000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER2_INTERRUPT_MASK 0x00004000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER3_INTERRUPT_MASK 0x00008000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER4_INTERRUPT_MASK 0x00010000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER5_INTERRUPT_MASK 0x00020000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER6_INTERRUPT_MASK 0x00040000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER7_INTERRUPT_MASK 0x00080000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER_OFF_INTERRUPT_MASK 0x00100000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE10__CRTC1_RANGE_TIMING_UPDATE_MASK 0x00400000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE10__CRTC2_RANGE_TIMING_UPDATE_MASK 0x00800000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE10__CRTC3_RANGE_TIMING_UPDATE_MASK 0x01000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE10__CRTC4_RANGE_TIMING_UPDATE_MASK 0x02000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE10__CRTC5_RANGE_TIMING_UPDATE_MASK 0x04000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE10__CRTC6_RANGE_TIMING_UPDATE_MASK 0x08000000L
+-#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11_MASK 0x80000000L
+-//DCO_CLK_CNTL2
+-#define DCO_CLK_CNTL2__DCO_TEST_CLK_SEL__SHIFT 0x0
+-#define DCO_CLK_CNTL2__SCLK_G_AFMTA_GATE_DIS__SHIFT 0x7
+-#define DCO_CLK_CNTL2__SCLK_G_AFMTB_GATE_DIS__SHIFT 0x8
+-#define DCO_CLK_CNTL2__SCLK_G_AFMTC_GATE_DIS__SHIFT 0x9
+-#define DCO_CLK_CNTL2__SCLK_G_AFMTD_GATE_DIS__SHIFT 0xa
+-#define DCO_CLK_CNTL2__SCLK_G_AFMTE_GATE_DIS__SHIFT 0xb
+-#define DCO_CLK_CNTL2__SCLK_G_AFMTF_GATE_DIS__SHIFT 0xc
+-#define DCO_CLK_CNTL2__SCLK_G_AFMTG_GATE_DIS__SHIFT 0xd
+-#define DCO_CLK_CNTL2__SCLK_G_AFMTLPA_GATE_DIS__SHIFT 0xf
+-#define DCO_CLK_CNTL2__SCLK_G_AFMTLPB_GATE_DIS__SHIFT 0x10
+-#define DCO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS__SHIFT 0x11
+-#define DCO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS__SHIFT 0x12
+-#define DCO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS__SHIFT 0x13
+-#define DCO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS__SHIFT 0x14
+-#define DCO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS__SHIFT 0x15
+-#define DCO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS__SHIFT 0x16
+-#define DCO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS__SHIFT 0x17
+-#define DCO_CLK_CNTL2__SYMCLKLPA_FE_G_AFMT_GATE_DIS__SHIFT 0x19
+-#define DCO_CLK_CNTL2__SYMCLKLPB_FE_G_AFMT_GATE_DIS__SHIFT 0x1a
+-#define DCO_CLK_CNTL2__DCO_TEST_CLK_SEL_MASK 0x0000007FL
+-#define DCO_CLK_CNTL2__SCLK_G_AFMTA_GATE_DIS_MASK 0x00000080L
+-#define DCO_CLK_CNTL2__SCLK_G_AFMTB_GATE_DIS_MASK 0x00000100L
+-#define DCO_CLK_CNTL2__SCLK_G_AFMTC_GATE_DIS_MASK 0x00000200L
+-#define DCO_CLK_CNTL2__SCLK_G_AFMTD_GATE_DIS_MASK 0x00000400L
+-#define DCO_CLK_CNTL2__SCLK_G_AFMTE_GATE_DIS_MASK 0x00000800L
+-#define DCO_CLK_CNTL2__SCLK_G_AFMTF_GATE_DIS_MASK 0x00001000L
+-#define DCO_CLK_CNTL2__SCLK_G_AFMTG_GATE_DIS_MASK 0x00002000L
+-#define DCO_CLK_CNTL2__SCLK_G_AFMTLPA_GATE_DIS_MASK 0x00008000L
+-#define DCO_CLK_CNTL2__SCLK_G_AFMTLPB_GATE_DIS_MASK 0x00010000L
+-#define DCO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS_MASK 0x00020000L
+-#define DCO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS_MASK 0x00040000L
+-#define DCO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS_MASK 0x00080000L
+-#define DCO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS_MASK 0x00100000L
+-#define DCO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS_MASK 0x00200000L
+-#define DCO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS_MASK 0x00400000L
+-#define DCO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS_MASK 0x00800000L
+-#define DCO_CLK_CNTL2__SYMCLKLPA_FE_G_AFMT_GATE_DIS_MASK 0x02000000L
+-#define DCO_CLK_CNTL2__SYMCLKLPB_FE_G_AFMT_GATE_DIS_MASK 0x04000000L
+-//DCO_CLK_CNTL3
+-#define DCO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS__SHIFT 0x0
+-#define DCO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS__SHIFT 0x1
+-#define DCO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS__SHIFT 0x2
+-#define DCO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS__SHIFT 0x3
+-#define DCO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS__SHIFT 0x4
+-#define DCO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS__SHIFT 0x5
+-#define DCO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS__SHIFT 0x6
+-#define DCO_CLK_CNTL3__SYMCLKLPA_FE_G_TMDS_GATE_DIS__SHIFT 0x8
+-#define DCO_CLK_CNTL3__SYMCLKLPB_FE_G_TMDS_GATE_DIS__SHIFT 0x9
+-#define DCO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS__SHIFT 0xa
+-#define DCO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS__SHIFT 0xb
+-#define DCO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS__SHIFT 0xc
+-#define DCO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS__SHIFT 0xd
+-#define DCO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS__SHIFT 0xe
+-#define DCO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS__SHIFT 0xf
+-#define DCO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS__SHIFT 0x10
+-#define DCO_CLK_CNTL3__SYMCLKLPA_G_TMDS_GATE_DIS__SHIFT 0x12
+-#define DCO_CLK_CNTL3__SYMCLKLPB_G_TMDS_GATE_DIS__SHIFT 0x13
+-#define DCO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS_MASK 0x00000001L
+-#define DCO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS_MASK 0x00000002L
+-#define DCO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS_MASK 0x00000004L
+-#define DCO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS_MASK 0x00000008L
+-#define DCO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS_MASK 0x00000010L
+-#define DCO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS_MASK 0x00000020L
+-#define DCO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS_MASK 0x00000040L
+-#define DCO_CLK_CNTL3__SYMCLKLPA_FE_G_TMDS_GATE_DIS_MASK 0x00000100L
+-#define DCO_CLK_CNTL3__SYMCLKLPB_FE_G_TMDS_GATE_DIS_MASK 0x00000200L
+-#define DCO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS_MASK 0x00000400L
+-#define DCO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS_MASK 0x00000800L
+-#define DCO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS_MASK 0x00001000L
+-#define DCO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS_MASK 0x00002000L
+-#define DCO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS_MASK 0x00004000L
+-#define DCO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS_MASK 0x00008000L
+-#define DCO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS_MASK 0x00010000L
+-#define DCO_CLK_CNTL3__SYMCLKLPA_G_TMDS_GATE_DIS_MASK 0x00040000L
+-#define DCO_CLK_CNTL3__SYMCLKLPB_G_TMDS_GATE_DIS_MASK 0x00080000L
+-//DCO_HDMI_RXSTATUS_TIMER_CONTROL
+-#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_ENABLE__SHIFT 0x0
+-#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_TYPE__SHIFT 0x4
+-#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_STATUS__SHIFT 0x8
+-#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_MASK__SHIFT 0xc
+-#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_INTERVAL__SHIFT 0x10
+-#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_ENABLE_MASK 0x00000001L
+-#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_TYPE_MASK 0x00000010L
+-#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_STATUS_MASK 0x00000100L
+-#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_MASK_MASK 0x00001000L
+-#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_INTERVAL_MASK 0x0FFF0000L
+-//DCO_PSP_INTERRUPT_STATUS
+-#define DCO_PSP_INTERRUPT_STATUS__DCO_PSP_INTERRUPT_STATUS__SHIFT 0x0
+-#define DCO_PSP_INTERRUPT_STATUS__DCO_PSP_INTERRUPT_MESSAGE__SHIFT 0x1
+-#define DCO_PSP_INTERRUPT_STATUS__DCO_PSP_INTERRUPT_STATUS_MASK 0x00000001L
+-#define DCO_PSP_INTERRUPT_STATUS__DCO_PSP_INTERRUPT_MESSAGE_MASK 0xFFFFFFFEL
+-//DCO_PSP_INTERRUPT_CLEAR
+-#define DCO_PSP_INTERRUPT_CLEAR__DCO_PSP_INTERRUPT_CLEAR__SHIFT 0x0
+-#define DCO_PSP_INTERRUPT_CLEAR__DCO_PSP_INTERRUPT_CLEAR_MASK 0x00000001L
+-//DCO_GENERIC_INTERRUPT_MESSAGE
+-#define DCO_GENERIC_INTERRUPT_MESSAGE__DCO_GENERIC_INTERRUPT_STATUS__SHIFT 0x0
+-#define DCO_GENERIC_INTERRUPT_MESSAGE__DCO_GENERIC_INTERRUPT_MESSAGE__SHIFT 0x1
+-#define DCO_GENERIC_INTERRUPT_MESSAGE__DCO_GENERIC_INTERRUPT_STATUS_MASK 0x00000001L
+-#define DCO_GENERIC_INTERRUPT_MESSAGE__DCO_GENERIC_INTERRUPT_MESSAGE_MASK 0xFFFFFFFEL
+-//DCO_GENERIC_INTERRUPT_CLEAR
+-#define DCO_GENERIC_INTERRUPT_CLEAR__DCO_GENERIC_INTERRUPT_CLEAR__SHIFT 0x0
+-#define DCO_GENERIC_INTERRUPT_CLEAR__DCO_GENERIC_INTERRUPT_CLEAR_MASK 0x00000001L
+-//FMT_MEMORY0_CONTROL
+-#define FMT_MEMORY0_CONTROL__FMT420_MEM0_SOURCE_SEL__SHIFT 0x0
+-#define FMT_MEMORY0_CONTROL__FMT420_MEM0_PWR_FORCE__SHIFT 0x4
+-#define FMT_MEMORY0_CONTROL__FMT420_MEM0_PWR_DIS__SHIFT 0x8
+-#define FMT_MEMORY0_CONTROL__FMT420_MEM0_PWR_STATE__SHIFT 0xc
+-#define FMT_MEMORY0_CONTROL__FMT420_MEM0_SOURCE_SEL_MASK 0x00000007L
+-#define FMT_MEMORY0_CONTROL__FMT420_MEM0_PWR_FORCE_MASK 0x00000030L
+-#define FMT_MEMORY0_CONTROL__FMT420_MEM0_PWR_DIS_MASK 0x00000100L
+-#define FMT_MEMORY0_CONTROL__FMT420_MEM0_PWR_STATE_MASK 0x00003000L
+-//FMT_MEMORY1_CONTROL
+-#define FMT_MEMORY1_CONTROL__FMT420_MEM1_SOURCE_SEL__SHIFT 0x0
+-#define FMT_MEMORY1_CONTROL__FMT420_MEM1_PWR_FORCE__SHIFT 0x4
+-#define FMT_MEMORY1_CONTROL__FMT420_MEM1_PWR_DIS__SHIFT 0x8
+-#define FMT_MEMORY1_CONTROL__FMT420_MEM1_PWR_STATE__SHIFT 0xc
+-#define FMT_MEMORY1_CONTROL__FMT420_MEM1_SOURCE_SEL_MASK 0x00000007L
+-#define FMT_MEMORY1_CONTROL__FMT420_MEM1_PWR_FORCE_MASK 0x00000030L
+-#define FMT_MEMORY1_CONTROL__FMT420_MEM1_PWR_DIS_MASK 0x00000100L
+-#define FMT_MEMORY1_CONTROL__FMT420_MEM1_PWR_STATE_MASK 0x00003000L
+-//FMT_MEMORY2_CONTROL
+-#define FMT_MEMORY2_CONTROL__FMT420_MEM2_SOURCE_SEL__SHIFT 0x0
+-#define FMT_MEMORY2_CONTROL__FMT420_MEM2_PWR_FORCE__SHIFT 0x4
+-#define FMT_MEMORY2_CONTROL__FMT420_MEM2_PWR_DIS__SHIFT 0x8
+-#define FMT_MEMORY2_CONTROL__FMT420_MEM2_PWR_STATE__SHIFT 0xc
+-#define FMT_MEMORY2_CONTROL__FMT420_MEM2_SOURCE_SEL_MASK 0x00000007L
+-#define FMT_MEMORY2_CONTROL__FMT420_MEM2_PWR_FORCE_MASK 0x00000030L
+-#define FMT_MEMORY2_CONTROL__FMT420_MEM2_PWR_DIS_MASK 0x00000100L
+-#define FMT_MEMORY2_CONTROL__FMT420_MEM2_PWR_STATE_MASK 0x00003000L
+-//FMT_MEMORY3_CONTROL
+-#define FMT_MEMORY3_CONTROL__FMT420_MEM3_SOURCE_SEL__SHIFT 0x0
+-#define FMT_MEMORY3_CONTROL__FMT420_MEM3_PWR_FORCE__SHIFT 0x4
+-#define FMT_MEMORY3_CONTROL__FMT420_MEM3_PWR_DIS__SHIFT 0x8
+-#define FMT_MEMORY3_CONTROL__FMT420_MEM3_PWR_STATE__SHIFT 0xc
+-#define FMT_MEMORY3_CONTROL__FMT420_MEM3_SOURCE_SEL_MASK 0x00000007L
+-#define FMT_MEMORY3_CONTROL__FMT420_MEM3_PWR_FORCE_MASK 0x00000030L
+-#define FMT_MEMORY3_CONTROL__FMT420_MEM3_PWR_DIS_MASK 0x00000100L
+-#define FMT_MEMORY3_CONTROL__FMT420_MEM3_PWR_STATE_MASK 0x00003000L
+-//FMT_MEMORY4_CONTROL
+-#define FMT_MEMORY4_CONTROL__FMT420_MEM4_SOURCE_SEL__SHIFT 0x0
+-#define FMT_MEMORY4_CONTROL__FMT420_MEM4_PWR_FORCE__SHIFT 0x4
+-#define FMT_MEMORY4_CONTROL__FMT420_MEM4_PWR_DIS__SHIFT 0x8
+-#define FMT_MEMORY4_CONTROL__FMT420_MEM4_PWR_STATE__SHIFT 0xc
+-#define FMT_MEMORY4_CONTROL__FMT420_MEM4_SOURCE_SEL_MASK 0x00000007L
+-#define FMT_MEMORY4_CONTROL__FMT420_MEM4_PWR_FORCE_MASK 0x00000030L
+-#define FMT_MEMORY4_CONTROL__FMT420_MEM4_PWR_DIS_MASK 0x00000100L
+-#define FMT_MEMORY4_CONTROL__FMT420_MEM4_PWR_STATE_MASK 0x00003000L
+-//FMT_MEMORY5_CONTROL
+-#define FMT_MEMORY5_CONTROL__FMT420_MEM5_SOURCE_SEL__SHIFT 0x0
+-#define FMT_MEMORY5_CONTROL__FMT420_MEM5_PWR_FORCE__SHIFT 0x4
+-#define FMT_MEMORY5_CONTROL__FMT420_MEM5_PWR_DIS__SHIFT 0x8
+-#define FMT_MEMORY5_CONTROL__FMT420_MEM5_PWR_STATE__SHIFT 0xc
+-#define FMT_MEMORY5_CONTROL__FMT420_MEM5_SOURCE_SEL_MASK 0x00000007L
+-#define FMT_MEMORY5_CONTROL__FMT420_MEM5_PWR_FORCE_MASK 0x00000030L
+-#define FMT_MEMORY5_CONTROL__FMT420_MEM5_PWR_DIS_MASK 0x00000100L
+-#define FMT_MEMORY5_CONTROL__FMT420_MEM5_PWR_STATE_MASK 0x00003000L
+-//DISP_INTERRUPT_STATUS_CONTINUE11
+-#define DISP_INTERRUPT_STATUS_CONTINUE11__DCP0_xdma_vsync_flip_timeout_interrupt__SHIFT 0x0
+-#define DISP_INTERRUPT_STATUS_CONTINUE11__DCP1_xdma_vsync_flip_timeout_interrupt__SHIFT 0x1
+-#define DISP_INTERRUPT_STATUS_CONTINUE11__DCP2_xdma_vsync_flip_timeout_interrupt__SHIFT 0x2
+-#define DISP_INTERRUPT_STATUS_CONTINUE11__DCP3_xdma_vsync_flip_timeout_interrupt__SHIFT 0x3
+-#define DISP_INTERRUPT_STATUS_CONTINUE11__DCP4_xdma_vsync_flip_timeout_interrupt__SHIFT 0x4
+-#define DISP_INTERRUPT_STATUS_CONTINUE11__DCP5_xdma_vsync_flip_timeout_interrupt__SHIFT 0x5
+-#define DISP_INTERRUPT_STATUS_CONTINUE11__DCP0_xdma_vsync_flip_timeout_interrupt_MASK 0x00000001L
+-#define DISP_INTERRUPT_STATUS_CONTINUE11__DCP1_xdma_vsync_flip_timeout_interrupt_MASK 0x00000002L
+-#define DISP_INTERRUPT_STATUS_CONTINUE11__DCP2_xdma_vsync_flip_timeout_interrupt_MASK 0x00000004L
+-#define DISP_INTERRUPT_STATUS_CONTINUE11__DCP3_xdma_vsync_flip_timeout_interrupt_MASK 0x00000008L
+-#define DISP_INTERRUPT_STATUS_CONTINUE11__DCP4_xdma_vsync_flip_timeout_interrupt_MASK 0x00000010L
+-#define DISP_INTERRUPT_STATUS_CONTINUE11__DCP5_xdma_vsync_flip_timeout_interrupt_MASK 0x00000020L
+-//DC_GENERICA
+-#define DC_GENERICA__GENERICA_EN__SHIFT 0x0
+-#define DC_GENERICA__GENERICA_SEL__SHIFT 0x7
+-#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc
+-#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10
+-#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14
+-#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18
+-#define DC_GENERICA__GENERICA_EN_MASK 0x00000001L
+-#define DC_GENERICA__GENERICA_SEL_MASK 0x00000F80L
+-#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK 0x0000F000L
+-#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK 0x000F0000L
+-#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x00F00000L
+-#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x0F000000L
+-//DC_GENERICB
+-#define DC_GENERICB__GENERICB_EN__SHIFT 0x0
+-#define DC_GENERICB__GENERICB_SEL__SHIFT 0x8
+-#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc
+-#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10
+-#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14
+-#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18
+-#define DC_GENERICB__GENERICB_EN_MASK 0x00000001L
+-#define DC_GENERICB__GENERICB_SEL_MASK 0x00000F00L
+-#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK 0x0000F000L
+-#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK 0x000F0000L
+-#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x00F00000L
+-#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x0F000000L
+-//DC_PAD_EXTERN_SIG
+-#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL__SHIFT 0x0
+-#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS__SHIFT 0x4
+-#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL_MASK 0x0000000FL
+-#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS_MASK 0x00000030L
+-//DC_REF_CLK_CNTL
+-#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0
+-#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x8
+-#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x00000003L
+-#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x00000300L
+-//DC_GPIO_DEBUG
+-#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG__SHIFT 0x0
+-#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG__SHIFT 0x8
+-#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL__SHIFT 0x10
+-#define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN__SHIFT 0x11
+-#define DC_GPIO_DEBUG__DPRX_LOOPBACK_ENABLE__SHIFT 0x1f
+-#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG_MASK 0x00000001L
+-#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG_MASK 0x00000300L
+-#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_MASK 0x00010000L
+-#define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN_MASK 0x00020000L
+-#define DC_GPIO_DEBUG__DPRX_LOOPBACK_ENABLE_MASK 0x80000000L
+-//UNIPHYA_LINK_CNTL
+-#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
+-#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
+-#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+-#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
+-#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
+-#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
+-#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
+-#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
+-#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
+-#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L
+-#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L
+-#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L
+-#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
+-#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
+-#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
+-#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
+-#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L
+-#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L
+-//UNIPHYA_CHANNEL_XBAR_CNTL
+-#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+-#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+-#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+-#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+-#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
+-#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
+-#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
+-#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
+-#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
+-#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L
+-//UNIPHYB_LINK_CNTL
+-#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
+-#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
+-#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+-#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
+-#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
+-#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
+-#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
+-#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
+-#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
+-#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L
+-#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L
+-#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L
+-#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
+-#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
+-#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
+-#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
+-#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L
+-#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L
+-//UNIPHYB_CHANNEL_XBAR_CNTL
+-#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+-#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+-#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+-#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+-#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
+-#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
+-#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
+-#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
+-#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
+-#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L
+-//UNIPHYC_LINK_CNTL
+-#define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
+-#define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
+-#define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+-#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
+-#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
+-#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
+-#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
+-#define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
+-#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
+-#define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L
+-#define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L
+-#define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L
+-#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
+-#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
+-#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
+-#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
+-#define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L
+-#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L
+-//UNIPHYC_CHANNEL_XBAR_CNTL
+-#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+-#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+-#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+-#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+-#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
+-#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
+-#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
+-#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
+-#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
+-#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L
+-//UNIPHYD_LINK_CNTL
+-#define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
+-#define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
+-#define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+-#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
+-#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
+-#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
+-#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
+-#define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
+-#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
+-#define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L
+-#define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L
+-#define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L
+-#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
+-#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
+-#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
+-#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
+-#define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L
+-#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L
+-//UNIPHYD_CHANNEL_XBAR_CNTL
+-#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+-#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+-#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+-#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+-#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
+-#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
+-#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
+-#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
+-#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
+-#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L
+-//UNIPHYE_LINK_CNTL
+-#define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
+-#define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
+-#define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+-#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
+-#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
+-#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
+-#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
+-#define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
+-#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
+-#define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L
+-#define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L
+-#define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L
+-#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
+-#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
+-#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
+-#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
+-#define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L
+-#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L
+-//UNIPHYE_CHANNEL_XBAR_CNTL
+-#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+-#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+-#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+-#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+-#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
+-#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
+-#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
+-#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
+-#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
+-#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L
+-//UNIPHYF_LINK_CNTL
+-#define UNIPHYF_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
+-#define UNIPHYF_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
+-#define UNIPHYF_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+-#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
+-#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
+-#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
+-#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
+-#define UNIPHYF_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
+-#define UNIPHYF_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
+-#define UNIPHYF_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L
+-#define UNIPHYF_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L
+-#define UNIPHYF_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L
+-#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
+-#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
+-#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
+-#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
+-#define UNIPHYF_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L
+-#define UNIPHYF_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L
+-//UNIPHYF_CHANNEL_XBAR_CNTL
+-#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+-#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+-#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+-#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+-#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
+-#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
+-#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
+-#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
+-#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
+-#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L
+-//UNIPHYG_LINK_CNTL
+-#define UNIPHYG_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
+-#define UNIPHYG_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
+-#define UNIPHYG_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+-#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
+-#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
+-#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
+-#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
+-#define UNIPHYG_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
+-#define UNIPHYG_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
+-#define UNIPHYG_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L
+-#define UNIPHYG_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L
+-#define UNIPHYG_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L
+-#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
+-#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
+-#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
+-#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
+-#define UNIPHYG_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L
+-#define UNIPHYG_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L
+-//UNIPHYG_CHANNEL_XBAR_CNTL
+-#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+-#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+-#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+-#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+-#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
+-#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
+-#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
+-#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
+-#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
+-#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L
+-//DCIO_WRCMD_DELAY
+-#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT 0x0
+-#define DCIO_WRCMD_DELAY__DAC_DELAY__SHIFT 0x4
+-#define DCIO_WRCMD_DELAY__DPHY_DELAY__SHIFT 0x8
+-#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY__SHIFT 0xc
+-#define DCIO_WRCMD_DELAY__ZCAL_DELAY__SHIFT 0x10
+-#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK 0x0000000FL
+-#define DCIO_WRCMD_DELAY__DAC_DELAY_MASK 0x000000F0L
+-#define DCIO_WRCMD_DELAY__DPHY_DELAY_MASK 0x00000F00L
+-#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY_MASK 0x0000F000L
+-#define DCIO_WRCMD_DELAY__ZCAL_DELAY_MASK 0x000F0000L
+-//DC_DVODATA_CONFIG
+-#define DC_DVODATA_CONFIG__VIP_MUX_EN__SHIFT 0x13
+-#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN__SHIFT 0x14
+-#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN__SHIFT 0x15
+-#define DC_DVODATA_CONFIG__VIP_MUX_EN_MASK 0x00080000L
+-#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN_MASK 0x00100000L
+-#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN_MASK 0x00200000L
+-//LVTMA_PWRSEQ_CNTL
+-#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN__SHIFT 0x0
+-#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN__SHIFT 0x1
+-#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE__SHIFT 0x4
+-#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT 0x8
+-#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD__SHIFT 0x9
+-#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT 0xa
+-#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT 0x10
+-#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x11
+-#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT 0x12
+-#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT 0x18
+-#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT 0x19
+-#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL__SHIFT 0x1a
+-#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN_MASK 0x00000001L
+-#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN_MASK 0x00000002L
+-#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE_MASK 0x00000010L
+-#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK 0x00000100L
+-#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD_MASK 0x00000200L
+-#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK 0x00000400L
+-#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_MASK 0x00010000L
+-#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD_MASK 0x00020000L
+-#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL_MASK 0x00040000L
+-#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_MASK 0x01000000L
+-#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD_MASK 0x02000000L
+-#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL_MASK 0x04000000L
+-//LVTMA_PWRSEQ_STATE
+-#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT 0x0
+-#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON__SHIFT 0x1
+-#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN__SHIFT 0x2
+-#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON__SHIFT 0x3
+-#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE__SHIFT 0x4
+-#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT 0x8
+-#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R_MASK 0x00000001L
+-#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK 0x00000002L
+-#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN_MASK 0x00000004L
+-#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON_MASK 0x00000008L
+-#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE_MASK 0x00000010L
+-#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE_MASK 0x00000F00L
+-//LVTMA_PWRSEQ_REF_DIV
+-#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV__SHIFT 0x0
+-#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT 0x10
+-#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV_MASK 0x00000FFFL
+-#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xFFFF0000L
+-//LVTMA_PWRSEQ_DELAY1
+-#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1__SHIFT 0x0
+-#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2__SHIFT 0x8
+-#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1__SHIFT 0x10
+-#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2__SHIFT 0x18
+-#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1_MASK 0x000000FFL
+-#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2_MASK 0x0000FF00L
+-#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1_MASK 0x00FF0000L
+-#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2_MASK 0xFF000000L
+-//LVTMA_PWRSEQ_DELAY2
+-#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH__SHIFT 0x0
+-#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3__SHIFT 0x8
+-#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3__SHIFT 0x10
+-#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN__SHIFT 0x18
+-#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH_MASK 0x000000FFL
+-#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3_MASK 0x0000FF00L
+-#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3_MASK 0x00FF0000L
+-#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN_MASK 0x01000000L
+-//BL_PWM_CNTL
+-#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT 0x0
+-#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT 0x1e
+-#define BL_PWM_CNTL__BL_PWM_EN__SHIFT 0x1f
+-#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK 0x0000FFFFL
+-#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK 0x40000000L
+-#define BL_PWM_CNTL__BL_PWM_EN_MASK 0x80000000L
+-//BL_PWM_CNTL2
+-#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x0
+-#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT 0x1e
+-#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__SHIFT 0x1f
+-#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0x0000FFFFL
+-#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK 0x40000000L
+-#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_MASK 0x80000000L
+-//BL_PWM_PERIOD_CNTL
+-#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT 0x0
+-#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT 0x10
+-#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0x0000FFFFL
+-#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK 0x000F0000L
+-//BL_PWM_GRP1_REG_LOCK
+-#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT 0x0
+-#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT 0x8
+-#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT 0x10
+-#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL__SHIFT 0x11
+-#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT 0x18
+-#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f
+-#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK 0x00000001L
+-#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK 0x00000100L
+-#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK 0x00010000L
+-#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL_MASK 0x000E0000L
+-#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L
+-#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L
+-//DCIO_GSL_GENLK_PAD_CNTL
+-#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL__SHIFT 0x0
+-#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL__SHIFT 0x4
+-#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x8
+-#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL__SHIFT 0x10
+-#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL__SHIFT 0x14
+-#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x18
+-#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL_MASK 0x00000003L
+-#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL_MASK 0x00000030L
+-#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x00000300L
+-#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL_MASK 0x00030000L
+-#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL_MASK 0x00300000L
+-#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x03000000L
+-//DCIO_GSL_SWAPLOCK_PAD_CNTL
+-#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL__SHIFT 0x0
+-#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL__SHIFT 0x4
+-#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x8
+-#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL__SHIFT 0x10
+-#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL__SHIFT 0x14
+-#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x18
+-#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL_MASK 0x00000003L
+-#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL_MASK 0x00000030L
+-#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x00000300L
+-#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL_MASK 0x00030000L
+-#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL_MASK 0x00300000L
+-#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x03000000L
+-//DCIO_GSL0_CNTL
+-#define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL__SHIFT 0x0
+-#define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL__SHIFT 0x8
+-#define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL__SHIFT 0x10
+-#define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL_MASK 0x00000007L
+-#define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL_MASK 0x00000700L
+-#define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL_MASK 0x00070000L
+-//DCIO_GSL1_CNTL
+-#define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL__SHIFT 0x0
+-#define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL__SHIFT 0x8
+-#define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL__SHIFT 0x10
+-#define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL_MASK 0x00000007L
+-#define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL_MASK 0x00000700L
+-#define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL_MASK 0x00070000L
+-//DCIO_GSL2_CNTL
+-#define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL__SHIFT 0x0
+-#define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL__SHIFT 0x8
+-#define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL__SHIFT 0x10
+-#define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL_MASK 0x00000007L
+-#define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL_MASK 0x00000700L
+-#define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL_MASK 0x00070000L
+-//DC_GPU_TIMER_START_POSITION_V_UPDATE
+-#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT 0x0
+-#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT 0x4
+-#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT 0x8
+-#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT 0xc
+-#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT 0x10
+-#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT 0x14
+-#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK 0x00000007L
+-#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK 0x00000070L
+-#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK 0x00000700L
+-#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK 0x00007000L
+-#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK 0x00070000L
+-#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK 0x00700000L
+-//DC_GPU_TIMER_START_POSITION_P_FLIP
+-#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP__SHIFT 0x0
+-#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP__SHIFT 0x4
+-#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP__SHIFT 0x8
+-#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP__SHIFT 0xc
+-#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP__SHIFT 0x10
+-#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP__SHIFT 0x14
+-#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_DCFEV0_P_FLIP__SHIFT 0x17
+-#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_DCFEV1_P_FLIP__SHIFT 0x1a
+-#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP_MASK 0x00000007L
+-#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP_MASK 0x00000070L
+-#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP_MASK 0x00000700L
+-#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP_MASK 0x00007000L
+-#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP_MASK 0x00070000L
+-#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP_MASK 0x00700000L
+-#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_DCFEV0_P_FLIP_MASK 0x03800000L
+-#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_DCFEV1_P_FLIP_MASK 0x1C000000L
+-//DC_GPU_TIMER_READ
+-#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x0
+-#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK 0xFFFFFFFFL
+-//DC_GPU_TIMER_READ_CNTL
+-#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT 0x0
+-#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT 0x8
+-#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT 0xb
+-#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT 0xe
+-#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT 0x11
+-#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT 0x14
+-#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT 0x17
+-#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK 0x0000003FL
+-#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK 0x00000700L
+-#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK 0x00003800L
+-#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK 0x0001C000L
+-#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK 0x000E0000L
+-#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK 0x00700000L
+-#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK 0x03800000L
+-//DCIO_CLOCK_CNTL
+-#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT 0x0
+-#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT 0x5
+-#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK 0x0000001FL
+-#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK 0x00000020L
+-//DCO_DCFE_EXT_VSYNC_CNTL
+-#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX__SHIFT 0x0
+-#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX__SHIFT 0x4
+-#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX__SHIFT 0x8
+-#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX__SHIFT 0xc
+-#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX__SHIFT 0x10
+-#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX__SHIFT 0x14
+-#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK__SHIFT 0x18
+-#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK__SHIFT 0x1c
+-#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL__SHIFT 0x1f
+-#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX_MASK 0x00000007L
+-#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX_MASK 0x00000070L
+-#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX_MASK 0x00000700L
+-#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX_MASK 0x00007000L
+-#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX_MASK 0x00070000L
+-#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX_MASK 0x00700000L
+-#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK_MASK 0x07000000L
+-#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK_MASK 0x70000000L
+-#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL_MASK 0x80000000L
+-//DCIO_SOFT_RESET
+-#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT 0x0
+-#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT 0x1
+-#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT 0x2
+-#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT 0x3
+-#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT 0x4
+-#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT 0x5
+-#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT 0x6
+-#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT 0x7
+-#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT 0x8
+-#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT 0x9
+-#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT 0xa
+-#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT 0xb
+-#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT 0xc
+-#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT 0xd
+-#define DCIO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x10
+-#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET__SHIFT 0x14
+-#define DCIO_SOFT_RESET__DPHY_SOFT_RESET__SHIFT 0x18
+-#define DCIO_SOFT_RESET__ZCAL_SOFT_RESET__SHIFT 0x1a
+-#define DCIO_SOFT_RESET__UNIPHYLPA_SOFT_RESET__SHIFT 0x1c
+-#define DCIO_SOFT_RESET__DSYNCLPA_SOFT_RESET__SHIFT 0x1d
+-#define DCIO_SOFT_RESET__UNIPHYLPB_SOFT_RESET__SHIFT 0x1e
+-#define DCIO_SOFT_RESET__DSYNCLPB_SOFT_RESET__SHIFT 0x1f
+-#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK 0x00000001L
+-#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET_MASK 0x00000002L
+-#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK 0x00000004L
+-#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET_MASK 0x00000008L
+-#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK 0x00000010L
+-#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET_MASK 0x00000020L
+-#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK 0x00000040L
+-#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET_MASK 0x00000080L
+-#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK 0x00000100L
+-#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET_MASK 0x00000200L
+-#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK 0x00000400L
+-#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET_MASK 0x00000800L
+-#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK 0x00001000L
+-#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET_MASK 0x00002000L
+-#define DCIO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x00010000L
+-#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET_MASK 0x00100000L
+-#define DCIO_SOFT_RESET__DPHY_SOFT_RESET_MASK 0x01000000L
+-#define DCIO_SOFT_RESET__ZCAL_SOFT_RESET_MASK 0x04000000L
+-#define DCIO_SOFT_RESET__UNIPHYLPA_SOFT_RESET_MASK 0x10000000L
+-#define DCIO_SOFT_RESET__DSYNCLPA_SOFT_RESET_MASK 0x20000000L
+-#define DCIO_SOFT_RESET__UNIPHYLPB_SOFT_RESET_MASK 0x40000000L
+-#define DCIO_SOFT_RESET__DSYNCLPB_SOFT_RESET_MASK 0x80000000L
+-//DCIO_DPHY_SEL
+-#define DCIO_DPHY_SEL__DPHY_LANE0_SEL__SHIFT 0x0
+-#define DCIO_DPHY_SEL__DPHY_LANE1_SEL__SHIFT 0x2
+-#define DCIO_DPHY_SEL__DPHY_LANE2_SEL__SHIFT 0x4
+-#define DCIO_DPHY_SEL__DPHY_LANE3_SEL__SHIFT 0x6
+-#define DCIO_DPHY_SEL__DPHY_LANE0_SEL_MASK 0x00000003L
+-#define DCIO_DPHY_SEL__DPHY_LANE1_SEL_MASK 0x0000000CL
+-#define DCIO_DPHY_SEL__DPHY_LANE2_SEL_MASK 0x00000030L
+-#define DCIO_DPHY_SEL__DPHY_LANE3_SEL_MASK 0x000000C0L
+-//UNIPHY_IMPCAL_LINKA
+-#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA__SHIFT 0x0
+-#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA__SHIFT 0x8
+-#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA__SHIFT 0x9
+-#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK__SHIFT 0xa
+-#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA__SHIFT 0x10
+-#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA__SHIFT 0x14
+-#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA__SHIFT 0x18
+-#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA__SHIFT 0x1c
+-#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA__SHIFT 0x1e
+-#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA_MASK 0x00000001L
+-#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA_MASK 0x00000100L
+-#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_MASK 0x00000200L
+-#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK_MASK 0x00000400L
+-#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA_MASK 0x000F0000L
+-#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA_MASK 0x00F00000L
+-#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA_MASK 0x0F000000L
+-#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA_MASK 0x10000000L
+-#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA_MASK 0x40000000L
+-//UNIPHY_IMPCAL_LINKB
+-#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB__SHIFT 0x0
+-#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB__SHIFT 0x8
+-#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB__SHIFT 0x9
+-#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK__SHIFT 0xa
+-#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB__SHIFT 0x10
+-#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB__SHIFT 0x14
+-#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB__SHIFT 0x18
+-#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB__SHIFT 0x1c
+-#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB__SHIFT 0x1e
+-#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB_MASK 0x00000001L
+-#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB_MASK 0x00000100L
+-#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_MASK 0x00000200L
+-#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK_MASK 0x00000400L
+-#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB_MASK 0x000F0000L
+-#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB_MASK 0x00F00000L
+-#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB_MASK 0x0F000000L
+-#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB_MASK 0x10000000L
+-#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB_MASK 0x40000000L
+-//UNIPHY_IMPCAL_PERIOD
+-#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD__SHIFT 0x0
+-#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD_MASK 0xFFFFFFFFL
+-//AUXP_IMPCAL
+-#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE__SHIFT 0x0
+-#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT__SHIFT 0x8
+-#define AUXP_IMPCAL__AUXP_CALOUT_ERROR__SHIFT 0x9
+-#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK__SHIFT 0xa
+-#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE__SHIFT 0x10
+-#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY__SHIFT 0x14
+-#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE__SHIFT 0x18
+-#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c
+-#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE_MASK 0x00000001L
+-#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT_MASK 0x00000100L
+-#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_MASK 0x00000200L
+-#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK_MASK 0x00000400L
+-#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE_MASK 0x000F0000L
+-#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY_MASK 0x00F00000L
+-#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_MASK 0x0F000000L
+-#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000L
+-//AUXN_IMPCAL
+-#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE__SHIFT 0x0
+-#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT__SHIFT 0x8
+-#define AUXN_IMPCAL__AUXN_CALOUT_ERROR__SHIFT 0x9
+-#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK__SHIFT 0xa
+-#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE__SHIFT 0x10
+-#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY__SHIFT 0x14
+-#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE__SHIFT 0x18
+-#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c
+-#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE_MASK 0x00000001L
+-#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT_MASK 0x00000100L
+-#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_MASK 0x00000200L
+-#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK_MASK 0x00000400L
+-#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE_MASK 0x000F0000L
+-#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY_MASK 0x00F00000L
+-#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_MASK 0x0F000000L
+-#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000L
+-//DCIO_IMPCAL_CNTL
+-#define DCIO_IMPCAL_CNTL__CALR_CNTL_OVERRIDE__SHIFT 0x0
+-#define DCIO_IMPCAL_CNTL__IMPCAL_SOFT_RESET__SHIFT 0x5
+-#define DCIO_IMPCAL_CNTL__IMPCAL_STATUS__SHIFT 0x8
+-#define DCIO_IMPCAL_CNTL__IMPCAL_ARB_STATE__SHIFT 0xc
+-#define DCIO_IMPCAL_CNTL__AUX_IMPCAL_INTERVAL__SHIFT 0xf
+-#define DCIO_IMPCAL_CNTL__CALR_CNTL_OVERRIDE_MASK 0x0000000FL
+-#define DCIO_IMPCAL_CNTL__IMPCAL_SOFT_RESET_MASK 0x00000020L
+-#define DCIO_IMPCAL_CNTL__IMPCAL_STATUS_MASK 0x00000300L
+-#define DCIO_IMPCAL_CNTL__IMPCAL_ARB_STATE_MASK 0x00007000L
+-#define DCIO_IMPCAL_CNTL__AUX_IMPCAL_INTERVAL_MASK 0x00078000L
+-//UNIPHY_IMPCAL_PSW_AB
+-#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA__SHIFT 0x0
+-#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB__SHIFT 0x10
+-#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA_MASK 0x00007FFFL
+-#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB_MASK 0x7FFF0000L
+-//UNIPHY_IMPCAL_LINKC
+-#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC__SHIFT 0x0
+-#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC__SHIFT 0x8
+-#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC__SHIFT 0x9
+-#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK__SHIFT 0xa
+-#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC__SHIFT 0x10
+-#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC__SHIFT 0x14
+-#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC__SHIFT 0x18
+-#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC__SHIFT 0x1c
+-#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC__SHIFT 0x1e
+-#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC_MASK 0x00000001L
+-#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC_MASK 0x00000100L
+-#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_MASK 0x00000200L
+-#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK_MASK 0x00000400L
+-#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC_MASK 0x000F0000L
+-#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC_MASK 0x00F00000L
+-#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC_MASK 0x0F000000L
+-#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC_MASK 0x10000000L
+-#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC_MASK 0x40000000L
+-//UNIPHY_IMPCAL_LINKD
+-#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD__SHIFT 0x0
+-#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD__SHIFT 0x8
+-#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD__SHIFT 0x9
+-#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK__SHIFT 0xa
+-#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD__SHIFT 0x10
+-#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD__SHIFT 0x14
+-#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD__SHIFT 0x18
+-#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD__SHIFT 0x1c
+-#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD__SHIFT 0x1e
+-#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD_MASK 0x00000001L
+-#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD_MASK 0x00000100L
+-#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_MASK 0x00000200L
+-#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK_MASK 0x00000400L
+-#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD_MASK 0x000F0000L
+-#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD_MASK 0x00F00000L
+-#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD_MASK 0x0F000000L
+-#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD_MASK 0x10000000L
+-#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD_MASK 0x40000000L
+-//DCIO_IMPCAL_CNTL_CD
+-#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE__SHIFT 0x0
+-#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET__SHIFT 0x5
+-#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS__SHIFT 0x8
+-#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE__SHIFT 0xc
+-#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE_MASK 0x0000000FL
+-#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET_MASK 0x00000020L
+-#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS_MASK 0x00000300L
+-#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE_MASK 0x00007000L
+-//UNIPHY_IMPCAL_PSW_CD
+-#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC__SHIFT 0x0
+-#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD__SHIFT 0x10
+-#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC_MASK 0x00007FFFL
+-#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD_MASK 0x7FFF0000L
+-//UNIPHY_IMPCAL_LINKE
+-#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE__SHIFT 0x0
+-#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE__SHIFT 0x8
+-#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE__SHIFT 0x9
+-#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK__SHIFT 0xa
+-#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE__SHIFT 0x10
+-#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE__SHIFT 0x14
+-#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE__SHIFT 0x18
+-#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE__SHIFT 0x1c
+-#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE__SHIFT 0x1e
+-#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE_MASK 0x00000001L
+-#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE_MASK 0x00000100L
+-#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_MASK 0x00000200L
+-#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK_MASK 0x00000400L
+-#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE_MASK 0x000F0000L
+-#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE_MASK 0x00F00000L
+-#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE_MASK 0x0F000000L
+-#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE_MASK 0x10000000L
+-#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE_MASK 0x40000000L
+-//UNIPHY_IMPCAL_LINKF
+-#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF__SHIFT 0x0
+-#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF__SHIFT 0x8
+-#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF__SHIFT 0x9
+-#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK__SHIFT 0xa
+-#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF__SHIFT 0x10
+-#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF__SHIFT 0x14
+-#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF__SHIFT 0x18
+-#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF__SHIFT 0x1c
+-#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF__SHIFT 0x1e
+-#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF_MASK 0x00000001L
+-#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF_MASK 0x00000100L
+-#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_MASK 0x00000200L
+-#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK_MASK 0x00000400L
+-#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF_MASK 0x000F0000L
+-#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF_MASK 0x00F00000L
+-#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF_MASK 0x0F000000L
+-#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF_MASK 0x10000000L
+-#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF_MASK 0x40000000L
+-//DCIO_IMPCAL_CNTL_EF
+-#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE__SHIFT 0x0
+-#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET__SHIFT 0x5
+-#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS__SHIFT 0x8
+-#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE__SHIFT 0xc
+-#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE_MASK 0x0000000FL
+-#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET_MASK 0x00000020L
+-#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS_MASK 0x00000300L
+-#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE_MASK 0x00007000L
+-//UNIPHY_IMPCAL_PSW_EF
+-#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE__SHIFT 0x0
+-#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF__SHIFT 0x10
+-#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE_MASK 0x00007FFFL
+-#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF_MASK 0x7FFF0000L
+-//UNIPHYLPA_LINK_CNTL
+-#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_PFREQCHG__SHIFT 0x0
+-#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_PIXVLD_RESET__SHIFT 0x4
+-#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+-#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL0_INVERT__SHIFT 0xc
+-#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL1_INVERT__SHIFT 0xd
+-#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL2_INVERT__SHIFT 0xe
+-#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL3_INVERT__SHIFT 0xf
+-#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_LANE_STAGGER_DELAY__SHIFT 0x14
+-#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_LINK_ENABLE_HPD_MASK__SHIFT 0x18
+-#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_PFREQCHG_MASK 0x00000001L
+-#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_PIXVLD_RESET_MASK 0x00000010L
+-#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L
+-#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL0_INVERT_MASK 0x00001000L
+-#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL1_INVERT_MASK 0x00002000L
+-#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL2_INVERT_MASK 0x00004000L
+-#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL3_INVERT_MASK 0x00008000L
+-#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_LANE_STAGGER_DELAY_MASK 0x00700000L
+-#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_LINK_ENABLE_HPD_MASK_MASK 0x03000000L
+-//UNIPHYLPB_LINK_CNTL
+-#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_PFREQCHG__SHIFT 0x0
+-#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_PIXVLD_RESET__SHIFT 0x4
+-#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+-#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL0_INVERT__SHIFT 0xc
+-#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL1_INVERT__SHIFT 0xd
+-#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL2_INVERT__SHIFT 0xe
+-#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL3_INVERT__SHIFT 0xf
+-#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_LANE_STAGGER_DELAY__SHIFT 0x14
+-#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_LINK_ENABLE_HPD_MASK__SHIFT 0x18
+-#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_PFREQCHG_MASK 0x00000001L
+-#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_PIXVLD_RESET_MASK 0x00000010L
+-#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L
+-#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL0_INVERT_MASK 0x00001000L
+-#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL1_INVERT_MASK 0x00002000L
+-#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL2_INVERT_MASK 0x00004000L
+-#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL3_INVERT_MASK 0x00008000L
+-#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_LANE_STAGGER_DELAY_MASK 0x00700000L
+-#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_LINK_ENABLE_HPD_MASK_MASK 0x03000000L
+-//UNIPHYLPA_CHANNEL_XBAR_CNTL
+-#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+-#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+-#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+-#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+-#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_LINK_ENABLE__SHIFT 0x1c
+-#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
+-#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
+-#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
+-#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
+-#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_LINK_ENABLE_MASK 0x10000000L
+-//UNIPHYLPB_CHANNEL_XBAR_CNTL
+-#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+-#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+-#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+-#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+-#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_LINK_ENABLE__SHIFT 0x1c
+-#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
+-#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
+-#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
+-#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
+-#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_LINK_ENABLE_MASK 0x10000000L
+-//DCIO_DPCS_TX_INTERRUPT
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_TYPE__SHIFT 0x0
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_MASK__SHIFT 0x1
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_OCCUR__SHIFT 0x2
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_TYPE__SHIFT 0x3
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_MASK__SHIFT 0x4
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_OCCUR__SHIFT 0x5
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_TYPE__SHIFT 0x6
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_MASK__SHIFT 0x7
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_OCCUR__SHIFT 0x8
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_TYPE__SHIFT 0x9
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_MASK__SHIFT 0xa
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_OCCUR__SHIFT 0xb
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_TYPE__SHIFT 0xc
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_MASK__SHIFT 0xd
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_OCCUR__SHIFT 0xe
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_TYPE__SHIFT 0xf
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_MASK__SHIFT 0x10
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_OCCUR__SHIFT 0x11
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_TYPE__SHIFT 0x12
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_MASK__SHIFT 0x13
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_OCCUR__SHIFT 0x14
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPA_INT_TYPE__SHIFT 0x18
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPA_INT_MASK__SHIFT 0x19
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPA_INT_OCCUR__SHIFT 0x1a
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPB_INT_TYPE__SHIFT 0x1b
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPB_INT_MASK__SHIFT 0x1c
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPB_INT_OCCUR__SHIFT 0x1d
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_TYPE_MASK 0x00000001L
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_MASK_MASK 0x00000002L
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_OCCUR_MASK 0x00000004L
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_TYPE_MASK 0x00000008L
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_MASK_MASK 0x00000010L
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_OCCUR_MASK 0x00000020L
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_TYPE_MASK 0x00000040L
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_MASK_MASK 0x00000080L
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_OCCUR_MASK 0x00000100L
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_TYPE_MASK 0x00000200L
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_MASK_MASK 0x00000400L
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_OCCUR_MASK 0x00000800L
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_TYPE_MASK 0x00001000L
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_MASK_MASK 0x00002000L
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_OCCUR_MASK 0x00004000L
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_TYPE_MASK 0x00008000L
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_MASK_MASK 0x00010000L
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_OCCUR_MASK 0x00020000L
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_TYPE_MASK 0x00040000L
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_MASK_MASK 0x00080000L
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_OCCUR_MASK 0x00100000L
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPA_INT_TYPE_MASK 0x01000000L
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPA_INT_MASK_MASK 0x02000000L
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPA_INT_OCCUR_MASK 0x04000000L
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPB_INT_TYPE_MASK 0x08000000L
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPB_INT_MASK_MASK 0x10000000L
+-#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPB_INT_OCCUR_MASK 0x20000000L
+-//DCIO_DPCS_RX_INTERRUPT
+-#define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_TYPE__SHIFT 0x0
+-#define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_MASK__SHIFT 0x1
+-#define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_OCCUR__SHIFT 0x2
+-#define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_TYPE_MASK 0x00000001L
+-#define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_MASK_MASK 0x00000002L
+-#define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_OCCUR_MASK 0x00000004L
+-//DCIO_SEMAPHORE0
+-#define DCIO_SEMAPHORE0__DCIO_SEMAPHORE0_REQ__SHIFT 0x0
+-#define DCIO_SEMAPHORE0__DCIO_SEMAPHORE0_GNT__SHIFT 0x10
+-#define DCIO_SEMAPHORE0__DCIO_SEMAPHORE0_REQ_MASK 0x0000FFFFL
+-#define DCIO_SEMAPHORE0__DCIO_SEMAPHORE0_GNT_MASK 0xFFFF0000L
+-//DCIO_SEMAPHORE1
+-#define DCIO_SEMAPHORE1__DCIO_SEMAPHORE1_REQ__SHIFT 0x0
+-#define DCIO_SEMAPHORE1__DCIO_SEMAPHORE1_GNT__SHIFT 0x10
+-#define DCIO_SEMAPHORE1__DCIO_SEMAPHORE1_REQ_MASK 0x0000FFFFL
+-#define DCIO_SEMAPHORE1__DCIO_SEMAPHORE1_GNT_MASK 0xFFFF0000L
+-//DCIO_SEMAPHORE2
+-#define DCIO_SEMAPHORE2__DCIO_SEMAPHORE2_REQ__SHIFT 0x0
+-#define DCIO_SEMAPHORE2__DCIO_SEMAPHORE2_GNT__SHIFT 0x10
+-#define DCIO_SEMAPHORE2__DCIO_SEMAPHORE2_REQ_MASK 0x0000FFFFL
+-#define DCIO_SEMAPHORE2__DCIO_SEMAPHORE2_GNT_MASK 0xFFFF0000L
+-//DCIO_SEMAPHORE3
+-#define DCIO_SEMAPHORE3__DCIO_SEMAPHORE3_REQ__SHIFT 0x0
+-#define DCIO_SEMAPHORE3__DCIO_SEMAPHORE3_GNT__SHIFT 0x10
+-#define DCIO_SEMAPHORE3__DCIO_SEMAPHORE3_REQ_MASK 0x0000FFFFL
+-#define DCIO_SEMAPHORE3__DCIO_SEMAPHORE3_GNT_MASK 0xFFFF0000L
+-//DCIO_SEMAPHORE4
+-#define DCIO_SEMAPHORE4__DCIO_SEMAPHORE4_REQ__SHIFT 0x0
+-#define DCIO_SEMAPHORE4__DCIO_SEMAPHORE4_GNT__SHIFT 0x10
+-#define DCIO_SEMAPHORE4__DCIO_SEMAPHORE4_REQ_MASK 0x0000FFFFL
+-#define DCIO_SEMAPHORE4__DCIO_SEMAPHORE4_GNT_MASK 0xFFFF0000L
+-//DCIO_SEMAPHORE5
+-#define DCIO_SEMAPHORE5__DCIO_SEMAPHORE5_REQ__SHIFT 0x0
+-#define DCIO_SEMAPHORE5__DCIO_SEMAPHORE5_GNT__SHIFT 0x10
+-#define DCIO_SEMAPHORE5__DCIO_SEMAPHORE5_REQ_MASK 0x0000FFFFL
+-#define DCIO_SEMAPHORE5__DCIO_SEMAPHORE5_GNT_MASK 0xFFFF0000L
+-//DCIO_SEMAPHORE6
+-#define DCIO_SEMAPHORE6__DCIO_SEMAPHORE6_REQ__SHIFT 0x0
+-#define DCIO_SEMAPHORE6__DCIO_SEMAPHORE6_GNT__SHIFT 0x10
+-#define DCIO_SEMAPHORE6__DCIO_SEMAPHORE6_REQ_MASK 0x0000FFFFL
+-#define DCIO_SEMAPHORE6__DCIO_SEMAPHORE6_GNT_MASK 0xFFFF0000L
+-//DCIO_SEMAPHORE7
+-#define DCIO_SEMAPHORE7__DCIO_SEMAPHORE7_REQ__SHIFT 0x0
+-#define DCIO_SEMAPHORE7__DCIO_SEMAPHORE7_GNT__SHIFT 0x10
+-#define DCIO_SEMAPHORE7__DCIO_SEMAPHORE7_REQ_MASK 0x0000FFFFL
+-#define DCIO_SEMAPHORE7__DCIO_SEMAPHORE7_GNT_MASK 0xFFFF0000L
+-//DC_GPIO_GENERIC_MASK
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT 0x0
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT 0x1
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT 0x2
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT 0x4
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT 0x5
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT 0x6
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT 0x8
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT 0x9
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT 0xa
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT 0xc
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT 0xd
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT 0xe
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT 0x10
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT 0x11
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT 0x12
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT 0x14
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT 0x15
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT 0x16
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT 0x18
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT 0x19
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT 0x1a
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK 0x00000001L
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK 0x00000002L
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK 0x0000000CL
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK 0x00000010L
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK 0x00000020L
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK 0x000000C0L
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK 0x00000100L
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK 0x00000200L
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK 0x00000C00L
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK 0x00001000L
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK 0x00002000L
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK 0x0000C000L
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK 0x00010000L
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK 0x00020000L
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK 0x000C0000L
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK 0x00100000L
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK 0x00200000L
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK 0x00C00000L
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK 0x01000000L
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK 0x02000000L
+-#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK 0x0C000000L
+-//DC_GPIO_GENERIC_A
+-#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT 0x0
+-#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT 0x8
+-#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT 0x10
+-#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT 0x14
+-#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT 0x15
+-#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT 0x16
+-#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT 0x17
+-#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK 0x00000001L
+-#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK 0x00000100L
+-#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK 0x00010000L
+-#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK 0x00100000L
+-#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK 0x00200000L
+-#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK 0x00400000L
+-#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK 0x00800000L
+-//DC_GPIO_GENERIC_EN
+-#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT 0x0
+-#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT 0x8
+-#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT 0x10
+-#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT 0x14
+-#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT 0x15
+-#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT 0x16
+-#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT 0x17
+-#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK 0x00000001L
+-#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK 0x00000100L
+-#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK 0x00010000L
+-#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK 0x00100000L
+-#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK 0x00200000L
+-#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK 0x00400000L
+-#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK 0x00800000L
+-//DC_GPIO_GENERIC_Y
+-#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT 0x0
+-#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT 0x8
+-#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT 0x10
+-#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT 0x14
+-#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT 0x15
+-#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT 0x16
+-#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT 0x17
+-#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK 0x00000001L
+-#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK 0x00000100L
+-#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK 0x00010000L
+-#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK 0x00100000L
+-#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK 0x00200000L
+-#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK 0x00400000L
+-#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK 0x00800000L
+-//DC_GPIO_DVODATA_MASK
+-#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK__SHIFT 0x0
+-#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK__SHIFT 0x18
+-#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK__SHIFT 0x1d
+-#define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK__SHIFT 0x1e
+-#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK_MASK 0x00FFFFFFL
+-#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK_MASK 0x1F000000L
+-#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK_MASK 0x20000000L
+-#define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK_MASK 0xC0000000L
+-//DC_GPIO_DVODATA_A
+-#define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A__SHIFT 0x0
+-#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A__SHIFT 0x18
+-#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A__SHIFT 0x1d
+-#define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A__SHIFT 0x1e
+-#define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A_MASK 0x00FFFFFFL
+-#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A_MASK 0x1F000000L
+-#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A_MASK 0x20000000L
+-#define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A_MASK 0xC0000000L
+-//DC_GPIO_DVODATA_EN
+-#define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN__SHIFT 0x0
+-#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN__SHIFT 0x18
+-#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN__SHIFT 0x1d
+-#define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN__SHIFT 0x1e
+-#define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN_MASK 0x00FFFFFFL
+-#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN_MASK 0x1F000000L
+-#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN_MASK 0x20000000L
+-#define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN_MASK 0xC0000000L
+-//DC_GPIO_DVODATA_Y
+-#define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y__SHIFT 0x0
+-#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y__SHIFT 0x18
+-#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y__SHIFT 0x1d
+-#define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y__SHIFT 0x1e
+-#define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y_MASK 0x00FFFFFFL
+-#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y_MASK 0x1F000000L
+-#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y_MASK 0x20000000L
+-#define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y_MASK 0xC0000000L
+-//DC_GPIO_DDC1_MASK
+-#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT 0x0
+-#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT 0x4
+-#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT 0x6
+-#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT 0x8
+-#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT 0xc
+-#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT 0xe
+-#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x10
+-#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x14
+-#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT 0x16
+-#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT 0x18
+-#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT 0x1c
+-#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK 0x00000001L
+-#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK 0x00000010L
+-#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK 0x00000040L
+-#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK 0x00000100L
+-#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK 0x00001000L
+-#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK 0x00004000L
+-#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x00010000L
+-#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x00100000L
+-#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK 0x00400000L
+-#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK 0x0F000000L
+-#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK 0xF0000000L
+-//DC_GPIO_DDC1_A
+-#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT 0x0
+-#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT 0x8
+-#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK 0x00000001L
+-#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK 0x00000100L
+-//DC_GPIO_DDC1_EN
+-#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT 0x0
+-#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT 0x8
+-#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK 0x00000001L
+-#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK 0x00000100L
+-//DC_GPIO_DDC1_Y
+-#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT 0x0
+-#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT 0x8
+-#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK 0x00000001L
+-#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK 0x00000100L
+-//DC_GPIO_DDC2_MASK
+-#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT 0x0
+-#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT 0x4
+-#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT 0x6
+-#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT 0x8
+-#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT 0xc
+-#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT 0xe
+-#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x10
+-#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x14
+-#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT 0x16
+-#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT 0x18
+-#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT 0x1c
+-#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK 0x00000001L
+-#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK 0x00000010L
+-#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK 0x00000040L
+-#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK 0x00000100L
+-#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK 0x00001000L
+-#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK 0x00004000L
+-#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x00010000L
+-#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x00100000L
+-#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK 0x00400000L
+-#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK 0x0F000000L
+-#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK 0xF0000000L
+-//DC_GPIO_DDC2_A
+-#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT 0x0
+-#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT 0x8
+-#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK 0x00000001L
+-#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK 0x00000100L
+-//DC_GPIO_DDC2_EN
+-#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT 0x0
+-#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT 0x8
+-#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK 0x00000001L
+-#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK 0x00000100L
+-//DC_GPIO_DDC2_Y
+-#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT 0x0
+-#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT 0x8
+-#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK 0x00000001L
+-#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK 0x00000100L
+-//DC_GPIO_DDC3_MASK
+-#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT 0x0
+-#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT 0x4
+-#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT 0x6
+-#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT 0x8
+-#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT 0xc
+-#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT 0xe
+-#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT 0x10
+-#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT 0x14
+-#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT 0x16
+-#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT 0x18
+-#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT 0x1c
+-#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK 0x00000001L
+-#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK 0x00000010L
+-#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK 0x00000040L
+-#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK 0x00000100L
+-#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK 0x00001000L
+-#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK 0x00004000L
+-#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK 0x00010000L
+-#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK 0x00100000L
+-#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK 0x00400000L
+-#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK 0x0F000000L
+-#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK 0xF0000000L
+-//DC_GPIO_DDC3_A
+-#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT 0x0
+-#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT 0x8
+-#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK 0x00000001L
+-#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK 0x00000100L
+-//DC_GPIO_DDC3_EN
+-#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT 0x0
+-#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT 0x8
+-#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK 0x00000001L
+-#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK 0x00000100L
+-//DC_GPIO_DDC3_Y
+-#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT 0x0
+-#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT 0x8
+-#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK 0x00000001L
+-#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK 0x00000100L
+-//DC_GPIO_DDC4_MASK
+-#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT 0x0
+-#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT 0x4
+-#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT 0x6
+-#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT 0x8
+-#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT 0xc
+-#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT 0xe
+-#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT 0x10
+-#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT 0x14
+-#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT 0x16
+-#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT 0x18
+-#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT 0x1c
+-#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK 0x00000001L
+-#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK 0x00000010L
+-#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK 0x00000040L
+-#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK 0x00000100L
+-#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK 0x00001000L
+-#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK 0x00004000L
+-#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK 0x00010000L
+-#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK 0x00100000L
+-#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK 0x00400000L
+-#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK 0x0F000000L
+-#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK 0xF0000000L
+-//DC_GPIO_DDC4_A
+-#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT 0x0
+-#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT 0x8
+-#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK 0x00000001L
+-#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK 0x00000100L
+-//DC_GPIO_DDC4_EN
+-#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT 0x0
+-#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT 0x8
+-#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK 0x00000001L
+-#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK 0x00000100L
+-//DC_GPIO_DDC4_Y
+-#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT 0x0
+-#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT 0x8
+-#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK 0x00000001L
+-#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK 0x00000100L
+-//DC_GPIO_DDC5_MASK
+-#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT 0x0
+-#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT 0x4
+-#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT 0x6
+-#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT 0x8
+-#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT 0xc
+-#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT 0xe
+-#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x10
+-#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT 0x14
+-#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT 0x16
+-#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT 0x18
+-#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT 0x1c
+-#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK 0x00000001L
+-#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK 0x00000010L
+-#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK 0x00000040L
+-#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK 0x00000100L
+-#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK 0x00001000L
+-#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK 0x00004000L
+-#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK 0x00010000L
+-#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK 0x00100000L
+-#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK 0x00400000L
+-#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK 0x0F000000L
+-#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK 0xF0000000L
+-//DC_GPIO_DDC5_A
+-#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT 0x0
+-#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT 0x8
+-#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK 0x00000001L
+-#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK 0x00000100L
+-//DC_GPIO_DDC5_EN
+-#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT 0x0
+-#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT 0x8
+-#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK 0x00000001L
+-#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK 0x00000100L
+-//DC_GPIO_DDC5_Y
+-#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT 0x0
+-#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT 0x8
+-#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK 0x00000001L
+-#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK 0x00000100L
+-//DC_GPIO_DDC6_MASK
+-#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK__SHIFT 0x0
+-#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN__SHIFT 0x4
+-#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV__SHIFT 0x6
+-#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK__SHIFT 0x8
+-#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN__SHIFT 0xc
+-#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV__SHIFT 0xe
+-#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE__SHIFT 0x10
+-#define DC_GPIO_DDC6_MASK__AUX6_POL__SHIFT 0x14
+-#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN__SHIFT 0x16
+-#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR__SHIFT 0x18
+-#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR__SHIFT 0x1c
+-#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK_MASK 0x00000001L
+-#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN_MASK 0x00000010L
+-#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV_MASK 0x00000040L
+-#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK_MASK 0x00000100L
+-#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN_MASK 0x00001000L
+-#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV_MASK 0x00004000L
+-#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE_MASK 0x00010000L
+-#define DC_GPIO_DDC6_MASK__AUX6_POL_MASK 0x00100000L
+-#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN_MASK 0x00400000L
+-#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR_MASK 0x0F000000L
+-#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR_MASK 0xF0000000L
+-//DC_GPIO_DDC6_A
+-#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A__SHIFT 0x0
+-#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A__SHIFT 0x8
+-#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK 0x00000001L
+-#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK 0x00000100L
+-//DC_GPIO_DDC6_EN
+-#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN__SHIFT 0x0
+-#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN__SHIFT 0x8
+-#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN_MASK 0x00000001L
+-#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN_MASK 0x00000100L
+-//DC_GPIO_DDC6_Y
+-#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y__SHIFT 0x0
+-#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y__SHIFT 0x8
+-#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y_MASK 0x00000001L
+-#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y_MASK 0x00000100L
+-//DC_GPIO_DDCVGA_MASK
+-#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x0
+-#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x6
+-#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x8
+-#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0xc
+-#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0xe
+-#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT 0x10
+-#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x14
+-#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x16
+-#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT 0x18
+-#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x1c
+-#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x00000001L
+-#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x00000040L
+-#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x00000100L
+-#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x00001000L
+-#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x00004000L
+-#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK 0x00010000L
+-#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x00100000L
+-#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x00400000L
+-#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK 0x0F000000L
+-#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xF0000000L
+-//DC_GPIO_DDCVGA_A
+-#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x0
+-#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x8
+-#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x00000001L
+-#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x00000100L
+-//DC_GPIO_DDCVGA_EN
+-#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x0
+-#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x8
+-#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x00000001L
+-#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x00000100L
+-//DC_GPIO_DDCVGA_Y
+-#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x0
+-#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x8
+-#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x00000001L
+-#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x00000100L
+-//DC_GPIO_SYNCA_MASK
+-#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK__SHIFT 0x0
+-#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS__SHIFT 0x4
+-#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV__SHIFT 0x6
+-#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK__SHIFT 0x8
+-#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS__SHIFT 0xc
+-#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV__SHIFT 0xe
+-#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK__SHIFT 0x18
+-#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK__SHIFT 0x1c
+-#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK_MASK 0x00000001L
+-#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS_MASK 0x00000010L
+-#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV_MASK 0x000000C0L
+-#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK_MASK 0x00000100L
+-#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS_MASK 0x00001000L
+-#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV_MASK 0x0000C000L
+-#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK_MASK 0x07000000L
+-#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK_MASK 0x70000000L
+-//DC_GPIO_SYNCA_A
+-#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A__SHIFT 0x0
+-#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A__SHIFT 0x8
+-#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK 0x00000001L
+-#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK 0x00000100L
+-//DC_GPIO_SYNCA_EN
+-#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN__SHIFT 0x0
+-#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN__SHIFT 0x8
+-#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN_MASK 0x00000001L
+-#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN_MASK 0x00000100L
+-//DC_GPIO_SYNCA_Y
+-#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y__SHIFT 0x0
+-#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y__SHIFT 0x8
+-#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y_MASK 0x00000001L
+-#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y_MASK 0x00000100L
+-//DC_GPIO_GENLK_MASK
+-#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT 0x0
+-#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT 0x1
+-#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT 0x3
+-#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT 0x4
+-#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT 0x8
+-#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT 0x9
+-#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT 0xb
+-#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT 0xc
+-#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT 0x10
+-#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT 0x11
+-#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT 0x13
+-#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT 0x14
+-#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT 0x18
+-#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT 0x19
+-#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT 0x1b
+-#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT 0x1c
+-#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK 0x00000001L
+-#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK 0x00000002L
+-#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK 0x00000008L
+-#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK 0x00000030L
+-#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK 0x00000100L
+-#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK 0x00000200L
+-#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK 0x00000800L
+-#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK 0x00003000L
+-#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK 0x00010000L
+-#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK 0x00020000L
+-#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK 0x00080000L
+-#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK 0x00300000L
+-#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK 0x01000000L
+-#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK 0x02000000L
+-#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK 0x08000000L
+-#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK 0x30000000L
+-//DC_GPIO_GENLK_A
+-#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT 0x0
+-#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT 0x8
+-#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT 0x10
+-#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT 0x18
+-#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK 0x00000001L
+-#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK 0x00000100L
+-#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK 0x00010000L
+-#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK 0x01000000L
+-//DC_GPIO_GENLK_EN
+-#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT 0x0
+-#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT 0x8
+-#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT 0x10
+-#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT 0x18
+-#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK 0x00000001L
+-#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK 0x00000100L
+-#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK 0x00010000L
+-#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK 0x01000000L
+-//DC_GPIO_GENLK_Y
+-#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT 0x0
+-#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT 0x8
+-#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT 0x10
+-#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT 0x18
+-#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK 0x00000001L
+-#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK 0x00000100L
+-#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK 0x00010000L
+-#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK 0x01000000L
+-//DC_GPIO_HPD_MASK
+-#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT 0x0
+-#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK__SHIFT 0x1
+-#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS__SHIFT 0x2
+-#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL__SHIFT 0x3
+-#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT 0x4
+-#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT 0x6
+-#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT 0x8
+-#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT 0x9
+-#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT 0xa
+-#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT 0x10
+-#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT 0x11
+-#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT 0x12
+-#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT 0x14
+-#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT 0x15
+-#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT 0x16
+-#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT 0x18
+-#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT 0x19
+-#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT 0x1a
+-#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT 0x1c
+-#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT 0x1d
+-#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT 0x1e
+-#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK 0x00000001L
+-#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK_MASK 0x00000002L
+-#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS_MASK 0x00000004L
+-#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL_MASK 0x00000008L
+-#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK 0x00000010L
+-#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK 0x000000C0L
+-#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK 0x00000100L
+-#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK 0x00000200L
+-#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK 0x00000C00L
+-#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK 0x00010000L
+-#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK 0x00020000L
+-#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK 0x000C0000L
+-#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK 0x00100000L
+-#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK 0x00200000L
+-#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK 0x00C00000L
+-#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK 0x01000000L
+-#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK 0x02000000L
+-#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK 0x0C000000L
+-#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK 0x10000000L
+-#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK 0x20000000L
+-#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK 0xC0000000L
+-//DC_GPIO_HPD_A
+-#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT 0x0
+-#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT 0x8
+-#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT 0x10
+-#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT 0x18
+-#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT 0x1a
+-#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT 0x1c
+-#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK 0x00000001L
+-#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK 0x00000100L
+-#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK 0x00010000L
+-#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK 0x01000000L
+-#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK 0x04000000L
+-#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK 0x10000000L
+-//DC_GPIO_HPD_EN
+-#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT 0x0
+-#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI__SHIFT 0x1
+-#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE__SHIFT 0x2
+-#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI__SHIFT 0x3
+-#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE__SHIFT 0x4
+-#define DC_GPIO_HPD_EN__HPD12_SPARE0__SHIFT 0x5
+-#define DC_GPIO_HPD_EN__HPD1_SEL0__SHIFT 0x6
+-#define DC_GPIO_HPD_EN__RX_HPD_SEL0__SHIFT 0x7
+-#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT 0x8
+-#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI__SHIFT 0x9
+-#define DC_GPIO_HPD_EN__HPD12_SPARE1__SHIFT 0xa
+-#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT 0x10
+-#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI__SHIFT 0x11
+-#define DC_GPIO_HPD_EN__HPD34_SPARE0__SHIFT 0x12
+-#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT 0x14
+-#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI__SHIFT 0x15
+-#define DC_GPIO_HPD_EN__HPD34_SPARE1__SHIFT 0x16
+-#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT 0x18
+-#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI__SHIFT 0x19
+-#define DC_GPIO_HPD_EN__HPD56_SPARE0__SHIFT 0x1a
+-#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT 0x1c
+-#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI__SHIFT 0x1d
+-#define DC_GPIO_HPD_EN__HPD56_SPARE1__SHIFT 0x1e
+-#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK 0x00000001L
+-#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI_MASK 0x00000002L
+-#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE_MASK 0x00000004L
+-#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI_MASK 0x00000008L
+-#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE_MASK 0x00000010L
+-#define DC_GPIO_HPD_EN__HPD12_SPARE0_MASK 0x00000020L
+-#define DC_GPIO_HPD_EN__HPD1_SEL0_MASK 0x00000040L
+-#define DC_GPIO_HPD_EN__RX_HPD_SEL0_MASK 0x00000080L
+-#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK 0x00000100L
+-#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI_MASK 0x00000200L
+-#define DC_GPIO_HPD_EN__HPD12_SPARE1_MASK 0x00000400L
+-#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK 0x00010000L
+-#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI_MASK 0x00020000L
+-#define DC_GPIO_HPD_EN__HPD34_SPARE0_MASK 0x00040000L
+-#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK 0x00100000L
+-#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI_MASK 0x00200000L
+-#define DC_GPIO_HPD_EN__HPD34_SPARE1_MASK 0x00400000L
+-#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK 0x01000000L
+-#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI_MASK 0x02000000L
+-#define DC_GPIO_HPD_EN__HPD56_SPARE0_MASK 0x04000000L
+-#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK 0x10000000L
+-#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI_MASK 0x20000000L
+-#define DC_GPIO_HPD_EN__HPD56_SPARE1_MASK 0x40000000L
+-//DC_GPIO_HPD_Y
+-#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT 0x0
+-#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT 0x8
+-#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT 0x10
+-#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT 0x18
+-#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT 0x1a
+-#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT 0x1c
+-#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK 0x00000001L
+-#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK 0x00000100L
+-#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK 0x00010000L
+-#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK 0x01000000L
+-#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK 0x04000000L
+-#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK 0x10000000L
+-//DC_GPIO_PWRSEQ_MASK
+-#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT 0x0
+-#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT 0x4
+-#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT 0x6
+-#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT 0x8
+-#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT 0xc
+-#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0xe
+-#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK__SHIFT 0x10
+-#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS__SHIFT 0x14
+-#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV__SHIFT 0x16
+-#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK__SHIFT 0x18
+-#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS__SHIFT 0x19
+-#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV__SHIFT 0x1a
+-#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK__SHIFT 0x1c
+-#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS__SHIFT 0x1d
+-#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV__SHIFT 0x1e
+-#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK 0x00000001L
+-#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK 0x00000010L
+-#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK 0x000000C0L
+-#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK 0x00000100L
+-#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK 0x00001000L
+-#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK 0x0000C000L
+-#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK_MASK 0x00010000L
+-#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS_MASK 0x00100000L
+-#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV_MASK 0x00C00000L
+-#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK_MASK 0x01000000L
+-#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS_MASK 0x02000000L
+-#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV_MASK 0x04000000L
+-#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK_MASK 0x10000000L
+-#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS_MASK 0x20000000L
+-#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV_MASK 0x40000000L
+-//DC_GPIO_PWRSEQ_A
+-#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A__SHIFT 0x0
+-#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A__SHIFT 0x8
+-#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A__SHIFT 0x10
+-#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A__SHIFT 0x18
+-#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A__SHIFT 0x1f
+-#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A_MASK 0x00000001L
+-#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A_MASK 0x00000100L
+-#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A_MASK 0x00010000L
+-#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A_MASK 0x01000000L
+-#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A_MASK 0x80000000L
+-//DC_GPIO_PWRSEQ_EN
+-#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT 0x0
+-#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x1
+-#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT 0x8
+-#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN__SHIFT 0x10
+-#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN__SHIFT 0x18
+-#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN__SHIFT 0x1f
+-#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK 0x00000001L
+-#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x00000002L
+-#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK 0x00000100L
+-#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN_MASK 0x00010000L
+-#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN_MASK 0x01000000L
+-#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN_MASK 0x80000000L
+-//DC_GPIO_PWRSEQ_Y
+-#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y__SHIFT 0x0
+-#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y__SHIFT 0x8
+-#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y__SHIFT 0x10
+-#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN__SHIFT 0x18
+-#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN__SHIFT 0x1f
+-#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y_MASK 0x00000001L
+-#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y_MASK 0x00000100L
+-#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y_MASK 0x00010000L
+-#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN_MASK 0x01000000L
+-#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN_MASK 0x80000000L
+-//DC_GPIO_PAD_STRENGTH_1
+-#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x0
+-#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x4
+-#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN__SHIFT 0x8
+-#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP__SHIFT 0xc
+-#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN__SHIFT 0x10
+-#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP__SHIFT 0x14
+-#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x18
+-#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x1c
+-#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0x0000000FL
+-#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0x000000F0L
+-#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN_MASK 0x00000F00L
+-#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP_MASK 0x0000F000L
+-#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN_MASK 0x000F0000L
+-#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP_MASK 0x00F00000L
+-#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0x0F000000L
+-#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xF0000000L
+-//DC_GPIO_PAD_STRENGTH_2
+-#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT 0x0
+-#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT 0x4
+-#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT 0x8
+-#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT 0xc
+-#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN__SHIFT 0x10
+-#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP__SHIFT 0x14
+-#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT 0x1e
+-#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK 0x0000000FL
+-#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK 0x000000F0L
+-#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK 0x00000700L
+-#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK 0x00007000L
+-#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN_MASK 0x000F0000L
+-#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP_MASK 0x00F00000L
+-#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK 0xC0000000L
+-//PHY_AUX_CNTL
+-#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN__SHIFT 0x0
+-#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE__SHIFT 0x1
+-#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL__SHIFT 0x2
+-#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE__SHIFT 0x3
+-#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN__SHIFT 0x4
+-#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN__SHIFT 0x5
+-#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN__SHIFT 0x6
+-#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN__SHIFT 0x7
+-#define PHY_AUX_CNTL__AUX_PAD_SLEWN__SHIFT 0xc
+-#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN__SHIFT 0xd
+-#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0xe
+-#define PHY_AUX_CNTL__AUX_PAD_RXSEL__SHIFT 0x10
+-#define PHY_AUX_CNTL__AUX_CAL_BIASENTST__SHIFT 0x14
+-#define PHY_AUX_CNTL__AUX_CAL_RESBIASEN__SHIFT 0x17
+-#define PHY_AUX_CNTL__AUX_CAL_SPARE__SHIFT 0x18
+-#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN_MASK 0x00000001L
+-#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE_MASK 0x00000002L
+-#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL_MASK 0x00000004L
+-#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE_MASK 0x00000008L
+-#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN_MASK 0x00000010L
+-#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN_MASK 0x00000020L
+-#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN_MASK 0x00000040L
+-#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN_MASK 0x00000080L
+-#define PHY_AUX_CNTL__AUX_PAD_SLEWN_MASK 0x00001000L
+-#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN_MASK 0x00002000L
+-#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK 0x00004000L
+-#define PHY_AUX_CNTL__AUX_PAD_RXSEL_MASK 0x00030000L
+-#define PHY_AUX_CNTL__AUX_CAL_BIASENTST_MASK 0x00700000L
+-#define PHY_AUX_CNTL__AUX_CAL_RESBIASEN_MASK 0x00800000L
+-#define PHY_AUX_CNTL__AUX_CAL_SPARE_MASK 0x03000000L
+-//DC_GPIO_I2CPAD_MASK
+-#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK__SHIFT 0x0
+-#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS__SHIFT 0x1
+-#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV__SHIFT 0x2
+-#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK__SHIFT 0x4
+-#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS__SHIFT 0x5
+-#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV__SHIFT 0x6
+-#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK_MASK 0x00000001L
+-#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS_MASK 0x00000002L
+-#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV_MASK 0x00000004L
+-#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK_MASK 0x00000010L
+-#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS_MASK 0x00000020L
+-#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV_MASK 0x00000040L
+-//DC_GPIO_I2CPAD_A
+-#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A__SHIFT 0x0
+-#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A__SHIFT 0x1
+-#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A_MASK 0x00000001L
+-#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A_MASK 0x00000002L
+-//DC_GPIO_I2CPAD_EN
+-#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN__SHIFT 0x0
+-#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN__SHIFT 0x1
+-#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN_MASK 0x00000001L
+-#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN_MASK 0x00000002L
+-//DC_GPIO_I2CPAD_Y
+-#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y__SHIFT 0x0
+-#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y__SHIFT 0x1
+-#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y_MASK 0x00000001L
+-#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y_MASK 0x00000002L
+-//DC_GPIO_I2CPAD_STRENGTH
+-#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN__SHIFT 0x0
+-#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP__SHIFT 0x4
+-#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN_MASK 0x0000000FL
+-#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP_MASK 0x000000F0L
+-//DVO_STRENGTH_CONTROL
+-#define DVO_STRENGTH_CONTROL__DVO_SP__SHIFT 0x0
+-#define DVO_STRENGTH_CONTROL__DVO_SN__SHIFT 0x4
+-#define DVO_STRENGTH_CONTROL__DVOCLK_SP__SHIFT 0x8
+-#define DVO_STRENGTH_CONTROL__DVOCLK_SN__SHIFT 0xc
+-#define DVO_STRENGTH_CONTROL__DVO_DRVSTRENGTH__SHIFT 0x10
+-#define DVO_STRENGTH_CONTROL__DVOCLK_DRVSTRENGTH__SHIFT 0x14
+-#define DVO_STRENGTH_CONTROL__FLDO_VITNE_DRVSTRENGTH__SHIFT 0x18
+-#define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE__SHIFT 0x1c
+-#define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE__SHIFT 0x1d
+-#define DVO_STRENGTH_CONTROL__DVO_SP_MASK 0x0000000FL
+-#define DVO_STRENGTH_CONTROL__DVO_SN_MASK 0x000000F0L
+-#define DVO_STRENGTH_CONTROL__DVOCLK_SP_MASK 0x00000F00L
+-#define DVO_STRENGTH_CONTROL__DVOCLK_SN_MASK 0x0000F000L
+-#define DVO_STRENGTH_CONTROL__DVO_DRVSTRENGTH_MASK 0x00070000L
+-#define DVO_STRENGTH_CONTROL__DVOCLK_DRVSTRENGTH_MASK 0x00700000L
+-#define DVO_STRENGTH_CONTROL__FLDO_VITNE_DRVSTRENGTH_MASK 0x07000000L
+-#define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE_MASK 0x10000000L
+-#define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE_MASK 0x20000000L
+-//DVO_VREF_CONTROL
+-#define DVO_VREF_CONTROL__DVO_VREFPON__SHIFT 0x0
+-#define DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT 0x1
+-#define DVO_VREF_CONTROL__DVO_VREFCAL__SHIFT 0x4
+-#define DVO_VREF_CONTROL__DVO_VREFPON_MASK 0x00000001L
+-#define DVO_VREF_CONTROL__DVO_VREFSEL_MASK 0x00000002L
+-#define DVO_VREF_CONTROL__DVO_VREFCAL_MASK 0x000000F0L
+-//DVO_SKEW_ADJUST
+-#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST__SHIFT 0x0
+-#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST_MASK 0xFFFFFFFFL
+-//DC_GPIO_I2S_SPDIF_MASK
+-#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA0_MASK__SHIFT 0x0
+-#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK0_MASK__SHIFT 0x4
+-#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK0_MASK__SHIFT 0x5
+-#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK0_MASK__SHIFT 0x6
+-#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF0_MASK__SHIFT 0x7
+-#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA1_MASK__SHIFT 0x8
+-#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK1_MASK__SHIFT 0x9
+-#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK1_MASK__SHIFT 0xa
+-#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK1_MASK__SHIFT 0xb
+-#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF1_MASK__SHIFT 0xc
+-#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA0_MASK_MASK 0x0000000FL
+-#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK0_MASK_MASK 0x00000010L
+-#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK0_MASK_MASK 0x00000020L
+-#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK0_MASK_MASK 0x00000040L
+-#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF0_MASK_MASK 0x00000080L
+-#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA1_MASK_MASK 0x00000100L
+-#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK1_MASK_MASK 0x00000200L
+-#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK1_MASK_MASK 0x00000400L
+-#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK1_MASK_MASK 0x00000800L
+-#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF1_MASK_MASK 0x00001000L
+-//DC_GPIO_I2S_SPDIF_A
+-#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA0_A__SHIFT 0x0
+-#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK0_A__SHIFT 0x4
+-#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK0_A__SHIFT 0x5
+-#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK0_A__SHIFT 0x6
+-#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF0_A__SHIFT 0x7
+-#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA1_A__SHIFT 0x8
+-#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK1_A__SHIFT 0x9
+-#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK1_A__SHIFT 0xa
+-#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK1_A__SHIFT 0xb
+-#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF1_A__SHIFT 0xc
+-#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA0_A_MASK 0x0000000FL
+-#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK0_A_MASK 0x00000010L
+-#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK0_A_MASK 0x00000020L
+-#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK0_A_MASK 0x00000040L
+-#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF0_A_MASK 0x00000080L
+-#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA1_A_MASK 0x00000100L
+-#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK1_A_MASK 0x00000200L
+-#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK1_A_MASK 0x00000400L
+-#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK1_A_MASK 0x00000800L
+-#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF1_A_MASK 0x00001000L
+-//DC_GPIO_I2S_SPDIF_EN
+-#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA0_EN__SHIFT 0x0
+-#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK0_EN__SHIFT 0x4
+-#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK0_EN__SHIFT 0x5
+-#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK0_EN__SHIFT 0x6
+-#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF0_EN__SHIFT 0x7
+-#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA1_EN__SHIFT 0x8
+-#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK1_EN__SHIFT 0x9
+-#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK1_EN__SHIFT 0xa
+-#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK1_EN__SHIFT 0xb
+-#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF1_EN__SHIFT 0xc
+-#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_APORT__SHIFT 0xd
+-#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_PU__SHIFT 0xe
+-#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_RXSEL__SHIFT 0xf
+-#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_SCHMEN__SHIFT 0x10
+-#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_SMODE_EN__SHIFT 0x11
+-#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_IMODE__SHIFT 0x12
+-#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA0_EN_MASK 0x0000000FL
+-#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK0_EN_MASK 0x00000010L
+-#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK0_EN_MASK 0x00000020L
+-#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK0_EN_MASK 0x00000040L
+-#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF0_EN_MASK 0x00000080L
+-#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA1_EN_MASK 0x00000100L
+-#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK1_EN_MASK 0x00000200L
+-#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK1_EN_MASK 0x00000400L
+-#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK1_EN_MASK 0x00000800L
+-#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF1_EN_MASK 0x00001000L
+-#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_APORT_MASK 0x00002000L
+-#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_PU_MASK 0x00004000L
+-#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_RXSEL_MASK 0x00008000L
+-#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_SCHMEN_MASK 0x00010000L
+-#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_SMODE_EN_MASK 0x00020000L
+-#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_IMODE_MASK 0x00040000L
+-//DC_GPIO_I2S_SPDIF_Y
+-#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA0_Y__SHIFT 0x0
+-#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK0_Y__SHIFT 0x4
+-#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK0_Y__SHIFT 0x5
+-#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK0_Y__SHIFT 0x6
+-#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF0_Y__SHIFT 0x7
+-#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA1_Y__SHIFT 0x8
+-#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK1_Y__SHIFT 0x9
+-#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK1_Y__SHIFT 0xa
+-#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK1_Y__SHIFT 0xb
+-#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF1_Y__SHIFT 0xc
+-#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA0_Y_MASK 0x0000000FL
+-#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK0_Y_MASK 0x00000010L
+-#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK0_Y_MASK 0x00000020L
+-#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK0_Y_MASK 0x00000040L
+-#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF0_Y_MASK 0x00000080L
+-#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA1_Y_MASK 0x00000100L
+-#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK1_Y_MASK 0x00000200L
+-#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK1_Y_MASK 0x00000400L
+-#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK1_Y_MASK 0x00000800L
+-#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF1_Y_MASK 0x00001000L
+-//DC_GPIO_I2S_SPDIF_STRENGTH
+-#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S0_DRVSTRENGTH__SHIFT 0x0
+-#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_SN__SHIFT 0x8
+-#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_SP__SHIFT 0xb
+-#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S1_DRVSTRENGTH__SHIFT 0x10
+-#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH_SN__SHIFT 0x18
+-#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH_SP__SHIFT 0x1b
+-#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S0_DRVSTRENGTH_MASK 0x00000007L
+-#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_SN_MASK 0x00000700L
+-#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_SP_MASK 0x00003800L
+-#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S1_DRVSTRENGTH_MASK 0x00070000L
+-#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH_SN_MASK 0x07000000L
+-#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH_SP_MASK 0x38000000L
+-//DC_GPIO_TX12_EN
+-#define DC_GPIO_TX12_EN__DC_GPIO_BLON_TX12_EN__SHIFT 0x0
+-#define DC_GPIO_TX12_EN__DC_GPIO_DIGON_TX12_EN__SHIFT 0x1
+-#define DC_GPIO_TX12_EN__DC_GPIO_ENA_BL_TX12_EN__SHIFT 0x2
+-#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN__SHIFT 0x3
+-#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN__SHIFT 0x4
+-#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN__SHIFT 0x5
+-#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN__SHIFT 0x6
+-#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN__SHIFT 0x7
+-#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN__SHIFT 0x8
+-#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN__SHIFT 0x9
+-#define DC_GPIO_TX12_EN__DC_GPIO_HSYNC_TX12_EN__SHIFT 0xa
+-#define DC_GPIO_TX12_EN__DC_GPIO_VSYNC_TX12_EN__SHIFT 0xb
+-#define DC_GPIO_TX12_EN__DC_GPIO_GENLK_CLK_TX12_EN__SHIFT 0xc
+-#define DC_GPIO_TX12_EN__DC_GPIO_GENLK_VSYNC_TX12_EN__SHIFT 0xd
+-#define DC_GPIO_TX12_EN__DC_GPIO_SWAPLOCKA_TX12_EN__SHIFT 0xe
+-#define DC_GPIO_TX12_EN__DC_GPIO_SWAPLOCKB_TX12_EN__SHIFT 0xf
+-#define DC_GPIO_TX12_EN__DC_GPIO_SCL_TX12_EN__SHIFT 0x10
+-#define DC_GPIO_TX12_EN__DC_GPIO_SDA_TX12_EN__SHIFT 0x11
+-#define DC_GPIO_TX12_EN__DC_GPIO_HPD1_TX12_EN__SHIFT 0x12
+-#define DC_GPIO_TX12_EN__DC_GPIO_BLON_TX12_EN_MASK 0x00000001L
+-#define DC_GPIO_TX12_EN__DC_GPIO_DIGON_TX12_EN_MASK 0x00000002L
+-#define DC_GPIO_TX12_EN__DC_GPIO_ENA_BL_TX12_EN_MASK 0x00000004L
+-#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN_MASK 0x00000008L
+-#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN_MASK 0x00000010L
+-#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN_MASK 0x00000020L
+-#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN_MASK 0x00000040L
+-#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN_MASK 0x00000080L
+-#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN_MASK 0x00000100L
+-#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN_MASK 0x00000200L
+-#define DC_GPIO_TX12_EN__DC_GPIO_HSYNC_TX12_EN_MASK 0x00000400L
+-#define DC_GPIO_TX12_EN__DC_GPIO_VSYNC_TX12_EN_MASK 0x00000800L
+-#define DC_GPIO_TX12_EN__DC_GPIO_GENLK_CLK_TX12_EN_MASK 0x00001000L
+-#define DC_GPIO_TX12_EN__DC_GPIO_GENLK_VSYNC_TX12_EN_MASK 0x00002000L
+-#define DC_GPIO_TX12_EN__DC_GPIO_SWAPLOCKA_TX12_EN_MASK 0x00004000L
+-#define DC_GPIO_TX12_EN__DC_GPIO_SWAPLOCKB_TX12_EN_MASK 0x00008000L
+-#define DC_GPIO_TX12_EN__DC_GPIO_SCL_TX12_EN_MASK 0x00010000L
+-#define DC_GPIO_TX12_EN__DC_GPIO_SDA_TX12_EN_MASK 0x00020000L
+-#define DC_GPIO_TX12_EN__DC_GPIO_HPD1_TX12_EN_MASK 0x00040000L
+-//DC_GPIO_AUX_CTRL_0
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL__SHIFT 0x0
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL__SHIFT 0x2
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL__SHIFT 0x4
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL__SHIFT 0x6
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL__SHIFT 0x8
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL__SHIFT 0xa
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL__SHIFT 0xc
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_GENI2C_FALLSLEWSEL__SHIFT 0xe
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN__SHIFT 0x10
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN__SHIFT 0x11
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN__SHIFT 0x12
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN__SHIFT 0x13
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN__SHIFT 0x14
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN__SHIFT 0x15
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN__SHIFT 0x16
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_GENI2C_SPIKERCEN__SHIFT 0x17
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL__SHIFT 0x18
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL__SHIFT 0x19
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL__SHIFT 0x1a
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL__SHIFT 0x1b
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL__SHIFT 0x1c
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL__SHIFT 0x1d
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL__SHIFT 0x1e
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_GENI2C_SPIKERCSEL__SHIFT 0x1f
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL_MASK 0x00000003L
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL_MASK 0x0000000CL
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL_MASK 0x00000030L
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL_MASK 0x000000C0L
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL_MASK 0x00000300L
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL_MASK 0x00000C00L
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL_MASK 0x00003000L
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_GENI2C_FALLSLEWSEL_MASK 0x0000C000L
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN_MASK 0x00010000L
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN_MASK 0x00020000L
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN_MASK 0x00040000L
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN_MASK 0x00080000L
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN_MASK 0x00100000L
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN_MASK 0x00200000L
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN_MASK 0x00400000L
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_GENI2C_SPIKERCEN_MASK 0x00800000L
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL_MASK 0x01000000L
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL_MASK 0x02000000L
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL_MASK 0x04000000L
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL_MASK 0x08000000L
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL_MASK 0x10000000L
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL_MASK 0x20000000L
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL_MASK 0x40000000L
+-#define DC_GPIO_AUX_CTRL_0__DC_GPIO_GENI2C_SPIKERCSEL_MASK 0x80000000L
+-//DC_GPIO_AUX_CTRL_1
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9__SHIFT 0x0
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1__SHIFT 0x1
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9__SHIFT 0x2
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1__SHIFT 0x3
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9__SHIFT 0x4
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1__SHIFT 0x5
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9__SHIFT 0x6
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1__SHIFT 0x7
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN__SHIFT 0x8
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN__SHIFT 0x9
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN__SHIFT 0xa
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN__SHIFT 0xb
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_COMPSEL__SHIFT 0xc
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_COMPSEL__SHIFT 0xd
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE__SHIFT 0xe
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_SPARE__SHIFT 0x10
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN__SHIFT 0x12
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_SLEWN__SHIFT 0x13
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL__SHIFT 0x14
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_RXSEL__SHIFT 0x16
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_PDEN__SHIFT 0x18
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9_MASK 0x00000001L
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1_MASK 0x00000002L
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9_MASK 0x00000004L
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1_MASK 0x00000008L
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9_MASK 0x00000010L
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1_MASK 0x00000020L
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9_MASK 0x00000040L
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1_MASK 0x00000080L
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN_MASK 0x00000100L
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN_MASK 0x00000200L
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN_MASK 0x00000400L
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN_MASK 0x00000800L
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_COMPSEL_MASK 0x00001000L
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_COMPSEL_MASK 0x00002000L
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE_MASK 0x0000C000L
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_SPARE_MASK 0x00030000L
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN_MASK 0x00040000L
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_SLEWN_MASK 0x00080000L
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL_MASK 0x00300000L
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_RXSEL_MASK 0x00C00000L
+-#define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_PDEN_MASK 0x01000000L
+-//DC_GPIO_AUX_CTRL_2
+-#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL__SHIFT 0x0
+-#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL__SHIFT 0x2
+-#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL__SHIFT 0x4
+-#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN__SHIFT 0x8
+-#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN__SHIFT 0x9
+-#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN__SHIFT 0xa
+-#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL__SHIFT 0xc
+-#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL__SHIFT 0xd
+-#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL__SHIFT 0xe
+-#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9__SHIFT 0x10
+-#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1__SHIFT 0x11
+-#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9__SHIFT 0x12
+-#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1__SHIFT 0x13
+-#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN__SHIFT 0x14
+-#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN__SHIFT 0x18
+-#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN__SHIFT 0x19
+-#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN__SHIFT 0x1a
+-#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL_MASK 0x00000003L
+-#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL_MASK 0x0000000CL
+-#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL_MASK 0x00000030L
+-#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN_MASK 0x00000100L
+-#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN_MASK 0x00000200L
+-#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN_MASK 0x00000400L
+-#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL_MASK 0x00001000L
+-#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL_MASK 0x00002000L
+-#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL_MASK 0x00004000L
+-#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9_MASK 0x00010000L
+-#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1_MASK 0x00020000L
+-#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9_MASK 0x00040000L
+-#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1_MASK 0x00080000L
+-#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN_MASK 0x00100000L
+-#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN_MASK 0x01000000L
+-#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN_MASK 0x02000000L
+-#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN_MASK 0x04000000L
+-//DC_GPIO_RXEN
+-#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN__SHIFT 0x0
+-#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN__SHIFT 0x1
+-#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN__SHIFT 0x2
+-#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN__SHIFT 0x3
+-#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN__SHIFT 0x4
+-#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN__SHIFT 0x5
+-#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN__SHIFT 0x6
+-#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN__SHIFT 0x8
+-#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN__SHIFT 0x9
+-#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN__SHIFT 0xa
+-#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN__SHIFT 0xb
+-#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN__SHIFT 0xc
+-#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN__SHIFT 0xd
+-#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN__SHIFT 0xe
+-#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN__SHIFT 0xf
+-#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN__SHIFT 0x10
+-#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN__SHIFT 0x11
+-#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN__SHIFT 0x12
+-#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN__SHIFT 0x13
+-#define DC_GPIO_RXEN__DC_GPIO_BLON_RXEN__SHIFT 0x14
+-#define DC_GPIO_RXEN__DC_GPIO_DIGON_RXEN__SHIFT 0x15
+-#define DC_GPIO_RXEN__DC_GPIO_ENA_BL_RXEN__SHIFT 0x16
+-#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN_MASK 0x00000001L
+-#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN_MASK 0x00000002L
+-#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN_MASK 0x00000004L
+-#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN_MASK 0x00000008L
+-#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN_MASK 0x00000010L
+-#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN_MASK 0x00000020L
+-#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN_MASK 0x00000040L
+-#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN_MASK 0x00000100L
+-#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN_MASK 0x00000200L
+-#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN_MASK 0x00000400L
+-#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN_MASK 0x00000800L
+-#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN_MASK 0x00001000L
+-#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN_MASK 0x00002000L
+-#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN_MASK 0x00004000L
+-#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN_MASK 0x00008000L
+-#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN_MASK 0x00010000L
+-#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN_MASK 0x00020000L
+-#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN_MASK 0x00040000L
+-#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN_MASK 0x00080000L
+-#define DC_GPIO_RXEN__DC_GPIO_BLON_RXEN_MASK 0x00100000L
+-#define DC_GPIO_RXEN__DC_GPIO_DIGON_RXEN_MASK 0x00200000L
+-#define DC_GPIO_RXEN__DC_GPIO_ENA_BL_RXEN_MASK 0x00400000L
+-//BPHYC_DAC_MACRO_CNTL
+-#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL__SHIFT 0x0
+-#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL__SHIFT 0x8
+-#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT__SHIFT 0x10
+-#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR__SHIFT 0x18
+-#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON__SHIFT 0x1c
+-#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL_MASK 0x00000003L
+-#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL_MASK 0x00003F00L
+-#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT_MASK 0x003F0000L
+-#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR_MASK 0x0F000000L
+-#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON_MASK 0x10000000L
+-//DAC_MACRO_CNTL_RESERVED0
+-#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//BPHYC_DAC_AUTO_CALIB_CONTROL
+-#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB__SHIFT 0x0
+-#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN__SHIFT 0x1
+-#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN__SHIFT 0x2
+-#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST__SHIFT 0x4
+-#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK__SHIFT 0x14
+-#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE__SHIFT 0x1c
+-#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB_MASK 0x00000001L
+-#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN_MASK 0x00000002L
+-#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN_MASK 0x00000004L
+-#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST_MASK 0x00003FF0L
+-#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK_MASK 0x00700000L
+-#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE_MASK 0x10000000L
+-//DAC_MACRO_CNTL_RESERVED1
+-#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DAC_MACRO_CNTL_RESERVED2
+-#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DAC_MACRO_CNTL_RESERVED3
+-#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DISP_DSI_DUAL_CTRL
+-#define DISP_DSI_DUAL_CTRL__DUAL_PIPE_MODE__SHIFT 0x0
+-#define DISP_DSI_DUAL_CTRL__DUAL_PIPE_MODE_MASK 0x00000001L
+-//DPHY_MACRO_CNTL_RESERVED0
+-#define DPHY_MACRO_CNTL_RESERVED0__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED0__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED1
+-#define DPHY_MACRO_CNTL_RESERVED1__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED1__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED2
+-#define DPHY_MACRO_CNTL_RESERVED2__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED2__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED3
+-#define DPHY_MACRO_CNTL_RESERVED3__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED3__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED4
+-#define DPHY_MACRO_CNTL_RESERVED4__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED4__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED5
+-#define DPHY_MACRO_CNTL_RESERVED5__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED5__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED6
+-#define DPHY_MACRO_CNTL_RESERVED6__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED6__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED7
+-#define DPHY_MACRO_CNTL_RESERVED7__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED7__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED8
+-#define DPHY_MACRO_CNTL_RESERVED8__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED8__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED9
+-#define DPHY_MACRO_CNTL_RESERVED9__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED9__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED10
+-#define DPHY_MACRO_CNTL_RESERVED10__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED10__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED11
+-#define DPHY_MACRO_CNTL_RESERVED11__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED11__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED12
+-#define DPHY_MACRO_CNTL_RESERVED12__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED12__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED13
+-#define DPHY_MACRO_CNTL_RESERVED13__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED13__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED14
+-#define DPHY_MACRO_CNTL_RESERVED14__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED14__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED15
+-#define DPHY_MACRO_CNTL_RESERVED15__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED15__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED16
+-#define DPHY_MACRO_CNTL_RESERVED16__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED16__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED17
+-#define DPHY_MACRO_CNTL_RESERVED17__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED17__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED18
+-#define DPHY_MACRO_CNTL_RESERVED18__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED18__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED19
+-#define DPHY_MACRO_CNTL_RESERVED19__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED19__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED20
+-#define DPHY_MACRO_CNTL_RESERVED20__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED20__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED21
+-#define DPHY_MACRO_CNTL_RESERVED21__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED21__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED22
+-#define DPHY_MACRO_CNTL_RESERVED22__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED22__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED23
+-#define DPHY_MACRO_CNTL_RESERVED23__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED23__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED24
+-#define DPHY_MACRO_CNTL_RESERVED24__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED24__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED25
+-#define DPHY_MACRO_CNTL_RESERVED25__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED25__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED26
+-#define DPHY_MACRO_CNTL_RESERVED26__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED26__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED27
+-#define DPHY_MACRO_CNTL_RESERVED27__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED27__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED28
+-#define DPHY_MACRO_CNTL_RESERVED28__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED28__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED29
+-#define DPHY_MACRO_CNTL_RESERVED29__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED29__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED30
+-#define DPHY_MACRO_CNTL_RESERVED30__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED30__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED31
+-#define DPHY_MACRO_CNTL_RESERVED31__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED31__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED32
+-#define DPHY_MACRO_CNTL_RESERVED32__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED32__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED33
+-#define DPHY_MACRO_CNTL_RESERVED33__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED33__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED34
+-#define DPHY_MACRO_CNTL_RESERVED34__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED34__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED35
+-#define DPHY_MACRO_CNTL_RESERVED35__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED35__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED36
+-#define DPHY_MACRO_CNTL_RESERVED36__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED36__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED37
+-#define DPHY_MACRO_CNTL_RESERVED37__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED37__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED38
+-#define DPHY_MACRO_CNTL_RESERVED38__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED38__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED39
+-#define DPHY_MACRO_CNTL_RESERVED39__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED39__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED40
+-#define DPHY_MACRO_CNTL_RESERVED40__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED40__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED41
+-#define DPHY_MACRO_CNTL_RESERVED41__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED41__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED42
+-#define DPHY_MACRO_CNTL_RESERVED42__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED42__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED43
+-#define DPHY_MACRO_CNTL_RESERVED43__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED43__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED44
+-#define DPHY_MACRO_CNTL_RESERVED44__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED44__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED45
+-#define DPHY_MACRO_CNTL_RESERVED45__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED45__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED46
+-#define DPHY_MACRO_CNTL_RESERVED46__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED46__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED47
+-#define DPHY_MACRO_CNTL_RESERVED47__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED47__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED48
+-#define DPHY_MACRO_CNTL_RESERVED48__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED48__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED49
+-#define DPHY_MACRO_CNTL_RESERVED49__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED49__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED50
+-#define DPHY_MACRO_CNTL_RESERVED50__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED50__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED51
+-#define DPHY_MACRO_CNTL_RESERVED51__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED51__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED52
+-#define DPHY_MACRO_CNTL_RESERVED52__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED52__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED53
+-#define DPHY_MACRO_CNTL_RESERVED53__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED53__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED54
+-#define DPHY_MACRO_CNTL_RESERVED54__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED54__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED55
+-#define DPHY_MACRO_CNTL_RESERVED55__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED55__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED56
+-#define DPHY_MACRO_CNTL_RESERVED56__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED56__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED57
+-#define DPHY_MACRO_CNTL_RESERVED57__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED57__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED58
+-#define DPHY_MACRO_CNTL_RESERVED58__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED58__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED59
+-#define DPHY_MACRO_CNTL_RESERVED59__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED59__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED60
+-#define DPHY_MACRO_CNTL_RESERVED60__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED60__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED61
+-#define DPHY_MACRO_CNTL_RESERVED61__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED61__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED62
+-#define DPHY_MACRO_CNTL_RESERVED62__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED62__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPHY_MACRO_CNTL_RESERVED63
+-#define DPHY_MACRO_CNTL_RESERVED63__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DPHY_MACRO_CNTL_RESERVED63__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DPRX_AUX_REFERENCE_PULSE_DIV
+-#define DPRX_AUX_REFERENCE_PULSE_DIV__DPRX_AUX_1_MICROSECOND_DIV__SHIFT 0x0
+-#define DPRX_AUX_REFERENCE_PULSE_DIV__DPRX_AUX_1_MICROSECOND_SOURCE_SEL__SHIFT 0xf
+-#define DPRX_AUX_REFERENCE_PULSE_DIV__DPRX_AUX_100_MICROSECOND_DIV__SHIFT 0x10
+-#define DPRX_AUX_REFERENCE_PULSE_DIV__DPRX_AUX_1_MILLISECOND_DIV__SHIFT 0x18
+-#define DPRX_AUX_REFERENCE_PULSE_DIV__DPRX_AUX_1_MICROSECOND_DIV_MASK 0x000003FFL
+-#define DPRX_AUX_REFERENCE_PULSE_DIV__DPRX_AUX_1_MICROSECOND_SOURCE_SEL_MASK 0x00008000L
+-#define DPRX_AUX_REFERENCE_PULSE_DIV__DPRX_AUX_100_MICROSECOND_DIV_MASK 0x00FF0000L
+-#define DPRX_AUX_REFERENCE_PULSE_DIV__DPRX_AUX_1_MILLISECOND_DIV_MASK 0x3F000000L
+-//DPRX_AUX_CONTROL
+-#define DPRX_AUX_CONTROL__DPRX_AUX_EN__SHIFT 0x0
+-#define DPRX_AUX_CONTROL__DPRX_AUX_REQUEST_TIMEOUT_LEN__SHIFT 0x8
+-#define DPRX_AUX_CONTROL__DPRX_AUX_IMPCAL_REQ_EN__SHIFT 0x18
+-#define DPRX_AUX_CONTROL__DPRX_AUX_TEST_MODE__SHIFT 0x1c
+-#define DPRX_AUX_CONTROL__DPRX_AUX_DEGLITCH_EN__SHIFT 0x1d
+-#define DPRX_AUX_CONTROL__DPRX_AUX_SPARE_0__SHIFT 0x1e
+-#define DPRX_AUX_CONTROL__DPRX_AUX_SPARE_1__SHIFT 0x1f
+-#define DPRX_AUX_CONTROL__DPRX_AUX_EN_MASK 0x00000001L
+-#define DPRX_AUX_CONTROL__DPRX_AUX_REQUEST_TIMEOUT_LEN_MASK 0x0001FF00L
+-#define DPRX_AUX_CONTROL__DPRX_AUX_IMPCAL_REQ_EN_MASK 0x01000000L
+-#define DPRX_AUX_CONTROL__DPRX_AUX_TEST_MODE_MASK 0x10000000L
+-#define DPRX_AUX_CONTROL__DPRX_AUX_DEGLITCH_EN_MASK 0x20000000L
+-#define DPRX_AUX_CONTROL__DPRX_AUX_SPARE_0_MASK 0x40000000L
+-#define DPRX_AUX_CONTROL__DPRX_AUX_SPARE_1_MASK 0x80000000L
+-//DPRX_AUX_HPD_CONTROL1
+-#define DPRX_AUX_HPD_CONTROL1__DPRX_AUX_HPD_IRQ_PULSE_WIDTH__SHIFT 0x0
+-#define DPRX_AUX_HPD_CONTROL1__DPRX_AUX_HPD_IRQ_GAP__SHIFT 0x8
+-#define DPRX_AUX_HPD_CONTROL1__DPRX_AUX_HPD_A__SHIFT 0x10
+-#define DPRX_AUX_HPD_CONTROL1__DPRX_AUX_HPD_EN__SHIFT 0x11
+-#define DPRX_AUX_HPD_CONTROL1__DPRX_AUX_HPD_IRQ_PULSE_WIDTH_MASK 0x0000000FL
+-#define DPRX_AUX_HPD_CONTROL1__DPRX_AUX_HPD_IRQ_GAP_MASK 0x00003F00L
+-#define DPRX_AUX_HPD_CONTROL1__DPRX_AUX_HPD_A_MASK 0x00010000L
+-#define DPRX_AUX_HPD_CONTROL1__DPRX_AUX_HPD_EN_MASK 0x00020000L
+-//DPRX_AUX_HPD_CONTROL2
+-#define DPRX_AUX_HPD_CONTROL2__DPRX_AUX_HPD_IRQ_TRIGGER__SHIFT 0x0
+-#define DPRX_AUX_HPD_CONTROL2__DPRX_AUX_NEW_HPD_IRQ_READY__SHIFT 0x1
+-#define DPRX_AUX_HPD_CONTROL2__DPRX_AUX_HPD_IRQ_TRIGGER_MASK 0x00000001L
+-#define DPRX_AUX_HPD_CONTROL2__DPRX_AUX_NEW_HPD_IRQ_READY_MASK 0x00000002L
+-//DPRX_AUX_RX_STATUS
+-#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_STATUS_CLEAR__SHIFT 0x0
+-#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_DONE__SHIFT 0x7
+-#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_OVERFLOW__SHIFT 0x8
+-#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_TIMEOUT__SHIFT 0x9
+-#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_PARTIAL_BYTE__SHIFT 0xa
+-#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_MIN_COUNT_VIOL__SHIFT 0xc
+-#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_INVALID_STOP__SHIFT 0xe
+-#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_SYNC_INVALID_L__SHIFT 0x11
+-#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_SYNC_INVALID_H__SHIFT 0x12
+-#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_INVALID_START__SHIFT 0x13
+-#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_RECV_NO_DET__SHIFT 0x14
+-#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_RECV_INVALID_H__SHIFT 0x16
+-#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_RECV_INVALID_L__SHIFT 0x17
+-#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_BYTE_COUNT__SHIFT 0x18
+-#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_STATUS_CLEAR_MASK 0x00000001L
+-#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_DONE_MASK 0x00000080L
+-#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_OVERFLOW_MASK 0x00000100L
+-#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_TIMEOUT_MASK 0x00000200L
+-#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_PARTIAL_BYTE_MASK 0x00000400L
+-#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+-#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_INVALID_STOP_MASK 0x00004000L
+-#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_SYNC_INVALID_L_MASK 0x00020000L
+-#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_SYNC_INVALID_H_MASK 0x00040000L
+-#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_INVALID_START_MASK 0x00080000L
+-#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_RECV_NO_DET_MASK 0x00100000L
+-#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_RECV_INVALID_H_MASK 0x00400000L
+-#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_RECV_INVALID_L_MASK 0x00800000L
+-#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_BYTE_COUNT_MASK 0x1F000000L
+-//DPRX_AUX_RX_ERROR_MASK
+-#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_OVERFLOW_MASK__SHIFT 0x8
+-#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_TIMEOUT_MASK__SHIFT 0x9
+-#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_PARTIAL_BYTE_MASK__SHIFT 0xa
+-#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_MIN_COUNT_VIOL_MASK__SHIFT 0xc
+-#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_INVALID_STOP_MASK__SHIFT 0xe
+-#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_SYNC_INVALID_L_MASK__SHIFT 0x11
+-#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_SYNC_INVALID_H_MASK__SHIFT 0x12
+-#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_INVALID_START_MASK__SHIFT 0x13
+-#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_RECV_NO_DET_MASK__SHIFT 0x14
+-#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_RECV_INVALID_H_MASK__SHIFT 0x16
+-#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_RECV_INVALID_L_MASK__SHIFT 0x17
+-#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_OVERFLOW_MASK_MASK 0x00000100L
+-#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_TIMEOUT_MASK_MASK 0x00000200L
+-#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_PARTIAL_BYTE_MASK_MASK 0x00000400L
+-#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_MIN_COUNT_VIOL_MASK_MASK 0x00001000L
+-#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_INVALID_STOP_MASK_MASK 0x00004000L
+-#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_SYNC_INVALID_L_MASK_MASK 0x00020000L
+-#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_SYNC_INVALID_H_MASK_MASK 0x00040000L
+-#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_INVALID_START_MASK_MASK 0x00080000L
+-#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_RECV_NO_DET_MASK_MASK 0x00100000L
+-#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_RECV_INVALID_H_MASK_MASK 0x00400000L
+-#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_RECV_INVALID_L_MASK_MASK 0x00800000L
+-//DPRX_AUX_DPHY_TX_REF_CONTROL
+-#define DPRX_AUX_DPHY_TX_REF_CONTROL__DPRX_AUX_TX_REF_SEL__SHIFT 0x0
+-#define DPRX_AUX_DPHY_TX_REF_CONTROL__DPRX_AUX_TX_RATE__SHIFT 0x4
+-#define DPRX_AUX_DPHY_TX_REF_CONTROL__DPRX_AUX_TX_REF_DIV__SHIFT 0x10
+-#define DPRX_AUX_DPHY_TX_REF_CONTROL__DPRX_AUX_TX_REF_SEL_MASK 0x00000001L
+-#define DPRX_AUX_DPHY_TX_REF_CONTROL__DPRX_AUX_TX_RATE_MASK 0x00000030L
+-#define DPRX_AUX_DPHY_TX_REF_CONTROL__DPRX_AUX_TX_REF_DIV_MASK 0x01FF0000L
+-//DPRX_AUX_DPHY_TX_CONTROL
+-#define DPRX_AUX_DPHY_TX_CONTROL__DPRX_AUX_TX_PRECHARGE_LEN__SHIFT 0x0
+-#define DPRX_AUX_DPHY_TX_CONTROL__DPRX_AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8
+-#define DPRX_AUX_DPHY_TX_CONTROL__DPRX_AUX_TX_PRECHARGE_LEN_MASK 0x00000007L
+-#define DPRX_AUX_DPHY_TX_CONTROL__DPRX_AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L
+-//DPRX_AUX_DPHY_RX_CONTROL0
+-#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_START_WINDOW__SHIFT 0x4
+-#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_RECEIVE_WINDOW__SHIFT 0x8
+-#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc
+-#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10
+-#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11
+-#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12
+-#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13
+-#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14
+-#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c
+-#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_START_WINDOW_MASK 0x00000070L
+-#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L
+-#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L
+-#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L
+-#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L
+-#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L
+-#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L
+-#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L
+-#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L
+-//DPRX_AUX_DPHY_RX_CONTROL1
+-#define DPRX_AUX_DPHY_RX_CONTROL1__DPRX_AUX_RX_PRECHARGE_SKIP__SHIFT 0x0
+-#define DPRX_AUX_DPHY_RX_CONTROL1__DPRX_AUX_RX_TIMEOUT_LEN__SHIFT 0x8
+-#define DPRX_AUX_DPHY_RX_CONTROL1__DPRX_AUX_RX_TIMEOUT_COUNTER_START__SHIFT 0x18
+-#define DPRX_AUX_DPHY_RX_CONTROL1__DPRX_AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL
+-#define DPRX_AUX_DPHY_RX_CONTROL1__DPRX_AUX_RX_TIMEOUT_LEN_MASK 0x0001FF00L
+-#define DPRX_AUX_DPHY_RX_CONTROL1__DPRX_AUX_RX_TIMEOUT_COUNTER_START_MASK 0x1F000000L
+-//DPRX_AUX_DPHY_TX_STATUS
+-#define DPRX_AUX_DPHY_TX_STATUS__DPRX_AUX_TX_ACTIVE__SHIFT 0x0
+-#define DPRX_AUX_DPHY_TX_STATUS__DPRX_AUX_TX_STATE__SHIFT 0x4
+-#define DPRX_AUX_DPHY_TX_STATUS__DPRX_AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10
+-#define DPRX_AUX_DPHY_TX_STATUS__DPRX_AUX_TX_ACTIVE_MASK 0x00000001L
+-#define DPRX_AUX_DPHY_TX_STATUS__DPRX_AUX_TX_STATE_MASK 0x000000F0L
+-#define DPRX_AUX_DPHY_TX_STATUS__DPRX_AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L
+-//DPRX_AUX_DPHY_RX_STATUS
+-#define DPRX_AUX_DPHY_RX_STATUS__DPRX_AUX_RX_STATE__SHIFT 0x0
+-#define DPRX_AUX_DPHY_RX_STATUS__DPRX_AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8
+-#define DPRX_AUX_DPHY_RX_STATUS__DPRX_AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10
+-#define DPRX_AUX_DPHY_RX_STATUS__DPRX_AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15
+-#define DPRX_AUX_DPHY_RX_STATUS__DPRX_AUX_RX_STATE_MASK 0x00000007L
+-#define DPRX_AUX_DPHY_RX_STATUS__DPRX_AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L
+-#define DPRX_AUX_DPHY_RX_STATUS__DPRX_AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L
+-#define DPRX_AUX_DPHY_RX_STATUS__DPRX_AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L
+-//DPRX_AUX_DMCU_HW_INT_STATUS
+-#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_AUX_INT_STATUS__SHIFT 0x0
+-#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_I2C_INT_STATUS__SHIFT 0x1
+-#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG1_TIMEOUT_INT_STATUS__SHIFT 0x2
+-#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG2_TIMEOUT_INT_STATUS__SHIFT 0x3
+-#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG3_TIMEOUT_INT_STATUS__SHIFT 0x4
+-#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG4_TIMEOUT_INT_STATUS__SHIFT 0x5
+-#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_AUX_INT_MASK__SHIFT 0x8
+-#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_I2C_INT_MASK__SHIFT 0x9
+-#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG1_TIMEOUT_INT_MASK__SHIFT 0xa
+-#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG2_TIMEOUT_INT_MASK__SHIFT 0xb
+-#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG3_TIMEOUT_INT_MASK__SHIFT 0xc
+-#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG4_TIMEOUT_INT_MASK__SHIFT 0xd
+-#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_AUX_EVENT_OCCURRED__SHIFT 0x10
+-#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_I2C_EVENT_OCCURRED__SHIFT 0x11
+-#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG1_TIMEOUT_EVENT_OCCURRED__SHIFT 0x12
+-#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG2_TIMEOUT_EVENT_OCCURRED__SHIFT 0x13
+-#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG3_TIMEOUT_EVENT_OCCURRED__SHIFT 0x14
+-#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG4_TIMEOUT_EVENT_OCCURRED__SHIFT 0x15
+-#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_AUX_INT_STATUS_MASK 0x00000001L
+-#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_I2C_INT_STATUS_MASK 0x00000002L
+-#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG1_TIMEOUT_INT_STATUS_MASK 0x00000004L
+-#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG2_TIMEOUT_INT_STATUS_MASK 0x00000008L
+-#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG3_TIMEOUT_INT_STATUS_MASK 0x00000010L
+-#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG4_TIMEOUT_INT_STATUS_MASK 0x00000020L
+-#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_AUX_INT_MASK_MASK 0x00000100L
+-#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_I2C_INT_MASK_MASK 0x00000200L
+-#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG1_TIMEOUT_INT_MASK_MASK 0x00000400L
+-#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG2_TIMEOUT_INT_MASK_MASK 0x00000800L
+-#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG3_TIMEOUT_INT_MASK_MASK 0x00001000L
+-#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG4_TIMEOUT_INT_MASK_MASK 0x00002000L
+-#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_AUX_EVENT_OCCURRED_MASK 0x00010000L
+-#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_I2C_EVENT_OCCURRED_MASK 0x00020000L
+-#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG1_TIMEOUT_EVENT_OCCURRED_MASK 0x00040000L
+-#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG2_TIMEOUT_EVENT_OCCURRED_MASK 0x00080000L
+-#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG3_TIMEOUT_EVENT_OCCURRED_MASK 0x00100000L
+-#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG4_TIMEOUT_EVENT_OCCURRED_MASK 0x00200000L
+-//DPRX_AUX_DMCU_HW_INT_ACK
+-#define DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_AUX_INT_ACK__SHIFT 0x0
+-#define DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_I2C_INT_ACK__SHIFT 0x1
+-#define DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_MSG1_TIMEOUT_INT_ACK__SHIFT 0x2
+-#define DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_MSG2_TIMEOUT_INT_ACK__SHIFT 0x3
+-#define DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_MSG3_TIMEOUT_INT_ACK__SHIFT 0x4
+-#define DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_MSG4_TIMEOUT_INT_ACK__SHIFT 0x5
+-#define DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_AUX_INT_ACK_MASK 0x00000001L
+-#define DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_I2C_INT_ACK_MASK 0x00000002L
+-#define DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_MSG1_TIMEOUT_INT_ACK_MASK 0x00000004L
+-#define DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_MSG2_TIMEOUT_INT_ACK_MASK 0x00000008L
+-#define DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_MSG3_TIMEOUT_INT_ACK_MASK 0x00000010L
+-#define DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_MSG4_TIMEOUT_INT_ACK_MASK 0x00000020L
+-//DPRX_AUX_CPU_TO_DMCU_INTERRUPT1
+-#define DPRX_AUX_CPU_TO_DMCU_INTERRUPT1__DPRX_AUX_CPU_TO_DMCU_INT_TRIGGER__SHIFT 0x0
+-#define DPRX_AUX_CPU_TO_DMCU_INTERRUPT1__DPRX_AUX_CPU_TO_DMCU_INT_TRIGGER_MASK 0x00000001L
+-//DPRX_AUX_CPU_TO_DMCU_INTERRUPT2
+-#define DPRX_AUX_CPU_TO_DMCU_INTERRUPT2__DPRX_AUX_CPU_TO_DMCU_INT_MASK__SHIFT 0x0
+-#define DPRX_AUX_CPU_TO_DMCU_INTERRUPT2__DPRX_AUX_CPU_TO_DMCU_INT_ACK__SHIFT 0x8
+-#define DPRX_AUX_CPU_TO_DMCU_INTERRUPT2__DPRX_AUX_CPU_TO_DMCU_INT_STATUS__SHIFT 0x10
+-#define DPRX_AUX_CPU_TO_DMCU_INTERRUPT2__DPRX_AUX_CPU_TO_DMCU_INT_MASK_MASK 0x00000001L
+-#define DPRX_AUX_CPU_TO_DMCU_INTERRUPT2__DPRX_AUX_CPU_TO_DMCU_INT_ACK_MASK 0x00000100L
+-#define DPRX_AUX_CPU_TO_DMCU_INTERRUPT2__DPRX_AUX_CPU_TO_DMCU_INT_STATUS_MASK 0x00010000L
+-//DPRX_AUX_DMCU_TO_CPU_INTERRUPT1
+-#define DPRX_AUX_DMCU_TO_CPU_INTERRUPT1__DPRX_AUX_DMCU_TO_CPU_INT_TRIGGER__SHIFT 0x0
+-#define DPRX_AUX_DMCU_TO_CPU_INTERRUPT1__DPRX_AUX_DMCU_TO_CPU_INT_TRIGGER_MASK 0x00000001L
+-//DPRX_AUX_DMCU_TO_CPU_INTERRUPT2
+-#define DPRX_AUX_DMCU_TO_CPU_INTERRUPT2__DPRX_AUX_DMCU_TO_CPU_INT_MASK__SHIFT 0x0
+-#define DPRX_AUX_DMCU_TO_CPU_INTERRUPT2__DPRX_AUX_DMCU_TO_CPU_INT_TYPE__SHIFT 0x1
+-#define DPRX_AUX_DMCU_TO_CPU_INTERRUPT2__DPRX_AUX_DMCU_TO_CPU_INT_ACK__SHIFT 0x8
+-#define DPRX_AUX_DMCU_TO_CPU_INTERRUPT2__DPRX_AUX_DMCU_TO_CPU_INT_OCCURRED__SHIFT 0x10
+-#define DPRX_AUX_DMCU_TO_CPU_INTERRUPT2__DPRX_AUX_DMCU_TO_CPU_INT_MASK_MASK 0x00000001L
+-#define DPRX_AUX_DMCU_TO_CPU_INTERRUPT2__DPRX_AUX_DMCU_TO_CPU_INT_TYPE_MASK 0x00000002L
+-#define DPRX_AUX_DMCU_TO_CPU_INTERRUPT2__DPRX_AUX_DMCU_TO_CPU_INT_ACK_MASK 0x00000100L
+-#define DPRX_AUX_DMCU_TO_CPU_INTERRUPT2__DPRX_AUX_DMCU_TO_CPU_INT_OCCURRED_MASK 0x00010000L
+-//DPRX_AUX_AUX_BUF_INDEX
+-#define DPRX_AUX_AUX_BUF_INDEX__DPRX_AUX_AUX_BUF_INDEX__SHIFT 0x0
+-#define DPRX_AUX_AUX_BUF_INDEX__DPRX_AUX_AUX_BUF_INDEX_MASK 0x0000007FL
+-//DPRX_AUX_AUX_BUF_DATA
+-#define DPRX_AUX_AUX_BUF_DATA__DPRX_AUX_AUX_BUF_DATA__SHIFT 0x0
+-#define DPRX_AUX_AUX_BUF_DATA__DPRX_AUX_AUX_BUF_DATA_MASK 0xFFFFFFFFL
+-//DPRX_AUX_EDID_INDEX
+-#define DPRX_AUX_EDID_INDEX__DPRX_AUX_EDID_INDEX__SHIFT 0x0
+-#define DPRX_AUX_EDID_INDEX__DPRX_AUX_EDID_MODE__SHIFT 0x10
+-#define DPRX_AUX_EDID_INDEX__DPRX_AUX_EDID_INDEX_MASK 0x000003FFL
+-#define DPRX_AUX_EDID_INDEX__DPRX_AUX_EDID_MODE_MASK 0x00010000L
+-//DPRX_AUX_EDID_DATA
+-#define DPRX_AUX_EDID_DATA__DPRX_AUX_EDID_DATA__SHIFT 0x0
+-#define DPRX_AUX_EDID_DATA__DPRX_AUX_EDID_DATA_MASK 0xFFFFFFFFL
+-//DPRX_AUX_DPCD_INDEX1
+-#define DPRX_AUX_DPCD_INDEX1__DPRX_AUX_DPCD_INDEX1__SHIFT 0x0
+-#define DPRX_AUX_DPCD_INDEX1__DPRX_AUX_DPCD_MODE1__SHIFT 0x10
+-#define DPRX_AUX_DPCD_INDEX1__DPRX_AUX_DPCD_INDEX1_MASK 0x000007FFL
+-#define DPRX_AUX_DPCD_INDEX1__DPRX_AUX_DPCD_MODE1_MASK 0x00010000L
+-//DPRX_AUX_DPCD_DATA1
+-#define DPRX_AUX_DPCD_DATA1__DPRX_AUX_DPCD_DATA1__SHIFT 0x0
+-#define DPRX_AUX_DPCD_DATA1__DPRX_AUX_DPCD_DATA1_MASK 0xFFFFFFFFL
+-//DPRX_AUX_DPCD_INDEX2
+-#define DPRX_AUX_DPCD_INDEX2__DPRX_AUX_DPCD_INDEX2__SHIFT 0x0
+-#define DPRX_AUX_DPCD_INDEX2__DPRX_AUX_DPCD_MODE2__SHIFT 0x10
+-#define DPRX_AUX_DPCD_INDEX2__DPRX_AUX_DPCD_INDEX2_MASK 0x000007FFL
+-#define DPRX_AUX_DPCD_INDEX2__DPRX_AUX_DPCD_MODE2_MASK 0x00010000L
+-//DPRX_AUX_DPCD_DATA2
+-#define DPRX_AUX_DPCD_DATA2__DPRX_AUX_DPCD_DATA2__SHIFT 0x0
+-#define DPRX_AUX_DPCD_DATA2__DPRX_AUX_DPCD_DATA2_MASK 0xFFFFFFFFL
+-//DPRX_AUX_MSG_INDEX1
+-#define DPRX_AUX_MSG_INDEX1__DPRX_AUX_MSG_INDEX1__SHIFT 0x0
+-#define DPRX_AUX_MSG_INDEX1__DPRX_AUX_MSG_MODE1__SHIFT 0x10
+-#define DPRX_AUX_MSG_INDEX1__DPRX_AUX_MSG_INDEX1_MASK 0x000003FFL
+-#define DPRX_AUX_MSG_INDEX1__DPRX_AUX_MSG_MODE1_MASK 0x00010000L
+-//DPRX_AUX_MSG_DATA1
+-#define DPRX_AUX_MSG_DATA1__DPRX_AUX_MSG_DATA1__SHIFT 0x0
+-#define DPRX_AUX_MSG_DATA1__DPRX_AUX_MSG_DATA1_MASK 0xFFFFFFFFL
+-//DPRX_AUX_MSG_INDEX2
+-#define DPRX_AUX_MSG_INDEX2__DPRX_AUX_MSG_INDEX2__SHIFT 0x0
+-#define DPRX_AUX_MSG_INDEX2__DPRX_AUX_MSG_MODE2__SHIFT 0x10
+-#define DPRX_AUX_MSG_INDEX2__DPRX_AUX_MSG_INDEX2_MASK 0x000003FFL
+-#define DPRX_AUX_MSG_INDEX2__DPRX_AUX_MSG_MODE2_MASK 0x00010000L
+-//DPRX_AUX_MSG_DATA2
+-#define DPRX_AUX_MSG_DATA2__DPRX_AUX_MSG_DATA2__SHIFT 0x0
+-#define DPRX_AUX_MSG_DATA2__DPRX_AUX_MSG_DATA2_MASK 0xFFFFFFFFL
+-//DPRX_AUX_KSV_INDEX1
+-#define DPRX_AUX_KSV_INDEX1__DPRX_AUX_KSV_INDEX1__SHIFT 0x0
+-#define DPRX_AUX_KSV_INDEX1__DPRX_AUX_KSV_MODE1__SHIFT 0x10
+-#define DPRX_AUX_KSV_INDEX1__DPRX_AUX_KSV_INDEX1_MASK 0x000003FFL
+-#define DPRX_AUX_KSV_INDEX1__DPRX_AUX_KSV_MODE1_MASK 0x00010000L
+-//DPRX_AUX_KSV_DATA1
+-#define DPRX_AUX_KSV_DATA1__DPRX_AUX_KSV_DATA1__SHIFT 0x0
+-#define DPRX_AUX_KSV_DATA1__DPRX_AUX_KSV_DATA1_MASK 0xFFFFFFFFL
+-//DPRX_AUX_KSV_INDEX2
+-#define DPRX_AUX_KSV_INDEX2__DPRX_AUX_KSV_INDEX2__SHIFT 0x0
+-#define DPRX_AUX_KSV_INDEX2__DPRX_AUX_KSV_MODE2__SHIFT 0x10
+-#define DPRX_AUX_KSV_INDEX2__DPRX_AUX_KSV_INDEX2_MASK 0x000003FFL
+-#define DPRX_AUX_KSV_INDEX2__DPRX_AUX_KSV_MODE2_MASK 0x00010000L
+-//DPRX_AUX_KSV_DATA2
+-#define DPRX_AUX_KSV_DATA2__DPRX_AUX_KSV_DATA2__SHIFT 0x0
+-#define DPRX_AUX_KSV_DATA2__DPRX_AUX_KSV_DATA2_MASK 0xFFFFFFFFL
+-//DPRX_AUX_MSG_TIMEOUT_CONTROL
+-#define DPRX_AUX_MSG_TIMEOUT_CONTROL__DPRX_AUX_MSG_TIMEOUT_LEN__SHIFT 0x0
+-#define DPRX_AUX_MSG_TIMEOUT_CONTROL__DPRX_AUX_MSG_TIMEOUT_LEN_MASK 0x000000FFL
+-//DPRX_AUX_MSG_BUF_CONTROL1
+-#define DPRX_AUX_MSG_BUF_CONTROL1__DPRX_AUX_MSG_REP_WRITE_REQ1__SHIFT 0x0
+-#define DPRX_AUX_MSG_BUF_CONTROL1__DPRX_AUX_MSG_REP_WRITE_GNT1__SHIFT 0x1
+-#define DPRX_AUX_MSG_BUF_CONTROL1__DPRX_AUX_MSG_REP_WRITE_REQ1_MASK 0x00000001L
+-#define DPRX_AUX_MSG_BUF_CONTROL1__DPRX_AUX_MSG_REP_WRITE_GNT1_MASK 0x00000002L
+-//DPRX_AUX_MSG_BUF_CONTROL2
+-#define DPRX_AUX_MSG_BUF_CONTROL2__DPRX_AUX_MSG_REP_WRITE_REQ2__SHIFT 0x0
+-#define DPRX_AUX_MSG_BUF_CONTROL2__DPRX_AUX_MSG_REP_WRITE_GNT2__SHIFT 0x1
+-#define DPRX_AUX_MSG_BUF_CONTROL2__DPRX_AUX_MSG_REP_WRITE_REQ2_MASK 0x00000001L
+-#define DPRX_AUX_MSG_BUF_CONTROL2__DPRX_AUX_MSG_REP_WRITE_GNT2_MASK 0x00000002L
+-//DPRX_AUX_SCRATCH1
+-#define DPRX_AUX_SCRATCH1__DPRX_AUX_SCRATCH1__SHIFT 0x0
+-#define DPRX_AUX_SCRATCH1__DPRX_AUX_SCRATCH1_MASK 0xFFFFFFFFL
+-//DPRX_AUX_SCRATCH2
+-#define DPRX_AUX_SCRATCH2__DPRX_AUX_SCRATCH2__SHIFT 0x0
+-#define DPRX_AUX_SCRATCH2__DPRX_AUX_SCRATCH2_MASK 0xFFFFFFFFL
+-//DPRX_AUX_MSG1_PENDING
+-#define DPRX_AUX_MSG1_PENDING__DPRX_AUX_MSG1_PENDING__SHIFT 0x0
+-#define DPRX_AUX_MSG1_PENDING__DPRX_AUX_MSG1_PENDING_MASK 0x00000001L
+-//DPRX_AUX_MSG2_PENDING
+-#define DPRX_AUX_MSG2_PENDING__DPRX_AUX_MSG2_PENDING__SHIFT 0x0
+-#define DPRX_AUX_MSG2_PENDING__DPRX_AUX_MSG2_PENDING_MASK 0x00000001L
+-//DPRX_AUX_MSG3_PENDING
+-#define DPRX_AUX_MSG3_PENDING__DPRX_AUX_MSG3_PENDING__SHIFT 0x0
+-#define DPRX_AUX_MSG3_PENDING__DPRX_AUX_MSG3_PENDING_MASK 0x00000001L
+-//DPRX_AUX_MSG4_PENDING
+-#define DPRX_AUX_MSG4_PENDING__DPRX_AUX_MSG4_PENDING__SHIFT 0x0
+-#define DPRX_AUX_MSG4_PENDING__DPRX_AUX_MSG4_PENDING_MASK 0x00000001L
+-//DPRX_DPHY_DPCD_LANE_COUNT_SET
+-#define DPRX_DPHY_DPCD_LANE_COUNT_SET__LANE_COUNT_SET__SHIFT 0x0
+-#define DPRX_DPHY_DPCD_LANE_COUNT_SET__LANE_COUNT_SET_MASK 0x0000001FL
+-//DPRX_DPHY_DPCD_TRAINING_PATTERN_SET
+-#define DPRX_DPHY_DPCD_TRAINING_PATTERN_SET__TRAINING_PATTERN_SET__SHIFT 0x0
+-#define DPRX_DPHY_DPCD_TRAINING_PATTERN_SET__TRAINING_PATTERN_SET_MASK 0x00000003L
+-//DPRX_DPHY_DPCD_MSTM_CTRL
+-#define DPRX_DPHY_DPCD_MSTM_CTRL__MST_EN__SHIFT 0x0
+-#define DPRX_DPHY_DPCD_MSTM_CTRL__MST_EN_MASK 0x00000001L
+-//DPRX_DPHY_DPCD_LINK_QUAL_LANE0_SET
+-#define DPRX_DPHY_DPCD_LINK_QUAL_LANE0_SET__LANE0_LINK_QUAL_PATTERN_SET__SHIFT 0x0
+-#define DPRX_DPHY_DPCD_LINK_QUAL_LANE0_SET__LANE0_LINK_QUAL_PATTERN_SET_MASK 0x00000007L
+-//DPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS
+-#define DPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS__LANE0_LINK_QUAL_PATTERN_DETECT__SHIFT 0x0
+-#define DPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS__LANE0_HBR2_COMPL_EYE_PATTERN_DETECT__SHIFT 0x3
+-#define DPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS__LANE0_LINK_QUAL_PATTERN_DETECT_MASK 0x00000007L
+-#define DPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS__LANE0_HBR2_COMPL_EYE_PATTERN_DETECT_MASK 0x00000018L
+-//DPRX_DPHY_DPCD_LINK_QUAL_LANE1_SET
+-#define DPRX_DPHY_DPCD_LINK_QUAL_LANE1_SET__LANE1_LINK_QUAL_PATTERN_SET__SHIFT 0x0
+-#define DPRX_DPHY_DPCD_LINK_QUAL_LANE1_SET__LANE1_LINK_QUAL_PATTERN_SET_MASK 0x00000007L
+-//DPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS
+-#define DPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS__LANE1_LINK_QUAL_PATTERN_DETECT__SHIFT 0x0
+-#define DPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS__LANE1_HBR2_COMPL_EYE_PATTERN_DETECT__SHIFT 0x3
+-#define DPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS__LANE1_LINK_QUAL_PATTERN_DETECT_MASK 0x00000007L
+-#define DPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS__LANE1_HBR2_COMPL_EYE_PATTERN_DETECT_MASK 0x00000018L
+-//DPRX_DPHY_DPCD_LINK_QUAL_LANE2_SET
+-#define DPRX_DPHY_DPCD_LINK_QUAL_LANE2_SET__LANE2_LINK_QUAL_PATTERN_SET__SHIFT 0x0
+-#define DPRX_DPHY_DPCD_LINK_QUAL_LANE2_SET__LANE2_LINK_QUAL_PATTERN_SET_MASK 0x00000007L
+-//DPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS
+-#define DPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS__LANE2_LINK_QUAL_PATTERN_DETECT__SHIFT 0x0
+-#define DPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS__LANE2_HBR2_COMPL_EYE_PATTERN_DETECT__SHIFT 0x3
+-#define DPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS__LANE2_LINK_QUAL_PATTERN_DETECT_MASK 0x00000007L
+-#define DPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS__LANE2_HBR2_COMPL_EYE_PATTERN_DETECT_MASK 0x00000018L
+-//DPRX_DPHY_DPCD_LINK_QUAL_LANE3_SET
+-#define DPRX_DPHY_DPCD_LINK_QUAL_LANE3_SET__LANE3_LINK_QUAL_PATTERN_SET__SHIFT 0x0
+-#define DPRX_DPHY_DPCD_LINK_QUAL_LANE3_SET__LANE3_LINK_QUAL_PATTERN_SET_MASK 0x00000007L
+-//DPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS
+-#define DPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS__LANE3_LINK_QUAL_PATTERN_DETECT__SHIFT 0x0
+-#define DPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS__LANE3_HBR2_COMPL_EYE_PATTERN_DETECT__SHIFT 0x3
+-#define DPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS__LANE3_LINK_QUAL_PATTERN_DETECT_MASK 0x00000007L
+-#define DPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS__LANE3_HBR2_COMPL_EYE_PATTERN_DETECT_MASK 0x00000018L
+-//DPRX_DPHY_READY
+-#define DPRX_DPHY_READY__CP_READY__SHIFT 0x0
+-#define DPRX_DPHY_READY__ACT_READY__SHIFT 0x1
+-#define DPRX_DPHY_READY__SDOUT_READY__SHIFT 0x2
+-#define DPRX_DPHY_READY__ACT_READY_CLR__SHIFT 0x3
+-#define DPRX_DPHY_READY__MVOTE_DATA_ERROR__SHIFT 0x4
+-#define DPRX_DPHY_READY__MVOTE_DATA_ERROR_CLR__SHIFT 0x5
+-#define DPRX_DPHY_READY__MVOTE_KCODE_ERROR__SHIFT 0x6
+-#define DPRX_DPHY_READY__MVOTE_KCODE_ERROR_CLR__SHIFT 0x7
+-#define DPRX_DPHY_READY__CP_READY_MASK 0x00000001L
+-#define DPRX_DPHY_READY__ACT_READY_MASK 0x00000002L
+-#define DPRX_DPHY_READY__SDOUT_READY_MASK 0x00000004L
+-#define DPRX_DPHY_READY__ACT_READY_CLR_MASK 0x00000008L
+-#define DPRX_DPHY_READY__MVOTE_DATA_ERROR_MASK 0x00000010L
+-#define DPRX_DPHY_READY__MVOTE_DATA_ERROR_CLR_MASK 0x00000020L
+-#define DPRX_DPHY_READY__MVOTE_KCODE_ERROR_MASK 0x00000040L
+-#define DPRX_DPHY_READY__MVOTE_KCODE_ERROR_CLR_MASK 0x00000080L
+-//DPRX_DPHY_COMMA_STATUS
+-#define DPRX_DPHY_COMMA_STATUS__LANE0_COMMA_LOCKED__SHIFT 0x0
+-#define DPRX_DPHY_COMMA_STATUS__LANE1_COMMA_LOCKED__SHIFT 0x1
+-#define DPRX_DPHY_COMMA_STATUS__LANE2_COMMA_LOCKED__SHIFT 0x2
+-#define DPRX_DPHY_COMMA_STATUS__LANE3_COMMA_LOCKED__SHIFT 0x3
+-#define DPRX_DPHY_COMMA_STATUS__LANE0_SR_LOCKED__SHIFT 0x4
+-#define DPRX_DPHY_COMMA_STATUS__LANE1_SR_LOCKED__SHIFT 0x5
+-#define DPRX_DPHY_COMMA_STATUS__LANE2_SR_LOCKED__SHIFT 0x6
+-#define DPRX_DPHY_COMMA_STATUS__LANE3_SR_LOCKED__SHIFT 0x7
+-#define DPRX_DPHY_COMMA_STATUS__LANE0_COMMA_LOCKED_MASK 0x00000001L
+-#define DPRX_DPHY_COMMA_STATUS__LANE1_COMMA_LOCKED_MASK 0x00000002L
+-#define DPRX_DPHY_COMMA_STATUS__LANE2_COMMA_LOCKED_MASK 0x00000004L
+-#define DPRX_DPHY_COMMA_STATUS__LANE3_COMMA_LOCKED_MASK 0x00000008L
+-#define DPRX_DPHY_COMMA_STATUS__LANE0_SR_LOCKED_MASK 0x00000010L
+-#define DPRX_DPHY_COMMA_STATUS__LANE1_SR_LOCKED_MASK 0x00000020L
+-#define DPRX_DPHY_COMMA_STATUS__LANE2_SR_LOCKED_MASK 0x00000040L
+-#define DPRX_DPHY_COMMA_STATUS__LANE3_SR_LOCKED_MASK 0x00000080L
+-//DPRX_DPHY_LANE_ALIGN_ERROR_STATUS_UPDATED
+-#define DPRX_DPHY_LANE_ALIGN_ERROR_STATUS_UPDATED__LANE0_INTERLANE_ALIGN_ERROR_COUNT__SHIFT 0x0
+-#define DPRX_DPHY_LANE_ALIGN_ERROR_STATUS_UPDATED__LANE0_INTERLANE_ALIGN_ERROR_COUNT_MASK 0x0000000FL
+-//DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED
+-#define DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED__INTERLANE_ALIGN_DONE__SHIFT 0x0
+-#define DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED__INTERLANE_ALIGN_CHECK_DONE__SHIFT 0x1
+-#define DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED__INTERLANE_ALIGN_FIFO_LEVEL__SHIFT 0x2
+-#define DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED__INTERLANE_ALIGN_STATE__SHIFT 0x19
+-#define DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED__INTERLANE_ALIGN_WAIT_COUNT__SHIFT 0x1b
+-#define DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED__INTERLANE_ALIGN_DONE_MASK 0x00000001L
+-#define DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED__INTERLANE_ALIGN_CHECK_DONE_MASK 0x00000002L
+-#define DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED__INTERLANE_ALIGN_FIFO_LEVEL_MASK 0x0003FFFCL
+-#define DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED__INTERLANE_ALIGN_STATE_MASK 0x06000000L
+-#define DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED__INTERLANE_ALIGN_WAIT_COUNT_MASK 0xF8000000L
+-//DPRX_DPHY_ERROR_THRESH_A_LANE0
+-#define DPRX_DPHY_ERROR_THRESH_A_LANE0__LANE0_SYMBOL_ERROR_COUNT_THRESH__SHIFT 0x0
+-#define DPRX_DPHY_ERROR_THRESH_A_LANE0__LANE0_DISPARITY_ERROR_COUNT_THRESH__SHIFT 0x8
+-#define DPRX_DPHY_ERROR_THRESH_A_LANE0__LANE0_TEST_PATTERN_ERROR_THRESH__SHIFT 0x18
+-#define DPRX_DPHY_ERROR_THRESH_A_LANE0__LANE0_SYMBOL_ERROR_COUNT_THRESH_MASK 0x000000FFL
+-#define DPRX_DPHY_ERROR_THRESH_A_LANE0__LANE0_DISPARITY_ERROR_COUNT_THRESH_MASK 0x0000FF00L
+-#define DPRX_DPHY_ERROR_THRESH_A_LANE0__LANE0_TEST_PATTERN_ERROR_THRESH_MASK 0xFF000000L
+-//DPRX_DPHY_ERROR_COUNT_A_LANE0
+-#define DPRX_DPHY_ERROR_COUNT_A_LANE0__LANE0_SYMBOL_ERROR_COUNT__SHIFT 0x0
+-#define DPRX_DPHY_ERROR_COUNT_A_LANE0__LANE0_SYMBOL_ERROR_COUNT_VALID__SHIFT 0xf
+-#define DPRX_DPHY_ERROR_COUNT_A_LANE0__LANE0_DISPARITY_ERROR_COUNT__SHIFT 0x10
+-#define DPRX_DPHY_ERROR_COUNT_A_LANE0__LANE0_DISPARITY_ERROR_COUNT_VALID__SHIFT 0x1f
+-#define DPRX_DPHY_ERROR_COUNT_A_LANE0__LANE0_SYMBOL_ERROR_COUNT_MASK 0x00007FFFL
+-#define DPRX_DPHY_ERROR_COUNT_A_LANE0__LANE0_SYMBOL_ERROR_COUNT_VALID_MASK 0x00008000L
+-#define DPRX_DPHY_ERROR_COUNT_A_LANE0__LANE0_DISPARITY_ERROR_COUNT_MASK 0x7FFF0000L
+-#define DPRX_DPHY_ERROR_COUNT_A_LANE0__LANE0_DISPARITY_ERROR_COUNT_VALID_MASK 0x80000000L
+-//DPRX_DPHY_ERROR_COUNT_B_LANE0
+-#define DPRX_DPHY_ERROR_COUNT_B_LANE0__LANE0_TEST_PATTERN_ERROR_COUNT__SHIFT 0x10
+-#define DPRX_DPHY_ERROR_COUNT_B_LANE0__LANE0_TEST_PATTERN_ERROR_COUNT_VALID__SHIFT 0x1f
+-#define DPRX_DPHY_ERROR_COUNT_B_LANE0__LANE0_TEST_PATTERN_ERROR_COUNT_MASK 0x7FFF0000L
+-#define DPRX_DPHY_ERROR_COUNT_B_LANE0__LANE0_TEST_PATTERN_ERROR_COUNT_VALID_MASK 0x80000000L
+-//DPRX_DPHY_ERROR_COUNT_C_LANE0
+-#define DPRX_DPHY_ERROR_COUNT_C_LANE0__LANE0_SYMBOL_ERROR_COUNT_CLR__SHIFT 0x1b
+-#define DPRX_DPHY_ERROR_COUNT_C_LANE0__LANE0_DISPARITY_ERROR_COUNT_CLR__SHIFT 0x1c
+-#define DPRX_DPHY_ERROR_COUNT_C_LANE0__LANE0_TEST_PATTERN_ERROR_COUNT_CLR__SHIFT 0x1e
+-#define DPRX_DPHY_ERROR_COUNT_C_LANE0__LANE0_SYMBOL_ERROR_COUNT_CLR_MASK 0x08000000L
+-#define DPRX_DPHY_ERROR_COUNT_C_LANE0__LANE0_DISPARITY_ERROR_COUNT_CLR_MASK 0x10000000L
+-#define DPRX_DPHY_ERROR_COUNT_C_LANE0__LANE0_TEST_PATTERN_ERROR_COUNT_CLR_MASK 0x40000000L
+-//DPRX_DPHY_ERROR_THRESH_A_LANE1
+-#define DPRX_DPHY_ERROR_THRESH_A_LANE1__LANE1_SYMBOL_ERROR_COUNT_THRESH__SHIFT 0x0
+-#define DPRX_DPHY_ERROR_THRESH_A_LANE1__LANE1_DISPARITY_ERROR_COUNT_THRESH__SHIFT 0x8
+-#define DPRX_DPHY_ERROR_THRESH_A_LANE1__LANE1_TEST_PATTERN_ERROR_THRESH__SHIFT 0x18
+-#define DPRX_DPHY_ERROR_THRESH_A_LANE1__LANE1_SYMBOL_ERROR_COUNT_THRESH_MASK 0x000000FFL
+-#define DPRX_DPHY_ERROR_THRESH_A_LANE1__LANE1_DISPARITY_ERROR_COUNT_THRESH_MASK 0x0000FF00L
+-#define DPRX_DPHY_ERROR_THRESH_A_LANE1__LANE1_TEST_PATTERN_ERROR_THRESH_MASK 0xFF000000L
+-//DPRX_DPHY_ERROR_COUNT_A_LANE1
+-#define DPRX_DPHY_ERROR_COUNT_A_LANE1__LANE1_SYMBOL_ERROR_COUNT__SHIFT 0x0
+-#define DPRX_DPHY_ERROR_COUNT_A_LANE1__LANE1_SYMBOL_ERROR_COUNT_VALID__SHIFT 0xf
+-#define DPRX_DPHY_ERROR_COUNT_A_LANE1__LANE1_DISPARITY_ERROR_COUNT__SHIFT 0x10
+-#define DPRX_DPHY_ERROR_COUNT_A_LANE1__LANE1_DISPARITY_ERROR_COUNT_VALID__SHIFT 0x1f
+-#define DPRX_DPHY_ERROR_COUNT_A_LANE1__LANE1_SYMBOL_ERROR_COUNT_MASK 0x00007FFFL
+-#define DPRX_DPHY_ERROR_COUNT_A_LANE1__LANE1_SYMBOL_ERROR_COUNT_VALID_MASK 0x00008000L
+-#define DPRX_DPHY_ERROR_COUNT_A_LANE1__LANE1_DISPARITY_ERROR_COUNT_MASK 0x7FFF0000L
+-#define DPRX_DPHY_ERROR_COUNT_A_LANE1__LANE1_DISPARITY_ERROR_COUNT_VALID_MASK 0x80000000L
+-//DPRX_DPHY_ERROR_COUNT_B_LANE1
+-#define DPRX_DPHY_ERROR_COUNT_B_LANE1__LANE1_TEST_PATTERN_ERROR_COUNT__SHIFT 0x10
+-#define DPRX_DPHY_ERROR_COUNT_B_LANE1__LANE1_TEST_PATTERN_ERROR_COUNT_VALID__SHIFT 0x1f
+-#define DPRX_DPHY_ERROR_COUNT_B_LANE1__LANE1_TEST_PATTERN_ERROR_COUNT_MASK 0x7FFF0000L
+-#define DPRX_DPHY_ERROR_COUNT_B_LANE1__LANE1_TEST_PATTERN_ERROR_COUNT_VALID_MASK 0x80000000L
+-//DPRX_DPHY_ERROR_COUNT_C_LANE1
+-#define DPRX_DPHY_ERROR_COUNT_C_LANE1__LANE1_SYMBOL_ERROR_COUNT_CLR__SHIFT 0x1b
+-#define DPRX_DPHY_ERROR_COUNT_C_LANE1__LANE1_DISPARITY_ERROR_COUNT_CLR__SHIFT 0x1c
+-#define DPRX_DPHY_ERROR_COUNT_C_LANE1__LANE1_TEST_PATTERN_ERROR_COUNT_CLR__SHIFT 0x1e
+-#define DPRX_DPHY_ERROR_COUNT_C_LANE1__LANE1_SYMBOL_ERROR_COUNT_CLR_MASK 0x08000000L
+-#define DPRX_DPHY_ERROR_COUNT_C_LANE1__LANE1_DISPARITY_ERROR_COUNT_CLR_MASK 0x10000000L
+-#define DPRX_DPHY_ERROR_COUNT_C_LANE1__LANE1_TEST_PATTERN_ERROR_COUNT_CLR_MASK 0x40000000L
+-//DPRX_DPHY_ERROR_THRESH_A_LANE2
+-#define DPRX_DPHY_ERROR_THRESH_A_LANE2__LANE2_SYMBOL_ERROR_COUNT_THRESH__SHIFT 0x0
+-#define DPRX_DPHY_ERROR_THRESH_A_LANE2__LANE2_DISPARITY_ERROR_COUNT_THRESH__SHIFT 0x8
+-#define DPRX_DPHY_ERROR_THRESH_A_LANE2__LANE2_TEST_PATTERN_ERROR_THRESH__SHIFT 0x18
+-#define DPRX_DPHY_ERROR_THRESH_A_LANE2__LANE2_SYMBOL_ERROR_COUNT_THRESH_MASK 0x000000FFL
+-#define DPRX_DPHY_ERROR_THRESH_A_LANE2__LANE2_DISPARITY_ERROR_COUNT_THRESH_MASK 0x0000FF00L
+-#define DPRX_DPHY_ERROR_THRESH_A_LANE2__LANE2_TEST_PATTERN_ERROR_THRESH_MASK 0xFF000000L
+-//DPRX_DPHY_ERROR_COUNT_A_LANE2
+-#define DPRX_DPHY_ERROR_COUNT_A_LANE2__LANE2_SYMBOL_ERROR_COUNT__SHIFT 0x0
+-#define DPRX_DPHY_ERROR_COUNT_A_LANE2__LANE2_SYMBOL_ERROR_COUNT_VALID__SHIFT 0xf
+-#define DPRX_DPHY_ERROR_COUNT_A_LANE2__LANE2_DISPARITY_ERROR_COUNT__SHIFT 0x10
+-#define DPRX_DPHY_ERROR_COUNT_A_LANE2__LANE2_DISPARITY_ERROR_COUNT_VALID__SHIFT 0x1f
+-#define DPRX_DPHY_ERROR_COUNT_A_LANE2__LANE2_SYMBOL_ERROR_COUNT_MASK 0x00007FFFL
+-#define DPRX_DPHY_ERROR_COUNT_A_LANE2__LANE2_SYMBOL_ERROR_COUNT_VALID_MASK 0x00008000L
+-#define DPRX_DPHY_ERROR_COUNT_A_LANE2__LANE2_DISPARITY_ERROR_COUNT_MASK 0x7FFF0000L
+-#define DPRX_DPHY_ERROR_COUNT_A_LANE2__LANE2_DISPARITY_ERROR_COUNT_VALID_MASK 0x80000000L
+-//DPRX_DPHY_ERROR_COUNT_B_LANE2
+-#define DPRX_DPHY_ERROR_COUNT_B_LANE2__LANE2_TEST_PATTERN_ERROR_COUNT__SHIFT 0x10
+-#define DPRX_DPHY_ERROR_COUNT_B_LANE2__LANE2_TEST_PATTERN_ERROR_COUNT_VALID__SHIFT 0x1f
+-#define DPRX_DPHY_ERROR_COUNT_B_LANE2__LANE2_TEST_PATTERN_ERROR_COUNT_MASK 0x7FFF0000L
+-#define DPRX_DPHY_ERROR_COUNT_B_LANE2__LANE2_TEST_PATTERN_ERROR_COUNT_VALID_MASK 0x80000000L
+-//DPRX_DPHY_ERROR_COUNT_C_LANE2
+-#define DPRX_DPHY_ERROR_COUNT_C_LANE2__LANE2_SYMBOL_ERROR_COUNT_CLR__SHIFT 0x1b
+-#define DPRX_DPHY_ERROR_COUNT_C_LANE2__LANE2_DISPARITY_ERROR_COUNT_CLR__SHIFT 0x1c
+-#define DPRX_DPHY_ERROR_COUNT_C_LANE2__LANE2_TEST_PATTERN_ERROR_COUNT_CLR__SHIFT 0x1e
+-#define DPRX_DPHY_ERROR_COUNT_C_LANE2__LANE2_SYMBOL_ERROR_COUNT_CLR_MASK 0x08000000L
+-#define DPRX_DPHY_ERROR_COUNT_C_LANE2__LANE2_DISPARITY_ERROR_COUNT_CLR_MASK 0x10000000L
+-#define DPRX_DPHY_ERROR_COUNT_C_LANE2__LANE2_TEST_PATTERN_ERROR_COUNT_CLR_MASK 0x40000000L
+-//DPRX_DPHY_ERROR_THRESH_A_LANE3
+-#define DPRX_DPHY_ERROR_THRESH_A_LANE3__LANE3_SYMBOL_ERROR_COUNT_THRESH__SHIFT 0x0
+-#define DPRX_DPHY_ERROR_THRESH_A_LANE3__LANE3_DISPARITY_ERROR_COUNT_THRESH__SHIFT 0x8
+-#define DPRX_DPHY_ERROR_THRESH_A_LANE3__LANE3_TEST_PATTERN_ERROR_THRESH__SHIFT 0x18
+-#define DPRX_DPHY_ERROR_THRESH_A_LANE3__LANE3_SYMBOL_ERROR_COUNT_THRESH_MASK 0x000000FFL
+-#define DPRX_DPHY_ERROR_THRESH_A_LANE3__LANE3_DISPARITY_ERROR_COUNT_THRESH_MASK 0x0000FF00L
+-#define DPRX_DPHY_ERROR_THRESH_A_LANE3__LANE3_TEST_PATTERN_ERROR_THRESH_MASK 0xFF000000L
+-//DPRX_DPHY_ERROR_COUNT_A_LANE3
+-#define DPRX_DPHY_ERROR_COUNT_A_LANE3__LANE3_SYMBOL_ERROR_COUNT__SHIFT 0x0
+-#define DPRX_DPHY_ERROR_COUNT_A_LANE3__LANE3_SYMBOL_ERROR_COUNT_VALID__SHIFT 0xf
+-#define DPRX_DPHY_ERROR_COUNT_A_LANE3__LANE3_DISPARITY_ERROR_COUNT__SHIFT 0x10
+-#define DPRX_DPHY_ERROR_COUNT_A_LANE3__LANE3_DISPARITY_ERROR_COUNT_VALID__SHIFT 0x1f
+-#define DPRX_DPHY_ERROR_COUNT_A_LANE3__LANE3_SYMBOL_ERROR_COUNT_MASK 0x00007FFFL
+-#define DPRX_DPHY_ERROR_COUNT_A_LANE3__LANE3_SYMBOL_ERROR_COUNT_VALID_MASK 0x00008000L
+-#define DPRX_DPHY_ERROR_COUNT_A_LANE3__LANE3_DISPARITY_ERROR_COUNT_MASK 0x7FFF0000L
+-#define DPRX_DPHY_ERROR_COUNT_A_LANE3__LANE3_DISPARITY_ERROR_COUNT_VALID_MASK 0x80000000L
+-//DPRX_DPHY_ERROR_COUNT_B_LANE3
+-#define DPRX_DPHY_ERROR_COUNT_B_LANE3__LANE3_TEST_PATTERN_ERROR_COUNT__SHIFT 0x10
+-#define DPRX_DPHY_ERROR_COUNT_B_LANE3__LANE3_TEST_PATTERN_ERROR_COUNT_VALID__SHIFT 0x1f
+-#define DPRX_DPHY_ERROR_COUNT_B_LANE3__LANE3_TEST_PATTERN_ERROR_COUNT_MASK 0x7FFF0000L
+-#define DPRX_DPHY_ERROR_COUNT_B_LANE3__LANE3_TEST_PATTERN_ERROR_COUNT_VALID_MASK 0x80000000L
+-//DPRX_DPHY_ERROR_COUNT_C_LANE3
+-#define DPRX_DPHY_ERROR_COUNT_C_LANE3__LANE3_SYMBOL_ERROR_COUNT_CLR__SHIFT 0x1b
+-#define DPRX_DPHY_ERROR_COUNT_C_LANE3__LANE3_DISPARITY_ERROR_COUNT_CLR__SHIFT 0x1c
+-#define DPRX_DPHY_ERROR_COUNT_C_LANE3__LANE3_TEST_PATTERN_ERROR_COUNT_CLR__SHIFT 0x1e
+-#define DPRX_DPHY_ERROR_COUNT_C_LANE3__LANE3_SYMBOL_ERROR_COUNT_CLR_MASK 0x08000000L
+-#define DPRX_DPHY_ERROR_COUNT_C_LANE3__LANE3_DISPARITY_ERROR_COUNT_CLR_MASK 0x10000000L
+-#define DPRX_DPHY_ERROR_COUNT_C_LANE3__LANE3_TEST_PATTERN_ERROR_COUNT_CLR_MASK 0x40000000L
+-//DPRX_DPHY_BS_ERROR_THRESH_GLOBAL
+-#define DPRX_DPHY_BS_ERROR_THRESH_GLOBAL__BS_INTERVAL_ERROR_THRESH__SHIFT 0x0
+-#define DPRX_DPHY_BS_ERROR_THRESH_GLOBAL__BS_INTERVAL_UNCERTAINTY_THRESH__SHIFT 0x8
+-#define DPRX_DPHY_BS_ERROR_THRESH_GLOBAL__BS_INTERVAL_ERROR_THRESH_MASK 0x0000001FL
+-#define DPRX_DPHY_BS_ERROR_THRESH_GLOBAL__BS_INTERVAL_UNCERTAINTY_THRESH_MASK 0x0000FF00L
+-//DPRX_DPHY_SR_ERROR_COUNT_A
+-#define DPRX_DPHY_SR_ERROR_COUNT_A__SR_ERROR_COUNT__SHIFT 0x0
+-#define DPRX_DPHY_SR_ERROR_COUNT_A__SR_INTERVAL_COUNT__SHIFT 0x8
+-#define DPRX_DPHY_SR_ERROR_COUNT_A__SR_ERROR_COUNT_CLR__SHIFT 0x19
+-#define DPRX_DPHY_SR_ERROR_COUNT_A__SR_ERROR_COUNT_MASK 0x000000FFL
+-#define DPRX_DPHY_SR_ERROR_COUNT_A__SR_INTERVAL_COUNT_MASK 0x01FFFF00L
+-#define DPRX_DPHY_SR_ERROR_COUNT_A__SR_ERROR_COUNT_CLR_MASK 0x02000000L
+-//DPRX_DPHY_BS_ERROR_COUNT_A
+-#define DPRX_DPHY_BS_ERROR_COUNT_A__BS_ERROR_COUNT__SHIFT 0x0
+-#define DPRX_DPHY_BS_ERROR_COUNT_A__BS_INTERVAL_COUNT__SHIFT 0x8
+-#define DPRX_DPHY_BS_ERROR_COUNT_A__BS_ERROR_COUNT_CLR__SHIFT 0x19
+-#define DPRX_DPHY_BS_ERROR_COUNT_A__BS_ERROR_COUNT_MASK 0x000000FFL
+-#define DPRX_DPHY_BS_ERROR_COUNT_A__BS_INTERVAL_COUNT_MASK 0x01FFFF00L
+-#define DPRX_DPHY_BS_ERROR_COUNT_A__BS_ERROR_COUNT_CLR_MASK 0x02000000L
+-//DPRX_DPHY_BS_ERROR_COUNT_B
+-#define DPRX_DPHY_BS_ERROR_COUNT_B__BS_INTERVAL_UNCERTAINTY_COUNT__SHIFT 0x0
+-#define DPRX_DPHY_BS_ERROR_COUNT_B__BS_INTERVAL_ERROR_COUNT__SHIFT 0x8
+-#define DPRX_DPHY_BS_ERROR_COUNT_B__BS_INTERVAL_ERROR_COUNT_CLR__SHIFT 0x11
+-#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE0_CPBS_ERROR_CLR__SHIFT 0x14
+-#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE1_CPBS_ERROR_CLR__SHIFT 0x15
+-#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE2_CPBS_ERROR_CLR__SHIFT 0x16
+-#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE3_CPBS_ERROR_CLR__SHIFT 0x17
+-#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE0_CPBS_ERROR__SHIFT 0x18
+-#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE1_CPBS_ERROR__SHIFT 0x1a
+-#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE2_CPBS_ERROR__SHIFT 0x1c
+-#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE3_CPBS_ERROR__SHIFT 0x1e
+-#define DPRX_DPHY_BS_ERROR_COUNT_B__BS_INTERVAL_UNCERTAINTY_COUNT_MASK 0x000000FFL
+-#define DPRX_DPHY_BS_ERROR_COUNT_B__BS_INTERVAL_ERROR_COUNT_MASK 0x00001F00L
+-#define DPRX_DPHY_BS_ERROR_COUNT_B__BS_INTERVAL_ERROR_COUNT_CLR_MASK 0x00020000L
+-#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE0_CPBS_ERROR_CLR_MASK 0x00100000L
+-#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE1_CPBS_ERROR_CLR_MASK 0x00200000L
+-#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE2_CPBS_ERROR_CLR_MASK 0x00400000L
+-#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE3_CPBS_ERROR_CLR_MASK 0x00800000L
+-#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE0_CPBS_ERROR_MASK 0x03000000L
+-#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE1_CPBS_ERROR_MASK 0x0C000000L
+-#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE2_CPBS_ERROR_MASK 0x30000000L
+-#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE3_CPBS_ERROR_MASK 0xC0000000L
+-//DPRX_DPHY_LANESETUP0
+-#define DPRX_DPHY_LANESETUP0__LANE_MAP__SHIFT 0x0
+-#define DPRX_DPHY_LANESETUP0__LANE_MAP_MASK 0x000000FFL
+-//DPRX_DPHY_LANESETUP1
+-#define DPRX_DPHY_LANESETUP1__LANEINV__SHIFT 0x0
+-#define DPRX_DPHY_LANESETUP1__LANEINV_MASK 0x0000000FL
+-//DPRX_DPHY_LFSRADV
+-#define DPRX_DPHY_LFSRADV__TWOSYMCORRECTMIDDLE_ENABLE__SHIFT 0x1
+-#define DPRX_DPHY_LFSRADV__TWOSYMCORRECTLR_ENABLE__SHIFT 0x2
+-#define DPRX_DPHY_LFSRADV__SEVENSYMBOLWINDOW_ENABLE__SHIFT 0x3
+-#define DPRX_DPHY_LFSRADV__SUPPRESS_SINGLE_BS_BF_CP_SR_EN__SHIFT 0x4
+-#define DPRX_DPHY_LFSRADV__IGNORE_ERROR_FLAG_FOR_BS_INTERVAL__SHIFT 0x5
+-#define DPRX_DPHY_LFSRADV__TWOSYMCORRECTMIDDLE_ENABLE_MASK 0x00000002L
+-#define DPRX_DPHY_LFSRADV__TWOSYMCORRECTLR_ENABLE_MASK 0x00000004L
+-#define DPRX_DPHY_LFSRADV__SEVENSYMBOLWINDOW_ENABLE_MASK 0x00000008L
+-#define DPRX_DPHY_LFSRADV__SUPPRESS_SINGLE_BS_BF_CP_SR_EN_MASK 0x00000010L
+-#define DPRX_DPHY_LFSRADV__IGNORE_ERROR_FLAG_FOR_BS_INTERVAL_MASK 0x00000020L
+-//DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT
+-#define DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT__SEVENSYMBOLWINDOW_ERROR_DETECT_LANE0__SHIFT 0x0
+-#define DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT__SEVENSYMBOLWINDOW_ERROR_DETECT_LANE1__SHIFT 0x8
+-#define DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT__SEVENSYMBOLWINDOW_ERROR_DETECT_LANE2__SHIFT 0x10
+-#define DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT__SEVENSYMBOLWINDOW_ERROR_DETECT_LANE3__SHIFT 0x18
+-#define DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT__SEVENSYMBOLWINDOW_ERROR_DETECT_CLEAR__SHIFT 0x1f
+-#define DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT__SEVENSYMBOLWINDOW_ERROR_DETECT_LANE0_MASK 0x0000007FL
+-#define DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT__SEVENSYMBOLWINDOW_ERROR_DETECT_LANE1_MASK 0x00007F00L
+-#define DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT__SEVENSYMBOLWINDOW_ERROR_DETECT_LANE2_MASK 0x007F0000L
+-#define DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT__SEVENSYMBOLWINDOW_ERROR_DETECT_LANE3_MASK 0x7F000000L
+-#define DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT__SEVENSYMBOLWINDOW_ERROR_DETECT_CLEAR_MASK 0x80000000L
+-//DPRX_DPHY_SET_ENABLE
+-#define DPRX_DPHY_SET_ENABLE__SET_ENABLE__SHIFT 0x0
+-#define DPRX_DPHY_SET_ENABLE__CLOCK_ENABLE__SHIFT 0x8
+-#define DPRX_DPHY_SET_ENABLE__CLOCK_ON__SHIFT 0xc
+-#define DPRX_DPHY_SET_ENABLE__SET_ENABLE_MASK 0x00000003L
+-#define DPRX_DPHY_SET_ENABLE__CLOCK_ENABLE_MASK 0x00000100L
+-#define DPRX_DPHY_SET_ENABLE__CLOCK_ON_MASK 0x00001000L
+-//DPRX_DPHY_ECF_LSB
+-#define DPRX_DPHY_ECF_LSB__ECF_LSB__SHIFT 0x0
+-#define DPRX_DPHY_ECF_LSB__ECF_LSB_MASK 0xFFFFFFFFL
+-//DPRX_DPHY_ECF_MSB
+-#define DPRX_DPHY_ECF_MSB__ECF_MSB__SHIFT 0x0
+-#define DPRX_DPHY_ECF_MSB__ECF_MSB_MASK 0xFFFFFFFFL
+-//DPRX_DPHY_ENHANCED_FRAME_EN
+-#define DPRX_DPHY_ENHANCED_FRAME_EN__ENHANCED_FRAME_EN__SHIFT 0x0
+-#define DPRX_DPHY_ENHANCED_FRAME_EN__ENHANCED_FRAME_EN_MASK 0x00000001L
+-//DPRX_DPHY_MTP_HEADER_COUNT_FORCE
+-#define DPRX_DPHY_MTP_HEADER_COUNT_FORCE__MTP_HEADER_COUNT_FORCE__SHIFT 0x0
+-#define DPRX_DPHY_MTP_HEADER_COUNT_FORCE__USE_TRAILING_BF__SHIFT 0x11
+-#define DPRX_DPHY_MTP_HEADER_COUNT_FORCE__LINK_LINE_COUNT_FORCE__SHIFT 0x12
+-#define DPRX_DPHY_MTP_HEADER_COUNT_FORCE__BS_COUNT_FORCE__SHIFT 0x14
+-#define DPRX_DPHY_MTP_HEADER_COUNT_FORCE__MTP_HEADER_COUNT_FORCE_MASK 0x000003FFL
+-#define DPRX_DPHY_MTP_HEADER_COUNT_FORCE__USE_TRAILING_BF_MASK 0x00020000L
+-#define DPRX_DPHY_MTP_HEADER_COUNT_FORCE__LINK_LINE_COUNT_FORCE_MASK 0x000C0000L
+-#define DPRX_DPHY_MTP_HEADER_COUNT_FORCE__BS_COUNT_FORCE_MASK 0x3FF00000L
+-//DPRX_DPHY_DYNAMIC_DESKEW_DATA
+-#define DPRX_DPHY_DYNAMIC_DESKEW_DATA__MATCH0_DATA__SHIFT 0x0
+-#define DPRX_DPHY_DYNAMIC_DESKEW_DATA__MATCH1_DATA__SHIFT 0x8
+-#define DPRX_DPHY_DYNAMIC_DESKEW_DATA__MATCH2_DATA__SHIFT 0x10
+-#define DPRX_DPHY_DYNAMIC_DESKEW_DATA__MATCH3_DATA__SHIFT 0x18
+-#define DPRX_DPHY_DYNAMIC_DESKEW_DATA__MATCH0_DATA_MASK 0x000000FFL
+-#define DPRX_DPHY_DYNAMIC_DESKEW_DATA__MATCH1_DATA_MASK 0x0000FF00L
+-#define DPRX_DPHY_DYNAMIC_DESKEW_DATA__MATCH2_DATA_MASK 0x00FF0000L
+-#define DPRX_DPHY_DYNAMIC_DESKEW_DATA__MATCH3_DATA_MASK 0xFF000000L
+-//DPRX_DPHY_DYNAMIC_DESKEW_CONTROL
+-#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__DESKEW_WAIT_COUNT__SHIFT 0x0
+-#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH0_KCODE__SHIFT 0x5
+-#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH0_DATA_DONTCARE__SHIFT 0x6
+-#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH0_KCODE_DONTCARE__SHIFT 0x7
+-#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH1_KCODE__SHIFT 0x8
+-#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH1_DATA_DONTCARE__SHIFT 0x9
+-#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH1_KCODE_DONTCARE__SHIFT 0xa
+-#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH2_KCODE__SHIFT 0xb
+-#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH2_DATA_DONTCARE__SHIFT 0xc
+-#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH2_KCODE_DONTCARE__SHIFT 0xd
+-#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH3_KCODE__SHIFT 0xe
+-#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH3_DATA_DONTCARE__SHIFT 0xf
+-#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH3_KCODE_DONTCARE__SHIFT 0x10
+-#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__INTERLANE_ALIGN_CHECK_COUNT__SHIFT 0x11
+-#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__FIFO_LEN_IGNORE_DURING_DS_RST__SHIFT 0x1f
+-#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__DESKEW_WAIT_COUNT_MASK 0x0000001FL
+-#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH0_KCODE_MASK 0x00000020L
+-#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH0_DATA_DONTCARE_MASK 0x00000040L
+-#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH0_KCODE_DONTCARE_MASK 0x00000080L
+-#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH1_KCODE_MASK 0x00000100L
+-#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH1_DATA_DONTCARE_MASK 0x00000200L
+-#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH1_KCODE_DONTCARE_MASK 0x00000400L
+-#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH2_KCODE_MASK 0x00000800L
+-#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH2_DATA_DONTCARE_MASK 0x00001000L
+-#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH2_KCODE_DONTCARE_MASK 0x00002000L
+-#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH3_KCODE_MASK 0x00004000L
+-#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH3_DATA_DONTCARE_MASK 0x00008000L
+-#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH3_KCODE_DONTCARE_MASK 0x00010000L
+-#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__INTERLANE_ALIGN_CHECK_COUNT_MASK 0x007E0000L
+-#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__FIFO_LEN_IGNORE_DURING_DS_RST_MASK 0x80000000L
+-//DPRX_DPHY_BYPASS
+-#define DPRX_DPHY_BYPASS__LANE0_SDESKEW_BYPASS__SHIFT 0x4
+-#define DPRX_DPHY_BYPASS__LANE1_SDESKEW_BYPASS__SHIFT 0x5
+-#define DPRX_DPHY_BYPASS__LANE2_SDESKEW_BYPASS__SHIFT 0x6
+-#define DPRX_DPHY_BYPASS__LANE3_SDESKEW_BYPASS__SHIFT 0x7
+-#define DPRX_DPHY_BYPASS__LANE0_SDESKEW_BYPASS_MASK 0x00000010L
+-#define DPRX_DPHY_BYPASS__LANE1_SDESKEW_BYPASS_MASK 0x00000020L
+-#define DPRX_DPHY_BYPASS__LANE2_SDESKEW_BYPASS_MASK 0x00000040L
+-#define DPRX_DPHY_BYPASS__LANE3_SDESKEW_BYPASS_MASK 0x00000080L
+-//DPRX_DPHY_INT_RESET
+-#define DPRX_DPHY_INT_RESET__LANE0_ALIGN_RESET__SHIFT 0x0
+-#define DPRX_DPHY_INT_RESET__LANE1_ALIGN_RESET__SHIFT 0x1
+-#define DPRX_DPHY_INT_RESET__LANE2_ALIGN_RESET__SHIFT 0x2
+-#define DPRX_DPHY_INT_RESET__LANE3_ALIGN_RESET__SHIFT 0x3
+-#define DPRX_DPHY_INT_RESET__LANE0_SDESKEW_RESET__SHIFT 0x4
+-#define DPRX_DPHY_INT_RESET__LANE1_SDESKEW_RESET__SHIFT 0x5
+-#define DPRX_DPHY_INT_RESET__LANE2_SDESKEW_RESET__SHIFT 0x6
+-#define DPRX_DPHY_INT_RESET__LANE3_SDESKEW_RESET__SHIFT 0x7
+-#define DPRX_DPHY_INT_RESET__LANE0_8B10BDEC_RESET__SHIFT 0x8
+-#define DPRX_DPHY_INT_RESET__LANE1_8B10BDEC_RESET__SHIFT 0x9
+-#define DPRX_DPHY_INT_RESET__LANE2_8B10BDEC_RESET__SHIFT 0xa
+-#define DPRX_DPHY_INT_RESET__LANE3_8B10BDEC_RESET__SHIFT 0xb
+-#define DPRX_DPHY_INT_RESET__LANE0_LCOUNT_RESET__SHIFT 0x10
+-#define DPRX_DPHY_INT_RESET__LANE1_LCOUNT_RESET__SHIFT 0x11
+-#define DPRX_DPHY_INT_RESET__LANE2_LCOUNT_RESET__SHIFT 0x12
+-#define DPRX_DPHY_INT_RESET__LANE3_LCOUNT_RESET__SHIFT 0x13
+-#define DPRX_DPHY_INT_RESET__LANE0_DDESKEW_RESET__SHIFT 0x14
+-#define DPRX_DPHY_INT_RESET__LANE1_DDESKEW_RESET__SHIFT 0x15
+-#define DPRX_DPHY_INT_RESET__LANE2_DDESKEW_RESET__SHIFT 0x16
+-#define DPRX_DPHY_INT_RESET__LANE3_DDESKEW_RESET__SHIFT 0x17
+-#define DPRX_DPHY_INT_RESET__INV_RESET__SHIFT 0x18
+-#define DPRX_DPHY_INT_RESET__LANEREV_RESET__SHIFT 0x19
+-#define DPRX_DPHY_INT_RESET__ENABLE_RESET__SHIFT 0x1a
+-#define DPRX_DPHY_INT_RESET__CTL_RESET__SHIFT 0x1b
+-#define DPRX_DPHY_INT_RESET__CTL_DS_RESET__SHIFT 0x1c
+-#define DPRX_DPHY_INT_RESET__CTL_TRN_RESET__SHIFT 0x1d
+-#define DPRX_DPHY_INT_RESET__HEADERPARSE_RESET__SHIFT 0x1e
+-#define DPRX_DPHY_INT_RESET__SDOUT_RESET__SHIFT 0x1f
+-#define DPRX_DPHY_INT_RESET__LANE0_ALIGN_RESET_MASK 0x00000001L
+-#define DPRX_DPHY_INT_RESET__LANE1_ALIGN_RESET_MASK 0x00000002L
+-#define DPRX_DPHY_INT_RESET__LANE2_ALIGN_RESET_MASK 0x00000004L
+-#define DPRX_DPHY_INT_RESET__LANE3_ALIGN_RESET_MASK 0x00000008L
+-#define DPRX_DPHY_INT_RESET__LANE0_SDESKEW_RESET_MASK 0x00000010L
+-#define DPRX_DPHY_INT_RESET__LANE1_SDESKEW_RESET_MASK 0x00000020L
+-#define DPRX_DPHY_INT_RESET__LANE2_SDESKEW_RESET_MASK 0x00000040L
+-#define DPRX_DPHY_INT_RESET__LANE3_SDESKEW_RESET_MASK 0x00000080L
+-#define DPRX_DPHY_INT_RESET__LANE0_8B10BDEC_RESET_MASK 0x00000100L
+-#define DPRX_DPHY_INT_RESET__LANE1_8B10BDEC_RESET_MASK 0x00000200L
+-#define DPRX_DPHY_INT_RESET__LANE2_8B10BDEC_RESET_MASK 0x00000400L
+-#define DPRX_DPHY_INT_RESET__LANE3_8B10BDEC_RESET_MASK 0x00000800L
+-#define DPRX_DPHY_INT_RESET__LANE0_LCOUNT_RESET_MASK 0x00010000L
+-#define DPRX_DPHY_INT_RESET__LANE1_LCOUNT_RESET_MASK 0x00020000L
+-#define DPRX_DPHY_INT_RESET__LANE2_LCOUNT_RESET_MASK 0x00040000L
+-#define DPRX_DPHY_INT_RESET__LANE3_LCOUNT_RESET_MASK 0x00080000L
+-#define DPRX_DPHY_INT_RESET__LANE0_DDESKEW_RESET_MASK 0x00100000L
+-#define DPRX_DPHY_INT_RESET__LANE1_DDESKEW_RESET_MASK 0x00200000L
+-#define DPRX_DPHY_INT_RESET__LANE2_DDESKEW_RESET_MASK 0x00400000L
+-#define DPRX_DPHY_INT_RESET__LANE3_DDESKEW_RESET_MASK 0x00800000L
+-#define DPRX_DPHY_INT_RESET__INV_RESET_MASK 0x01000000L
+-#define DPRX_DPHY_INT_RESET__LANEREV_RESET_MASK 0x02000000L
+-#define DPRX_DPHY_INT_RESET__ENABLE_RESET_MASK 0x04000000L
+-#define DPRX_DPHY_INT_RESET__CTL_RESET_MASK 0x08000000L
+-#define DPRX_DPHY_INT_RESET__CTL_DS_RESET_MASK 0x10000000L
+-#define DPRX_DPHY_INT_RESET__CTL_TRN_RESET_MASK 0x20000000L
+-#define DPRX_DPHY_INT_RESET__HEADERPARSE_RESET_MASK 0x40000000L
+-#define DPRX_DPHY_INT_RESET__SDOUT_RESET_MASK 0x80000000L
+-//DPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS
+-#define DPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS__BS_INTERVAL_ERROR_THRESH_EXCEEDED_FLAG__SHIFT 0x0
+-#define DPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS__BS_INTERVAL_ERROR_THRESH_EXCEEDED_ACK__SHIFT 0x4
+-#define DPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS__BS_INTERVAL_ERROR_THRESH_EXCEEDED_MASK__SHIFT 0x8
+-#define DPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS__BS_INTERVAL_ERROR_THRESH_EXCEEDED_FLAG_MASK 0x00000001L
+-#define DPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS__BS_INTERVAL_ERROR_THRESH_EXCEEDED_ACK_MASK 0x00000010L
+-#define DPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS__BS_INTERVAL_ERROR_THRESH_EXCEEDED_MASK_MASK 0x00000100L
+-//DPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS
+-#define DPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS__SYMBOL_ERROR_THRESH_EXCEEDED_FLAG__SHIFT 0x0
+-#define DPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS__SYMBOL_ERROR_THRESH_EXCEEDED_ACK__SHIFT 0x4
+-#define DPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS__SYMBOL_ERROR_THRESH_EXCEEDED_MASK__SHIFT 0x8
+-#define DPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS__SYMBOL_ERROR_THRESH_EXCEEDED_FLAG_MASK 0x00000001L
+-#define DPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS__SYMBOL_ERROR_THRESH_EXCEEDED_ACK_MASK 0x00000010L
+-#define DPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS__SYMBOL_ERROR_THRESH_EXCEEDED_MASK_MASK 0x00000100L
+-//DPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS
+-#define DPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS__DISPARITY_ERROR_THRESH_EXCEEDED_FLAG__SHIFT 0x0
+-#define DPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS__DISPARITY_ERROR_THRESH_EXCEEDED_ACK__SHIFT 0x4
+-#define DPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS__DISPARITY_ERROR_THRESH_EXCEEDED_MASK__SHIFT 0x8
+-#define DPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS__DISPARITY_ERROR_THRESH_EXCEEDED_FLAG_MASK 0x00000001L
+-#define DPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS__DISPARITY_ERROR_THRESH_EXCEEDED_ACK_MASK 0x00000010L
+-#define DPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS__DISPARITY_ERROR_THRESH_EXCEEDED_MASK_MASK 0x00000100L
+-//DPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS
+-#define DPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS__TEST_PATTERN_ERROR_THRESH_EXCEEDED_FLAG__SHIFT 0x0
+-#define DPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS__TEST_PATTERN_ERROR_THRESH_EXCEEDED_ACK__SHIFT 0x4
+-#define DPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS__TEST_PATTERN_ERROR_THRESH_EXCEEDED_MASK__SHIFT 0x8
+-#define DPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS__TEST_PATTERN_ERROR_THRESH_EXCEEDED_FLAG_MASK 0x00000001L
+-#define DPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS__TEST_PATTERN_ERROR_THRESH_EXCEEDED_ACK_MASK 0x00000010L
+-#define DPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS__TEST_PATTERN_ERROR_THRESH_EXCEEDED_MASK_MASK 0x00000100L
+-//DPRX_DPHY_DETECT_SR_LOCK_STATUS
+-#define DPRX_DPHY_DETECT_SR_LOCK_STATUS__DETECT_SR_LOCK_STATUS_FLAG__SHIFT 0x0
+-#define DPRX_DPHY_DETECT_SR_LOCK_STATUS__DETECT_SR_LOCK_STATUS_ACK__SHIFT 0x4
+-#define DPRX_DPHY_DETECT_SR_LOCK_STATUS__DETECT_SR_LOCK_STATUS_MASK__SHIFT 0x8
+-#define DPRX_DPHY_DETECT_SR_LOCK_STATUS__DETECT_SR_LOCK_STATUS_TYPE__SHIFT 0xc
+-#define DPRX_DPHY_DETECT_SR_LOCK_STATUS__DETECT_SR_LOCK_STATUS_FLAG_MASK 0x00000001L
+-#define DPRX_DPHY_DETECT_SR_LOCK_STATUS__DETECT_SR_LOCK_STATUS_ACK_MASK 0x00000010L
+-#define DPRX_DPHY_DETECT_SR_LOCK_STATUS__DETECT_SR_LOCK_STATUS_MASK_MASK 0x00000100L
+-#define DPRX_DPHY_DETECT_SR_LOCK_STATUS__DETECT_SR_LOCK_STATUS_TYPE_MASK 0x00001000L
+-//DPRX_DPHY_LOSS_OF_ALIGN_STATUS
+-#define DPRX_DPHY_LOSS_OF_ALIGN_STATUS__LOSS_OF_ALIGN_FLAG__SHIFT 0x0
+-#define DPRX_DPHY_LOSS_OF_ALIGN_STATUS__LOSS_OF_ALIGN_ACK__SHIFT 0x4
+-#define DPRX_DPHY_LOSS_OF_ALIGN_STATUS__LOSS_OF_ALIGN_MASK__SHIFT 0x8
+-#define DPRX_DPHY_LOSS_OF_ALIGN_STATUS__LOSS_OF_ALIGN_FLAG_MASK 0x00000001L
+-#define DPRX_DPHY_LOSS_OF_ALIGN_STATUS__LOSS_OF_ALIGN_ACK_MASK 0x00000010L
+-#define DPRX_DPHY_LOSS_OF_ALIGN_STATUS__LOSS_OF_ALIGN_MASK_MASK 0x00000100L
+-//DPRX_DPHY_LOSS_OF_DESKEW_STATUS
+-#define DPRX_DPHY_LOSS_OF_DESKEW_STATUS__LOSS_OF_DESKEW_FLAG__SHIFT 0x0
+-#define DPRX_DPHY_LOSS_OF_DESKEW_STATUS__LOSS_OF_DESKEW_ACK__SHIFT 0x4
+-#define DPRX_DPHY_LOSS_OF_DESKEW_STATUS__LOSS_OF_DESKEW_MASK__SHIFT 0x8
+-#define DPRX_DPHY_LOSS_OF_DESKEW_STATUS__LOSS_OF_DESKEW_FLAG_MASK 0x00000001L
+-#define DPRX_DPHY_LOSS_OF_DESKEW_STATUS__LOSS_OF_DESKEW_ACK_MASK 0x00000010L
+-#define DPRX_DPHY_LOSS_OF_DESKEW_STATUS__LOSS_OF_DESKEW_MASK_MASK 0x00000100L
+-//DPRX_DPHY_EXCESSIVE_ERROR_STATUS
+-#define DPRX_DPHY_EXCESSIVE_ERROR_STATUS__EXCESSIVE_ERROR_FLAG__SHIFT 0x0
+-#define DPRX_DPHY_EXCESSIVE_ERROR_STATUS__EXCESSIVE_ERROR_ACK__SHIFT 0x4
+-#define DPRX_DPHY_EXCESSIVE_ERROR_STATUS__EXCESSIVE_ERROR_MASK__SHIFT 0x8
+-#define DPRX_DPHY_EXCESSIVE_ERROR_STATUS__EXCESSIVE_ERROR_FLAG_MASK 0x00000001L
+-#define DPRX_DPHY_EXCESSIVE_ERROR_STATUS__EXCESSIVE_ERROR_ACK_MASK 0x00000010L
+-#define DPRX_DPHY_EXCESSIVE_ERROR_STATUS__EXCESSIVE_ERROR_MASK_MASK 0x00000100L
+-//DPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS
+-#define DPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS__DESKEW_FIFO_OVERFLOW_FLAG__SHIFT 0x0
+-#define DPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS__DESKEW_FIFO_OVERFLOW_ACK__SHIFT 0x4
+-#define DPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS__DESKEW_FIFO_OVERFLOW_MASK__SHIFT 0x8
+-#define DPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS__DESKEW_FIFO_OVERFLOW_FLAG_MASK 0x00000001L
+-#define DPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS__DESKEW_FIFO_OVERFLOW_ACK_MASK 0x00000010L
+-#define DPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS__DESKEW_FIFO_OVERFLOW_MASK_MASK 0x00000100L
+-//DPRX_DPHY_SPARE
+-#define DPRX_DPHY_SPARE__DPHY_SPARE__SHIFT 0x0
+-#define DPRX_DPHY_SPARE__DPHY_SPARE_MASK 0xFFFFFFFFL
+-//DCRX_GATE_DISABLE_CNTL
+-#define DCRX_GATE_DISABLE_CNTL__DCRX_DISPCLK_CWB0_SD0_GATE_DISABLE__SHIFT 0x0
+-#define DCRX_GATE_DISABLE_CNTL__DCRX_DISPCLK_CWB1_SD1_GATE_DISABLE__SHIFT 0x1
+-#define DCRX_GATE_DISABLE_CNTL__DCRX_DISPCLK_AUX_GATE_DISABLE__SHIFT 0x2
+-#define DCRX_GATE_DISABLE_CNTL__DCRX_DISPCLK_R_GATE_DISABLE__SHIFT 0x3
+-#define DCRX_GATE_DISABLE_CNTL__DCRX_SYMCLK_RX_SD0_GATE_DISABLE__SHIFT 0x8
+-#define DCRX_GATE_DISABLE_CNTL__DCRX_SYMCLK_RX_SD1_GATE_DISABLE__SHIFT 0x9
+-#define DCRX_GATE_DISABLE_CNTL__DCRX_SYMCLK_RX_DPHY_GATE_DISABLE__SHIFT 0xa
+-#define DCRX_GATE_DISABLE_CNTL__DCRX_SYMCLK_RX_P_GATE_DISABLE__SHIFT 0xc
+-#define DCRX_GATE_DISABLE_CNTL__DCRX_DISPCLK_CWB0_SD0_GATE_DISABLE_MASK 0x00000001L
+-#define DCRX_GATE_DISABLE_CNTL__DCRX_DISPCLK_CWB1_SD1_GATE_DISABLE_MASK 0x00000002L
+-#define DCRX_GATE_DISABLE_CNTL__DCRX_DISPCLK_AUX_GATE_DISABLE_MASK 0x00000004L
+-#define DCRX_GATE_DISABLE_CNTL__DCRX_DISPCLK_R_GATE_DISABLE_MASK 0x00000008L
+-#define DCRX_GATE_DISABLE_CNTL__DCRX_SYMCLK_RX_SD0_GATE_DISABLE_MASK 0x00000100L
+-#define DCRX_GATE_DISABLE_CNTL__DCRX_SYMCLK_RX_SD1_GATE_DISABLE_MASK 0x00000200L
+-#define DCRX_GATE_DISABLE_CNTL__DCRX_SYMCLK_RX_DPHY_GATE_DISABLE_MASK 0x00000400L
+-#define DCRX_GATE_DISABLE_CNTL__DCRX_SYMCLK_RX_P_GATE_DISABLE_MASK 0x00001000L
+-//DCRX_SOFT_RESET
+-#define DCRX_SOFT_RESET__DCRX_DISPCLK_CWB0_SD0_SOFT_RESET__SHIFT 0x0
+-#define DCRX_SOFT_RESET__DCRX_DISPCLK_CWB1_SD1_SOFT_RESET__SHIFT 0x1
+-#define DCRX_SOFT_RESET__DCRX_DISPCLK_AUX_SOFT_RESET__SHIFT 0x2
+-#define DCRX_SOFT_RESET__DCRX_DISPCLK_P_SOFT_RESET__SHIFT 0x4
+-#define DCRX_SOFT_RESET__DCRX_SYMCLK_RX_SD0_SOFT_RESET__SHIFT 0x8
+-#define DCRX_SOFT_RESET__DCRX_SYMCLK_RX_SD1_SOFT_RESET__SHIFT 0x9
+-#define DCRX_SOFT_RESET__DCRX_SYMCLK_RX_DPHY_SOFT_RESET__SHIFT 0xa
+-#define DCRX_SOFT_RESET__DCRX_SYMCLK_RX_P_SOFT_RESET__SHIFT 0xc
+-#define DCRX_SOFT_RESET__DCRX_REFCLK_SOFT_RESET__SHIFT 0x10
+-#define DCRX_SOFT_RESET__DCRX_SCLK_SOFT_RESET__SHIFT 0x11
+-#define DCRX_SOFT_RESET__DCRX_DISPCLK_CWB0_SD0_SOFT_RESET_MASK 0x00000001L
+-#define DCRX_SOFT_RESET__DCRX_DISPCLK_CWB1_SD1_SOFT_RESET_MASK 0x00000002L
+-#define DCRX_SOFT_RESET__DCRX_DISPCLK_AUX_SOFT_RESET_MASK 0x00000004L
+-#define DCRX_SOFT_RESET__DCRX_DISPCLK_P_SOFT_RESET_MASK 0x00000010L
+-#define DCRX_SOFT_RESET__DCRX_SYMCLK_RX_SD0_SOFT_RESET_MASK 0x00000100L
+-#define DCRX_SOFT_RESET__DCRX_SYMCLK_RX_SD1_SOFT_RESET_MASK 0x00000200L
+-#define DCRX_SOFT_RESET__DCRX_SYMCLK_RX_DPHY_SOFT_RESET_MASK 0x00000400L
+-#define DCRX_SOFT_RESET__DCRX_SYMCLK_RX_P_SOFT_RESET_MASK 0x00001000L
+-#define DCRX_SOFT_RESET__DCRX_REFCLK_SOFT_RESET_MASK 0x00010000L
+-#define DCRX_SOFT_RESET__DCRX_SCLK_SOFT_RESET_MASK 0x00020000L
+-//DCRX_LIGHT_SLEEP_CNTL
+-#define DCRX_LIGHT_SLEEP_CNTL__DCRX_AUX_LIGHT_SLEEP_DIS__SHIFT 0x0
+-#define DCRX_LIGHT_SLEEP_CNTL__DCRX_DPRX_LIGHT_SLEEP_DIS__SHIFT 0x8
+-#define DCRX_LIGHT_SLEEP_CNTL__DCRX_AUX_LIGHT_SLEEP_DIS_MASK 0x00000001L
+-#define DCRX_LIGHT_SLEEP_CNTL__DCRX_DPRX_LIGHT_SLEEP_DIS_MASK 0x00000100L
+-//DCRX_DISPCLK_GATE_CNTL
+-#define DCRX_DISPCLK_GATE_CNTL__DCRX_DISPCLK_TURN_ON_DELAY__SHIFT 0x0
+-#define DCRX_DISPCLK_GATE_CNTL__DCRX_DISPCLK_TURN_OFF_DELAY__SHIFT 0x4
+-#define DCRX_DISPCLK_GATE_CNTL__DCRX_DISPCLK_TURN_ON_DELAY_MASK 0x0000000FL
+-#define DCRX_DISPCLK_GATE_CNTL__DCRX_DISPCLK_TURN_OFF_DELAY_MASK 0x00000FF0L
+-//DCRX_CLK_CNTL
+-#define DCRX_CLK_CNTL__DCRX_SYMCLK_RX_P_ENABLE__SHIFT 0x2
+-#define DCRX_CLK_CNTL__DCRX_SYMCLK_RX_P_ENABLE_MASK 0x00000004L
+-//DCRX_TEST_CLK_CNTL
+-#define DCRX_TEST_CLK_CNTL__DCRX_TEST_CLK_GENERICA_SEL__SHIFT 0x0
+-#define DCRX_TEST_CLK_CNTL__DCRX_TEST_CLK_GENERICA_INV__SHIFT 0x7
+-#define DCRX_TEST_CLK_CNTL__DCRX_TEST_CLK_GENERICB_SEL__SHIFT 0x8
+-#define DCRX_TEST_CLK_CNTL__DCRX_TEST_CLK_GENERICB_INV__SHIFT 0xf
+-#define DCRX_TEST_CLK_CNTL__DCRX_TEST_CLK_GENERICA_SEL_MASK 0x0000001FL
+-#define DCRX_TEST_CLK_CNTL__DCRX_TEST_CLK_GENERICA_INV_MASK 0x00000080L
+-#define DCRX_TEST_CLK_CNTL__DCRX_TEST_CLK_GENERICB_SEL_MASK 0x00001F00L
+-#define DCRX_TEST_CLK_CNTL__DCRX_TEST_CLK_GENERICB_INV_MASK 0x00008000L
+-//DCRX_PHY_MACRO_CNTL_RESERVED0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED0__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED0__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED1
+-#define DCRX_PHY_MACRO_CNTL_RESERVED1__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED1__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED2
+-#define DCRX_PHY_MACRO_CNTL_RESERVED2__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED2__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED3
+-#define DCRX_PHY_MACRO_CNTL_RESERVED3__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED3__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED4
+-#define DCRX_PHY_MACRO_CNTL_RESERVED4__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED4__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED5
+-#define DCRX_PHY_MACRO_CNTL_RESERVED5__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED5__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED6
+-#define DCRX_PHY_MACRO_CNTL_RESERVED6__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED6__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED7
+-#define DCRX_PHY_MACRO_CNTL_RESERVED7__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED7__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED8
+-#define DCRX_PHY_MACRO_CNTL_RESERVED8__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED8__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED9
+-#define DCRX_PHY_MACRO_CNTL_RESERVED9__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED9__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED10
+-#define DCRX_PHY_MACRO_CNTL_RESERVED10__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED10__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED11
+-#define DCRX_PHY_MACRO_CNTL_RESERVED11__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED11__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED12
+-#define DCRX_PHY_MACRO_CNTL_RESERVED12__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED12__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED13
+-#define DCRX_PHY_MACRO_CNTL_RESERVED13__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED13__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED14
+-#define DCRX_PHY_MACRO_CNTL_RESERVED14__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED14__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED15
+-#define DCRX_PHY_MACRO_CNTL_RESERVED15__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED15__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED16
+-#define DCRX_PHY_MACRO_CNTL_RESERVED16__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED16__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED17
+-#define DCRX_PHY_MACRO_CNTL_RESERVED17__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED17__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED18
+-#define DCRX_PHY_MACRO_CNTL_RESERVED18__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED18__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED19
+-#define DCRX_PHY_MACRO_CNTL_RESERVED19__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED19__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED20
+-#define DCRX_PHY_MACRO_CNTL_RESERVED20__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED20__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED21
+-#define DCRX_PHY_MACRO_CNTL_RESERVED21__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED21__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED22
+-#define DCRX_PHY_MACRO_CNTL_RESERVED22__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED22__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED23
+-#define DCRX_PHY_MACRO_CNTL_RESERVED23__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED23__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED24
+-#define DCRX_PHY_MACRO_CNTL_RESERVED24__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED24__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED25
+-#define DCRX_PHY_MACRO_CNTL_RESERVED25__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED25__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED26
+-#define DCRX_PHY_MACRO_CNTL_RESERVED26__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED26__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED27
+-#define DCRX_PHY_MACRO_CNTL_RESERVED27__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED27__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED28
+-#define DCRX_PHY_MACRO_CNTL_RESERVED28__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED28__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED29
+-#define DCRX_PHY_MACRO_CNTL_RESERVED29__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED29__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED30
+-#define DCRX_PHY_MACRO_CNTL_RESERVED30__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED30__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED31
+-#define DCRX_PHY_MACRO_CNTL_RESERVED31__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED31__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED32
+-#define DCRX_PHY_MACRO_CNTL_RESERVED32__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED32__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED33
+-#define DCRX_PHY_MACRO_CNTL_RESERVED33__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED33__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED34
+-#define DCRX_PHY_MACRO_CNTL_RESERVED34__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED34__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED35
+-#define DCRX_PHY_MACRO_CNTL_RESERVED35__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED35__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED36
+-#define DCRX_PHY_MACRO_CNTL_RESERVED36__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED36__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED37
+-#define DCRX_PHY_MACRO_CNTL_RESERVED37__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED37__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED38
+-#define DCRX_PHY_MACRO_CNTL_RESERVED38__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED38__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED39
+-#define DCRX_PHY_MACRO_CNTL_RESERVED39__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED39__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED40
+-#define DCRX_PHY_MACRO_CNTL_RESERVED40__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED40__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED41
+-#define DCRX_PHY_MACRO_CNTL_RESERVED41__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED41__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED42
+-#define DCRX_PHY_MACRO_CNTL_RESERVED42__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED42__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED43
+-#define DCRX_PHY_MACRO_CNTL_RESERVED43__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED43__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED44
+-#define DCRX_PHY_MACRO_CNTL_RESERVED44__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED44__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED45
+-#define DCRX_PHY_MACRO_CNTL_RESERVED45__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED45__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED46
+-#define DCRX_PHY_MACRO_CNTL_RESERVED46__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED46__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED47
+-#define DCRX_PHY_MACRO_CNTL_RESERVED47__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED47__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED48
+-#define DCRX_PHY_MACRO_CNTL_RESERVED48__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED48__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED49
+-#define DCRX_PHY_MACRO_CNTL_RESERVED49__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED49__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED50
+-#define DCRX_PHY_MACRO_CNTL_RESERVED50__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED50__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED51
+-#define DCRX_PHY_MACRO_CNTL_RESERVED51__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED51__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED52
+-#define DCRX_PHY_MACRO_CNTL_RESERVED52__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED52__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED53
+-#define DCRX_PHY_MACRO_CNTL_RESERVED53__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED53__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED54
+-#define DCRX_PHY_MACRO_CNTL_RESERVED54__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED54__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED55
+-#define DCRX_PHY_MACRO_CNTL_RESERVED55__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED55__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED56
+-#define DCRX_PHY_MACRO_CNTL_RESERVED56__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED56__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED57
+-#define DCRX_PHY_MACRO_CNTL_RESERVED57__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED57__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED58
+-#define DCRX_PHY_MACRO_CNTL_RESERVED58__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED58__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED59
+-#define DCRX_PHY_MACRO_CNTL_RESERVED59__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED59__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED60
+-#define DCRX_PHY_MACRO_CNTL_RESERVED60__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED60__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED61
+-#define DCRX_PHY_MACRO_CNTL_RESERVED61__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED61__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED62
+-#define DCRX_PHY_MACRO_CNTL_RESERVED62__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED62__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED63
+-#define DCRX_PHY_MACRO_CNTL_RESERVED63__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED63__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED64
+-#define DCRX_PHY_MACRO_CNTL_RESERVED64__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED64__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED65
+-#define DCRX_PHY_MACRO_CNTL_RESERVED65__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED65__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED66
+-#define DCRX_PHY_MACRO_CNTL_RESERVED66__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED66__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED67
+-#define DCRX_PHY_MACRO_CNTL_RESERVED67__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED67__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED68
+-#define DCRX_PHY_MACRO_CNTL_RESERVED68__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED68__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED69
+-#define DCRX_PHY_MACRO_CNTL_RESERVED69__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED69__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED70
+-#define DCRX_PHY_MACRO_CNTL_RESERVED70__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED70__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED71
+-#define DCRX_PHY_MACRO_CNTL_RESERVED71__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED71__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED72
+-#define DCRX_PHY_MACRO_CNTL_RESERVED72__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED72__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED73
+-#define DCRX_PHY_MACRO_CNTL_RESERVED73__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED73__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED74
+-#define DCRX_PHY_MACRO_CNTL_RESERVED74__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED74__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED75
+-#define DCRX_PHY_MACRO_CNTL_RESERVED75__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED75__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED76
+-#define DCRX_PHY_MACRO_CNTL_RESERVED76__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED76__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED77
+-#define DCRX_PHY_MACRO_CNTL_RESERVED77__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED77__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED78
+-#define DCRX_PHY_MACRO_CNTL_RESERVED78__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED78__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED79
+-#define DCRX_PHY_MACRO_CNTL_RESERVED79__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED79__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED80
+-#define DCRX_PHY_MACRO_CNTL_RESERVED80__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED80__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED81
+-#define DCRX_PHY_MACRO_CNTL_RESERVED81__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED81__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED82
+-#define DCRX_PHY_MACRO_CNTL_RESERVED82__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED82__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED83
+-#define DCRX_PHY_MACRO_CNTL_RESERVED83__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED83__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED84
+-#define DCRX_PHY_MACRO_CNTL_RESERVED84__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED84__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED85
+-#define DCRX_PHY_MACRO_CNTL_RESERVED85__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED85__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED86
+-#define DCRX_PHY_MACRO_CNTL_RESERVED86__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED86__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED87
+-#define DCRX_PHY_MACRO_CNTL_RESERVED87__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED87__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED88
+-#define DCRX_PHY_MACRO_CNTL_RESERVED88__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED88__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED89
+-#define DCRX_PHY_MACRO_CNTL_RESERVED89__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED89__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED90
+-#define DCRX_PHY_MACRO_CNTL_RESERVED90__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED90__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED91
+-#define DCRX_PHY_MACRO_CNTL_RESERVED91__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED91__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED92
+-#define DCRX_PHY_MACRO_CNTL_RESERVED92__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED92__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED93
+-#define DCRX_PHY_MACRO_CNTL_RESERVED93__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED93__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED94
+-#define DCRX_PHY_MACRO_CNTL_RESERVED94__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED94__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED95
+-#define DCRX_PHY_MACRO_CNTL_RESERVED95__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED95__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED96
+-#define DCRX_PHY_MACRO_CNTL_RESERVED96__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED96__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED97
+-#define DCRX_PHY_MACRO_CNTL_RESERVED97__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED97__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED98
+-#define DCRX_PHY_MACRO_CNTL_RESERVED98__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED98__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED99
+-#define DCRX_PHY_MACRO_CNTL_RESERVED99__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED99__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED100
+-#define DCRX_PHY_MACRO_CNTL_RESERVED100__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED100__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED101
+-#define DCRX_PHY_MACRO_CNTL_RESERVED101__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED101__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED102
+-#define DCRX_PHY_MACRO_CNTL_RESERVED102__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED102__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED103
+-#define DCRX_PHY_MACRO_CNTL_RESERVED103__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED103__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED104
+-#define DCRX_PHY_MACRO_CNTL_RESERVED104__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED104__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED105
+-#define DCRX_PHY_MACRO_CNTL_RESERVED105__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED105__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED106
+-#define DCRX_PHY_MACRO_CNTL_RESERVED106__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED106__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED107
+-#define DCRX_PHY_MACRO_CNTL_RESERVED107__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED107__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED108
+-#define DCRX_PHY_MACRO_CNTL_RESERVED108__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED108__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED109
+-#define DCRX_PHY_MACRO_CNTL_RESERVED109__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED109__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED110
+-#define DCRX_PHY_MACRO_CNTL_RESERVED110__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED110__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED111
+-#define DCRX_PHY_MACRO_CNTL_RESERVED111__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED111__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED112
+-#define DCRX_PHY_MACRO_CNTL_RESERVED112__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED112__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED113
+-#define DCRX_PHY_MACRO_CNTL_RESERVED113__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED113__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED114
+-#define DCRX_PHY_MACRO_CNTL_RESERVED114__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED114__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED115
+-#define DCRX_PHY_MACRO_CNTL_RESERVED115__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED115__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED116
+-#define DCRX_PHY_MACRO_CNTL_RESERVED116__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED116__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED117
+-#define DCRX_PHY_MACRO_CNTL_RESERVED117__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED117__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED118
+-#define DCRX_PHY_MACRO_CNTL_RESERVED118__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED118__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED119
+-#define DCRX_PHY_MACRO_CNTL_RESERVED119__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED119__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED120
+-#define DCRX_PHY_MACRO_CNTL_RESERVED120__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED120__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED121
+-#define DCRX_PHY_MACRO_CNTL_RESERVED121__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED121__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED122
+-#define DCRX_PHY_MACRO_CNTL_RESERVED122__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED122__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED123
+-#define DCRX_PHY_MACRO_CNTL_RESERVED123__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED123__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED124
+-#define DCRX_PHY_MACRO_CNTL_RESERVED124__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED124__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED125
+-#define DCRX_PHY_MACRO_CNTL_RESERVED125__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED125__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED126
+-#define DCRX_PHY_MACRO_CNTL_RESERVED126__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED126__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED127
+-#define DCRX_PHY_MACRO_CNTL_RESERVED127__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED127__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED128
+-#define DCRX_PHY_MACRO_CNTL_RESERVED128__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED128__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED129
+-#define DCRX_PHY_MACRO_CNTL_RESERVED129__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED129__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED130
+-#define DCRX_PHY_MACRO_CNTL_RESERVED130__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED130__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED131
+-#define DCRX_PHY_MACRO_CNTL_RESERVED131__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED131__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED132
+-#define DCRX_PHY_MACRO_CNTL_RESERVED132__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED132__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED133
+-#define DCRX_PHY_MACRO_CNTL_RESERVED133__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED133__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED134
+-#define DCRX_PHY_MACRO_CNTL_RESERVED134__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED134__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED135
+-#define DCRX_PHY_MACRO_CNTL_RESERVED135__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED135__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED136
+-#define DCRX_PHY_MACRO_CNTL_RESERVED136__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED136__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED137
+-#define DCRX_PHY_MACRO_CNTL_RESERVED137__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED137__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED138
+-#define DCRX_PHY_MACRO_CNTL_RESERVED138__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED138__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED139
+-#define DCRX_PHY_MACRO_CNTL_RESERVED139__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED139__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED140
+-#define DCRX_PHY_MACRO_CNTL_RESERVED140__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED140__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED141
+-#define DCRX_PHY_MACRO_CNTL_RESERVED141__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED141__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED142
+-#define DCRX_PHY_MACRO_CNTL_RESERVED142__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED142__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED143
+-#define DCRX_PHY_MACRO_CNTL_RESERVED143__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED143__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED144
+-#define DCRX_PHY_MACRO_CNTL_RESERVED144__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED144__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED145
+-#define DCRX_PHY_MACRO_CNTL_RESERVED145__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED145__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED146
+-#define DCRX_PHY_MACRO_CNTL_RESERVED146__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED146__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED147
+-#define DCRX_PHY_MACRO_CNTL_RESERVED147__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED147__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED148
+-#define DCRX_PHY_MACRO_CNTL_RESERVED148__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED148__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED149
+-#define DCRX_PHY_MACRO_CNTL_RESERVED149__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED149__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED150
+-#define DCRX_PHY_MACRO_CNTL_RESERVED150__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED150__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED151
+-#define DCRX_PHY_MACRO_CNTL_RESERVED151__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED151__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED152
+-#define DCRX_PHY_MACRO_CNTL_RESERVED152__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED152__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED153
+-#define DCRX_PHY_MACRO_CNTL_RESERVED153__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED153__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED154
+-#define DCRX_PHY_MACRO_CNTL_RESERVED154__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED154__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED155
+-#define DCRX_PHY_MACRO_CNTL_RESERVED155__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED155__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED156
+-#define DCRX_PHY_MACRO_CNTL_RESERVED156__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED156__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED157
+-#define DCRX_PHY_MACRO_CNTL_RESERVED157__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED157__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED158
+-#define DCRX_PHY_MACRO_CNTL_RESERVED158__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED158__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED159
+-#define DCRX_PHY_MACRO_CNTL_RESERVED159__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED159__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED160
+-#define DCRX_PHY_MACRO_CNTL_RESERVED160__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED160__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED161
+-#define DCRX_PHY_MACRO_CNTL_RESERVED161__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED161__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED162
+-#define DCRX_PHY_MACRO_CNTL_RESERVED162__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED162__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED163
+-#define DCRX_PHY_MACRO_CNTL_RESERVED163__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED163__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED164
+-#define DCRX_PHY_MACRO_CNTL_RESERVED164__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED164__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED165
+-#define DCRX_PHY_MACRO_CNTL_RESERVED165__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED165__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED166
+-#define DCRX_PHY_MACRO_CNTL_RESERVED166__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED166__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED167
+-#define DCRX_PHY_MACRO_CNTL_RESERVED167__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED167__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED168
+-#define DCRX_PHY_MACRO_CNTL_RESERVED168__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED168__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED169
+-#define DCRX_PHY_MACRO_CNTL_RESERVED169__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED169__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED170
+-#define DCRX_PHY_MACRO_CNTL_RESERVED170__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED170__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED171
+-#define DCRX_PHY_MACRO_CNTL_RESERVED171__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED171__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED172
+-#define DCRX_PHY_MACRO_CNTL_RESERVED172__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED172__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED173
+-#define DCRX_PHY_MACRO_CNTL_RESERVED173__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED173__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED174
+-#define DCRX_PHY_MACRO_CNTL_RESERVED174__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED174__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED175
+-#define DCRX_PHY_MACRO_CNTL_RESERVED175__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED175__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED176
+-#define DCRX_PHY_MACRO_CNTL_RESERVED176__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED176__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED177
+-#define DCRX_PHY_MACRO_CNTL_RESERVED177__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED177__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED178
+-#define DCRX_PHY_MACRO_CNTL_RESERVED178__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED178__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED179
+-#define DCRX_PHY_MACRO_CNTL_RESERVED179__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED179__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED180
+-#define DCRX_PHY_MACRO_CNTL_RESERVED180__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED180__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED181
+-#define DCRX_PHY_MACRO_CNTL_RESERVED181__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED181__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED182
+-#define DCRX_PHY_MACRO_CNTL_RESERVED182__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED182__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED183
+-#define DCRX_PHY_MACRO_CNTL_RESERVED183__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED183__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED184
+-#define DCRX_PHY_MACRO_CNTL_RESERVED184__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED184__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED185
+-#define DCRX_PHY_MACRO_CNTL_RESERVED185__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED185__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED186
+-#define DCRX_PHY_MACRO_CNTL_RESERVED186__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED186__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED187
+-#define DCRX_PHY_MACRO_CNTL_RESERVED187__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED187__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED188
+-#define DCRX_PHY_MACRO_CNTL_RESERVED188__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED188__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED189
+-#define DCRX_PHY_MACRO_CNTL_RESERVED189__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED189__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED190
+-#define DCRX_PHY_MACRO_CNTL_RESERVED190__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED190__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED191
+-#define DCRX_PHY_MACRO_CNTL_RESERVED191__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED191__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED192
+-#define DCRX_PHY_MACRO_CNTL_RESERVED192__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED192__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED193
+-#define DCRX_PHY_MACRO_CNTL_RESERVED193__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED193__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED194
+-#define DCRX_PHY_MACRO_CNTL_RESERVED194__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED194__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED195
+-#define DCRX_PHY_MACRO_CNTL_RESERVED195__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED195__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED196
+-#define DCRX_PHY_MACRO_CNTL_RESERVED196__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED196__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED197
+-#define DCRX_PHY_MACRO_CNTL_RESERVED197__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED197__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED198
+-#define DCRX_PHY_MACRO_CNTL_RESERVED198__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED198__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED199
+-#define DCRX_PHY_MACRO_CNTL_RESERVED199__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED199__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED200
+-#define DCRX_PHY_MACRO_CNTL_RESERVED200__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED200__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED201
+-#define DCRX_PHY_MACRO_CNTL_RESERVED201__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED201__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED202
+-#define DCRX_PHY_MACRO_CNTL_RESERVED202__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED202__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED203
+-#define DCRX_PHY_MACRO_CNTL_RESERVED203__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED203__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED204
+-#define DCRX_PHY_MACRO_CNTL_RESERVED204__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED204__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED205
+-#define DCRX_PHY_MACRO_CNTL_RESERVED205__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED205__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED206
+-#define DCRX_PHY_MACRO_CNTL_RESERVED206__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED206__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED207
+-#define DCRX_PHY_MACRO_CNTL_RESERVED207__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED207__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED208
+-#define DCRX_PHY_MACRO_CNTL_RESERVED208__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED208__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED209
+-#define DCRX_PHY_MACRO_CNTL_RESERVED209__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED209__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED210
+-#define DCRX_PHY_MACRO_CNTL_RESERVED210__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED210__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED211
+-#define DCRX_PHY_MACRO_CNTL_RESERVED211__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED211__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED212
+-#define DCRX_PHY_MACRO_CNTL_RESERVED212__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED212__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED213
+-#define DCRX_PHY_MACRO_CNTL_RESERVED213__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED213__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED214
+-#define DCRX_PHY_MACRO_CNTL_RESERVED214__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED214__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED215
+-#define DCRX_PHY_MACRO_CNTL_RESERVED215__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED215__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED216
+-#define DCRX_PHY_MACRO_CNTL_RESERVED216__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED216__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED217
+-#define DCRX_PHY_MACRO_CNTL_RESERVED217__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED217__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED218
+-#define DCRX_PHY_MACRO_CNTL_RESERVED218__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED218__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED219
+-#define DCRX_PHY_MACRO_CNTL_RESERVED219__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED219__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED220
+-#define DCRX_PHY_MACRO_CNTL_RESERVED220__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED220__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED221
+-#define DCRX_PHY_MACRO_CNTL_RESERVED221__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED221__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED222
+-#define DCRX_PHY_MACRO_CNTL_RESERVED222__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED222__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED223
+-#define DCRX_PHY_MACRO_CNTL_RESERVED223__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED223__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED224
+-#define DCRX_PHY_MACRO_CNTL_RESERVED224__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED224__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED225
+-#define DCRX_PHY_MACRO_CNTL_RESERVED225__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED225__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED226
+-#define DCRX_PHY_MACRO_CNTL_RESERVED226__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED226__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED227
+-#define DCRX_PHY_MACRO_CNTL_RESERVED227__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED227__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED228
+-#define DCRX_PHY_MACRO_CNTL_RESERVED228__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED228__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED229
+-#define DCRX_PHY_MACRO_CNTL_RESERVED229__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED229__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED230
+-#define DCRX_PHY_MACRO_CNTL_RESERVED230__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED230__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED231
+-#define DCRX_PHY_MACRO_CNTL_RESERVED231__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED231__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED232
+-#define DCRX_PHY_MACRO_CNTL_RESERVED232__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED232__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED233
+-#define DCRX_PHY_MACRO_CNTL_RESERVED233__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED233__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED234
+-#define DCRX_PHY_MACRO_CNTL_RESERVED234__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED234__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED235
+-#define DCRX_PHY_MACRO_CNTL_RESERVED235__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED235__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED236
+-#define DCRX_PHY_MACRO_CNTL_RESERVED236__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED236__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED237
+-#define DCRX_PHY_MACRO_CNTL_RESERVED237__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED237__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED238
+-#define DCRX_PHY_MACRO_CNTL_RESERVED238__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED238__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED239
+-#define DCRX_PHY_MACRO_CNTL_RESERVED239__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED239__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED240
+-#define DCRX_PHY_MACRO_CNTL_RESERVED240__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED240__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED241
+-#define DCRX_PHY_MACRO_CNTL_RESERVED241__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED241__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED242
+-#define DCRX_PHY_MACRO_CNTL_RESERVED242__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED242__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED243
+-#define DCRX_PHY_MACRO_CNTL_RESERVED243__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED243__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED244
+-#define DCRX_PHY_MACRO_CNTL_RESERVED244__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED244__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED245
+-#define DCRX_PHY_MACRO_CNTL_RESERVED245__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED245__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED246
+-#define DCRX_PHY_MACRO_CNTL_RESERVED246__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED246__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED247
+-#define DCRX_PHY_MACRO_CNTL_RESERVED247__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED247__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED248
+-#define DCRX_PHY_MACRO_CNTL_RESERVED248__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED248__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED249
+-#define DCRX_PHY_MACRO_CNTL_RESERVED249__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED249__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED250
+-#define DCRX_PHY_MACRO_CNTL_RESERVED250__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED250__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED251
+-#define DCRX_PHY_MACRO_CNTL_RESERVED251__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED251__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED252
+-#define DCRX_PHY_MACRO_CNTL_RESERVED252__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED252__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED253
+-#define DCRX_PHY_MACRO_CNTL_RESERVED253__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED253__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED254
+-#define DCRX_PHY_MACRO_CNTL_RESERVED254__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED254__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED255
+-#define DCRX_PHY_MACRO_CNTL_RESERVED255__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED255__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED256
+-#define DCRX_PHY_MACRO_CNTL_RESERVED256__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED256__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED257
+-#define DCRX_PHY_MACRO_CNTL_RESERVED257__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED257__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED258
+-#define DCRX_PHY_MACRO_CNTL_RESERVED258__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED258__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED259
+-#define DCRX_PHY_MACRO_CNTL_RESERVED259__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED259__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED260
+-#define DCRX_PHY_MACRO_CNTL_RESERVED260__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED260__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED261
+-#define DCRX_PHY_MACRO_CNTL_RESERVED261__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED261__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED262
+-#define DCRX_PHY_MACRO_CNTL_RESERVED262__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED262__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED263
+-#define DCRX_PHY_MACRO_CNTL_RESERVED263__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED263__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED264
+-#define DCRX_PHY_MACRO_CNTL_RESERVED264__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED264__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED265
+-#define DCRX_PHY_MACRO_CNTL_RESERVED265__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED265__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED266
+-#define DCRX_PHY_MACRO_CNTL_RESERVED266__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED266__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED267
+-#define DCRX_PHY_MACRO_CNTL_RESERVED267__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED267__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED268
+-#define DCRX_PHY_MACRO_CNTL_RESERVED268__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED268__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED269
+-#define DCRX_PHY_MACRO_CNTL_RESERVED269__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED269__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED270
+-#define DCRX_PHY_MACRO_CNTL_RESERVED270__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED270__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED271
+-#define DCRX_PHY_MACRO_CNTL_RESERVED271__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED271__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED272
+-#define DCRX_PHY_MACRO_CNTL_RESERVED272__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED272__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED273
+-#define DCRX_PHY_MACRO_CNTL_RESERVED273__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED273__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED274
+-#define DCRX_PHY_MACRO_CNTL_RESERVED274__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED274__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED275
+-#define DCRX_PHY_MACRO_CNTL_RESERVED275__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED275__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED276
+-#define DCRX_PHY_MACRO_CNTL_RESERVED276__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED276__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED277
+-#define DCRX_PHY_MACRO_CNTL_RESERVED277__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED277__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED278
+-#define DCRX_PHY_MACRO_CNTL_RESERVED278__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED278__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED279
+-#define DCRX_PHY_MACRO_CNTL_RESERVED279__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED279__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED280
+-#define DCRX_PHY_MACRO_CNTL_RESERVED280__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED280__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED281
+-#define DCRX_PHY_MACRO_CNTL_RESERVED281__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED281__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED282
+-#define DCRX_PHY_MACRO_CNTL_RESERVED282__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED282__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED283
+-#define DCRX_PHY_MACRO_CNTL_RESERVED283__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED283__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED284
+-#define DCRX_PHY_MACRO_CNTL_RESERVED284__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED284__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED285
+-#define DCRX_PHY_MACRO_CNTL_RESERVED285__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED285__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED286
+-#define DCRX_PHY_MACRO_CNTL_RESERVED286__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED286__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED287
+-#define DCRX_PHY_MACRO_CNTL_RESERVED287__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED287__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED288
+-#define DCRX_PHY_MACRO_CNTL_RESERVED288__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED288__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED289
+-#define DCRX_PHY_MACRO_CNTL_RESERVED289__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED289__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED290
+-#define DCRX_PHY_MACRO_CNTL_RESERVED290__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED290__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED291
+-#define DCRX_PHY_MACRO_CNTL_RESERVED291__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED291__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED292
+-#define DCRX_PHY_MACRO_CNTL_RESERVED292__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED292__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED293
+-#define DCRX_PHY_MACRO_CNTL_RESERVED293__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED293__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED294
+-#define DCRX_PHY_MACRO_CNTL_RESERVED294__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED294__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED295
+-#define DCRX_PHY_MACRO_CNTL_RESERVED295__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED295__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED296
+-#define DCRX_PHY_MACRO_CNTL_RESERVED296__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED296__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED297
+-#define DCRX_PHY_MACRO_CNTL_RESERVED297__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED297__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED298
+-#define DCRX_PHY_MACRO_CNTL_RESERVED298__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED298__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED299
+-#define DCRX_PHY_MACRO_CNTL_RESERVED299__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED299__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED300
+-#define DCRX_PHY_MACRO_CNTL_RESERVED300__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED300__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED301
+-#define DCRX_PHY_MACRO_CNTL_RESERVED301__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED301__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED302
+-#define DCRX_PHY_MACRO_CNTL_RESERVED302__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED302__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED303
+-#define DCRX_PHY_MACRO_CNTL_RESERVED303__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED303__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED304
+-#define DCRX_PHY_MACRO_CNTL_RESERVED304__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED304__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED305
+-#define DCRX_PHY_MACRO_CNTL_RESERVED305__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED305__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED306
+-#define DCRX_PHY_MACRO_CNTL_RESERVED306__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED306__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED307
+-#define DCRX_PHY_MACRO_CNTL_RESERVED307__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED307__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED308
+-#define DCRX_PHY_MACRO_CNTL_RESERVED308__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED308__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED309
+-#define DCRX_PHY_MACRO_CNTL_RESERVED309__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED309__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED310
+-#define DCRX_PHY_MACRO_CNTL_RESERVED310__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED310__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED311
+-#define DCRX_PHY_MACRO_CNTL_RESERVED311__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED311__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED312
+-#define DCRX_PHY_MACRO_CNTL_RESERVED312__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED312__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED313
+-#define DCRX_PHY_MACRO_CNTL_RESERVED313__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED313__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED314
+-#define DCRX_PHY_MACRO_CNTL_RESERVED314__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED314__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED315
+-#define DCRX_PHY_MACRO_CNTL_RESERVED315__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED315__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED316
+-#define DCRX_PHY_MACRO_CNTL_RESERVED316__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED316__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED317
+-#define DCRX_PHY_MACRO_CNTL_RESERVED317__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED317__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED318
+-#define DCRX_PHY_MACRO_CNTL_RESERVED318__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED318__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED319
+-#define DCRX_PHY_MACRO_CNTL_RESERVED319__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED319__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED320
+-#define DCRX_PHY_MACRO_CNTL_RESERVED320__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED320__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED321
+-#define DCRX_PHY_MACRO_CNTL_RESERVED321__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED321__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED322
+-#define DCRX_PHY_MACRO_CNTL_RESERVED322__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED322__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED323
+-#define DCRX_PHY_MACRO_CNTL_RESERVED323__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED323__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED324
+-#define DCRX_PHY_MACRO_CNTL_RESERVED324__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED324__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED325
+-#define DCRX_PHY_MACRO_CNTL_RESERVED325__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED325__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED326
+-#define DCRX_PHY_MACRO_CNTL_RESERVED326__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED326__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED327
+-#define DCRX_PHY_MACRO_CNTL_RESERVED327__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED327__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED328
+-#define DCRX_PHY_MACRO_CNTL_RESERVED328__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED328__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED329
+-#define DCRX_PHY_MACRO_CNTL_RESERVED329__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED329__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED330
+-#define DCRX_PHY_MACRO_CNTL_RESERVED330__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED330__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED331
+-#define DCRX_PHY_MACRO_CNTL_RESERVED331__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED331__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED332
+-#define DCRX_PHY_MACRO_CNTL_RESERVED332__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED332__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED333
+-#define DCRX_PHY_MACRO_CNTL_RESERVED333__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED333__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED334
+-#define DCRX_PHY_MACRO_CNTL_RESERVED334__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED334__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED335
+-#define DCRX_PHY_MACRO_CNTL_RESERVED335__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED335__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED336
+-#define DCRX_PHY_MACRO_CNTL_RESERVED336__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED336__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED337
+-#define DCRX_PHY_MACRO_CNTL_RESERVED337__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED337__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED338
+-#define DCRX_PHY_MACRO_CNTL_RESERVED338__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED338__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED339
+-#define DCRX_PHY_MACRO_CNTL_RESERVED339__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED339__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED340
+-#define DCRX_PHY_MACRO_CNTL_RESERVED340__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED340__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED341
+-#define DCRX_PHY_MACRO_CNTL_RESERVED341__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED341__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED342
+-#define DCRX_PHY_MACRO_CNTL_RESERVED342__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED342__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED343
+-#define DCRX_PHY_MACRO_CNTL_RESERVED343__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED343__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED344
+-#define DCRX_PHY_MACRO_CNTL_RESERVED344__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED344__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED345
+-#define DCRX_PHY_MACRO_CNTL_RESERVED345__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED345__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED346
+-#define DCRX_PHY_MACRO_CNTL_RESERVED346__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED346__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED347
+-#define DCRX_PHY_MACRO_CNTL_RESERVED347__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED347__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED348
+-#define DCRX_PHY_MACRO_CNTL_RESERVED348__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED348__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED349
+-#define DCRX_PHY_MACRO_CNTL_RESERVED349__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED349__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED350
+-#define DCRX_PHY_MACRO_CNTL_RESERVED350__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED350__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED351
+-#define DCRX_PHY_MACRO_CNTL_RESERVED351__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED351__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED352
+-#define DCRX_PHY_MACRO_CNTL_RESERVED352__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED352__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED353
+-#define DCRX_PHY_MACRO_CNTL_RESERVED353__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED353__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED354
+-#define DCRX_PHY_MACRO_CNTL_RESERVED354__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED354__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED355
+-#define DCRX_PHY_MACRO_CNTL_RESERVED355__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED355__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED356
+-#define DCRX_PHY_MACRO_CNTL_RESERVED356__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED356__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED357
+-#define DCRX_PHY_MACRO_CNTL_RESERVED357__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED357__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED358
+-#define DCRX_PHY_MACRO_CNTL_RESERVED358__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED358__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED359
+-#define DCRX_PHY_MACRO_CNTL_RESERVED359__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED359__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED360
+-#define DCRX_PHY_MACRO_CNTL_RESERVED360__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED360__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED361
+-#define DCRX_PHY_MACRO_CNTL_RESERVED361__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED361__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED362
+-#define DCRX_PHY_MACRO_CNTL_RESERVED362__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED362__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED363
+-#define DCRX_PHY_MACRO_CNTL_RESERVED363__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED363__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED364
+-#define DCRX_PHY_MACRO_CNTL_RESERVED364__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED364__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED365
+-#define DCRX_PHY_MACRO_CNTL_RESERVED365__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED365__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED366
+-#define DCRX_PHY_MACRO_CNTL_RESERVED366__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED366__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED367
+-#define DCRX_PHY_MACRO_CNTL_RESERVED367__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED367__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED368
+-#define DCRX_PHY_MACRO_CNTL_RESERVED368__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED368__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED369
+-#define DCRX_PHY_MACRO_CNTL_RESERVED369__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED369__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED370
+-#define DCRX_PHY_MACRO_CNTL_RESERVED370__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED370__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED371
+-#define DCRX_PHY_MACRO_CNTL_RESERVED371__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED371__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED372
+-#define DCRX_PHY_MACRO_CNTL_RESERVED372__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED372__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED373
+-#define DCRX_PHY_MACRO_CNTL_RESERVED373__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED373__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED374
+-#define DCRX_PHY_MACRO_CNTL_RESERVED374__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED374__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED375
+-#define DCRX_PHY_MACRO_CNTL_RESERVED375__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED375__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED376
+-#define DCRX_PHY_MACRO_CNTL_RESERVED376__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED376__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED377
+-#define DCRX_PHY_MACRO_CNTL_RESERVED377__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED377__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED378
+-#define DCRX_PHY_MACRO_CNTL_RESERVED378__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED378__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCRX_PHY_MACRO_CNTL_RESERVED379
+-#define DCRX_PHY_MACRO_CNTL_RESERVED379__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCRX_PHY_MACRO_CNTL_RESERVED379__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//I2S0_CNTL
+-#define I2S0_CNTL__I2S0_WORD_SIZE__SHIFT 0x0
+-#define I2S0_CNTL__I2S0_SAMPLE_ALIGNMENT__SHIFT 0x4
+-#define I2S0_CNTL__I2S0_SAMPLE_BIT_ORDER__SHIFT 0x8
+-#define I2S0_CNTL__I2S0_LRCLK_POLARITY__SHIFT 0xc
+-#define I2S0_CNTL__I2S0_WORD_ALIGNMENT__SHIFT 0x10
+-#define I2S0_CNTL__I2S0_ENABLE__SHIFT 0x1a
+-#define I2S0_CNTL__I2S0_FIFO_START_ADDR__SHIFT 0x1e
+-#define I2S0_CNTL__I2S0_WORD_SIZE_MASK 0x00000001L
+-#define I2S0_CNTL__I2S0_SAMPLE_ALIGNMENT_MASK 0x00000010L
+-#define I2S0_CNTL__I2S0_SAMPLE_BIT_ORDER_MASK 0x00000100L
+-#define I2S0_CNTL__I2S0_LRCLK_POLARITY_MASK 0x00001000L
+-#define I2S0_CNTL__I2S0_WORD_ALIGNMENT_MASK 0x00010000L
+-#define I2S0_CNTL__I2S0_ENABLE_MASK 0x04000000L
+-#define I2S0_CNTL__I2S0_FIFO_START_ADDR_MASK 0x40000000L
+-//SPDIF0_CNTL
+-#define SPDIF0_CNTL__SPDIF0_EN__SHIFT 0x0
+-#define SPDIF0_CNTL__SPDIF0_FIFO_START_ADDR__SHIFT 0x4
+-#define SPDIF0_CNTL__SPDIF0_EN_MASK 0x00000001L
+-#define SPDIF0_CNTL__SPDIF0_FIFO_START_ADDR_MASK 0x00000010L
+-//I2S1_CNTL
+-#define I2S1_CNTL__I2S1_WORD_SIZE__SHIFT 0x0
+-#define I2S1_CNTL__I2S1_SAMPLE_ALIGNMENT__SHIFT 0x4
+-#define I2S1_CNTL__I2S1_SAMPLE_BIT_ORDER__SHIFT 0x8
+-#define I2S1_CNTL__I2S1_LRCLK_POLARITY__SHIFT 0xc
+-#define I2S1_CNTL__I2S1_WORD_ALIGNMENT__SHIFT 0x10
+-#define I2S1_CNTL__I2S1_ENABLE__SHIFT 0x1a
+-#define I2S1_CNTL__I2S1_FIFO_START_ADDR__SHIFT 0x1e
+-#define I2S1_CNTL__I2S1_WORD_SIZE_MASK 0x00000001L
+-#define I2S1_CNTL__I2S1_SAMPLE_ALIGNMENT_MASK 0x00000010L
+-#define I2S1_CNTL__I2S1_SAMPLE_BIT_ORDER_MASK 0x00000100L
+-#define I2S1_CNTL__I2S1_LRCLK_POLARITY_MASK 0x00001000L
+-#define I2S1_CNTL__I2S1_WORD_ALIGNMENT_MASK 0x00010000L
+-#define I2S1_CNTL__I2S1_ENABLE_MASK 0x04000000L
+-#define I2S1_CNTL__I2S1_FIFO_START_ADDR_MASK 0x40000000L
+-//SPDIF1_CNTL
+-#define SPDIF1_CNTL__SPDIF1_EN__SHIFT 0x0
+-#define SPDIF1_CNTL__SPDIF1_FIFO_START_ADDR__SHIFT 0x4
+-#define SPDIF1_CNTL__SPDIF1_INVERT_EN__SHIFT 0x8
+-#define SPDIF1_CNTL__SPDIF1_EN_MASK 0x00000001L
+-#define SPDIF1_CNTL__SPDIF1_FIFO_START_ADDR_MASK 0x00000010L
+-#define SPDIF1_CNTL__SPDIF1_INVERT_EN_MASK 0x00000100L
+-//I2S0_STATUS
+-#define I2S0_STATUS__STREAM0_AUDIO_ENABLE__SHIFT 0x0
+-#define I2S0_STATUS__STREAM0_IDLE__SHIFT 0x1
+-#define I2S0_STATUS__I2S0_DATA_RDY__SHIFT 0x2
+-#define I2S0_STATUS__I2S0_SAMPLE_RATE__SHIFT 0x3
+-#define I2S0_STATUS__STREAM0_AUDIO_ENABLE_MASK 0x00000001L
+-#define I2S0_STATUS__STREAM0_IDLE_MASK 0x00000002L
+-#define I2S0_STATUS__I2S0_DATA_RDY_MASK 0x00000004L
+-#define I2S0_STATUS__I2S0_SAMPLE_RATE_MASK 0x00000038L
+-//I2S1_STATUS
+-#define I2S1_STATUS__STREAM1_AUDIO_ENABLE__SHIFT 0x0
+-#define I2S1_STATUS__STREAM1_IDLE__SHIFT 0x1
+-#define I2S1_STATUS__I2S1_DATA_RDY__SHIFT 0x2
+-#define I2S1_STATUS__I2S1_SAMPLE_RATE__SHIFT 0x3
+-#define I2S1_STATUS__STREAM1_AUDIO_ENABLE_MASK 0x00000001L
+-#define I2S1_STATUS__STREAM1_IDLE_MASK 0x00000002L
+-#define I2S1_STATUS__I2S1_DATA_RDY_MASK 0x00000004L
+-#define I2S1_STATUS__I2S1_SAMPLE_RATE_MASK 0x00000038L
+-//I2S0_CRC_TEST_CNTL
+-#define I2S0_CRC_TEST_CNTL__I2S0_CRC_TEST_EN__SHIFT 0x0
+-#define I2S0_CRC_TEST_CNTL__I2S0_CRC_SOFT_RESET__SHIFT 0x1
+-#define I2S0_CRC_TEST_CNTL__I2S0_CRC_TEST_CONT_EN__SHIFT 0x4
+-#define I2S0_CRC_TEST_CNTL__I2S0_CRC_TEST_NUMBER_OF_SAMPLES__SHIFT 0x8
+-#define I2S0_CRC_TEST_CNTL__I2S0_CRC_TEST_EN_MASK 0x00000001L
+-#define I2S0_CRC_TEST_CNTL__I2S0_CRC_SOFT_RESET_MASK 0x00000002L
+-#define I2S0_CRC_TEST_CNTL__I2S0_CRC_TEST_CONT_EN_MASK 0x00000010L
+-#define I2S0_CRC_TEST_CNTL__I2S0_CRC_TEST_NUMBER_OF_SAMPLES_MASK 0xFFFFFF00L
+-//I2S0_CRC_TEST_DATA_01
+-#define I2S0_CRC_TEST_DATA_01__I2S0_CRC_TEST_DATA0__SHIFT 0x0
+-#define I2S0_CRC_TEST_DATA_01__I2S0_CRC_TEST_DATA1__SHIFT 0x10
+-#define I2S0_CRC_TEST_DATA_01__I2S0_CRC_TEST_DATA0_MASK 0x0000FFFFL
+-#define I2S0_CRC_TEST_DATA_01__I2S0_CRC_TEST_DATA1_MASK 0xFFFF0000L
+-//I2S0_CRC_TEST_DATA_23
+-#define I2S0_CRC_TEST_DATA_23__I2S0_CRC_TEST_DATA2__SHIFT 0x0
+-#define I2S0_CRC_TEST_DATA_23__I2S0_CRC_TEST_DATA3__SHIFT 0x10
+-#define I2S0_CRC_TEST_DATA_23__I2S0_CRC_TEST_DATA2_MASK 0x0000FFFFL
+-#define I2S0_CRC_TEST_DATA_23__I2S0_CRC_TEST_DATA3_MASK 0xFFFF0000L
+-//I2S1_CRC_TEST_CNTL
+-#define I2S1_CRC_TEST_CNTL__I2S1_CRC_TEST_EN__SHIFT 0x0
+-#define I2S1_CRC_TEST_CNTL__I2S1_CRC_SOFT_RESET__SHIFT 0x1
+-#define I2S1_CRC_TEST_CNTL__I2S1_CRC_TEST_CONT_EN__SHIFT 0x4
+-#define I2S1_CRC_TEST_CNTL__I2S1_CRC_TEST_NUMBER_OF_SAMPLES__SHIFT 0x8
+-#define I2S1_CRC_TEST_CNTL__I2S1_CRC_TEST_EN_MASK 0x00000001L
+-#define I2S1_CRC_TEST_CNTL__I2S1_CRC_SOFT_RESET_MASK 0x00000002L
+-#define I2S1_CRC_TEST_CNTL__I2S1_CRC_TEST_CONT_EN_MASK 0x00000010L
+-#define I2S1_CRC_TEST_CNTL__I2S1_CRC_TEST_NUMBER_OF_SAMPLES_MASK 0xFFFFFF00L
+-//I2S1_CRC_TEST_DATA_0
+-#define I2S1_CRC_TEST_DATA_0__I2S1_CRC_TEST_DATA0__SHIFT 0x0
+-#define I2S1_CRC_TEST_DATA_0__I2S1_CRC_TEST_DATA0_MASK 0x0000FFFFL
+-//SPDIF0_CRC_TEST_CNTL
+-#define SPDIF0_CRC_TEST_CNTL__SPDIF0_CRC_TEST_EN__SHIFT 0x0
+-#define SPDIF0_CRC_TEST_CNTL__SPDIF0_CRC_SOFT_RESET__SHIFT 0x1
+-#define SPDIF0_CRC_TEST_CNTL__SPDIF0_CRC_TEST_CONT_EN__SHIFT 0x4
+-#define SPDIF0_CRC_TEST_CNTL__SPDIF0_CRC_TEST_NUMBER_OF_SAMPLES__SHIFT 0x8
+-#define SPDIF0_CRC_TEST_CNTL__SPDIF0_CRC_TEST_EN_MASK 0x00000001L
+-#define SPDIF0_CRC_TEST_CNTL__SPDIF0_CRC_SOFT_RESET_MASK 0x00000002L
+-#define SPDIF0_CRC_TEST_CNTL__SPDIF0_CRC_TEST_CONT_EN_MASK 0x00000010L
+-#define SPDIF0_CRC_TEST_CNTL__SPDIF0_CRC_TEST_NUMBER_OF_SAMPLES_MASK 0xFFFFFF00L
+-//SPDIF0_CRC_TEST_DATA_0
+-#define SPDIF0_CRC_TEST_DATA_0__SPDIF0_CRC_TEST_DATA0__SHIFT 0x0
+-#define SPDIF0_CRC_TEST_DATA_0__SPDIF0_CRC_TEST_DATA0_MASK 0x0000FFFFL
+-//SPDIF1_CRC_TEST_CNTL
+-#define SPDIF1_CRC_TEST_CNTL__SPDIF1_CRC_TEST_EN__SHIFT 0x0
+-#define SPDIF1_CRC_TEST_CNTL__SPDIF1_CRC_SOFT_RESET__SHIFT 0x1
+-#define SPDIF1_CRC_TEST_CNTL__SPDIF1_CRC_TEST_CONT_EN__SHIFT 0x4
+-#define SPDIF1_CRC_TEST_CNTL__SPDIF1_CRC_TEST_NUMBER_OF_SAMPLES__SHIFT 0x8
+-#define SPDIF1_CRC_TEST_CNTL__SPDIF1_CRC_TEST_EN_MASK 0x00000001L
+-#define SPDIF1_CRC_TEST_CNTL__SPDIF1_CRC_SOFT_RESET_MASK 0x00000002L
+-#define SPDIF1_CRC_TEST_CNTL__SPDIF1_CRC_TEST_CONT_EN_MASK 0x00000010L
+-#define SPDIF1_CRC_TEST_CNTL__SPDIF1_CRC_TEST_NUMBER_OF_SAMPLES_MASK 0xFFFFFF00L
+-//SPDIF1_CRC_TEST_DATA
+-#define SPDIF1_CRC_TEST_DATA__SPDIF1_CRC_TEST_DATA__SHIFT 0x0
+-#define SPDIF1_CRC_TEST_DATA__SPDIF1_CRC_TEST_DATA_MASK 0x0000FFFFL
+-//CRC_I2S_CONT_REPEAT_NUM
+-#define CRC_I2S_CONT_REPEAT_NUM__I2S0_CRC_CONT_REPEAT_NUM__SHIFT 0x0
+-#define CRC_I2S_CONT_REPEAT_NUM__I2S1_CRC_CONT_REPEAT_NUM__SHIFT 0x10
+-#define CRC_I2S_CONT_REPEAT_NUM__I2S0_CRC_CONT_REPEAT_NUM_MASK 0x0000FFFFL
+-#define CRC_I2S_CONT_REPEAT_NUM__I2S1_CRC_CONT_REPEAT_NUM_MASK 0xFFFF0000L
+-//CRC_SPDIF_CONT_REPEAT_NUM
+-#define CRC_SPDIF_CONT_REPEAT_NUM__SPDIF0_CRC_CONT_REPEAT_NUM__SHIFT 0x0
+-#define CRC_SPDIF_CONT_REPEAT_NUM__SPDIF1_CRC_CONT_REPEAT_NUM__SHIFT 0x10
+-#define CRC_SPDIF_CONT_REPEAT_NUM__SPDIF0_CRC_CONT_REPEAT_NUM_MASK 0x0000FFFFL
+-#define CRC_SPDIF_CONT_REPEAT_NUM__SPDIF1_CRC_CONT_REPEAT_NUM_MASK 0xFFFF0000L
+-//ZCAL_MACRO_CNTL_RESERVED0
+-#define ZCAL_MACRO_CNTL_RESERVED0__ZCAL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define ZCAL_MACRO_CNTL_RESERVED0__ZCAL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//ZCAL_MACRO_CNTL_RESERVED1
+-#define ZCAL_MACRO_CNTL_RESERVED1__ZCAL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define ZCAL_MACRO_CNTL_RESERVED1__ZCAL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//ZCAL_MACRO_CNTL_RESERVED2
+-#define ZCAL_MACRO_CNTL_RESERVED2__ZCAL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define ZCAL_MACRO_CNTL_RESERVED2__ZCAL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//ZCAL_MACRO_CNTL_RESERVED3
+-#define ZCAL_MACRO_CNTL_RESERVED3__ZCAL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define ZCAL_MACRO_CNTL_RESERVED3__ZCAL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//ZCAL_MACRO_CNTL_RESERVED4
+-#define ZCAL_MACRO_CNTL_RESERVED4__ZCAL_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define ZCAL_MACRO_CNTL_RESERVED4__ZCAL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_azf0stream0_dispdec
+-//AZF0STREAM0_AZALIA_STREAM_INDEX
+-#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+-#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+-#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+-#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+-//AZF0STREAM0_AZALIA_STREAM_DATA
+-#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+-#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_azf0stream1_dispdec
+-//AZF0STREAM1_AZALIA_STREAM_INDEX
+-#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+-#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+-#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+-#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+-//AZF0STREAM1_AZALIA_STREAM_DATA
+-#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+-#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_azf0stream2_dispdec
+-//AZF0STREAM2_AZALIA_STREAM_INDEX
+-#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+-#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+-#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+-#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+-//AZF0STREAM2_AZALIA_STREAM_DATA
+-#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+-#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_azf0stream3_dispdec
+-//AZF0STREAM3_AZALIA_STREAM_INDEX
+-#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+-#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+-#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+-#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+-//AZF0STREAM3_AZALIA_STREAM_DATA
+-#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+-#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_azf0stream4_dispdec
+-//AZF0STREAM4_AZALIA_STREAM_INDEX
+-#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+-#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+-#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+-#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+-//AZF0STREAM4_AZALIA_STREAM_DATA
+-#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+-#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_azf0stream5_dispdec
+-//AZF0STREAM5_AZALIA_STREAM_INDEX
+-#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+-#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+-#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+-#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+-//AZF0STREAM5_AZALIA_STREAM_DATA
+-#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+-#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_azf0stream6_dispdec
+-//AZF0STREAM6_AZALIA_STREAM_INDEX
+-#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+-#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+-#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+-#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+-//AZF0STREAM6_AZALIA_STREAM_DATA
+-#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+-#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_azf0stream7_dispdec
+-//AZF0STREAM7_AZALIA_STREAM_INDEX
+-#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+-#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+-#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+-#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+-//AZF0STREAM7_AZALIA_STREAM_DATA
+-#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+-#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_azf0endpoint0_dispdec
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_azf0endpoint1_dispdec
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_azf0endpoint2_dispdec
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_azf0endpoint3_dispdec
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_azf0endpoint4_dispdec
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_azf0endpoint5_dispdec
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_azf0endpoint6_dispdec
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_azf0endpoint7_dispdec
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_azf0stream8_dispdec
+-//AZF0STREAM8_AZALIA_STREAM_INDEX
+-#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+-#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+-#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+-#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+-//AZF0STREAM8_AZALIA_STREAM_DATA
+-#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+-#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_azf0stream9_dispdec
+-//AZF0STREAM9_AZALIA_STREAM_INDEX
+-#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+-#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+-#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+-#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+-//AZF0STREAM9_AZALIA_STREAM_DATA
+-#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+-#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_azf0stream10_dispdec
+-//AZF0STREAM10_AZALIA_STREAM_INDEX
+-#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+-#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+-#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+-#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+-//AZF0STREAM10_AZALIA_STREAM_DATA
+-#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+-#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_azf0stream11_dispdec
+-//AZF0STREAM11_AZALIA_STREAM_INDEX
+-#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+-#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+-#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+-#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+-//AZF0STREAM11_AZALIA_STREAM_DATA
+-#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+-#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_azf0stream12_dispdec
+-//AZF0STREAM12_AZALIA_STREAM_INDEX
+-#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+-#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+-#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+-#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+-//AZF0STREAM12_AZALIA_STREAM_DATA
+-#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+-#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_azf0stream13_dispdec
+-//AZF0STREAM13_AZALIA_STREAM_INDEX
+-#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+-#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+-#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+-#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+-//AZF0STREAM13_AZALIA_STREAM_DATA
+-#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+-#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_azf0stream14_dispdec
+-//AZF0STREAM14_AZALIA_STREAM_INDEX
+-#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+-#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+-#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+-#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+-//AZF0STREAM14_AZALIA_STREAM_DATA
+-#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+-#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_azf0stream15_dispdec
+-//AZF0STREAM15_AZALIA_STREAM_INDEX
+-#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+-#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+-#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+-#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+-//AZF0STREAM15_AZALIA_STREAM_DATA
+-#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+-#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_azf0inputendpoint0_dispdec
+-//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+-//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_azf0inputendpoint1_dispdec
+-//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+-//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_azf0inputendpoint2_dispdec
+-//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+-//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_azf0inputendpoint3_dispdec
+-//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+-//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_azf0inputendpoint4_dispdec
+-//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+-//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_azf0inputendpoint5_dispdec
+-//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+-//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_azf0inputendpoint6_dispdec
+-//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+-//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_azf0inputendpoint7_dispdec
+-//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+-//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dcp0_dispdec
+-//DCP0_GRPH_ENABLE
+-#define DCP0_GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0
+-#define DCP0_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL__SHIFT 0x1
+-#define DCP0_GRPH_ENABLE__GRPH_ENABLE_MASK 0x00000001L
+-#define DCP0_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL_MASK 0x00000002L
+-//DCP0_GRPH_CONTROL
+-#define DCP0_GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0
+-#define DCP0_GRPH_CONTROL__GRPH_SE_ENABLE__SHIFT 0x2
+-#define DCP0_GRPH_CONTROL__GRPH_Z__SHIFT 0x4
+-#define DCP0_GRPH_CONTROL__GRPH_DIM_TYPE__SHIFT 0x6
+-#define DCP0_GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8
+-#define DCP0_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0xc
+-#define DCP0_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10
+-#define DCP0_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11
+-#define DCP0_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES__SHIFT 0x12
+-#define DCP0_GRPH_CONTROL__GRPH_SW_MODE__SHIFT 0x14
+-#define DCP0_GRPH_CONTROL__GRPH_NUM_PIPES__SHIFT 0x1c
+-#define DCP0_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f
+-#define DCP0_GRPH_CONTROL__GRPH_DEPTH_MASK 0x00000003L
+-#define DCP0_GRPH_CONTROL__GRPH_SE_ENABLE_MASK 0x00000004L
+-#define DCP0_GRPH_CONTROL__GRPH_Z_MASK 0x00000030L
+-#define DCP0_GRPH_CONTROL__GRPH_DIM_TYPE_MASK 0x000000C0L
+-#define DCP0_GRPH_CONTROL__GRPH_FORMAT_MASK 0x00000700L
+-#define DCP0_GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0x00007000L
+-#define DCP0_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x00010000L
+-#define DCP0_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x00020000L
+-#define DCP0_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES_MASK 0x000C0000L
+-#define DCP0_GRPH_CONTROL__GRPH_SW_MODE_MASK 0x01F00000L
+-#define DCP0_GRPH_CONTROL__GRPH_NUM_PIPES_MASK 0x70000000L
+-#define DCP0_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000L
+-//DCP0_GRPH_LUT_10BIT_BYPASS
+-#define DCP0_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT 0x8
+-#define DCP0_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x10
+-#define DCP0_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK 0x00000100L
+-#define DCP0_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x00010000L
+-//DCP0_GRPH_SWAP_CNTL
+-#define DCP0_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0
+-#define DCP0_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4
+-#define DCP0_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6
+-#define DCP0_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8
+-#define DCP0_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT 0xa
+-#define DCP0_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x00000003L
+-#define DCP0_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x00000030L
+-#define DCP0_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0x000000C0L
+-#define DCP0_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x00000300L
+-#define DCP0_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK 0x00000C00L
+-//DCP0_GRPH_PRIMARY_SURFACE_ADDRESS
+-#define DCP0_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT 0x0
+-#define DCP0_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT 0x8
+-#define DCP0_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK 0x00000001L
+-#define DCP0_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+-//DCP0_GRPH_SECONDARY_SURFACE_ADDRESS
+-#define DCP0_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT 0x0
+-#define DCP0_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8
+-#define DCP0_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK 0x00000001L
+-#define DCP0_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+-//DCP0_GRPH_PITCH
+-#define DCP0_GRPH_PITCH__GRPH_PITCH__SHIFT 0x0
+-#define DCP0_GRPH_PITCH__GRPH_PITCH_MASK 0x00007FFFL
+-//DCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+-#define DCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+-#define DCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+-//DCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+-#define DCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+-#define DCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+-//DCP0_GRPH_SURFACE_OFFSET_X
+-#define DCP0_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT 0x0
+-#define DCP0_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK 0x00003FFFL
+-//DCP0_GRPH_SURFACE_OFFSET_Y
+-#define DCP0_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT 0x0
+-#define DCP0_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK 0x00003FFFL
+-//DCP0_GRPH_X_START
+-#define DCP0_GRPH_X_START__GRPH_X_START__SHIFT 0x0
+-#define DCP0_GRPH_X_START__GRPH_X_START_MASK 0x00003FFFL
+-//DCP0_GRPH_Y_START
+-#define DCP0_GRPH_Y_START__GRPH_Y_START__SHIFT 0x0
+-#define DCP0_GRPH_Y_START__GRPH_Y_START_MASK 0x00003FFFL
+-//DCP0_GRPH_X_END
+-#define DCP0_GRPH_X_END__GRPH_X_END__SHIFT 0x0
+-#define DCP0_GRPH_X_END__GRPH_X_END_MASK 0x00007FFFL
+-//DCP0_GRPH_Y_END
+-#define DCP0_GRPH_Y_END__GRPH_Y_END__SHIFT 0x0
+-#define DCP0_GRPH_Y_END__GRPH_Y_END_MASK 0x00007FFFL
+-//DCP0_INPUT_GAMMA_CONTROL
+-#define DCP0_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x0
+-#define DCP0_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK 0x00000001L
+-//DCP0_GRPH_UPDATE
+-#define DCP0_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0
+-#define DCP0_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1
+-#define DCP0_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2
+-#define DCP0_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3
+-#define DCP0_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR__SHIFT 0x8
+-#define DCP0_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE__SHIFT 0x9
+-#define DCP0_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE__SHIFT 0xa
+-#define DCP0_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10
+-#define DCP0_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14
+-#define DCP0_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+-#define DCP0_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c
+-#define DCP0_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x00000001L
+-#define DCP0_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x00000002L
+-#define DCP0_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x00000004L
+-#define DCP0_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x00000008L
+-#define DCP0_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR_MASK 0x00000100L
+-#define DCP0_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE_MASK 0x00000200L
+-#define DCP0_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE_MASK 0x00000400L
+-#define DCP0_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x00010000L
+-#define DCP0_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x00100000L
+-#define DCP0_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
+-#define DCP0_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000L
+-//DCP0_GRPH_FLIP_CONTROL
+-#define DCP0_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT 0x0
+-#define DCP0_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN__SHIFT 0x1
+-#define DCP0_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN__SHIFT 0x4
+-#define DCP0_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT 0x5
+-#define DCP0_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK 0x00000001L
+-#define DCP0_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN_MASK 0x00000002L
+-#define DCP0_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN_MASK 0x00000010L
+-#define DCP0_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK 0x00000020L
+-//DCP0_GRPH_SURFACE_ADDRESS_INUSE
+-#define DCP0_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT 0x8
+-#define DCP0_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK 0xFFFFFF00L
+-//DCP0_GRPH_DFQ_CONTROL
+-#define DCP0_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x0
+-#define DCP0_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x4
+-#define DCP0_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8
+-#define DCP0_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x00000001L
+-#define DCP0_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x00000070L
+-#define DCP0_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x00000700L
+-//DCP0_GRPH_DFQ_STATUS
+-#define DCP0_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x0
+-#define DCP0_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4
+-#define DCP0_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x8
+-#define DCP0_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x9
+-#define DCP0_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0x0000000FL
+-#define DCP0_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0x000000F0L
+-#define DCP0_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x00000100L
+-#define DCP0_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x00000200L
+-//DCP0_GRPH_INTERRUPT_STATUS
+-#define DCP0_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0
+-#define DCP0_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8
+-#define DCP0_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x00000001L
+-#define DCP0_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x00000100L
+-//DCP0_GRPH_INTERRUPT_CONTROL
+-#define DCP0_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0
+-#define DCP0_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8
+-#define DCP0_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x00000001L
+-#define DCP0_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x00000100L
+-//DCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE
+-#define DCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0
+-#define DCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK 0x000000FFL
+-//DCP0_GRPH_COMPRESS_SURFACE_ADDRESS
+-#define DCP0_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT 0x8
+-#define DCP0_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+-//DCP0_GRPH_COMPRESS_PITCH
+-#define DCP0_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT 0x6
+-#define DCP0_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK 0x0001FFC0L
+-//DCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH
+-#define DCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+-#define DCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+-//DCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT
+-#define DCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__SHIFT 0x0
+-#define DCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_MASK 0x000000FFL
+-//DCP0_PRESCALE_GRPH_CONTROL
+-#define DCP0_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT 0x0
+-#define DCP0_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT 0x1
+-#define DCP0_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x2
+-#define DCP0_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT 0x3
+-#define DCP0_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT 0x4
+-#define DCP0_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK 0x00000001L
+-#define DCP0_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x00000002L
+-#define DCP0_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK 0x00000004L
+-#define DCP0_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK 0x00000008L
+-#define DCP0_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK 0x00000010L
+-//DCP0_PRESCALE_VALUES_GRPH_R
+-#define DCP0_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT 0x0
+-#define DCP0_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT 0x10
+-#define DCP0_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK 0x0000FFFFL
+-#define DCP0_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK 0xFFFF0000L
+-//DCP0_PRESCALE_VALUES_GRPH_G
+-#define DCP0_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT 0x0
+-#define DCP0_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT 0x10
+-#define DCP0_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK 0x0000FFFFL
+-#define DCP0_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK 0xFFFF0000L
+-//DCP0_PRESCALE_VALUES_GRPH_B
+-#define DCP0_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT 0x0
+-#define DCP0_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT 0x10
+-#define DCP0_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK 0x0000FFFFL
+-#define DCP0_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK 0xFFFF0000L
+-//DCP0_INPUT_CSC_CONTROL
+-#define DCP0_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT 0x0
+-#define DCP0_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK 0x00000003L
+-//DCP0_INPUT_CSC_C11_C12
+-#define DCP0_INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT 0x0
+-#define DCP0_INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT 0x10
+-#define DCP0_INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK 0x0000FFFFL
+-#define DCP0_INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK 0xFFFF0000L
+-//DCP0_INPUT_CSC_C13_C14
+-#define DCP0_INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT 0x0
+-#define DCP0_INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT 0x10
+-#define DCP0_INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK 0x0000FFFFL
+-#define DCP0_INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK 0xFFFF0000L
+-//DCP0_INPUT_CSC_C21_C22
+-#define DCP0_INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT 0x0
+-#define DCP0_INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT 0x10
+-#define DCP0_INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK 0x0000FFFFL
+-#define DCP0_INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK 0xFFFF0000L
+-//DCP0_INPUT_CSC_C23_C24
+-#define DCP0_INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT 0x0
+-#define DCP0_INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT 0x10
+-#define DCP0_INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK 0x0000FFFFL
+-#define DCP0_INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK 0xFFFF0000L
+-//DCP0_INPUT_CSC_C31_C32
+-#define DCP0_INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT 0x0
+-#define DCP0_INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT 0x10
+-#define DCP0_INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK 0x0000FFFFL
+-#define DCP0_INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK 0xFFFF0000L
+-//DCP0_INPUT_CSC_C33_C34
+-#define DCP0_INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT 0x0
+-#define DCP0_INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT 0x10
+-#define DCP0_INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK 0x0000FFFFL
+-#define DCP0_INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK 0xFFFF0000L
+-//DCP0_OUTPUT_CSC_CONTROL
+-#define DCP0_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT 0x0
+-#define DCP0_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK 0x00000007L
+-//DCP0_OUTPUT_CSC_C11_C12
+-#define DCP0_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT 0x0
+-#define DCP0_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT 0x10
+-#define DCP0_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK 0x0000FFFFL
+-#define DCP0_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK 0xFFFF0000L
+-//DCP0_OUTPUT_CSC_C13_C14
+-#define DCP0_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT 0x0
+-#define DCP0_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT 0x10
+-#define DCP0_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK 0x0000FFFFL
+-#define DCP0_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK 0xFFFF0000L
+-//DCP0_OUTPUT_CSC_C21_C22
+-#define DCP0_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT 0x0
+-#define DCP0_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT 0x10
+-#define DCP0_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK 0x0000FFFFL
+-#define DCP0_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK 0xFFFF0000L
+-//DCP0_OUTPUT_CSC_C23_C24
+-#define DCP0_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT 0x0
+-#define DCP0_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT 0x10
+-#define DCP0_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK 0x0000FFFFL
+-#define DCP0_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK 0xFFFF0000L
+-//DCP0_OUTPUT_CSC_C31_C32
+-#define DCP0_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT 0x0
+-#define DCP0_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT 0x10
+-#define DCP0_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK 0x0000FFFFL
+-#define DCP0_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK 0xFFFF0000L
+-//DCP0_OUTPUT_CSC_C33_C34
+-#define DCP0_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT 0x0
+-#define DCP0_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT 0x10
+-#define DCP0_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK 0x0000FFFFL
+-#define DCP0_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK 0xFFFF0000L
+-//DCP0_COMM_MATRIXA_TRANS_C11_C12
+-#define DCP0_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT 0x0
+-#define DCP0_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT 0x10
+-#define DCP0_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK 0x0000FFFFL
+-#define DCP0_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK 0xFFFF0000L
+-//DCP0_COMM_MATRIXA_TRANS_C13_C14
+-#define DCP0_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT 0x0
+-#define DCP0_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT 0x10
+-#define DCP0_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK 0x0000FFFFL
+-#define DCP0_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK 0xFFFF0000L
+-//DCP0_COMM_MATRIXA_TRANS_C21_C22
+-#define DCP0_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT 0x0
+-#define DCP0_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT 0x10
+-#define DCP0_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK 0x0000FFFFL
+-#define DCP0_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK 0xFFFF0000L
+-//DCP0_COMM_MATRIXA_TRANS_C23_C24
+-#define DCP0_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT 0x0
+-#define DCP0_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT 0x10
+-#define DCP0_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK 0x0000FFFFL
+-#define DCP0_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK 0xFFFF0000L
+-//DCP0_COMM_MATRIXA_TRANS_C31_C32
+-#define DCP0_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT 0x0
+-#define DCP0_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT 0x10
+-#define DCP0_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK 0x0000FFFFL
+-#define DCP0_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK 0xFFFF0000L
+-//DCP0_COMM_MATRIXA_TRANS_C33_C34
+-#define DCP0_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT 0x0
+-#define DCP0_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT 0x10
+-#define DCP0_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK 0x0000FFFFL
+-#define DCP0_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK 0xFFFF0000L
+-//DCP0_COMM_MATRIXB_TRANS_C11_C12
+-#define DCP0_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT 0x0
+-#define DCP0_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT 0x10
+-#define DCP0_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK 0x0000FFFFL
+-#define DCP0_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK 0xFFFF0000L
+-//DCP0_COMM_MATRIXB_TRANS_C13_C14
+-#define DCP0_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT 0x0
+-#define DCP0_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT 0x10
+-#define DCP0_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK 0x0000FFFFL
+-#define DCP0_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK 0xFFFF0000L
+-//DCP0_COMM_MATRIXB_TRANS_C21_C22
+-#define DCP0_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT 0x0
+-#define DCP0_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT 0x10
+-#define DCP0_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK 0x0000FFFFL
+-#define DCP0_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK 0xFFFF0000L
+-//DCP0_COMM_MATRIXB_TRANS_C23_C24
+-#define DCP0_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT 0x0
+-#define DCP0_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT 0x10
+-#define DCP0_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK 0x0000FFFFL
+-#define DCP0_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK 0xFFFF0000L
+-//DCP0_COMM_MATRIXB_TRANS_C31_C32
+-#define DCP0_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT 0x0
+-#define DCP0_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT 0x10
+-#define DCP0_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK 0x0000FFFFL
+-#define DCP0_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK 0xFFFF0000L
+-//DCP0_COMM_MATRIXB_TRANS_C33_C34
+-#define DCP0_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT 0x0
+-#define DCP0_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT 0x10
+-#define DCP0_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK 0x0000FFFFL
+-#define DCP0_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK 0xFFFF0000L
+-//DCP0_DENORM_CONTROL
+-#define DCP0_DENORM_CONTROL__DENORM_MODE__SHIFT 0x0
+-#define DCP0_DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT 0x4
+-#define DCP0_DENORM_CONTROL__DENORM_MODE_MASK 0x00000007L
+-#define DCP0_DENORM_CONTROL__DENORM_14BIT_OUT_MASK 0x00000010L
+-//DCP0_OUT_ROUND_CONTROL
+-#define DCP0_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT 0x0
+-#define DCP0_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK 0x0000000FL
+-//DCP0_OUT_CLAMP_CONTROL_R_CR
+-#define DCP0_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT 0x0
+-#define DCP0_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT 0x10
+-#define DCP0_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK 0x00003FFFL
+-#define DCP0_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK 0x3FFF0000L
+-//DCP0_OUT_CLAMP_CONTROL_G_Y
+-#define DCP0_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT 0x0
+-#define DCP0_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT 0x10
+-#define DCP0_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK 0x00003FFFL
+-#define DCP0_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK 0x3FFF0000L
+-//DCP0_OUT_CLAMP_CONTROL_B_CB
+-#define DCP0_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT 0x0
+-#define DCP0_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT 0x10
+-#define DCP0_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK 0x00003FFFL
+-#define DCP0_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK 0x3FFF0000L
+-//DCP0_KEY_CONTROL
+-#define DCP0_KEY_CONTROL__KEY_MODE__SHIFT 0x1
+-#define DCP0_KEY_CONTROL__KEY_MODE_MASK 0x00000006L
+-//DCP0_KEY_RANGE_ALPHA
+-#define DCP0_KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT 0x0
+-#define DCP0_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT 0x10
+-#define DCP0_KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK 0x0000FFFFL
+-#define DCP0_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK 0xFFFF0000L
+-//DCP0_KEY_RANGE_RED
+-#define DCP0_KEY_RANGE_RED__KEY_RED_LOW__SHIFT 0x0
+-#define DCP0_KEY_RANGE_RED__KEY_RED_HIGH__SHIFT 0x10
+-#define DCP0_KEY_RANGE_RED__KEY_RED_LOW_MASK 0x0000FFFFL
+-#define DCP0_KEY_RANGE_RED__KEY_RED_HIGH_MASK 0xFFFF0000L
+-//DCP0_KEY_RANGE_GREEN
+-#define DCP0_KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT 0x0
+-#define DCP0_KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT 0x10
+-#define DCP0_KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK 0x0000FFFFL
+-#define DCP0_KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK 0xFFFF0000L
+-//DCP0_KEY_RANGE_BLUE
+-#define DCP0_KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT 0x0
+-#define DCP0_KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT 0x10
+-#define DCP0_KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK 0x0000FFFFL
+-#define DCP0_KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK 0xFFFF0000L
+-//DCP0_DEGAMMA_CONTROL
+-#define DCP0_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x0
+-#define DCP0_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT 0x8
+-#define DCP0_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0xc
+-#define DCP0_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x00000003L
+-#define DCP0_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK 0x00000300L
+-#define DCP0_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK 0x00003000L
+-//DCP0_GAMUT_REMAP_CONTROL
+-#define DCP0_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT 0x0
+-#define DCP0_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK 0x00000003L
+-//DCP0_GAMUT_REMAP_C11_C12
+-#define DCP0_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT 0x0
+-#define DCP0_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT 0x10
+-#define DCP0_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK 0x0000FFFFL
+-#define DCP0_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK 0xFFFF0000L
+-//DCP0_GAMUT_REMAP_C13_C14
+-#define DCP0_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT 0x0
+-#define DCP0_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT 0x10
+-#define DCP0_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK 0x0000FFFFL
+-#define DCP0_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK 0xFFFF0000L
+-//DCP0_GAMUT_REMAP_C21_C22
+-#define DCP0_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT 0x0
+-#define DCP0_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT 0x10
+-#define DCP0_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK 0x0000FFFFL
+-#define DCP0_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK 0xFFFF0000L
+-//DCP0_GAMUT_REMAP_C23_C24
+-#define DCP0_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT 0x0
+-#define DCP0_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT 0x10
+-#define DCP0_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK 0x0000FFFFL
+-#define DCP0_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK 0xFFFF0000L
+-//DCP0_GAMUT_REMAP_C31_C32
+-#define DCP0_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT 0x0
+-#define DCP0_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT 0x10
+-#define DCP0_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK 0x0000FFFFL
+-#define DCP0_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK 0xFFFF0000L
+-//DCP0_GAMUT_REMAP_C33_C34
+-#define DCP0_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT 0x0
+-#define DCP0_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT 0x10
+-#define DCP0_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK 0x0000FFFFL
+-#define DCP0_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK 0xFFFF0000L
+-//DCP0_DCP_SPATIAL_DITHER_CNTL
+-#define DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT 0x0
+-#define DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT 0x4
+-#define DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT 0x6
+-#define DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT 0x8
+-#define DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT 0x9
+-#define DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT 0xa
+-#define DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK 0x00000001L
+-#define DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK 0x00000030L
+-#define DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK 0x000000C0L
+-#define DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK 0x00000100L
+-#define DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK 0x00000200L
+-#define DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK 0x00000400L
+-//DCP0_DCP_RANDOM_SEEDS
+-#define DCP0_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT 0x0
+-#define DCP0_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT 0x8
+-#define DCP0_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT 0x10
+-#define DCP0_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK 0x000000FFL
+-#define DCP0_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK 0x0000FF00L
+-#define DCP0_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK 0x00FF0000L
+-//DCP0_DCP_FP_CONVERTED_FIELD
+-#define DCP0_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT 0x0
+-#define DCP0_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14
+-#define DCP0_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK 0x0003FFFFL
+-#define DCP0_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK 0x07F00000L
+-//DCP0_CUR_CONTROL
+-#define DCP0_CUR_CONTROL__CURSOR_EN__SHIFT 0x0
+-#define DCP0_CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT 0x4
+-#define DCP0_CUR_CONTROL__CURSOR_MODE__SHIFT 0x8
+-#define DCP0_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM__SHIFT 0xb
+-#define DCP0_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION__SHIFT 0xc
+-#define DCP0_CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x10
+-#define DCP0_CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT 0x14
+-#define DCP0_CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT 0x18
+-#define DCP0_CUR_CONTROL__CURSOR_EN_MASK 0x00000001L
+-#define DCP0_CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK 0x00000010L
+-#define DCP0_CUR_CONTROL__CURSOR_MODE_MASK 0x00000300L
+-#define DCP0_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM_MASK 0x00000800L
+-#define DCP0_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION_MASK 0x0000F000L
+-#define DCP0_CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00010000L
+-#define DCP0_CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK 0x00100000L
+-#define DCP0_CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK 0x07000000L
+-//DCP0_CUR_SURFACE_ADDRESS
+-#define DCP0_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0
+-#define DCP0_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+-//DCP0_CUR_SIZE
+-#define DCP0_CUR_SIZE__CURSOR_HEIGHT__SHIFT 0x0
+-#define DCP0_CUR_SIZE__CURSOR_WIDTH__SHIFT 0x10
+-#define DCP0_CUR_SIZE__CURSOR_HEIGHT_MASK 0x0000007FL
+-#define DCP0_CUR_SIZE__CURSOR_WIDTH_MASK 0x007F0000L
+-//DCP0_CUR_SURFACE_ADDRESS_HIGH
+-#define DCP0_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+-#define DCP0_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+-//DCP0_CUR_POSITION
+-#define DCP0_CUR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0
+-#define DCP0_CUR_POSITION__CURSOR_X_POSITION__SHIFT 0x10
+-#define DCP0_CUR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL
+-#define DCP0_CUR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L
+-//DCP0_CUR_HOT_SPOT
+-#define DCP0_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0
+-#define DCP0_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10
+-#define DCP0_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x0000007FL
+-#define DCP0_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x007F0000L
+-//DCP0_CUR_COLOR1
+-#define DCP0_CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT 0x0
+-#define DCP0_CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT 0x8
+-#define DCP0_CUR_COLOR1__CUR_COLOR1_RED__SHIFT 0x10
+-#define DCP0_CUR_COLOR1__CUR_COLOR1_BLUE_MASK 0x000000FFL
+-#define DCP0_CUR_COLOR1__CUR_COLOR1_GREEN_MASK 0x0000FF00L
+-#define DCP0_CUR_COLOR1__CUR_COLOR1_RED_MASK 0x00FF0000L
+-//DCP0_CUR_COLOR2
+-#define DCP0_CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT 0x0
+-#define DCP0_CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT 0x8
+-#define DCP0_CUR_COLOR2__CUR_COLOR2_RED__SHIFT 0x10
+-#define DCP0_CUR_COLOR2__CUR_COLOR2_BLUE_MASK 0x000000FFL
+-#define DCP0_CUR_COLOR2__CUR_COLOR2_GREEN_MASK 0x0000FF00L
+-#define DCP0_CUR_COLOR2__CUR_COLOR2_RED_MASK 0x00FF0000L
+-//DCP0_CUR_UPDATE
+-#define DCP0_CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT 0x0
+-#define DCP0_CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT 0x1
+-#define DCP0_CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT 0x10
+-#define DCP0_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+-#define DCP0_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE__SHIFT 0x19
+-#define DCP0_CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK 0x00000001L
+-#define DCP0_CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x00000002L
+-#define DCP0_CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK 0x00010000L
+-#define DCP0_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
+-#define DCP0_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE_MASK 0x06000000L
+-//DCP0_CUR_REQUEST_FILTER_CNTL
+-#define DCP0_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT 0x0
+-#define DCP0_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK 0x00000001L
+-//DCP0_CUR_STEREO_CONTROL
+-#define DCP0_CUR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0
+-#define DCP0_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4
+-#define DCP0_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x10
+-#define DCP0_CUR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L
+-#define DCP0_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x00003FF0L
+-#define DCP0_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0x03FF0000L
+-//DCP0_DC_LUT_RW_MODE
+-#define DCP0_DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT 0x0
+-#define DCP0_DC_LUT_RW_MODE__DC_LUT_ERROR__SHIFT 0x10
+-#define DCP0_DC_LUT_RW_MODE__DC_LUT_ERROR_RST__SHIFT 0x11
+-#define DCP0_DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK 0x00000001L
+-#define DCP0_DC_LUT_RW_MODE__DC_LUT_ERROR_MASK 0x00010000L
+-#define DCP0_DC_LUT_RW_MODE__DC_LUT_ERROR_RST_MASK 0x00020000L
+-//DCP0_DC_LUT_RW_INDEX
+-#define DCP0_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT 0x0
+-#define DCP0_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK 0x000000FFL
+-//DCP0_DC_LUT_SEQ_COLOR
+-#define DCP0_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT 0x0
+-#define DCP0_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK 0x0000FFFFL
+-//DCP0_DC_LUT_PWL_DATA
+-#define DCP0_DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT 0x0
+-#define DCP0_DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT 0x10
+-#define DCP0_DC_LUT_PWL_DATA__DC_LUT_BASE_MASK 0x0000FFFFL
+-#define DCP0_DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK 0xFFFF0000L
+-//DCP0_DC_LUT_30_COLOR
+-#define DCP0_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT 0x0
+-#define DCP0_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT 0xa
+-#define DCP0_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT 0x14
+-#define DCP0_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK 0x000003FFL
+-#define DCP0_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK 0x000FFC00L
+-#define DCP0_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK 0x3FF00000L
+-//DCP0_DC_LUT_VGA_ACCESS_ENABLE
+-#define DCP0_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT 0x0
+-#define DCP0_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK 0x00000001L
+-//DCP0_DC_LUT_WRITE_EN_MASK
+-#define DCP0_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT 0x0
+-#define DCP0_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK 0x00000007L
+-//DCP0_DC_LUT_AUTOFILL
+-#define DCP0_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT 0x0
+-#define DCP0_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT 0x1
+-#define DCP0_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK 0x00000001L
+-#define DCP0_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x00000002L
+-//DCP0_DC_LUT_CONTROL
+-#define DCP0_DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT 0x0
+-#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT 0x4
+-#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT 0x5
+-#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT 0x6
+-#define DCP0_DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT 0x8
+-#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT 0xc
+-#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT 0xd
+-#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT 0xe
+-#define DCP0_DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT 0x10
+-#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT 0x14
+-#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT 0x15
+-#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT 0x16
+-#define DCP0_DC_LUT_CONTROL__DC_LUT_INC_B_MASK 0x0000000FL
+-#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK 0x00000010L
+-#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK 0x00000020L
+-#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK 0x000000C0L
+-#define DCP0_DC_LUT_CONTROL__DC_LUT_INC_G_MASK 0x00000F00L
+-#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK 0x00001000L
+-#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK 0x00002000L
+-#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK 0x0000C000L
+-#define DCP0_DC_LUT_CONTROL__DC_LUT_INC_R_MASK 0x000F0000L
+-#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK 0x00100000L
+-#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK 0x00200000L
+-#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK 0x00C00000L
+-//DCP0_DC_LUT_BLACK_OFFSET_BLUE
+-#define DCP0_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0
+-#define DCP0_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK 0x0000FFFFL
+-//DCP0_DC_LUT_BLACK_OFFSET_GREEN
+-#define DCP0_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0
+-#define DCP0_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK 0x0000FFFFL
+-//DCP0_DC_LUT_BLACK_OFFSET_RED
+-#define DCP0_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT 0x0
+-#define DCP0_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK 0x0000FFFFL
+-//DCP0_DC_LUT_WHITE_OFFSET_BLUE
+-#define DCP0_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT 0x0
+-#define DCP0_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK 0x0000FFFFL
+-//DCP0_DC_LUT_WHITE_OFFSET_GREEN
+-#define DCP0_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT 0x0
+-#define DCP0_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK 0x0000FFFFL
+-//DCP0_DC_LUT_WHITE_OFFSET_RED
+-#define DCP0_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT 0x0
+-#define DCP0_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK 0x0000FFFFL
+-//DCP0_DCP_CRC_CONTROL
+-#define DCP0_DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT 0x0
+-#define DCP0_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x2
+-#define DCP0_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT 0x8
+-#define DCP0_DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK 0x00000001L
+-#define DCP0_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK 0x0000001CL
+-#define DCP0_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK 0x00000300L
+-//DCP0_DCP_CRC_MASK
+-#define DCP0_DCP_CRC_MASK__DCP_CRC_MASK__SHIFT 0x0
+-#define DCP0_DCP_CRC_MASK__DCP_CRC_MASK_MASK 0xFFFFFFFFL
+-//DCP0_DCP_CRC_CURRENT
+-#define DCP0_DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT 0x0
+-#define DCP0_DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK 0xFFFFFFFFL
+-//DCP0_DVMM_PTE_CONTROL
+-#define DCP0_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT 0x0
+-#define DCP0_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT 0x1
+-#define DCP0_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT 0x5
+-#define DCP0_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT 0x9
+-#define DCP0_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT 0x14
+-#define DCP0_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT 0x15
+-#define DCP0_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK 0x00000001L
+-#define DCP0_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK 0x0000001EL
+-#define DCP0_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK 0x000001E0L
+-#define DCP0_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK 0x0007FE00L
+-#define DCP0_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK 0x00100000L
+-#define DCP0_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK 0x00200000L
+-//DCP0_DCP_CRC_LAST
+-#define DCP0_DCP_CRC_LAST__DCP_CRC_LAST__SHIFT 0x0
+-#define DCP0_DCP_CRC_LAST__DCP_CRC_LAST_MASK 0xFFFFFFFFL
+-//DCP0_DVMM_PTE_ARB_CONTROL
+-#define DCP0_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT 0x0
+-#define DCP0_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT 0x8
+-#define DCP0_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK 0x0000003FL
+-#define DCP0_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK 0x0000FF00L
+-//DCP0_GRPH_FLIP_RATE_CNTL
+-#define DCP0_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT 0x0
+-#define DCP0_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT 0x3
+-#define DCP0_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK 0x00000007L
+-#define DCP0_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK 0x00000008L
+-//DCP0_DCP_GSL_CONTROL
+-#define DCP0_DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT 0x0
+-#define DCP0_DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT 0x1
+-#define DCP0_DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x2
+-#define DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT 0x4
+-#define DCP0_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT 0x14
+-#define DCP0_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP__SHIFT 0x15
+-#define DCP0_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN__SHIFT 0x17
+-#define DCP0_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT 0x18
+-#define DCP0_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC__SHIFT 0x1a
+-#define DCP0_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT 0x1b
+-#define DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT 0x1c
+-#define DCP0_DCP_GSL_CONTROL__DCP_GSL0_EN_MASK 0x00000001L
+-#define DCP0_DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x00000002L
+-#define DCP0_DCP_GSL_CONTROL__DCP_GSL2_EN_MASK 0x00000004L
+-#define DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK 0x000FFFF0L
+-#define DCP0_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK 0x00100000L
+-#define DCP0_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_MASK 0x00600000L
+-#define DCP0_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_MASK 0x00800000L
+-#define DCP0_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK 0x03000000L
+-#define DCP0_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_MASK 0x04000000L
+-#define DCP0_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK 0x08000000L
+-#define DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK 0xF0000000L
+-//DCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK
+-#define DCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT 0x0
+-#define DCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT 0x4
+-#define DCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK 0x0000000FL
+-#define DCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK 0x000001F0L
+-//DCP0_GRPH_STEREOSYNC_FLIP
+-#define DCP0_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0
+-#define DCP0_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x8
+-#define DCP0_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10
+-#define DCP0_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11
+-#define DCP0_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c
+-#define DCP0_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x00000001L
+-#define DCP0_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x00000300L
+-#define DCP0_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x00010000L
+-#define DCP0_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x00020000L
+-#define DCP0_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000L
+-//DCP0_HW_ROTATION
+-#define DCP0_HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT 0x0
+-#define DCP0_HW_ROTATION__GRPH_ROTATION_ANGLE_MASK 0x00000007L
+-//DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL
+-#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT 0x0
+-#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT 0x1
+-#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT 0x4
+-#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK 0x00000001L
+-#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK 0x00000002L
+-#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK 0x0001FFF0L
+-//DCP0_REGAMMA_CONTROL
+-#define DCP0_REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT 0x0
+-#define DCP0_REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK 0x00000007L
+-//DCP0_REGAMMA_LUT_INDEX
+-#define DCP0_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x0
+-#define DCP0_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK 0x000001FFL
+-//DCP0_REGAMMA_LUT_DATA
+-#define DCP0_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT 0x0
+-#define DCP0_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK 0x0007FFFFL
+-//DCP0_REGAMMA_LUT_WRITE_EN_MASK
+-#define DCP0_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x0
+-#define DCP0_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x00000007L
+-//DCP0_REGAMMA_CNTLA_START_CNTL
+-#define DCP0_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x0
+-#define DCP0_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14
+-#define DCP0_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK 0x0003FFFFL
+-#define DCP0_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
+-//DCP0_REGAMMA_CNTLA_SLOPE_CNTL
+-#define DCP0_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+-#define DCP0_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
+-//DCP0_REGAMMA_CNTLA_END_CNTL1
+-#define DCP0_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x0
+-#define DCP0_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK 0x0000FFFFL
+-//DCP0_REGAMMA_CNTLA_END_CNTL2
+-#define DCP0_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0
+-#define DCP0_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10
+-#define DCP0_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
+-#define DCP0_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xFFFF0000L
+-//DCP0_REGAMMA_CNTLA_REGION_0_1
+-#define DCP0_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+-#define DCP0_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP0_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+-#define DCP0_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP0_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP0_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP0_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP0_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP0_REGAMMA_CNTLA_REGION_2_3
+-#define DCP0_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+-#define DCP0_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP0_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+-#define DCP0_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP0_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP0_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP0_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP0_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP0_REGAMMA_CNTLA_REGION_4_5
+-#define DCP0_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+-#define DCP0_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP0_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+-#define DCP0_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP0_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP0_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP0_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP0_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP0_REGAMMA_CNTLA_REGION_6_7
+-#define DCP0_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+-#define DCP0_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP0_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+-#define DCP0_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP0_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP0_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP0_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP0_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP0_REGAMMA_CNTLA_REGION_8_9
+-#define DCP0_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+-#define DCP0_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP0_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+-#define DCP0_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP0_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP0_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP0_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP0_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP0_REGAMMA_CNTLA_REGION_10_11
+-#define DCP0_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+-#define DCP0_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP0_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+-#define DCP0_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP0_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP0_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP0_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP0_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP0_REGAMMA_CNTLA_REGION_12_13
+-#define DCP0_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+-#define DCP0_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP0_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+-#define DCP0_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP0_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP0_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP0_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP0_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP0_REGAMMA_CNTLA_REGION_14_15
+-#define DCP0_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+-#define DCP0_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP0_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+-#define DCP0_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP0_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP0_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP0_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP0_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP0_REGAMMA_CNTLB_START_CNTL
+-#define DCP0_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x0
+-#define DCP0_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14
+-#define DCP0_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK 0x0003FFFFL
+-#define DCP0_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
+-//DCP0_REGAMMA_CNTLB_SLOPE_CNTL
+-#define DCP0_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+-#define DCP0_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
+-//DCP0_REGAMMA_CNTLB_END_CNTL1
+-#define DCP0_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x0
+-#define DCP0_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK 0x0000FFFFL
+-//DCP0_REGAMMA_CNTLB_END_CNTL2
+-#define DCP0_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0
+-#define DCP0_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10
+-#define DCP0_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
+-#define DCP0_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xFFFF0000L
+-//DCP0_REGAMMA_CNTLB_REGION_0_1
+-#define DCP0_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+-#define DCP0_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP0_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+-#define DCP0_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP0_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP0_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP0_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP0_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP0_REGAMMA_CNTLB_REGION_2_3
+-#define DCP0_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+-#define DCP0_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP0_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+-#define DCP0_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP0_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP0_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP0_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP0_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP0_REGAMMA_CNTLB_REGION_4_5
+-#define DCP0_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+-#define DCP0_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP0_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+-#define DCP0_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP0_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP0_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP0_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP0_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP0_REGAMMA_CNTLB_REGION_6_7
+-#define DCP0_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+-#define DCP0_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP0_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+-#define DCP0_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP0_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP0_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP0_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP0_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP0_REGAMMA_CNTLB_REGION_8_9
+-#define DCP0_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+-#define DCP0_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP0_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+-#define DCP0_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP0_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP0_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP0_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP0_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP0_REGAMMA_CNTLB_REGION_10_11
+-#define DCP0_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+-#define DCP0_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP0_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+-#define DCP0_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP0_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP0_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP0_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP0_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP0_REGAMMA_CNTLB_REGION_12_13
+-#define DCP0_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+-#define DCP0_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP0_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+-#define DCP0_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP0_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP0_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP0_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP0_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP0_REGAMMA_CNTLB_REGION_14_15
+-#define DCP0_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+-#define DCP0_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP0_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+-#define DCP0_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP0_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP0_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP0_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP0_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP0_ALPHA_CONTROL
+-#define DCP0_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT 0x0
+-#define DCP0_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT 0x1
+-#define DCP0_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK 0x00000001L
+-#define DCP0_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK 0x00000002L
+-//DCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS
+-#define DCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT 0x8
+-#define DCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+-//DCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH
+-#define DCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+-#define DCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+-//DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS
+-#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT 0x0
+-#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT 0x18
+-#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT 0x19
+-#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT 0x1a
+-#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT 0x1c
+-#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT 0x1d
+-#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT 0x1e
+-#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK 0x000FFFFFL
+-#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK 0x01000000L
+-#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK 0x02000000L
+-#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK 0x04000000L
+-#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK 0x10000000L
+-#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK 0x20000000L
+-#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK 0x40000000L
+-//DCP0_GRPH_XDMA_FLIP_TIMEOUT
+-#define DCP0_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS__SHIFT 0x0
+-#define DCP0_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK__SHIFT 0x1
+-#define DCP0_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK__SHIFT 0x2
+-#define DCP0_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS_MASK 0x00000001L
+-#define DCP0_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK_MASK 0x00000002L
+-#define DCP0_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK_MASK 0x00000004L
+-//DCP0_GRPH_XDMA_FLIP_AVG_DELAY
+-#define DCP0_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY__SHIFT 0x0
+-#define DCP0_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD__SHIFT 0x10
+-#define DCP0_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY_MASK 0x0000FFFFL
+-#define DCP0_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD_MASK 0x00FF0000L
+-//DCP0_GRPH_SURFACE_COUNTER_CONTROL
+-#define DCP0_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN__SHIFT 0x0
+-#define DCP0_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT__SHIFT 0x1
+-#define DCP0_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED__SHIFT 0x9
+-#define DCP0_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN_MASK 0x00000001L
+-#define DCP0_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT_MASK 0x0000001EL
+-#define DCP0_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_MASK 0x00000200L
+-//DCP0_GRPH_SURFACE_COUNTER_OUTPUT
+-#define DCP0_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN__SHIFT 0x0
+-#define DCP0_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX__SHIFT 0x10
+-#define DCP0_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN_MASK 0x0000FFFFL
+-#define DCP0_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX_MASK 0xFFFF0000L
+-
+-
+-// addressBlock: dce_dc_lb0_dispdec
+-//LB0_LB_DATA_FORMAT
+-#define LB0_LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0
+-#define LB0_LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2
+-#define LB0_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3
+-#define LB0_LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4
+-#define LB0_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5
+-#define LB0_LB_DATA_FORMAT__PREFILL_EN__SHIFT 0x8
+-#define LB0_LB_DATA_FORMAT__PREFETCH__SHIFT 0xc
+-#define LB0_LB_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18
+-#define LB0_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f
+-#define LB0_LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x00000003L
+-#define LB0_LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x00000004L
+-#define LB0_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000008L
+-#define LB0_LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x00000010L
+-#define LB0_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x00000020L
+-#define LB0_LB_DATA_FORMAT__PREFILL_EN_MASK 0x00000100L
+-#define LB0_LB_DATA_FORMAT__PREFETCH_MASK 0x00001000L
+-#define LB0_LB_DATA_FORMAT__REQUEST_MODE_MASK 0x01000000L
+-#define LB0_LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000L
+-//LB0_LB_MEMORY_CTRL
+-#define LB0_LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0
+-#define LB0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
+-#define LB0_LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14
+-#define LB0_LB_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0x00001FFFL
+-#define LB0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x000F0000L
+-#define LB0_LB_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x00300000L
+-//LB0_LB_MEMORY_SIZE_STATUS
+-#define LB0_LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0
+-#define LB0_LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0x00001FFFL
+-//LB0_LB_DESKTOP_HEIGHT
+-#define LB0_LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0
+-#define LB0_LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x00007FFFL
+-//LB0_LB_VLINE_START_END
+-#define LB0_LB_VLINE_START_END__VLINE_START__SHIFT 0x0
+-#define LB0_LB_VLINE_START_END__VLINE_END__SHIFT 0x10
+-#define LB0_LB_VLINE_START_END__VLINE_INV__SHIFT 0x1f
+-#define LB0_LB_VLINE_START_END__VLINE_START_MASK 0x00003FFFL
+-#define LB0_LB_VLINE_START_END__VLINE_END_MASK 0x7FFF0000L
+-#define LB0_LB_VLINE_START_END__VLINE_INV_MASK 0x80000000L
+-//LB0_LB_VLINE2_START_END
+-#define LB0_LB_VLINE2_START_END__VLINE2_START__SHIFT 0x0
+-#define LB0_LB_VLINE2_START_END__VLINE2_END__SHIFT 0x10
+-#define LB0_LB_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f
+-#define LB0_LB_VLINE2_START_END__VLINE2_START_MASK 0x00003FFFL
+-#define LB0_LB_VLINE2_START_END__VLINE2_END_MASK 0x7FFF0000L
+-#define LB0_LB_VLINE2_START_END__VLINE2_INV_MASK 0x80000000L
+-//LB0_LB_V_COUNTER
+-#define LB0_LB_V_COUNTER__V_COUNTER__SHIFT 0x0
+-#define LB0_LB_V_COUNTER__V_COUNTER_MASK 0x00007FFFL
+-//LB0_LB_SNAPSHOT_V_COUNTER
+-#define LB0_LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0
+-#define LB0_LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x00007FFFL
+-//LB0_LB_INTERRUPT_MASK
+-#define LB0_LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0
+-#define LB0_LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4
+-#define LB0_LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8
+-#define LB0_LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x00000001L
+-#define LB0_LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x00000010L
+-#define LB0_LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x00000100L
+-//LB0_LB_VLINE_STATUS
+-#define LB0_LB_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0
+-#define LB0_LB_VLINE_STATUS__VLINE_ACK__SHIFT 0x4
+-#define LB0_LB_VLINE_STATUS__VLINE_STAT__SHIFT 0xc
+-#define LB0_LB_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10
+-#define LB0_LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11
+-#define LB0_LB_VLINE_STATUS__VLINE_OCCURRED_MASK 0x00000001L
+-#define LB0_LB_VLINE_STATUS__VLINE_ACK_MASK 0x00000010L
+-#define LB0_LB_VLINE_STATUS__VLINE_STAT_MASK 0x00001000L
+-#define LB0_LB_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x00010000L
+-#define LB0_LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x00020000L
+-//LB0_LB_VLINE2_STATUS
+-#define LB0_LB_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0
+-#define LB0_LB_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4
+-#define LB0_LB_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc
+-#define LB0_LB_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10
+-#define LB0_LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11
+-#define LB0_LB_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x00000001L
+-#define LB0_LB_VLINE2_STATUS__VLINE2_ACK_MASK 0x00000010L
+-#define LB0_LB_VLINE2_STATUS__VLINE2_STAT_MASK 0x00001000L
+-#define LB0_LB_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x00010000L
+-#define LB0_LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x00020000L
+-//LB0_LB_VBLANK_STATUS
+-#define LB0_LB_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0
+-#define LB0_LB_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4
+-#define LB0_LB_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc
+-#define LB0_LB_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10
+-#define LB0_LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11
+-#define LB0_LB_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x00000001L
+-#define LB0_LB_VBLANK_STATUS__VBLANK_ACK_MASK 0x00000010L
+-#define LB0_LB_VBLANK_STATUS__VBLANK_STAT_MASK 0x00001000L
+-#define LB0_LB_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x00010000L
+-#define LB0_LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x00020000L
+-//LB0_LB_SYNC_RESET_SEL
+-#define LB0_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0
+-#define LB0_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4
+-#define LB0_LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8
+-#define LB0_LB_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16
+-#define LB0_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x00000003L
+-#define LB0_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x00000010L
+-#define LB0_LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0x0000FF00L
+-#define LB0_LB_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0x00C00000L
+-//LB0_LB_BLACK_KEYER_R_CR
+-#define LB0_LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4
+-#define LB0_LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0x0000FFF0L
+-//LB0_LB_BLACK_KEYER_G_Y
+-#define LB0_LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4
+-#define LB0_LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0x0000FFF0L
+-//LB0_LB_BLACK_KEYER_B_CB
+-#define LB0_LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4
+-#define LB0_LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0x0000FFF0L
+-//LB0_LB_KEYER_COLOR_CTRL
+-#define LB0_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0
+-#define LB0_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8
+-#define LB0_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x00000001L
+-#define LB0_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x00000100L
+-//LB0_LB_KEYER_COLOR_R_CR
+-#define LB0_LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4
+-#define LB0_LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0x0000FFF0L
+-//LB0_LB_KEYER_COLOR_G_Y
+-#define LB0_LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4
+-#define LB0_LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0x0000FFF0L
+-//LB0_LB_KEYER_COLOR_B_CB
+-#define LB0_LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4
+-#define LB0_LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0x0000FFF0L
+-//LB0_LB_KEYER_COLOR_REP_R_CR
+-#define LB0_LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4
+-#define LB0_LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0x0000FFF0L
+-//LB0_LB_KEYER_COLOR_REP_G_Y
+-#define LB0_LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4
+-#define LB0_LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0x0000FFF0L
+-//LB0_LB_KEYER_COLOR_REP_B_CB
+-#define LB0_LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4
+-#define LB0_LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0x0000FFF0L
+-//LB0_LB_BUFFER_LEVEL_STATUS
+-#define LB0_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0
+-#define LB0_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa
+-#define LB0_LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10
+-#define LB0_LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c
+-#define LB0_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x0000003FL
+-#define LB0_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0x0000FC00L
+-#define LB0_LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0x0FFF0000L
+-#define LB0_LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xF0000000L
+-//LB0_LB_BUFFER_URGENCY_CTRL
+-#define LB0_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0
+-#define LB0_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10
+-#define LB0_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0x00000FFFL
+-#define LB0_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0x0FFF0000L
+-//LB0_LB_BUFFER_URGENCY_STATUS
+-#define LB0_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0
+-#define LB0_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10
+-#define LB0_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0x00000FFFL
+-#define LB0_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x00010000L
+-//LB0_LB_BUFFER_STATUS
+-#define LB0_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0
+-#define LB0_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4
+-#define LB0_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8
+-#define LB0_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc
+-#define LB0_LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10
+-#define LB0_LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14
+-#define LB0_LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18
+-#define LB0_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0x0000000FL
+-#define LB0_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x00000010L
+-#define LB0_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x00000100L
+-#define LB0_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x00001000L
+-#define LB0_LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x00010000L
+-#define LB0_LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x00100000L
+-#define LB0_LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x01000000L
+-//LB0_LB_NO_OUTSTANDING_REQ_STATUS
+-#define LB0_LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0
+-#define LB0_LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x00000001L
+-//LB0_MVP_AFR_FLIP_MODE
+-#define LB0_MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT 0x0
+-#define LB0_MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK 0x00000003L
+-//LB0_MVP_AFR_FLIP_FIFO_CNTL
+-#define LB0_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT 0x0
+-#define LB0_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT 0x4
+-#define LB0_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT 0x8
+-#define LB0_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT 0xc
+-#define LB0_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK 0x0000000FL
+-#define LB0_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK 0x00000010L
+-#define LB0_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK 0x00000100L
+-#define LB0_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK 0x00001000L
+-//LB0_MVP_FLIP_LINE_NUM_INSERT
+-#define LB0_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT 0x0
+-#define LB0_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT 0x8
+-#define LB0_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT 0x18
+-#define LB0_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT 0x1e
+-#define LB0_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK 0x00000003L
+-#define LB0_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK 0x007FFF00L
+-#define LB0_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK 0x3F000000L
+-#define LB0_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK 0x40000000L
+-//LB0_DC_MVP_LB_CONTROL
+-#define LB0_DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT 0x0
+-#define LB0_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT 0x8
+-#define LB0_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT 0xc
+-#define LB0_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT 0x10
+-#define LB0_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT 0x14
+-#define LB0_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT 0x1c
+-#define LB0_DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT 0x1f
+-#define LB0_DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK 0x00000003L
+-#define LB0_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK 0x00000100L
+-#define LB0_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK 0x00001000L
+-#define LB0_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK 0x00010000L
+-#define LB0_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK 0x00100000L
+-#define LB0_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK 0x10000000L
+-#define LB0_DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK 0x80000000L
+-
+-
+-// addressBlock: dce_dc_dcfe0_dispdec
+-//DCFE0_DCFE_CLOCK_CONTROL
+-#define DCFE0_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x4
+-#define DCFE0_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x8
+-#define DCFE0_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0xc
+-#define DCFE0_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE__SHIFT 0xf
+-#define DCFE0_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE__SHIFT 0x11
+-#define DCFE0_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL__SHIFT 0x18
+-#define DCFE0_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE__SHIFT 0x1f
+-#define DCFE0_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x00000010L
+-#define DCFE0_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE_MASK 0x00000100L
+-#define DCFE0_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE_MASK 0x00001000L
+-#define DCFE0_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE_MASK 0x00008000L
+-#define DCFE0_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE_MASK 0x00020000L
+-#define DCFE0_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL_MASK 0x1F000000L
+-#define DCFE0_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE_MASK 0x80000000L
+-//DCFE0_DCFE_SOFT_RESET
+-#define DCFE0_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET__SHIFT 0x0
+-#define DCFE0_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET__SHIFT 0x1
+-#define DCFE0_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET__SHIFT 0x2
+-#define DCFE0_DCFE_SOFT_RESET__SCL_SOFT_RESET__SHIFT 0x3
+-#define DCFE0_DCFE_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4
+-#define DCFE0_DCFE_SOFT_RESET__PSCL_SOFT_RESET__SHIFT 0x5
+-#define DCFE0_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET_MASK 0x00000001L
+-#define DCFE0_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET_MASK 0x00000002L
+-#define DCFE0_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET_MASK 0x00000004L
+-#define DCFE0_DCFE_SOFT_RESET__SCL_SOFT_RESET_MASK 0x00000008L
+-#define DCFE0_DCFE_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x00000010L
+-#define DCFE0_DCFE_SOFT_RESET__PSCL_SOFT_RESET_MASK 0x00000020L
+-//DCFE0_DCFE_MEM_PWR_CTRL
+-#define DCFE0_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE__SHIFT 0x0
+-#define DCFE0_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS__SHIFT 0x2
+-#define DCFE0_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE__SHIFT 0x3
+-#define DCFE0_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS__SHIFT 0x5
+-#define DCFE0_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE__SHIFT 0x6
+-#define DCFE0_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS__SHIFT 0x8
+-#define DCFE0_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE__SHIFT 0x9
+-#define DCFE0_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS__SHIFT 0xb
+-#define DCFE0_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE__SHIFT 0xc
+-#define DCFE0_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS__SHIFT 0xe
+-#define DCFE0_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE__SHIFT 0xf
+-#define DCFE0_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS__SHIFT 0x11
+-#define DCFE0_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE__SHIFT 0x12
+-#define DCFE0_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS__SHIFT 0x14
+-#define DCFE0_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE__SHIFT 0x15
+-#define DCFE0_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS__SHIFT 0x17
+-#define DCFE0_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE__SHIFT 0x18
+-#define DCFE0_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS__SHIFT 0x1a
+-#define DCFE0_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE__SHIFT 0x1b
+-#define DCFE0_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS__SHIFT 0x1d
+-#define DCFE0_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE_MASK 0x00000003L
+-#define DCFE0_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS_MASK 0x00000004L
+-#define DCFE0_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE_MASK 0x00000018L
+-#define DCFE0_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS_MASK 0x00000020L
+-#define DCFE0_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE_MASK 0x000000C0L
+-#define DCFE0_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS_MASK 0x00000100L
+-#define DCFE0_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE_MASK 0x00000600L
+-#define DCFE0_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS_MASK 0x00000800L
+-#define DCFE0_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE_MASK 0x00003000L
+-#define DCFE0_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS_MASK 0x00004000L
+-#define DCFE0_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE_MASK 0x00018000L
+-#define DCFE0_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK 0x00020000L
+-#define DCFE0_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE_MASK 0x000C0000L
+-#define DCFE0_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS_MASK 0x00100000L
+-#define DCFE0_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE_MASK 0x00600000L
+-#define DCFE0_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS_MASK 0x00800000L
+-#define DCFE0_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE_MASK 0x03000000L
+-#define DCFE0_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS_MASK 0x04000000L
+-#define DCFE0_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE_MASK 0x18000000L
+-#define DCFE0_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS_MASK 0x20000000L
+-//DCFE0_DCFE_MEM_PWR_CTRL2
+-#define DCFE0_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL__SHIFT 0x0
+-#define DCFE0_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2
+-#define DCFE0_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4
+-#define DCFE0_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL__SHIFT 0x6
+-#define DCFE0_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL__SHIFT 0x8
+-#define DCFE0_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL__SHIFT 0xa
+-#define DCFE0_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL__SHIFT 0xc
+-#define DCFE0_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL__SHIFT 0xe
+-#define DCFE0_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE__SHIFT 0x10
+-#define DCFE0_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS__SHIFT 0x12
+-#define DCFE0_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE__SHIFT 0x15
+-#define DCFE0_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS__SHIFT 0x17
+-#define DCFE0_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL_MASK 0x00000003L
+-#define DCFE0_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL_MASK 0x0000000CL
+-#define DCFE0_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL_MASK 0x00000030L
+-#define DCFE0_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL_MASK 0x000000C0L
+-#define DCFE0_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL_MASK 0x00000300L
+-#define DCFE0_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL_MASK 0x00000C00L
+-#define DCFE0_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL_MASK 0x00003000L
+-#define DCFE0_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL_MASK 0x0000C000L
+-#define DCFE0_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE_MASK 0x00030000L
+-#define DCFE0_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS_MASK 0x00040000L
+-#define DCFE0_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE_MASK 0x00600000L
+-#define DCFE0_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS_MASK 0x00800000L
+-//DCFE0_DCFE_MEM_PWR_STATUS
+-#define DCFE0_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE__SHIFT 0x0
+-#define DCFE0_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE__SHIFT 0x2
+-#define DCFE0_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE__SHIFT 0x4
+-#define DCFE0_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x6
+-#define DCFE0_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE__SHIFT 0x8
+-#define DCFE0_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE__SHIFT 0xa
+-#define DCFE0_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE__SHIFT 0xc
+-#define DCFE0_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE__SHIFT 0xe
+-#define DCFE0_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT 0x10
+-#define DCFE0_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE__SHIFT 0x12
+-#define DCFE0_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE__SHIFT 0x14
+-#define DCFE0_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE__SHIFT 0x16
+-#define DCFE0_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK 0x00000003L
+-#define DCFE0_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE_MASK 0x0000000CL
+-#define DCFE0_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE_MASK 0x00000030L
+-#define DCFE0_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE_MASK 0x000000C0L
+-#define DCFE0_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE_MASK 0x00000300L
+-#define DCFE0_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE_MASK 0x00000C00L
+-#define DCFE0_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE_MASK 0x00003000L
+-#define DCFE0_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE_MASK 0x0000C000L
+-#define DCFE0_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE_MASK 0x00030000L
+-#define DCFE0_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK 0x000C0000L
+-#define DCFE0_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE_MASK 0x00300000L
+-#define DCFE0_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE_MASK 0x00C00000L
+-//DCFE0_DCFE_MISC
+-#define DCFE0_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN__SHIFT 0x0
+-#define DCFE0_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN_MASK 0x00000001L
+-//DCFE0_DCFE_FLUSH
+-#define DCFE0_DCFE_FLUSH__FLUSH_OCCURED__SHIFT 0x0
+-#define DCFE0_DCFE_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT 0x1
+-#define DCFE0_DCFE_FLUSH__FLUSH_DEEP__SHIFT 0x2
+-#define DCFE0_DCFE_FLUSH__CLEAR_FLUSH_DEEP__SHIFT 0x3
+-#define DCFE0_DCFE_FLUSH__ALL_MC_REQ_RET__SHIFT 0x4
+-#define DCFE0_DCFE_FLUSH__FLUSH_OCCURED_MASK 0x00000001L
+-#define DCFE0_DCFE_FLUSH__CLEAR_FLUSH_OCCURED_MASK 0x00000002L
+-#define DCFE0_DCFE_FLUSH__FLUSH_DEEP_MASK 0x00000004L
+-#define DCFE0_DCFE_FLUSH__CLEAR_FLUSH_DEEP_MASK 0x00000008L
+-#define DCFE0_DCFE_FLUSH__ALL_MC_REQ_RET_MASK 0x00000010L
+-
+-
+-// addressBlock: dce_dc_dc_perfmon3_dispdec
+-//DC_PERFMON3_PERFCOUNTER_CNTL
+-#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+-#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+-#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+-#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+-#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+-#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
+-#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+-#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+-#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+-#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+-#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+-#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
+-#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+-#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+-#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+-#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+-#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+-#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+-#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
+-#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+-#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+-#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+-#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+-#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+-#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
+-#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+-//DC_PERFMON3_PERFCOUNTER_CNTL2
+-#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+-#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+-#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+-#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+-#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+-#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+-#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+-#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+-//DC_PERFMON3_PERFCOUNTER_STATE
+-#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+-#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+-#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+-#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+-#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+-#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+-#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+-#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+-#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+-#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+-#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+-#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+-#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+-#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+-#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+-#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+-#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+-#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+-#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+-#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+-#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+-#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+-#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+-#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+-#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+-#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+-#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+-#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+-#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+-#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+-#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+-#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+-//DC_PERFMON3_PERFMON_CNTL
+-#define DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+-#define DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+-#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+-#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+-#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+-#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+-#define DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+-#define DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+-#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+-#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+-#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+-#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+-//DC_PERFMON3_PERFMON_CNTL2
+-#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+-#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+-#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+-#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+-#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+-#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+-#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+-#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+-//DC_PERFMON3_PERFMON_CVALUE_INT_MISC
+-#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+-#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+-#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+-#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+-#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+-#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+-#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+-#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+-#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+-#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+-#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+-#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+-#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+-#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+-#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+-#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+-#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+-#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+-#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+-#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+-#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+-#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+-#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+-#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+-#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+-#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+-#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+-#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+-#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+-#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+-#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+-#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+-#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+-#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+-//DC_PERFMON3_PERFMON_CVALUE_LOW
+-#define DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+-#define DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+-//DC_PERFMON3_PERFMON_HI
+-#define DC_PERFMON3_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+-#define DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+-#define DC_PERFMON3_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+-#define DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+-//DC_PERFMON3_PERFMON_LOW
+-#define DC_PERFMON3_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+-#define DC_PERFMON3_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dmif_pg0_dispdec
+-//DMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1
+-#define DMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
+-#define DMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
+-#define DMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0x0000FFFFL
+-#define DMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xFFFF0000L
+-//DMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2
+-#define DMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
+-#define DMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
+-#define DMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0x0000FFFFL
+-#define DMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xFFFF0000L
+-//DMIF_PG0_DPG_WATERMARK_MASK_CONTROL
+-#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
+-#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x4
+-#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
+-#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK__SHIFT 0xc
+-#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0xf
+-#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x12
+-#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL__SHIFT 0x13
+-#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL__SHIFT 0x14
+-#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000007L
+-#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000070L
+-#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x00000700L
+-#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK_MASK 0x00007000L
+-#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00038000L
+-#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x00040000L
+-#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL_MASK 0x00080000L
+-#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL_MASK 0x3FF00000L
+-//DMIF_PG0_DPG_PIPE_URGENCY_CONTROL
+-#define DMIF_PG0_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
+-#define DMIF_PG0_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
+-#define DMIF_PG0_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0x0000FFFFL
+-#define DMIF_PG0_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xFFFF0000L
+-//DMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL
+-#define DMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK__SHIFT 0x0
+-#define DMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK__SHIFT 0x10
+-#define DMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK_MASK 0x0000FFFFL
+-#define DMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK_MASK 0xFFFF0000L
+-//DMIF_PG0_DPG_PIPE_STUTTER_CONTROL
+-#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
+-#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
+-#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
+-#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
+-#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
+-#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
+-#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
+-#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH__SHIFT 0x10
+-#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x14
+-#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x15
+-#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x16
+-#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x17
+-#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0x1a
+-#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0x1b
+-#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L
+-#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L
+-#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x00000020L
+-#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x00000040L
+-#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x00000080L
+-#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x00000400L
+-#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x00000800L
+-#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH_MASK 0x00010000L
+-#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x00100000L
+-#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x00200000L
+-#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x00400000L
+-#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x00800000L
+-#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x04000000L
+-#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x08000000L
+-//DMIF_PG0_DPG_PIPE_STUTTER_CONTROL2
+-#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x0
+-#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK__SHIFT 0x10
+-#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0x0000FFFFL
+-#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK 0xFFFF0000L
+-//DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL
+-#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE__SHIFT 0x0
+-#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE__SHIFT 0x1
+-#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
+-#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
+-#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
+-#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
+-#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK__SHIFT 0xf
+-#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE_MASK 0x00000001L
+-#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE_MASK 0x00000002L
+-#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L
+-#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x00000100L
+-#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON_MASK 0x00000200L
+-#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT_MASK 0x00000400L
+-#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK_MASK 0xFFFF8000L
+-//DMIF_PG0_DPG_REPEATER_PROGRAM
+-#define DMIF_PG0_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
+-#define DMIF_PG0_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
+-#define DMIF_PG0_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x00000007L
+-#define DMIF_PG0_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x00000070L
+-//DMIF_PG0_DPG_CHK_PRE_PROC_CNTL
+-#define DMIF_PG0_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0
+-#define DMIF_PG0_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x00000001L
+-//DMIF_PG0_DPG_DVMM_STATUS
+-#define DMIF_PG0_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED__SHIFT 0x0
+-#define DMIF_PG0_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED__SHIFT 0x1
+-#define DMIF_PG0_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR__SHIFT 0x4
+-#define DMIF_PG0_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR__SHIFT 0x5
+-#define DMIF_PG0_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_MASK 0x00000001L
+-#define DMIF_PG0_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_MASK 0x00000002L
+-#define DMIF_PG0_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR_MASK 0x00000010L
+-#define DMIF_PG0_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR_MASK 0x00000020L
+-
+-
+-// addressBlock: dce_dc_scl0_dispdec
+-//SCL0_SCL_COEF_RAM_SELECT
+-#define SCL0_SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0
+-#define SCL0_SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8
+-#define SCL0_SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10
+-#define SCL0_SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x0000000FL
+-#define SCL0_SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x00000F00L
+-#define SCL0_SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x00070000L
+-//SCL0_SCL_COEF_RAM_TAP_DATA
+-#define SCL0_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0
+-#define SCL0_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
+-#define SCL0_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10
+-#define SCL0_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
+-#define SCL0_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL
+-#define SCL0_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L
+-#define SCL0_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L
+-#define SCL0_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L
+-//SCL0_SCL_MODE
+-#define SCL0_SCL_MODE__SCL_MODE__SHIFT 0x0
+-#define SCL0_SCL_MODE__SCL_PSCL_EN__SHIFT 0x4
+-#define SCL0_SCL_MODE__SCL_MODE_MASK 0x00000003L
+-#define SCL0_SCL_MODE__SCL_PSCL_EN_MASK 0x00000010L
+-//SCL0_SCL_TAP_CONTROL
+-#define SCL0_SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0
+-#define SCL0_SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x8
+-#define SCL0_SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x00000007L
+-#define SCL0_SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0x00000F00L
+-//SCL0_SCL_CONTROL
+-#define SCL0_SCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
+-#define SCL0_SCL_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4
+-#define SCL0_SCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L
+-#define SCL0_SCL_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x00000010L
+-//SCL0_SCL_BYPASS_CONTROL
+-#define SCL0_SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT 0x0
+-#define SCL0_SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x00000003L
+-//SCL0_SCL_MANUAL_REPLICATE_CONTROL
+-#define SCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
+-#define SCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
+-#define SCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL
+-#define SCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L
+-//SCL0_SCL_AUTOMATIC_MODE_CONTROL
+-#define SCL0_SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0
+-#define SCL0_SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10
+-#define SCL0_SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x00000001L
+-#define SCL0_SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x00010000L
+-//SCL0_SCL_HORZ_FILTER_CONTROL
+-#define SCL0_SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT 0x0
+-#define SCL0_SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+-#define SCL0_SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK 0x00000001L
+-#define SCL0_SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
+-//SCL0_SCL_HORZ_FILTER_SCALE_RATIO
+-#define SCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
+-#define SCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL
+-//SCL0_SCL_HORZ_FILTER_INIT
+-#define SCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
+-#define SCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
+-#define SCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL
+-#define SCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L
+-//SCL0_SCL_VERT_FILTER_CONTROL
+-#define SCL0_SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT 0x0
+-#define SCL0_SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+-#define SCL0_SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK 0x00000001L
+-#define SCL0_SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
+-//SCL0_SCL_VERT_FILTER_SCALE_RATIO
+-#define SCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
+-#define SCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL
+-//SCL0_SCL_VERT_FILTER_INIT
+-#define SCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
+-#define SCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
+-#define SCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL
+-#define SCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x07000000L
+-//SCL0_SCL_VERT_FILTER_INIT_BOT
+-#define SCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
+-#define SCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
+-#define SCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL
+-#define SCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x07000000L
+-//SCL0_SCL_ROUND_OFFSET
+-#define SCL0_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0
+-#define SCL0_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10
+-#define SCL0_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0x0000FFFFL
+-#define SCL0_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xFFFF0000L
+-//SCL0_SCL_UPDATE
+-#define SCL0_SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
+-#define SCL0_SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8
+-#define SCL0_SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10
+-#define SCL0_SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18
+-#define SCL0_SCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L
+-#define SCL0_SCL_UPDATE__SCL_UPDATE_TAKEN_MASK 0x00000100L
+-#define SCL0_SCL_UPDATE__SCL_UPDATE_LOCK_MASK 0x00010000L
+-#define SCL0_SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x01000000L
+-//SCL0_SCL_F_SHARP_CONTROL
+-#define SCL0_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT 0x0
+-#define SCL0_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT 0x4
+-#define SCL0_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT 0x8
+-#define SCL0_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT 0xc
+-#define SCL0_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK 0x00000007L
+-#define SCL0_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK 0x00000010L
+-#define SCL0_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK 0x00000700L
+-#define SCL0_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK 0x00001000L
+-//SCL0_SCL_ALU_CONTROL
+-#define SCL0_SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0
+-#define SCL0_SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x00000001L
+-//SCL0_SCL_COEF_RAM_CONFLICT_STATUS
+-#define SCL0_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT 0x0
+-#define SCL0_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT 0x8
+-#define SCL0_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT 0xc
+-#define SCL0_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10
+-#define SCL0_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK 0x00000001L
+-#define SCL0_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK 0x00000100L
+-#define SCL0_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK 0x00001000L
+-#define SCL0_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK 0x00010000L
+-//SCL0_VIEWPORT_START_SECONDARY
+-#define SCL0_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0
+-#define SCL0_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10
+-#define SCL0_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x00003FFFL
+-#define SCL0_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3FFF0000L
+-//SCL0_VIEWPORT_START
+-#define SCL0_VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0
+-#define SCL0_VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10
+-#define SCL0_VIEWPORT_START__VIEWPORT_Y_START_MASK 0x00003FFFL
+-#define SCL0_VIEWPORT_START__VIEWPORT_X_START_MASK 0x3FFF0000L
+-//SCL0_VIEWPORT_SIZE
+-#define SCL0_VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0
+-#define SCL0_VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10
+-#define SCL0_VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x00003FFFL
+-#define SCL0_VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x3FFF0000L
+-//SCL0_EXT_OVERSCAN_LEFT_RIGHT
+-#define SCL0_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
+-#define SCL0_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
+-#define SCL0_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL
+-#define SCL0_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L
+-//SCL0_EXT_OVERSCAN_TOP_BOTTOM
+-#define SCL0_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
+-#define SCL0_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
+-#define SCL0_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL
+-#define SCL0_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L
+-//SCL0_SCL_MODE_CHANGE_DET1
+-#define SCL0_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0
+-#define SCL0_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4
+-#define SCL0_SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7
+-#define SCL0_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x00000001L
+-#define SCL0_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x00000010L
+-#define SCL0_SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0x0FFFFF80L
+-//SCL0_SCL_MODE_CHANGE_DET2
+-#define SCL0_SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0
+-#define SCL0_SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x001FFFFFL
+-//SCL0_SCL_MODE_CHANGE_DET3
+-#define SCL0_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0
+-#define SCL0_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10
+-#define SCL0_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x00003FFFL
+-#define SCL0_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3FFF0000L
+-//SCL0_SCL_MODE_CHANGE_MASK
+-#define SCL0_SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0
+-#define SCL0_SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x00000001L
+-
+-
+-// addressBlock: dce_dc_blnd0_dispdec
+-//BLND0_BLND_CONTROL
+-#define BLND0_BLND_CONTROL__BLND_GLOBAL_GAIN__SHIFT 0x0
+-#define BLND0_BLND_CONTROL__BLND_MODE__SHIFT 0x8
+-#define BLND0_BLND_CONTROL__BLND_STEREO_TYPE__SHIFT 0xa
+-#define BLND0_BLND_CONTROL__BLND_STEREO_POLARITY__SHIFT 0xc
+-#define BLND0_BLND_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT 0xd
+-#define BLND0_BLND_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10
+-#define BLND0_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x12
+-#define BLND0_BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14
+-#define BLND0_BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18
+-#define BLND0_BLND_CONTROL__BLND_GLOBAL_GAIN_MASK 0x000000FFL
+-#define BLND0_BLND_CONTROL__BLND_MODE_MASK 0x00000300L
+-#define BLND0_BLND_CONTROL__BLND_STEREO_TYPE_MASK 0x00000C00L
+-#define BLND0_BLND_CONTROL__BLND_STEREO_POLARITY_MASK 0x00001000L
+-#define BLND0_BLND_CONTROL__BLND_FEEDTHROUGH_EN_MASK 0x00002000L
+-#define BLND0_BLND_CONTROL__BLND_ALPHA_MODE_MASK 0x00030000L
+-#define BLND0_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00040000L
+-#define BLND0_BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x00100000L
+-#define BLND0_BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xFF000000L
+-//BLND0_BLND_SM_CONTROL2
+-#define BLND0_BLND_SM_CONTROL2__SM_MODE__SHIFT 0x0
+-#define BLND0_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4
+-#define BLND0_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5
+-#define BLND0_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
+-#define BLND0_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
+-#define BLND0_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18
+-#define BLND0_BLND_SM_CONTROL2__SM_MODE_MASK 0x00000007L
+-#define BLND0_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x00000010L
+-#define BLND0_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x00000020L
+-#define BLND0_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L
+-#define BLND0_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L
+-#define BLND0_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x01000000L
+-//BLND0_BLND_CONTROL2
+-#define BLND0_BLND_CONTROL2__PTI_ENABLE__SHIFT 0x0
+-#define BLND0_BLND_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT 0x4
+-#define BLND0_BLND_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT 0x6
+-#define BLND0_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT 0x7
+-#define BLND0_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT 0x8
+-#define BLND0_BLND_CONTROL2__PTI_ENABLE_MASK 0x00000001L
+-#define BLND0_BLND_CONTROL2__PTI_NEW_PIXEL_GAP_MASK 0x00000030L
+-#define BLND0_BLND_CONTROL2__BLND_NEW_PIXEL_MODE_MASK 0x00000040L
+-#define BLND0_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK 0x00000080L
+-#define BLND0_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK 0x00000100L
+-//BLND0_BLND_UPDATE
+-#define BLND0_BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0
+-#define BLND0_BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8
+-#define BLND0_BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10
+-#define BLND0_BLND_UPDATE__BLND_UPDATE_PENDING_MASK 0x00000001L
+-#define BLND0_BLND_UPDATE__BLND_UPDATE_TAKEN_MASK 0x00000100L
+-#define BLND0_BLND_UPDATE__BLND_UPDATE_LOCK_MASK 0x00010000L
+-//BLND0_BLND_UNDERFLOW_INTERRUPT
+-#define BLND0_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0
+-#define BLND0_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8
+-#define BLND0_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc
+-#define BLND0_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10
+-#define BLND0_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x00000001L
+-#define BLND0_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x00000100L
+-#define BLND0_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x00001000L
+-#define BLND0_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x00030000L
+-//BLND0_BLND_V_UPDATE_LOCK
+-#define BLND0_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0
+-#define BLND0_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1
+-#define BLND0_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10
+-#define BLND0_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c
+-#define BLND0_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT 0x1d
+-#define BLND0_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT 0x1f
+-#define BLND0_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x00000001L
+-#define BLND0_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x00000002L
+-#define BLND0_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x00010000L
+-#define BLND0_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000L
+-#define BLND0_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK 0x20000000L
+-#define BLND0_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK 0x80000000L
+-//BLND0_BLND_REG_UPDATE_STATUS
+-#define BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT 0x0
+-#define BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT 0x1
+-#define BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2
+-#define BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3
+-#define BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT 0x6
+-#define BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT 0x7
+-#define BLND0_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT 0x8
+-#define BLND0_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT 0x9
+-#define BLND0_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT 0xa
+-#define BLND0_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT 0xb
+-#define BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK 0x00000001L
+-#define BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK 0x00000002L
+-#define BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK 0x00000004L
+-#define BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK 0x00000008L
+-#define BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK 0x00000040L
+-#define BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK 0x00000080L
+-#define BLND0_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK 0x00000100L
+-#define BLND0_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK 0x00000200L
+-#define BLND0_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK 0x00000400L
+-#define BLND0_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK 0x00000800L
+-
+-
+-// addressBlock: dce_dc_crtc0_dispdec
+-//CRTC0_CRTC_H_BLANK_EARLY_NUM
+-#define CRTC0_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0
+-#define CRTC0_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10
+-#define CRTC0_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x000003FFL
+-#define CRTC0_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x00010000L
+-//CRTC0_CRTC_H_TOTAL
+-#define CRTC0_CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0
+-#define CRTC0_CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x00003FFFL
+-//CRTC0_CRTC_H_BLANK_START_END
+-#define CRTC0_CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0
+-#define CRTC0_CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10
+-#define CRTC0_CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x00003FFFL
+-#define CRTC0_CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3FFF0000L
+-//CRTC0_CRTC_H_SYNC_A
+-#define CRTC0_CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0
+-#define CRTC0_CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10
+-#define CRTC0_CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x00003FFFL
+-#define CRTC0_CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3FFF0000L
+-//CRTC0_CRTC_H_SYNC_A_CNTL
+-#define CRTC0_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0
+-#define CRTC0_CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10
+-#define CRTC0_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11
+-#define CRTC0_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x00000001L
+-#define CRTC0_CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x00010000L
+-#define CRTC0_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x00020000L
+-//CRTC0_CRTC_H_SYNC_B
+-#define CRTC0_CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0
+-#define CRTC0_CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10
+-#define CRTC0_CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x00003FFFL
+-#define CRTC0_CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x3FFF0000L
+-//CRTC0_CRTC_H_SYNC_B_CNTL
+-#define CRTC0_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0
+-#define CRTC0_CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10
+-#define CRTC0_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11
+-#define CRTC0_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x00000001L
+-#define CRTC0_CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x00010000L
+-#define CRTC0_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x00020000L
+-//CRTC0_CRTC_VBI_END
+-#define CRTC0_CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x0
+-#define CRTC0_CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x10
+-#define CRTC0_CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x00003FFFL
+-#define CRTC0_CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x3FFF0000L
+-//CRTC0_CRTC_V_TOTAL
+-#define CRTC0_CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0
+-#define CRTC0_CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x00003FFFL
+-//CRTC0_CRTC_V_TOTAL_MIN
+-#define CRTC0_CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0
+-#define CRTC0_CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x00003FFFL
+-//CRTC0_CRTC_V_TOTAL_MAX
+-#define CRTC0_CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0
+-#define CRTC0_CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10
+-#define CRTC0_CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x00003FFFL
+-#define CRTC0_CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x00010000L
+-//CRTC0_CRTC_V_TOTAL_CONTROL
+-#define CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0
+-#define CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4
+-#define CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8
+-#define CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc
+-#define CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf
+-#define CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10
+-#define CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x00000001L
+-#define CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x00000010L
+-#define CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x00000100L
+-#define CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x00001000L
+-#define CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00008000L
+-#define CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L
+-//CRTC0_CRTC_V_TOTAL_INT_STATUS
+-#define CRTC0_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0
+-#define CRTC0_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4
+-#define CRTC0_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8
+-#define CRTC0_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc
+-#define CRTC0_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L
+-#define CRTC0_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L
+-#define CRTC0_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L
+-#define CRTC0_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L
+-//CRTC0_CRTC_VSYNC_NOM_INT_STATUS
+-#define CRTC0_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0
+-#define CRTC0_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4
+-#define CRTC0_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x00000001L
+-#define CRTC0_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L
+-//CRTC0_CRTC_V_BLANK_START_END
+-#define CRTC0_CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0
+-#define CRTC0_CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10
+-#define CRTC0_CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x00003FFFL
+-#define CRTC0_CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3FFF0000L
+-//CRTC0_CRTC_V_SYNC_A
+-#define CRTC0_CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0
+-#define CRTC0_CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10
+-#define CRTC0_CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x00003FFFL
+-#define CRTC0_CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3FFF0000L
+-//CRTC0_CRTC_V_SYNC_A_CNTL
+-#define CRTC0_CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0
+-#define CRTC0_CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x00000001L
+-//CRTC0_CRTC_V_SYNC_B
+-#define CRTC0_CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0
+-#define CRTC0_CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10
+-#define CRTC0_CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x00003FFFL
+-#define CRTC0_CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x3FFF0000L
+-//CRTC0_CRTC_V_SYNC_B_CNTL
+-#define CRTC0_CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0
+-#define CRTC0_CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x00000001L
+-//CRTC0_CRTC_DTMTEST_CNTL
+-#define CRTC0_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0
+-#define CRTC0_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1
+-#define CRTC0_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x00000001L
+-#define CRTC0_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x0000001EL
+-//CRTC0_CRTC_DTMTEST_STATUS_POSITION
+-#define CRTC0_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0
+-#define CRTC0_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10
+-#define CRTC0_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x00003FFFL
+-#define CRTC0_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x3FFF0000L
+-//CRTC0_CRTC_TRIGA_CNTL
+-#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0
+-#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5
+-#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8
+-#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9
+-#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa
+-#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb
+-#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
+-#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
+-#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14
+-#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18
+-#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f
+-#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x0000001FL
+-#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0x000000E0L
+-#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000100L
+-#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x00000200L
+-#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x00000400L
+-#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x00000800L
+-#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
+-#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
+-#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L
+-#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1F000000L
+-#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000L
+-//CRTC0_CRTC_TRIGA_MANUAL_TRIG
+-#define CRTC0_CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0
+-#define CRTC0_CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x00000001L
+-//CRTC0_CRTC_TRIGB_CNTL
+-#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0
+-#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5
+-#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8
+-#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9
+-#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa
+-#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb
+-#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
+-#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
+-#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14
+-#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18
+-#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f
+-#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x0000001FL
+-#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0x000000E0L
+-#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000100L
+-#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x00000200L
+-#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x00000400L
+-#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x00000800L
+-#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
+-#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
+-#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L
+-#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1F000000L
+-#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000L
+-//CRTC0_CRTC_TRIGB_MANUAL_TRIG
+-#define CRTC0_CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0
+-#define CRTC0_CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x00000001L
+-//CRTC0_CRTC_FORCE_COUNT_NOW_CNTL
+-#define CRTC0_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0
+-#define CRTC0_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4
+-#define CRTC0_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8
+-#define CRTC0_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10
+-#define CRTC0_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18
+-#define CRTC0_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x00000003L
+-#define CRTC0_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L
+-#define CRTC0_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L
+-#define CRTC0_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L
+-#define CRTC0_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L
+-//CRTC0_CRTC_FLOW_CONTROL
+-#define CRTC0_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0
+-#define CRTC0_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8
+-#define CRTC0_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10
+-#define CRTC0_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18
+-#define CRTC0_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL
+-#define CRTC0_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x00000100L
+-#define CRTC0_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L
+-#define CRTC0_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L
+-//CRTC0_CRTC_STEREO_FORCE_NEXT_EYE
+-#define CRTC0_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0
+-#define CRTC0_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER__SHIFT 0x8
+-#define CRTC0_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER__SHIFT 0x10
+-#define CRTC0_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L
+-#define CRTC0_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L
+-#define CRTC0_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L
+-//CRTC0_CRTC_AVSYNC_COUNTER
+-#define CRTC0_CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER__SHIFT 0x0
+-#define CRTC0_CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER_MASK 0xFFFFFFFFL
+-//CRTC0_CRTC_CONTROL
+-#define CRTC0_CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x0
+-#define CRTC0_CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4
+-#define CRTC0_CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8
+-#define CRTC0_CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc
+-#define CRTC0_CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd
+-#define CRTC0_CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe
+-#define CRTC0_CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10
+-#define CRTC0_CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14
+-#define CRTC0_CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d
+-#define CRTC0_CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e
+-#define CRTC0_CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f
+-#define CRTC0_CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x00000001L
+-#define CRTC0_CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x00000010L
+-#define CRTC0_CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x00000300L
+-#define CRTC0_CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x00001000L
+-#define CRTC0_CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x00002000L
+-#define CRTC0_CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x00004000L
+-#define CRTC0_CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x00010000L
+-#define CRTC0_CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x00700000L
+-#define CRTC0_CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000L
+-#define CRTC0_CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L
+-#define CRTC0_CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L
+-//CRTC0_CRTC_BLANK_CONTROL
+-#define CRTC0_CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0
+-#define CRTC0_CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8
+-#define CRTC0_CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10
+-#define CRTC0_CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x00000001L
+-#define CRTC0_CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x00000100L
+-#define CRTC0_CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x00010000L
+-//CRTC0_CRTC_INTERLACE_CONTROL
+-#define CRTC0_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0
+-#define CRTC0_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10
+-#define CRTC0_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x00000001L
+-#define CRTC0_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L
+-//CRTC0_CRTC_INTERLACE_STATUS
+-#define CRTC0_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0
+-#define CRTC0_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1
+-#define CRTC0_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x00000001L
+-#define CRTC0_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x00000002L
+-//CRTC0_CRTC_FIELD_INDICATION_CONTROL
+-#define CRTC0_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0
+-#define CRTC0_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1
+-#define CRTC0_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x00000001L
+-#define CRTC0_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x00000002L
+-//CRTC0_CRTC_PIXEL_DATA_READBACK0
+-#define CRTC0_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0
+-#define CRTC0_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10
+-#define CRTC0_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0x00000FFFL
+-#define CRTC0_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0x0FFF0000L
+-//CRTC0_CRTC_PIXEL_DATA_READBACK1
+-#define CRTC0_CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0
+-#define CRTC0_CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0x00000FFFL
+-//CRTC0_CRTC_STATUS
+-#define CRTC0_CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x0
+-#define CRTC0_CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1
+-#define CRTC0_CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x2
+-#define CRTC0_CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x3
+-#define CRTC0_CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x4
+-#define CRTC0_CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5
+-#define CRTC0_CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x10
+-#define CRTC0_CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11
+-#define CRTC0_CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x12
+-#define CRTC0_CRTC_STATUS__CRTC_V_BLANK_MASK 0x00000001L
+-#define CRTC0_CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x00000002L
+-#define CRTC0_CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x00000004L
+-#define CRTC0_CRTC_STATUS__CRTC_V_UPDATE_MASK 0x00000008L
+-#define CRTC0_CRTC_STATUS__CRTC_V_START_LINE_MASK 0x00000010L
+-#define CRTC0_CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x00000020L
+-#define CRTC0_CRTC_STATUS__CRTC_H_BLANK_MASK 0x00010000L
+-#define CRTC0_CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x00020000L
+-#define CRTC0_CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x00040000L
+-//CRTC0_CRTC_STATUS_POSITION
+-#define CRTC0_CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0
+-#define CRTC0_CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10
+-#define CRTC0_CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x00003FFFL
+-#define CRTC0_CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x3FFF0000L
+-//CRTC0_CRTC_NOM_VERT_POSITION
+-#define CRTC0_CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0
+-#define CRTC0_CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x00003FFFL
+-//CRTC0_CRTC_STATUS_FRAME_COUNT
+-#define CRTC0_CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0
+-#define CRTC0_CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0x00FFFFFFL
+-//CRTC0_CRTC_STATUS_VF_COUNT
+-#define CRTC0_CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0
+-#define CRTC0_CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x3FFFFFFFL
+-//CRTC0_CRTC_STATUS_HV_COUNT
+-#define CRTC0_CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0
+-#define CRTC0_CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x3FFFFFFFL
+-//CRTC0_CRTC_COUNT_CONTROL
+-#define CRTC0_CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0
+-#define CRTC0_CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1
+-#define CRTC0_CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x00000001L
+-#define CRTC0_CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x0000001EL
+-//CRTC0_CRTC_COUNT_RESET
+-#define CRTC0_CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0
+-#define CRTC0_CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x00000001L
+-//CRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE
+-#define CRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0
+-#define CRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L
+-//CRTC0_CRTC_VERT_SYNC_CONTROL
+-#define CRTC0_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0
+-#define CRTC0_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8
+-#define CRTC0_CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10
+-#define CRTC0_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L
+-#define CRTC0_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L
+-#define CRTC0_CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L
+-//CRTC0_CRTC_STEREO_STATUS
+-#define CRTC0_CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0
+-#define CRTC0_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8
+-#define CRTC0_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10
+-#define CRTC0_CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG__SHIFT 0x14
+-#define CRTC0_CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18
+-#define CRTC0_CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x00000001L
+-#define CRTC0_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x00000100L
+-#define CRTC0_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x00010000L
+-#define CRTC0_CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG_MASK 0x00100000L
+-#define CRTC0_CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L
+-//CRTC0_CRTC_STEREO_CONTROL
+-#define CRTC0_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0
+-#define CRTC0_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf
+-#define CRTC0_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10
+-#define CRTC0_CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11
+-#define CRTC0_CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12
+-#define CRTC0_CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM__SHIFT 0x13
+-#define CRTC0_CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14
+-#define CRTC0_CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18
+-#define CRTC0_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00003FFFL
+-#define CRTC0_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L
+-#define CRTC0_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x00010000L
+-#define CRTC0_CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L
+-#define CRTC0_CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L
+-#define CRTC0_CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM_MASK 0x00080000L
+-#define CRTC0_CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L
+-#define CRTC0_CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x01000000L
+-//CRTC0_CRTC_SNAPSHOT_STATUS
+-#define CRTC0_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0
+-#define CRTC0_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1
+-#define CRTC0_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2
+-#define CRTC0_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x00000001L
+-#define CRTC0_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x00000002L
+-#define CRTC0_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L
+-//CRTC0_CRTC_SNAPSHOT_CONTROL
+-#define CRTC0_CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0
+-#define CRTC0_CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L
+-//CRTC0_CRTC_SNAPSHOT_POSITION
+-#define CRTC0_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0
+-#define CRTC0_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10
+-#define CRTC0_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x00003FFFL
+-#define CRTC0_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x3FFF0000L
+-//CRTC0_CRTC_SNAPSHOT_FRAME
+-#define CRTC0_CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0
+-#define CRTC0_CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL
+-//CRTC0_CRTC_START_LINE_CONTROL
+-#define CRTC0_CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0
+-#define CRTC0_CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x1
+-#define CRTC0_CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x2
+-#define CRTC0_CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x8
+-#define CRTC0_CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc
+-#define CRTC0_CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x00000001L
+-#define CRTC0_CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x00000002L
+-#define CRTC0_CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x00000004L
+-#define CRTC0_CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x00000100L
+-#define CRTC0_CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0x000FF000L
+-//CRTC0_CRTC_INTERRUPT_CONTROL
+-#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0
+-#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1
+-#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4
+-#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5
+-#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8
+-#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9
+-#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10
+-#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11
+-#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18
+-#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19
+-#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a
+-#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b
+-#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c
+-#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d
+-#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e
+-#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f
+-#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x00000001L
+-#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x00000002L
+-#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x00000010L
+-#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x00000020L
+-#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L
+-#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L
+-#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L
+-#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L
+-#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x01000000L
+-#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x02000000L
+-#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x04000000L
+-#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x08000000L
+-#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000L
+-#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000L
+-#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L
+-#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L
+-//CRTC0_CRTC_UPDATE_LOCK
+-#define CRTC0_CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0
+-#define CRTC0_CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x00000001L
+-//CRTC0_CRTC_DOUBLE_BUFFER_CONTROL
+-#define CRTC0_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0
+-#define CRTC0_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8
+-#define CRTC0_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10
+-#define CRTC0_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18
+-#define CRTC0_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x19
+-#define CRTC0_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x00000001L
+-#define CRTC0_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x00000100L
+-#define CRTC0_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L
+-#define CRTC0_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x01000000L
+-#define CRTC0_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x02000000L
+-//CRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE
+-#define CRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0
+-#define CRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x00000001L
+-//CRTC0_CRTC_TEST_PATTERN_CONTROL
+-#define CRTC0_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0
+-#define CRTC0_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8
+-#define CRTC0_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10
+-#define CRTC0_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18
+-#define CRTC0_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x00000001L
+-#define CRTC0_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x00000700L
+-#define CRTC0_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L
+-#define CRTC0_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xFF000000L
+-//CRTC0_CRTC_TEST_PATTERN_PARAMETERS
+-#define CRTC0_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0
+-#define CRTC0_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4
+-#define CRTC0_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8
+-#define CRTC0_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc
+-#define CRTC0_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10
+-#define CRTC0_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0x0000000FL
+-#define CRTC0_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0x000000F0L
+-#define CRTC0_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0x00000F00L
+-#define CRTC0_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0x0000F000L
+-#define CRTC0_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xFFFF0000L
+-//CRTC0_CRTC_TEST_PATTERN_COLOR
+-#define CRTC0_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0
+-#define CRTC0_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10
+-#define CRTC0_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0x0000FFFFL
+-#define CRTC0_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x003F0000L
+-//CRTC0_CRTC_MASTER_UPDATE_LOCK
+-#define CRTC0_CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0
+-#define CRTC0_CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8
+-#define CRTC0_CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK__SHIFT 0x10
+-#define CRTC0_CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x00000001L
+-#define CRTC0_CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x00000100L
+-#define CRTC0_CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK_MASK 0x00010000L
+-//CRTC0_CRTC_MASTER_UPDATE_MODE
+-#define CRTC0_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0
+-#define CRTC0_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10
+-#define CRTC0_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x00000007L
+-#define CRTC0_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00030000L
+-//CRTC0_CRTC_MVP_INBAND_CNTL_INSERT
+-#define CRTC0_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0
+-#define CRTC0_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8
+-#define CRTC0_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x00000003L
+-#define CRTC0_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xFFFFFF00L
+-//CRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER
+-#define CRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0
+-#define CRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0x000000FFL
+-//CRTC0_CRTC_MVP_STATUS
+-#define CRTC0_CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0
+-#define CRTC0_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4
+-#define CRTC0_CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10
+-#define CRTC0_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14
+-#define CRTC0_CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x00000001L
+-#define CRTC0_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x00000010L
+-#define CRTC0_CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x00010000L
+-#define CRTC0_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x00100000L
+-//CRTC0_CRTC_MASTER_EN
+-#define CRTC0_CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0
+-#define CRTC0_CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x00000001L
+-//CRTC0_CRTC_ALLOW_STOP_OFF_V_CNT
+-#define CRTC0_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0
+-#define CRTC0_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10
+-#define CRTC0_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0x000000FFL
+-#define CRTC0_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x00010000L
+-//CRTC0_CRTC_V_UPDATE_INT_STATUS
+-#define CRTC0_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0
+-#define CRTC0_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8
+-#define CRTC0_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x00000001L
+-#define CRTC0_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x00000100L
+-//CRTC0_CRTC_OVERSCAN_COLOR
+-#define CRTC0_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0
+-#define CRTC0_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa
+-#define CRTC0_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14
+-#define CRTC0_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x000003FFL
+-#define CRTC0_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0x000FFC00L
+-#define CRTC0_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3FF00000L
+-//CRTC0_CRTC_OVERSCAN_COLOR_EXT
+-#define CRTC0_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0
+-#define CRTC0_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8
+-#define CRTC0_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10
+-#define CRTC0_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x00000003L
+-#define CRTC0_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x00000300L
+-#define CRTC0_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x00030000L
+-//CRTC0_CRTC_BLANK_DATA_COLOR
+-#define CRTC0_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0
+-#define CRTC0_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa
+-#define CRTC0_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14
+-#define CRTC0_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL
+-#define CRTC0_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L
+-#define CRTC0_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L
+-//CRTC0_CRTC_BLANK_DATA_COLOR_EXT
+-#define CRTC0_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0
+-#define CRTC0_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8
+-#define CRTC0_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10
+-#define CRTC0_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x00000003L
+-#define CRTC0_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00000300L
+-#define CRTC0_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x00030000L
+-//CRTC0_CRTC_BLACK_COLOR
+-#define CRTC0_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0
+-#define CRTC0_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa
+-#define CRTC0_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14
+-#define CRTC0_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x000003FFL
+-#define CRTC0_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0x000FFC00L
+-#define CRTC0_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3FF00000L
+-//CRTC0_CRTC_BLACK_COLOR_EXT
+-#define CRTC0_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0
+-#define CRTC0_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8
+-#define CRTC0_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10
+-#define CRTC0_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x00000003L
+-#define CRTC0_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x00000300L
+-#define CRTC0_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x00030000L
+-//CRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION
+-#define CRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0
+-#define CRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10
+-#define CRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00003FFFL
+-#define CRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x3FFF0000L
+-//CRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL
+-#define CRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4
+-#define CRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8
+-#define CRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc
+-#define CRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10
+-#define CRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14
+-#define CRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18
+-#define CRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L
+-#define CRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L
+-#define CRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L
+-#define CRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L
+-#define CRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L
+-#define CRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L
+-//CRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION
+-#define CRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0
+-#define CRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00003FFFL
+-//CRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL
+-#define CRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8
+-#define CRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc
+-#define CRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10
+-#define CRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14
+-#define CRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18
+-#define CRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L
+-#define CRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L
+-#define CRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L
+-#define CRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L
+-#define CRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L
+-//CRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION
+-#define CRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0
+-#define CRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00003FFFL
+-//CRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL
+-#define CRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8
+-#define CRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc
+-#define CRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10
+-#define CRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14
+-#define CRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18
+-#define CRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L
+-#define CRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L
+-#define CRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L
+-#define CRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L
+-#define CRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L
+-//CRTC0_CRTC_CRC_CNTL
+-#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0
+-#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4
+-#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8
+-#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc
+-#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
+-#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14
+-#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18
+-#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC_EN_MASK 0x00000001L
+-#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x00000010L
+-#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x00000300L
+-#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x00003000L
+-#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
+-#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x00700000L
+-#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x07000000L
+-//CRTC0_CRTC_CRC0_WINDOWA_X_CONTROL
+-#define CRTC0_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0
+-#define CRTC0_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10
+-#define CRTC0_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x00003FFFL
+-#define CRTC0_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3FFF0000L
+-//CRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL
+-#define CRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0
+-#define CRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10
+-#define CRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x00003FFFL
+-#define CRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3FFF0000L
+-//CRTC0_CRTC_CRC0_WINDOWB_X_CONTROL
+-#define CRTC0_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0
+-#define CRTC0_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10
+-#define CRTC0_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x00003FFFL
+-#define CRTC0_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3FFF0000L
+-//CRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL
+-#define CRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0
+-#define CRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10
+-#define CRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x00003FFFL
+-#define CRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3FFF0000L
+-//CRTC0_CRTC_CRC0_DATA_RG
+-#define CRTC0_CRTC_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0
+-#define CRTC0_CRTC_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10
+-#define CRTC0_CRTC_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL
+-#define CRTC0_CRTC_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L
+-//CRTC0_CRTC_CRC0_DATA_B
+-#define CRTC0_CRTC_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0
+-#define CRTC0_CRTC_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL
+-//CRTC0_CRTC_CRC1_WINDOWA_X_CONTROL
+-#define CRTC0_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0
+-#define CRTC0_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10
+-#define CRTC0_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x00003FFFL
+-#define CRTC0_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3FFF0000L
+-//CRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL
+-#define CRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0
+-#define CRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10
+-#define CRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x00003FFFL
+-#define CRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3FFF0000L
+-//CRTC0_CRTC_CRC1_WINDOWB_X_CONTROL
+-#define CRTC0_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0
+-#define CRTC0_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10
+-#define CRTC0_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x00003FFFL
+-#define CRTC0_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3FFF0000L
+-//CRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL
+-#define CRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0
+-#define CRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10
+-#define CRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x00003FFFL
+-#define CRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3FFF0000L
+-//CRTC0_CRTC_CRC1_DATA_RG
+-#define CRTC0_CRTC_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0
+-#define CRTC0_CRTC_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10
+-#define CRTC0_CRTC_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL
+-#define CRTC0_CRTC_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L
+-//CRTC0_CRTC_CRC1_DATA_B
+-#define CRTC0_CRTC_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0
+-#define CRTC0_CRTC_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL
+-//CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE__SHIFT 0x0
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__SHIFT 0x3
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__SHIFT 0x4
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__SHIFT 0x5
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__SHIFT 0x8
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__SHIFT 0x9
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__SHIFT 0xc
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__SHIFT 0xd
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__SHIFT 0xe
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE__SHIFT 0x18
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE__SHIFT 0x1c
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE_MASK 0x00000003L
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_MASK 0x00000008L
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_MASK 0x00000010L
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_MASK 0x00000060L
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_MASK 0x00000100L
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_MASK 0x00000200L
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_MASK 0x00001000L
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_MASK 0x00002000L
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_MASK 0x00004000L
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE_MASK 0x07000000L
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE_MASK 0x70000000L
+-//CRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X__SHIFT 0x0
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y__SHIFT 0x10
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X_MASK 0x00003FFFL
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y_MASK 0x3FFF0000L
+-//CRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X__SHIFT 0x0
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y__SHIFT 0x10
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X_MASK 0x00003FFFL
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y_MASK 0x3FFF0000L
+-//CRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__SHIFT 0x0
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS__SHIFT 0x4
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS__SHIFT 0x8
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__SHIFT 0x10
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__SHIFT 0x14
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__SHIFT 0x1d
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_MASK 0x00000001L
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS_MASK 0x00000010L
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS_MASK 0x00000100L
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_MASK 0x00010000L
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_MASK 0x00100000L
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_MASK 0xE0000000L
+-//CRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE__SHIFT 0x0
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS__SHIFT 0x4
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS__SHIFT 0x8
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR__SHIFT 0x10
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE__SHIFT 0x14
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE_MASK 0x00000001L
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS_MASK 0x00000010L
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS_MASK 0x00000100L
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR_MASK 0x00010000L
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE_MASK 0x00100000L
+-//CRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__SHIFT 0x0
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS__SHIFT 0x4
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS__SHIFT 0x8
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__SHIFT 0x10
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__SHIFT 0x14
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_MASK 0x00000001L
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS_MASK 0x00000010L
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS_MASK 0x00000100L
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_MASK 0x00010000L
+-#define CRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_MASK 0x00100000L
+-//CRTC0_CRTC_STATIC_SCREEN_CONTROL
+-#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0
+-#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10
+-#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18
+-#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19
+-#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a
+-#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b
+-#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c
+-#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e
+-#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f
+-#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL
+-#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L
+-#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x01000000L
+-#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x02000000L
+-#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x04000000L
+-#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x08000000L
+-#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000L
+-#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L
+-#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L
+-//CRTC0_CRTC_3D_STRUCTURE_CONTROL
+-#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0
+-#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4
+-#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8
+-#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc
+-#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10
+-#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11
+-#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12
+-#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x00000001L
+-#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x00000010L
+-#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L
+-#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L
+-#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L
+-#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L
+-#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L
+-//CRTC0_CRTC_GSL_VSYNC_GAP
+-#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0
+-#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8
+-#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10
+-#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11
+-#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13
+-#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14
+-#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17
+-#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18
+-#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL
+-#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L
+-#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L
+-#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x00060000L
+-#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L
+-#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L
+-#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L
+-#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xFF000000L
+-//CRTC0_CRTC_GSL_WINDOW
+-#define CRTC0_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0
+-#define CRTC0_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10
+-#define CRTC0_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x00003FFFL
+-#define CRTC0_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x3FFF0000L
+-//CRTC0_CRTC_GSL_CONTROL
+-#define CRTC0_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0
+-#define CRTC0_CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10
+-#define CRTC0_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c
+-#define CRTC0_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x00003FFFL
+-#define CRTC0_CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x001F0000L
+-#define CRTC0_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L
+-//CRTC0_CRTC_RANGE_TIMING_INT_STATUS
+-#define CRTC0_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0
+-#define CRTC0_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4
+-#define CRTC0_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8
+-#define CRTC0_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc
+-#define CRTC0_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10
+-#define CRTC0_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L
+-#define CRTC0_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L
+-#define CRTC0_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L
+-#define CRTC0_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L
+-#define CRTC0_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L
+-//CRTC0_CRTC_DRR_CONTROL
+-#define CRTC0_CRTC_DRR_CONTROL__CRTC_XDMA_PREFETCH_DELAY__SHIFT 0x0
+-#define CRTC0_CRTC_DRR_CONTROL__CRTC_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0xe
+-#define CRTC0_CRTC_DRR_CONTROL__CRTC_SET_V_TOTAL_MIN_AUTO_DIS__SHIFT 0x1c
+-#define CRTC0_CRTC_DRR_CONTROL__CRTC_DRR_MODE_DBUF_UPDATE_MODE__SHIFT 0x1d
+-#define CRTC0_CRTC_DRR_CONTROL__CRTC_XDMA_PREFETCH_DELAY_MASK 0x00003FFFL
+-#define CRTC0_CRTC_DRR_CONTROL__CRTC_V_TOTAL_LAST_USED_BY_DRR_MASK 0x0FFFC000L
+-#define CRTC0_CRTC_DRR_CONTROL__CRTC_SET_V_TOTAL_MIN_AUTO_DIS_MASK 0x10000000L
+-#define CRTC0_CRTC_DRR_CONTROL__CRTC_DRR_MODE_DBUF_UPDATE_MODE_MASK 0x60000000L
+-
+-
+-// addressBlock: dce_dc_fmt0_dispdec
+-//FMT0_FMT_CLAMP_COMPONENT_R
+-#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0
+-#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10
+-#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL
+-#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L
+-//FMT0_FMT_CLAMP_COMPONENT_G
+-#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0
+-#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10
+-#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL
+-#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L
+-//FMT0_FMT_CLAMP_COMPONENT_B
+-#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0
+-#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10
+-#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL
+-#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L
+-//FMT0_FMT_DYNAMIC_EXP_CNTL
+-#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0
+-#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4
+-#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L
+-#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L
+-//FMT0_FMT_CONTROL
+-#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0
+-#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT 0x4
+-#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8
+-#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc
+-#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10
+-#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12
+-#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14
+-#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15
+-#define FMT0_FMT_CONTROL__FMT_SRC_SELECT__SHIFT 0x18
+-#define FMT0_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED__SHIFT 0x1e
+-#define FMT0_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_CLEAR__SHIFT 0x1f
+-#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L
+-#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK 0x00000010L
+-#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L
+-#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L
+-#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L
+-#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L
+-#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L
+-#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L
+-#define FMT0_FMT_CONTROL__FMT_SRC_SELECT_MASK 0x07000000L
+-#define FMT0_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_MASK 0x40000000L
+-#define FMT0_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_CLEAR_MASK 0x80000000L
+-//FMT0_FMT_BIT_DEPTH_CONTROL
+-#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0
+-#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1
+-#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4
+-#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8
+-#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9
+-#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb
+-#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd
+-#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe
+-#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf
+-#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10
+-#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11
+-#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15
+-#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18
+-#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19
+-#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a
+-#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c
+-#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e
+-#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L
+-#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L
+-#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L
+-#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L
+-#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L
+-#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L
+-#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L
+-#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L
+-#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L
+-#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L
+-#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L
+-#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L
+-#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L
+-#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L
+-#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L
+-#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L
+-#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L
+-//FMT0_FMT_DITHER_RAND_R_SEED
+-#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0
+-#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10
+-#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL
+-#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L
+-//FMT0_FMT_DITHER_RAND_G_SEED
+-#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0
+-#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10
+-#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL
+-#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L
+-//FMT0_FMT_DITHER_RAND_B_SEED
+-#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0
+-#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10
+-#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL
+-#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L
+-//FMT0_FMT_CLAMP_CNTL
+-#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0
+-#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10
+-#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L
+-#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L
+-//FMT0_FMT_CRC_CNTL
+-#define FMT0_FMT_CRC_CNTL__FMT_CRC_EN__SHIFT 0x0
+-#define FMT0_FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN__SHIFT 0x1
+-#define FMT0_FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT 0x4
+-#define FMT0_FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING__SHIFT 0x5
+-#define FMT0_FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN__SHIFT 0x6
+-#define FMT0_FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB__SHIFT 0x8
+-#define FMT0_FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE__SHIFT 0x9
+-#define FMT0_FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT 0xc
+-#define FMT0_FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
+-#define FMT0_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT 0x14
+-#define FMT0_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT 0x18
+-#define FMT0_FMT_CRC_CNTL__FMT_CRC_EN_MASK 0x00000001L
+-#define FMT0_FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN_MASK 0x00000002L
+-#define FMT0_FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK 0x00000010L
+-#define FMT0_FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING_MASK 0x00000020L
+-#define FMT0_FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN_MASK 0x00000040L
+-#define FMT0_FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB_MASK 0x00000100L
+-#define FMT0_FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE_MASK 0x00000200L
+-#define FMT0_FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK 0x00003000L
+-#define FMT0_FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
+-#define FMT0_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK 0x00100000L
+-#define FMT0_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK 0x01000000L
+-//FMT0_FMT_CRC_SIG_RED_GREEN_MASK
+-#define FMT0_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT 0x0
+-#define FMT0_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT 0x10
+-#define FMT0_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK 0x0000FFFFL
+-#define FMT0_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L
+-//FMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK
+-#define FMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT 0x0
+-#define FMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT 0x10
+-#define FMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL
+-#define FMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L
+-//FMT0_FMT_CRC_SIG_RED_GREEN
+-#define FMT0_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT 0x0
+-#define FMT0_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT 0x10
+-#define FMT0_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK 0x0000FFFFL
+-#define FMT0_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK 0xFFFF0000L
+-//FMT0_FMT_CRC_SIG_BLUE_CONTROL
+-#define FMT0_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT 0x0
+-#define FMT0_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT 0x10
+-#define FMT0_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK 0x0000FFFFL
+-#define FMT0_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK 0xFFFF0000L
+-//FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+-#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0
+-#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL
+-//FMT0_FMT_420_HBLANK_EARLY_START
+-#define FMT0_FMT_420_HBLANK_EARLY_START__FMT_420_HBLANK_EARLY_START__SHIFT 0x0
+-#define FMT0_FMT_420_HBLANK_EARLY_START__FMT_420_HBLANK_EARLY_START_MASK 0x00000FFFL
+-
+-
+-// addressBlock: dce_dc_dcp1_dispdec
+-//DCP1_GRPH_ENABLE
+-#define DCP1_GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0
+-#define DCP1_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL__SHIFT 0x1
+-#define DCP1_GRPH_ENABLE__GRPH_ENABLE_MASK 0x00000001L
+-#define DCP1_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL_MASK 0x00000002L
+-//DCP1_GRPH_CONTROL
+-#define DCP1_GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0
+-#define DCP1_GRPH_CONTROL__GRPH_SE_ENABLE__SHIFT 0x2
+-#define DCP1_GRPH_CONTROL__GRPH_Z__SHIFT 0x4
+-#define DCP1_GRPH_CONTROL__GRPH_DIM_TYPE__SHIFT 0x6
+-#define DCP1_GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8
+-#define DCP1_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0xc
+-#define DCP1_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10
+-#define DCP1_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11
+-#define DCP1_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES__SHIFT 0x12
+-#define DCP1_GRPH_CONTROL__GRPH_SW_MODE__SHIFT 0x14
+-#define DCP1_GRPH_CONTROL__GRPH_NUM_PIPES__SHIFT 0x1c
+-#define DCP1_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f
+-#define DCP1_GRPH_CONTROL__GRPH_DEPTH_MASK 0x00000003L
+-#define DCP1_GRPH_CONTROL__GRPH_SE_ENABLE_MASK 0x00000004L
+-#define DCP1_GRPH_CONTROL__GRPH_Z_MASK 0x00000030L
+-#define DCP1_GRPH_CONTROL__GRPH_DIM_TYPE_MASK 0x000000C0L
+-#define DCP1_GRPH_CONTROL__GRPH_FORMAT_MASK 0x00000700L
+-#define DCP1_GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0x00007000L
+-#define DCP1_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x00010000L
+-#define DCP1_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x00020000L
+-#define DCP1_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES_MASK 0x000C0000L
+-#define DCP1_GRPH_CONTROL__GRPH_SW_MODE_MASK 0x01F00000L
+-#define DCP1_GRPH_CONTROL__GRPH_NUM_PIPES_MASK 0x70000000L
+-#define DCP1_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000L
+-//DCP1_GRPH_LUT_10BIT_BYPASS
+-#define DCP1_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT 0x8
+-#define DCP1_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x10
+-#define DCP1_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK 0x00000100L
+-#define DCP1_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x00010000L
+-//DCP1_GRPH_SWAP_CNTL
+-#define DCP1_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0
+-#define DCP1_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4
+-#define DCP1_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6
+-#define DCP1_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8
+-#define DCP1_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT 0xa
+-#define DCP1_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x00000003L
+-#define DCP1_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x00000030L
+-#define DCP1_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0x000000C0L
+-#define DCP1_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x00000300L
+-#define DCP1_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK 0x00000C00L
+-//DCP1_GRPH_PRIMARY_SURFACE_ADDRESS
+-#define DCP1_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT 0x0
+-#define DCP1_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT 0x8
+-#define DCP1_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK 0x00000001L
+-#define DCP1_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+-//DCP1_GRPH_SECONDARY_SURFACE_ADDRESS
+-#define DCP1_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT 0x0
+-#define DCP1_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8
+-#define DCP1_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK 0x00000001L
+-#define DCP1_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+-//DCP1_GRPH_PITCH
+-#define DCP1_GRPH_PITCH__GRPH_PITCH__SHIFT 0x0
+-#define DCP1_GRPH_PITCH__GRPH_PITCH_MASK 0x00007FFFL
+-//DCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+-#define DCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+-#define DCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+-//DCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+-#define DCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+-#define DCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+-//DCP1_GRPH_SURFACE_OFFSET_X
+-#define DCP1_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT 0x0
+-#define DCP1_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK 0x00003FFFL
+-//DCP1_GRPH_SURFACE_OFFSET_Y
+-#define DCP1_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT 0x0
+-#define DCP1_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK 0x00003FFFL
+-//DCP1_GRPH_X_START
+-#define DCP1_GRPH_X_START__GRPH_X_START__SHIFT 0x0
+-#define DCP1_GRPH_X_START__GRPH_X_START_MASK 0x00003FFFL
+-//DCP1_GRPH_Y_START
+-#define DCP1_GRPH_Y_START__GRPH_Y_START__SHIFT 0x0
+-#define DCP1_GRPH_Y_START__GRPH_Y_START_MASK 0x00003FFFL
+-//DCP1_GRPH_X_END
+-#define DCP1_GRPH_X_END__GRPH_X_END__SHIFT 0x0
+-#define DCP1_GRPH_X_END__GRPH_X_END_MASK 0x00007FFFL
+-//DCP1_GRPH_Y_END
+-#define DCP1_GRPH_Y_END__GRPH_Y_END__SHIFT 0x0
+-#define DCP1_GRPH_Y_END__GRPH_Y_END_MASK 0x00007FFFL
+-//DCP1_INPUT_GAMMA_CONTROL
+-#define DCP1_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x0
+-#define DCP1_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK 0x00000001L
+-//DCP1_GRPH_UPDATE
+-#define DCP1_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0
+-#define DCP1_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1
+-#define DCP1_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2
+-#define DCP1_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3
+-#define DCP1_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR__SHIFT 0x8
+-#define DCP1_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE__SHIFT 0x9
+-#define DCP1_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE__SHIFT 0xa
+-#define DCP1_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10
+-#define DCP1_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14
+-#define DCP1_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+-#define DCP1_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c
+-#define DCP1_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x00000001L
+-#define DCP1_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x00000002L
+-#define DCP1_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x00000004L
+-#define DCP1_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x00000008L
+-#define DCP1_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR_MASK 0x00000100L
+-#define DCP1_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE_MASK 0x00000200L
+-#define DCP1_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE_MASK 0x00000400L
+-#define DCP1_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x00010000L
+-#define DCP1_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x00100000L
+-#define DCP1_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
+-#define DCP1_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000L
+-//DCP1_GRPH_FLIP_CONTROL
+-#define DCP1_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT 0x0
+-#define DCP1_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN__SHIFT 0x1
+-#define DCP1_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN__SHIFT 0x4
+-#define DCP1_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT 0x5
+-#define DCP1_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK 0x00000001L
+-#define DCP1_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN_MASK 0x00000002L
+-#define DCP1_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN_MASK 0x00000010L
+-#define DCP1_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK 0x00000020L
+-//DCP1_GRPH_SURFACE_ADDRESS_INUSE
+-#define DCP1_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT 0x8
+-#define DCP1_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK 0xFFFFFF00L
+-//DCP1_GRPH_DFQ_CONTROL
+-#define DCP1_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x0
+-#define DCP1_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x4
+-#define DCP1_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8
+-#define DCP1_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x00000001L
+-#define DCP1_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x00000070L
+-#define DCP1_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x00000700L
+-//DCP1_GRPH_DFQ_STATUS
+-#define DCP1_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x0
+-#define DCP1_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4
+-#define DCP1_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x8
+-#define DCP1_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x9
+-#define DCP1_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0x0000000FL
+-#define DCP1_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0x000000F0L
+-#define DCP1_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x00000100L
+-#define DCP1_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x00000200L
+-//DCP1_GRPH_INTERRUPT_STATUS
+-#define DCP1_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0
+-#define DCP1_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8
+-#define DCP1_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x00000001L
+-#define DCP1_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x00000100L
+-//DCP1_GRPH_INTERRUPT_CONTROL
+-#define DCP1_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0
+-#define DCP1_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8
+-#define DCP1_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x00000001L
+-#define DCP1_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x00000100L
+-//DCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE
+-#define DCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0
+-#define DCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK 0x000000FFL
+-//DCP1_GRPH_COMPRESS_SURFACE_ADDRESS
+-#define DCP1_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT 0x8
+-#define DCP1_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+-//DCP1_GRPH_COMPRESS_PITCH
+-#define DCP1_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT 0x6
+-#define DCP1_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK 0x0001FFC0L
+-//DCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH
+-#define DCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+-#define DCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+-//DCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT
+-#define DCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__SHIFT 0x0
+-#define DCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_MASK 0x000000FFL
+-//DCP1_PRESCALE_GRPH_CONTROL
+-#define DCP1_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT 0x0
+-#define DCP1_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT 0x1
+-#define DCP1_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x2
+-#define DCP1_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT 0x3
+-#define DCP1_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT 0x4
+-#define DCP1_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK 0x00000001L
+-#define DCP1_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x00000002L
+-#define DCP1_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK 0x00000004L
+-#define DCP1_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK 0x00000008L
+-#define DCP1_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK 0x00000010L
+-//DCP1_PRESCALE_VALUES_GRPH_R
+-#define DCP1_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT 0x0
+-#define DCP1_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT 0x10
+-#define DCP1_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK 0x0000FFFFL
+-#define DCP1_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK 0xFFFF0000L
+-//DCP1_PRESCALE_VALUES_GRPH_G
+-#define DCP1_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT 0x0
+-#define DCP1_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT 0x10
+-#define DCP1_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK 0x0000FFFFL
+-#define DCP1_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK 0xFFFF0000L
+-//DCP1_PRESCALE_VALUES_GRPH_B
+-#define DCP1_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT 0x0
+-#define DCP1_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT 0x10
+-#define DCP1_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK 0x0000FFFFL
+-#define DCP1_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK 0xFFFF0000L
+-//DCP1_INPUT_CSC_CONTROL
+-#define DCP1_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT 0x0
+-#define DCP1_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK 0x00000003L
+-//DCP1_INPUT_CSC_C11_C12
+-#define DCP1_INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT 0x0
+-#define DCP1_INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT 0x10
+-#define DCP1_INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK 0x0000FFFFL
+-#define DCP1_INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK 0xFFFF0000L
+-//DCP1_INPUT_CSC_C13_C14
+-#define DCP1_INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT 0x0
+-#define DCP1_INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT 0x10
+-#define DCP1_INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK 0x0000FFFFL
+-#define DCP1_INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK 0xFFFF0000L
+-//DCP1_INPUT_CSC_C21_C22
+-#define DCP1_INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT 0x0
+-#define DCP1_INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT 0x10
+-#define DCP1_INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK 0x0000FFFFL
+-#define DCP1_INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK 0xFFFF0000L
+-//DCP1_INPUT_CSC_C23_C24
+-#define DCP1_INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT 0x0
+-#define DCP1_INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT 0x10
+-#define DCP1_INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK 0x0000FFFFL
+-#define DCP1_INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK 0xFFFF0000L
+-//DCP1_INPUT_CSC_C31_C32
+-#define DCP1_INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT 0x0
+-#define DCP1_INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT 0x10
+-#define DCP1_INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK 0x0000FFFFL
+-#define DCP1_INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK 0xFFFF0000L
+-//DCP1_INPUT_CSC_C33_C34
+-#define DCP1_INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT 0x0
+-#define DCP1_INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT 0x10
+-#define DCP1_INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK 0x0000FFFFL
+-#define DCP1_INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK 0xFFFF0000L
+-//DCP1_OUTPUT_CSC_CONTROL
+-#define DCP1_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT 0x0
+-#define DCP1_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK 0x00000007L
+-//DCP1_OUTPUT_CSC_C11_C12
+-#define DCP1_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT 0x0
+-#define DCP1_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT 0x10
+-#define DCP1_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK 0x0000FFFFL
+-#define DCP1_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK 0xFFFF0000L
+-//DCP1_OUTPUT_CSC_C13_C14
+-#define DCP1_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT 0x0
+-#define DCP1_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT 0x10
+-#define DCP1_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK 0x0000FFFFL
+-#define DCP1_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK 0xFFFF0000L
+-//DCP1_OUTPUT_CSC_C21_C22
+-#define DCP1_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT 0x0
+-#define DCP1_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT 0x10
+-#define DCP1_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK 0x0000FFFFL
+-#define DCP1_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK 0xFFFF0000L
+-//DCP1_OUTPUT_CSC_C23_C24
+-#define DCP1_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT 0x0
+-#define DCP1_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT 0x10
+-#define DCP1_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK 0x0000FFFFL
+-#define DCP1_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK 0xFFFF0000L
+-//DCP1_OUTPUT_CSC_C31_C32
+-#define DCP1_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT 0x0
+-#define DCP1_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT 0x10
+-#define DCP1_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK 0x0000FFFFL
+-#define DCP1_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK 0xFFFF0000L
+-//DCP1_OUTPUT_CSC_C33_C34
+-#define DCP1_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT 0x0
+-#define DCP1_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT 0x10
+-#define DCP1_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK 0x0000FFFFL
+-#define DCP1_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK 0xFFFF0000L
+-//DCP1_COMM_MATRIXA_TRANS_C11_C12
+-#define DCP1_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT 0x0
+-#define DCP1_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT 0x10
+-#define DCP1_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK 0x0000FFFFL
+-#define DCP1_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK 0xFFFF0000L
+-//DCP1_COMM_MATRIXA_TRANS_C13_C14
+-#define DCP1_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT 0x0
+-#define DCP1_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT 0x10
+-#define DCP1_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK 0x0000FFFFL
+-#define DCP1_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK 0xFFFF0000L
+-//DCP1_COMM_MATRIXA_TRANS_C21_C22
+-#define DCP1_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT 0x0
+-#define DCP1_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT 0x10
+-#define DCP1_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK 0x0000FFFFL
+-#define DCP1_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK 0xFFFF0000L
+-//DCP1_COMM_MATRIXA_TRANS_C23_C24
+-#define DCP1_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT 0x0
+-#define DCP1_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT 0x10
+-#define DCP1_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK 0x0000FFFFL
+-#define DCP1_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK 0xFFFF0000L
+-//DCP1_COMM_MATRIXA_TRANS_C31_C32
+-#define DCP1_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT 0x0
+-#define DCP1_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT 0x10
+-#define DCP1_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK 0x0000FFFFL
+-#define DCP1_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK 0xFFFF0000L
+-//DCP1_COMM_MATRIXA_TRANS_C33_C34
+-#define DCP1_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT 0x0
+-#define DCP1_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT 0x10
+-#define DCP1_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK 0x0000FFFFL
+-#define DCP1_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK 0xFFFF0000L
+-//DCP1_COMM_MATRIXB_TRANS_C11_C12
+-#define DCP1_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT 0x0
+-#define DCP1_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT 0x10
+-#define DCP1_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK 0x0000FFFFL
+-#define DCP1_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK 0xFFFF0000L
+-//DCP1_COMM_MATRIXB_TRANS_C13_C14
+-#define DCP1_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT 0x0
+-#define DCP1_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT 0x10
+-#define DCP1_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK 0x0000FFFFL
+-#define DCP1_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK 0xFFFF0000L
+-//DCP1_COMM_MATRIXB_TRANS_C21_C22
+-#define DCP1_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT 0x0
+-#define DCP1_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT 0x10
+-#define DCP1_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK 0x0000FFFFL
+-#define DCP1_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK 0xFFFF0000L
+-//DCP1_COMM_MATRIXB_TRANS_C23_C24
+-#define DCP1_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT 0x0
+-#define DCP1_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT 0x10
+-#define DCP1_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK 0x0000FFFFL
+-#define DCP1_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK 0xFFFF0000L
+-//DCP1_COMM_MATRIXB_TRANS_C31_C32
+-#define DCP1_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT 0x0
+-#define DCP1_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT 0x10
+-#define DCP1_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK 0x0000FFFFL
+-#define DCP1_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK 0xFFFF0000L
+-//DCP1_COMM_MATRIXB_TRANS_C33_C34
+-#define DCP1_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT 0x0
+-#define DCP1_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT 0x10
+-#define DCP1_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK 0x0000FFFFL
+-#define DCP1_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK 0xFFFF0000L
+-//DCP1_DENORM_CONTROL
+-#define DCP1_DENORM_CONTROL__DENORM_MODE__SHIFT 0x0
+-#define DCP1_DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT 0x4
+-#define DCP1_DENORM_CONTROL__DENORM_MODE_MASK 0x00000007L
+-#define DCP1_DENORM_CONTROL__DENORM_14BIT_OUT_MASK 0x00000010L
+-//DCP1_OUT_ROUND_CONTROL
+-#define DCP1_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT 0x0
+-#define DCP1_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK 0x0000000FL
+-//DCP1_OUT_CLAMP_CONTROL_R_CR
+-#define DCP1_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT 0x0
+-#define DCP1_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT 0x10
+-#define DCP1_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK 0x00003FFFL
+-#define DCP1_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK 0x3FFF0000L
+-//DCP1_OUT_CLAMP_CONTROL_G_Y
+-#define DCP1_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT 0x0
+-#define DCP1_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT 0x10
+-#define DCP1_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK 0x00003FFFL
+-#define DCP1_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK 0x3FFF0000L
+-//DCP1_OUT_CLAMP_CONTROL_B_CB
+-#define DCP1_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT 0x0
+-#define DCP1_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT 0x10
+-#define DCP1_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK 0x00003FFFL
+-#define DCP1_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK 0x3FFF0000L
+-//DCP1_KEY_CONTROL
+-#define DCP1_KEY_CONTROL__KEY_MODE__SHIFT 0x1
+-#define DCP1_KEY_CONTROL__KEY_MODE_MASK 0x00000006L
+-//DCP1_KEY_RANGE_ALPHA
+-#define DCP1_KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT 0x0
+-#define DCP1_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT 0x10
+-#define DCP1_KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK 0x0000FFFFL
+-#define DCP1_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK 0xFFFF0000L
+-//DCP1_KEY_RANGE_RED
+-#define DCP1_KEY_RANGE_RED__KEY_RED_LOW__SHIFT 0x0
+-#define DCP1_KEY_RANGE_RED__KEY_RED_HIGH__SHIFT 0x10
+-#define DCP1_KEY_RANGE_RED__KEY_RED_LOW_MASK 0x0000FFFFL
+-#define DCP1_KEY_RANGE_RED__KEY_RED_HIGH_MASK 0xFFFF0000L
+-//DCP1_KEY_RANGE_GREEN
+-#define DCP1_KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT 0x0
+-#define DCP1_KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT 0x10
+-#define DCP1_KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK 0x0000FFFFL
+-#define DCP1_KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK 0xFFFF0000L
+-//DCP1_KEY_RANGE_BLUE
+-#define DCP1_KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT 0x0
+-#define DCP1_KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT 0x10
+-#define DCP1_KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK 0x0000FFFFL
+-#define DCP1_KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK 0xFFFF0000L
+-//DCP1_DEGAMMA_CONTROL
+-#define DCP1_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x0
+-#define DCP1_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT 0x8
+-#define DCP1_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0xc
+-#define DCP1_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x00000003L
+-#define DCP1_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK 0x00000300L
+-#define DCP1_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK 0x00003000L
+-//DCP1_GAMUT_REMAP_CONTROL
+-#define DCP1_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT 0x0
+-#define DCP1_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK 0x00000003L
+-//DCP1_GAMUT_REMAP_C11_C12
+-#define DCP1_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT 0x0
+-#define DCP1_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT 0x10
+-#define DCP1_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK 0x0000FFFFL
+-#define DCP1_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK 0xFFFF0000L
+-//DCP1_GAMUT_REMAP_C13_C14
+-#define DCP1_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT 0x0
+-#define DCP1_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT 0x10
+-#define DCP1_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK 0x0000FFFFL
+-#define DCP1_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK 0xFFFF0000L
+-//DCP1_GAMUT_REMAP_C21_C22
+-#define DCP1_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT 0x0
+-#define DCP1_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT 0x10
+-#define DCP1_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK 0x0000FFFFL
+-#define DCP1_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK 0xFFFF0000L
+-//DCP1_GAMUT_REMAP_C23_C24
+-#define DCP1_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT 0x0
+-#define DCP1_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT 0x10
+-#define DCP1_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK 0x0000FFFFL
+-#define DCP1_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK 0xFFFF0000L
+-//DCP1_GAMUT_REMAP_C31_C32
+-#define DCP1_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT 0x0
+-#define DCP1_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT 0x10
+-#define DCP1_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK 0x0000FFFFL
+-#define DCP1_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK 0xFFFF0000L
+-//DCP1_GAMUT_REMAP_C33_C34
+-#define DCP1_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT 0x0
+-#define DCP1_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT 0x10
+-#define DCP1_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK 0x0000FFFFL
+-#define DCP1_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK 0xFFFF0000L
+-//DCP1_DCP_SPATIAL_DITHER_CNTL
+-#define DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT 0x0
+-#define DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT 0x4
+-#define DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT 0x6
+-#define DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT 0x8
+-#define DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT 0x9
+-#define DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT 0xa
+-#define DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK 0x00000001L
+-#define DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK 0x00000030L
+-#define DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK 0x000000C0L
+-#define DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK 0x00000100L
+-#define DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK 0x00000200L
+-#define DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK 0x00000400L
+-//DCP1_DCP_RANDOM_SEEDS
+-#define DCP1_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT 0x0
+-#define DCP1_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT 0x8
+-#define DCP1_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT 0x10
+-#define DCP1_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK 0x000000FFL
+-#define DCP1_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK 0x0000FF00L
+-#define DCP1_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK 0x00FF0000L
+-//DCP1_DCP_FP_CONVERTED_FIELD
+-#define DCP1_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT 0x0
+-#define DCP1_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14
+-#define DCP1_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK 0x0003FFFFL
+-#define DCP1_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK 0x07F00000L
+-//DCP1_CUR_CONTROL
+-#define DCP1_CUR_CONTROL__CURSOR_EN__SHIFT 0x0
+-#define DCP1_CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT 0x4
+-#define DCP1_CUR_CONTROL__CURSOR_MODE__SHIFT 0x8
+-#define DCP1_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM__SHIFT 0xb
+-#define DCP1_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION__SHIFT 0xc
+-#define DCP1_CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x10
+-#define DCP1_CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT 0x14
+-#define DCP1_CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT 0x18
+-#define DCP1_CUR_CONTROL__CURSOR_EN_MASK 0x00000001L
+-#define DCP1_CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK 0x00000010L
+-#define DCP1_CUR_CONTROL__CURSOR_MODE_MASK 0x00000300L
+-#define DCP1_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM_MASK 0x00000800L
+-#define DCP1_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION_MASK 0x0000F000L
+-#define DCP1_CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00010000L
+-#define DCP1_CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK 0x00100000L
+-#define DCP1_CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK 0x07000000L
+-//DCP1_CUR_SURFACE_ADDRESS
+-#define DCP1_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0
+-#define DCP1_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+-//DCP1_CUR_SIZE
+-#define DCP1_CUR_SIZE__CURSOR_HEIGHT__SHIFT 0x0
+-#define DCP1_CUR_SIZE__CURSOR_WIDTH__SHIFT 0x10
+-#define DCP1_CUR_SIZE__CURSOR_HEIGHT_MASK 0x0000007FL
+-#define DCP1_CUR_SIZE__CURSOR_WIDTH_MASK 0x007F0000L
+-//DCP1_CUR_SURFACE_ADDRESS_HIGH
+-#define DCP1_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+-#define DCP1_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+-//DCP1_CUR_POSITION
+-#define DCP1_CUR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0
+-#define DCP1_CUR_POSITION__CURSOR_X_POSITION__SHIFT 0x10
+-#define DCP1_CUR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL
+-#define DCP1_CUR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L
+-//DCP1_CUR_HOT_SPOT
+-#define DCP1_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0
+-#define DCP1_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10
+-#define DCP1_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x0000007FL
+-#define DCP1_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x007F0000L
+-//DCP1_CUR_COLOR1
+-#define DCP1_CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT 0x0
+-#define DCP1_CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT 0x8
+-#define DCP1_CUR_COLOR1__CUR_COLOR1_RED__SHIFT 0x10
+-#define DCP1_CUR_COLOR1__CUR_COLOR1_BLUE_MASK 0x000000FFL
+-#define DCP1_CUR_COLOR1__CUR_COLOR1_GREEN_MASK 0x0000FF00L
+-#define DCP1_CUR_COLOR1__CUR_COLOR1_RED_MASK 0x00FF0000L
+-//DCP1_CUR_COLOR2
+-#define DCP1_CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT 0x0
+-#define DCP1_CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT 0x8
+-#define DCP1_CUR_COLOR2__CUR_COLOR2_RED__SHIFT 0x10
+-#define DCP1_CUR_COLOR2__CUR_COLOR2_BLUE_MASK 0x000000FFL
+-#define DCP1_CUR_COLOR2__CUR_COLOR2_GREEN_MASK 0x0000FF00L
+-#define DCP1_CUR_COLOR2__CUR_COLOR2_RED_MASK 0x00FF0000L
+-//DCP1_CUR_UPDATE
+-#define DCP1_CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT 0x0
+-#define DCP1_CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT 0x1
+-#define DCP1_CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT 0x10
+-#define DCP1_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+-#define DCP1_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE__SHIFT 0x19
+-#define DCP1_CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK 0x00000001L
+-#define DCP1_CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x00000002L
+-#define DCP1_CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK 0x00010000L
+-#define DCP1_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
+-#define DCP1_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE_MASK 0x06000000L
+-//DCP1_CUR_REQUEST_FILTER_CNTL
+-#define DCP1_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT 0x0
+-#define DCP1_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK 0x00000001L
+-//DCP1_CUR_STEREO_CONTROL
+-#define DCP1_CUR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0
+-#define DCP1_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4
+-#define DCP1_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x10
+-#define DCP1_CUR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L
+-#define DCP1_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x00003FF0L
+-#define DCP1_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0x03FF0000L
+-//DCP1_DC_LUT_RW_MODE
+-#define DCP1_DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT 0x0
+-#define DCP1_DC_LUT_RW_MODE__DC_LUT_ERROR__SHIFT 0x10
+-#define DCP1_DC_LUT_RW_MODE__DC_LUT_ERROR_RST__SHIFT 0x11
+-#define DCP1_DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK 0x00000001L
+-#define DCP1_DC_LUT_RW_MODE__DC_LUT_ERROR_MASK 0x00010000L
+-#define DCP1_DC_LUT_RW_MODE__DC_LUT_ERROR_RST_MASK 0x00020000L
+-//DCP1_DC_LUT_RW_INDEX
+-#define DCP1_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT 0x0
+-#define DCP1_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK 0x000000FFL
+-//DCP1_DC_LUT_SEQ_COLOR
+-#define DCP1_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT 0x0
+-#define DCP1_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK 0x0000FFFFL
+-//DCP1_DC_LUT_PWL_DATA
+-#define DCP1_DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT 0x0
+-#define DCP1_DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT 0x10
+-#define DCP1_DC_LUT_PWL_DATA__DC_LUT_BASE_MASK 0x0000FFFFL
+-#define DCP1_DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK 0xFFFF0000L
+-//DCP1_DC_LUT_30_COLOR
+-#define DCP1_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT 0x0
+-#define DCP1_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT 0xa
+-#define DCP1_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT 0x14
+-#define DCP1_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK 0x000003FFL
+-#define DCP1_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK 0x000FFC00L
+-#define DCP1_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK 0x3FF00000L
+-//DCP1_DC_LUT_VGA_ACCESS_ENABLE
+-#define DCP1_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT 0x0
+-#define DCP1_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK 0x00000001L
+-//DCP1_DC_LUT_WRITE_EN_MASK
+-#define DCP1_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT 0x0
+-#define DCP1_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK 0x00000007L
+-//DCP1_DC_LUT_AUTOFILL
+-#define DCP1_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT 0x0
+-#define DCP1_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT 0x1
+-#define DCP1_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK 0x00000001L
+-#define DCP1_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x00000002L
+-//DCP1_DC_LUT_CONTROL
+-#define DCP1_DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT 0x0
+-#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT 0x4
+-#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT 0x5
+-#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT 0x6
+-#define DCP1_DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT 0x8
+-#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT 0xc
+-#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT 0xd
+-#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT 0xe
+-#define DCP1_DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT 0x10
+-#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT 0x14
+-#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT 0x15
+-#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT 0x16
+-#define DCP1_DC_LUT_CONTROL__DC_LUT_INC_B_MASK 0x0000000FL
+-#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK 0x00000010L
+-#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK 0x00000020L
+-#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK 0x000000C0L
+-#define DCP1_DC_LUT_CONTROL__DC_LUT_INC_G_MASK 0x00000F00L
+-#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK 0x00001000L
+-#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK 0x00002000L
+-#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK 0x0000C000L
+-#define DCP1_DC_LUT_CONTROL__DC_LUT_INC_R_MASK 0x000F0000L
+-#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK 0x00100000L
+-#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK 0x00200000L
+-#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK 0x00C00000L
+-//DCP1_DC_LUT_BLACK_OFFSET_BLUE
+-#define DCP1_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0
+-#define DCP1_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK 0x0000FFFFL
+-//DCP1_DC_LUT_BLACK_OFFSET_GREEN
+-#define DCP1_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0
+-#define DCP1_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK 0x0000FFFFL
+-//DCP1_DC_LUT_BLACK_OFFSET_RED
+-#define DCP1_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT 0x0
+-#define DCP1_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK 0x0000FFFFL
+-//DCP1_DC_LUT_WHITE_OFFSET_BLUE
+-#define DCP1_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT 0x0
+-#define DCP1_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK 0x0000FFFFL
+-//DCP1_DC_LUT_WHITE_OFFSET_GREEN
+-#define DCP1_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT 0x0
+-#define DCP1_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK 0x0000FFFFL
+-//DCP1_DC_LUT_WHITE_OFFSET_RED
+-#define DCP1_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT 0x0
+-#define DCP1_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK 0x0000FFFFL
+-//DCP1_DCP_CRC_CONTROL
+-#define DCP1_DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT 0x0
+-#define DCP1_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x2
+-#define DCP1_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT 0x8
+-#define DCP1_DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK 0x00000001L
+-#define DCP1_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK 0x0000001CL
+-#define DCP1_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK 0x00000300L
+-//DCP1_DCP_CRC_MASK
+-#define DCP1_DCP_CRC_MASK__DCP_CRC_MASK__SHIFT 0x0
+-#define DCP1_DCP_CRC_MASK__DCP_CRC_MASK_MASK 0xFFFFFFFFL
+-//DCP1_DCP_CRC_CURRENT
+-#define DCP1_DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT 0x0
+-#define DCP1_DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK 0xFFFFFFFFL
+-//DCP1_DVMM_PTE_CONTROL
+-#define DCP1_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT 0x0
+-#define DCP1_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT 0x1
+-#define DCP1_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT 0x5
+-#define DCP1_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT 0x9
+-#define DCP1_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT 0x14
+-#define DCP1_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT 0x15
+-#define DCP1_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK 0x00000001L
+-#define DCP1_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK 0x0000001EL
+-#define DCP1_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK 0x000001E0L
+-#define DCP1_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK 0x0007FE00L
+-#define DCP1_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK 0x00100000L
+-#define DCP1_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK 0x00200000L
+-//DCP1_DCP_CRC_LAST
+-#define DCP1_DCP_CRC_LAST__DCP_CRC_LAST__SHIFT 0x0
+-#define DCP1_DCP_CRC_LAST__DCP_CRC_LAST_MASK 0xFFFFFFFFL
+-//DCP1_DVMM_PTE_ARB_CONTROL
+-#define DCP1_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT 0x0
+-#define DCP1_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT 0x8
+-#define DCP1_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK 0x0000003FL
+-#define DCP1_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK 0x0000FF00L
+-//DCP1_GRPH_FLIP_RATE_CNTL
+-#define DCP1_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT 0x0
+-#define DCP1_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT 0x3
+-#define DCP1_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK 0x00000007L
+-#define DCP1_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK 0x00000008L
+-//DCP1_DCP_GSL_CONTROL
+-#define DCP1_DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT 0x0
+-#define DCP1_DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT 0x1
+-#define DCP1_DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x2
+-#define DCP1_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT 0x4
+-#define DCP1_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT 0x14
+-#define DCP1_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP__SHIFT 0x15
+-#define DCP1_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN__SHIFT 0x17
+-#define DCP1_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT 0x18
+-#define DCP1_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC__SHIFT 0x1a
+-#define DCP1_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT 0x1b
+-#define DCP1_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT 0x1c
+-#define DCP1_DCP_GSL_CONTROL__DCP_GSL0_EN_MASK 0x00000001L
+-#define DCP1_DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x00000002L
+-#define DCP1_DCP_GSL_CONTROL__DCP_GSL2_EN_MASK 0x00000004L
+-#define DCP1_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK 0x000FFFF0L
+-#define DCP1_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK 0x00100000L
+-#define DCP1_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_MASK 0x00600000L
+-#define DCP1_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_MASK 0x00800000L
+-#define DCP1_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK 0x03000000L
+-#define DCP1_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_MASK 0x04000000L
+-#define DCP1_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK 0x08000000L
+-#define DCP1_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK 0xF0000000L
+-//DCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK
+-#define DCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT 0x0
+-#define DCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT 0x4
+-#define DCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK 0x0000000FL
+-#define DCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK 0x000001F0L
+-//DCP1_GRPH_STEREOSYNC_FLIP
+-#define DCP1_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0
+-#define DCP1_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x8
+-#define DCP1_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10
+-#define DCP1_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11
+-#define DCP1_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c
+-#define DCP1_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x00000001L
+-#define DCP1_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x00000300L
+-#define DCP1_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x00010000L
+-#define DCP1_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x00020000L
+-#define DCP1_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000L
+-//DCP1_HW_ROTATION
+-#define DCP1_HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT 0x0
+-#define DCP1_HW_ROTATION__GRPH_ROTATION_ANGLE_MASK 0x00000007L
+-//DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL
+-#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT 0x0
+-#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT 0x1
+-#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT 0x4
+-#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK 0x00000001L
+-#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK 0x00000002L
+-#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK 0x0001FFF0L
+-//DCP1_REGAMMA_CONTROL
+-#define DCP1_REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT 0x0
+-#define DCP1_REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK 0x00000007L
+-//DCP1_REGAMMA_LUT_INDEX
+-#define DCP1_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x0
+-#define DCP1_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK 0x000001FFL
+-//DCP1_REGAMMA_LUT_DATA
+-#define DCP1_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT 0x0
+-#define DCP1_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK 0x0007FFFFL
+-//DCP1_REGAMMA_LUT_WRITE_EN_MASK
+-#define DCP1_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x0
+-#define DCP1_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x00000007L
+-//DCP1_REGAMMA_CNTLA_START_CNTL
+-#define DCP1_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x0
+-#define DCP1_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14
+-#define DCP1_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK 0x0003FFFFL
+-#define DCP1_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
+-//DCP1_REGAMMA_CNTLA_SLOPE_CNTL
+-#define DCP1_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+-#define DCP1_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
+-//DCP1_REGAMMA_CNTLA_END_CNTL1
+-#define DCP1_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x0
+-#define DCP1_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK 0x0000FFFFL
+-//DCP1_REGAMMA_CNTLA_END_CNTL2
+-#define DCP1_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0
+-#define DCP1_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10
+-#define DCP1_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
+-#define DCP1_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xFFFF0000L
+-//DCP1_REGAMMA_CNTLA_REGION_0_1
+-#define DCP1_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+-#define DCP1_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP1_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+-#define DCP1_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP1_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP1_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP1_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP1_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP1_REGAMMA_CNTLA_REGION_2_3
+-#define DCP1_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+-#define DCP1_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP1_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+-#define DCP1_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP1_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP1_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP1_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP1_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP1_REGAMMA_CNTLA_REGION_4_5
+-#define DCP1_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+-#define DCP1_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP1_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+-#define DCP1_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP1_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP1_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP1_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP1_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP1_REGAMMA_CNTLA_REGION_6_7
+-#define DCP1_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+-#define DCP1_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP1_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+-#define DCP1_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP1_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP1_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP1_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP1_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP1_REGAMMA_CNTLA_REGION_8_9
+-#define DCP1_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+-#define DCP1_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP1_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+-#define DCP1_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP1_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP1_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP1_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP1_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP1_REGAMMA_CNTLA_REGION_10_11
+-#define DCP1_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+-#define DCP1_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP1_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+-#define DCP1_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP1_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP1_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP1_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP1_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP1_REGAMMA_CNTLA_REGION_12_13
+-#define DCP1_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+-#define DCP1_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP1_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+-#define DCP1_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP1_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP1_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP1_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP1_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP1_REGAMMA_CNTLA_REGION_14_15
+-#define DCP1_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+-#define DCP1_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP1_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+-#define DCP1_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP1_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP1_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP1_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP1_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP1_REGAMMA_CNTLB_START_CNTL
+-#define DCP1_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x0
+-#define DCP1_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14
+-#define DCP1_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK 0x0003FFFFL
+-#define DCP1_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
+-//DCP1_REGAMMA_CNTLB_SLOPE_CNTL
+-#define DCP1_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+-#define DCP1_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
+-//DCP1_REGAMMA_CNTLB_END_CNTL1
+-#define DCP1_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x0
+-#define DCP1_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK 0x0000FFFFL
+-//DCP1_REGAMMA_CNTLB_END_CNTL2
+-#define DCP1_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0
+-#define DCP1_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10
+-#define DCP1_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
+-#define DCP1_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xFFFF0000L
+-//DCP1_REGAMMA_CNTLB_REGION_0_1
+-#define DCP1_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+-#define DCP1_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP1_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+-#define DCP1_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP1_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP1_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP1_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP1_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP1_REGAMMA_CNTLB_REGION_2_3
+-#define DCP1_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+-#define DCP1_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP1_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+-#define DCP1_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP1_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP1_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP1_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP1_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP1_REGAMMA_CNTLB_REGION_4_5
+-#define DCP1_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+-#define DCP1_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP1_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+-#define DCP1_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP1_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP1_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP1_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP1_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP1_REGAMMA_CNTLB_REGION_6_7
+-#define DCP1_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+-#define DCP1_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP1_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+-#define DCP1_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP1_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP1_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP1_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP1_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP1_REGAMMA_CNTLB_REGION_8_9
+-#define DCP1_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+-#define DCP1_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP1_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+-#define DCP1_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP1_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP1_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP1_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP1_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP1_REGAMMA_CNTLB_REGION_10_11
+-#define DCP1_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+-#define DCP1_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP1_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+-#define DCP1_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP1_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP1_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP1_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP1_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP1_REGAMMA_CNTLB_REGION_12_13
+-#define DCP1_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+-#define DCP1_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP1_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+-#define DCP1_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP1_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP1_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP1_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP1_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP1_REGAMMA_CNTLB_REGION_14_15
+-#define DCP1_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+-#define DCP1_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP1_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+-#define DCP1_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP1_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP1_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP1_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP1_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP1_ALPHA_CONTROL
+-#define DCP1_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT 0x0
+-#define DCP1_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT 0x1
+-#define DCP1_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK 0x00000001L
+-#define DCP1_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK 0x00000002L
+-//DCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS
+-#define DCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT 0x8
+-#define DCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+-//DCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH
+-#define DCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+-#define DCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+-//DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS
+-#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT 0x0
+-#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT 0x18
+-#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT 0x19
+-#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT 0x1a
+-#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT 0x1c
+-#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT 0x1d
+-#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT 0x1e
+-#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK 0x000FFFFFL
+-#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK 0x01000000L
+-#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK 0x02000000L
+-#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK 0x04000000L
+-#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK 0x10000000L
+-#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK 0x20000000L
+-#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK 0x40000000L
+-//DCP1_GRPH_XDMA_FLIP_TIMEOUT
+-#define DCP1_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS__SHIFT 0x0
+-#define DCP1_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK__SHIFT 0x1
+-#define DCP1_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK__SHIFT 0x2
+-#define DCP1_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS_MASK 0x00000001L
+-#define DCP1_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK_MASK 0x00000002L
+-#define DCP1_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK_MASK 0x00000004L
+-//DCP1_GRPH_XDMA_FLIP_AVG_DELAY
+-#define DCP1_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY__SHIFT 0x0
+-#define DCP1_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD__SHIFT 0x10
+-#define DCP1_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY_MASK 0x0000FFFFL
+-#define DCP1_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD_MASK 0x00FF0000L
+-//DCP1_GRPH_SURFACE_COUNTER_CONTROL
+-#define DCP1_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN__SHIFT 0x0
+-#define DCP1_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT__SHIFT 0x1
+-#define DCP1_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED__SHIFT 0x9
+-#define DCP1_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN_MASK 0x00000001L
+-#define DCP1_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT_MASK 0x0000001EL
+-#define DCP1_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_MASK 0x00000200L
+-//DCP1_GRPH_SURFACE_COUNTER_OUTPUT
+-#define DCP1_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN__SHIFT 0x0
+-#define DCP1_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX__SHIFT 0x10
+-#define DCP1_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN_MASK 0x0000FFFFL
+-#define DCP1_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX_MASK 0xFFFF0000L
+-
+-
+-// addressBlock: dce_dc_lb1_dispdec
+-//LB1_LB_DATA_FORMAT
+-#define LB1_LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0
+-#define LB1_LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2
+-#define LB1_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3
+-#define LB1_LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4
+-#define LB1_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5
+-#define LB1_LB_DATA_FORMAT__PREFILL_EN__SHIFT 0x8
+-#define LB1_LB_DATA_FORMAT__PREFETCH__SHIFT 0xc
+-#define LB1_LB_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18
+-#define LB1_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f
+-#define LB1_LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x00000003L
+-#define LB1_LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x00000004L
+-#define LB1_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000008L
+-#define LB1_LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x00000010L
+-#define LB1_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x00000020L
+-#define LB1_LB_DATA_FORMAT__PREFILL_EN_MASK 0x00000100L
+-#define LB1_LB_DATA_FORMAT__PREFETCH_MASK 0x00001000L
+-#define LB1_LB_DATA_FORMAT__REQUEST_MODE_MASK 0x01000000L
+-#define LB1_LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000L
+-//LB1_LB_MEMORY_CTRL
+-#define LB1_LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0
+-#define LB1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
+-#define LB1_LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14
+-#define LB1_LB_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0x00001FFFL
+-#define LB1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x000F0000L
+-#define LB1_LB_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x00300000L
+-//LB1_LB_MEMORY_SIZE_STATUS
+-#define LB1_LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0
+-#define LB1_LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0x00001FFFL
+-//LB1_LB_DESKTOP_HEIGHT
+-#define LB1_LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0
+-#define LB1_LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x00007FFFL
+-//LB1_LB_VLINE_START_END
+-#define LB1_LB_VLINE_START_END__VLINE_START__SHIFT 0x0
+-#define LB1_LB_VLINE_START_END__VLINE_END__SHIFT 0x10
+-#define LB1_LB_VLINE_START_END__VLINE_INV__SHIFT 0x1f
+-#define LB1_LB_VLINE_START_END__VLINE_START_MASK 0x00003FFFL
+-#define LB1_LB_VLINE_START_END__VLINE_END_MASK 0x7FFF0000L
+-#define LB1_LB_VLINE_START_END__VLINE_INV_MASK 0x80000000L
+-//LB1_LB_VLINE2_START_END
+-#define LB1_LB_VLINE2_START_END__VLINE2_START__SHIFT 0x0
+-#define LB1_LB_VLINE2_START_END__VLINE2_END__SHIFT 0x10
+-#define LB1_LB_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f
+-#define LB1_LB_VLINE2_START_END__VLINE2_START_MASK 0x00003FFFL
+-#define LB1_LB_VLINE2_START_END__VLINE2_END_MASK 0x7FFF0000L
+-#define LB1_LB_VLINE2_START_END__VLINE2_INV_MASK 0x80000000L
+-//LB1_LB_V_COUNTER
+-#define LB1_LB_V_COUNTER__V_COUNTER__SHIFT 0x0
+-#define LB1_LB_V_COUNTER__V_COUNTER_MASK 0x00007FFFL
+-//LB1_LB_SNAPSHOT_V_COUNTER
+-#define LB1_LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0
+-#define LB1_LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x00007FFFL
+-//LB1_LB_INTERRUPT_MASK
+-#define LB1_LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0
+-#define LB1_LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4
+-#define LB1_LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8
+-#define LB1_LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x00000001L
+-#define LB1_LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x00000010L
+-#define LB1_LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x00000100L
+-//LB1_LB_VLINE_STATUS
+-#define LB1_LB_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0
+-#define LB1_LB_VLINE_STATUS__VLINE_ACK__SHIFT 0x4
+-#define LB1_LB_VLINE_STATUS__VLINE_STAT__SHIFT 0xc
+-#define LB1_LB_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10
+-#define LB1_LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11
+-#define LB1_LB_VLINE_STATUS__VLINE_OCCURRED_MASK 0x00000001L
+-#define LB1_LB_VLINE_STATUS__VLINE_ACK_MASK 0x00000010L
+-#define LB1_LB_VLINE_STATUS__VLINE_STAT_MASK 0x00001000L
+-#define LB1_LB_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x00010000L
+-#define LB1_LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x00020000L
+-//LB1_LB_VLINE2_STATUS
+-#define LB1_LB_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0
+-#define LB1_LB_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4
+-#define LB1_LB_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc
+-#define LB1_LB_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10
+-#define LB1_LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11
+-#define LB1_LB_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x00000001L
+-#define LB1_LB_VLINE2_STATUS__VLINE2_ACK_MASK 0x00000010L
+-#define LB1_LB_VLINE2_STATUS__VLINE2_STAT_MASK 0x00001000L
+-#define LB1_LB_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x00010000L
+-#define LB1_LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x00020000L
+-//LB1_LB_VBLANK_STATUS
+-#define LB1_LB_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0
+-#define LB1_LB_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4
+-#define LB1_LB_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc
+-#define LB1_LB_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10
+-#define LB1_LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11
+-#define LB1_LB_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x00000001L
+-#define LB1_LB_VBLANK_STATUS__VBLANK_ACK_MASK 0x00000010L
+-#define LB1_LB_VBLANK_STATUS__VBLANK_STAT_MASK 0x00001000L
+-#define LB1_LB_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x00010000L
+-#define LB1_LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x00020000L
+-//LB1_LB_SYNC_RESET_SEL
+-#define LB1_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0
+-#define LB1_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4
+-#define LB1_LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8
+-#define LB1_LB_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16
+-#define LB1_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x00000003L
+-#define LB1_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x00000010L
+-#define LB1_LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0x0000FF00L
+-#define LB1_LB_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0x00C00000L
+-//LB1_LB_BLACK_KEYER_R_CR
+-#define LB1_LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4
+-#define LB1_LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0x0000FFF0L
+-//LB1_LB_BLACK_KEYER_G_Y
+-#define LB1_LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4
+-#define LB1_LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0x0000FFF0L
+-//LB1_LB_BLACK_KEYER_B_CB
+-#define LB1_LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4
+-#define LB1_LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0x0000FFF0L
+-//LB1_LB_KEYER_COLOR_CTRL
+-#define LB1_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0
+-#define LB1_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8
+-#define LB1_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x00000001L
+-#define LB1_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x00000100L
+-//LB1_LB_KEYER_COLOR_R_CR
+-#define LB1_LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4
+-#define LB1_LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0x0000FFF0L
+-//LB1_LB_KEYER_COLOR_G_Y
+-#define LB1_LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4
+-#define LB1_LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0x0000FFF0L
+-//LB1_LB_KEYER_COLOR_B_CB
+-#define LB1_LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4
+-#define LB1_LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0x0000FFF0L
+-//LB1_LB_KEYER_COLOR_REP_R_CR
+-#define LB1_LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4
+-#define LB1_LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0x0000FFF0L
+-//LB1_LB_KEYER_COLOR_REP_G_Y
+-#define LB1_LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4
+-#define LB1_LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0x0000FFF0L
+-//LB1_LB_KEYER_COLOR_REP_B_CB
+-#define LB1_LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4
+-#define LB1_LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0x0000FFF0L
+-//LB1_LB_BUFFER_LEVEL_STATUS
+-#define LB1_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0
+-#define LB1_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa
+-#define LB1_LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10
+-#define LB1_LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c
+-#define LB1_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x0000003FL
+-#define LB1_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0x0000FC00L
+-#define LB1_LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0x0FFF0000L
+-#define LB1_LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xF0000000L
+-//LB1_LB_BUFFER_URGENCY_CTRL
+-#define LB1_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0
+-#define LB1_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10
+-#define LB1_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0x00000FFFL
+-#define LB1_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0x0FFF0000L
+-//LB1_LB_BUFFER_URGENCY_STATUS
+-#define LB1_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0
+-#define LB1_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10
+-#define LB1_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0x00000FFFL
+-#define LB1_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x00010000L
+-//LB1_LB_BUFFER_STATUS
+-#define LB1_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0
+-#define LB1_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4
+-#define LB1_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8
+-#define LB1_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc
+-#define LB1_LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10
+-#define LB1_LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14
+-#define LB1_LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18
+-#define LB1_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0x0000000FL
+-#define LB1_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x00000010L
+-#define LB1_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x00000100L
+-#define LB1_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x00001000L
+-#define LB1_LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x00010000L
+-#define LB1_LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x00100000L
+-#define LB1_LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x01000000L
+-//LB1_LB_NO_OUTSTANDING_REQ_STATUS
+-#define LB1_LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0
+-#define LB1_LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x00000001L
+-//LB1_MVP_AFR_FLIP_MODE
+-#define LB1_MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT 0x0
+-#define LB1_MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK 0x00000003L
+-//LB1_MVP_AFR_FLIP_FIFO_CNTL
+-#define LB1_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT 0x0
+-#define LB1_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT 0x4
+-#define LB1_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT 0x8
+-#define LB1_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT 0xc
+-#define LB1_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK 0x0000000FL
+-#define LB1_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK 0x00000010L
+-#define LB1_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK 0x00000100L
+-#define LB1_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK 0x00001000L
+-//LB1_MVP_FLIP_LINE_NUM_INSERT
+-#define LB1_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT 0x0
+-#define LB1_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT 0x8
+-#define LB1_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT 0x18
+-#define LB1_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT 0x1e
+-#define LB1_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK 0x00000003L
+-#define LB1_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK 0x007FFF00L
+-#define LB1_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK 0x3F000000L
+-#define LB1_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK 0x40000000L
+-//LB1_DC_MVP_LB_CONTROL
+-#define LB1_DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT 0x0
+-#define LB1_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT 0x8
+-#define LB1_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT 0xc
+-#define LB1_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT 0x10
+-#define LB1_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT 0x14
+-#define LB1_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT 0x1c
+-#define LB1_DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT 0x1f
+-#define LB1_DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK 0x00000003L
+-#define LB1_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK 0x00000100L
+-#define LB1_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK 0x00001000L
+-#define LB1_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK 0x00010000L
+-#define LB1_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK 0x00100000L
+-#define LB1_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK 0x10000000L
+-#define LB1_DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK 0x80000000L
+-
+-
+-// addressBlock: dce_dc_dcfe1_dispdec
+-//DCFE1_DCFE_CLOCK_CONTROL
+-#define DCFE1_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x4
+-#define DCFE1_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x8
+-#define DCFE1_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0xc
+-#define DCFE1_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE__SHIFT 0xf
+-#define DCFE1_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE__SHIFT 0x11
+-#define DCFE1_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL__SHIFT 0x18
+-#define DCFE1_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE__SHIFT 0x1f
+-#define DCFE1_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x00000010L
+-#define DCFE1_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE_MASK 0x00000100L
+-#define DCFE1_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE_MASK 0x00001000L
+-#define DCFE1_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE_MASK 0x00008000L
+-#define DCFE1_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE_MASK 0x00020000L
+-#define DCFE1_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL_MASK 0x1F000000L
+-#define DCFE1_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE_MASK 0x80000000L
+-//DCFE1_DCFE_SOFT_RESET
+-#define DCFE1_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET__SHIFT 0x0
+-#define DCFE1_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET__SHIFT 0x1
+-#define DCFE1_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET__SHIFT 0x2
+-#define DCFE1_DCFE_SOFT_RESET__SCL_SOFT_RESET__SHIFT 0x3
+-#define DCFE1_DCFE_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4
+-#define DCFE1_DCFE_SOFT_RESET__PSCL_SOFT_RESET__SHIFT 0x5
+-#define DCFE1_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET_MASK 0x00000001L
+-#define DCFE1_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET_MASK 0x00000002L
+-#define DCFE1_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET_MASK 0x00000004L
+-#define DCFE1_DCFE_SOFT_RESET__SCL_SOFT_RESET_MASK 0x00000008L
+-#define DCFE1_DCFE_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x00000010L
+-#define DCFE1_DCFE_SOFT_RESET__PSCL_SOFT_RESET_MASK 0x00000020L
+-//DCFE1_DCFE_MEM_PWR_CTRL
+-#define DCFE1_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE__SHIFT 0x0
+-#define DCFE1_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS__SHIFT 0x2
+-#define DCFE1_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE__SHIFT 0x3
+-#define DCFE1_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS__SHIFT 0x5
+-#define DCFE1_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE__SHIFT 0x6
+-#define DCFE1_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS__SHIFT 0x8
+-#define DCFE1_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE__SHIFT 0x9
+-#define DCFE1_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS__SHIFT 0xb
+-#define DCFE1_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE__SHIFT 0xc
+-#define DCFE1_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS__SHIFT 0xe
+-#define DCFE1_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE__SHIFT 0xf
+-#define DCFE1_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS__SHIFT 0x11
+-#define DCFE1_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE__SHIFT 0x12
+-#define DCFE1_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS__SHIFT 0x14
+-#define DCFE1_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE__SHIFT 0x15
+-#define DCFE1_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS__SHIFT 0x17
+-#define DCFE1_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE__SHIFT 0x18
+-#define DCFE1_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS__SHIFT 0x1a
+-#define DCFE1_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE__SHIFT 0x1b
+-#define DCFE1_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS__SHIFT 0x1d
+-#define DCFE1_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE_MASK 0x00000003L
+-#define DCFE1_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS_MASK 0x00000004L
+-#define DCFE1_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE_MASK 0x00000018L
+-#define DCFE1_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS_MASK 0x00000020L
+-#define DCFE1_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE_MASK 0x000000C0L
+-#define DCFE1_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS_MASK 0x00000100L
+-#define DCFE1_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE_MASK 0x00000600L
+-#define DCFE1_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS_MASK 0x00000800L
+-#define DCFE1_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE_MASK 0x00003000L
+-#define DCFE1_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS_MASK 0x00004000L
+-#define DCFE1_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE_MASK 0x00018000L
+-#define DCFE1_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK 0x00020000L
+-#define DCFE1_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE_MASK 0x000C0000L
+-#define DCFE1_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS_MASK 0x00100000L
+-#define DCFE1_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE_MASK 0x00600000L
+-#define DCFE1_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS_MASK 0x00800000L
+-#define DCFE1_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE_MASK 0x03000000L
+-#define DCFE1_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS_MASK 0x04000000L
+-#define DCFE1_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE_MASK 0x18000000L
+-#define DCFE1_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS_MASK 0x20000000L
+-//DCFE1_DCFE_MEM_PWR_CTRL2
+-#define DCFE1_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL__SHIFT 0x0
+-#define DCFE1_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2
+-#define DCFE1_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4
+-#define DCFE1_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL__SHIFT 0x6
+-#define DCFE1_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL__SHIFT 0x8
+-#define DCFE1_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL__SHIFT 0xa
+-#define DCFE1_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL__SHIFT 0xc
+-#define DCFE1_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL__SHIFT 0xe
+-#define DCFE1_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE__SHIFT 0x10
+-#define DCFE1_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS__SHIFT 0x12
+-#define DCFE1_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE__SHIFT 0x15
+-#define DCFE1_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS__SHIFT 0x17
+-#define DCFE1_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL_MASK 0x00000003L
+-#define DCFE1_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL_MASK 0x0000000CL
+-#define DCFE1_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL_MASK 0x00000030L
+-#define DCFE1_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL_MASK 0x000000C0L
+-#define DCFE1_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL_MASK 0x00000300L
+-#define DCFE1_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL_MASK 0x00000C00L
+-#define DCFE1_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL_MASK 0x00003000L
+-#define DCFE1_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL_MASK 0x0000C000L
+-#define DCFE1_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE_MASK 0x00030000L
+-#define DCFE1_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS_MASK 0x00040000L
+-#define DCFE1_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE_MASK 0x00600000L
+-#define DCFE1_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS_MASK 0x00800000L
+-//DCFE1_DCFE_MEM_PWR_STATUS
+-#define DCFE1_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE__SHIFT 0x0
+-#define DCFE1_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE__SHIFT 0x2
+-#define DCFE1_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE__SHIFT 0x4
+-#define DCFE1_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x6
+-#define DCFE1_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE__SHIFT 0x8
+-#define DCFE1_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE__SHIFT 0xa
+-#define DCFE1_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE__SHIFT 0xc
+-#define DCFE1_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE__SHIFT 0xe
+-#define DCFE1_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT 0x10
+-#define DCFE1_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE__SHIFT 0x12
+-#define DCFE1_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE__SHIFT 0x14
+-#define DCFE1_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE__SHIFT 0x16
+-#define DCFE1_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK 0x00000003L
+-#define DCFE1_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE_MASK 0x0000000CL
+-#define DCFE1_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE_MASK 0x00000030L
+-#define DCFE1_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE_MASK 0x000000C0L
+-#define DCFE1_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE_MASK 0x00000300L
+-#define DCFE1_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE_MASK 0x00000C00L
+-#define DCFE1_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE_MASK 0x00003000L
+-#define DCFE1_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE_MASK 0x0000C000L
+-#define DCFE1_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE_MASK 0x00030000L
+-#define DCFE1_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK 0x000C0000L
+-#define DCFE1_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE_MASK 0x00300000L
+-#define DCFE1_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE_MASK 0x00C00000L
+-//DCFE1_DCFE_MISC
+-#define DCFE1_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN__SHIFT 0x0
+-#define DCFE1_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN_MASK 0x00000001L
+-//DCFE1_DCFE_FLUSH
+-#define DCFE1_DCFE_FLUSH__FLUSH_OCCURED__SHIFT 0x0
+-#define DCFE1_DCFE_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT 0x1
+-#define DCFE1_DCFE_FLUSH__FLUSH_DEEP__SHIFT 0x2
+-#define DCFE1_DCFE_FLUSH__CLEAR_FLUSH_DEEP__SHIFT 0x3
+-#define DCFE1_DCFE_FLUSH__ALL_MC_REQ_RET__SHIFT 0x4
+-#define DCFE1_DCFE_FLUSH__FLUSH_OCCURED_MASK 0x00000001L
+-#define DCFE1_DCFE_FLUSH__CLEAR_FLUSH_OCCURED_MASK 0x00000002L
+-#define DCFE1_DCFE_FLUSH__FLUSH_DEEP_MASK 0x00000004L
+-#define DCFE1_DCFE_FLUSH__CLEAR_FLUSH_DEEP_MASK 0x00000008L
+-#define DCFE1_DCFE_FLUSH__ALL_MC_REQ_RET_MASK 0x00000010L
+-
+-
+-// addressBlock: dce_dc_dc_perfmon4_dispdec
+-//DC_PERFMON4_PERFCOUNTER_CNTL
+-#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+-#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+-#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+-#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+-#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+-#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
+-#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+-#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+-#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+-#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+-#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+-#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
+-#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+-#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+-#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+-#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+-#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+-#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+-#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
+-#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+-#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+-#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+-#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+-#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+-#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
+-#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+-//DC_PERFMON4_PERFCOUNTER_CNTL2
+-#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+-#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+-#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+-#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+-#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+-#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+-#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+-#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+-//DC_PERFMON4_PERFCOUNTER_STATE
+-#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+-#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+-#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+-#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+-#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+-#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+-#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+-#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+-#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+-#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+-#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+-#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+-#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+-#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+-#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+-#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+-#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+-#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+-#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+-#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+-#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+-#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+-#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+-#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+-#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+-#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+-#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+-#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+-#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+-#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+-#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+-#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+-//DC_PERFMON4_PERFMON_CNTL
+-#define DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+-#define DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+-#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+-#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+-#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+-#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+-#define DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+-#define DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+-#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+-#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+-#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+-#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+-//DC_PERFMON4_PERFMON_CNTL2
+-#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+-#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+-#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+-#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+-#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+-#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+-#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+-#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+-//DC_PERFMON4_PERFMON_CVALUE_INT_MISC
+-#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+-#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+-#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+-#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+-#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+-#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+-#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+-#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+-#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+-#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+-#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+-#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+-#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+-#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+-#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+-#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+-#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+-#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+-#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+-#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+-#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+-#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+-#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+-#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+-#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+-#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+-#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+-#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+-#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+-#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+-#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+-#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+-#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+-#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+-//DC_PERFMON4_PERFMON_CVALUE_LOW
+-#define DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+-#define DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+-//DC_PERFMON4_PERFMON_HI
+-#define DC_PERFMON4_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+-#define DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+-#define DC_PERFMON4_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+-#define DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+-//DC_PERFMON4_PERFMON_LOW
+-#define DC_PERFMON4_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+-#define DC_PERFMON4_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dmif_pg1_dispdec
+-//DMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1
+-#define DMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
+-#define DMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
+-#define DMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0x0000FFFFL
+-#define DMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xFFFF0000L
+-//DMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2
+-#define DMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
+-#define DMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
+-#define DMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0x0000FFFFL
+-#define DMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xFFFF0000L
+-//DMIF_PG1_DPG_WATERMARK_MASK_CONTROL
+-#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
+-#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x4
+-#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
+-#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK__SHIFT 0xc
+-#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0xf
+-#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x12
+-#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL__SHIFT 0x13
+-#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL__SHIFT 0x14
+-#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000007L
+-#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000070L
+-#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x00000700L
+-#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK_MASK 0x00007000L
+-#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00038000L
+-#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x00040000L
+-#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL_MASK 0x00080000L
+-#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL_MASK 0x3FF00000L
+-//DMIF_PG1_DPG_PIPE_URGENCY_CONTROL
+-#define DMIF_PG1_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
+-#define DMIF_PG1_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
+-#define DMIF_PG1_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0x0000FFFFL
+-#define DMIF_PG1_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xFFFF0000L
+-//DMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL
+-#define DMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK__SHIFT 0x0
+-#define DMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK__SHIFT 0x10
+-#define DMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK_MASK 0x0000FFFFL
+-#define DMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK_MASK 0xFFFF0000L
+-//DMIF_PG1_DPG_PIPE_STUTTER_CONTROL
+-#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
+-#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
+-#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
+-#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
+-#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
+-#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
+-#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
+-#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH__SHIFT 0x10
+-#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x14
+-#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x15
+-#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x16
+-#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x17
+-#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0x1a
+-#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0x1b
+-#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L
+-#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L
+-#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x00000020L
+-#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x00000040L
+-#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x00000080L
+-#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x00000400L
+-#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x00000800L
+-#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH_MASK 0x00010000L
+-#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x00100000L
+-#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x00200000L
+-#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x00400000L
+-#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x00800000L
+-#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x04000000L
+-#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x08000000L
+-//DMIF_PG1_DPG_PIPE_STUTTER_CONTROL2
+-#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x0
+-#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK__SHIFT 0x10
+-#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0x0000FFFFL
+-#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK 0xFFFF0000L
+-//DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL
+-#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE__SHIFT 0x0
+-#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE__SHIFT 0x1
+-#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
+-#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
+-#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
+-#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
+-#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK__SHIFT 0xf
+-#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE_MASK 0x00000001L
+-#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE_MASK 0x00000002L
+-#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L
+-#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x00000100L
+-#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON_MASK 0x00000200L
+-#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT_MASK 0x00000400L
+-#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK_MASK 0xFFFF8000L
+-//DMIF_PG1_DPG_REPEATER_PROGRAM
+-#define DMIF_PG1_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
+-#define DMIF_PG1_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
+-#define DMIF_PG1_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x00000007L
+-#define DMIF_PG1_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x00000070L
+-//DMIF_PG1_DPG_CHK_PRE_PROC_CNTL
+-#define DMIF_PG1_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0
+-#define DMIF_PG1_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x00000001L
+-//DMIF_PG1_DPG_DVMM_STATUS
+-#define DMIF_PG1_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED__SHIFT 0x0
+-#define DMIF_PG1_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED__SHIFT 0x1
+-#define DMIF_PG1_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR__SHIFT 0x4
+-#define DMIF_PG1_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR__SHIFT 0x5
+-#define DMIF_PG1_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_MASK 0x00000001L
+-#define DMIF_PG1_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_MASK 0x00000002L
+-#define DMIF_PG1_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR_MASK 0x00000010L
+-#define DMIF_PG1_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR_MASK 0x00000020L
+-
+-
+-// addressBlock: dce_dc_scl1_dispdec
+-//SCL1_SCL_COEF_RAM_SELECT
+-#define SCL1_SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0
+-#define SCL1_SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8
+-#define SCL1_SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10
+-#define SCL1_SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x0000000FL
+-#define SCL1_SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x00000F00L
+-#define SCL1_SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x00070000L
+-//SCL1_SCL_COEF_RAM_TAP_DATA
+-#define SCL1_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0
+-#define SCL1_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
+-#define SCL1_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10
+-#define SCL1_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
+-#define SCL1_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL
+-#define SCL1_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L
+-#define SCL1_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L
+-#define SCL1_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L
+-//SCL1_SCL_MODE
+-#define SCL1_SCL_MODE__SCL_MODE__SHIFT 0x0
+-#define SCL1_SCL_MODE__SCL_PSCL_EN__SHIFT 0x4
+-#define SCL1_SCL_MODE__SCL_MODE_MASK 0x00000003L
+-#define SCL1_SCL_MODE__SCL_PSCL_EN_MASK 0x00000010L
+-//SCL1_SCL_TAP_CONTROL
+-#define SCL1_SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0
+-#define SCL1_SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x8
+-#define SCL1_SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x00000007L
+-#define SCL1_SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0x00000F00L
+-//SCL1_SCL_CONTROL
+-#define SCL1_SCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
+-#define SCL1_SCL_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4
+-#define SCL1_SCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L
+-#define SCL1_SCL_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x00000010L
+-//SCL1_SCL_BYPASS_CONTROL
+-#define SCL1_SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT 0x0
+-#define SCL1_SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x00000003L
+-//SCL1_SCL_MANUAL_REPLICATE_CONTROL
+-#define SCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
+-#define SCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
+-#define SCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL
+-#define SCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L
+-//SCL1_SCL_AUTOMATIC_MODE_CONTROL
+-#define SCL1_SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0
+-#define SCL1_SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10
+-#define SCL1_SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x00000001L
+-#define SCL1_SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x00010000L
+-//SCL1_SCL_HORZ_FILTER_CONTROL
+-#define SCL1_SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT 0x0
+-#define SCL1_SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+-#define SCL1_SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK 0x00000001L
+-#define SCL1_SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
+-//SCL1_SCL_HORZ_FILTER_SCALE_RATIO
+-#define SCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
+-#define SCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL
+-//SCL1_SCL_HORZ_FILTER_INIT
+-#define SCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
+-#define SCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
+-#define SCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL
+-#define SCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L
+-//SCL1_SCL_VERT_FILTER_CONTROL
+-#define SCL1_SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT 0x0
+-#define SCL1_SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+-#define SCL1_SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK 0x00000001L
+-#define SCL1_SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
+-//SCL1_SCL_VERT_FILTER_SCALE_RATIO
+-#define SCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
+-#define SCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL
+-//SCL1_SCL_VERT_FILTER_INIT
+-#define SCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
+-#define SCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
+-#define SCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL
+-#define SCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x07000000L
+-//SCL1_SCL_VERT_FILTER_INIT_BOT
+-#define SCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
+-#define SCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
+-#define SCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL
+-#define SCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x07000000L
+-//SCL1_SCL_ROUND_OFFSET
+-#define SCL1_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0
+-#define SCL1_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10
+-#define SCL1_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0x0000FFFFL
+-#define SCL1_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xFFFF0000L
+-//SCL1_SCL_UPDATE
+-#define SCL1_SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
+-#define SCL1_SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8
+-#define SCL1_SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10
+-#define SCL1_SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18
+-#define SCL1_SCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L
+-#define SCL1_SCL_UPDATE__SCL_UPDATE_TAKEN_MASK 0x00000100L
+-#define SCL1_SCL_UPDATE__SCL_UPDATE_LOCK_MASK 0x00010000L
+-#define SCL1_SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x01000000L
+-//SCL1_SCL_F_SHARP_CONTROL
+-#define SCL1_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT 0x0
+-#define SCL1_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT 0x4
+-#define SCL1_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT 0x8
+-#define SCL1_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT 0xc
+-#define SCL1_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK 0x00000007L
+-#define SCL1_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK 0x00000010L
+-#define SCL1_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK 0x00000700L
+-#define SCL1_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK 0x00001000L
+-//SCL1_SCL_ALU_CONTROL
+-#define SCL1_SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0
+-#define SCL1_SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x00000001L
+-//SCL1_SCL_COEF_RAM_CONFLICT_STATUS
+-#define SCL1_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT 0x0
+-#define SCL1_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT 0x8
+-#define SCL1_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT 0xc
+-#define SCL1_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10
+-#define SCL1_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK 0x00000001L
+-#define SCL1_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK 0x00000100L
+-#define SCL1_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK 0x00001000L
+-#define SCL1_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK 0x00010000L
+-//SCL1_VIEWPORT_START_SECONDARY
+-#define SCL1_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0
+-#define SCL1_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10
+-#define SCL1_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x00003FFFL
+-#define SCL1_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3FFF0000L
+-//SCL1_VIEWPORT_START
+-#define SCL1_VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0
+-#define SCL1_VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10
+-#define SCL1_VIEWPORT_START__VIEWPORT_Y_START_MASK 0x00003FFFL
+-#define SCL1_VIEWPORT_START__VIEWPORT_X_START_MASK 0x3FFF0000L
+-//SCL1_VIEWPORT_SIZE
+-#define SCL1_VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0
+-#define SCL1_VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10
+-#define SCL1_VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x00003FFFL
+-#define SCL1_VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x3FFF0000L
+-//SCL1_EXT_OVERSCAN_LEFT_RIGHT
+-#define SCL1_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
+-#define SCL1_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
+-#define SCL1_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL
+-#define SCL1_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L
+-//SCL1_EXT_OVERSCAN_TOP_BOTTOM
+-#define SCL1_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
+-#define SCL1_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
+-#define SCL1_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL
+-#define SCL1_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L
+-//SCL1_SCL_MODE_CHANGE_DET1
+-#define SCL1_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0
+-#define SCL1_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4
+-#define SCL1_SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7
+-#define SCL1_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x00000001L
+-#define SCL1_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x00000010L
+-#define SCL1_SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0x0FFFFF80L
+-//SCL1_SCL_MODE_CHANGE_DET2
+-#define SCL1_SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0
+-#define SCL1_SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x001FFFFFL
+-//SCL1_SCL_MODE_CHANGE_DET3
+-#define SCL1_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0
+-#define SCL1_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10
+-#define SCL1_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x00003FFFL
+-#define SCL1_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3FFF0000L
+-//SCL1_SCL_MODE_CHANGE_MASK
+-#define SCL1_SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0
+-#define SCL1_SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x00000001L
+-
+-
+-// addressBlock: dce_dc_blnd1_dispdec
+-//BLND1_BLND_CONTROL
+-#define BLND1_BLND_CONTROL__BLND_GLOBAL_GAIN__SHIFT 0x0
+-#define BLND1_BLND_CONTROL__BLND_MODE__SHIFT 0x8
+-#define BLND1_BLND_CONTROL__BLND_STEREO_TYPE__SHIFT 0xa
+-#define BLND1_BLND_CONTROL__BLND_STEREO_POLARITY__SHIFT 0xc
+-#define BLND1_BLND_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT 0xd
+-#define BLND1_BLND_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10
+-#define BLND1_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x12
+-#define BLND1_BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14
+-#define BLND1_BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18
+-#define BLND1_BLND_CONTROL__BLND_GLOBAL_GAIN_MASK 0x000000FFL
+-#define BLND1_BLND_CONTROL__BLND_MODE_MASK 0x00000300L
+-#define BLND1_BLND_CONTROL__BLND_STEREO_TYPE_MASK 0x00000C00L
+-#define BLND1_BLND_CONTROL__BLND_STEREO_POLARITY_MASK 0x00001000L
+-#define BLND1_BLND_CONTROL__BLND_FEEDTHROUGH_EN_MASK 0x00002000L
+-#define BLND1_BLND_CONTROL__BLND_ALPHA_MODE_MASK 0x00030000L
+-#define BLND1_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00040000L
+-#define BLND1_BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x00100000L
+-#define BLND1_BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xFF000000L
+-//BLND1_BLND_SM_CONTROL2
+-#define BLND1_BLND_SM_CONTROL2__SM_MODE__SHIFT 0x0
+-#define BLND1_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4
+-#define BLND1_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5
+-#define BLND1_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
+-#define BLND1_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
+-#define BLND1_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18
+-#define BLND1_BLND_SM_CONTROL2__SM_MODE_MASK 0x00000007L
+-#define BLND1_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x00000010L
+-#define BLND1_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x00000020L
+-#define BLND1_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L
+-#define BLND1_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L
+-#define BLND1_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x01000000L
+-//BLND1_BLND_CONTROL2
+-#define BLND1_BLND_CONTROL2__PTI_ENABLE__SHIFT 0x0
+-#define BLND1_BLND_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT 0x4
+-#define BLND1_BLND_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT 0x6
+-#define BLND1_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT 0x7
+-#define BLND1_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT 0x8
+-#define BLND1_BLND_CONTROL2__PTI_ENABLE_MASK 0x00000001L
+-#define BLND1_BLND_CONTROL2__PTI_NEW_PIXEL_GAP_MASK 0x00000030L
+-#define BLND1_BLND_CONTROL2__BLND_NEW_PIXEL_MODE_MASK 0x00000040L
+-#define BLND1_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK 0x00000080L
+-#define BLND1_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK 0x00000100L
+-//BLND1_BLND_UPDATE
+-#define BLND1_BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0
+-#define BLND1_BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8
+-#define BLND1_BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10
+-#define BLND1_BLND_UPDATE__BLND_UPDATE_PENDING_MASK 0x00000001L
+-#define BLND1_BLND_UPDATE__BLND_UPDATE_TAKEN_MASK 0x00000100L
+-#define BLND1_BLND_UPDATE__BLND_UPDATE_LOCK_MASK 0x00010000L
+-//BLND1_BLND_UNDERFLOW_INTERRUPT
+-#define BLND1_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0
+-#define BLND1_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8
+-#define BLND1_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc
+-#define BLND1_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10
+-#define BLND1_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x00000001L
+-#define BLND1_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x00000100L
+-#define BLND1_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x00001000L
+-#define BLND1_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x00030000L
+-//BLND1_BLND_V_UPDATE_LOCK
+-#define BLND1_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0
+-#define BLND1_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1
+-#define BLND1_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10
+-#define BLND1_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c
+-#define BLND1_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT 0x1d
+-#define BLND1_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT 0x1f
+-#define BLND1_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x00000001L
+-#define BLND1_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x00000002L
+-#define BLND1_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x00010000L
+-#define BLND1_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000L
+-#define BLND1_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK 0x20000000L
+-#define BLND1_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK 0x80000000L
+-//BLND1_BLND_REG_UPDATE_STATUS
+-#define BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT 0x0
+-#define BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT 0x1
+-#define BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2
+-#define BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3
+-#define BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT 0x6
+-#define BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT 0x7
+-#define BLND1_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT 0x8
+-#define BLND1_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT 0x9
+-#define BLND1_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT 0xa
+-#define BLND1_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT 0xb
+-#define BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK 0x00000001L
+-#define BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK 0x00000002L
+-#define BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK 0x00000004L
+-#define BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK 0x00000008L
+-#define BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK 0x00000040L
+-#define BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK 0x00000080L
+-#define BLND1_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK 0x00000100L
+-#define BLND1_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK 0x00000200L
+-#define BLND1_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK 0x00000400L
+-#define BLND1_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK 0x00000800L
+-
+-
+-// addressBlock: dce_dc_crtc1_dispdec
+-//CRTC1_CRTC_H_BLANK_EARLY_NUM
+-#define CRTC1_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0
+-#define CRTC1_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10
+-#define CRTC1_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x000003FFL
+-#define CRTC1_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x00010000L
+-//CRTC1_CRTC_H_TOTAL
+-#define CRTC1_CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0
+-#define CRTC1_CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x00003FFFL
+-//CRTC1_CRTC_H_BLANK_START_END
+-#define CRTC1_CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0
+-#define CRTC1_CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10
+-#define CRTC1_CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x00003FFFL
+-#define CRTC1_CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3FFF0000L
+-//CRTC1_CRTC_H_SYNC_A
+-#define CRTC1_CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0
+-#define CRTC1_CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10
+-#define CRTC1_CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x00003FFFL
+-#define CRTC1_CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3FFF0000L
+-//CRTC1_CRTC_H_SYNC_A_CNTL
+-#define CRTC1_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0
+-#define CRTC1_CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10
+-#define CRTC1_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11
+-#define CRTC1_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x00000001L
+-#define CRTC1_CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x00010000L
+-#define CRTC1_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x00020000L
+-//CRTC1_CRTC_H_SYNC_B
+-#define CRTC1_CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0
+-#define CRTC1_CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10
+-#define CRTC1_CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x00003FFFL
+-#define CRTC1_CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x3FFF0000L
+-//CRTC1_CRTC_H_SYNC_B_CNTL
+-#define CRTC1_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0
+-#define CRTC1_CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10
+-#define CRTC1_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11
+-#define CRTC1_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x00000001L
+-#define CRTC1_CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x00010000L
+-#define CRTC1_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x00020000L
+-//CRTC1_CRTC_VBI_END
+-#define CRTC1_CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x0
+-#define CRTC1_CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x10
+-#define CRTC1_CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x00003FFFL
+-#define CRTC1_CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x3FFF0000L
+-//CRTC1_CRTC_V_TOTAL
+-#define CRTC1_CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0
+-#define CRTC1_CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x00003FFFL
+-//CRTC1_CRTC_V_TOTAL_MIN
+-#define CRTC1_CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0
+-#define CRTC1_CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x00003FFFL
+-//CRTC1_CRTC_V_TOTAL_MAX
+-#define CRTC1_CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0
+-#define CRTC1_CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10
+-#define CRTC1_CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x00003FFFL
+-#define CRTC1_CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x00010000L
+-//CRTC1_CRTC_V_TOTAL_CONTROL
+-#define CRTC1_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0
+-#define CRTC1_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4
+-#define CRTC1_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8
+-#define CRTC1_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc
+-#define CRTC1_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf
+-#define CRTC1_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10
+-#define CRTC1_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x00000001L
+-#define CRTC1_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x00000010L
+-#define CRTC1_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x00000100L
+-#define CRTC1_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x00001000L
+-#define CRTC1_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00008000L
+-#define CRTC1_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L
+-//CRTC1_CRTC_V_TOTAL_INT_STATUS
+-#define CRTC1_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0
+-#define CRTC1_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4
+-#define CRTC1_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8
+-#define CRTC1_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc
+-#define CRTC1_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L
+-#define CRTC1_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L
+-#define CRTC1_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L
+-#define CRTC1_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L
+-//CRTC1_CRTC_VSYNC_NOM_INT_STATUS
+-#define CRTC1_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0
+-#define CRTC1_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4
+-#define CRTC1_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x00000001L
+-#define CRTC1_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L
+-//CRTC1_CRTC_V_BLANK_START_END
+-#define CRTC1_CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0
+-#define CRTC1_CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10
+-#define CRTC1_CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x00003FFFL
+-#define CRTC1_CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3FFF0000L
+-//CRTC1_CRTC_V_SYNC_A
+-#define CRTC1_CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0
+-#define CRTC1_CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10
+-#define CRTC1_CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x00003FFFL
+-#define CRTC1_CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3FFF0000L
+-//CRTC1_CRTC_V_SYNC_A_CNTL
+-#define CRTC1_CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0
+-#define CRTC1_CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x00000001L
+-//CRTC1_CRTC_V_SYNC_B
+-#define CRTC1_CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0
+-#define CRTC1_CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10
+-#define CRTC1_CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x00003FFFL
+-#define CRTC1_CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x3FFF0000L
+-//CRTC1_CRTC_V_SYNC_B_CNTL
+-#define CRTC1_CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0
+-#define CRTC1_CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x00000001L
+-//CRTC1_CRTC_DTMTEST_CNTL
+-#define CRTC1_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0
+-#define CRTC1_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1
+-#define CRTC1_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x00000001L
+-#define CRTC1_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x0000001EL
+-//CRTC1_CRTC_DTMTEST_STATUS_POSITION
+-#define CRTC1_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0
+-#define CRTC1_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10
+-#define CRTC1_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x00003FFFL
+-#define CRTC1_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x3FFF0000L
+-//CRTC1_CRTC_TRIGA_CNTL
+-#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0
+-#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5
+-#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8
+-#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9
+-#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa
+-#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb
+-#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
+-#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
+-#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14
+-#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18
+-#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f
+-#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x0000001FL
+-#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0x000000E0L
+-#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000100L
+-#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x00000200L
+-#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x00000400L
+-#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x00000800L
+-#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
+-#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
+-#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L
+-#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1F000000L
+-#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000L
+-//CRTC1_CRTC_TRIGA_MANUAL_TRIG
+-#define CRTC1_CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0
+-#define CRTC1_CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x00000001L
+-//CRTC1_CRTC_TRIGB_CNTL
+-#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0
+-#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5
+-#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8
+-#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9
+-#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa
+-#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb
+-#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
+-#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
+-#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14
+-#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18
+-#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f
+-#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x0000001FL
+-#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0x000000E0L
+-#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000100L
+-#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x00000200L
+-#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x00000400L
+-#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x00000800L
+-#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
+-#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
+-#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L
+-#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1F000000L
+-#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000L
+-//CRTC1_CRTC_TRIGB_MANUAL_TRIG
+-#define CRTC1_CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0
+-#define CRTC1_CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x00000001L
+-//CRTC1_CRTC_FORCE_COUNT_NOW_CNTL
+-#define CRTC1_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0
+-#define CRTC1_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4
+-#define CRTC1_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8
+-#define CRTC1_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10
+-#define CRTC1_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18
+-#define CRTC1_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x00000003L
+-#define CRTC1_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L
+-#define CRTC1_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L
+-#define CRTC1_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L
+-#define CRTC1_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L
+-//CRTC1_CRTC_FLOW_CONTROL
+-#define CRTC1_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0
+-#define CRTC1_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8
+-#define CRTC1_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10
+-#define CRTC1_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18
+-#define CRTC1_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL
+-#define CRTC1_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x00000100L
+-#define CRTC1_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L
+-#define CRTC1_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L
+-//CRTC1_CRTC_STEREO_FORCE_NEXT_EYE
+-#define CRTC1_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0
+-#define CRTC1_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER__SHIFT 0x8
+-#define CRTC1_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER__SHIFT 0x10
+-#define CRTC1_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L
+-#define CRTC1_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L
+-#define CRTC1_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L
+-//CRTC1_CRTC_AVSYNC_COUNTER
+-#define CRTC1_CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER__SHIFT 0x0
+-#define CRTC1_CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER_MASK 0xFFFFFFFFL
+-//CRTC1_CRTC_CONTROL
+-#define CRTC1_CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x0
+-#define CRTC1_CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4
+-#define CRTC1_CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8
+-#define CRTC1_CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc
+-#define CRTC1_CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd
+-#define CRTC1_CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe
+-#define CRTC1_CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10
+-#define CRTC1_CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14
+-#define CRTC1_CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d
+-#define CRTC1_CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e
+-#define CRTC1_CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f
+-#define CRTC1_CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x00000001L
+-#define CRTC1_CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x00000010L
+-#define CRTC1_CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x00000300L
+-#define CRTC1_CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x00001000L
+-#define CRTC1_CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x00002000L
+-#define CRTC1_CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x00004000L
+-#define CRTC1_CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x00010000L
+-#define CRTC1_CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x00700000L
+-#define CRTC1_CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000L
+-#define CRTC1_CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L
+-#define CRTC1_CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L
+-//CRTC1_CRTC_BLANK_CONTROL
+-#define CRTC1_CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0
+-#define CRTC1_CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8
+-#define CRTC1_CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10
+-#define CRTC1_CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x00000001L
+-#define CRTC1_CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x00000100L
+-#define CRTC1_CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x00010000L
+-//CRTC1_CRTC_INTERLACE_CONTROL
+-#define CRTC1_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0
+-#define CRTC1_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10
+-#define CRTC1_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x00000001L
+-#define CRTC1_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L
+-//CRTC1_CRTC_INTERLACE_STATUS
+-#define CRTC1_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0
+-#define CRTC1_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1
+-#define CRTC1_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x00000001L
+-#define CRTC1_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x00000002L
+-//CRTC1_CRTC_FIELD_INDICATION_CONTROL
+-#define CRTC1_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0
+-#define CRTC1_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1
+-#define CRTC1_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x00000001L
+-#define CRTC1_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x00000002L
+-//CRTC1_CRTC_PIXEL_DATA_READBACK0
+-#define CRTC1_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0
+-#define CRTC1_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10
+-#define CRTC1_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0x00000FFFL
+-#define CRTC1_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0x0FFF0000L
+-//CRTC1_CRTC_PIXEL_DATA_READBACK1
+-#define CRTC1_CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0
+-#define CRTC1_CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0x00000FFFL
+-//CRTC1_CRTC_STATUS
+-#define CRTC1_CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x0
+-#define CRTC1_CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1
+-#define CRTC1_CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x2
+-#define CRTC1_CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x3
+-#define CRTC1_CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x4
+-#define CRTC1_CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5
+-#define CRTC1_CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x10
+-#define CRTC1_CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11
+-#define CRTC1_CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x12
+-#define CRTC1_CRTC_STATUS__CRTC_V_BLANK_MASK 0x00000001L
+-#define CRTC1_CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x00000002L
+-#define CRTC1_CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x00000004L
+-#define CRTC1_CRTC_STATUS__CRTC_V_UPDATE_MASK 0x00000008L
+-#define CRTC1_CRTC_STATUS__CRTC_V_START_LINE_MASK 0x00000010L
+-#define CRTC1_CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x00000020L
+-#define CRTC1_CRTC_STATUS__CRTC_H_BLANK_MASK 0x00010000L
+-#define CRTC1_CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x00020000L
+-#define CRTC1_CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x00040000L
+-//CRTC1_CRTC_STATUS_POSITION
+-#define CRTC1_CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0
+-#define CRTC1_CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10
+-#define CRTC1_CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x00003FFFL
+-#define CRTC1_CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x3FFF0000L
+-//CRTC1_CRTC_NOM_VERT_POSITION
+-#define CRTC1_CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0
+-#define CRTC1_CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x00003FFFL
+-//CRTC1_CRTC_STATUS_FRAME_COUNT
+-#define CRTC1_CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0
+-#define CRTC1_CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0x00FFFFFFL
+-//CRTC1_CRTC_STATUS_VF_COUNT
+-#define CRTC1_CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0
+-#define CRTC1_CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x3FFFFFFFL
+-//CRTC1_CRTC_STATUS_HV_COUNT
+-#define CRTC1_CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0
+-#define CRTC1_CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x3FFFFFFFL
+-//CRTC1_CRTC_COUNT_CONTROL
+-#define CRTC1_CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0
+-#define CRTC1_CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1
+-#define CRTC1_CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x00000001L
+-#define CRTC1_CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x0000001EL
+-//CRTC1_CRTC_COUNT_RESET
+-#define CRTC1_CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0
+-#define CRTC1_CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x00000001L
+-//CRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE
+-#define CRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0
+-#define CRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L
+-//CRTC1_CRTC_VERT_SYNC_CONTROL
+-#define CRTC1_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0
+-#define CRTC1_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8
+-#define CRTC1_CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10
+-#define CRTC1_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L
+-#define CRTC1_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L
+-#define CRTC1_CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L
+-//CRTC1_CRTC_STEREO_STATUS
+-#define CRTC1_CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0
+-#define CRTC1_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8
+-#define CRTC1_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10
+-#define CRTC1_CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG__SHIFT 0x14
+-#define CRTC1_CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18
+-#define CRTC1_CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x00000001L
+-#define CRTC1_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x00000100L
+-#define CRTC1_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x00010000L
+-#define CRTC1_CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG_MASK 0x00100000L
+-#define CRTC1_CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L
+-//CRTC1_CRTC_STEREO_CONTROL
+-#define CRTC1_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0
+-#define CRTC1_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf
+-#define CRTC1_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10
+-#define CRTC1_CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11
+-#define CRTC1_CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12
+-#define CRTC1_CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM__SHIFT 0x13
+-#define CRTC1_CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14
+-#define CRTC1_CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18
+-#define CRTC1_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00003FFFL
+-#define CRTC1_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L
+-#define CRTC1_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x00010000L
+-#define CRTC1_CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L
+-#define CRTC1_CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L
+-#define CRTC1_CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM_MASK 0x00080000L
+-#define CRTC1_CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L
+-#define CRTC1_CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x01000000L
+-//CRTC1_CRTC_SNAPSHOT_STATUS
+-#define CRTC1_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0
+-#define CRTC1_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1
+-#define CRTC1_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2
+-#define CRTC1_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x00000001L
+-#define CRTC1_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x00000002L
+-#define CRTC1_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L
+-//CRTC1_CRTC_SNAPSHOT_CONTROL
+-#define CRTC1_CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0
+-#define CRTC1_CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L
+-//CRTC1_CRTC_SNAPSHOT_POSITION
+-#define CRTC1_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0
+-#define CRTC1_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10
+-#define CRTC1_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x00003FFFL
+-#define CRTC1_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x3FFF0000L
+-//CRTC1_CRTC_SNAPSHOT_FRAME
+-#define CRTC1_CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0
+-#define CRTC1_CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL
+-//CRTC1_CRTC_START_LINE_CONTROL
+-#define CRTC1_CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0
+-#define CRTC1_CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x1
+-#define CRTC1_CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x2
+-#define CRTC1_CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x8
+-#define CRTC1_CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc
+-#define CRTC1_CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x00000001L
+-#define CRTC1_CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x00000002L
+-#define CRTC1_CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x00000004L
+-#define CRTC1_CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x00000100L
+-#define CRTC1_CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0x000FF000L
+-//CRTC1_CRTC_INTERRUPT_CONTROL
+-#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0
+-#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1
+-#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4
+-#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5
+-#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8
+-#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9
+-#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10
+-#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11
+-#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18
+-#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19
+-#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a
+-#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b
+-#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c
+-#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d
+-#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e
+-#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f
+-#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x00000001L
+-#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x00000002L
+-#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x00000010L
+-#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x00000020L
+-#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L
+-#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L
+-#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L
+-#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L
+-#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x01000000L
+-#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x02000000L
+-#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x04000000L
+-#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x08000000L
+-#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000L
+-#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000L
+-#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L
+-#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L
+-//CRTC1_CRTC_UPDATE_LOCK
+-#define CRTC1_CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0
+-#define CRTC1_CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x00000001L
+-//CRTC1_CRTC_DOUBLE_BUFFER_CONTROL
+-#define CRTC1_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0
+-#define CRTC1_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8
+-#define CRTC1_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10
+-#define CRTC1_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18
+-#define CRTC1_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x19
+-#define CRTC1_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x00000001L
+-#define CRTC1_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x00000100L
+-#define CRTC1_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L
+-#define CRTC1_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x01000000L
+-#define CRTC1_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x02000000L
+-//CRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE
+-#define CRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0
+-#define CRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x00000001L
+-//CRTC1_CRTC_TEST_PATTERN_CONTROL
+-#define CRTC1_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0
+-#define CRTC1_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8
+-#define CRTC1_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10
+-#define CRTC1_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18
+-#define CRTC1_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x00000001L
+-#define CRTC1_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x00000700L
+-#define CRTC1_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L
+-#define CRTC1_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xFF000000L
+-//CRTC1_CRTC_TEST_PATTERN_PARAMETERS
+-#define CRTC1_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0
+-#define CRTC1_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4
+-#define CRTC1_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8
+-#define CRTC1_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc
+-#define CRTC1_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10
+-#define CRTC1_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0x0000000FL
+-#define CRTC1_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0x000000F0L
+-#define CRTC1_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0x00000F00L
+-#define CRTC1_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0x0000F000L
+-#define CRTC1_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xFFFF0000L
+-//CRTC1_CRTC_TEST_PATTERN_COLOR
+-#define CRTC1_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0
+-#define CRTC1_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10
+-#define CRTC1_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0x0000FFFFL
+-#define CRTC1_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x003F0000L
+-//CRTC1_CRTC_MASTER_UPDATE_LOCK
+-#define CRTC1_CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0
+-#define CRTC1_CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8
+-#define CRTC1_CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK__SHIFT 0x10
+-#define CRTC1_CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x00000001L
+-#define CRTC1_CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x00000100L
+-#define CRTC1_CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK_MASK 0x00010000L
+-//CRTC1_CRTC_MASTER_UPDATE_MODE
+-#define CRTC1_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0
+-#define CRTC1_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10
+-#define CRTC1_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x00000007L
+-#define CRTC1_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00030000L
+-//CRTC1_CRTC_MVP_INBAND_CNTL_INSERT
+-#define CRTC1_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0
+-#define CRTC1_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8
+-#define CRTC1_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x00000003L
+-#define CRTC1_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xFFFFFF00L
+-//CRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER
+-#define CRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0
+-#define CRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0x000000FFL
+-//CRTC1_CRTC_MVP_STATUS
+-#define CRTC1_CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0
+-#define CRTC1_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4
+-#define CRTC1_CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10
+-#define CRTC1_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14
+-#define CRTC1_CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x00000001L
+-#define CRTC1_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x00000010L
+-#define CRTC1_CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x00010000L
+-#define CRTC1_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x00100000L
+-//CRTC1_CRTC_MASTER_EN
+-#define CRTC1_CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0
+-#define CRTC1_CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x00000001L
+-//CRTC1_CRTC_ALLOW_STOP_OFF_V_CNT
+-#define CRTC1_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0
+-#define CRTC1_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10
+-#define CRTC1_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0x000000FFL
+-#define CRTC1_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x00010000L
+-//CRTC1_CRTC_V_UPDATE_INT_STATUS
+-#define CRTC1_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0
+-#define CRTC1_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8
+-#define CRTC1_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x00000001L
+-#define CRTC1_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x00000100L
+-//CRTC1_CRTC_OVERSCAN_COLOR
+-#define CRTC1_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0
+-#define CRTC1_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa
+-#define CRTC1_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14
+-#define CRTC1_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x000003FFL
+-#define CRTC1_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0x000FFC00L
+-#define CRTC1_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3FF00000L
+-//CRTC1_CRTC_OVERSCAN_COLOR_EXT
+-#define CRTC1_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0
+-#define CRTC1_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8
+-#define CRTC1_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10
+-#define CRTC1_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x00000003L
+-#define CRTC1_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x00000300L
+-#define CRTC1_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x00030000L
+-//CRTC1_CRTC_BLANK_DATA_COLOR
+-#define CRTC1_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0
+-#define CRTC1_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa
+-#define CRTC1_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14
+-#define CRTC1_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL
+-#define CRTC1_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L
+-#define CRTC1_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L
+-//CRTC1_CRTC_BLANK_DATA_COLOR_EXT
+-#define CRTC1_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0
+-#define CRTC1_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8
+-#define CRTC1_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10
+-#define CRTC1_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x00000003L
+-#define CRTC1_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00000300L
+-#define CRTC1_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x00030000L
+-//CRTC1_CRTC_BLACK_COLOR
+-#define CRTC1_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0
+-#define CRTC1_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa
+-#define CRTC1_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14
+-#define CRTC1_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x000003FFL
+-#define CRTC1_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0x000FFC00L
+-#define CRTC1_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3FF00000L
+-//CRTC1_CRTC_BLACK_COLOR_EXT
+-#define CRTC1_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0
+-#define CRTC1_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8
+-#define CRTC1_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10
+-#define CRTC1_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x00000003L
+-#define CRTC1_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x00000300L
+-#define CRTC1_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x00030000L
+-//CRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION
+-#define CRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0
+-#define CRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10
+-#define CRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00003FFFL
+-#define CRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x3FFF0000L
+-//CRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL
+-#define CRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4
+-#define CRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8
+-#define CRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc
+-#define CRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10
+-#define CRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14
+-#define CRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18
+-#define CRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L
+-#define CRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L
+-#define CRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L
+-#define CRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L
+-#define CRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L
+-#define CRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L
+-//CRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION
+-#define CRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0
+-#define CRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00003FFFL
+-//CRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL
+-#define CRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8
+-#define CRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc
+-#define CRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10
+-#define CRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14
+-#define CRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18
+-#define CRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L
+-#define CRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L
+-#define CRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L
+-#define CRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L
+-#define CRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L
+-//CRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION
+-#define CRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0
+-#define CRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00003FFFL
+-//CRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL
+-#define CRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8
+-#define CRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc
+-#define CRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10
+-#define CRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14
+-#define CRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18
+-#define CRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L
+-#define CRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L
+-#define CRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L
+-#define CRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L
+-#define CRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L
+-//CRTC1_CRTC_CRC_CNTL
+-#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0
+-#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4
+-#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8
+-#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc
+-#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
+-#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14
+-#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18
+-#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC_EN_MASK 0x00000001L
+-#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x00000010L
+-#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x00000300L
+-#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x00003000L
+-#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
+-#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x00700000L
+-#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x07000000L
+-//CRTC1_CRTC_CRC0_WINDOWA_X_CONTROL
+-#define CRTC1_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0
+-#define CRTC1_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10
+-#define CRTC1_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x00003FFFL
+-#define CRTC1_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3FFF0000L
+-//CRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL
+-#define CRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0
+-#define CRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10
+-#define CRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x00003FFFL
+-#define CRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3FFF0000L
+-//CRTC1_CRTC_CRC0_WINDOWB_X_CONTROL
+-#define CRTC1_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0
+-#define CRTC1_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10
+-#define CRTC1_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x00003FFFL
+-#define CRTC1_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3FFF0000L
+-//CRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL
+-#define CRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0
+-#define CRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10
+-#define CRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x00003FFFL
+-#define CRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3FFF0000L
+-//CRTC1_CRTC_CRC0_DATA_RG
+-#define CRTC1_CRTC_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0
+-#define CRTC1_CRTC_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10
+-#define CRTC1_CRTC_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL
+-#define CRTC1_CRTC_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L
+-//CRTC1_CRTC_CRC0_DATA_B
+-#define CRTC1_CRTC_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0
+-#define CRTC1_CRTC_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL
+-//CRTC1_CRTC_CRC1_WINDOWA_X_CONTROL
+-#define CRTC1_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0
+-#define CRTC1_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10
+-#define CRTC1_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x00003FFFL
+-#define CRTC1_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3FFF0000L
+-//CRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL
+-#define CRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0
+-#define CRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10
+-#define CRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x00003FFFL
+-#define CRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3FFF0000L
+-//CRTC1_CRTC_CRC1_WINDOWB_X_CONTROL
+-#define CRTC1_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0
+-#define CRTC1_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10
+-#define CRTC1_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x00003FFFL
+-#define CRTC1_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3FFF0000L
+-//CRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL
+-#define CRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0
+-#define CRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10
+-#define CRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x00003FFFL
+-#define CRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3FFF0000L
+-//CRTC1_CRTC_CRC1_DATA_RG
+-#define CRTC1_CRTC_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0
+-#define CRTC1_CRTC_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10
+-#define CRTC1_CRTC_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL
+-#define CRTC1_CRTC_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L
+-//CRTC1_CRTC_CRC1_DATA_B
+-#define CRTC1_CRTC_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0
+-#define CRTC1_CRTC_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL
+-//CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE__SHIFT 0x0
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__SHIFT 0x3
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__SHIFT 0x4
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__SHIFT 0x5
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__SHIFT 0x8
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__SHIFT 0x9
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__SHIFT 0xc
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__SHIFT 0xd
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__SHIFT 0xe
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE__SHIFT 0x18
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE__SHIFT 0x1c
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE_MASK 0x00000003L
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_MASK 0x00000008L
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_MASK 0x00000010L
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_MASK 0x00000060L
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_MASK 0x00000100L
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_MASK 0x00000200L
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_MASK 0x00001000L
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_MASK 0x00002000L
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_MASK 0x00004000L
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE_MASK 0x07000000L
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE_MASK 0x70000000L
+-//CRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X__SHIFT 0x0
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y__SHIFT 0x10
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X_MASK 0x00003FFFL
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y_MASK 0x3FFF0000L
+-//CRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X__SHIFT 0x0
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y__SHIFT 0x10
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X_MASK 0x00003FFFL
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y_MASK 0x3FFF0000L
+-//CRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__SHIFT 0x0
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS__SHIFT 0x4
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS__SHIFT 0x8
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__SHIFT 0x10
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__SHIFT 0x14
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__SHIFT 0x1d
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_MASK 0x00000001L
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS_MASK 0x00000010L
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS_MASK 0x00000100L
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_MASK 0x00010000L
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_MASK 0x00100000L
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_MASK 0xE0000000L
+-//CRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE__SHIFT 0x0
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS__SHIFT 0x4
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS__SHIFT 0x8
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR__SHIFT 0x10
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE__SHIFT 0x14
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE_MASK 0x00000001L
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS_MASK 0x00000010L
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS_MASK 0x00000100L
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR_MASK 0x00010000L
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE_MASK 0x00100000L
+-//CRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__SHIFT 0x0
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS__SHIFT 0x4
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS__SHIFT 0x8
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__SHIFT 0x10
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__SHIFT 0x14
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_MASK 0x00000001L
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS_MASK 0x00000010L
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS_MASK 0x00000100L
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_MASK 0x00010000L
+-#define CRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_MASK 0x00100000L
+-//CRTC1_CRTC_STATIC_SCREEN_CONTROL
+-#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0
+-#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10
+-#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18
+-#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19
+-#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a
+-#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b
+-#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c
+-#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e
+-#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f
+-#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL
+-#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L
+-#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x01000000L
+-#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x02000000L
+-#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x04000000L
+-#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x08000000L
+-#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000L
+-#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L
+-#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L
+-//CRTC1_CRTC_3D_STRUCTURE_CONTROL
+-#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0
+-#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4
+-#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8
+-#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc
+-#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10
+-#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11
+-#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12
+-#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x00000001L
+-#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x00000010L
+-#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L
+-#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L
+-#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L
+-#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L
+-#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L
+-//CRTC1_CRTC_GSL_VSYNC_GAP
+-#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0
+-#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8
+-#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10
+-#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11
+-#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13
+-#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14
+-#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17
+-#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18
+-#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL
+-#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L
+-#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L
+-#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x00060000L
+-#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L
+-#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L
+-#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L
+-#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xFF000000L
+-//CRTC1_CRTC_GSL_WINDOW
+-#define CRTC1_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0
+-#define CRTC1_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10
+-#define CRTC1_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x00003FFFL
+-#define CRTC1_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x3FFF0000L
+-//CRTC1_CRTC_GSL_CONTROL
+-#define CRTC1_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0
+-#define CRTC1_CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10
+-#define CRTC1_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c
+-#define CRTC1_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x00003FFFL
+-#define CRTC1_CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x001F0000L
+-#define CRTC1_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L
+-//CRTC1_CRTC_RANGE_TIMING_INT_STATUS
+-#define CRTC1_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0
+-#define CRTC1_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4
+-#define CRTC1_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8
+-#define CRTC1_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc
+-#define CRTC1_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10
+-#define CRTC1_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L
+-#define CRTC1_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L
+-#define CRTC1_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L
+-#define CRTC1_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L
+-#define CRTC1_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L
+-//CRTC1_CRTC_DRR_CONTROL
+-#define CRTC1_CRTC_DRR_CONTROL__CRTC_XDMA_PREFETCH_DELAY__SHIFT 0x0
+-#define CRTC1_CRTC_DRR_CONTROL__CRTC_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0xe
+-#define CRTC1_CRTC_DRR_CONTROL__CRTC_SET_V_TOTAL_MIN_AUTO_DIS__SHIFT 0x1c
+-#define CRTC1_CRTC_DRR_CONTROL__CRTC_DRR_MODE_DBUF_UPDATE_MODE__SHIFT 0x1d
+-#define CRTC1_CRTC_DRR_CONTROL__CRTC_XDMA_PREFETCH_DELAY_MASK 0x00003FFFL
+-#define CRTC1_CRTC_DRR_CONTROL__CRTC_V_TOTAL_LAST_USED_BY_DRR_MASK 0x0FFFC000L
+-#define CRTC1_CRTC_DRR_CONTROL__CRTC_SET_V_TOTAL_MIN_AUTO_DIS_MASK 0x10000000L
+-#define CRTC1_CRTC_DRR_CONTROL__CRTC_DRR_MODE_DBUF_UPDATE_MODE_MASK 0x60000000L
+-
+-
+-// addressBlock: dce_dc_fmt1_dispdec
+-//FMT1_FMT_CLAMP_COMPONENT_R
+-#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0
+-#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10
+-#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL
+-#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L
+-//FMT1_FMT_CLAMP_COMPONENT_G
+-#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0
+-#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10
+-#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL
+-#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L
+-//FMT1_FMT_CLAMP_COMPONENT_B
+-#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0
+-#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10
+-#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL
+-#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L
+-//FMT1_FMT_DYNAMIC_EXP_CNTL
+-#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0
+-#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4
+-#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L
+-#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L
+-//FMT1_FMT_CONTROL
+-#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0
+-#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT 0x4
+-#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8
+-#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc
+-#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10
+-#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12
+-#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14
+-#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15
+-#define FMT1_FMT_CONTROL__FMT_SRC_SELECT__SHIFT 0x18
+-#define FMT1_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED__SHIFT 0x1e
+-#define FMT1_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_CLEAR__SHIFT 0x1f
+-#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L
+-#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK 0x00000010L
+-#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L
+-#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L
+-#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L
+-#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L
+-#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L
+-#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L
+-#define FMT1_FMT_CONTROL__FMT_SRC_SELECT_MASK 0x07000000L
+-#define FMT1_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_MASK 0x40000000L
+-#define FMT1_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_CLEAR_MASK 0x80000000L
+-//FMT1_FMT_BIT_DEPTH_CONTROL
+-#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0
+-#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1
+-#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4
+-#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8
+-#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9
+-#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb
+-#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd
+-#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe
+-#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf
+-#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10
+-#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11
+-#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15
+-#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18
+-#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19
+-#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a
+-#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c
+-#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e
+-#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L
+-#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L
+-#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L
+-#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L
+-#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L
+-#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L
+-#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L
+-#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L
+-#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L
+-#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L
+-#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L
+-#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L
+-#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L
+-#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L
+-#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L
+-#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L
+-#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L
+-//FMT1_FMT_DITHER_RAND_R_SEED
+-#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0
+-#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10
+-#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL
+-#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L
+-//FMT1_FMT_DITHER_RAND_G_SEED
+-#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0
+-#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10
+-#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL
+-#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L
+-//FMT1_FMT_DITHER_RAND_B_SEED
+-#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0
+-#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10
+-#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL
+-#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L
+-//FMT1_FMT_CLAMP_CNTL
+-#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0
+-#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10
+-#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L
+-#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L
+-//FMT1_FMT_CRC_CNTL
+-#define FMT1_FMT_CRC_CNTL__FMT_CRC_EN__SHIFT 0x0
+-#define FMT1_FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN__SHIFT 0x1
+-#define FMT1_FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT 0x4
+-#define FMT1_FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING__SHIFT 0x5
+-#define FMT1_FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN__SHIFT 0x6
+-#define FMT1_FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB__SHIFT 0x8
+-#define FMT1_FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE__SHIFT 0x9
+-#define FMT1_FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT 0xc
+-#define FMT1_FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
+-#define FMT1_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT 0x14
+-#define FMT1_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT 0x18
+-#define FMT1_FMT_CRC_CNTL__FMT_CRC_EN_MASK 0x00000001L
+-#define FMT1_FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN_MASK 0x00000002L
+-#define FMT1_FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK 0x00000010L
+-#define FMT1_FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING_MASK 0x00000020L
+-#define FMT1_FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN_MASK 0x00000040L
+-#define FMT1_FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB_MASK 0x00000100L
+-#define FMT1_FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE_MASK 0x00000200L
+-#define FMT1_FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK 0x00003000L
+-#define FMT1_FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
+-#define FMT1_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK 0x00100000L
+-#define FMT1_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK 0x01000000L
+-//FMT1_FMT_CRC_SIG_RED_GREEN_MASK
+-#define FMT1_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT 0x0
+-#define FMT1_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT 0x10
+-#define FMT1_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK 0x0000FFFFL
+-#define FMT1_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L
+-//FMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK
+-#define FMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT 0x0
+-#define FMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT 0x10
+-#define FMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL
+-#define FMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L
+-//FMT1_FMT_CRC_SIG_RED_GREEN
+-#define FMT1_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT 0x0
+-#define FMT1_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT 0x10
+-#define FMT1_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK 0x0000FFFFL
+-#define FMT1_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK 0xFFFF0000L
+-//FMT1_FMT_CRC_SIG_BLUE_CONTROL
+-#define FMT1_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT 0x0
+-#define FMT1_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT 0x10
+-#define FMT1_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK 0x0000FFFFL
+-#define FMT1_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK 0xFFFF0000L
+-//FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+-#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0
+-#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL
+-//FMT1_FMT_420_HBLANK_EARLY_START
+-#define FMT1_FMT_420_HBLANK_EARLY_START__FMT_420_HBLANK_EARLY_START__SHIFT 0x0
+-#define FMT1_FMT_420_HBLANK_EARLY_START__FMT_420_HBLANK_EARLY_START_MASK 0x00000FFFL
+-
+-
+-// addressBlock: dce_dc_dcp2_dispdec
+-//DCP2_GRPH_ENABLE
+-#define DCP2_GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0
+-#define DCP2_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL__SHIFT 0x1
+-#define DCP2_GRPH_ENABLE__GRPH_ENABLE_MASK 0x00000001L
+-#define DCP2_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL_MASK 0x00000002L
+-//DCP2_GRPH_CONTROL
+-#define DCP2_GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0
+-#define DCP2_GRPH_CONTROL__GRPH_SE_ENABLE__SHIFT 0x2
+-#define DCP2_GRPH_CONTROL__GRPH_Z__SHIFT 0x4
+-#define DCP2_GRPH_CONTROL__GRPH_DIM_TYPE__SHIFT 0x6
+-#define DCP2_GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8
+-#define DCP2_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0xc
+-#define DCP2_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10
+-#define DCP2_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11
+-#define DCP2_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES__SHIFT 0x12
+-#define DCP2_GRPH_CONTROL__GRPH_SW_MODE__SHIFT 0x14
+-#define DCP2_GRPH_CONTROL__GRPH_NUM_PIPES__SHIFT 0x1c
+-#define DCP2_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f
+-#define DCP2_GRPH_CONTROL__GRPH_DEPTH_MASK 0x00000003L
+-#define DCP2_GRPH_CONTROL__GRPH_SE_ENABLE_MASK 0x00000004L
+-#define DCP2_GRPH_CONTROL__GRPH_Z_MASK 0x00000030L
+-#define DCP2_GRPH_CONTROL__GRPH_DIM_TYPE_MASK 0x000000C0L
+-#define DCP2_GRPH_CONTROL__GRPH_FORMAT_MASK 0x00000700L
+-#define DCP2_GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0x00007000L
+-#define DCP2_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x00010000L
+-#define DCP2_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x00020000L
+-#define DCP2_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES_MASK 0x000C0000L
+-#define DCP2_GRPH_CONTROL__GRPH_SW_MODE_MASK 0x01F00000L
+-#define DCP2_GRPH_CONTROL__GRPH_NUM_PIPES_MASK 0x70000000L
+-#define DCP2_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000L
+-//DCP2_GRPH_LUT_10BIT_BYPASS
+-#define DCP2_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT 0x8
+-#define DCP2_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x10
+-#define DCP2_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK 0x00000100L
+-#define DCP2_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x00010000L
+-//DCP2_GRPH_SWAP_CNTL
+-#define DCP2_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0
+-#define DCP2_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4
+-#define DCP2_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6
+-#define DCP2_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8
+-#define DCP2_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT 0xa
+-#define DCP2_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x00000003L
+-#define DCP2_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x00000030L
+-#define DCP2_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0x000000C0L
+-#define DCP2_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x00000300L
+-#define DCP2_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK 0x00000C00L
+-//DCP2_GRPH_PRIMARY_SURFACE_ADDRESS
+-#define DCP2_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT 0x0
+-#define DCP2_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT 0x8
+-#define DCP2_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK 0x00000001L
+-#define DCP2_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+-//DCP2_GRPH_SECONDARY_SURFACE_ADDRESS
+-#define DCP2_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT 0x0
+-#define DCP2_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8
+-#define DCP2_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK 0x00000001L
+-#define DCP2_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+-//DCP2_GRPH_PITCH
+-#define DCP2_GRPH_PITCH__GRPH_PITCH__SHIFT 0x0
+-#define DCP2_GRPH_PITCH__GRPH_PITCH_MASK 0x00007FFFL
+-//DCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+-#define DCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+-#define DCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+-//DCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+-#define DCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+-#define DCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+-//DCP2_GRPH_SURFACE_OFFSET_X
+-#define DCP2_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT 0x0
+-#define DCP2_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK 0x00003FFFL
+-//DCP2_GRPH_SURFACE_OFFSET_Y
+-#define DCP2_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT 0x0
+-#define DCP2_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK 0x00003FFFL
+-//DCP2_GRPH_X_START
+-#define DCP2_GRPH_X_START__GRPH_X_START__SHIFT 0x0
+-#define DCP2_GRPH_X_START__GRPH_X_START_MASK 0x00003FFFL
+-//DCP2_GRPH_Y_START
+-#define DCP2_GRPH_Y_START__GRPH_Y_START__SHIFT 0x0
+-#define DCP2_GRPH_Y_START__GRPH_Y_START_MASK 0x00003FFFL
+-//DCP2_GRPH_X_END
+-#define DCP2_GRPH_X_END__GRPH_X_END__SHIFT 0x0
+-#define DCP2_GRPH_X_END__GRPH_X_END_MASK 0x00007FFFL
+-//DCP2_GRPH_Y_END
+-#define DCP2_GRPH_Y_END__GRPH_Y_END__SHIFT 0x0
+-#define DCP2_GRPH_Y_END__GRPH_Y_END_MASK 0x00007FFFL
+-//DCP2_INPUT_GAMMA_CONTROL
+-#define DCP2_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x0
+-#define DCP2_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK 0x00000001L
+-//DCP2_GRPH_UPDATE
+-#define DCP2_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0
+-#define DCP2_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1
+-#define DCP2_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2
+-#define DCP2_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3
+-#define DCP2_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR__SHIFT 0x8
+-#define DCP2_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE__SHIFT 0x9
+-#define DCP2_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE__SHIFT 0xa
+-#define DCP2_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10
+-#define DCP2_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14
+-#define DCP2_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+-#define DCP2_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c
+-#define DCP2_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x00000001L
+-#define DCP2_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x00000002L
+-#define DCP2_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x00000004L
+-#define DCP2_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x00000008L
+-#define DCP2_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR_MASK 0x00000100L
+-#define DCP2_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE_MASK 0x00000200L
+-#define DCP2_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE_MASK 0x00000400L
+-#define DCP2_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x00010000L
+-#define DCP2_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x00100000L
+-#define DCP2_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
+-#define DCP2_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000L
+-//DCP2_GRPH_FLIP_CONTROL
+-#define DCP2_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT 0x0
+-#define DCP2_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN__SHIFT 0x1
+-#define DCP2_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN__SHIFT 0x4
+-#define DCP2_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT 0x5
+-#define DCP2_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK 0x00000001L
+-#define DCP2_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN_MASK 0x00000002L
+-#define DCP2_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN_MASK 0x00000010L
+-#define DCP2_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK 0x00000020L
+-//DCP2_GRPH_SURFACE_ADDRESS_INUSE
+-#define DCP2_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT 0x8
+-#define DCP2_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK 0xFFFFFF00L
+-//DCP2_GRPH_DFQ_CONTROL
+-#define DCP2_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x0
+-#define DCP2_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x4
+-#define DCP2_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8
+-#define DCP2_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x00000001L
+-#define DCP2_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x00000070L
+-#define DCP2_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x00000700L
+-//DCP2_GRPH_DFQ_STATUS
+-#define DCP2_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x0
+-#define DCP2_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4
+-#define DCP2_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x8
+-#define DCP2_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x9
+-#define DCP2_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0x0000000FL
+-#define DCP2_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0x000000F0L
+-#define DCP2_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x00000100L
+-#define DCP2_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x00000200L
+-//DCP2_GRPH_INTERRUPT_STATUS
+-#define DCP2_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0
+-#define DCP2_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8
+-#define DCP2_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x00000001L
+-#define DCP2_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x00000100L
+-//DCP2_GRPH_INTERRUPT_CONTROL
+-#define DCP2_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0
+-#define DCP2_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8
+-#define DCP2_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x00000001L
+-#define DCP2_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x00000100L
+-//DCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE
+-#define DCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0
+-#define DCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK 0x000000FFL
+-//DCP2_GRPH_COMPRESS_SURFACE_ADDRESS
+-#define DCP2_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT 0x8
+-#define DCP2_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+-//DCP2_GRPH_COMPRESS_PITCH
+-#define DCP2_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT 0x6
+-#define DCP2_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK 0x0001FFC0L
+-//DCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH
+-#define DCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+-#define DCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+-//DCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT
+-#define DCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__SHIFT 0x0
+-#define DCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_MASK 0x000000FFL
+-//DCP2_PRESCALE_GRPH_CONTROL
+-#define DCP2_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT 0x0
+-#define DCP2_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT 0x1
+-#define DCP2_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x2
+-#define DCP2_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT 0x3
+-#define DCP2_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT 0x4
+-#define DCP2_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK 0x00000001L
+-#define DCP2_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x00000002L
+-#define DCP2_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK 0x00000004L
+-#define DCP2_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK 0x00000008L
+-#define DCP2_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK 0x00000010L
+-//DCP2_PRESCALE_VALUES_GRPH_R
+-#define DCP2_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT 0x0
+-#define DCP2_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT 0x10
+-#define DCP2_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK 0x0000FFFFL
+-#define DCP2_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK 0xFFFF0000L
+-//DCP2_PRESCALE_VALUES_GRPH_G
+-#define DCP2_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT 0x0
+-#define DCP2_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT 0x10
+-#define DCP2_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK 0x0000FFFFL
+-#define DCP2_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK 0xFFFF0000L
+-//DCP2_PRESCALE_VALUES_GRPH_B
+-#define DCP2_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT 0x0
+-#define DCP2_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT 0x10
+-#define DCP2_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK 0x0000FFFFL
+-#define DCP2_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK 0xFFFF0000L
+-//DCP2_INPUT_CSC_CONTROL
+-#define DCP2_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT 0x0
+-#define DCP2_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK 0x00000003L
+-//DCP2_INPUT_CSC_C11_C12
+-#define DCP2_INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT 0x0
+-#define DCP2_INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT 0x10
+-#define DCP2_INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK 0x0000FFFFL
+-#define DCP2_INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK 0xFFFF0000L
+-//DCP2_INPUT_CSC_C13_C14
+-#define DCP2_INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT 0x0
+-#define DCP2_INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT 0x10
+-#define DCP2_INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK 0x0000FFFFL
+-#define DCP2_INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK 0xFFFF0000L
+-//DCP2_INPUT_CSC_C21_C22
+-#define DCP2_INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT 0x0
+-#define DCP2_INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT 0x10
+-#define DCP2_INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK 0x0000FFFFL
+-#define DCP2_INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK 0xFFFF0000L
+-//DCP2_INPUT_CSC_C23_C24
+-#define DCP2_INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT 0x0
+-#define DCP2_INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT 0x10
+-#define DCP2_INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK 0x0000FFFFL
+-#define DCP2_INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK 0xFFFF0000L
+-//DCP2_INPUT_CSC_C31_C32
+-#define DCP2_INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT 0x0
+-#define DCP2_INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT 0x10
+-#define DCP2_INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK 0x0000FFFFL
+-#define DCP2_INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK 0xFFFF0000L
+-//DCP2_INPUT_CSC_C33_C34
+-#define DCP2_INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT 0x0
+-#define DCP2_INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT 0x10
+-#define DCP2_INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK 0x0000FFFFL
+-#define DCP2_INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK 0xFFFF0000L
+-//DCP2_OUTPUT_CSC_CONTROL
+-#define DCP2_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT 0x0
+-#define DCP2_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK 0x00000007L
+-//DCP2_OUTPUT_CSC_C11_C12
+-#define DCP2_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT 0x0
+-#define DCP2_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT 0x10
+-#define DCP2_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK 0x0000FFFFL
+-#define DCP2_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK 0xFFFF0000L
+-//DCP2_OUTPUT_CSC_C13_C14
+-#define DCP2_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT 0x0
+-#define DCP2_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT 0x10
+-#define DCP2_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK 0x0000FFFFL
+-#define DCP2_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK 0xFFFF0000L
+-//DCP2_OUTPUT_CSC_C21_C22
+-#define DCP2_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT 0x0
+-#define DCP2_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT 0x10
+-#define DCP2_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK 0x0000FFFFL
+-#define DCP2_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK 0xFFFF0000L
+-//DCP2_OUTPUT_CSC_C23_C24
+-#define DCP2_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT 0x0
+-#define DCP2_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT 0x10
+-#define DCP2_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK 0x0000FFFFL
+-#define DCP2_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK 0xFFFF0000L
+-//DCP2_OUTPUT_CSC_C31_C32
+-#define DCP2_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT 0x0
+-#define DCP2_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT 0x10
+-#define DCP2_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK 0x0000FFFFL
+-#define DCP2_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK 0xFFFF0000L
+-//DCP2_OUTPUT_CSC_C33_C34
+-#define DCP2_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT 0x0
+-#define DCP2_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT 0x10
+-#define DCP2_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK 0x0000FFFFL
+-#define DCP2_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK 0xFFFF0000L
+-//DCP2_COMM_MATRIXA_TRANS_C11_C12
+-#define DCP2_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT 0x0
+-#define DCP2_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT 0x10
+-#define DCP2_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK 0x0000FFFFL
+-#define DCP2_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK 0xFFFF0000L
+-//DCP2_COMM_MATRIXA_TRANS_C13_C14
+-#define DCP2_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT 0x0
+-#define DCP2_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT 0x10
+-#define DCP2_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK 0x0000FFFFL
+-#define DCP2_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK 0xFFFF0000L
+-//DCP2_COMM_MATRIXA_TRANS_C21_C22
+-#define DCP2_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT 0x0
+-#define DCP2_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT 0x10
+-#define DCP2_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK 0x0000FFFFL
+-#define DCP2_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK 0xFFFF0000L
+-//DCP2_COMM_MATRIXA_TRANS_C23_C24
+-#define DCP2_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT 0x0
+-#define DCP2_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT 0x10
+-#define DCP2_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK 0x0000FFFFL
+-#define DCP2_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK 0xFFFF0000L
+-//DCP2_COMM_MATRIXA_TRANS_C31_C32
+-#define DCP2_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT 0x0
+-#define DCP2_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT 0x10
+-#define DCP2_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK 0x0000FFFFL
+-#define DCP2_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK 0xFFFF0000L
+-//DCP2_COMM_MATRIXA_TRANS_C33_C34
+-#define DCP2_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT 0x0
+-#define DCP2_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT 0x10
+-#define DCP2_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK 0x0000FFFFL
+-#define DCP2_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK 0xFFFF0000L
+-//DCP2_COMM_MATRIXB_TRANS_C11_C12
+-#define DCP2_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT 0x0
+-#define DCP2_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT 0x10
+-#define DCP2_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK 0x0000FFFFL
+-#define DCP2_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK 0xFFFF0000L
+-//DCP2_COMM_MATRIXB_TRANS_C13_C14
+-#define DCP2_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT 0x0
+-#define DCP2_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT 0x10
+-#define DCP2_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK 0x0000FFFFL
+-#define DCP2_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK 0xFFFF0000L
+-//DCP2_COMM_MATRIXB_TRANS_C21_C22
+-#define DCP2_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT 0x0
+-#define DCP2_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT 0x10
+-#define DCP2_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK 0x0000FFFFL
+-#define DCP2_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK 0xFFFF0000L
+-//DCP2_COMM_MATRIXB_TRANS_C23_C24
+-#define DCP2_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT 0x0
+-#define DCP2_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT 0x10
+-#define DCP2_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK 0x0000FFFFL
+-#define DCP2_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK 0xFFFF0000L
+-//DCP2_COMM_MATRIXB_TRANS_C31_C32
+-#define DCP2_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT 0x0
+-#define DCP2_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT 0x10
+-#define DCP2_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK 0x0000FFFFL
+-#define DCP2_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK 0xFFFF0000L
+-//DCP2_COMM_MATRIXB_TRANS_C33_C34
+-#define DCP2_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT 0x0
+-#define DCP2_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT 0x10
+-#define DCP2_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK 0x0000FFFFL
+-#define DCP2_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK 0xFFFF0000L
+-//DCP2_DENORM_CONTROL
+-#define DCP2_DENORM_CONTROL__DENORM_MODE__SHIFT 0x0
+-#define DCP2_DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT 0x4
+-#define DCP2_DENORM_CONTROL__DENORM_MODE_MASK 0x00000007L
+-#define DCP2_DENORM_CONTROL__DENORM_14BIT_OUT_MASK 0x00000010L
+-//DCP2_OUT_ROUND_CONTROL
+-#define DCP2_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT 0x0
+-#define DCP2_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK 0x0000000FL
+-//DCP2_OUT_CLAMP_CONTROL_R_CR
+-#define DCP2_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT 0x0
+-#define DCP2_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT 0x10
+-#define DCP2_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK 0x00003FFFL
+-#define DCP2_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK 0x3FFF0000L
+-//DCP2_OUT_CLAMP_CONTROL_G_Y
+-#define DCP2_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT 0x0
+-#define DCP2_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT 0x10
+-#define DCP2_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK 0x00003FFFL
+-#define DCP2_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK 0x3FFF0000L
+-//DCP2_OUT_CLAMP_CONTROL_B_CB
+-#define DCP2_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT 0x0
+-#define DCP2_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT 0x10
+-#define DCP2_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK 0x00003FFFL
+-#define DCP2_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK 0x3FFF0000L
+-//DCP2_KEY_CONTROL
+-#define DCP2_KEY_CONTROL__KEY_MODE__SHIFT 0x1
+-#define DCP2_KEY_CONTROL__KEY_MODE_MASK 0x00000006L
+-//DCP2_KEY_RANGE_ALPHA
+-#define DCP2_KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT 0x0
+-#define DCP2_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT 0x10
+-#define DCP2_KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK 0x0000FFFFL
+-#define DCP2_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK 0xFFFF0000L
+-//DCP2_KEY_RANGE_RED
+-#define DCP2_KEY_RANGE_RED__KEY_RED_LOW__SHIFT 0x0
+-#define DCP2_KEY_RANGE_RED__KEY_RED_HIGH__SHIFT 0x10
+-#define DCP2_KEY_RANGE_RED__KEY_RED_LOW_MASK 0x0000FFFFL
+-#define DCP2_KEY_RANGE_RED__KEY_RED_HIGH_MASK 0xFFFF0000L
+-//DCP2_KEY_RANGE_GREEN
+-#define DCP2_KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT 0x0
+-#define DCP2_KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT 0x10
+-#define DCP2_KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK 0x0000FFFFL
+-#define DCP2_KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK 0xFFFF0000L
+-//DCP2_KEY_RANGE_BLUE
+-#define DCP2_KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT 0x0
+-#define DCP2_KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT 0x10
+-#define DCP2_KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK 0x0000FFFFL
+-#define DCP2_KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK 0xFFFF0000L
+-//DCP2_DEGAMMA_CONTROL
+-#define DCP2_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x0
+-#define DCP2_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT 0x8
+-#define DCP2_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0xc
+-#define DCP2_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x00000003L
+-#define DCP2_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK 0x00000300L
+-#define DCP2_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK 0x00003000L
+-//DCP2_GAMUT_REMAP_CONTROL
+-#define DCP2_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT 0x0
+-#define DCP2_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK 0x00000003L
+-//DCP2_GAMUT_REMAP_C11_C12
+-#define DCP2_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT 0x0
+-#define DCP2_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT 0x10
+-#define DCP2_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK 0x0000FFFFL
+-#define DCP2_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK 0xFFFF0000L
+-//DCP2_GAMUT_REMAP_C13_C14
+-#define DCP2_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT 0x0
+-#define DCP2_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT 0x10
+-#define DCP2_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK 0x0000FFFFL
+-#define DCP2_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK 0xFFFF0000L
+-//DCP2_GAMUT_REMAP_C21_C22
+-#define DCP2_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT 0x0
+-#define DCP2_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT 0x10
+-#define DCP2_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK 0x0000FFFFL
+-#define DCP2_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK 0xFFFF0000L
+-//DCP2_GAMUT_REMAP_C23_C24
+-#define DCP2_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT 0x0
+-#define DCP2_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT 0x10
+-#define DCP2_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK 0x0000FFFFL
+-#define DCP2_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK 0xFFFF0000L
+-//DCP2_GAMUT_REMAP_C31_C32
+-#define DCP2_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT 0x0
+-#define DCP2_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT 0x10
+-#define DCP2_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK 0x0000FFFFL
+-#define DCP2_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK 0xFFFF0000L
+-//DCP2_GAMUT_REMAP_C33_C34
+-#define DCP2_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT 0x0
+-#define DCP2_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT 0x10
+-#define DCP2_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK 0x0000FFFFL
+-#define DCP2_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK 0xFFFF0000L
+-//DCP2_DCP_SPATIAL_DITHER_CNTL
+-#define DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT 0x0
+-#define DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT 0x4
+-#define DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT 0x6
+-#define DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT 0x8
+-#define DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT 0x9
+-#define DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT 0xa
+-#define DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK 0x00000001L
+-#define DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK 0x00000030L
+-#define DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK 0x000000C0L
+-#define DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK 0x00000100L
+-#define DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK 0x00000200L
+-#define DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK 0x00000400L
+-//DCP2_DCP_RANDOM_SEEDS
+-#define DCP2_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT 0x0
+-#define DCP2_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT 0x8
+-#define DCP2_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT 0x10
+-#define DCP2_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK 0x000000FFL
+-#define DCP2_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK 0x0000FF00L
+-#define DCP2_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK 0x00FF0000L
+-//DCP2_DCP_FP_CONVERTED_FIELD
+-#define DCP2_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT 0x0
+-#define DCP2_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14
+-#define DCP2_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK 0x0003FFFFL
+-#define DCP2_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK 0x07F00000L
+-//DCP2_CUR_CONTROL
+-#define DCP2_CUR_CONTROL__CURSOR_EN__SHIFT 0x0
+-#define DCP2_CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT 0x4
+-#define DCP2_CUR_CONTROL__CURSOR_MODE__SHIFT 0x8
+-#define DCP2_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM__SHIFT 0xb
+-#define DCP2_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION__SHIFT 0xc
+-#define DCP2_CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x10
+-#define DCP2_CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT 0x14
+-#define DCP2_CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT 0x18
+-#define DCP2_CUR_CONTROL__CURSOR_EN_MASK 0x00000001L
+-#define DCP2_CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK 0x00000010L
+-#define DCP2_CUR_CONTROL__CURSOR_MODE_MASK 0x00000300L
+-#define DCP2_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM_MASK 0x00000800L
+-#define DCP2_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION_MASK 0x0000F000L
+-#define DCP2_CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00010000L
+-#define DCP2_CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK 0x00100000L
+-#define DCP2_CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK 0x07000000L
+-//DCP2_CUR_SURFACE_ADDRESS
+-#define DCP2_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0
+-#define DCP2_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+-//DCP2_CUR_SIZE
+-#define DCP2_CUR_SIZE__CURSOR_HEIGHT__SHIFT 0x0
+-#define DCP2_CUR_SIZE__CURSOR_WIDTH__SHIFT 0x10
+-#define DCP2_CUR_SIZE__CURSOR_HEIGHT_MASK 0x0000007FL
+-#define DCP2_CUR_SIZE__CURSOR_WIDTH_MASK 0x007F0000L
+-//DCP2_CUR_SURFACE_ADDRESS_HIGH
+-#define DCP2_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+-#define DCP2_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+-//DCP2_CUR_POSITION
+-#define DCP2_CUR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0
+-#define DCP2_CUR_POSITION__CURSOR_X_POSITION__SHIFT 0x10
+-#define DCP2_CUR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL
+-#define DCP2_CUR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L
+-//DCP2_CUR_HOT_SPOT
+-#define DCP2_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0
+-#define DCP2_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10
+-#define DCP2_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x0000007FL
+-#define DCP2_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x007F0000L
+-//DCP2_CUR_COLOR1
+-#define DCP2_CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT 0x0
+-#define DCP2_CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT 0x8
+-#define DCP2_CUR_COLOR1__CUR_COLOR1_RED__SHIFT 0x10
+-#define DCP2_CUR_COLOR1__CUR_COLOR1_BLUE_MASK 0x000000FFL
+-#define DCP2_CUR_COLOR1__CUR_COLOR1_GREEN_MASK 0x0000FF00L
+-#define DCP2_CUR_COLOR1__CUR_COLOR1_RED_MASK 0x00FF0000L
+-//DCP2_CUR_COLOR2
+-#define DCP2_CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT 0x0
+-#define DCP2_CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT 0x8
+-#define DCP2_CUR_COLOR2__CUR_COLOR2_RED__SHIFT 0x10
+-#define DCP2_CUR_COLOR2__CUR_COLOR2_BLUE_MASK 0x000000FFL
+-#define DCP2_CUR_COLOR2__CUR_COLOR2_GREEN_MASK 0x0000FF00L
+-#define DCP2_CUR_COLOR2__CUR_COLOR2_RED_MASK 0x00FF0000L
+-//DCP2_CUR_UPDATE
+-#define DCP2_CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT 0x0
+-#define DCP2_CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT 0x1
+-#define DCP2_CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT 0x10
+-#define DCP2_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+-#define DCP2_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE__SHIFT 0x19
+-#define DCP2_CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK 0x00000001L
+-#define DCP2_CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x00000002L
+-#define DCP2_CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK 0x00010000L
+-#define DCP2_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
+-#define DCP2_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE_MASK 0x06000000L
+-//DCP2_CUR_REQUEST_FILTER_CNTL
+-#define DCP2_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT 0x0
+-#define DCP2_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK 0x00000001L
+-//DCP2_CUR_STEREO_CONTROL
+-#define DCP2_CUR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0
+-#define DCP2_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4
+-#define DCP2_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x10
+-#define DCP2_CUR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L
+-#define DCP2_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x00003FF0L
+-#define DCP2_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0x03FF0000L
+-//DCP2_DC_LUT_RW_MODE
+-#define DCP2_DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT 0x0
+-#define DCP2_DC_LUT_RW_MODE__DC_LUT_ERROR__SHIFT 0x10
+-#define DCP2_DC_LUT_RW_MODE__DC_LUT_ERROR_RST__SHIFT 0x11
+-#define DCP2_DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK 0x00000001L
+-#define DCP2_DC_LUT_RW_MODE__DC_LUT_ERROR_MASK 0x00010000L
+-#define DCP2_DC_LUT_RW_MODE__DC_LUT_ERROR_RST_MASK 0x00020000L
+-//DCP2_DC_LUT_RW_INDEX
+-#define DCP2_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT 0x0
+-#define DCP2_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK 0x000000FFL
+-//DCP2_DC_LUT_SEQ_COLOR
+-#define DCP2_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT 0x0
+-#define DCP2_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK 0x0000FFFFL
+-//DCP2_DC_LUT_PWL_DATA
+-#define DCP2_DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT 0x0
+-#define DCP2_DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT 0x10
+-#define DCP2_DC_LUT_PWL_DATA__DC_LUT_BASE_MASK 0x0000FFFFL
+-#define DCP2_DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK 0xFFFF0000L
+-//DCP2_DC_LUT_30_COLOR
+-#define DCP2_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT 0x0
+-#define DCP2_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT 0xa
+-#define DCP2_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT 0x14
+-#define DCP2_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK 0x000003FFL
+-#define DCP2_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK 0x000FFC00L
+-#define DCP2_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK 0x3FF00000L
+-//DCP2_DC_LUT_VGA_ACCESS_ENABLE
+-#define DCP2_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT 0x0
+-#define DCP2_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK 0x00000001L
+-//DCP2_DC_LUT_WRITE_EN_MASK
+-#define DCP2_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT 0x0
+-#define DCP2_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK 0x00000007L
+-//DCP2_DC_LUT_AUTOFILL
+-#define DCP2_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT 0x0
+-#define DCP2_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT 0x1
+-#define DCP2_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK 0x00000001L
+-#define DCP2_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x00000002L
+-//DCP2_DC_LUT_CONTROL
+-#define DCP2_DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT 0x0
+-#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT 0x4
+-#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT 0x5
+-#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT 0x6
+-#define DCP2_DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT 0x8
+-#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT 0xc
+-#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT 0xd
+-#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT 0xe
+-#define DCP2_DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT 0x10
+-#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT 0x14
+-#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT 0x15
+-#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT 0x16
+-#define DCP2_DC_LUT_CONTROL__DC_LUT_INC_B_MASK 0x0000000FL
+-#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK 0x00000010L
+-#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK 0x00000020L
+-#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK 0x000000C0L
+-#define DCP2_DC_LUT_CONTROL__DC_LUT_INC_G_MASK 0x00000F00L
+-#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK 0x00001000L
+-#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK 0x00002000L
+-#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK 0x0000C000L
+-#define DCP2_DC_LUT_CONTROL__DC_LUT_INC_R_MASK 0x000F0000L
+-#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK 0x00100000L
+-#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK 0x00200000L
+-#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK 0x00C00000L
+-//DCP2_DC_LUT_BLACK_OFFSET_BLUE
+-#define DCP2_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0
+-#define DCP2_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK 0x0000FFFFL
+-//DCP2_DC_LUT_BLACK_OFFSET_GREEN
+-#define DCP2_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0
+-#define DCP2_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK 0x0000FFFFL
+-//DCP2_DC_LUT_BLACK_OFFSET_RED
+-#define DCP2_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT 0x0
+-#define DCP2_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK 0x0000FFFFL
+-//DCP2_DC_LUT_WHITE_OFFSET_BLUE
+-#define DCP2_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT 0x0
+-#define DCP2_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK 0x0000FFFFL
+-//DCP2_DC_LUT_WHITE_OFFSET_GREEN
+-#define DCP2_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT 0x0
+-#define DCP2_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK 0x0000FFFFL
+-//DCP2_DC_LUT_WHITE_OFFSET_RED
+-#define DCP2_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT 0x0
+-#define DCP2_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK 0x0000FFFFL
+-//DCP2_DCP_CRC_CONTROL
+-#define DCP2_DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT 0x0
+-#define DCP2_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x2
+-#define DCP2_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT 0x8
+-#define DCP2_DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK 0x00000001L
+-#define DCP2_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK 0x0000001CL
+-#define DCP2_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK 0x00000300L
+-//DCP2_DCP_CRC_MASK
+-#define DCP2_DCP_CRC_MASK__DCP_CRC_MASK__SHIFT 0x0
+-#define DCP2_DCP_CRC_MASK__DCP_CRC_MASK_MASK 0xFFFFFFFFL
+-//DCP2_DCP_CRC_CURRENT
+-#define DCP2_DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT 0x0
+-#define DCP2_DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK 0xFFFFFFFFL
+-//DCP2_DVMM_PTE_CONTROL
+-#define DCP2_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT 0x0
+-#define DCP2_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT 0x1
+-#define DCP2_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT 0x5
+-#define DCP2_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT 0x9
+-#define DCP2_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT 0x14
+-#define DCP2_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT 0x15
+-#define DCP2_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK 0x00000001L
+-#define DCP2_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK 0x0000001EL
+-#define DCP2_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK 0x000001E0L
+-#define DCP2_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK 0x0007FE00L
+-#define DCP2_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK 0x00100000L
+-#define DCP2_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK 0x00200000L
+-//DCP2_DCP_CRC_LAST
+-#define DCP2_DCP_CRC_LAST__DCP_CRC_LAST__SHIFT 0x0
+-#define DCP2_DCP_CRC_LAST__DCP_CRC_LAST_MASK 0xFFFFFFFFL
+-//DCP2_DVMM_PTE_ARB_CONTROL
+-#define DCP2_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT 0x0
+-#define DCP2_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT 0x8
+-#define DCP2_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK 0x0000003FL
+-#define DCP2_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK 0x0000FF00L
+-//DCP2_GRPH_FLIP_RATE_CNTL
+-#define DCP2_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT 0x0
+-#define DCP2_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT 0x3
+-#define DCP2_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK 0x00000007L
+-#define DCP2_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK 0x00000008L
+-//DCP2_DCP_GSL_CONTROL
+-#define DCP2_DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT 0x0
+-#define DCP2_DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT 0x1
+-#define DCP2_DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x2
+-#define DCP2_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT 0x4
+-#define DCP2_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT 0x14
+-#define DCP2_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP__SHIFT 0x15
+-#define DCP2_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN__SHIFT 0x17
+-#define DCP2_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT 0x18
+-#define DCP2_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC__SHIFT 0x1a
+-#define DCP2_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT 0x1b
+-#define DCP2_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT 0x1c
+-#define DCP2_DCP_GSL_CONTROL__DCP_GSL0_EN_MASK 0x00000001L
+-#define DCP2_DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x00000002L
+-#define DCP2_DCP_GSL_CONTROL__DCP_GSL2_EN_MASK 0x00000004L
+-#define DCP2_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK 0x000FFFF0L
+-#define DCP2_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK 0x00100000L
+-#define DCP2_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_MASK 0x00600000L
+-#define DCP2_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_MASK 0x00800000L
+-#define DCP2_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK 0x03000000L
+-#define DCP2_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_MASK 0x04000000L
+-#define DCP2_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK 0x08000000L
+-#define DCP2_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK 0xF0000000L
+-//DCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK
+-#define DCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT 0x0
+-#define DCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT 0x4
+-#define DCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK 0x0000000FL
+-#define DCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK 0x000001F0L
+-//DCP2_GRPH_STEREOSYNC_FLIP
+-#define DCP2_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0
+-#define DCP2_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x8
+-#define DCP2_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10
+-#define DCP2_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11
+-#define DCP2_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c
+-#define DCP2_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x00000001L
+-#define DCP2_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x00000300L
+-#define DCP2_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x00010000L
+-#define DCP2_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x00020000L
+-#define DCP2_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000L
+-//DCP2_HW_ROTATION
+-#define DCP2_HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT 0x0
+-#define DCP2_HW_ROTATION__GRPH_ROTATION_ANGLE_MASK 0x00000007L
+-//DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL
+-#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT 0x0
+-#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT 0x1
+-#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT 0x4
+-#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK 0x00000001L
+-#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK 0x00000002L
+-#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK 0x0001FFF0L
+-//DCP2_REGAMMA_CONTROL
+-#define DCP2_REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT 0x0
+-#define DCP2_REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK 0x00000007L
+-//DCP2_REGAMMA_LUT_INDEX
+-#define DCP2_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x0
+-#define DCP2_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK 0x000001FFL
+-//DCP2_REGAMMA_LUT_DATA
+-#define DCP2_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT 0x0
+-#define DCP2_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK 0x0007FFFFL
+-//DCP2_REGAMMA_LUT_WRITE_EN_MASK
+-#define DCP2_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x0
+-#define DCP2_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x00000007L
+-//DCP2_REGAMMA_CNTLA_START_CNTL
+-#define DCP2_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x0
+-#define DCP2_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14
+-#define DCP2_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK 0x0003FFFFL
+-#define DCP2_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
+-//DCP2_REGAMMA_CNTLA_SLOPE_CNTL
+-#define DCP2_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+-#define DCP2_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
+-//DCP2_REGAMMA_CNTLA_END_CNTL1
+-#define DCP2_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x0
+-#define DCP2_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK 0x0000FFFFL
+-//DCP2_REGAMMA_CNTLA_END_CNTL2
+-#define DCP2_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0
+-#define DCP2_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10
+-#define DCP2_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
+-#define DCP2_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xFFFF0000L
+-//DCP2_REGAMMA_CNTLA_REGION_0_1
+-#define DCP2_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+-#define DCP2_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP2_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+-#define DCP2_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP2_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP2_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP2_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP2_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP2_REGAMMA_CNTLA_REGION_2_3
+-#define DCP2_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+-#define DCP2_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP2_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+-#define DCP2_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP2_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP2_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP2_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP2_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP2_REGAMMA_CNTLA_REGION_4_5
+-#define DCP2_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+-#define DCP2_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP2_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+-#define DCP2_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP2_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP2_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP2_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP2_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP2_REGAMMA_CNTLA_REGION_6_7
+-#define DCP2_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+-#define DCP2_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP2_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+-#define DCP2_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP2_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP2_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP2_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP2_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP2_REGAMMA_CNTLA_REGION_8_9
+-#define DCP2_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+-#define DCP2_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP2_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+-#define DCP2_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP2_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP2_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP2_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP2_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP2_REGAMMA_CNTLA_REGION_10_11
+-#define DCP2_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+-#define DCP2_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP2_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+-#define DCP2_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP2_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP2_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP2_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP2_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP2_REGAMMA_CNTLA_REGION_12_13
+-#define DCP2_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+-#define DCP2_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP2_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+-#define DCP2_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP2_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP2_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP2_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP2_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP2_REGAMMA_CNTLA_REGION_14_15
+-#define DCP2_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+-#define DCP2_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP2_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+-#define DCP2_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP2_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP2_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP2_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP2_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP2_REGAMMA_CNTLB_START_CNTL
+-#define DCP2_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x0
+-#define DCP2_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14
+-#define DCP2_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK 0x0003FFFFL
+-#define DCP2_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
+-//DCP2_REGAMMA_CNTLB_SLOPE_CNTL
+-#define DCP2_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+-#define DCP2_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
+-//DCP2_REGAMMA_CNTLB_END_CNTL1
+-#define DCP2_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x0
+-#define DCP2_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK 0x0000FFFFL
+-//DCP2_REGAMMA_CNTLB_END_CNTL2
+-#define DCP2_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0
+-#define DCP2_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10
+-#define DCP2_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
+-#define DCP2_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xFFFF0000L
+-//DCP2_REGAMMA_CNTLB_REGION_0_1
+-#define DCP2_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+-#define DCP2_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP2_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+-#define DCP2_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP2_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP2_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP2_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP2_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP2_REGAMMA_CNTLB_REGION_2_3
+-#define DCP2_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+-#define DCP2_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP2_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+-#define DCP2_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP2_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP2_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP2_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP2_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP2_REGAMMA_CNTLB_REGION_4_5
+-#define DCP2_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+-#define DCP2_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP2_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+-#define DCP2_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP2_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP2_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP2_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP2_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP2_REGAMMA_CNTLB_REGION_6_7
+-#define DCP2_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+-#define DCP2_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP2_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+-#define DCP2_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP2_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP2_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP2_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP2_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP2_REGAMMA_CNTLB_REGION_8_9
+-#define DCP2_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+-#define DCP2_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP2_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+-#define DCP2_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP2_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP2_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP2_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP2_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP2_REGAMMA_CNTLB_REGION_10_11
+-#define DCP2_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+-#define DCP2_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP2_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+-#define DCP2_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP2_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP2_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP2_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP2_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP2_REGAMMA_CNTLB_REGION_12_13
+-#define DCP2_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+-#define DCP2_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP2_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+-#define DCP2_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP2_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP2_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP2_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP2_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP2_REGAMMA_CNTLB_REGION_14_15
+-#define DCP2_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+-#define DCP2_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP2_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+-#define DCP2_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP2_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP2_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP2_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP2_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP2_ALPHA_CONTROL
+-#define DCP2_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT 0x0
+-#define DCP2_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT 0x1
+-#define DCP2_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK 0x00000001L
+-#define DCP2_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK 0x00000002L
+-//DCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS
+-#define DCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT 0x8
+-#define DCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+-//DCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH
+-#define DCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+-#define DCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+-//DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS
+-#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT 0x0
+-#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT 0x18
+-#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT 0x19
+-#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT 0x1a
+-#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT 0x1c
+-#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT 0x1d
+-#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT 0x1e
+-#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK 0x000FFFFFL
+-#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK 0x01000000L
+-#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK 0x02000000L
+-#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK 0x04000000L
+-#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK 0x10000000L
+-#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK 0x20000000L
+-#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK 0x40000000L
+-//DCP2_GRPH_XDMA_FLIP_TIMEOUT
+-#define DCP2_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS__SHIFT 0x0
+-#define DCP2_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK__SHIFT 0x1
+-#define DCP2_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK__SHIFT 0x2
+-#define DCP2_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS_MASK 0x00000001L
+-#define DCP2_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK_MASK 0x00000002L
+-#define DCP2_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK_MASK 0x00000004L
+-//DCP2_GRPH_XDMA_FLIP_AVG_DELAY
+-#define DCP2_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY__SHIFT 0x0
+-#define DCP2_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD__SHIFT 0x10
+-#define DCP2_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY_MASK 0x0000FFFFL
+-#define DCP2_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD_MASK 0x00FF0000L
+-//DCP2_GRPH_SURFACE_COUNTER_CONTROL
+-#define DCP2_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN__SHIFT 0x0
+-#define DCP2_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT__SHIFT 0x1
+-#define DCP2_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED__SHIFT 0x9
+-#define DCP2_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN_MASK 0x00000001L
+-#define DCP2_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT_MASK 0x0000001EL
+-#define DCP2_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_MASK 0x00000200L
+-//DCP2_GRPH_SURFACE_COUNTER_OUTPUT
+-#define DCP2_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN__SHIFT 0x0
+-#define DCP2_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX__SHIFT 0x10
+-#define DCP2_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN_MASK 0x0000FFFFL
+-#define DCP2_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX_MASK 0xFFFF0000L
+-
+-
+-// addressBlock: dce_dc_lb2_dispdec
+-//LB2_LB_DATA_FORMAT
+-#define LB2_LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0
+-#define LB2_LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2
+-#define LB2_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3
+-#define LB2_LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4
+-#define LB2_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5
+-#define LB2_LB_DATA_FORMAT__PREFILL_EN__SHIFT 0x8
+-#define LB2_LB_DATA_FORMAT__PREFETCH__SHIFT 0xc
+-#define LB2_LB_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18
+-#define LB2_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f
+-#define LB2_LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x00000003L
+-#define LB2_LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x00000004L
+-#define LB2_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000008L
+-#define LB2_LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x00000010L
+-#define LB2_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x00000020L
+-#define LB2_LB_DATA_FORMAT__PREFILL_EN_MASK 0x00000100L
+-#define LB2_LB_DATA_FORMAT__PREFETCH_MASK 0x00001000L
+-#define LB2_LB_DATA_FORMAT__REQUEST_MODE_MASK 0x01000000L
+-#define LB2_LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000L
+-//LB2_LB_MEMORY_CTRL
+-#define LB2_LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0
+-#define LB2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
+-#define LB2_LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14
+-#define LB2_LB_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0x00001FFFL
+-#define LB2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x000F0000L
+-#define LB2_LB_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x00300000L
+-//LB2_LB_MEMORY_SIZE_STATUS
+-#define LB2_LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0
+-#define LB2_LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0x00001FFFL
+-//LB2_LB_DESKTOP_HEIGHT
+-#define LB2_LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0
+-#define LB2_LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x00007FFFL
+-//LB2_LB_VLINE_START_END
+-#define LB2_LB_VLINE_START_END__VLINE_START__SHIFT 0x0
+-#define LB2_LB_VLINE_START_END__VLINE_END__SHIFT 0x10
+-#define LB2_LB_VLINE_START_END__VLINE_INV__SHIFT 0x1f
+-#define LB2_LB_VLINE_START_END__VLINE_START_MASK 0x00003FFFL
+-#define LB2_LB_VLINE_START_END__VLINE_END_MASK 0x7FFF0000L
+-#define LB2_LB_VLINE_START_END__VLINE_INV_MASK 0x80000000L
+-//LB2_LB_VLINE2_START_END
+-#define LB2_LB_VLINE2_START_END__VLINE2_START__SHIFT 0x0
+-#define LB2_LB_VLINE2_START_END__VLINE2_END__SHIFT 0x10
+-#define LB2_LB_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f
+-#define LB2_LB_VLINE2_START_END__VLINE2_START_MASK 0x00003FFFL
+-#define LB2_LB_VLINE2_START_END__VLINE2_END_MASK 0x7FFF0000L
+-#define LB2_LB_VLINE2_START_END__VLINE2_INV_MASK 0x80000000L
+-//LB2_LB_V_COUNTER
+-#define LB2_LB_V_COUNTER__V_COUNTER__SHIFT 0x0
+-#define LB2_LB_V_COUNTER__V_COUNTER_MASK 0x00007FFFL
+-//LB2_LB_SNAPSHOT_V_COUNTER
+-#define LB2_LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0
+-#define LB2_LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x00007FFFL
+-//LB2_LB_INTERRUPT_MASK
+-#define LB2_LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0
+-#define LB2_LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4
+-#define LB2_LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8
+-#define LB2_LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x00000001L
+-#define LB2_LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x00000010L
+-#define LB2_LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x00000100L
+-//LB2_LB_VLINE_STATUS
+-#define LB2_LB_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0
+-#define LB2_LB_VLINE_STATUS__VLINE_ACK__SHIFT 0x4
+-#define LB2_LB_VLINE_STATUS__VLINE_STAT__SHIFT 0xc
+-#define LB2_LB_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10
+-#define LB2_LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11
+-#define LB2_LB_VLINE_STATUS__VLINE_OCCURRED_MASK 0x00000001L
+-#define LB2_LB_VLINE_STATUS__VLINE_ACK_MASK 0x00000010L
+-#define LB2_LB_VLINE_STATUS__VLINE_STAT_MASK 0x00001000L
+-#define LB2_LB_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x00010000L
+-#define LB2_LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x00020000L
+-//LB2_LB_VLINE2_STATUS
+-#define LB2_LB_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0
+-#define LB2_LB_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4
+-#define LB2_LB_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc
+-#define LB2_LB_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10
+-#define LB2_LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11
+-#define LB2_LB_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x00000001L
+-#define LB2_LB_VLINE2_STATUS__VLINE2_ACK_MASK 0x00000010L
+-#define LB2_LB_VLINE2_STATUS__VLINE2_STAT_MASK 0x00001000L
+-#define LB2_LB_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x00010000L
+-#define LB2_LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x00020000L
+-//LB2_LB_VBLANK_STATUS
+-#define LB2_LB_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0
+-#define LB2_LB_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4
+-#define LB2_LB_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc
+-#define LB2_LB_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10
+-#define LB2_LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11
+-#define LB2_LB_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x00000001L
+-#define LB2_LB_VBLANK_STATUS__VBLANK_ACK_MASK 0x00000010L
+-#define LB2_LB_VBLANK_STATUS__VBLANK_STAT_MASK 0x00001000L
+-#define LB2_LB_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x00010000L
+-#define LB2_LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x00020000L
+-//LB2_LB_SYNC_RESET_SEL
+-#define LB2_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0
+-#define LB2_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4
+-#define LB2_LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8
+-#define LB2_LB_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16
+-#define LB2_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x00000003L
+-#define LB2_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x00000010L
+-#define LB2_LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0x0000FF00L
+-#define LB2_LB_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0x00C00000L
+-//LB2_LB_BLACK_KEYER_R_CR
+-#define LB2_LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4
+-#define LB2_LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0x0000FFF0L
+-//LB2_LB_BLACK_KEYER_G_Y
+-#define LB2_LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4
+-#define LB2_LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0x0000FFF0L
+-//LB2_LB_BLACK_KEYER_B_CB
+-#define LB2_LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4
+-#define LB2_LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0x0000FFF0L
+-//LB2_LB_KEYER_COLOR_CTRL
+-#define LB2_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0
+-#define LB2_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8
+-#define LB2_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x00000001L
+-#define LB2_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x00000100L
+-//LB2_LB_KEYER_COLOR_R_CR
+-#define LB2_LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4
+-#define LB2_LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0x0000FFF0L
+-//LB2_LB_KEYER_COLOR_G_Y
+-#define LB2_LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4
+-#define LB2_LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0x0000FFF0L
+-//LB2_LB_KEYER_COLOR_B_CB
+-#define LB2_LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4
+-#define LB2_LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0x0000FFF0L
+-//LB2_LB_KEYER_COLOR_REP_R_CR
+-#define LB2_LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4
+-#define LB2_LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0x0000FFF0L
+-//LB2_LB_KEYER_COLOR_REP_G_Y
+-#define LB2_LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4
+-#define LB2_LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0x0000FFF0L
+-//LB2_LB_KEYER_COLOR_REP_B_CB
+-#define LB2_LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4
+-#define LB2_LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0x0000FFF0L
+-//LB2_LB_BUFFER_LEVEL_STATUS
+-#define LB2_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0
+-#define LB2_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa
+-#define LB2_LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10
+-#define LB2_LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c
+-#define LB2_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x0000003FL
+-#define LB2_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0x0000FC00L
+-#define LB2_LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0x0FFF0000L
+-#define LB2_LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xF0000000L
+-//LB2_LB_BUFFER_URGENCY_CTRL
+-#define LB2_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0
+-#define LB2_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10
+-#define LB2_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0x00000FFFL
+-#define LB2_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0x0FFF0000L
+-//LB2_LB_BUFFER_URGENCY_STATUS
+-#define LB2_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0
+-#define LB2_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10
+-#define LB2_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0x00000FFFL
+-#define LB2_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x00010000L
+-//LB2_LB_BUFFER_STATUS
+-#define LB2_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0
+-#define LB2_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4
+-#define LB2_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8
+-#define LB2_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc
+-#define LB2_LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10
+-#define LB2_LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14
+-#define LB2_LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18
+-#define LB2_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0x0000000FL
+-#define LB2_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x00000010L
+-#define LB2_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x00000100L
+-#define LB2_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x00001000L
+-#define LB2_LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x00010000L
+-#define LB2_LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x00100000L
+-#define LB2_LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x01000000L
+-//LB2_LB_NO_OUTSTANDING_REQ_STATUS
+-#define LB2_LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0
+-#define LB2_LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x00000001L
+-//LB2_MVP_AFR_FLIP_MODE
+-#define LB2_MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT 0x0
+-#define LB2_MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK 0x00000003L
+-//LB2_MVP_AFR_FLIP_FIFO_CNTL
+-#define LB2_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT 0x0
+-#define LB2_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT 0x4
+-#define LB2_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT 0x8
+-#define LB2_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT 0xc
+-#define LB2_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK 0x0000000FL
+-#define LB2_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK 0x00000010L
+-#define LB2_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK 0x00000100L
+-#define LB2_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK 0x00001000L
+-//LB2_MVP_FLIP_LINE_NUM_INSERT
+-#define LB2_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT 0x0
+-#define LB2_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT 0x8
+-#define LB2_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT 0x18
+-#define LB2_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT 0x1e
+-#define LB2_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK 0x00000003L
+-#define LB2_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK 0x007FFF00L
+-#define LB2_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK 0x3F000000L
+-#define LB2_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK 0x40000000L
+-//LB2_DC_MVP_LB_CONTROL
+-#define LB2_DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT 0x0
+-#define LB2_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT 0x8
+-#define LB2_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT 0xc
+-#define LB2_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT 0x10
+-#define LB2_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT 0x14
+-#define LB2_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT 0x1c
+-#define LB2_DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT 0x1f
+-#define LB2_DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK 0x00000003L
+-#define LB2_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK 0x00000100L
+-#define LB2_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK 0x00001000L
+-#define LB2_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK 0x00010000L
+-#define LB2_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK 0x00100000L
+-#define LB2_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK 0x10000000L
+-#define LB2_DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK 0x80000000L
+-
+-
+-// addressBlock: dce_dc_dcfe2_dispdec
+-//DCFE2_DCFE_CLOCK_CONTROL
+-#define DCFE2_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x4
+-#define DCFE2_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x8
+-#define DCFE2_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0xc
+-#define DCFE2_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE__SHIFT 0xf
+-#define DCFE2_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE__SHIFT 0x11
+-#define DCFE2_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL__SHIFT 0x18
+-#define DCFE2_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE__SHIFT 0x1f
+-#define DCFE2_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x00000010L
+-#define DCFE2_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE_MASK 0x00000100L
+-#define DCFE2_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE_MASK 0x00001000L
+-#define DCFE2_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE_MASK 0x00008000L
+-#define DCFE2_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE_MASK 0x00020000L
+-#define DCFE2_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL_MASK 0x1F000000L
+-#define DCFE2_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE_MASK 0x80000000L
+-//DCFE2_DCFE_SOFT_RESET
+-#define DCFE2_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET__SHIFT 0x0
+-#define DCFE2_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET__SHIFT 0x1
+-#define DCFE2_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET__SHIFT 0x2
+-#define DCFE2_DCFE_SOFT_RESET__SCL_SOFT_RESET__SHIFT 0x3
+-#define DCFE2_DCFE_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4
+-#define DCFE2_DCFE_SOFT_RESET__PSCL_SOFT_RESET__SHIFT 0x5
+-#define DCFE2_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET_MASK 0x00000001L
+-#define DCFE2_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET_MASK 0x00000002L
+-#define DCFE2_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET_MASK 0x00000004L
+-#define DCFE2_DCFE_SOFT_RESET__SCL_SOFT_RESET_MASK 0x00000008L
+-#define DCFE2_DCFE_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x00000010L
+-#define DCFE2_DCFE_SOFT_RESET__PSCL_SOFT_RESET_MASK 0x00000020L
+-//DCFE2_DCFE_MEM_PWR_CTRL
+-#define DCFE2_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE__SHIFT 0x0
+-#define DCFE2_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS__SHIFT 0x2
+-#define DCFE2_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE__SHIFT 0x3
+-#define DCFE2_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS__SHIFT 0x5
+-#define DCFE2_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE__SHIFT 0x6
+-#define DCFE2_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS__SHIFT 0x8
+-#define DCFE2_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE__SHIFT 0x9
+-#define DCFE2_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS__SHIFT 0xb
+-#define DCFE2_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE__SHIFT 0xc
+-#define DCFE2_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS__SHIFT 0xe
+-#define DCFE2_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE__SHIFT 0xf
+-#define DCFE2_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS__SHIFT 0x11
+-#define DCFE2_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE__SHIFT 0x12
+-#define DCFE2_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS__SHIFT 0x14
+-#define DCFE2_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE__SHIFT 0x15
+-#define DCFE2_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS__SHIFT 0x17
+-#define DCFE2_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE__SHIFT 0x18
+-#define DCFE2_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS__SHIFT 0x1a
+-#define DCFE2_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE__SHIFT 0x1b
+-#define DCFE2_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS__SHIFT 0x1d
+-#define DCFE2_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE_MASK 0x00000003L
+-#define DCFE2_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS_MASK 0x00000004L
+-#define DCFE2_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE_MASK 0x00000018L
+-#define DCFE2_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS_MASK 0x00000020L
+-#define DCFE2_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE_MASK 0x000000C0L
+-#define DCFE2_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS_MASK 0x00000100L
+-#define DCFE2_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE_MASK 0x00000600L
+-#define DCFE2_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS_MASK 0x00000800L
+-#define DCFE2_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE_MASK 0x00003000L
+-#define DCFE2_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS_MASK 0x00004000L
+-#define DCFE2_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE_MASK 0x00018000L
+-#define DCFE2_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK 0x00020000L
+-#define DCFE2_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE_MASK 0x000C0000L
+-#define DCFE2_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS_MASK 0x00100000L
+-#define DCFE2_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE_MASK 0x00600000L
+-#define DCFE2_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS_MASK 0x00800000L
+-#define DCFE2_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE_MASK 0x03000000L
+-#define DCFE2_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS_MASK 0x04000000L
+-#define DCFE2_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE_MASK 0x18000000L
+-#define DCFE2_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS_MASK 0x20000000L
+-//DCFE2_DCFE_MEM_PWR_CTRL2
+-#define DCFE2_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL__SHIFT 0x0
+-#define DCFE2_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2
+-#define DCFE2_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4
+-#define DCFE2_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL__SHIFT 0x6
+-#define DCFE2_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL__SHIFT 0x8
+-#define DCFE2_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL__SHIFT 0xa
+-#define DCFE2_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL__SHIFT 0xc
+-#define DCFE2_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL__SHIFT 0xe
+-#define DCFE2_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE__SHIFT 0x10
+-#define DCFE2_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS__SHIFT 0x12
+-#define DCFE2_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE__SHIFT 0x15
+-#define DCFE2_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS__SHIFT 0x17
+-#define DCFE2_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL_MASK 0x00000003L
+-#define DCFE2_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL_MASK 0x0000000CL
+-#define DCFE2_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL_MASK 0x00000030L
+-#define DCFE2_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL_MASK 0x000000C0L
+-#define DCFE2_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL_MASK 0x00000300L
+-#define DCFE2_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL_MASK 0x00000C00L
+-#define DCFE2_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL_MASK 0x00003000L
+-#define DCFE2_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL_MASK 0x0000C000L
+-#define DCFE2_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE_MASK 0x00030000L
+-#define DCFE2_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS_MASK 0x00040000L
+-#define DCFE2_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE_MASK 0x00600000L
+-#define DCFE2_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS_MASK 0x00800000L
+-//DCFE2_DCFE_MEM_PWR_STATUS
+-#define DCFE2_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE__SHIFT 0x0
+-#define DCFE2_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE__SHIFT 0x2
+-#define DCFE2_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE__SHIFT 0x4
+-#define DCFE2_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x6
+-#define DCFE2_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE__SHIFT 0x8
+-#define DCFE2_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE__SHIFT 0xa
+-#define DCFE2_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE__SHIFT 0xc
+-#define DCFE2_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE__SHIFT 0xe
+-#define DCFE2_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT 0x10
+-#define DCFE2_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE__SHIFT 0x12
+-#define DCFE2_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE__SHIFT 0x14
+-#define DCFE2_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE__SHIFT 0x16
+-#define DCFE2_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK 0x00000003L
+-#define DCFE2_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE_MASK 0x0000000CL
+-#define DCFE2_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE_MASK 0x00000030L
+-#define DCFE2_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE_MASK 0x000000C0L
+-#define DCFE2_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE_MASK 0x00000300L
+-#define DCFE2_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE_MASK 0x00000C00L
+-#define DCFE2_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE_MASK 0x00003000L
+-#define DCFE2_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE_MASK 0x0000C000L
+-#define DCFE2_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE_MASK 0x00030000L
+-#define DCFE2_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK 0x000C0000L
+-#define DCFE2_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE_MASK 0x00300000L
+-#define DCFE2_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE_MASK 0x00C00000L
+-//DCFE2_DCFE_MISC
+-#define DCFE2_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN__SHIFT 0x0
+-#define DCFE2_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN_MASK 0x00000001L
+-//DCFE2_DCFE_FLUSH
+-#define DCFE2_DCFE_FLUSH__FLUSH_OCCURED__SHIFT 0x0
+-#define DCFE2_DCFE_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT 0x1
+-#define DCFE2_DCFE_FLUSH__FLUSH_DEEP__SHIFT 0x2
+-#define DCFE2_DCFE_FLUSH__CLEAR_FLUSH_DEEP__SHIFT 0x3
+-#define DCFE2_DCFE_FLUSH__ALL_MC_REQ_RET__SHIFT 0x4
+-#define DCFE2_DCFE_FLUSH__FLUSH_OCCURED_MASK 0x00000001L
+-#define DCFE2_DCFE_FLUSH__CLEAR_FLUSH_OCCURED_MASK 0x00000002L
+-#define DCFE2_DCFE_FLUSH__FLUSH_DEEP_MASK 0x00000004L
+-#define DCFE2_DCFE_FLUSH__CLEAR_FLUSH_DEEP_MASK 0x00000008L
+-#define DCFE2_DCFE_FLUSH__ALL_MC_REQ_RET_MASK 0x00000010L
+-
+-
+-// addressBlock: dce_dc_dc_perfmon5_dispdec
+-//DC_PERFMON5_PERFCOUNTER_CNTL
+-#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+-#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+-#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+-#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+-#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+-#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
+-#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+-#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+-#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+-#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+-#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+-#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
+-#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+-#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+-#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+-#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+-#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+-#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+-#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
+-#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+-#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+-#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+-#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+-#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+-#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
+-#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+-//DC_PERFMON5_PERFCOUNTER_CNTL2
+-#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+-#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+-#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+-#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+-#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+-#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+-#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+-#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+-//DC_PERFMON5_PERFCOUNTER_STATE
+-#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+-#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+-#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+-#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+-#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+-#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+-#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+-#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+-#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+-#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+-#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+-#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+-#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+-#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+-#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+-#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+-#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+-#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+-#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+-#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+-#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+-#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+-#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+-#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+-#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+-#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+-#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+-#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+-#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+-#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+-#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+-#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+-//DC_PERFMON5_PERFMON_CNTL
+-#define DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+-#define DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+-#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+-#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+-#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+-#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+-#define DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+-#define DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+-#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+-#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+-#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+-#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+-//DC_PERFMON5_PERFMON_CNTL2
+-#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+-#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+-#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+-#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+-#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+-#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+-#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+-#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+-//DC_PERFMON5_PERFMON_CVALUE_INT_MISC
+-#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+-#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+-#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+-#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+-#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+-#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+-#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+-#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+-#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+-#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+-#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+-#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+-#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+-#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+-#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+-#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+-#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+-#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+-#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+-#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+-#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+-#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+-#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+-#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+-#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+-#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+-#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+-#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+-#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+-#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+-#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+-#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+-#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+-#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+-//DC_PERFMON5_PERFMON_CVALUE_LOW
+-#define DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+-#define DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+-//DC_PERFMON5_PERFMON_HI
+-#define DC_PERFMON5_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+-#define DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+-#define DC_PERFMON5_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+-#define DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+-//DC_PERFMON5_PERFMON_LOW
+-#define DC_PERFMON5_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+-#define DC_PERFMON5_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dmif_pg2_dispdec
+-//DMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1
+-#define DMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
+-#define DMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
+-#define DMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0x0000FFFFL
+-#define DMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xFFFF0000L
+-//DMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2
+-#define DMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
+-#define DMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
+-#define DMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0x0000FFFFL
+-#define DMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xFFFF0000L
+-//DMIF_PG2_DPG_WATERMARK_MASK_CONTROL
+-#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
+-#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x4
+-#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
+-#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK__SHIFT 0xc
+-#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0xf
+-#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x12
+-#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL__SHIFT 0x13
+-#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL__SHIFT 0x14
+-#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000007L
+-#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000070L
+-#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x00000700L
+-#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK_MASK 0x00007000L
+-#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00038000L
+-#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x00040000L
+-#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL_MASK 0x00080000L
+-#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL_MASK 0x3FF00000L
+-//DMIF_PG2_DPG_PIPE_URGENCY_CONTROL
+-#define DMIF_PG2_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
+-#define DMIF_PG2_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
+-#define DMIF_PG2_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0x0000FFFFL
+-#define DMIF_PG2_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xFFFF0000L
+-//DMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL
+-#define DMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK__SHIFT 0x0
+-#define DMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK__SHIFT 0x10
+-#define DMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK_MASK 0x0000FFFFL
+-#define DMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK_MASK 0xFFFF0000L
+-//DMIF_PG2_DPG_PIPE_STUTTER_CONTROL
+-#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
+-#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
+-#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
+-#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
+-#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
+-#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
+-#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
+-#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH__SHIFT 0x10
+-#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x14
+-#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x15
+-#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x16
+-#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x17
+-#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0x1a
+-#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0x1b
+-#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L
+-#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L
+-#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x00000020L
+-#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x00000040L
+-#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x00000080L
+-#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x00000400L
+-#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x00000800L
+-#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH_MASK 0x00010000L
+-#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x00100000L
+-#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x00200000L
+-#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x00400000L
+-#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x00800000L
+-#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x04000000L
+-#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x08000000L
+-//DMIF_PG2_DPG_PIPE_STUTTER_CONTROL2
+-#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x0
+-#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK__SHIFT 0x10
+-#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0x0000FFFFL
+-#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK 0xFFFF0000L
+-//DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL
+-#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE__SHIFT 0x0
+-#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE__SHIFT 0x1
+-#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
+-#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
+-#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
+-#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
+-#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK__SHIFT 0xf
+-#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE_MASK 0x00000001L
+-#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE_MASK 0x00000002L
+-#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L
+-#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x00000100L
+-#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON_MASK 0x00000200L
+-#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT_MASK 0x00000400L
+-#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK_MASK 0xFFFF8000L
+-//DMIF_PG2_DPG_REPEATER_PROGRAM
+-#define DMIF_PG2_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
+-#define DMIF_PG2_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
+-#define DMIF_PG2_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x00000007L
+-#define DMIF_PG2_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x00000070L
+-//DMIF_PG2_DPG_CHK_PRE_PROC_CNTL
+-#define DMIF_PG2_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0
+-#define DMIF_PG2_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x00000001L
+-//DMIF_PG2_DPG_DVMM_STATUS
+-#define DMIF_PG2_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED__SHIFT 0x0
+-#define DMIF_PG2_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED__SHIFT 0x1
+-#define DMIF_PG2_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR__SHIFT 0x4
+-#define DMIF_PG2_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR__SHIFT 0x5
+-#define DMIF_PG2_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_MASK 0x00000001L
+-#define DMIF_PG2_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_MASK 0x00000002L
+-#define DMIF_PG2_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR_MASK 0x00000010L
+-#define DMIF_PG2_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR_MASK 0x00000020L
+-
+-
+-// addressBlock: dce_dc_scl2_dispdec
+-//SCL2_SCL_COEF_RAM_SELECT
+-#define SCL2_SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0
+-#define SCL2_SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8
+-#define SCL2_SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10
+-#define SCL2_SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x0000000FL
+-#define SCL2_SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x00000F00L
+-#define SCL2_SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x00070000L
+-//SCL2_SCL_COEF_RAM_TAP_DATA
+-#define SCL2_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0
+-#define SCL2_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
+-#define SCL2_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10
+-#define SCL2_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
+-#define SCL2_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL
+-#define SCL2_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L
+-#define SCL2_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L
+-#define SCL2_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L
+-//SCL2_SCL_MODE
+-#define SCL2_SCL_MODE__SCL_MODE__SHIFT 0x0
+-#define SCL2_SCL_MODE__SCL_PSCL_EN__SHIFT 0x4
+-#define SCL2_SCL_MODE__SCL_MODE_MASK 0x00000003L
+-#define SCL2_SCL_MODE__SCL_PSCL_EN_MASK 0x00000010L
+-//SCL2_SCL_TAP_CONTROL
+-#define SCL2_SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0
+-#define SCL2_SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x8
+-#define SCL2_SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x00000007L
+-#define SCL2_SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0x00000F00L
+-//SCL2_SCL_CONTROL
+-#define SCL2_SCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
+-#define SCL2_SCL_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4
+-#define SCL2_SCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L
+-#define SCL2_SCL_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x00000010L
+-//SCL2_SCL_BYPASS_CONTROL
+-#define SCL2_SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT 0x0
+-#define SCL2_SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x00000003L
+-//SCL2_SCL_MANUAL_REPLICATE_CONTROL
+-#define SCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
+-#define SCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
+-#define SCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL
+-#define SCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L
+-//SCL2_SCL_AUTOMATIC_MODE_CONTROL
+-#define SCL2_SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0
+-#define SCL2_SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10
+-#define SCL2_SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x00000001L
+-#define SCL2_SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x00010000L
+-//SCL2_SCL_HORZ_FILTER_CONTROL
+-#define SCL2_SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT 0x0
+-#define SCL2_SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+-#define SCL2_SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK 0x00000001L
+-#define SCL2_SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
+-//SCL2_SCL_HORZ_FILTER_SCALE_RATIO
+-#define SCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
+-#define SCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL
+-//SCL2_SCL_HORZ_FILTER_INIT
+-#define SCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
+-#define SCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
+-#define SCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL
+-#define SCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L
+-//SCL2_SCL_VERT_FILTER_CONTROL
+-#define SCL2_SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT 0x0
+-#define SCL2_SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+-#define SCL2_SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK 0x00000001L
+-#define SCL2_SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
+-//SCL2_SCL_VERT_FILTER_SCALE_RATIO
+-#define SCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
+-#define SCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL
+-//SCL2_SCL_VERT_FILTER_INIT
+-#define SCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
+-#define SCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
+-#define SCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL
+-#define SCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x07000000L
+-//SCL2_SCL_VERT_FILTER_INIT_BOT
+-#define SCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
+-#define SCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
+-#define SCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL
+-#define SCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x07000000L
+-//SCL2_SCL_ROUND_OFFSET
+-#define SCL2_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0
+-#define SCL2_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10
+-#define SCL2_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0x0000FFFFL
+-#define SCL2_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xFFFF0000L
+-//SCL2_SCL_UPDATE
+-#define SCL2_SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
+-#define SCL2_SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8
+-#define SCL2_SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10
+-#define SCL2_SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18
+-#define SCL2_SCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L
+-#define SCL2_SCL_UPDATE__SCL_UPDATE_TAKEN_MASK 0x00000100L
+-#define SCL2_SCL_UPDATE__SCL_UPDATE_LOCK_MASK 0x00010000L
+-#define SCL2_SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x01000000L
+-//SCL2_SCL_F_SHARP_CONTROL
+-#define SCL2_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT 0x0
+-#define SCL2_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT 0x4
+-#define SCL2_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT 0x8
+-#define SCL2_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT 0xc
+-#define SCL2_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK 0x00000007L
+-#define SCL2_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK 0x00000010L
+-#define SCL2_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK 0x00000700L
+-#define SCL2_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK 0x00001000L
+-//SCL2_SCL_ALU_CONTROL
+-#define SCL2_SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0
+-#define SCL2_SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x00000001L
+-//SCL2_SCL_COEF_RAM_CONFLICT_STATUS
+-#define SCL2_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT 0x0
+-#define SCL2_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT 0x8
+-#define SCL2_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT 0xc
+-#define SCL2_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10
+-#define SCL2_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK 0x00000001L
+-#define SCL2_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK 0x00000100L
+-#define SCL2_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK 0x00001000L
+-#define SCL2_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK 0x00010000L
+-//SCL2_VIEWPORT_START_SECONDARY
+-#define SCL2_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0
+-#define SCL2_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10
+-#define SCL2_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x00003FFFL
+-#define SCL2_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3FFF0000L
+-//SCL2_VIEWPORT_START
+-#define SCL2_VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0
+-#define SCL2_VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10
+-#define SCL2_VIEWPORT_START__VIEWPORT_Y_START_MASK 0x00003FFFL
+-#define SCL2_VIEWPORT_START__VIEWPORT_X_START_MASK 0x3FFF0000L
+-//SCL2_VIEWPORT_SIZE
+-#define SCL2_VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0
+-#define SCL2_VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10
+-#define SCL2_VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x00003FFFL
+-#define SCL2_VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x3FFF0000L
+-//SCL2_EXT_OVERSCAN_LEFT_RIGHT
+-#define SCL2_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
+-#define SCL2_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
+-#define SCL2_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL
+-#define SCL2_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L
+-//SCL2_EXT_OVERSCAN_TOP_BOTTOM
+-#define SCL2_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
+-#define SCL2_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
+-#define SCL2_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL
+-#define SCL2_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L
+-//SCL2_SCL_MODE_CHANGE_DET1
+-#define SCL2_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0
+-#define SCL2_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4
+-#define SCL2_SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7
+-#define SCL2_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x00000001L
+-#define SCL2_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x00000010L
+-#define SCL2_SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0x0FFFFF80L
+-//SCL2_SCL_MODE_CHANGE_DET2
+-#define SCL2_SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0
+-#define SCL2_SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x001FFFFFL
+-//SCL2_SCL_MODE_CHANGE_DET3
+-#define SCL2_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0
+-#define SCL2_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10
+-#define SCL2_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x00003FFFL
+-#define SCL2_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3FFF0000L
+-//SCL2_SCL_MODE_CHANGE_MASK
+-#define SCL2_SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0
+-#define SCL2_SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x00000001L
+-
+-
+-// addressBlock: dce_dc_blnd2_dispdec
+-//BLND2_BLND_CONTROL
+-#define BLND2_BLND_CONTROL__BLND_GLOBAL_GAIN__SHIFT 0x0
+-#define BLND2_BLND_CONTROL__BLND_MODE__SHIFT 0x8
+-#define BLND2_BLND_CONTROL__BLND_STEREO_TYPE__SHIFT 0xa
+-#define BLND2_BLND_CONTROL__BLND_STEREO_POLARITY__SHIFT 0xc
+-#define BLND2_BLND_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT 0xd
+-#define BLND2_BLND_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10
+-#define BLND2_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x12
+-#define BLND2_BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14
+-#define BLND2_BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18
+-#define BLND2_BLND_CONTROL__BLND_GLOBAL_GAIN_MASK 0x000000FFL
+-#define BLND2_BLND_CONTROL__BLND_MODE_MASK 0x00000300L
+-#define BLND2_BLND_CONTROL__BLND_STEREO_TYPE_MASK 0x00000C00L
+-#define BLND2_BLND_CONTROL__BLND_STEREO_POLARITY_MASK 0x00001000L
+-#define BLND2_BLND_CONTROL__BLND_FEEDTHROUGH_EN_MASK 0x00002000L
+-#define BLND2_BLND_CONTROL__BLND_ALPHA_MODE_MASK 0x00030000L
+-#define BLND2_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00040000L
+-#define BLND2_BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x00100000L
+-#define BLND2_BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xFF000000L
+-//BLND2_BLND_SM_CONTROL2
+-#define BLND2_BLND_SM_CONTROL2__SM_MODE__SHIFT 0x0
+-#define BLND2_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4
+-#define BLND2_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5
+-#define BLND2_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
+-#define BLND2_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
+-#define BLND2_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18
+-#define BLND2_BLND_SM_CONTROL2__SM_MODE_MASK 0x00000007L
+-#define BLND2_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x00000010L
+-#define BLND2_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x00000020L
+-#define BLND2_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L
+-#define BLND2_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L
+-#define BLND2_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x01000000L
+-//BLND2_BLND_CONTROL2
+-#define BLND2_BLND_CONTROL2__PTI_ENABLE__SHIFT 0x0
+-#define BLND2_BLND_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT 0x4
+-#define BLND2_BLND_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT 0x6
+-#define BLND2_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT 0x7
+-#define BLND2_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT 0x8
+-#define BLND2_BLND_CONTROL2__PTI_ENABLE_MASK 0x00000001L
+-#define BLND2_BLND_CONTROL2__PTI_NEW_PIXEL_GAP_MASK 0x00000030L
+-#define BLND2_BLND_CONTROL2__BLND_NEW_PIXEL_MODE_MASK 0x00000040L
+-#define BLND2_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK 0x00000080L
+-#define BLND2_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK 0x00000100L
+-//BLND2_BLND_UPDATE
+-#define BLND2_BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0
+-#define BLND2_BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8
+-#define BLND2_BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10
+-#define BLND2_BLND_UPDATE__BLND_UPDATE_PENDING_MASK 0x00000001L
+-#define BLND2_BLND_UPDATE__BLND_UPDATE_TAKEN_MASK 0x00000100L
+-#define BLND2_BLND_UPDATE__BLND_UPDATE_LOCK_MASK 0x00010000L
+-//BLND2_BLND_UNDERFLOW_INTERRUPT
+-#define BLND2_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0
+-#define BLND2_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8
+-#define BLND2_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc
+-#define BLND2_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10
+-#define BLND2_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x00000001L
+-#define BLND2_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x00000100L
+-#define BLND2_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x00001000L
+-#define BLND2_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x00030000L
+-//BLND2_BLND_V_UPDATE_LOCK
+-#define BLND2_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0
+-#define BLND2_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1
+-#define BLND2_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10
+-#define BLND2_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c
+-#define BLND2_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT 0x1d
+-#define BLND2_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT 0x1f
+-#define BLND2_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x00000001L
+-#define BLND2_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x00000002L
+-#define BLND2_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x00010000L
+-#define BLND2_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000L
+-#define BLND2_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK 0x20000000L
+-#define BLND2_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK 0x80000000L
+-//BLND2_BLND_REG_UPDATE_STATUS
+-#define BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT 0x0
+-#define BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT 0x1
+-#define BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2
+-#define BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3
+-#define BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT 0x6
+-#define BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT 0x7
+-#define BLND2_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT 0x8
+-#define BLND2_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT 0x9
+-#define BLND2_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT 0xa
+-#define BLND2_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT 0xb
+-#define BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK 0x00000001L
+-#define BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK 0x00000002L
+-#define BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK 0x00000004L
+-#define BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK 0x00000008L
+-#define BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK 0x00000040L
+-#define BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK 0x00000080L
+-#define BLND2_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK 0x00000100L
+-#define BLND2_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK 0x00000200L
+-#define BLND2_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK 0x00000400L
+-#define BLND2_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK 0x00000800L
+-
+-
+-// addressBlock: dce_dc_crtc2_dispdec
+-//CRTC2_CRTC_H_BLANK_EARLY_NUM
+-#define CRTC2_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0
+-#define CRTC2_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10
+-#define CRTC2_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x000003FFL
+-#define CRTC2_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x00010000L
+-//CRTC2_CRTC_H_TOTAL
+-#define CRTC2_CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0
+-#define CRTC2_CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x00003FFFL
+-//CRTC2_CRTC_H_BLANK_START_END
+-#define CRTC2_CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0
+-#define CRTC2_CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10
+-#define CRTC2_CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x00003FFFL
+-#define CRTC2_CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3FFF0000L
+-//CRTC2_CRTC_H_SYNC_A
+-#define CRTC2_CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0
+-#define CRTC2_CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10
+-#define CRTC2_CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x00003FFFL
+-#define CRTC2_CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3FFF0000L
+-//CRTC2_CRTC_H_SYNC_A_CNTL
+-#define CRTC2_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0
+-#define CRTC2_CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10
+-#define CRTC2_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11
+-#define CRTC2_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x00000001L
+-#define CRTC2_CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x00010000L
+-#define CRTC2_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x00020000L
+-//CRTC2_CRTC_H_SYNC_B
+-#define CRTC2_CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0
+-#define CRTC2_CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10
+-#define CRTC2_CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x00003FFFL
+-#define CRTC2_CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x3FFF0000L
+-//CRTC2_CRTC_H_SYNC_B_CNTL
+-#define CRTC2_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0
+-#define CRTC2_CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10
+-#define CRTC2_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11
+-#define CRTC2_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x00000001L
+-#define CRTC2_CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x00010000L
+-#define CRTC2_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x00020000L
+-//CRTC2_CRTC_VBI_END
+-#define CRTC2_CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x0
+-#define CRTC2_CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x10
+-#define CRTC2_CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x00003FFFL
+-#define CRTC2_CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x3FFF0000L
+-//CRTC2_CRTC_V_TOTAL
+-#define CRTC2_CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0
+-#define CRTC2_CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x00003FFFL
+-//CRTC2_CRTC_V_TOTAL_MIN
+-#define CRTC2_CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0
+-#define CRTC2_CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x00003FFFL
+-//CRTC2_CRTC_V_TOTAL_MAX
+-#define CRTC2_CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0
+-#define CRTC2_CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10
+-#define CRTC2_CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x00003FFFL
+-#define CRTC2_CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x00010000L
+-//CRTC2_CRTC_V_TOTAL_CONTROL
+-#define CRTC2_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0
+-#define CRTC2_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4
+-#define CRTC2_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8
+-#define CRTC2_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc
+-#define CRTC2_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf
+-#define CRTC2_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10
+-#define CRTC2_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x00000001L
+-#define CRTC2_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x00000010L
+-#define CRTC2_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x00000100L
+-#define CRTC2_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x00001000L
+-#define CRTC2_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00008000L
+-#define CRTC2_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L
+-//CRTC2_CRTC_V_TOTAL_INT_STATUS
+-#define CRTC2_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0
+-#define CRTC2_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4
+-#define CRTC2_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8
+-#define CRTC2_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc
+-#define CRTC2_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L
+-#define CRTC2_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L
+-#define CRTC2_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L
+-#define CRTC2_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L
+-//CRTC2_CRTC_VSYNC_NOM_INT_STATUS
+-#define CRTC2_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0
+-#define CRTC2_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4
+-#define CRTC2_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x00000001L
+-#define CRTC2_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L
+-//CRTC2_CRTC_V_BLANK_START_END
+-#define CRTC2_CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0
+-#define CRTC2_CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10
+-#define CRTC2_CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x00003FFFL
+-#define CRTC2_CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3FFF0000L
+-//CRTC2_CRTC_V_SYNC_A
+-#define CRTC2_CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0
+-#define CRTC2_CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10
+-#define CRTC2_CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x00003FFFL
+-#define CRTC2_CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3FFF0000L
+-//CRTC2_CRTC_V_SYNC_A_CNTL
+-#define CRTC2_CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0
+-#define CRTC2_CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x00000001L
+-//CRTC2_CRTC_V_SYNC_B
+-#define CRTC2_CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0
+-#define CRTC2_CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10
+-#define CRTC2_CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x00003FFFL
+-#define CRTC2_CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x3FFF0000L
+-//CRTC2_CRTC_V_SYNC_B_CNTL
+-#define CRTC2_CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0
+-#define CRTC2_CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x00000001L
+-//CRTC2_CRTC_DTMTEST_CNTL
+-#define CRTC2_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0
+-#define CRTC2_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1
+-#define CRTC2_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x00000001L
+-#define CRTC2_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x0000001EL
+-//CRTC2_CRTC_DTMTEST_STATUS_POSITION
+-#define CRTC2_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0
+-#define CRTC2_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10
+-#define CRTC2_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x00003FFFL
+-#define CRTC2_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x3FFF0000L
+-//CRTC2_CRTC_TRIGA_CNTL
+-#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0
+-#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5
+-#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8
+-#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9
+-#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa
+-#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb
+-#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
+-#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
+-#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14
+-#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18
+-#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f
+-#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x0000001FL
+-#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0x000000E0L
+-#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000100L
+-#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x00000200L
+-#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x00000400L
+-#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x00000800L
+-#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
+-#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
+-#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L
+-#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1F000000L
+-#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000L
+-//CRTC2_CRTC_TRIGA_MANUAL_TRIG
+-#define CRTC2_CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0
+-#define CRTC2_CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x00000001L
+-//CRTC2_CRTC_TRIGB_CNTL
+-#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0
+-#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5
+-#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8
+-#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9
+-#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa
+-#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb
+-#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
+-#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
+-#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14
+-#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18
+-#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f
+-#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x0000001FL
+-#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0x000000E0L
+-#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000100L
+-#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x00000200L
+-#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x00000400L
+-#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x00000800L
+-#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
+-#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
+-#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L
+-#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1F000000L
+-#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000L
+-//CRTC2_CRTC_TRIGB_MANUAL_TRIG
+-#define CRTC2_CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0
+-#define CRTC2_CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x00000001L
+-//CRTC2_CRTC_FORCE_COUNT_NOW_CNTL
+-#define CRTC2_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0
+-#define CRTC2_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4
+-#define CRTC2_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8
+-#define CRTC2_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10
+-#define CRTC2_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18
+-#define CRTC2_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x00000003L
+-#define CRTC2_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L
+-#define CRTC2_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L
+-#define CRTC2_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L
+-#define CRTC2_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L
+-//CRTC2_CRTC_FLOW_CONTROL
+-#define CRTC2_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0
+-#define CRTC2_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8
+-#define CRTC2_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10
+-#define CRTC2_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18
+-#define CRTC2_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL
+-#define CRTC2_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x00000100L
+-#define CRTC2_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L
+-#define CRTC2_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L
+-//CRTC2_CRTC_STEREO_FORCE_NEXT_EYE
+-#define CRTC2_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0
+-#define CRTC2_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER__SHIFT 0x8
+-#define CRTC2_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER__SHIFT 0x10
+-#define CRTC2_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L
+-#define CRTC2_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L
+-#define CRTC2_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L
+-//CRTC2_CRTC_AVSYNC_COUNTER
+-#define CRTC2_CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER__SHIFT 0x0
+-#define CRTC2_CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER_MASK 0xFFFFFFFFL
+-//CRTC2_CRTC_CONTROL
+-#define CRTC2_CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x0
+-#define CRTC2_CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4
+-#define CRTC2_CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8
+-#define CRTC2_CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc
+-#define CRTC2_CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd
+-#define CRTC2_CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe
+-#define CRTC2_CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10
+-#define CRTC2_CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14
+-#define CRTC2_CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d
+-#define CRTC2_CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e
+-#define CRTC2_CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f
+-#define CRTC2_CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x00000001L
+-#define CRTC2_CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x00000010L
+-#define CRTC2_CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x00000300L
+-#define CRTC2_CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x00001000L
+-#define CRTC2_CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x00002000L
+-#define CRTC2_CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x00004000L
+-#define CRTC2_CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x00010000L
+-#define CRTC2_CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x00700000L
+-#define CRTC2_CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000L
+-#define CRTC2_CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L
+-#define CRTC2_CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L
+-//CRTC2_CRTC_BLANK_CONTROL
+-#define CRTC2_CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0
+-#define CRTC2_CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8
+-#define CRTC2_CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10
+-#define CRTC2_CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x00000001L
+-#define CRTC2_CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x00000100L
+-#define CRTC2_CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x00010000L
+-//CRTC2_CRTC_INTERLACE_CONTROL
+-#define CRTC2_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0
+-#define CRTC2_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10
+-#define CRTC2_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x00000001L
+-#define CRTC2_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L
+-//CRTC2_CRTC_INTERLACE_STATUS
+-#define CRTC2_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0
+-#define CRTC2_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1
+-#define CRTC2_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x00000001L
+-#define CRTC2_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x00000002L
+-//CRTC2_CRTC_FIELD_INDICATION_CONTROL
+-#define CRTC2_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0
+-#define CRTC2_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1
+-#define CRTC2_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x00000001L
+-#define CRTC2_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x00000002L
+-//CRTC2_CRTC_PIXEL_DATA_READBACK0
+-#define CRTC2_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0
+-#define CRTC2_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10
+-#define CRTC2_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0x00000FFFL
+-#define CRTC2_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0x0FFF0000L
+-//CRTC2_CRTC_PIXEL_DATA_READBACK1
+-#define CRTC2_CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0
+-#define CRTC2_CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0x00000FFFL
+-//CRTC2_CRTC_STATUS
+-#define CRTC2_CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x0
+-#define CRTC2_CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1
+-#define CRTC2_CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x2
+-#define CRTC2_CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x3
+-#define CRTC2_CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x4
+-#define CRTC2_CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5
+-#define CRTC2_CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x10
+-#define CRTC2_CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11
+-#define CRTC2_CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x12
+-#define CRTC2_CRTC_STATUS__CRTC_V_BLANK_MASK 0x00000001L
+-#define CRTC2_CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x00000002L
+-#define CRTC2_CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x00000004L
+-#define CRTC2_CRTC_STATUS__CRTC_V_UPDATE_MASK 0x00000008L
+-#define CRTC2_CRTC_STATUS__CRTC_V_START_LINE_MASK 0x00000010L
+-#define CRTC2_CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x00000020L
+-#define CRTC2_CRTC_STATUS__CRTC_H_BLANK_MASK 0x00010000L
+-#define CRTC2_CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x00020000L
+-#define CRTC2_CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x00040000L
+-//CRTC2_CRTC_STATUS_POSITION
+-#define CRTC2_CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0
+-#define CRTC2_CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10
+-#define CRTC2_CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x00003FFFL
+-#define CRTC2_CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x3FFF0000L
+-//CRTC2_CRTC_NOM_VERT_POSITION
+-#define CRTC2_CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0
+-#define CRTC2_CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x00003FFFL
+-//CRTC2_CRTC_STATUS_FRAME_COUNT
+-#define CRTC2_CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0
+-#define CRTC2_CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0x00FFFFFFL
+-//CRTC2_CRTC_STATUS_VF_COUNT
+-#define CRTC2_CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0
+-#define CRTC2_CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x3FFFFFFFL
+-//CRTC2_CRTC_STATUS_HV_COUNT
+-#define CRTC2_CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0
+-#define CRTC2_CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x3FFFFFFFL
+-//CRTC2_CRTC_COUNT_CONTROL
+-#define CRTC2_CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0
+-#define CRTC2_CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1
+-#define CRTC2_CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x00000001L
+-#define CRTC2_CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x0000001EL
+-//CRTC2_CRTC_COUNT_RESET
+-#define CRTC2_CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0
+-#define CRTC2_CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x00000001L
+-//CRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE
+-#define CRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0
+-#define CRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L
+-//CRTC2_CRTC_VERT_SYNC_CONTROL
+-#define CRTC2_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0
+-#define CRTC2_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8
+-#define CRTC2_CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10
+-#define CRTC2_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L
+-#define CRTC2_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L
+-#define CRTC2_CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L
+-//CRTC2_CRTC_STEREO_STATUS
+-#define CRTC2_CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0
+-#define CRTC2_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8
+-#define CRTC2_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10
+-#define CRTC2_CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG__SHIFT 0x14
+-#define CRTC2_CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18
+-#define CRTC2_CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x00000001L
+-#define CRTC2_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x00000100L
+-#define CRTC2_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x00010000L
+-#define CRTC2_CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG_MASK 0x00100000L
+-#define CRTC2_CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L
+-//CRTC2_CRTC_STEREO_CONTROL
+-#define CRTC2_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0
+-#define CRTC2_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf
+-#define CRTC2_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10
+-#define CRTC2_CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11
+-#define CRTC2_CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12
+-#define CRTC2_CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM__SHIFT 0x13
+-#define CRTC2_CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14
+-#define CRTC2_CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18
+-#define CRTC2_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00003FFFL
+-#define CRTC2_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L
+-#define CRTC2_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x00010000L
+-#define CRTC2_CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L
+-#define CRTC2_CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L
+-#define CRTC2_CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM_MASK 0x00080000L
+-#define CRTC2_CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L
+-#define CRTC2_CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x01000000L
+-//CRTC2_CRTC_SNAPSHOT_STATUS
+-#define CRTC2_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0
+-#define CRTC2_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1
+-#define CRTC2_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2
+-#define CRTC2_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x00000001L
+-#define CRTC2_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x00000002L
+-#define CRTC2_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L
+-//CRTC2_CRTC_SNAPSHOT_CONTROL
+-#define CRTC2_CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0
+-#define CRTC2_CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L
+-//CRTC2_CRTC_SNAPSHOT_POSITION
+-#define CRTC2_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0
+-#define CRTC2_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10
+-#define CRTC2_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x00003FFFL
+-#define CRTC2_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x3FFF0000L
+-//CRTC2_CRTC_SNAPSHOT_FRAME
+-#define CRTC2_CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0
+-#define CRTC2_CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL
+-//CRTC2_CRTC_START_LINE_CONTROL
+-#define CRTC2_CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0
+-#define CRTC2_CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x1
+-#define CRTC2_CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x2
+-#define CRTC2_CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x8
+-#define CRTC2_CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc
+-#define CRTC2_CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x00000001L
+-#define CRTC2_CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x00000002L
+-#define CRTC2_CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x00000004L
+-#define CRTC2_CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x00000100L
+-#define CRTC2_CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0x000FF000L
+-//CRTC2_CRTC_INTERRUPT_CONTROL
+-#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0
+-#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1
+-#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4
+-#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5
+-#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8
+-#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9
+-#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10
+-#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11
+-#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18
+-#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19
+-#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a
+-#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b
+-#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c
+-#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d
+-#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e
+-#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f
+-#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x00000001L
+-#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x00000002L
+-#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x00000010L
+-#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x00000020L
+-#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L
+-#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L
+-#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L
+-#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L
+-#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x01000000L
+-#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x02000000L
+-#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x04000000L
+-#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x08000000L
+-#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000L
+-#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000L
+-#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L
+-#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L
+-//CRTC2_CRTC_UPDATE_LOCK
+-#define CRTC2_CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0
+-#define CRTC2_CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x00000001L
+-//CRTC2_CRTC_DOUBLE_BUFFER_CONTROL
+-#define CRTC2_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0
+-#define CRTC2_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8
+-#define CRTC2_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10
+-#define CRTC2_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18
+-#define CRTC2_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x19
+-#define CRTC2_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x00000001L
+-#define CRTC2_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x00000100L
+-#define CRTC2_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L
+-#define CRTC2_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x01000000L
+-#define CRTC2_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x02000000L
+-//CRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE
+-#define CRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0
+-#define CRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x00000001L
+-//CRTC2_CRTC_TEST_PATTERN_CONTROL
+-#define CRTC2_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0
+-#define CRTC2_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8
+-#define CRTC2_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10
+-#define CRTC2_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18
+-#define CRTC2_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x00000001L
+-#define CRTC2_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x00000700L
+-#define CRTC2_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L
+-#define CRTC2_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xFF000000L
+-//CRTC2_CRTC_TEST_PATTERN_PARAMETERS
+-#define CRTC2_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0
+-#define CRTC2_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4
+-#define CRTC2_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8
+-#define CRTC2_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc
+-#define CRTC2_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10
+-#define CRTC2_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0x0000000FL
+-#define CRTC2_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0x000000F0L
+-#define CRTC2_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0x00000F00L
+-#define CRTC2_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0x0000F000L
+-#define CRTC2_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xFFFF0000L
+-//CRTC2_CRTC_TEST_PATTERN_COLOR
+-#define CRTC2_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0
+-#define CRTC2_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10
+-#define CRTC2_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0x0000FFFFL
+-#define CRTC2_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x003F0000L
+-//CRTC2_CRTC_MASTER_UPDATE_LOCK
+-#define CRTC2_CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0
+-#define CRTC2_CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8
+-#define CRTC2_CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK__SHIFT 0x10
+-#define CRTC2_CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x00000001L
+-#define CRTC2_CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x00000100L
+-#define CRTC2_CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK_MASK 0x00010000L
+-//CRTC2_CRTC_MASTER_UPDATE_MODE
+-#define CRTC2_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0
+-#define CRTC2_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10
+-#define CRTC2_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x00000007L
+-#define CRTC2_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00030000L
+-//CRTC2_CRTC_MVP_INBAND_CNTL_INSERT
+-#define CRTC2_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0
+-#define CRTC2_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8
+-#define CRTC2_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x00000003L
+-#define CRTC2_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xFFFFFF00L
+-//CRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER
+-#define CRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0
+-#define CRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0x000000FFL
+-//CRTC2_CRTC_MVP_STATUS
+-#define CRTC2_CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0
+-#define CRTC2_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4
+-#define CRTC2_CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10
+-#define CRTC2_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14
+-#define CRTC2_CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x00000001L
+-#define CRTC2_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x00000010L
+-#define CRTC2_CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x00010000L
+-#define CRTC2_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x00100000L
+-//CRTC2_CRTC_MASTER_EN
+-#define CRTC2_CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0
+-#define CRTC2_CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x00000001L
+-//CRTC2_CRTC_ALLOW_STOP_OFF_V_CNT
+-#define CRTC2_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0
+-#define CRTC2_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10
+-#define CRTC2_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0x000000FFL
+-#define CRTC2_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x00010000L
+-//CRTC2_CRTC_V_UPDATE_INT_STATUS
+-#define CRTC2_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0
+-#define CRTC2_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8
+-#define CRTC2_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x00000001L
+-#define CRTC2_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x00000100L
+-//CRTC2_CRTC_OVERSCAN_COLOR
+-#define CRTC2_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0
+-#define CRTC2_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa
+-#define CRTC2_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14
+-#define CRTC2_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x000003FFL
+-#define CRTC2_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0x000FFC00L
+-#define CRTC2_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3FF00000L
+-//CRTC2_CRTC_OVERSCAN_COLOR_EXT
+-#define CRTC2_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0
+-#define CRTC2_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8
+-#define CRTC2_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10
+-#define CRTC2_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x00000003L
+-#define CRTC2_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x00000300L
+-#define CRTC2_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x00030000L
+-//CRTC2_CRTC_BLANK_DATA_COLOR
+-#define CRTC2_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0
+-#define CRTC2_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa
+-#define CRTC2_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14
+-#define CRTC2_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL
+-#define CRTC2_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L
+-#define CRTC2_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L
+-//CRTC2_CRTC_BLANK_DATA_COLOR_EXT
+-#define CRTC2_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0
+-#define CRTC2_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8
+-#define CRTC2_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10
+-#define CRTC2_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x00000003L
+-#define CRTC2_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00000300L
+-#define CRTC2_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x00030000L
+-//CRTC2_CRTC_BLACK_COLOR
+-#define CRTC2_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0
+-#define CRTC2_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa
+-#define CRTC2_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14
+-#define CRTC2_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x000003FFL
+-#define CRTC2_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0x000FFC00L
+-#define CRTC2_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3FF00000L
+-//CRTC2_CRTC_BLACK_COLOR_EXT
+-#define CRTC2_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0
+-#define CRTC2_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8
+-#define CRTC2_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10
+-#define CRTC2_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x00000003L
+-#define CRTC2_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x00000300L
+-#define CRTC2_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x00030000L
+-//CRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION
+-#define CRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0
+-#define CRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10
+-#define CRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00003FFFL
+-#define CRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x3FFF0000L
+-//CRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL
+-#define CRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4
+-#define CRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8
+-#define CRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc
+-#define CRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10
+-#define CRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14
+-#define CRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18
+-#define CRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L
+-#define CRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L
+-#define CRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L
+-#define CRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L
+-#define CRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L
+-#define CRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L
+-//CRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION
+-#define CRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0
+-#define CRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00003FFFL
+-//CRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL
+-#define CRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8
+-#define CRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc
+-#define CRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10
+-#define CRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14
+-#define CRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18
+-#define CRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L
+-#define CRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L
+-#define CRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L
+-#define CRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L
+-#define CRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L
+-//CRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION
+-#define CRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0
+-#define CRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00003FFFL
+-//CRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL
+-#define CRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8
+-#define CRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc
+-#define CRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10
+-#define CRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14
+-#define CRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18
+-#define CRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L
+-#define CRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L
+-#define CRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L
+-#define CRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L
+-#define CRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L
+-//CRTC2_CRTC_CRC_CNTL
+-#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0
+-#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4
+-#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8
+-#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc
+-#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
+-#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14
+-#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18
+-#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC_EN_MASK 0x00000001L
+-#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x00000010L
+-#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x00000300L
+-#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x00003000L
+-#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
+-#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x00700000L
+-#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x07000000L
+-//CRTC2_CRTC_CRC0_WINDOWA_X_CONTROL
+-#define CRTC2_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0
+-#define CRTC2_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10
+-#define CRTC2_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x00003FFFL
+-#define CRTC2_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3FFF0000L
+-//CRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL
+-#define CRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0
+-#define CRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10
+-#define CRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x00003FFFL
+-#define CRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3FFF0000L
+-//CRTC2_CRTC_CRC0_WINDOWB_X_CONTROL
+-#define CRTC2_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0
+-#define CRTC2_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10
+-#define CRTC2_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x00003FFFL
+-#define CRTC2_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3FFF0000L
+-//CRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL
+-#define CRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0
+-#define CRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10
+-#define CRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x00003FFFL
+-#define CRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3FFF0000L
+-//CRTC2_CRTC_CRC0_DATA_RG
+-#define CRTC2_CRTC_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0
+-#define CRTC2_CRTC_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10
+-#define CRTC2_CRTC_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL
+-#define CRTC2_CRTC_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L
+-//CRTC2_CRTC_CRC0_DATA_B
+-#define CRTC2_CRTC_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0
+-#define CRTC2_CRTC_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL
+-//CRTC2_CRTC_CRC1_WINDOWA_X_CONTROL
+-#define CRTC2_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0
+-#define CRTC2_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10
+-#define CRTC2_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x00003FFFL
+-#define CRTC2_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3FFF0000L
+-//CRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL
+-#define CRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0
+-#define CRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10
+-#define CRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x00003FFFL
+-#define CRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3FFF0000L
+-//CRTC2_CRTC_CRC1_WINDOWB_X_CONTROL
+-#define CRTC2_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0
+-#define CRTC2_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10
+-#define CRTC2_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x00003FFFL
+-#define CRTC2_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3FFF0000L
+-//CRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL
+-#define CRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0
+-#define CRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10
+-#define CRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x00003FFFL
+-#define CRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3FFF0000L
+-//CRTC2_CRTC_CRC1_DATA_RG
+-#define CRTC2_CRTC_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0
+-#define CRTC2_CRTC_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10
+-#define CRTC2_CRTC_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL
+-#define CRTC2_CRTC_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L
+-//CRTC2_CRTC_CRC1_DATA_B
+-#define CRTC2_CRTC_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0
+-#define CRTC2_CRTC_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL
+-//CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE__SHIFT 0x0
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__SHIFT 0x3
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__SHIFT 0x4
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__SHIFT 0x5
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__SHIFT 0x8
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__SHIFT 0x9
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__SHIFT 0xc
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__SHIFT 0xd
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__SHIFT 0xe
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE__SHIFT 0x18
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE__SHIFT 0x1c
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE_MASK 0x00000003L
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_MASK 0x00000008L
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_MASK 0x00000010L
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_MASK 0x00000060L
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_MASK 0x00000100L
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_MASK 0x00000200L
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_MASK 0x00001000L
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_MASK 0x00002000L
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_MASK 0x00004000L
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE_MASK 0x07000000L
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE_MASK 0x70000000L
+-//CRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X__SHIFT 0x0
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y__SHIFT 0x10
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X_MASK 0x00003FFFL
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y_MASK 0x3FFF0000L
+-//CRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X__SHIFT 0x0
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y__SHIFT 0x10
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X_MASK 0x00003FFFL
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y_MASK 0x3FFF0000L
+-//CRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__SHIFT 0x0
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS__SHIFT 0x4
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS__SHIFT 0x8
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__SHIFT 0x10
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__SHIFT 0x14
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__SHIFT 0x1d
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_MASK 0x00000001L
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS_MASK 0x00000010L
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS_MASK 0x00000100L
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_MASK 0x00010000L
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_MASK 0x00100000L
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_MASK 0xE0000000L
+-//CRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE__SHIFT 0x0
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS__SHIFT 0x4
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS__SHIFT 0x8
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR__SHIFT 0x10
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE__SHIFT 0x14
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE_MASK 0x00000001L
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS_MASK 0x00000010L
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS_MASK 0x00000100L
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR_MASK 0x00010000L
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE_MASK 0x00100000L
+-//CRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__SHIFT 0x0
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS__SHIFT 0x4
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS__SHIFT 0x8
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__SHIFT 0x10
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__SHIFT 0x14
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_MASK 0x00000001L
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS_MASK 0x00000010L
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS_MASK 0x00000100L
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_MASK 0x00010000L
+-#define CRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_MASK 0x00100000L
+-//CRTC2_CRTC_STATIC_SCREEN_CONTROL
+-#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0
+-#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10
+-#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18
+-#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19
+-#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a
+-#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b
+-#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c
+-#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e
+-#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f
+-#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL
+-#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L
+-#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x01000000L
+-#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x02000000L
+-#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x04000000L
+-#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x08000000L
+-#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000L
+-#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L
+-#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L
+-//CRTC2_CRTC_3D_STRUCTURE_CONTROL
+-#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0
+-#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4
+-#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8
+-#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc
+-#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10
+-#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11
+-#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12
+-#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x00000001L
+-#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x00000010L
+-#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L
+-#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L
+-#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L
+-#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L
+-#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L
+-//CRTC2_CRTC_GSL_VSYNC_GAP
+-#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0
+-#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8
+-#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10
+-#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11
+-#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13
+-#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14
+-#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17
+-#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18
+-#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL
+-#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L
+-#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L
+-#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x00060000L
+-#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L
+-#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L
+-#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L
+-#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xFF000000L
+-//CRTC2_CRTC_GSL_WINDOW
+-#define CRTC2_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0
+-#define CRTC2_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10
+-#define CRTC2_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x00003FFFL
+-#define CRTC2_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x3FFF0000L
+-//CRTC2_CRTC_GSL_CONTROL
+-#define CRTC2_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0
+-#define CRTC2_CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10
+-#define CRTC2_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c
+-#define CRTC2_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x00003FFFL
+-#define CRTC2_CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x001F0000L
+-#define CRTC2_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L
+-//CRTC2_CRTC_RANGE_TIMING_INT_STATUS
+-#define CRTC2_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0
+-#define CRTC2_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4
+-#define CRTC2_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8
+-#define CRTC2_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc
+-#define CRTC2_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10
+-#define CRTC2_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L
+-#define CRTC2_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L
+-#define CRTC2_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L
+-#define CRTC2_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L
+-#define CRTC2_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L
+-//CRTC2_CRTC_DRR_CONTROL
+-#define CRTC2_CRTC_DRR_CONTROL__CRTC_XDMA_PREFETCH_DELAY__SHIFT 0x0
+-#define CRTC2_CRTC_DRR_CONTROL__CRTC_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0xe
+-#define CRTC2_CRTC_DRR_CONTROL__CRTC_SET_V_TOTAL_MIN_AUTO_DIS__SHIFT 0x1c
+-#define CRTC2_CRTC_DRR_CONTROL__CRTC_DRR_MODE_DBUF_UPDATE_MODE__SHIFT 0x1d
+-#define CRTC2_CRTC_DRR_CONTROL__CRTC_XDMA_PREFETCH_DELAY_MASK 0x00003FFFL
+-#define CRTC2_CRTC_DRR_CONTROL__CRTC_V_TOTAL_LAST_USED_BY_DRR_MASK 0x0FFFC000L
+-#define CRTC2_CRTC_DRR_CONTROL__CRTC_SET_V_TOTAL_MIN_AUTO_DIS_MASK 0x10000000L
+-#define CRTC2_CRTC_DRR_CONTROL__CRTC_DRR_MODE_DBUF_UPDATE_MODE_MASK 0x60000000L
+-
+-
+-// addressBlock: dce_dc_fmt2_dispdec
+-//FMT2_FMT_CLAMP_COMPONENT_R
+-#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0
+-#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10
+-#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL
+-#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L
+-//FMT2_FMT_CLAMP_COMPONENT_G
+-#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0
+-#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10
+-#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL
+-#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L
+-//FMT2_FMT_CLAMP_COMPONENT_B
+-#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0
+-#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10
+-#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL
+-#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L
+-//FMT2_FMT_DYNAMIC_EXP_CNTL
+-#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0
+-#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4
+-#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L
+-#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L
+-//FMT2_FMT_CONTROL
+-#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0
+-#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT 0x4
+-#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8
+-#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc
+-#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10
+-#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12
+-#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14
+-#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15
+-#define FMT2_FMT_CONTROL__FMT_SRC_SELECT__SHIFT 0x18
+-#define FMT2_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED__SHIFT 0x1e
+-#define FMT2_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_CLEAR__SHIFT 0x1f
+-#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L
+-#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK 0x00000010L
+-#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L
+-#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L
+-#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L
+-#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L
+-#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L
+-#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L
+-#define FMT2_FMT_CONTROL__FMT_SRC_SELECT_MASK 0x07000000L
+-#define FMT2_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_MASK 0x40000000L
+-#define FMT2_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_CLEAR_MASK 0x80000000L
+-//FMT2_FMT_BIT_DEPTH_CONTROL
+-#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0
+-#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1
+-#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4
+-#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8
+-#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9
+-#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb
+-#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd
+-#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe
+-#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf
+-#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10
+-#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11
+-#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15
+-#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18
+-#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19
+-#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a
+-#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c
+-#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e
+-#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L
+-#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L
+-#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L
+-#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L
+-#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L
+-#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L
+-#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L
+-#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L
+-#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L
+-#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L
+-#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L
+-#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L
+-#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L
+-#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L
+-#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L
+-#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L
+-#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L
+-//FMT2_FMT_DITHER_RAND_R_SEED
+-#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0
+-#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10
+-#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL
+-#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L
+-//FMT2_FMT_DITHER_RAND_G_SEED
+-#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0
+-#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10
+-#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL
+-#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L
+-//FMT2_FMT_DITHER_RAND_B_SEED
+-#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0
+-#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10
+-#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL
+-#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L
+-//FMT2_FMT_CLAMP_CNTL
+-#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0
+-#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10
+-#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L
+-#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L
+-//FMT2_FMT_CRC_CNTL
+-#define FMT2_FMT_CRC_CNTL__FMT_CRC_EN__SHIFT 0x0
+-#define FMT2_FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN__SHIFT 0x1
+-#define FMT2_FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT 0x4
+-#define FMT2_FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING__SHIFT 0x5
+-#define FMT2_FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN__SHIFT 0x6
+-#define FMT2_FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB__SHIFT 0x8
+-#define FMT2_FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE__SHIFT 0x9
+-#define FMT2_FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT 0xc
+-#define FMT2_FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
+-#define FMT2_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT 0x14
+-#define FMT2_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT 0x18
+-#define FMT2_FMT_CRC_CNTL__FMT_CRC_EN_MASK 0x00000001L
+-#define FMT2_FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN_MASK 0x00000002L
+-#define FMT2_FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK 0x00000010L
+-#define FMT2_FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING_MASK 0x00000020L
+-#define FMT2_FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN_MASK 0x00000040L
+-#define FMT2_FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB_MASK 0x00000100L
+-#define FMT2_FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE_MASK 0x00000200L
+-#define FMT2_FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK 0x00003000L
+-#define FMT2_FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
+-#define FMT2_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK 0x00100000L
+-#define FMT2_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK 0x01000000L
+-//FMT2_FMT_CRC_SIG_RED_GREEN_MASK
+-#define FMT2_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT 0x0
+-#define FMT2_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT 0x10
+-#define FMT2_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK 0x0000FFFFL
+-#define FMT2_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L
+-//FMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK
+-#define FMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT 0x0
+-#define FMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT 0x10
+-#define FMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL
+-#define FMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L
+-//FMT2_FMT_CRC_SIG_RED_GREEN
+-#define FMT2_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT 0x0
+-#define FMT2_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT 0x10
+-#define FMT2_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK 0x0000FFFFL
+-#define FMT2_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK 0xFFFF0000L
+-//FMT2_FMT_CRC_SIG_BLUE_CONTROL
+-#define FMT2_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT 0x0
+-#define FMT2_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT 0x10
+-#define FMT2_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK 0x0000FFFFL
+-#define FMT2_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK 0xFFFF0000L
+-//FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+-#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0
+-#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL
+-//FMT2_FMT_420_HBLANK_EARLY_START
+-#define FMT2_FMT_420_HBLANK_EARLY_START__FMT_420_HBLANK_EARLY_START__SHIFT 0x0
+-#define FMT2_FMT_420_HBLANK_EARLY_START__FMT_420_HBLANK_EARLY_START_MASK 0x00000FFFL
+-
+-
+-// addressBlock: dce_dc_dcp3_dispdec
+-//DCP3_GRPH_ENABLE
+-#define DCP3_GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0
+-#define DCP3_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL__SHIFT 0x1
+-#define DCP3_GRPH_ENABLE__GRPH_ENABLE_MASK 0x00000001L
+-#define DCP3_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL_MASK 0x00000002L
+-//DCP3_GRPH_CONTROL
+-#define DCP3_GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0
+-#define DCP3_GRPH_CONTROL__GRPH_SE_ENABLE__SHIFT 0x2
+-#define DCP3_GRPH_CONTROL__GRPH_Z__SHIFT 0x4
+-#define DCP3_GRPH_CONTROL__GRPH_DIM_TYPE__SHIFT 0x6
+-#define DCP3_GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8
+-#define DCP3_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0xc
+-#define DCP3_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10
+-#define DCP3_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11
+-#define DCP3_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES__SHIFT 0x12
+-#define DCP3_GRPH_CONTROL__GRPH_SW_MODE__SHIFT 0x14
+-#define DCP3_GRPH_CONTROL__GRPH_NUM_PIPES__SHIFT 0x1c
+-#define DCP3_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f
+-#define DCP3_GRPH_CONTROL__GRPH_DEPTH_MASK 0x00000003L
+-#define DCP3_GRPH_CONTROL__GRPH_SE_ENABLE_MASK 0x00000004L
+-#define DCP3_GRPH_CONTROL__GRPH_Z_MASK 0x00000030L
+-#define DCP3_GRPH_CONTROL__GRPH_DIM_TYPE_MASK 0x000000C0L
+-#define DCP3_GRPH_CONTROL__GRPH_FORMAT_MASK 0x00000700L
+-#define DCP3_GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0x00007000L
+-#define DCP3_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x00010000L
+-#define DCP3_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x00020000L
+-#define DCP3_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES_MASK 0x000C0000L
+-#define DCP3_GRPH_CONTROL__GRPH_SW_MODE_MASK 0x01F00000L
+-#define DCP3_GRPH_CONTROL__GRPH_NUM_PIPES_MASK 0x70000000L
+-#define DCP3_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000L
+-//DCP3_GRPH_LUT_10BIT_BYPASS
+-#define DCP3_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT 0x8
+-#define DCP3_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x10
+-#define DCP3_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK 0x00000100L
+-#define DCP3_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x00010000L
+-//DCP3_GRPH_SWAP_CNTL
+-#define DCP3_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0
+-#define DCP3_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4
+-#define DCP3_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6
+-#define DCP3_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8
+-#define DCP3_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT 0xa
+-#define DCP3_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x00000003L
+-#define DCP3_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x00000030L
+-#define DCP3_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0x000000C0L
+-#define DCP3_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x00000300L
+-#define DCP3_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK 0x00000C00L
+-//DCP3_GRPH_PRIMARY_SURFACE_ADDRESS
+-#define DCP3_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT 0x0
+-#define DCP3_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT 0x8
+-#define DCP3_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK 0x00000001L
+-#define DCP3_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+-//DCP3_GRPH_SECONDARY_SURFACE_ADDRESS
+-#define DCP3_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT 0x0
+-#define DCP3_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8
+-#define DCP3_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK 0x00000001L
+-#define DCP3_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+-//DCP3_GRPH_PITCH
+-#define DCP3_GRPH_PITCH__GRPH_PITCH__SHIFT 0x0
+-#define DCP3_GRPH_PITCH__GRPH_PITCH_MASK 0x00007FFFL
+-//DCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+-#define DCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+-#define DCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+-//DCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+-#define DCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+-#define DCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+-//DCP3_GRPH_SURFACE_OFFSET_X
+-#define DCP3_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT 0x0
+-#define DCP3_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK 0x00003FFFL
+-//DCP3_GRPH_SURFACE_OFFSET_Y
+-#define DCP3_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT 0x0
+-#define DCP3_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK 0x00003FFFL
+-//DCP3_GRPH_X_START
+-#define DCP3_GRPH_X_START__GRPH_X_START__SHIFT 0x0
+-#define DCP3_GRPH_X_START__GRPH_X_START_MASK 0x00003FFFL
+-//DCP3_GRPH_Y_START
+-#define DCP3_GRPH_Y_START__GRPH_Y_START__SHIFT 0x0
+-#define DCP3_GRPH_Y_START__GRPH_Y_START_MASK 0x00003FFFL
+-//DCP3_GRPH_X_END
+-#define DCP3_GRPH_X_END__GRPH_X_END__SHIFT 0x0
+-#define DCP3_GRPH_X_END__GRPH_X_END_MASK 0x00007FFFL
+-//DCP3_GRPH_Y_END
+-#define DCP3_GRPH_Y_END__GRPH_Y_END__SHIFT 0x0
+-#define DCP3_GRPH_Y_END__GRPH_Y_END_MASK 0x00007FFFL
+-//DCP3_INPUT_GAMMA_CONTROL
+-#define DCP3_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x0
+-#define DCP3_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK 0x00000001L
+-//DCP3_GRPH_UPDATE
+-#define DCP3_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0
+-#define DCP3_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1
+-#define DCP3_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2
+-#define DCP3_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3
+-#define DCP3_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR__SHIFT 0x8
+-#define DCP3_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE__SHIFT 0x9
+-#define DCP3_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE__SHIFT 0xa
+-#define DCP3_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10
+-#define DCP3_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14
+-#define DCP3_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+-#define DCP3_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c
+-#define DCP3_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x00000001L
+-#define DCP3_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x00000002L
+-#define DCP3_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x00000004L
+-#define DCP3_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x00000008L
+-#define DCP3_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR_MASK 0x00000100L
+-#define DCP3_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE_MASK 0x00000200L
+-#define DCP3_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE_MASK 0x00000400L
+-#define DCP3_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x00010000L
+-#define DCP3_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x00100000L
+-#define DCP3_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
+-#define DCP3_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000L
+-//DCP3_GRPH_FLIP_CONTROL
+-#define DCP3_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT 0x0
+-#define DCP3_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN__SHIFT 0x1
+-#define DCP3_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN__SHIFT 0x4
+-#define DCP3_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT 0x5
+-#define DCP3_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK 0x00000001L
+-#define DCP3_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN_MASK 0x00000002L
+-#define DCP3_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN_MASK 0x00000010L
+-#define DCP3_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK 0x00000020L
+-//DCP3_GRPH_SURFACE_ADDRESS_INUSE
+-#define DCP3_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT 0x8
+-#define DCP3_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK 0xFFFFFF00L
+-//DCP3_GRPH_DFQ_CONTROL
+-#define DCP3_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x0
+-#define DCP3_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x4
+-#define DCP3_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8
+-#define DCP3_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x00000001L
+-#define DCP3_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x00000070L
+-#define DCP3_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x00000700L
+-//DCP3_GRPH_DFQ_STATUS
+-#define DCP3_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x0
+-#define DCP3_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4
+-#define DCP3_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x8
+-#define DCP3_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x9
+-#define DCP3_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0x0000000FL
+-#define DCP3_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0x000000F0L
+-#define DCP3_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x00000100L
+-#define DCP3_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x00000200L
+-//DCP3_GRPH_INTERRUPT_STATUS
+-#define DCP3_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0
+-#define DCP3_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8
+-#define DCP3_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x00000001L
+-#define DCP3_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x00000100L
+-//DCP3_GRPH_INTERRUPT_CONTROL
+-#define DCP3_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0
+-#define DCP3_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8
+-#define DCP3_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x00000001L
+-#define DCP3_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x00000100L
+-//DCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE
+-#define DCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0
+-#define DCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK 0x000000FFL
+-//DCP3_GRPH_COMPRESS_SURFACE_ADDRESS
+-#define DCP3_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT 0x8
+-#define DCP3_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+-//DCP3_GRPH_COMPRESS_PITCH
+-#define DCP3_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT 0x6
+-#define DCP3_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK 0x0001FFC0L
+-//DCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH
+-#define DCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+-#define DCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+-//DCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT
+-#define DCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__SHIFT 0x0
+-#define DCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_MASK 0x000000FFL
+-//DCP3_PRESCALE_GRPH_CONTROL
+-#define DCP3_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT 0x0
+-#define DCP3_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT 0x1
+-#define DCP3_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x2
+-#define DCP3_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT 0x3
+-#define DCP3_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT 0x4
+-#define DCP3_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK 0x00000001L
+-#define DCP3_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x00000002L
+-#define DCP3_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK 0x00000004L
+-#define DCP3_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK 0x00000008L
+-#define DCP3_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK 0x00000010L
+-//DCP3_PRESCALE_VALUES_GRPH_R
+-#define DCP3_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT 0x0
+-#define DCP3_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT 0x10
+-#define DCP3_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK 0x0000FFFFL
+-#define DCP3_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK 0xFFFF0000L
+-//DCP3_PRESCALE_VALUES_GRPH_G
+-#define DCP3_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT 0x0
+-#define DCP3_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT 0x10
+-#define DCP3_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK 0x0000FFFFL
+-#define DCP3_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK 0xFFFF0000L
+-//DCP3_PRESCALE_VALUES_GRPH_B
+-#define DCP3_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT 0x0
+-#define DCP3_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT 0x10
+-#define DCP3_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK 0x0000FFFFL
+-#define DCP3_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK 0xFFFF0000L
+-//DCP3_INPUT_CSC_CONTROL
+-#define DCP3_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT 0x0
+-#define DCP3_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK 0x00000003L
+-//DCP3_INPUT_CSC_C11_C12
+-#define DCP3_INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT 0x0
+-#define DCP3_INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT 0x10
+-#define DCP3_INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK 0x0000FFFFL
+-#define DCP3_INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK 0xFFFF0000L
+-//DCP3_INPUT_CSC_C13_C14
+-#define DCP3_INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT 0x0
+-#define DCP3_INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT 0x10
+-#define DCP3_INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK 0x0000FFFFL
+-#define DCP3_INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK 0xFFFF0000L
+-//DCP3_INPUT_CSC_C21_C22
+-#define DCP3_INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT 0x0
+-#define DCP3_INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT 0x10
+-#define DCP3_INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK 0x0000FFFFL
+-#define DCP3_INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK 0xFFFF0000L
+-//DCP3_INPUT_CSC_C23_C24
+-#define DCP3_INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT 0x0
+-#define DCP3_INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT 0x10
+-#define DCP3_INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK 0x0000FFFFL
+-#define DCP3_INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK 0xFFFF0000L
+-//DCP3_INPUT_CSC_C31_C32
+-#define DCP3_INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT 0x0
+-#define DCP3_INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT 0x10
+-#define DCP3_INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK 0x0000FFFFL
+-#define DCP3_INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK 0xFFFF0000L
+-//DCP3_INPUT_CSC_C33_C34
+-#define DCP3_INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT 0x0
+-#define DCP3_INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT 0x10
+-#define DCP3_INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK 0x0000FFFFL
+-#define DCP3_INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK 0xFFFF0000L
+-//DCP3_OUTPUT_CSC_CONTROL
+-#define DCP3_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT 0x0
+-#define DCP3_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK 0x00000007L
+-//DCP3_OUTPUT_CSC_C11_C12
+-#define DCP3_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT 0x0
+-#define DCP3_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT 0x10
+-#define DCP3_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK 0x0000FFFFL
+-#define DCP3_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK 0xFFFF0000L
+-//DCP3_OUTPUT_CSC_C13_C14
+-#define DCP3_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT 0x0
+-#define DCP3_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT 0x10
+-#define DCP3_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK 0x0000FFFFL
+-#define DCP3_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK 0xFFFF0000L
+-//DCP3_OUTPUT_CSC_C21_C22
+-#define DCP3_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT 0x0
+-#define DCP3_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT 0x10
+-#define DCP3_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK 0x0000FFFFL
+-#define DCP3_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK 0xFFFF0000L
+-//DCP3_OUTPUT_CSC_C23_C24
+-#define DCP3_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT 0x0
+-#define DCP3_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT 0x10
+-#define DCP3_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK 0x0000FFFFL
+-#define DCP3_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK 0xFFFF0000L
+-//DCP3_OUTPUT_CSC_C31_C32
+-#define DCP3_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT 0x0
+-#define DCP3_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT 0x10
+-#define DCP3_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK 0x0000FFFFL
+-#define DCP3_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK 0xFFFF0000L
+-//DCP3_OUTPUT_CSC_C33_C34
+-#define DCP3_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT 0x0
+-#define DCP3_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT 0x10
+-#define DCP3_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK 0x0000FFFFL
+-#define DCP3_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK 0xFFFF0000L
+-//DCP3_COMM_MATRIXA_TRANS_C11_C12
+-#define DCP3_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT 0x0
+-#define DCP3_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT 0x10
+-#define DCP3_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK 0x0000FFFFL
+-#define DCP3_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK 0xFFFF0000L
+-//DCP3_COMM_MATRIXA_TRANS_C13_C14
+-#define DCP3_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT 0x0
+-#define DCP3_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT 0x10
+-#define DCP3_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK 0x0000FFFFL
+-#define DCP3_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK 0xFFFF0000L
+-//DCP3_COMM_MATRIXA_TRANS_C21_C22
+-#define DCP3_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT 0x0
+-#define DCP3_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT 0x10
+-#define DCP3_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK 0x0000FFFFL
+-#define DCP3_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK 0xFFFF0000L
+-//DCP3_COMM_MATRIXA_TRANS_C23_C24
+-#define DCP3_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT 0x0
+-#define DCP3_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT 0x10
+-#define DCP3_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK 0x0000FFFFL
+-#define DCP3_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK 0xFFFF0000L
+-//DCP3_COMM_MATRIXA_TRANS_C31_C32
+-#define DCP3_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT 0x0
+-#define DCP3_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT 0x10
+-#define DCP3_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK 0x0000FFFFL
+-#define DCP3_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK 0xFFFF0000L
+-//DCP3_COMM_MATRIXA_TRANS_C33_C34
+-#define DCP3_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT 0x0
+-#define DCP3_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT 0x10
+-#define DCP3_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK 0x0000FFFFL
+-#define DCP3_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK 0xFFFF0000L
+-//DCP3_COMM_MATRIXB_TRANS_C11_C12
+-#define DCP3_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT 0x0
+-#define DCP3_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT 0x10
+-#define DCP3_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK 0x0000FFFFL
+-#define DCP3_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK 0xFFFF0000L
+-//DCP3_COMM_MATRIXB_TRANS_C13_C14
+-#define DCP3_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT 0x0
+-#define DCP3_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT 0x10
+-#define DCP3_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK 0x0000FFFFL
+-#define DCP3_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK 0xFFFF0000L
+-//DCP3_COMM_MATRIXB_TRANS_C21_C22
+-#define DCP3_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT 0x0
+-#define DCP3_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT 0x10
+-#define DCP3_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK 0x0000FFFFL
+-#define DCP3_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK 0xFFFF0000L
+-//DCP3_COMM_MATRIXB_TRANS_C23_C24
+-#define DCP3_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT 0x0
+-#define DCP3_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT 0x10
+-#define DCP3_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK 0x0000FFFFL
+-#define DCP3_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK 0xFFFF0000L
+-//DCP3_COMM_MATRIXB_TRANS_C31_C32
+-#define DCP3_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT 0x0
+-#define DCP3_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT 0x10
+-#define DCP3_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK 0x0000FFFFL
+-#define DCP3_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK 0xFFFF0000L
+-//DCP3_COMM_MATRIXB_TRANS_C33_C34
+-#define DCP3_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT 0x0
+-#define DCP3_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT 0x10
+-#define DCP3_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK 0x0000FFFFL
+-#define DCP3_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK 0xFFFF0000L
+-//DCP3_DENORM_CONTROL
+-#define DCP3_DENORM_CONTROL__DENORM_MODE__SHIFT 0x0
+-#define DCP3_DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT 0x4
+-#define DCP3_DENORM_CONTROL__DENORM_MODE_MASK 0x00000007L
+-#define DCP3_DENORM_CONTROL__DENORM_14BIT_OUT_MASK 0x00000010L
+-//DCP3_OUT_ROUND_CONTROL
+-#define DCP3_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT 0x0
+-#define DCP3_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK 0x0000000FL
+-//DCP3_OUT_CLAMP_CONTROL_R_CR
+-#define DCP3_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT 0x0
+-#define DCP3_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT 0x10
+-#define DCP3_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK 0x00003FFFL
+-#define DCP3_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK 0x3FFF0000L
+-//DCP3_OUT_CLAMP_CONTROL_G_Y
+-#define DCP3_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT 0x0
+-#define DCP3_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT 0x10
+-#define DCP3_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK 0x00003FFFL
+-#define DCP3_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK 0x3FFF0000L
+-//DCP3_OUT_CLAMP_CONTROL_B_CB
+-#define DCP3_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT 0x0
+-#define DCP3_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT 0x10
+-#define DCP3_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK 0x00003FFFL
+-#define DCP3_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK 0x3FFF0000L
+-//DCP3_KEY_CONTROL
+-#define DCP3_KEY_CONTROL__KEY_MODE__SHIFT 0x1
+-#define DCP3_KEY_CONTROL__KEY_MODE_MASK 0x00000006L
+-//DCP3_KEY_RANGE_ALPHA
+-#define DCP3_KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT 0x0
+-#define DCP3_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT 0x10
+-#define DCP3_KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK 0x0000FFFFL
+-#define DCP3_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK 0xFFFF0000L
+-//DCP3_KEY_RANGE_RED
+-#define DCP3_KEY_RANGE_RED__KEY_RED_LOW__SHIFT 0x0
+-#define DCP3_KEY_RANGE_RED__KEY_RED_HIGH__SHIFT 0x10
+-#define DCP3_KEY_RANGE_RED__KEY_RED_LOW_MASK 0x0000FFFFL
+-#define DCP3_KEY_RANGE_RED__KEY_RED_HIGH_MASK 0xFFFF0000L
+-//DCP3_KEY_RANGE_GREEN
+-#define DCP3_KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT 0x0
+-#define DCP3_KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT 0x10
+-#define DCP3_KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK 0x0000FFFFL
+-#define DCP3_KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK 0xFFFF0000L
+-//DCP3_KEY_RANGE_BLUE
+-#define DCP3_KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT 0x0
+-#define DCP3_KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT 0x10
+-#define DCP3_KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK 0x0000FFFFL
+-#define DCP3_KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK 0xFFFF0000L
+-//DCP3_DEGAMMA_CONTROL
+-#define DCP3_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x0
+-#define DCP3_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT 0x8
+-#define DCP3_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0xc
+-#define DCP3_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x00000003L
+-#define DCP3_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK 0x00000300L
+-#define DCP3_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK 0x00003000L
+-//DCP3_GAMUT_REMAP_CONTROL
+-#define DCP3_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT 0x0
+-#define DCP3_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK 0x00000003L
+-//DCP3_GAMUT_REMAP_C11_C12
+-#define DCP3_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT 0x0
+-#define DCP3_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT 0x10
+-#define DCP3_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK 0x0000FFFFL
+-#define DCP3_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK 0xFFFF0000L
+-//DCP3_GAMUT_REMAP_C13_C14
+-#define DCP3_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT 0x0
+-#define DCP3_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT 0x10
+-#define DCP3_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK 0x0000FFFFL
+-#define DCP3_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK 0xFFFF0000L
+-//DCP3_GAMUT_REMAP_C21_C22
+-#define DCP3_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT 0x0
+-#define DCP3_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT 0x10
+-#define DCP3_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK 0x0000FFFFL
+-#define DCP3_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK 0xFFFF0000L
+-//DCP3_GAMUT_REMAP_C23_C24
+-#define DCP3_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT 0x0
+-#define DCP3_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT 0x10
+-#define DCP3_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK 0x0000FFFFL
+-#define DCP3_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK 0xFFFF0000L
+-//DCP3_GAMUT_REMAP_C31_C32
+-#define DCP3_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT 0x0
+-#define DCP3_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT 0x10
+-#define DCP3_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK 0x0000FFFFL
+-#define DCP3_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK 0xFFFF0000L
+-//DCP3_GAMUT_REMAP_C33_C34
+-#define DCP3_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT 0x0
+-#define DCP3_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT 0x10
+-#define DCP3_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK 0x0000FFFFL
+-#define DCP3_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK 0xFFFF0000L
+-//DCP3_DCP_SPATIAL_DITHER_CNTL
+-#define DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT 0x0
+-#define DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT 0x4
+-#define DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT 0x6
+-#define DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT 0x8
+-#define DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT 0x9
+-#define DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT 0xa
+-#define DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK 0x00000001L
+-#define DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK 0x00000030L
+-#define DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK 0x000000C0L
+-#define DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK 0x00000100L
+-#define DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK 0x00000200L
+-#define DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK 0x00000400L
+-//DCP3_DCP_RANDOM_SEEDS
+-#define DCP3_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT 0x0
+-#define DCP3_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT 0x8
+-#define DCP3_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT 0x10
+-#define DCP3_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK 0x000000FFL
+-#define DCP3_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK 0x0000FF00L
+-#define DCP3_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK 0x00FF0000L
+-//DCP3_DCP_FP_CONVERTED_FIELD
+-#define DCP3_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT 0x0
+-#define DCP3_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14
+-#define DCP3_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK 0x0003FFFFL
+-#define DCP3_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK 0x07F00000L
+-//DCP3_CUR_CONTROL
+-#define DCP3_CUR_CONTROL__CURSOR_EN__SHIFT 0x0
+-#define DCP3_CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT 0x4
+-#define DCP3_CUR_CONTROL__CURSOR_MODE__SHIFT 0x8
+-#define DCP3_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM__SHIFT 0xb
+-#define DCP3_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION__SHIFT 0xc
+-#define DCP3_CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x10
+-#define DCP3_CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT 0x14
+-#define DCP3_CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT 0x18
+-#define DCP3_CUR_CONTROL__CURSOR_EN_MASK 0x00000001L
+-#define DCP3_CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK 0x00000010L
+-#define DCP3_CUR_CONTROL__CURSOR_MODE_MASK 0x00000300L
+-#define DCP3_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM_MASK 0x00000800L
+-#define DCP3_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION_MASK 0x0000F000L
+-#define DCP3_CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00010000L
+-#define DCP3_CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK 0x00100000L
+-#define DCP3_CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK 0x07000000L
+-//DCP3_CUR_SURFACE_ADDRESS
+-#define DCP3_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0
+-#define DCP3_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+-//DCP3_CUR_SIZE
+-#define DCP3_CUR_SIZE__CURSOR_HEIGHT__SHIFT 0x0
+-#define DCP3_CUR_SIZE__CURSOR_WIDTH__SHIFT 0x10
+-#define DCP3_CUR_SIZE__CURSOR_HEIGHT_MASK 0x0000007FL
+-#define DCP3_CUR_SIZE__CURSOR_WIDTH_MASK 0x007F0000L
+-//DCP3_CUR_SURFACE_ADDRESS_HIGH
+-#define DCP3_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+-#define DCP3_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+-//DCP3_CUR_POSITION
+-#define DCP3_CUR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0
+-#define DCP3_CUR_POSITION__CURSOR_X_POSITION__SHIFT 0x10
+-#define DCP3_CUR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL
+-#define DCP3_CUR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L
+-//DCP3_CUR_HOT_SPOT
+-#define DCP3_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0
+-#define DCP3_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10
+-#define DCP3_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x0000007FL
+-#define DCP3_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x007F0000L
+-//DCP3_CUR_COLOR1
+-#define DCP3_CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT 0x0
+-#define DCP3_CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT 0x8
+-#define DCP3_CUR_COLOR1__CUR_COLOR1_RED__SHIFT 0x10
+-#define DCP3_CUR_COLOR1__CUR_COLOR1_BLUE_MASK 0x000000FFL
+-#define DCP3_CUR_COLOR1__CUR_COLOR1_GREEN_MASK 0x0000FF00L
+-#define DCP3_CUR_COLOR1__CUR_COLOR1_RED_MASK 0x00FF0000L
+-//DCP3_CUR_COLOR2
+-#define DCP3_CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT 0x0
+-#define DCP3_CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT 0x8
+-#define DCP3_CUR_COLOR2__CUR_COLOR2_RED__SHIFT 0x10
+-#define DCP3_CUR_COLOR2__CUR_COLOR2_BLUE_MASK 0x000000FFL
+-#define DCP3_CUR_COLOR2__CUR_COLOR2_GREEN_MASK 0x0000FF00L
+-#define DCP3_CUR_COLOR2__CUR_COLOR2_RED_MASK 0x00FF0000L
+-//DCP3_CUR_UPDATE
+-#define DCP3_CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT 0x0
+-#define DCP3_CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT 0x1
+-#define DCP3_CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT 0x10
+-#define DCP3_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+-#define DCP3_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE__SHIFT 0x19
+-#define DCP3_CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK 0x00000001L
+-#define DCP3_CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x00000002L
+-#define DCP3_CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK 0x00010000L
+-#define DCP3_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
+-#define DCP3_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE_MASK 0x06000000L
+-//DCP3_CUR_REQUEST_FILTER_CNTL
+-#define DCP3_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT 0x0
+-#define DCP3_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK 0x00000001L
+-//DCP3_CUR_STEREO_CONTROL
+-#define DCP3_CUR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0
+-#define DCP3_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4
+-#define DCP3_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x10
+-#define DCP3_CUR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L
+-#define DCP3_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x00003FF0L
+-#define DCP3_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0x03FF0000L
+-//DCP3_DC_LUT_RW_MODE
+-#define DCP3_DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT 0x0
+-#define DCP3_DC_LUT_RW_MODE__DC_LUT_ERROR__SHIFT 0x10
+-#define DCP3_DC_LUT_RW_MODE__DC_LUT_ERROR_RST__SHIFT 0x11
+-#define DCP3_DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK 0x00000001L
+-#define DCP3_DC_LUT_RW_MODE__DC_LUT_ERROR_MASK 0x00010000L
+-#define DCP3_DC_LUT_RW_MODE__DC_LUT_ERROR_RST_MASK 0x00020000L
+-//DCP3_DC_LUT_RW_INDEX
+-#define DCP3_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT 0x0
+-#define DCP3_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK 0x000000FFL
+-//DCP3_DC_LUT_SEQ_COLOR
+-#define DCP3_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT 0x0
+-#define DCP3_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK 0x0000FFFFL
+-//DCP3_DC_LUT_PWL_DATA
+-#define DCP3_DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT 0x0
+-#define DCP3_DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT 0x10
+-#define DCP3_DC_LUT_PWL_DATA__DC_LUT_BASE_MASK 0x0000FFFFL
+-#define DCP3_DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK 0xFFFF0000L
+-//DCP3_DC_LUT_30_COLOR
+-#define DCP3_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT 0x0
+-#define DCP3_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT 0xa
+-#define DCP3_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT 0x14
+-#define DCP3_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK 0x000003FFL
+-#define DCP3_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK 0x000FFC00L
+-#define DCP3_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK 0x3FF00000L
+-//DCP3_DC_LUT_VGA_ACCESS_ENABLE
+-#define DCP3_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT 0x0
+-#define DCP3_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK 0x00000001L
+-//DCP3_DC_LUT_WRITE_EN_MASK
+-#define DCP3_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT 0x0
+-#define DCP3_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK 0x00000007L
+-//DCP3_DC_LUT_AUTOFILL
+-#define DCP3_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT 0x0
+-#define DCP3_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT 0x1
+-#define DCP3_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK 0x00000001L
+-#define DCP3_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x00000002L
+-//DCP3_DC_LUT_CONTROL
+-#define DCP3_DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT 0x0
+-#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT 0x4
+-#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT 0x5
+-#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT 0x6
+-#define DCP3_DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT 0x8
+-#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT 0xc
+-#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT 0xd
+-#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT 0xe
+-#define DCP3_DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT 0x10
+-#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT 0x14
+-#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT 0x15
+-#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT 0x16
+-#define DCP3_DC_LUT_CONTROL__DC_LUT_INC_B_MASK 0x0000000FL
+-#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK 0x00000010L
+-#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK 0x00000020L
+-#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK 0x000000C0L
+-#define DCP3_DC_LUT_CONTROL__DC_LUT_INC_G_MASK 0x00000F00L
+-#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK 0x00001000L
+-#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK 0x00002000L
+-#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK 0x0000C000L
+-#define DCP3_DC_LUT_CONTROL__DC_LUT_INC_R_MASK 0x000F0000L
+-#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK 0x00100000L
+-#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK 0x00200000L
+-#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK 0x00C00000L
+-//DCP3_DC_LUT_BLACK_OFFSET_BLUE
+-#define DCP3_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0
+-#define DCP3_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK 0x0000FFFFL
+-//DCP3_DC_LUT_BLACK_OFFSET_GREEN
+-#define DCP3_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0
+-#define DCP3_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK 0x0000FFFFL
+-//DCP3_DC_LUT_BLACK_OFFSET_RED
+-#define DCP3_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT 0x0
+-#define DCP3_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK 0x0000FFFFL
+-//DCP3_DC_LUT_WHITE_OFFSET_BLUE
+-#define DCP3_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT 0x0
+-#define DCP3_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK 0x0000FFFFL
+-//DCP3_DC_LUT_WHITE_OFFSET_GREEN
+-#define DCP3_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT 0x0
+-#define DCP3_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK 0x0000FFFFL
+-//DCP3_DC_LUT_WHITE_OFFSET_RED
+-#define DCP3_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT 0x0
+-#define DCP3_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK 0x0000FFFFL
+-//DCP3_DCP_CRC_CONTROL
+-#define DCP3_DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT 0x0
+-#define DCP3_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x2
+-#define DCP3_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT 0x8
+-#define DCP3_DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK 0x00000001L
+-#define DCP3_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK 0x0000001CL
+-#define DCP3_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK 0x00000300L
+-//DCP3_DCP_CRC_MASK
+-#define DCP3_DCP_CRC_MASK__DCP_CRC_MASK__SHIFT 0x0
+-#define DCP3_DCP_CRC_MASK__DCP_CRC_MASK_MASK 0xFFFFFFFFL
+-//DCP3_DCP_CRC_CURRENT
+-#define DCP3_DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT 0x0
+-#define DCP3_DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK 0xFFFFFFFFL
+-//DCP3_DVMM_PTE_CONTROL
+-#define DCP3_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT 0x0
+-#define DCP3_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT 0x1
+-#define DCP3_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT 0x5
+-#define DCP3_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT 0x9
+-#define DCP3_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT 0x14
+-#define DCP3_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT 0x15
+-#define DCP3_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK 0x00000001L
+-#define DCP3_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK 0x0000001EL
+-#define DCP3_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK 0x000001E0L
+-#define DCP3_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK 0x0007FE00L
+-#define DCP3_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK 0x00100000L
+-#define DCP3_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK 0x00200000L
+-//DCP3_DCP_CRC_LAST
+-#define DCP3_DCP_CRC_LAST__DCP_CRC_LAST__SHIFT 0x0
+-#define DCP3_DCP_CRC_LAST__DCP_CRC_LAST_MASK 0xFFFFFFFFL
+-//DCP3_DVMM_PTE_ARB_CONTROL
+-#define DCP3_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT 0x0
+-#define DCP3_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT 0x8
+-#define DCP3_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK 0x0000003FL
+-#define DCP3_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK 0x0000FF00L
+-//DCP3_GRPH_FLIP_RATE_CNTL
+-#define DCP3_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT 0x0
+-#define DCP3_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT 0x3
+-#define DCP3_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK 0x00000007L
+-#define DCP3_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK 0x00000008L
+-//DCP3_DCP_GSL_CONTROL
+-#define DCP3_DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT 0x0
+-#define DCP3_DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT 0x1
+-#define DCP3_DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x2
+-#define DCP3_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT 0x4
+-#define DCP3_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT 0x14
+-#define DCP3_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP__SHIFT 0x15
+-#define DCP3_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN__SHIFT 0x17
+-#define DCP3_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT 0x18
+-#define DCP3_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC__SHIFT 0x1a
+-#define DCP3_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT 0x1b
+-#define DCP3_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT 0x1c
+-#define DCP3_DCP_GSL_CONTROL__DCP_GSL0_EN_MASK 0x00000001L
+-#define DCP3_DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x00000002L
+-#define DCP3_DCP_GSL_CONTROL__DCP_GSL2_EN_MASK 0x00000004L
+-#define DCP3_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK 0x000FFFF0L
+-#define DCP3_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK 0x00100000L
+-#define DCP3_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_MASK 0x00600000L
+-#define DCP3_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_MASK 0x00800000L
+-#define DCP3_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK 0x03000000L
+-#define DCP3_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_MASK 0x04000000L
+-#define DCP3_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK 0x08000000L
+-#define DCP3_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK 0xF0000000L
+-//DCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK
+-#define DCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT 0x0
+-#define DCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT 0x4
+-#define DCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK 0x0000000FL
+-#define DCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK 0x000001F0L
+-//DCP3_GRPH_STEREOSYNC_FLIP
+-#define DCP3_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0
+-#define DCP3_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x8
+-#define DCP3_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10
+-#define DCP3_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11
+-#define DCP3_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c
+-#define DCP3_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x00000001L
+-#define DCP3_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x00000300L
+-#define DCP3_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x00010000L
+-#define DCP3_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x00020000L
+-#define DCP3_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000L
+-//DCP3_HW_ROTATION
+-#define DCP3_HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT 0x0
+-#define DCP3_HW_ROTATION__GRPH_ROTATION_ANGLE_MASK 0x00000007L
+-//DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL
+-#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT 0x0
+-#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT 0x1
+-#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT 0x4
+-#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK 0x00000001L
+-#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK 0x00000002L
+-#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK 0x0001FFF0L
+-//DCP3_REGAMMA_CONTROL
+-#define DCP3_REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT 0x0
+-#define DCP3_REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK 0x00000007L
+-//DCP3_REGAMMA_LUT_INDEX
+-#define DCP3_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x0
+-#define DCP3_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK 0x000001FFL
+-//DCP3_REGAMMA_LUT_DATA
+-#define DCP3_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT 0x0
+-#define DCP3_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK 0x0007FFFFL
+-//DCP3_REGAMMA_LUT_WRITE_EN_MASK
+-#define DCP3_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x0
+-#define DCP3_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x00000007L
+-//DCP3_REGAMMA_CNTLA_START_CNTL
+-#define DCP3_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x0
+-#define DCP3_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14
+-#define DCP3_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK 0x0003FFFFL
+-#define DCP3_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
+-//DCP3_REGAMMA_CNTLA_SLOPE_CNTL
+-#define DCP3_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+-#define DCP3_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
+-//DCP3_REGAMMA_CNTLA_END_CNTL1
+-#define DCP3_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x0
+-#define DCP3_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK 0x0000FFFFL
+-//DCP3_REGAMMA_CNTLA_END_CNTL2
+-#define DCP3_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0
+-#define DCP3_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10
+-#define DCP3_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
+-#define DCP3_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xFFFF0000L
+-//DCP3_REGAMMA_CNTLA_REGION_0_1
+-#define DCP3_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+-#define DCP3_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP3_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+-#define DCP3_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP3_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP3_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP3_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP3_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP3_REGAMMA_CNTLA_REGION_2_3
+-#define DCP3_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+-#define DCP3_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP3_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+-#define DCP3_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP3_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP3_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP3_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP3_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP3_REGAMMA_CNTLA_REGION_4_5
+-#define DCP3_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+-#define DCP3_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP3_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+-#define DCP3_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP3_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP3_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP3_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP3_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP3_REGAMMA_CNTLA_REGION_6_7
+-#define DCP3_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+-#define DCP3_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP3_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+-#define DCP3_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP3_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP3_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP3_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP3_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP3_REGAMMA_CNTLA_REGION_8_9
+-#define DCP3_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+-#define DCP3_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP3_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+-#define DCP3_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP3_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP3_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP3_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP3_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP3_REGAMMA_CNTLA_REGION_10_11
+-#define DCP3_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+-#define DCP3_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP3_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+-#define DCP3_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP3_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP3_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP3_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP3_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP3_REGAMMA_CNTLA_REGION_12_13
+-#define DCP3_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+-#define DCP3_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP3_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+-#define DCP3_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP3_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP3_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP3_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP3_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP3_REGAMMA_CNTLA_REGION_14_15
+-#define DCP3_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+-#define DCP3_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP3_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+-#define DCP3_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP3_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP3_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP3_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP3_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP3_REGAMMA_CNTLB_START_CNTL
+-#define DCP3_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x0
+-#define DCP3_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14
+-#define DCP3_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK 0x0003FFFFL
+-#define DCP3_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
+-//DCP3_REGAMMA_CNTLB_SLOPE_CNTL
+-#define DCP3_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+-#define DCP3_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
+-//DCP3_REGAMMA_CNTLB_END_CNTL1
+-#define DCP3_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x0
+-#define DCP3_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK 0x0000FFFFL
+-//DCP3_REGAMMA_CNTLB_END_CNTL2
+-#define DCP3_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0
+-#define DCP3_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10
+-#define DCP3_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
+-#define DCP3_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xFFFF0000L
+-//DCP3_REGAMMA_CNTLB_REGION_0_1
+-#define DCP3_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+-#define DCP3_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP3_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+-#define DCP3_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP3_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP3_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP3_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP3_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP3_REGAMMA_CNTLB_REGION_2_3
+-#define DCP3_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+-#define DCP3_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP3_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+-#define DCP3_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP3_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP3_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP3_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP3_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP3_REGAMMA_CNTLB_REGION_4_5
+-#define DCP3_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+-#define DCP3_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP3_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+-#define DCP3_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP3_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP3_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP3_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP3_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP3_REGAMMA_CNTLB_REGION_6_7
+-#define DCP3_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+-#define DCP3_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP3_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+-#define DCP3_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP3_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP3_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP3_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP3_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP3_REGAMMA_CNTLB_REGION_8_9
+-#define DCP3_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+-#define DCP3_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP3_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+-#define DCP3_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP3_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP3_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP3_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP3_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP3_REGAMMA_CNTLB_REGION_10_11
+-#define DCP3_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+-#define DCP3_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP3_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+-#define DCP3_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP3_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP3_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP3_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP3_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP3_REGAMMA_CNTLB_REGION_12_13
+-#define DCP3_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+-#define DCP3_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP3_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+-#define DCP3_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP3_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP3_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP3_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP3_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP3_REGAMMA_CNTLB_REGION_14_15
+-#define DCP3_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+-#define DCP3_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP3_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+-#define DCP3_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP3_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP3_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP3_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP3_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP3_ALPHA_CONTROL
+-#define DCP3_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT 0x0
+-#define DCP3_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT 0x1
+-#define DCP3_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK 0x00000001L
+-#define DCP3_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK 0x00000002L
+-//DCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS
+-#define DCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT 0x8
+-#define DCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+-//DCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH
+-#define DCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+-#define DCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+-//DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS
+-#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT 0x0
+-#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT 0x18
+-#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT 0x19
+-#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT 0x1a
+-#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT 0x1c
+-#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT 0x1d
+-#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT 0x1e
+-#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK 0x000FFFFFL
+-#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK 0x01000000L
+-#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK 0x02000000L
+-#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK 0x04000000L
+-#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK 0x10000000L
+-#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK 0x20000000L
+-#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK 0x40000000L
+-//DCP3_GRPH_XDMA_FLIP_TIMEOUT
+-#define DCP3_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS__SHIFT 0x0
+-#define DCP3_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK__SHIFT 0x1
+-#define DCP3_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK__SHIFT 0x2
+-#define DCP3_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS_MASK 0x00000001L
+-#define DCP3_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK_MASK 0x00000002L
+-#define DCP3_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK_MASK 0x00000004L
+-//DCP3_GRPH_XDMA_FLIP_AVG_DELAY
+-#define DCP3_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY__SHIFT 0x0
+-#define DCP3_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD__SHIFT 0x10
+-#define DCP3_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY_MASK 0x0000FFFFL
+-#define DCP3_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD_MASK 0x00FF0000L
+-//DCP3_GRPH_SURFACE_COUNTER_CONTROL
+-#define DCP3_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN__SHIFT 0x0
+-#define DCP3_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT__SHIFT 0x1
+-#define DCP3_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED__SHIFT 0x9
+-#define DCP3_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN_MASK 0x00000001L
+-#define DCP3_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT_MASK 0x0000001EL
+-#define DCP3_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_MASK 0x00000200L
+-//DCP3_GRPH_SURFACE_COUNTER_OUTPUT
+-#define DCP3_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN__SHIFT 0x0
+-#define DCP3_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX__SHIFT 0x10
+-#define DCP3_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN_MASK 0x0000FFFFL
+-#define DCP3_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX_MASK 0xFFFF0000L
+-
+-
+-// addressBlock: dce_dc_lb3_dispdec
+-//LB3_LB_DATA_FORMAT
+-#define LB3_LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0
+-#define LB3_LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2
+-#define LB3_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3
+-#define LB3_LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4
+-#define LB3_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5
+-#define LB3_LB_DATA_FORMAT__PREFILL_EN__SHIFT 0x8
+-#define LB3_LB_DATA_FORMAT__PREFETCH__SHIFT 0xc
+-#define LB3_LB_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18
+-#define LB3_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f
+-#define LB3_LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x00000003L
+-#define LB3_LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x00000004L
+-#define LB3_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000008L
+-#define LB3_LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x00000010L
+-#define LB3_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x00000020L
+-#define LB3_LB_DATA_FORMAT__PREFILL_EN_MASK 0x00000100L
+-#define LB3_LB_DATA_FORMAT__PREFETCH_MASK 0x00001000L
+-#define LB3_LB_DATA_FORMAT__REQUEST_MODE_MASK 0x01000000L
+-#define LB3_LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000L
+-//LB3_LB_MEMORY_CTRL
+-#define LB3_LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0
+-#define LB3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
+-#define LB3_LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14
+-#define LB3_LB_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0x00001FFFL
+-#define LB3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x000F0000L
+-#define LB3_LB_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x00300000L
+-//LB3_LB_MEMORY_SIZE_STATUS
+-#define LB3_LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0
+-#define LB3_LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0x00001FFFL
+-//LB3_LB_DESKTOP_HEIGHT
+-#define LB3_LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0
+-#define LB3_LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x00007FFFL
+-//LB3_LB_VLINE_START_END
+-#define LB3_LB_VLINE_START_END__VLINE_START__SHIFT 0x0
+-#define LB3_LB_VLINE_START_END__VLINE_END__SHIFT 0x10
+-#define LB3_LB_VLINE_START_END__VLINE_INV__SHIFT 0x1f
+-#define LB3_LB_VLINE_START_END__VLINE_START_MASK 0x00003FFFL
+-#define LB3_LB_VLINE_START_END__VLINE_END_MASK 0x7FFF0000L
+-#define LB3_LB_VLINE_START_END__VLINE_INV_MASK 0x80000000L
+-//LB3_LB_VLINE2_START_END
+-#define LB3_LB_VLINE2_START_END__VLINE2_START__SHIFT 0x0
+-#define LB3_LB_VLINE2_START_END__VLINE2_END__SHIFT 0x10
+-#define LB3_LB_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f
+-#define LB3_LB_VLINE2_START_END__VLINE2_START_MASK 0x00003FFFL
+-#define LB3_LB_VLINE2_START_END__VLINE2_END_MASK 0x7FFF0000L
+-#define LB3_LB_VLINE2_START_END__VLINE2_INV_MASK 0x80000000L
+-//LB3_LB_V_COUNTER
+-#define LB3_LB_V_COUNTER__V_COUNTER__SHIFT 0x0
+-#define LB3_LB_V_COUNTER__V_COUNTER_MASK 0x00007FFFL
+-//LB3_LB_SNAPSHOT_V_COUNTER
+-#define LB3_LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0
+-#define LB3_LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x00007FFFL
+-//LB3_LB_INTERRUPT_MASK
+-#define LB3_LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0
+-#define LB3_LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4
+-#define LB3_LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8
+-#define LB3_LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x00000001L
+-#define LB3_LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x00000010L
+-#define LB3_LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x00000100L
+-//LB3_LB_VLINE_STATUS
+-#define LB3_LB_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0
+-#define LB3_LB_VLINE_STATUS__VLINE_ACK__SHIFT 0x4
+-#define LB3_LB_VLINE_STATUS__VLINE_STAT__SHIFT 0xc
+-#define LB3_LB_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10
+-#define LB3_LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11
+-#define LB3_LB_VLINE_STATUS__VLINE_OCCURRED_MASK 0x00000001L
+-#define LB3_LB_VLINE_STATUS__VLINE_ACK_MASK 0x00000010L
+-#define LB3_LB_VLINE_STATUS__VLINE_STAT_MASK 0x00001000L
+-#define LB3_LB_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x00010000L
+-#define LB3_LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x00020000L
+-//LB3_LB_VLINE2_STATUS
+-#define LB3_LB_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0
+-#define LB3_LB_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4
+-#define LB3_LB_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc
+-#define LB3_LB_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10
+-#define LB3_LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11
+-#define LB3_LB_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x00000001L
+-#define LB3_LB_VLINE2_STATUS__VLINE2_ACK_MASK 0x00000010L
+-#define LB3_LB_VLINE2_STATUS__VLINE2_STAT_MASK 0x00001000L
+-#define LB3_LB_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x00010000L
+-#define LB3_LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x00020000L
+-//LB3_LB_VBLANK_STATUS
+-#define LB3_LB_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0
+-#define LB3_LB_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4
+-#define LB3_LB_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc
+-#define LB3_LB_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10
+-#define LB3_LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11
+-#define LB3_LB_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x00000001L
+-#define LB3_LB_VBLANK_STATUS__VBLANK_ACK_MASK 0x00000010L
+-#define LB3_LB_VBLANK_STATUS__VBLANK_STAT_MASK 0x00001000L
+-#define LB3_LB_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x00010000L
+-#define LB3_LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x00020000L
+-//LB3_LB_SYNC_RESET_SEL
+-#define LB3_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0
+-#define LB3_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4
+-#define LB3_LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8
+-#define LB3_LB_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16
+-#define LB3_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x00000003L
+-#define LB3_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x00000010L
+-#define LB3_LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0x0000FF00L
+-#define LB3_LB_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0x00C00000L
+-//LB3_LB_BLACK_KEYER_R_CR
+-#define LB3_LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4
+-#define LB3_LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0x0000FFF0L
+-//LB3_LB_BLACK_KEYER_G_Y
+-#define LB3_LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4
+-#define LB3_LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0x0000FFF0L
+-//LB3_LB_BLACK_KEYER_B_CB
+-#define LB3_LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4
+-#define LB3_LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0x0000FFF0L
+-//LB3_LB_KEYER_COLOR_CTRL
+-#define LB3_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0
+-#define LB3_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8
+-#define LB3_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x00000001L
+-#define LB3_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x00000100L
+-//LB3_LB_KEYER_COLOR_R_CR
+-#define LB3_LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4
+-#define LB3_LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0x0000FFF0L
+-//LB3_LB_KEYER_COLOR_G_Y
+-#define LB3_LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4
+-#define LB3_LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0x0000FFF0L
+-//LB3_LB_KEYER_COLOR_B_CB
+-#define LB3_LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4
+-#define LB3_LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0x0000FFF0L
+-//LB3_LB_KEYER_COLOR_REP_R_CR
+-#define LB3_LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4
+-#define LB3_LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0x0000FFF0L
+-//LB3_LB_KEYER_COLOR_REP_G_Y
+-#define LB3_LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4
+-#define LB3_LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0x0000FFF0L
+-//LB3_LB_KEYER_COLOR_REP_B_CB
+-#define LB3_LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4
+-#define LB3_LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0x0000FFF0L
+-//LB3_LB_BUFFER_LEVEL_STATUS
+-#define LB3_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0
+-#define LB3_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa
+-#define LB3_LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10
+-#define LB3_LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c
+-#define LB3_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x0000003FL
+-#define LB3_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0x0000FC00L
+-#define LB3_LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0x0FFF0000L
+-#define LB3_LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xF0000000L
+-//LB3_LB_BUFFER_URGENCY_CTRL
+-#define LB3_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0
+-#define LB3_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10
+-#define LB3_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0x00000FFFL
+-#define LB3_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0x0FFF0000L
+-//LB3_LB_BUFFER_URGENCY_STATUS
+-#define LB3_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0
+-#define LB3_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10
+-#define LB3_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0x00000FFFL
+-#define LB3_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x00010000L
+-//LB3_LB_BUFFER_STATUS
+-#define LB3_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0
+-#define LB3_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4
+-#define LB3_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8
+-#define LB3_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc
+-#define LB3_LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10
+-#define LB3_LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14
+-#define LB3_LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18
+-#define LB3_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0x0000000FL
+-#define LB3_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x00000010L
+-#define LB3_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x00000100L
+-#define LB3_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x00001000L
+-#define LB3_LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x00010000L
+-#define LB3_LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x00100000L
+-#define LB3_LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x01000000L
+-//LB3_LB_NO_OUTSTANDING_REQ_STATUS
+-#define LB3_LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0
+-#define LB3_LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x00000001L
+-//LB3_MVP_AFR_FLIP_MODE
+-#define LB3_MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT 0x0
+-#define LB3_MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK 0x00000003L
+-//LB3_MVP_AFR_FLIP_FIFO_CNTL
+-#define LB3_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT 0x0
+-#define LB3_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT 0x4
+-#define LB3_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT 0x8
+-#define LB3_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT 0xc
+-#define LB3_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK 0x0000000FL
+-#define LB3_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK 0x00000010L
+-#define LB3_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK 0x00000100L
+-#define LB3_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK 0x00001000L
+-//LB3_MVP_FLIP_LINE_NUM_INSERT
+-#define LB3_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT 0x0
+-#define LB3_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT 0x8
+-#define LB3_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT 0x18
+-#define LB3_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT 0x1e
+-#define LB3_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK 0x00000003L
+-#define LB3_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK 0x007FFF00L
+-#define LB3_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK 0x3F000000L
+-#define LB3_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK 0x40000000L
+-//LB3_DC_MVP_LB_CONTROL
+-#define LB3_DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT 0x0
+-#define LB3_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT 0x8
+-#define LB3_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT 0xc
+-#define LB3_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT 0x10
+-#define LB3_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT 0x14
+-#define LB3_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT 0x1c
+-#define LB3_DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT 0x1f
+-#define LB3_DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK 0x00000003L
+-#define LB3_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK 0x00000100L
+-#define LB3_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK 0x00001000L
+-#define LB3_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK 0x00010000L
+-#define LB3_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK 0x00100000L
+-#define LB3_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK 0x10000000L
+-#define LB3_DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK 0x80000000L
+-
+-
+-// addressBlock: dce_dc_dcfe3_dispdec
+-//DCFE3_DCFE_CLOCK_CONTROL
+-#define DCFE3_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x4
+-#define DCFE3_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x8
+-#define DCFE3_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0xc
+-#define DCFE3_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE__SHIFT 0xf
+-#define DCFE3_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE__SHIFT 0x11
+-#define DCFE3_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL__SHIFT 0x18
+-#define DCFE3_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE__SHIFT 0x1f
+-#define DCFE3_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x00000010L
+-#define DCFE3_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE_MASK 0x00000100L
+-#define DCFE3_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE_MASK 0x00001000L
+-#define DCFE3_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE_MASK 0x00008000L
+-#define DCFE3_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE_MASK 0x00020000L
+-#define DCFE3_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL_MASK 0x1F000000L
+-#define DCFE3_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE_MASK 0x80000000L
+-//DCFE3_DCFE_SOFT_RESET
+-#define DCFE3_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET__SHIFT 0x0
+-#define DCFE3_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET__SHIFT 0x1
+-#define DCFE3_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET__SHIFT 0x2
+-#define DCFE3_DCFE_SOFT_RESET__SCL_SOFT_RESET__SHIFT 0x3
+-#define DCFE3_DCFE_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4
+-#define DCFE3_DCFE_SOFT_RESET__PSCL_SOFT_RESET__SHIFT 0x5
+-#define DCFE3_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET_MASK 0x00000001L
+-#define DCFE3_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET_MASK 0x00000002L
+-#define DCFE3_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET_MASK 0x00000004L
+-#define DCFE3_DCFE_SOFT_RESET__SCL_SOFT_RESET_MASK 0x00000008L
+-#define DCFE3_DCFE_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x00000010L
+-#define DCFE3_DCFE_SOFT_RESET__PSCL_SOFT_RESET_MASK 0x00000020L
+-//DCFE3_DCFE_MEM_PWR_CTRL
+-#define DCFE3_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE__SHIFT 0x0
+-#define DCFE3_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS__SHIFT 0x2
+-#define DCFE3_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE__SHIFT 0x3
+-#define DCFE3_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS__SHIFT 0x5
+-#define DCFE3_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE__SHIFT 0x6
+-#define DCFE3_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS__SHIFT 0x8
+-#define DCFE3_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE__SHIFT 0x9
+-#define DCFE3_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS__SHIFT 0xb
+-#define DCFE3_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE__SHIFT 0xc
+-#define DCFE3_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS__SHIFT 0xe
+-#define DCFE3_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE__SHIFT 0xf
+-#define DCFE3_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS__SHIFT 0x11
+-#define DCFE3_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE__SHIFT 0x12
+-#define DCFE3_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS__SHIFT 0x14
+-#define DCFE3_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE__SHIFT 0x15
+-#define DCFE3_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS__SHIFT 0x17
+-#define DCFE3_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE__SHIFT 0x18
+-#define DCFE3_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS__SHIFT 0x1a
+-#define DCFE3_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE__SHIFT 0x1b
+-#define DCFE3_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS__SHIFT 0x1d
+-#define DCFE3_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE_MASK 0x00000003L
+-#define DCFE3_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS_MASK 0x00000004L
+-#define DCFE3_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE_MASK 0x00000018L
+-#define DCFE3_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS_MASK 0x00000020L
+-#define DCFE3_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE_MASK 0x000000C0L
+-#define DCFE3_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS_MASK 0x00000100L
+-#define DCFE3_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE_MASK 0x00000600L
+-#define DCFE3_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS_MASK 0x00000800L
+-#define DCFE3_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE_MASK 0x00003000L
+-#define DCFE3_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS_MASK 0x00004000L
+-#define DCFE3_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE_MASK 0x00018000L
+-#define DCFE3_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK 0x00020000L
+-#define DCFE3_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE_MASK 0x000C0000L
+-#define DCFE3_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS_MASK 0x00100000L
+-#define DCFE3_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE_MASK 0x00600000L
+-#define DCFE3_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS_MASK 0x00800000L
+-#define DCFE3_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE_MASK 0x03000000L
+-#define DCFE3_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS_MASK 0x04000000L
+-#define DCFE3_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE_MASK 0x18000000L
+-#define DCFE3_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS_MASK 0x20000000L
+-//DCFE3_DCFE_MEM_PWR_CTRL2
+-#define DCFE3_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL__SHIFT 0x0
+-#define DCFE3_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2
+-#define DCFE3_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4
+-#define DCFE3_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL__SHIFT 0x6
+-#define DCFE3_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL__SHIFT 0x8
+-#define DCFE3_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL__SHIFT 0xa
+-#define DCFE3_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL__SHIFT 0xc
+-#define DCFE3_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL__SHIFT 0xe
+-#define DCFE3_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE__SHIFT 0x10
+-#define DCFE3_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS__SHIFT 0x12
+-#define DCFE3_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE__SHIFT 0x15
+-#define DCFE3_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS__SHIFT 0x17
+-#define DCFE3_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL_MASK 0x00000003L
+-#define DCFE3_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL_MASK 0x0000000CL
+-#define DCFE3_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL_MASK 0x00000030L
+-#define DCFE3_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL_MASK 0x000000C0L
+-#define DCFE3_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL_MASK 0x00000300L
+-#define DCFE3_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL_MASK 0x00000C00L
+-#define DCFE3_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL_MASK 0x00003000L
+-#define DCFE3_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL_MASK 0x0000C000L
+-#define DCFE3_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE_MASK 0x00030000L
+-#define DCFE3_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS_MASK 0x00040000L
+-#define DCFE3_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE_MASK 0x00600000L
+-#define DCFE3_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS_MASK 0x00800000L
+-//DCFE3_DCFE_MEM_PWR_STATUS
+-#define DCFE3_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE__SHIFT 0x0
+-#define DCFE3_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE__SHIFT 0x2
+-#define DCFE3_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE__SHIFT 0x4
+-#define DCFE3_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x6
+-#define DCFE3_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE__SHIFT 0x8
+-#define DCFE3_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE__SHIFT 0xa
+-#define DCFE3_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE__SHIFT 0xc
+-#define DCFE3_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE__SHIFT 0xe
+-#define DCFE3_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT 0x10
+-#define DCFE3_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE__SHIFT 0x12
+-#define DCFE3_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE__SHIFT 0x14
+-#define DCFE3_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE__SHIFT 0x16
+-#define DCFE3_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK 0x00000003L
+-#define DCFE3_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE_MASK 0x0000000CL
+-#define DCFE3_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE_MASK 0x00000030L
+-#define DCFE3_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE_MASK 0x000000C0L
+-#define DCFE3_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE_MASK 0x00000300L
+-#define DCFE3_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE_MASK 0x00000C00L
+-#define DCFE3_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE_MASK 0x00003000L
+-#define DCFE3_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE_MASK 0x0000C000L
+-#define DCFE3_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE_MASK 0x00030000L
+-#define DCFE3_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK 0x000C0000L
+-#define DCFE3_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE_MASK 0x00300000L
+-#define DCFE3_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE_MASK 0x00C00000L
+-//DCFE3_DCFE_MISC
+-#define DCFE3_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN__SHIFT 0x0
+-#define DCFE3_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN_MASK 0x00000001L
+-//DCFE3_DCFE_FLUSH
+-#define DCFE3_DCFE_FLUSH__FLUSH_OCCURED__SHIFT 0x0
+-#define DCFE3_DCFE_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT 0x1
+-#define DCFE3_DCFE_FLUSH__FLUSH_DEEP__SHIFT 0x2
+-#define DCFE3_DCFE_FLUSH__CLEAR_FLUSH_DEEP__SHIFT 0x3
+-#define DCFE3_DCFE_FLUSH__ALL_MC_REQ_RET__SHIFT 0x4
+-#define DCFE3_DCFE_FLUSH__FLUSH_OCCURED_MASK 0x00000001L
+-#define DCFE3_DCFE_FLUSH__CLEAR_FLUSH_OCCURED_MASK 0x00000002L
+-#define DCFE3_DCFE_FLUSH__FLUSH_DEEP_MASK 0x00000004L
+-#define DCFE3_DCFE_FLUSH__CLEAR_FLUSH_DEEP_MASK 0x00000008L
+-#define DCFE3_DCFE_FLUSH__ALL_MC_REQ_RET_MASK 0x00000010L
+-
+-
+-// addressBlock: dce_dc_dc_perfmon6_dispdec
+-//DC_PERFMON6_PERFCOUNTER_CNTL
+-#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+-#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+-#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+-#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+-#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+-#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
+-#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+-#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+-#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+-#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+-#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+-#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
+-#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+-#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+-#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+-#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+-#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+-#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+-#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
+-#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+-#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+-#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+-#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+-#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+-#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
+-#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+-//DC_PERFMON6_PERFCOUNTER_CNTL2
+-#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+-#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+-#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+-#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+-#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+-#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+-#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+-#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+-//DC_PERFMON6_PERFCOUNTER_STATE
+-#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+-#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+-#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+-#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+-#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+-#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+-#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+-#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+-#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+-#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+-#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+-#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+-#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+-#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+-#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+-#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+-#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+-#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+-#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+-#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+-#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+-#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+-#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+-#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+-#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+-#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+-#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+-#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+-#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+-#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+-#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+-#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+-//DC_PERFMON6_PERFMON_CNTL
+-#define DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+-#define DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+-#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+-#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+-#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+-#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+-#define DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+-#define DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+-#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+-#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+-#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+-#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+-//DC_PERFMON6_PERFMON_CNTL2
+-#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+-#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+-#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+-#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+-#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+-#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+-#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+-#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+-//DC_PERFMON6_PERFMON_CVALUE_INT_MISC
+-#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+-#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+-#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+-#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+-#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+-#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+-#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+-#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+-#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+-#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+-#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+-#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+-#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+-#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+-#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+-#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+-#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+-#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+-#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+-#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+-#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+-#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+-#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+-#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+-#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+-#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+-#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+-#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+-#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+-#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+-#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+-#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+-#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+-#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+-//DC_PERFMON6_PERFMON_CVALUE_LOW
+-#define DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+-#define DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+-//DC_PERFMON6_PERFMON_HI
+-#define DC_PERFMON6_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+-#define DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+-#define DC_PERFMON6_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+-#define DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+-//DC_PERFMON6_PERFMON_LOW
+-#define DC_PERFMON6_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+-#define DC_PERFMON6_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dmif_pg3_dispdec
+-//DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1
+-#define DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
+-#define DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
+-#define DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0x0000FFFFL
+-#define DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xFFFF0000L
+-//DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2
+-#define DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
+-#define DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
+-#define DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0x0000FFFFL
+-#define DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xFFFF0000L
+-//DMIF_PG3_DPG_WATERMARK_MASK_CONTROL
+-#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
+-#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x4
+-#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
+-#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK__SHIFT 0xc
+-#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0xf
+-#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x12
+-#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL__SHIFT 0x13
+-#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL__SHIFT 0x14
+-#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000007L
+-#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000070L
+-#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x00000700L
+-#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK_MASK 0x00007000L
+-#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00038000L
+-#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x00040000L
+-#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL_MASK 0x00080000L
+-#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL_MASK 0x3FF00000L
+-//DMIF_PG3_DPG_PIPE_URGENCY_CONTROL
+-#define DMIF_PG3_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
+-#define DMIF_PG3_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
+-#define DMIF_PG3_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0x0000FFFFL
+-#define DMIF_PG3_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xFFFF0000L
+-//DMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL
+-#define DMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK__SHIFT 0x0
+-#define DMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK__SHIFT 0x10
+-#define DMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK_MASK 0x0000FFFFL
+-#define DMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK_MASK 0xFFFF0000L
+-//DMIF_PG3_DPG_PIPE_STUTTER_CONTROL
+-#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
+-#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
+-#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
+-#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
+-#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
+-#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
+-#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
+-#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH__SHIFT 0x10
+-#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x14
+-#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x15
+-#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x16
+-#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x17
+-#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0x1a
+-#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0x1b
+-#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L
+-#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L
+-#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x00000020L
+-#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x00000040L
+-#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x00000080L
+-#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x00000400L
+-#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x00000800L
+-#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH_MASK 0x00010000L
+-#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x00100000L
+-#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x00200000L
+-#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x00400000L
+-#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x00800000L
+-#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x04000000L
+-#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x08000000L
+-//DMIF_PG3_DPG_PIPE_STUTTER_CONTROL2
+-#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x0
+-#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK__SHIFT 0x10
+-#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0x0000FFFFL
+-#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK 0xFFFF0000L
+-//DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL
+-#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE__SHIFT 0x0
+-#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE__SHIFT 0x1
+-#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
+-#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
+-#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
+-#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
+-#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK__SHIFT 0xf
+-#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE_MASK 0x00000001L
+-#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE_MASK 0x00000002L
+-#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L
+-#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x00000100L
+-#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON_MASK 0x00000200L
+-#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT_MASK 0x00000400L
+-#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK_MASK 0xFFFF8000L
+-//DMIF_PG3_DPG_REPEATER_PROGRAM
+-#define DMIF_PG3_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
+-#define DMIF_PG3_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
+-#define DMIF_PG3_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x00000007L
+-#define DMIF_PG3_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x00000070L
+-//DMIF_PG3_DPG_CHK_PRE_PROC_CNTL
+-#define DMIF_PG3_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0
+-#define DMIF_PG3_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x00000001L
+-//DMIF_PG3_DPG_DVMM_STATUS
+-#define DMIF_PG3_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED__SHIFT 0x0
+-#define DMIF_PG3_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED__SHIFT 0x1
+-#define DMIF_PG3_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR__SHIFT 0x4
+-#define DMIF_PG3_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR__SHIFT 0x5
+-#define DMIF_PG3_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_MASK 0x00000001L
+-#define DMIF_PG3_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_MASK 0x00000002L
+-#define DMIF_PG3_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR_MASK 0x00000010L
+-#define DMIF_PG3_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR_MASK 0x00000020L
+-
+-
+-// addressBlock: dce_dc_scl3_dispdec
+-//SCL3_SCL_COEF_RAM_SELECT
+-#define SCL3_SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0
+-#define SCL3_SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8
+-#define SCL3_SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10
+-#define SCL3_SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x0000000FL
+-#define SCL3_SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x00000F00L
+-#define SCL3_SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x00070000L
+-//SCL3_SCL_COEF_RAM_TAP_DATA
+-#define SCL3_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0
+-#define SCL3_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
+-#define SCL3_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10
+-#define SCL3_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
+-#define SCL3_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL
+-#define SCL3_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L
+-#define SCL3_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L
+-#define SCL3_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L
+-//SCL3_SCL_MODE
+-#define SCL3_SCL_MODE__SCL_MODE__SHIFT 0x0
+-#define SCL3_SCL_MODE__SCL_PSCL_EN__SHIFT 0x4
+-#define SCL3_SCL_MODE__SCL_MODE_MASK 0x00000003L
+-#define SCL3_SCL_MODE__SCL_PSCL_EN_MASK 0x00000010L
+-//SCL3_SCL_TAP_CONTROL
+-#define SCL3_SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0
+-#define SCL3_SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x8
+-#define SCL3_SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x00000007L
+-#define SCL3_SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0x00000F00L
+-//SCL3_SCL_CONTROL
+-#define SCL3_SCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
+-#define SCL3_SCL_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4
+-#define SCL3_SCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L
+-#define SCL3_SCL_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x00000010L
+-//SCL3_SCL_BYPASS_CONTROL
+-#define SCL3_SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT 0x0
+-#define SCL3_SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x00000003L
+-//SCL3_SCL_MANUAL_REPLICATE_CONTROL
+-#define SCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
+-#define SCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
+-#define SCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL
+-#define SCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L
+-//SCL3_SCL_AUTOMATIC_MODE_CONTROL
+-#define SCL3_SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0
+-#define SCL3_SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10
+-#define SCL3_SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x00000001L
+-#define SCL3_SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x00010000L
+-//SCL3_SCL_HORZ_FILTER_CONTROL
+-#define SCL3_SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT 0x0
+-#define SCL3_SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+-#define SCL3_SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK 0x00000001L
+-#define SCL3_SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
+-//SCL3_SCL_HORZ_FILTER_SCALE_RATIO
+-#define SCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
+-#define SCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL
+-//SCL3_SCL_HORZ_FILTER_INIT
+-#define SCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
+-#define SCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
+-#define SCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL
+-#define SCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L
+-//SCL3_SCL_VERT_FILTER_CONTROL
+-#define SCL3_SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT 0x0
+-#define SCL3_SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+-#define SCL3_SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK 0x00000001L
+-#define SCL3_SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
+-//SCL3_SCL_VERT_FILTER_SCALE_RATIO
+-#define SCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
+-#define SCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL
+-//SCL3_SCL_VERT_FILTER_INIT
+-#define SCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
+-#define SCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
+-#define SCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL
+-#define SCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x07000000L
+-//SCL3_SCL_VERT_FILTER_INIT_BOT
+-#define SCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
+-#define SCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
+-#define SCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL
+-#define SCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x07000000L
+-//SCL3_SCL_ROUND_OFFSET
+-#define SCL3_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0
+-#define SCL3_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10
+-#define SCL3_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0x0000FFFFL
+-#define SCL3_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xFFFF0000L
+-//SCL3_SCL_UPDATE
+-#define SCL3_SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
+-#define SCL3_SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8
+-#define SCL3_SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10
+-#define SCL3_SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18
+-#define SCL3_SCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L
+-#define SCL3_SCL_UPDATE__SCL_UPDATE_TAKEN_MASK 0x00000100L
+-#define SCL3_SCL_UPDATE__SCL_UPDATE_LOCK_MASK 0x00010000L
+-#define SCL3_SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x01000000L
+-//SCL3_SCL_F_SHARP_CONTROL
+-#define SCL3_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT 0x0
+-#define SCL3_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT 0x4
+-#define SCL3_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT 0x8
+-#define SCL3_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT 0xc
+-#define SCL3_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK 0x00000007L
+-#define SCL3_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK 0x00000010L
+-#define SCL3_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK 0x00000700L
+-#define SCL3_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK 0x00001000L
+-//SCL3_SCL_ALU_CONTROL
+-#define SCL3_SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0
+-#define SCL3_SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x00000001L
+-//SCL3_SCL_COEF_RAM_CONFLICT_STATUS
+-#define SCL3_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT 0x0
+-#define SCL3_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT 0x8
+-#define SCL3_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT 0xc
+-#define SCL3_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10
+-#define SCL3_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK 0x00000001L
+-#define SCL3_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK 0x00000100L
+-#define SCL3_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK 0x00001000L
+-#define SCL3_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK 0x00010000L
+-//SCL3_VIEWPORT_START_SECONDARY
+-#define SCL3_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0
+-#define SCL3_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10
+-#define SCL3_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x00003FFFL
+-#define SCL3_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3FFF0000L
+-//SCL3_VIEWPORT_START
+-#define SCL3_VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0
+-#define SCL3_VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10
+-#define SCL3_VIEWPORT_START__VIEWPORT_Y_START_MASK 0x00003FFFL
+-#define SCL3_VIEWPORT_START__VIEWPORT_X_START_MASK 0x3FFF0000L
+-//SCL3_VIEWPORT_SIZE
+-#define SCL3_VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0
+-#define SCL3_VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10
+-#define SCL3_VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x00003FFFL
+-#define SCL3_VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x3FFF0000L
+-//SCL3_EXT_OVERSCAN_LEFT_RIGHT
+-#define SCL3_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
+-#define SCL3_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
+-#define SCL3_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL
+-#define SCL3_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L
+-//SCL3_EXT_OVERSCAN_TOP_BOTTOM
+-#define SCL3_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
+-#define SCL3_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
+-#define SCL3_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL
+-#define SCL3_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L
+-//SCL3_SCL_MODE_CHANGE_DET1
+-#define SCL3_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0
+-#define SCL3_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4
+-#define SCL3_SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7
+-#define SCL3_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x00000001L
+-#define SCL3_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x00000010L
+-#define SCL3_SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0x0FFFFF80L
+-//SCL3_SCL_MODE_CHANGE_DET2
+-#define SCL3_SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0
+-#define SCL3_SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x001FFFFFL
+-//SCL3_SCL_MODE_CHANGE_DET3
+-#define SCL3_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0
+-#define SCL3_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10
+-#define SCL3_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x00003FFFL
+-#define SCL3_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3FFF0000L
+-//SCL3_SCL_MODE_CHANGE_MASK
+-#define SCL3_SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0
+-#define SCL3_SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x00000001L
+-
+-
+-// addressBlock: dce_dc_blnd3_dispdec
+-//BLND3_BLND_CONTROL
+-#define BLND3_BLND_CONTROL__BLND_GLOBAL_GAIN__SHIFT 0x0
+-#define BLND3_BLND_CONTROL__BLND_MODE__SHIFT 0x8
+-#define BLND3_BLND_CONTROL__BLND_STEREO_TYPE__SHIFT 0xa
+-#define BLND3_BLND_CONTROL__BLND_STEREO_POLARITY__SHIFT 0xc
+-#define BLND3_BLND_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT 0xd
+-#define BLND3_BLND_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10
+-#define BLND3_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x12
+-#define BLND3_BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14
+-#define BLND3_BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18
+-#define BLND3_BLND_CONTROL__BLND_GLOBAL_GAIN_MASK 0x000000FFL
+-#define BLND3_BLND_CONTROL__BLND_MODE_MASK 0x00000300L
+-#define BLND3_BLND_CONTROL__BLND_STEREO_TYPE_MASK 0x00000C00L
+-#define BLND3_BLND_CONTROL__BLND_STEREO_POLARITY_MASK 0x00001000L
+-#define BLND3_BLND_CONTROL__BLND_FEEDTHROUGH_EN_MASK 0x00002000L
+-#define BLND3_BLND_CONTROL__BLND_ALPHA_MODE_MASK 0x00030000L
+-#define BLND3_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00040000L
+-#define BLND3_BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x00100000L
+-#define BLND3_BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xFF000000L
+-//BLND3_BLND_SM_CONTROL2
+-#define BLND3_BLND_SM_CONTROL2__SM_MODE__SHIFT 0x0
+-#define BLND3_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4
+-#define BLND3_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5
+-#define BLND3_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
+-#define BLND3_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
+-#define BLND3_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18
+-#define BLND3_BLND_SM_CONTROL2__SM_MODE_MASK 0x00000007L
+-#define BLND3_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x00000010L
+-#define BLND3_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x00000020L
+-#define BLND3_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L
+-#define BLND3_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L
+-#define BLND3_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x01000000L
+-//BLND3_BLND_CONTROL2
+-#define BLND3_BLND_CONTROL2__PTI_ENABLE__SHIFT 0x0
+-#define BLND3_BLND_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT 0x4
+-#define BLND3_BLND_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT 0x6
+-#define BLND3_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT 0x7
+-#define BLND3_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT 0x8
+-#define BLND3_BLND_CONTROL2__PTI_ENABLE_MASK 0x00000001L
+-#define BLND3_BLND_CONTROL2__PTI_NEW_PIXEL_GAP_MASK 0x00000030L
+-#define BLND3_BLND_CONTROL2__BLND_NEW_PIXEL_MODE_MASK 0x00000040L
+-#define BLND3_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK 0x00000080L
+-#define BLND3_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK 0x00000100L
+-//BLND3_BLND_UPDATE
+-#define BLND3_BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0
+-#define BLND3_BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8
+-#define BLND3_BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10
+-#define BLND3_BLND_UPDATE__BLND_UPDATE_PENDING_MASK 0x00000001L
+-#define BLND3_BLND_UPDATE__BLND_UPDATE_TAKEN_MASK 0x00000100L
+-#define BLND3_BLND_UPDATE__BLND_UPDATE_LOCK_MASK 0x00010000L
+-//BLND3_BLND_UNDERFLOW_INTERRUPT
+-#define BLND3_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0
+-#define BLND3_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8
+-#define BLND3_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc
+-#define BLND3_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10
+-#define BLND3_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x00000001L
+-#define BLND3_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x00000100L
+-#define BLND3_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x00001000L
+-#define BLND3_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x00030000L
+-//BLND3_BLND_V_UPDATE_LOCK
+-#define BLND3_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0
+-#define BLND3_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1
+-#define BLND3_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10
+-#define BLND3_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c
+-#define BLND3_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT 0x1d
+-#define BLND3_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT 0x1f
+-#define BLND3_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x00000001L
+-#define BLND3_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x00000002L
+-#define BLND3_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x00010000L
+-#define BLND3_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000L
+-#define BLND3_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK 0x20000000L
+-#define BLND3_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK 0x80000000L
+-//BLND3_BLND_REG_UPDATE_STATUS
+-#define BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT 0x0
+-#define BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT 0x1
+-#define BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2
+-#define BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3
+-#define BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT 0x6
+-#define BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT 0x7
+-#define BLND3_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT 0x8
+-#define BLND3_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT 0x9
+-#define BLND3_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT 0xa
+-#define BLND3_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT 0xb
+-#define BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK 0x00000001L
+-#define BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK 0x00000002L
+-#define BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK 0x00000004L
+-#define BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK 0x00000008L
+-#define BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK 0x00000040L
+-#define BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK 0x00000080L
+-#define BLND3_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK 0x00000100L
+-#define BLND3_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK 0x00000200L
+-#define BLND3_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK 0x00000400L
+-#define BLND3_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK 0x00000800L
+-
+-
+-// addressBlock: dce_dc_crtc3_dispdec
+-//CRTC3_CRTC_H_BLANK_EARLY_NUM
+-#define CRTC3_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0
+-#define CRTC3_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10
+-#define CRTC3_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x000003FFL
+-#define CRTC3_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x00010000L
+-//CRTC3_CRTC_H_TOTAL
+-#define CRTC3_CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0
+-#define CRTC3_CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x00003FFFL
+-//CRTC3_CRTC_H_BLANK_START_END
+-#define CRTC3_CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0
+-#define CRTC3_CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10
+-#define CRTC3_CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x00003FFFL
+-#define CRTC3_CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3FFF0000L
+-//CRTC3_CRTC_H_SYNC_A
+-#define CRTC3_CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0
+-#define CRTC3_CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10
+-#define CRTC3_CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x00003FFFL
+-#define CRTC3_CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3FFF0000L
+-//CRTC3_CRTC_H_SYNC_A_CNTL
+-#define CRTC3_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0
+-#define CRTC3_CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10
+-#define CRTC3_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11
+-#define CRTC3_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x00000001L
+-#define CRTC3_CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x00010000L
+-#define CRTC3_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x00020000L
+-//CRTC3_CRTC_H_SYNC_B
+-#define CRTC3_CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0
+-#define CRTC3_CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10
+-#define CRTC3_CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x00003FFFL
+-#define CRTC3_CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x3FFF0000L
+-//CRTC3_CRTC_H_SYNC_B_CNTL
+-#define CRTC3_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0
+-#define CRTC3_CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10
+-#define CRTC3_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11
+-#define CRTC3_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x00000001L
+-#define CRTC3_CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x00010000L
+-#define CRTC3_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x00020000L
+-//CRTC3_CRTC_VBI_END
+-#define CRTC3_CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x0
+-#define CRTC3_CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x10
+-#define CRTC3_CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x00003FFFL
+-#define CRTC3_CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x3FFF0000L
+-//CRTC3_CRTC_V_TOTAL
+-#define CRTC3_CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0
+-#define CRTC3_CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x00003FFFL
+-//CRTC3_CRTC_V_TOTAL_MIN
+-#define CRTC3_CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0
+-#define CRTC3_CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x00003FFFL
+-//CRTC3_CRTC_V_TOTAL_MAX
+-#define CRTC3_CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0
+-#define CRTC3_CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10
+-#define CRTC3_CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x00003FFFL
+-#define CRTC3_CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x00010000L
+-//CRTC3_CRTC_V_TOTAL_CONTROL
+-#define CRTC3_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0
+-#define CRTC3_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4
+-#define CRTC3_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8
+-#define CRTC3_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc
+-#define CRTC3_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf
+-#define CRTC3_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10
+-#define CRTC3_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x00000001L
+-#define CRTC3_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x00000010L
+-#define CRTC3_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x00000100L
+-#define CRTC3_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x00001000L
+-#define CRTC3_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00008000L
+-#define CRTC3_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L
+-//CRTC3_CRTC_V_TOTAL_INT_STATUS
+-#define CRTC3_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0
+-#define CRTC3_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4
+-#define CRTC3_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8
+-#define CRTC3_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc
+-#define CRTC3_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L
+-#define CRTC3_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L
+-#define CRTC3_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L
+-#define CRTC3_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L
+-//CRTC3_CRTC_VSYNC_NOM_INT_STATUS
+-#define CRTC3_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0
+-#define CRTC3_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4
+-#define CRTC3_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x00000001L
+-#define CRTC3_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L
+-//CRTC3_CRTC_V_BLANK_START_END
+-#define CRTC3_CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0
+-#define CRTC3_CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10
+-#define CRTC3_CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x00003FFFL
+-#define CRTC3_CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3FFF0000L
+-//CRTC3_CRTC_V_SYNC_A
+-#define CRTC3_CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0
+-#define CRTC3_CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10
+-#define CRTC3_CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x00003FFFL
+-#define CRTC3_CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3FFF0000L
+-//CRTC3_CRTC_V_SYNC_A_CNTL
+-#define CRTC3_CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0
+-#define CRTC3_CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x00000001L
+-//CRTC3_CRTC_V_SYNC_B
+-#define CRTC3_CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0
+-#define CRTC3_CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10
+-#define CRTC3_CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x00003FFFL
+-#define CRTC3_CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x3FFF0000L
+-//CRTC3_CRTC_V_SYNC_B_CNTL
+-#define CRTC3_CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0
+-#define CRTC3_CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x00000001L
+-//CRTC3_CRTC_DTMTEST_CNTL
+-#define CRTC3_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0
+-#define CRTC3_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1
+-#define CRTC3_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x00000001L
+-#define CRTC3_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x0000001EL
+-//CRTC3_CRTC_DTMTEST_STATUS_POSITION
+-#define CRTC3_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0
+-#define CRTC3_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10
+-#define CRTC3_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x00003FFFL
+-#define CRTC3_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x3FFF0000L
+-//CRTC3_CRTC_TRIGA_CNTL
+-#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0
+-#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5
+-#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8
+-#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9
+-#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa
+-#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb
+-#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
+-#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
+-#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14
+-#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18
+-#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f
+-#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x0000001FL
+-#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0x000000E0L
+-#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000100L
+-#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x00000200L
+-#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x00000400L
+-#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x00000800L
+-#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
+-#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
+-#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L
+-#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1F000000L
+-#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000L
+-//CRTC3_CRTC_TRIGA_MANUAL_TRIG
+-#define CRTC3_CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0
+-#define CRTC3_CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x00000001L
+-//CRTC3_CRTC_TRIGB_CNTL
+-#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0
+-#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5
+-#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8
+-#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9
+-#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa
+-#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb
+-#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
+-#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
+-#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14
+-#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18
+-#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f
+-#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x0000001FL
+-#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0x000000E0L
+-#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000100L
+-#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x00000200L
+-#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x00000400L
+-#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x00000800L
+-#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
+-#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
+-#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L
+-#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1F000000L
+-#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000L
+-//CRTC3_CRTC_TRIGB_MANUAL_TRIG
+-#define CRTC3_CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0
+-#define CRTC3_CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x00000001L
+-//CRTC3_CRTC_FORCE_COUNT_NOW_CNTL
+-#define CRTC3_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0
+-#define CRTC3_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4
+-#define CRTC3_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8
+-#define CRTC3_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10
+-#define CRTC3_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18
+-#define CRTC3_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x00000003L
+-#define CRTC3_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L
+-#define CRTC3_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L
+-#define CRTC3_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L
+-#define CRTC3_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L
+-//CRTC3_CRTC_FLOW_CONTROL
+-#define CRTC3_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0
+-#define CRTC3_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8
+-#define CRTC3_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10
+-#define CRTC3_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18
+-#define CRTC3_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL
+-#define CRTC3_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x00000100L
+-#define CRTC3_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L
+-#define CRTC3_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L
+-//CRTC3_CRTC_STEREO_FORCE_NEXT_EYE
+-#define CRTC3_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0
+-#define CRTC3_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER__SHIFT 0x8
+-#define CRTC3_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER__SHIFT 0x10
+-#define CRTC3_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L
+-#define CRTC3_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L
+-#define CRTC3_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L
+-//CRTC3_CRTC_AVSYNC_COUNTER
+-#define CRTC3_CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER__SHIFT 0x0
+-#define CRTC3_CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER_MASK 0xFFFFFFFFL
+-//CRTC3_CRTC_CONTROL
+-#define CRTC3_CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x0
+-#define CRTC3_CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4
+-#define CRTC3_CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8
+-#define CRTC3_CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc
+-#define CRTC3_CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd
+-#define CRTC3_CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe
+-#define CRTC3_CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10
+-#define CRTC3_CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14
+-#define CRTC3_CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d
+-#define CRTC3_CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e
+-#define CRTC3_CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f
+-#define CRTC3_CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x00000001L
+-#define CRTC3_CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x00000010L
+-#define CRTC3_CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x00000300L
+-#define CRTC3_CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x00001000L
+-#define CRTC3_CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x00002000L
+-#define CRTC3_CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x00004000L
+-#define CRTC3_CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x00010000L
+-#define CRTC3_CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x00700000L
+-#define CRTC3_CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000L
+-#define CRTC3_CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L
+-#define CRTC3_CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L
+-//CRTC3_CRTC_BLANK_CONTROL
+-#define CRTC3_CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0
+-#define CRTC3_CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8
+-#define CRTC3_CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10
+-#define CRTC3_CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x00000001L
+-#define CRTC3_CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x00000100L
+-#define CRTC3_CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x00010000L
+-//CRTC3_CRTC_INTERLACE_CONTROL
+-#define CRTC3_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0
+-#define CRTC3_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10
+-#define CRTC3_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x00000001L
+-#define CRTC3_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L
+-//CRTC3_CRTC_INTERLACE_STATUS
+-#define CRTC3_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0
+-#define CRTC3_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1
+-#define CRTC3_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x00000001L
+-#define CRTC3_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x00000002L
+-//CRTC3_CRTC_FIELD_INDICATION_CONTROL
+-#define CRTC3_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0
+-#define CRTC3_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1
+-#define CRTC3_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x00000001L
+-#define CRTC3_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x00000002L
+-//CRTC3_CRTC_PIXEL_DATA_READBACK0
+-#define CRTC3_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0
+-#define CRTC3_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10
+-#define CRTC3_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0x00000FFFL
+-#define CRTC3_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0x0FFF0000L
+-//CRTC3_CRTC_PIXEL_DATA_READBACK1
+-#define CRTC3_CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0
+-#define CRTC3_CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0x00000FFFL
+-//CRTC3_CRTC_STATUS
+-#define CRTC3_CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x0
+-#define CRTC3_CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1
+-#define CRTC3_CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x2
+-#define CRTC3_CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x3
+-#define CRTC3_CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x4
+-#define CRTC3_CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5
+-#define CRTC3_CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x10
+-#define CRTC3_CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11
+-#define CRTC3_CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x12
+-#define CRTC3_CRTC_STATUS__CRTC_V_BLANK_MASK 0x00000001L
+-#define CRTC3_CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x00000002L
+-#define CRTC3_CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x00000004L
+-#define CRTC3_CRTC_STATUS__CRTC_V_UPDATE_MASK 0x00000008L
+-#define CRTC3_CRTC_STATUS__CRTC_V_START_LINE_MASK 0x00000010L
+-#define CRTC3_CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x00000020L
+-#define CRTC3_CRTC_STATUS__CRTC_H_BLANK_MASK 0x00010000L
+-#define CRTC3_CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x00020000L
+-#define CRTC3_CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x00040000L
+-//CRTC3_CRTC_STATUS_POSITION
+-#define CRTC3_CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0
+-#define CRTC3_CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10
+-#define CRTC3_CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x00003FFFL
+-#define CRTC3_CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x3FFF0000L
+-//CRTC3_CRTC_NOM_VERT_POSITION
+-#define CRTC3_CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0
+-#define CRTC3_CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x00003FFFL
+-//CRTC3_CRTC_STATUS_FRAME_COUNT
+-#define CRTC3_CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0
+-#define CRTC3_CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0x00FFFFFFL
+-//CRTC3_CRTC_STATUS_VF_COUNT
+-#define CRTC3_CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0
+-#define CRTC3_CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x3FFFFFFFL
+-//CRTC3_CRTC_STATUS_HV_COUNT
+-#define CRTC3_CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0
+-#define CRTC3_CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x3FFFFFFFL
+-//CRTC3_CRTC_COUNT_CONTROL
+-#define CRTC3_CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0
+-#define CRTC3_CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1
+-#define CRTC3_CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x00000001L
+-#define CRTC3_CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x0000001EL
+-//CRTC3_CRTC_COUNT_RESET
+-#define CRTC3_CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0
+-#define CRTC3_CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x00000001L
+-//CRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE
+-#define CRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0
+-#define CRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L
+-//CRTC3_CRTC_VERT_SYNC_CONTROL
+-#define CRTC3_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0
+-#define CRTC3_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8
+-#define CRTC3_CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10
+-#define CRTC3_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L
+-#define CRTC3_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L
+-#define CRTC3_CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L
+-//CRTC3_CRTC_STEREO_STATUS
+-#define CRTC3_CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0
+-#define CRTC3_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8
+-#define CRTC3_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10
+-#define CRTC3_CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG__SHIFT 0x14
+-#define CRTC3_CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18
+-#define CRTC3_CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x00000001L
+-#define CRTC3_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x00000100L
+-#define CRTC3_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x00010000L
+-#define CRTC3_CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG_MASK 0x00100000L
+-#define CRTC3_CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L
+-//CRTC3_CRTC_STEREO_CONTROL
+-#define CRTC3_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0
+-#define CRTC3_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf
+-#define CRTC3_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10
+-#define CRTC3_CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11
+-#define CRTC3_CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12
+-#define CRTC3_CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM__SHIFT 0x13
+-#define CRTC3_CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14
+-#define CRTC3_CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18
+-#define CRTC3_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00003FFFL
+-#define CRTC3_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L
+-#define CRTC3_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x00010000L
+-#define CRTC3_CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L
+-#define CRTC3_CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L
+-#define CRTC3_CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM_MASK 0x00080000L
+-#define CRTC3_CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L
+-#define CRTC3_CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x01000000L
+-//CRTC3_CRTC_SNAPSHOT_STATUS
+-#define CRTC3_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0
+-#define CRTC3_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1
+-#define CRTC3_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2
+-#define CRTC3_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x00000001L
+-#define CRTC3_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x00000002L
+-#define CRTC3_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L
+-//CRTC3_CRTC_SNAPSHOT_CONTROL
+-#define CRTC3_CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0
+-#define CRTC3_CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L
+-//CRTC3_CRTC_SNAPSHOT_POSITION
+-#define CRTC3_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0
+-#define CRTC3_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10
+-#define CRTC3_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x00003FFFL
+-#define CRTC3_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x3FFF0000L
+-//CRTC3_CRTC_SNAPSHOT_FRAME
+-#define CRTC3_CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0
+-#define CRTC3_CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL
+-//CRTC3_CRTC_START_LINE_CONTROL
+-#define CRTC3_CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0
+-#define CRTC3_CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x1
+-#define CRTC3_CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x2
+-#define CRTC3_CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x8
+-#define CRTC3_CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc
+-#define CRTC3_CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x00000001L
+-#define CRTC3_CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x00000002L
+-#define CRTC3_CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x00000004L
+-#define CRTC3_CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x00000100L
+-#define CRTC3_CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0x000FF000L
+-//CRTC3_CRTC_INTERRUPT_CONTROL
+-#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0
+-#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1
+-#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4
+-#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5
+-#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8
+-#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9
+-#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10
+-#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11
+-#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18
+-#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19
+-#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a
+-#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b
+-#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c
+-#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d
+-#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e
+-#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f
+-#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x00000001L
+-#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x00000002L
+-#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x00000010L
+-#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x00000020L
+-#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L
+-#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L
+-#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L
+-#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L
+-#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x01000000L
+-#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x02000000L
+-#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x04000000L
+-#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x08000000L
+-#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000L
+-#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000L
+-#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L
+-#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L
+-//CRTC3_CRTC_UPDATE_LOCK
+-#define CRTC3_CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0
+-#define CRTC3_CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x00000001L
+-//CRTC3_CRTC_DOUBLE_BUFFER_CONTROL
+-#define CRTC3_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0
+-#define CRTC3_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8
+-#define CRTC3_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10
+-#define CRTC3_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18
+-#define CRTC3_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x19
+-#define CRTC3_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x00000001L
+-#define CRTC3_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x00000100L
+-#define CRTC3_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L
+-#define CRTC3_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x01000000L
+-#define CRTC3_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x02000000L
+-//CRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE
+-#define CRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0
+-#define CRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x00000001L
+-//CRTC3_CRTC_TEST_PATTERN_CONTROL
+-#define CRTC3_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0
+-#define CRTC3_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8
+-#define CRTC3_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10
+-#define CRTC3_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18
+-#define CRTC3_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x00000001L
+-#define CRTC3_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x00000700L
+-#define CRTC3_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L
+-#define CRTC3_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xFF000000L
+-//CRTC3_CRTC_TEST_PATTERN_PARAMETERS
+-#define CRTC3_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0
+-#define CRTC3_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4
+-#define CRTC3_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8
+-#define CRTC3_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc
+-#define CRTC3_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10
+-#define CRTC3_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0x0000000FL
+-#define CRTC3_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0x000000F0L
+-#define CRTC3_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0x00000F00L
+-#define CRTC3_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0x0000F000L
+-#define CRTC3_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xFFFF0000L
+-//CRTC3_CRTC_TEST_PATTERN_COLOR
+-#define CRTC3_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0
+-#define CRTC3_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10
+-#define CRTC3_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0x0000FFFFL
+-#define CRTC3_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x003F0000L
+-//CRTC3_CRTC_MASTER_UPDATE_LOCK
+-#define CRTC3_CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0
+-#define CRTC3_CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8
+-#define CRTC3_CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK__SHIFT 0x10
+-#define CRTC3_CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x00000001L
+-#define CRTC3_CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x00000100L
+-#define CRTC3_CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK_MASK 0x00010000L
+-//CRTC3_CRTC_MASTER_UPDATE_MODE
+-#define CRTC3_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0
+-#define CRTC3_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10
+-#define CRTC3_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x00000007L
+-#define CRTC3_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00030000L
+-//CRTC3_CRTC_MVP_INBAND_CNTL_INSERT
+-#define CRTC3_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0
+-#define CRTC3_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8
+-#define CRTC3_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x00000003L
+-#define CRTC3_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xFFFFFF00L
+-//CRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER
+-#define CRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0
+-#define CRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0x000000FFL
+-//CRTC3_CRTC_MVP_STATUS
+-#define CRTC3_CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0
+-#define CRTC3_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4
+-#define CRTC3_CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10
+-#define CRTC3_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14
+-#define CRTC3_CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x00000001L
+-#define CRTC3_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x00000010L
+-#define CRTC3_CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x00010000L
+-#define CRTC3_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x00100000L
+-//CRTC3_CRTC_MASTER_EN
+-#define CRTC3_CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0
+-#define CRTC3_CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x00000001L
+-//CRTC3_CRTC_ALLOW_STOP_OFF_V_CNT
+-#define CRTC3_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0
+-#define CRTC3_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10
+-#define CRTC3_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0x000000FFL
+-#define CRTC3_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x00010000L
+-//CRTC3_CRTC_V_UPDATE_INT_STATUS
+-#define CRTC3_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0
+-#define CRTC3_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8
+-#define CRTC3_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x00000001L
+-#define CRTC3_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x00000100L
+-//CRTC3_CRTC_OVERSCAN_COLOR
+-#define CRTC3_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0
+-#define CRTC3_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa
+-#define CRTC3_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14
+-#define CRTC3_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x000003FFL
+-#define CRTC3_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0x000FFC00L
+-#define CRTC3_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3FF00000L
+-//CRTC3_CRTC_OVERSCAN_COLOR_EXT
+-#define CRTC3_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0
+-#define CRTC3_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8
+-#define CRTC3_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10
+-#define CRTC3_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x00000003L
+-#define CRTC3_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x00000300L
+-#define CRTC3_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x00030000L
+-//CRTC3_CRTC_BLANK_DATA_COLOR
+-#define CRTC3_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0
+-#define CRTC3_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa
+-#define CRTC3_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14
+-#define CRTC3_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL
+-#define CRTC3_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L
+-#define CRTC3_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L
+-//CRTC3_CRTC_BLANK_DATA_COLOR_EXT
+-#define CRTC3_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0
+-#define CRTC3_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8
+-#define CRTC3_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10
+-#define CRTC3_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x00000003L
+-#define CRTC3_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00000300L
+-#define CRTC3_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x00030000L
+-//CRTC3_CRTC_BLACK_COLOR
+-#define CRTC3_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0
+-#define CRTC3_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa
+-#define CRTC3_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14
+-#define CRTC3_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x000003FFL
+-#define CRTC3_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0x000FFC00L
+-#define CRTC3_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3FF00000L
+-//CRTC3_CRTC_BLACK_COLOR_EXT
+-#define CRTC3_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0
+-#define CRTC3_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8
+-#define CRTC3_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10
+-#define CRTC3_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x00000003L
+-#define CRTC3_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x00000300L
+-#define CRTC3_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x00030000L
+-//CRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION
+-#define CRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0
+-#define CRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10
+-#define CRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00003FFFL
+-#define CRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x3FFF0000L
+-//CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL
+-#define CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4
+-#define CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8
+-#define CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc
+-#define CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10
+-#define CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14
+-#define CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18
+-#define CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L
+-#define CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L
+-#define CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L
+-#define CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L
+-#define CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L
+-#define CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L
+-//CRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION
+-#define CRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0
+-#define CRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00003FFFL
+-//CRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL
+-#define CRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8
+-#define CRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc
+-#define CRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10
+-#define CRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14
+-#define CRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18
+-#define CRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L
+-#define CRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L
+-#define CRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L
+-#define CRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L
+-#define CRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L
+-//CRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION
+-#define CRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0
+-#define CRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00003FFFL
+-//CRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL
+-#define CRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8
+-#define CRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc
+-#define CRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10
+-#define CRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14
+-#define CRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18
+-#define CRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L
+-#define CRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L
+-#define CRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L
+-#define CRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L
+-#define CRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L
+-//CRTC3_CRTC_CRC_CNTL
+-#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0
+-#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4
+-#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8
+-#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc
+-#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
+-#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14
+-#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18
+-#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC_EN_MASK 0x00000001L
+-#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x00000010L
+-#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x00000300L
+-#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x00003000L
+-#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
+-#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x00700000L
+-#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x07000000L
+-//CRTC3_CRTC_CRC0_WINDOWA_X_CONTROL
+-#define CRTC3_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0
+-#define CRTC3_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10
+-#define CRTC3_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x00003FFFL
+-#define CRTC3_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3FFF0000L
+-//CRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL
+-#define CRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0
+-#define CRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10
+-#define CRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x00003FFFL
+-#define CRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3FFF0000L
+-//CRTC3_CRTC_CRC0_WINDOWB_X_CONTROL
+-#define CRTC3_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0
+-#define CRTC3_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10
+-#define CRTC3_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x00003FFFL
+-#define CRTC3_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3FFF0000L
+-//CRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL
+-#define CRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0
+-#define CRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10
+-#define CRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x00003FFFL
+-#define CRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3FFF0000L
+-//CRTC3_CRTC_CRC0_DATA_RG
+-#define CRTC3_CRTC_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0
+-#define CRTC3_CRTC_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10
+-#define CRTC3_CRTC_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL
+-#define CRTC3_CRTC_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L
+-//CRTC3_CRTC_CRC0_DATA_B
+-#define CRTC3_CRTC_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0
+-#define CRTC3_CRTC_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL
+-//CRTC3_CRTC_CRC1_WINDOWA_X_CONTROL
+-#define CRTC3_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0
+-#define CRTC3_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10
+-#define CRTC3_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x00003FFFL
+-#define CRTC3_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3FFF0000L
+-//CRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL
+-#define CRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0
+-#define CRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10
+-#define CRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x00003FFFL
+-#define CRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3FFF0000L
+-//CRTC3_CRTC_CRC1_WINDOWB_X_CONTROL
+-#define CRTC3_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0
+-#define CRTC3_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10
+-#define CRTC3_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x00003FFFL
+-#define CRTC3_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3FFF0000L
+-//CRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL
+-#define CRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0
+-#define CRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10
+-#define CRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x00003FFFL
+-#define CRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3FFF0000L
+-//CRTC3_CRTC_CRC1_DATA_RG
+-#define CRTC3_CRTC_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0
+-#define CRTC3_CRTC_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10
+-#define CRTC3_CRTC_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL
+-#define CRTC3_CRTC_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L
+-//CRTC3_CRTC_CRC1_DATA_B
+-#define CRTC3_CRTC_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0
+-#define CRTC3_CRTC_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL
+-//CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE__SHIFT 0x0
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__SHIFT 0x3
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__SHIFT 0x4
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__SHIFT 0x5
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__SHIFT 0x8
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__SHIFT 0x9
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__SHIFT 0xc
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__SHIFT 0xd
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__SHIFT 0xe
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE__SHIFT 0x18
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE__SHIFT 0x1c
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE_MASK 0x00000003L
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_MASK 0x00000008L
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_MASK 0x00000010L
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_MASK 0x00000060L
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_MASK 0x00000100L
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_MASK 0x00000200L
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_MASK 0x00001000L
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_MASK 0x00002000L
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_MASK 0x00004000L
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE_MASK 0x07000000L
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE_MASK 0x70000000L
+-//CRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X__SHIFT 0x0
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y__SHIFT 0x10
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X_MASK 0x00003FFFL
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y_MASK 0x3FFF0000L
+-//CRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X__SHIFT 0x0
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y__SHIFT 0x10
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X_MASK 0x00003FFFL
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y_MASK 0x3FFF0000L
+-//CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__SHIFT 0x0
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS__SHIFT 0x4
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS__SHIFT 0x8
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__SHIFT 0x10
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__SHIFT 0x14
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__SHIFT 0x1d
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_MASK 0x00000001L
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS_MASK 0x00000010L
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS_MASK 0x00000100L
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_MASK 0x00010000L
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_MASK 0x00100000L
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_MASK 0xE0000000L
+-//CRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE__SHIFT 0x0
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS__SHIFT 0x4
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS__SHIFT 0x8
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR__SHIFT 0x10
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE__SHIFT 0x14
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE_MASK 0x00000001L
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS_MASK 0x00000010L
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS_MASK 0x00000100L
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR_MASK 0x00010000L
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE_MASK 0x00100000L
+-//CRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__SHIFT 0x0
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS__SHIFT 0x4
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS__SHIFT 0x8
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__SHIFT 0x10
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__SHIFT 0x14
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_MASK 0x00000001L
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS_MASK 0x00000010L
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS_MASK 0x00000100L
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_MASK 0x00010000L
+-#define CRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_MASK 0x00100000L
+-//CRTC3_CRTC_STATIC_SCREEN_CONTROL
+-#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0
+-#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10
+-#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18
+-#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19
+-#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a
+-#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b
+-#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c
+-#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e
+-#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f
+-#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL
+-#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L
+-#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x01000000L
+-#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x02000000L
+-#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x04000000L
+-#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x08000000L
+-#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000L
+-#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L
+-#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L
+-//CRTC3_CRTC_3D_STRUCTURE_CONTROL
+-#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0
+-#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4
+-#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8
+-#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc
+-#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10
+-#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11
+-#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12
+-#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x00000001L
+-#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x00000010L
+-#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L
+-#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L
+-#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L
+-#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L
+-#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L
+-//CRTC3_CRTC_GSL_VSYNC_GAP
+-#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0
+-#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8
+-#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10
+-#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11
+-#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13
+-#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14
+-#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17
+-#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18
+-#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL
+-#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L
+-#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L
+-#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x00060000L
+-#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L
+-#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L
+-#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L
+-#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xFF000000L
+-//CRTC3_CRTC_GSL_WINDOW
+-#define CRTC3_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0
+-#define CRTC3_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10
+-#define CRTC3_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x00003FFFL
+-#define CRTC3_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x3FFF0000L
+-//CRTC3_CRTC_GSL_CONTROL
+-#define CRTC3_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0
+-#define CRTC3_CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10
+-#define CRTC3_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c
+-#define CRTC3_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x00003FFFL
+-#define CRTC3_CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x001F0000L
+-#define CRTC3_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L
+-//CRTC3_CRTC_RANGE_TIMING_INT_STATUS
+-#define CRTC3_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0
+-#define CRTC3_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4
+-#define CRTC3_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8
+-#define CRTC3_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc
+-#define CRTC3_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10
+-#define CRTC3_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L
+-#define CRTC3_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L
+-#define CRTC3_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L
+-#define CRTC3_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L
+-#define CRTC3_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L
+-//CRTC3_CRTC_DRR_CONTROL
+-#define CRTC3_CRTC_DRR_CONTROL__CRTC_XDMA_PREFETCH_DELAY__SHIFT 0x0
+-#define CRTC3_CRTC_DRR_CONTROL__CRTC_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0xe
+-#define CRTC3_CRTC_DRR_CONTROL__CRTC_SET_V_TOTAL_MIN_AUTO_DIS__SHIFT 0x1c
+-#define CRTC3_CRTC_DRR_CONTROL__CRTC_DRR_MODE_DBUF_UPDATE_MODE__SHIFT 0x1d
+-#define CRTC3_CRTC_DRR_CONTROL__CRTC_XDMA_PREFETCH_DELAY_MASK 0x00003FFFL
+-#define CRTC3_CRTC_DRR_CONTROL__CRTC_V_TOTAL_LAST_USED_BY_DRR_MASK 0x0FFFC000L
+-#define CRTC3_CRTC_DRR_CONTROL__CRTC_SET_V_TOTAL_MIN_AUTO_DIS_MASK 0x10000000L
+-#define CRTC3_CRTC_DRR_CONTROL__CRTC_DRR_MODE_DBUF_UPDATE_MODE_MASK 0x60000000L
+-
+-
+-// addressBlock: dce_dc_fmt3_dispdec
+-//FMT3_FMT_CLAMP_COMPONENT_R
+-#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0
+-#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10
+-#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL
+-#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L
+-//FMT3_FMT_CLAMP_COMPONENT_G
+-#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0
+-#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10
+-#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL
+-#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L
+-//FMT3_FMT_CLAMP_COMPONENT_B
+-#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0
+-#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10
+-#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL
+-#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L
+-//FMT3_FMT_DYNAMIC_EXP_CNTL
+-#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0
+-#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4
+-#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L
+-#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L
+-//FMT3_FMT_CONTROL
+-#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0
+-#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT 0x4
+-#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8
+-#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc
+-#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10
+-#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12
+-#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14
+-#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15
+-#define FMT3_FMT_CONTROL__FMT_SRC_SELECT__SHIFT 0x18
+-#define FMT3_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED__SHIFT 0x1e
+-#define FMT3_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_CLEAR__SHIFT 0x1f
+-#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L
+-#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK 0x00000010L
+-#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L
+-#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L
+-#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L
+-#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L
+-#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L
+-#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L
+-#define FMT3_FMT_CONTROL__FMT_SRC_SELECT_MASK 0x07000000L
+-#define FMT3_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_MASK 0x40000000L
+-#define FMT3_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_CLEAR_MASK 0x80000000L
+-//FMT3_FMT_BIT_DEPTH_CONTROL
+-#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0
+-#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1
+-#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4
+-#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8
+-#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9
+-#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb
+-#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd
+-#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe
+-#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf
+-#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10
+-#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11
+-#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15
+-#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18
+-#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19
+-#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a
+-#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c
+-#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e
+-#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L
+-#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L
+-#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L
+-#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L
+-#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L
+-#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L
+-#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L
+-#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L
+-#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L
+-#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L
+-#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L
+-#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L
+-#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L
+-#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L
+-#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L
+-#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L
+-#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L
+-//FMT3_FMT_DITHER_RAND_R_SEED
+-#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0
+-#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10
+-#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL
+-#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L
+-//FMT3_FMT_DITHER_RAND_G_SEED
+-#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0
+-#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10
+-#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL
+-#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L
+-//FMT3_FMT_DITHER_RAND_B_SEED
+-#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0
+-#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10
+-#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL
+-#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L
+-//FMT3_FMT_CLAMP_CNTL
+-#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0
+-#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10
+-#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L
+-#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L
+-//FMT3_FMT_CRC_CNTL
+-#define FMT3_FMT_CRC_CNTL__FMT_CRC_EN__SHIFT 0x0
+-#define FMT3_FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN__SHIFT 0x1
+-#define FMT3_FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT 0x4
+-#define FMT3_FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING__SHIFT 0x5
+-#define FMT3_FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN__SHIFT 0x6
+-#define FMT3_FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB__SHIFT 0x8
+-#define FMT3_FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE__SHIFT 0x9
+-#define FMT3_FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT 0xc
+-#define FMT3_FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
+-#define FMT3_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT 0x14
+-#define FMT3_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT 0x18
+-#define FMT3_FMT_CRC_CNTL__FMT_CRC_EN_MASK 0x00000001L
+-#define FMT3_FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN_MASK 0x00000002L
+-#define FMT3_FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK 0x00000010L
+-#define FMT3_FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING_MASK 0x00000020L
+-#define FMT3_FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN_MASK 0x00000040L
+-#define FMT3_FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB_MASK 0x00000100L
+-#define FMT3_FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE_MASK 0x00000200L
+-#define FMT3_FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK 0x00003000L
+-#define FMT3_FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
+-#define FMT3_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK 0x00100000L
+-#define FMT3_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK 0x01000000L
+-//FMT3_FMT_CRC_SIG_RED_GREEN_MASK
+-#define FMT3_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT 0x0
+-#define FMT3_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT 0x10
+-#define FMT3_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK 0x0000FFFFL
+-#define FMT3_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L
+-//FMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK
+-#define FMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT 0x0
+-#define FMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT 0x10
+-#define FMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL
+-#define FMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L
+-//FMT3_FMT_CRC_SIG_RED_GREEN
+-#define FMT3_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT 0x0
+-#define FMT3_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT 0x10
+-#define FMT3_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK 0x0000FFFFL
+-#define FMT3_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK 0xFFFF0000L
+-//FMT3_FMT_CRC_SIG_BLUE_CONTROL
+-#define FMT3_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT 0x0
+-#define FMT3_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT 0x10
+-#define FMT3_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK 0x0000FFFFL
+-#define FMT3_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK 0xFFFF0000L
+-//FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+-#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0
+-#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL
+-//FMT3_FMT_420_HBLANK_EARLY_START
+-#define FMT3_FMT_420_HBLANK_EARLY_START__FMT_420_HBLANK_EARLY_START__SHIFT 0x0
+-#define FMT3_FMT_420_HBLANK_EARLY_START__FMT_420_HBLANK_EARLY_START_MASK 0x00000FFFL
+-
+-
+-// addressBlock: dce_dc_dcp4_dispdec
+-//DCP4_GRPH_ENABLE
+-#define DCP4_GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0
+-#define DCP4_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL__SHIFT 0x1
+-#define DCP4_GRPH_ENABLE__GRPH_ENABLE_MASK 0x00000001L
+-#define DCP4_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL_MASK 0x00000002L
+-//DCP4_GRPH_CONTROL
+-#define DCP4_GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0
+-#define DCP4_GRPH_CONTROL__GRPH_SE_ENABLE__SHIFT 0x2
+-#define DCP4_GRPH_CONTROL__GRPH_Z__SHIFT 0x4
+-#define DCP4_GRPH_CONTROL__GRPH_DIM_TYPE__SHIFT 0x6
+-#define DCP4_GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8
+-#define DCP4_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0xc
+-#define DCP4_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10
+-#define DCP4_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11
+-#define DCP4_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES__SHIFT 0x12
+-#define DCP4_GRPH_CONTROL__GRPH_SW_MODE__SHIFT 0x14
+-#define DCP4_GRPH_CONTROL__GRPH_NUM_PIPES__SHIFT 0x1c
+-#define DCP4_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f
+-#define DCP4_GRPH_CONTROL__GRPH_DEPTH_MASK 0x00000003L
+-#define DCP4_GRPH_CONTROL__GRPH_SE_ENABLE_MASK 0x00000004L
+-#define DCP4_GRPH_CONTROL__GRPH_Z_MASK 0x00000030L
+-#define DCP4_GRPH_CONTROL__GRPH_DIM_TYPE_MASK 0x000000C0L
+-#define DCP4_GRPH_CONTROL__GRPH_FORMAT_MASK 0x00000700L
+-#define DCP4_GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0x00007000L
+-#define DCP4_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x00010000L
+-#define DCP4_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x00020000L
+-#define DCP4_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES_MASK 0x000C0000L
+-#define DCP4_GRPH_CONTROL__GRPH_SW_MODE_MASK 0x01F00000L
+-#define DCP4_GRPH_CONTROL__GRPH_NUM_PIPES_MASK 0x70000000L
+-#define DCP4_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000L
+-//DCP4_GRPH_LUT_10BIT_BYPASS
+-#define DCP4_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT 0x8
+-#define DCP4_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x10
+-#define DCP4_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK 0x00000100L
+-#define DCP4_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x00010000L
+-//DCP4_GRPH_SWAP_CNTL
+-#define DCP4_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0
+-#define DCP4_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4
+-#define DCP4_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6
+-#define DCP4_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8
+-#define DCP4_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT 0xa
+-#define DCP4_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x00000003L
+-#define DCP4_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x00000030L
+-#define DCP4_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0x000000C0L
+-#define DCP4_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x00000300L
+-#define DCP4_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK 0x00000C00L
+-//DCP4_GRPH_PRIMARY_SURFACE_ADDRESS
+-#define DCP4_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT 0x0
+-#define DCP4_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT 0x8
+-#define DCP4_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK 0x00000001L
+-#define DCP4_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+-//DCP4_GRPH_SECONDARY_SURFACE_ADDRESS
+-#define DCP4_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT 0x0
+-#define DCP4_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8
+-#define DCP4_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK 0x00000001L
+-#define DCP4_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+-//DCP4_GRPH_PITCH
+-#define DCP4_GRPH_PITCH__GRPH_PITCH__SHIFT 0x0
+-#define DCP4_GRPH_PITCH__GRPH_PITCH_MASK 0x00007FFFL
+-//DCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+-#define DCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+-#define DCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+-//DCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+-#define DCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+-#define DCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+-//DCP4_GRPH_SURFACE_OFFSET_X
+-#define DCP4_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT 0x0
+-#define DCP4_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK 0x00003FFFL
+-//DCP4_GRPH_SURFACE_OFFSET_Y
+-#define DCP4_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT 0x0
+-#define DCP4_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK 0x00003FFFL
+-//DCP4_GRPH_X_START
+-#define DCP4_GRPH_X_START__GRPH_X_START__SHIFT 0x0
+-#define DCP4_GRPH_X_START__GRPH_X_START_MASK 0x00003FFFL
+-//DCP4_GRPH_Y_START
+-#define DCP4_GRPH_Y_START__GRPH_Y_START__SHIFT 0x0
+-#define DCP4_GRPH_Y_START__GRPH_Y_START_MASK 0x00003FFFL
+-//DCP4_GRPH_X_END
+-#define DCP4_GRPH_X_END__GRPH_X_END__SHIFT 0x0
+-#define DCP4_GRPH_X_END__GRPH_X_END_MASK 0x00007FFFL
+-//DCP4_GRPH_Y_END
+-#define DCP4_GRPH_Y_END__GRPH_Y_END__SHIFT 0x0
+-#define DCP4_GRPH_Y_END__GRPH_Y_END_MASK 0x00007FFFL
+-//DCP4_INPUT_GAMMA_CONTROL
+-#define DCP4_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x0
+-#define DCP4_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK 0x00000001L
+-//DCP4_GRPH_UPDATE
+-#define DCP4_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0
+-#define DCP4_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1
+-#define DCP4_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2
+-#define DCP4_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3
+-#define DCP4_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR__SHIFT 0x8
+-#define DCP4_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE__SHIFT 0x9
+-#define DCP4_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE__SHIFT 0xa
+-#define DCP4_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10
+-#define DCP4_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14
+-#define DCP4_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+-#define DCP4_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c
+-#define DCP4_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x00000001L
+-#define DCP4_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x00000002L
+-#define DCP4_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x00000004L
+-#define DCP4_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x00000008L
+-#define DCP4_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR_MASK 0x00000100L
+-#define DCP4_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE_MASK 0x00000200L
+-#define DCP4_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE_MASK 0x00000400L
+-#define DCP4_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x00010000L
+-#define DCP4_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x00100000L
+-#define DCP4_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
+-#define DCP4_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000L
+-//DCP4_GRPH_FLIP_CONTROL
+-#define DCP4_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT 0x0
+-#define DCP4_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN__SHIFT 0x1
+-#define DCP4_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN__SHIFT 0x4
+-#define DCP4_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT 0x5
+-#define DCP4_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK 0x00000001L
+-#define DCP4_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN_MASK 0x00000002L
+-#define DCP4_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN_MASK 0x00000010L
+-#define DCP4_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK 0x00000020L
+-//DCP4_GRPH_SURFACE_ADDRESS_INUSE
+-#define DCP4_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT 0x8
+-#define DCP4_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK 0xFFFFFF00L
+-//DCP4_GRPH_DFQ_CONTROL
+-#define DCP4_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x0
+-#define DCP4_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x4
+-#define DCP4_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8
+-#define DCP4_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x00000001L
+-#define DCP4_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x00000070L
+-#define DCP4_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x00000700L
+-//DCP4_GRPH_DFQ_STATUS
+-#define DCP4_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x0
+-#define DCP4_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4
+-#define DCP4_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x8
+-#define DCP4_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x9
+-#define DCP4_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0x0000000FL
+-#define DCP4_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0x000000F0L
+-#define DCP4_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x00000100L
+-#define DCP4_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x00000200L
+-//DCP4_GRPH_INTERRUPT_STATUS
+-#define DCP4_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0
+-#define DCP4_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8
+-#define DCP4_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x00000001L
+-#define DCP4_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x00000100L
+-//DCP4_GRPH_INTERRUPT_CONTROL
+-#define DCP4_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0
+-#define DCP4_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8
+-#define DCP4_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x00000001L
+-#define DCP4_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x00000100L
+-//DCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE
+-#define DCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0
+-#define DCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK 0x000000FFL
+-//DCP4_GRPH_COMPRESS_SURFACE_ADDRESS
+-#define DCP4_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT 0x8
+-#define DCP4_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+-//DCP4_GRPH_COMPRESS_PITCH
+-#define DCP4_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT 0x6
+-#define DCP4_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK 0x0001FFC0L
+-//DCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH
+-#define DCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+-#define DCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+-//DCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT
+-#define DCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__SHIFT 0x0
+-#define DCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_MASK 0x000000FFL
+-//DCP4_PRESCALE_GRPH_CONTROL
+-#define DCP4_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT 0x0
+-#define DCP4_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT 0x1
+-#define DCP4_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x2
+-#define DCP4_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT 0x3
+-#define DCP4_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT 0x4
+-#define DCP4_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK 0x00000001L
+-#define DCP4_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x00000002L
+-#define DCP4_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK 0x00000004L
+-#define DCP4_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK 0x00000008L
+-#define DCP4_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK 0x00000010L
+-//DCP4_PRESCALE_VALUES_GRPH_R
+-#define DCP4_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT 0x0
+-#define DCP4_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT 0x10
+-#define DCP4_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK 0x0000FFFFL
+-#define DCP4_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK 0xFFFF0000L
+-//DCP4_PRESCALE_VALUES_GRPH_G
+-#define DCP4_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT 0x0
+-#define DCP4_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT 0x10
+-#define DCP4_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK 0x0000FFFFL
+-#define DCP4_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK 0xFFFF0000L
+-//DCP4_PRESCALE_VALUES_GRPH_B
+-#define DCP4_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT 0x0
+-#define DCP4_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT 0x10
+-#define DCP4_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK 0x0000FFFFL
+-#define DCP4_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK 0xFFFF0000L
+-//DCP4_INPUT_CSC_CONTROL
+-#define DCP4_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT 0x0
+-#define DCP4_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK 0x00000003L
+-//DCP4_INPUT_CSC_C11_C12
+-#define DCP4_INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT 0x0
+-#define DCP4_INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT 0x10
+-#define DCP4_INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK 0x0000FFFFL
+-#define DCP4_INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK 0xFFFF0000L
+-//DCP4_INPUT_CSC_C13_C14
+-#define DCP4_INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT 0x0
+-#define DCP4_INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT 0x10
+-#define DCP4_INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK 0x0000FFFFL
+-#define DCP4_INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK 0xFFFF0000L
+-//DCP4_INPUT_CSC_C21_C22
+-#define DCP4_INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT 0x0
+-#define DCP4_INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT 0x10
+-#define DCP4_INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK 0x0000FFFFL
+-#define DCP4_INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK 0xFFFF0000L
+-//DCP4_INPUT_CSC_C23_C24
+-#define DCP4_INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT 0x0
+-#define DCP4_INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT 0x10
+-#define DCP4_INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK 0x0000FFFFL
+-#define DCP4_INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK 0xFFFF0000L
+-//DCP4_INPUT_CSC_C31_C32
+-#define DCP4_INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT 0x0
+-#define DCP4_INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT 0x10
+-#define DCP4_INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK 0x0000FFFFL
+-#define DCP4_INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK 0xFFFF0000L
+-//DCP4_INPUT_CSC_C33_C34
+-#define DCP4_INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT 0x0
+-#define DCP4_INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT 0x10
+-#define DCP4_INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK 0x0000FFFFL
+-#define DCP4_INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK 0xFFFF0000L
+-//DCP4_OUTPUT_CSC_CONTROL
+-#define DCP4_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT 0x0
+-#define DCP4_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK 0x00000007L
+-//DCP4_OUTPUT_CSC_C11_C12
+-#define DCP4_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT 0x0
+-#define DCP4_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT 0x10
+-#define DCP4_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK 0x0000FFFFL
+-#define DCP4_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK 0xFFFF0000L
+-//DCP4_OUTPUT_CSC_C13_C14
+-#define DCP4_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT 0x0
+-#define DCP4_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT 0x10
+-#define DCP4_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK 0x0000FFFFL
+-#define DCP4_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK 0xFFFF0000L
+-//DCP4_OUTPUT_CSC_C21_C22
+-#define DCP4_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT 0x0
+-#define DCP4_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT 0x10
+-#define DCP4_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK 0x0000FFFFL
+-#define DCP4_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK 0xFFFF0000L
+-//DCP4_OUTPUT_CSC_C23_C24
+-#define DCP4_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT 0x0
+-#define DCP4_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT 0x10
+-#define DCP4_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK 0x0000FFFFL
+-#define DCP4_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK 0xFFFF0000L
+-//DCP4_OUTPUT_CSC_C31_C32
+-#define DCP4_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT 0x0
+-#define DCP4_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT 0x10
+-#define DCP4_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK 0x0000FFFFL
+-#define DCP4_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK 0xFFFF0000L
+-//DCP4_OUTPUT_CSC_C33_C34
+-#define DCP4_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT 0x0
+-#define DCP4_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT 0x10
+-#define DCP4_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK 0x0000FFFFL
+-#define DCP4_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK 0xFFFF0000L
+-//DCP4_COMM_MATRIXA_TRANS_C11_C12
+-#define DCP4_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT 0x0
+-#define DCP4_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT 0x10
+-#define DCP4_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK 0x0000FFFFL
+-#define DCP4_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK 0xFFFF0000L
+-//DCP4_COMM_MATRIXA_TRANS_C13_C14
+-#define DCP4_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT 0x0
+-#define DCP4_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT 0x10
+-#define DCP4_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK 0x0000FFFFL
+-#define DCP4_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK 0xFFFF0000L
+-//DCP4_COMM_MATRIXA_TRANS_C21_C22
+-#define DCP4_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT 0x0
+-#define DCP4_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT 0x10
+-#define DCP4_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK 0x0000FFFFL
+-#define DCP4_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK 0xFFFF0000L
+-//DCP4_COMM_MATRIXA_TRANS_C23_C24
+-#define DCP4_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT 0x0
+-#define DCP4_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT 0x10
+-#define DCP4_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK 0x0000FFFFL
+-#define DCP4_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK 0xFFFF0000L
+-//DCP4_COMM_MATRIXA_TRANS_C31_C32
+-#define DCP4_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT 0x0
+-#define DCP4_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT 0x10
+-#define DCP4_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK 0x0000FFFFL
+-#define DCP4_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK 0xFFFF0000L
+-//DCP4_COMM_MATRIXA_TRANS_C33_C34
+-#define DCP4_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT 0x0
+-#define DCP4_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT 0x10
+-#define DCP4_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK 0x0000FFFFL
+-#define DCP4_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK 0xFFFF0000L
+-//DCP4_COMM_MATRIXB_TRANS_C11_C12
+-#define DCP4_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT 0x0
+-#define DCP4_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT 0x10
+-#define DCP4_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK 0x0000FFFFL
+-#define DCP4_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK 0xFFFF0000L
+-//DCP4_COMM_MATRIXB_TRANS_C13_C14
+-#define DCP4_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT 0x0
+-#define DCP4_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT 0x10
+-#define DCP4_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK 0x0000FFFFL
+-#define DCP4_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK 0xFFFF0000L
+-//DCP4_COMM_MATRIXB_TRANS_C21_C22
+-#define DCP4_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT 0x0
+-#define DCP4_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT 0x10
+-#define DCP4_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK 0x0000FFFFL
+-#define DCP4_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK 0xFFFF0000L
+-//DCP4_COMM_MATRIXB_TRANS_C23_C24
+-#define DCP4_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT 0x0
+-#define DCP4_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT 0x10
+-#define DCP4_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK 0x0000FFFFL
+-#define DCP4_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK 0xFFFF0000L
+-//DCP4_COMM_MATRIXB_TRANS_C31_C32
+-#define DCP4_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT 0x0
+-#define DCP4_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT 0x10
+-#define DCP4_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK 0x0000FFFFL
+-#define DCP4_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK 0xFFFF0000L
+-//DCP4_COMM_MATRIXB_TRANS_C33_C34
+-#define DCP4_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT 0x0
+-#define DCP4_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT 0x10
+-#define DCP4_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK 0x0000FFFFL
+-#define DCP4_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK 0xFFFF0000L
+-//DCP4_DENORM_CONTROL
+-#define DCP4_DENORM_CONTROL__DENORM_MODE__SHIFT 0x0
+-#define DCP4_DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT 0x4
+-#define DCP4_DENORM_CONTROL__DENORM_MODE_MASK 0x00000007L
+-#define DCP4_DENORM_CONTROL__DENORM_14BIT_OUT_MASK 0x00000010L
+-//DCP4_OUT_ROUND_CONTROL
+-#define DCP4_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT 0x0
+-#define DCP4_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK 0x0000000FL
+-//DCP4_OUT_CLAMP_CONTROL_R_CR
+-#define DCP4_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT 0x0
+-#define DCP4_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT 0x10
+-#define DCP4_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK 0x00003FFFL
+-#define DCP4_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK 0x3FFF0000L
+-//DCP4_OUT_CLAMP_CONTROL_G_Y
+-#define DCP4_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT 0x0
+-#define DCP4_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT 0x10
+-#define DCP4_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK 0x00003FFFL
+-#define DCP4_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK 0x3FFF0000L
+-//DCP4_OUT_CLAMP_CONTROL_B_CB
+-#define DCP4_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT 0x0
+-#define DCP4_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT 0x10
+-#define DCP4_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK 0x00003FFFL
+-#define DCP4_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK 0x3FFF0000L
+-//DCP4_KEY_CONTROL
+-#define DCP4_KEY_CONTROL__KEY_MODE__SHIFT 0x1
+-#define DCP4_KEY_CONTROL__KEY_MODE_MASK 0x00000006L
+-//DCP4_KEY_RANGE_ALPHA
+-#define DCP4_KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT 0x0
+-#define DCP4_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT 0x10
+-#define DCP4_KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK 0x0000FFFFL
+-#define DCP4_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK 0xFFFF0000L
+-//DCP4_KEY_RANGE_RED
+-#define DCP4_KEY_RANGE_RED__KEY_RED_LOW__SHIFT 0x0
+-#define DCP4_KEY_RANGE_RED__KEY_RED_HIGH__SHIFT 0x10
+-#define DCP4_KEY_RANGE_RED__KEY_RED_LOW_MASK 0x0000FFFFL
+-#define DCP4_KEY_RANGE_RED__KEY_RED_HIGH_MASK 0xFFFF0000L
+-//DCP4_KEY_RANGE_GREEN
+-#define DCP4_KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT 0x0
+-#define DCP4_KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT 0x10
+-#define DCP4_KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK 0x0000FFFFL
+-#define DCP4_KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK 0xFFFF0000L
+-//DCP4_KEY_RANGE_BLUE
+-#define DCP4_KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT 0x0
+-#define DCP4_KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT 0x10
+-#define DCP4_KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK 0x0000FFFFL
+-#define DCP4_KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK 0xFFFF0000L
+-//DCP4_DEGAMMA_CONTROL
+-#define DCP4_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x0
+-#define DCP4_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT 0x8
+-#define DCP4_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0xc
+-#define DCP4_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x00000003L
+-#define DCP4_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK 0x00000300L
+-#define DCP4_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK 0x00003000L
+-//DCP4_GAMUT_REMAP_CONTROL
+-#define DCP4_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT 0x0
+-#define DCP4_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK 0x00000003L
+-//DCP4_GAMUT_REMAP_C11_C12
+-#define DCP4_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT 0x0
+-#define DCP4_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT 0x10
+-#define DCP4_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK 0x0000FFFFL
+-#define DCP4_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK 0xFFFF0000L
+-//DCP4_GAMUT_REMAP_C13_C14
+-#define DCP4_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT 0x0
+-#define DCP4_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT 0x10
+-#define DCP4_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK 0x0000FFFFL
+-#define DCP4_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK 0xFFFF0000L
+-//DCP4_GAMUT_REMAP_C21_C22
+-#define DCP4_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT 0x0
+-#define DCP4_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT 0x10
+-#define DCP4_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK 0x0000FFFFL
+-#define DCP4_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK 0xFFFF0000L
+-//DCP4_GAMUT_REMAP_C23_C24
+-#define DCP4_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT 0x0
+-#define DCP4_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT 0x10
+-#define DCP4_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK 0x0000FFFFL
+-#define DCP4_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK 0xFFFF0000L
+-//DCP4_GAMUT_REMAP_C31_C32
+-#define DCP4_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT 0x0
+-#define DCP4_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT 0x10
+-#define DCP4_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK 0x0000FFFFL
+-#define DCP4_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK 0xFFFF0000L
+-//DCP4_GAMUT_REMAP_C33_C34
+-#define DCP4_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT 0x0
+-#define DCP4_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT 0x10
+-#define DCP4_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK 0x0000FFFFL
+-#define DCP4_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK 0xFFFF0000L
+-//DCP4_DCP_SPATIAL_DITHER_CNTL
+-#define DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT 0x0
+-#define DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT 0x4
+-#define DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT 0x6
+-#define DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT 0x8
+-#define DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT 0x9
+-#define DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT 0xa
+-#define DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK 0x00000001L
+-#define DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK 0x00000030L
+-#define DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK 0x000000C0L
+-#define DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK 0x00000100L
+-#define DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK 0x00000200L
+-#define DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK 0x00000400L
+-//DCP4_DCP_RANDOM_SEEDS
+-#define DCP4_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT 0x0
+-#define DCP4_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT 0x8
+-#define DCP4_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT 0x10
+-#define DCP4_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK 0x000000FFL
+-#define DCP4_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK 0x0000FF00L
+-#define DCP4_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK 0x00FF0000L
+-//DCP4_DCP_FP_CONVERTED_FIELD
+-#define DCP4_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT 0x0
+-#define DCP4_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14
+-#define DCP4_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK 0x0003FFFFL
+-#define DCP4_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK 0x07F00000L
+-//DCP4_CUR_CONTROL
+-#define DCP4_CUR_CONTROL__CURSOR_EN__SHIFT 0x0
+-#define DCP4_CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT 0x4
+-#define DCP4_CUR_CONTROL__CURSOR_MODE__SHIFT 0x8
+-#define DCP4_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM__SHIFT 0xb
+-#define DCP4_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION__SHIFT 0xc
+-#define DCP4_CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x10
+-#define DCP4_CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT 0x14
+-#define DCP4_CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT 0x18
+-#define DCP4_CUR_CONTROL__CURSOR_EN_MASK 0x00000001L
+-#define DCP4_CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK 0x00000010L
+-#define DCP4_CUR_CONTROL__CURSOR_MODE_MASK 0x00000300L
+-#define DCP4_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM_MASK 0x00000800L
+-#define DCP4_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION_MASK 0x0000F000L
+-#define DCP4_CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00010000L
+-#define DCP4_CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK 0x00100000L
+-#define DCP4_CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK 0x07000000L
+-//DCP4_CUR_SURFACE_ADDRESS
+-#define DCP4_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0
+-#define DCP4_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+-//DCP4_CUR_SIZE
+-#define DCP4_CUR_SIZE__CURSOR_HEIGHT__SHIFT 0x0
+-#define DCP4_CUR_SIZE__CURSOR_WIDTH__SHIFT 0x10
+-#define DCP4_CUR_SIZE__CURSOR_HEIGHT_MASK 0x0000007FL
+-#define DCP4_CUR_SIZE__CURSOR_WIDTH_MASK 0x007F0000L
+-//DCP4_CUR_SURFACE_ADDRESS_HIGH
+-#define DCP4_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+-#define DCP4_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+-//DCP4_CUR_POSITION
+-#define DCP4_CUR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0
+-#define DCP4_CUR_POSITION__CURSOR_X_POSITION__SHIFT 0x10
+-#define DCP4_CUR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL
+-#define DCP4_CUR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L
+-//DCP4_CUR_HOT_SPOT
+-#define DCP4_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0
+-#define DCP4_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10
+-#define DCP4_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x0000007FL
+-#define DCP4_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x007F0000L
+-//DCP4_CUR_COLOR1
+-#define DCP4_CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT 0x0
+-#define DCP4_CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT 0x8
+-#define DCP4_CUR_COLOR1__CUR_COLOR1_RED__SHIFT 0x10
+-#define DCP4_CUR_COLOR1__CUR_COLOR1_BLUE_MASK 0x000000FFL
+-#define DCP4_CUR_COLOR1__CUR_COLOR1_GREEN_MASK 0x0000FF00L
+-#define DCP4_CUR_COLOR1__CUR_COLOR1_RED_MASK 0x00FF0000L
+-//DCP4_CUR_COLOR2
+-#define DCP4_CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT 0x0
+-#define DCP4_CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT 0x8
+-#define DCP4_CUR_COLOR2__CUR_COLOR2_RED__SHIFT 0x10
+-#define DCP4_CUR_COLOR2__CUR_COLOR2_BLUE_MASK 0x000000FFL
+-#define DCP4_CUR_COLOR2__CUR_COLOR2_GREEN_MASK 0x0000FF00L
+-#define DCP4_CUR_COLOR2__CUR_COLOR2_RED_MASK 0x00FF0000L
+-//DCP4_CUR_UPDATE
+-#define DCP4_CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT 0x0
+-#define DCP4_CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT 0x1
+-#define DCP4_CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT 0x10
+-#define DCP4_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+-#define DCP4_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE__SHIFT 0x19
+-#define DCP4_CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK 0x00000001L
+-#define DCP4_CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x00000002L
+-#define DCP4_CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK 0x00010000L
+-#define DCP4_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
+-#define DCP4_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE_MASK 0x06000000L
+-//DCP4_CUR_REQUEST_FILTER_CNTL
+-#define DCP4_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT 0x0
+-#define DCP4_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK 0x00000001L
+-//DCP4_CUR_STEREO_CONTROL
+-#define DCP4_CUR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0
+-#define DCP4_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4
+-#define DCP4_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x10
+-#define DCP4_CUR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L
+-#define DCP4_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x00003FF0L
+-#define DCP4_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0x03FF0000L
+-//DCP4_DC_LUT_RW_MODE
+-#define DCP4_DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT 0x0
+-#define DCP4_DC_LUT_RW_MODE__DC_LUT_ERROR__SHIFT 0x10
+-#define DCP4_DC_LUT_RW_MODE__DC_LUT_ERROR_RST__SHIFT 0x11
+-#define DCP4_DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK 0x00000001L
+-#define DCP4_DC_LUT_RW_MODE__DC_LUT_ERROR_MASK 0x00010000L
+-#define DCP4_DC_LUT_RW_MODE__DC_LUT_ERROR_RST_MASK 0x00020000L
+-//DCP4_DC_LUT_RW_INDEX
+-#define DCP4_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT 0x0
+-#define DCP4_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK 0x000000FFL
+-//DCP4_DC_LUT_SEQ_COLOR
+-#define DCP4_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT 0x0
+-#define DCP4_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK 0x0000FFFFL
+-//DCP4_DC_LUT_PWL_DATA
+-#define DCP4_DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT 0x0
+-#define DCP4_DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT 0x10
+-#define DCP4_DC_LUT_PWL_DATA__DC_LUT_BASE_MASK 0x0000FFFFL
+-#define DCP4_DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK 0xFFFF0000L
+-//DCP4_DC_LUT_30_COLOR
+-#define DCP4_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT 0x0
+-#define DCP4_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT 0xa
+-#define DCP4_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT 0x14
+-#define DCP4_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK 0x000003FFL
+-#define DCP4_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK 0x000FFC00L
+-#define DCP4_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK 0x3FF00000L
+-//DCP4_DC_LUT_VGA_ACCESS_ENABLE
+-#define DCP4_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT 0x0
+-#define DCP4_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK 0x00000001L
+-//DCP4_DC_LUT_WRITE_EN_MASK
+-#define DCP4_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT 0x0
+-#define DCP4_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK 0x00000007L
+-//DCP4_DC_LUT_AUTOFILL
+-#define DCP4_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT 0x0
+-#define DCP4_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT 0x1
+-#define DCP4_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK 0x00000001L
+-#define DCP4_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x00000002L
+-//DCP4_DC_LUT_CONTROL
+-#define DCP4_DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT 0x0
+-#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT 0x4
+-#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT 0x5
+-#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT 0x6
+-#define DCP4_DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT 0x8
+-#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT 0xc
+-#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT 0xd
+-#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT 0xe
+-#define DCP4_DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT 0x10
+-#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT 0x14
+-#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT 0x15
+-#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT 0x16
+-#define DCP4_DC_LUT_CONTROL__DC_LUT_INC_B_MASK 0x0000000FL
+-#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK 0x00000010L
+-#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK 0x00000020L
+-#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK 0x000000C0L
+-#define DCP4_DC_LUT_CONTROL__DC_LUT_INC_G_MASK 0x00000F00L
+-#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK 0x00001000L
+-#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK 0x00002000L
+-#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK 0x0000C000L
+-#define DCP4_DC_LUT_CONTROL__DC_LUT_INC_R_MASK 0x000F0000L
+-#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK 0x00100000L
+-#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK 0x00200000L
+-#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK 0x00C00000L
+-//DCP4_DC_LUT_BLACK_OFFSET_BLUE
+-#define DCP4_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0
+-#define DCP4_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK 0x0000FFFFL
+-//DCP4_DC_LUT_BLACK_OFFSET_GREEN
+-#define DCP4_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0
+-#define DCP4_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK 0x0000FFFFL
+-//DCP4_DC_LUT_BLACK_OFFSET_RED
+-#define DCP4_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT 0x0
+-#define DCP4_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK 0x0000FFFFL
+-//DCP4_DC_LUT_WHITE_OFFSET_BLUE
+-#define DCP4_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT 0x0
+-#define DCP4_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK 0x0000FFFFL
+-//DCP4_DC_LUT_WHITE_OFFSET_GREEN
+-#define DCP4_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT 0x0
+-#define DCP4_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK 0x0000FFFFL
+-//DCP4_DC_LUT_WHITE_OFFSET_RED
+-#define DCP4_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT 0x0
+-#define DCP4_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK 0x0000FFFFL
+-//DCP4_DCP_CRC_CONTROL
+-#define DCP4_DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT 0x0
+-#define DCP4_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x2
+-#define DCP4_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT 0x8
+-#define DCP4_DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK 0x00000001L
+-#define DCP4_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK 0x0000001CL
+-#define DCP4_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK 0x00000300L
+-//DCP4_DCP_CRC_MASK
+-#define DCP4_DCP_CRC_MASK__DCP_CRC_MASK__SHIFT 0x0
+-#define DCP4_DCP_CRC_MASK__DCP_CRC_MASK_MASK 0xFFFFFFFFL
+-//DCP4_DCP_CRC_CURRENT
+-#define DCP4_DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT 0x0
+-#define DCP4_DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK 0xFFFFFFFFL
+-//DCP4_DVMM_PTE_CONTROL
+-#define DCP4_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT 0x0
+-#define DCP4_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT 0x1
+-#define DCP4_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT 0x5
+-#define DCP4_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT 0x9
+-#define DCP4_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT 0x14
+-#define DCP4_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT 0x15
+-#define DCP4_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK 0x00000001L
+-#define DCP4_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK 0x0000001EL
+-#define DCP4_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK 0x000001E0L
+-#define DCP4_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK 0x0007FE00L
+-#define DCP4_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK 0x00100000L
+-#define DCP4_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK 0x00200000L
+-//DCP4_DCP_CRC_LAST
+-#define DCP4_DCP_CRC_LAST__DCP_CRC_LAST__SHIFT 0x0
+-#define DCP4_DCP_CRC_LAST__DCP_CRC_LAST_MASK 0xFFFFFFFFL
+-//DCP4_DVMM_PTE_ARB_CONTROL
+-#define DCP4_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT 0x0
+-#define DCP4_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT 0x8
+-#define DCP4_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK 0x0000003FL
+-#define DCP4_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK 0x0000FF00L
+-//DCP4_GRPH_FLIP_RATE_CNTL
+-#define DCP4_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT 0x0
+-#define DCP4_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT 0x3
+-#define DCP4_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK 0x00000007L
+-#define DCP4_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK 0x00000008L
+-//DCP4_DCP_GSL_CONTROL
+-#define DCP4_DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT 0x0
+-#define DCP4_DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT 0x1
+-#define DCP4_DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x2
+-#define DCP4_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT 0x4
+-#define DCP4_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT 0x14
+-#define DCP4_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP__SHIFT 0x15
+-#define DCP4_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN__SHIFT 0x17
+-#define DCP4_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT 0x18
+-#define DCP4_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC__SHIFT 0x1a
+-#define DCP4_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT 0x1b
+-#define DCP4_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT 0x1c
+-#define DCP4_DCP_GSL_CONTROL__DCP_GSL0_EN_MASK 0x00000001L
+-#define DCP4_DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x00000002L
+-#define DCP4_DCP_GSL_CONTROL__DCP_GSL2_EN_MASK 0x00000004L
+-#define DCP4_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK 0x000FFFF0L
+-#define DCP4_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK 0x00100000L
+-#define DCP4_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_MASK 0x00600000L
+-#define DCP4_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_MASK 0x00800000L
+-#define DCP4_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK 0x03000000L
+-#define DCP4_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_MASK 0x04000000L
+-#define DCP4_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK 0x08000000L
+-#define DCP4_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK 0xF0000000L
+-//DCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK
+-#define DCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT 0x0
+-#define DCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT 0x4
+-#define DCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK 0x0000000FL
+-#define DCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK 0x000001F0L
+-//DCP4_GRPH_STEREOSYNC_FLIP
+-#define DCP4_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0
+-#define DCP4_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x8
+-#define DCP4_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10
+-#define DCP4_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11
+-#define DCP4_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c
+-#define DCP4_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x00000001L
+-#define DCP4_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x00000300L
+-#define DCP4_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x00010000L
+-#define DCP4_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x00020000L
+-#define DCP4_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000L
+-//DCP4_HW_ROTATION
+-#define DCP4_HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT 0x0
+-#define DCP4_HW_ROTATION__GRPH_ROTATION_ANGLE_MASK 0x00000007L
+-//DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL
+-#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT 0x0
+-#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT 0x1
+-#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT 0x4
+-#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK 0x00000001L
+-#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK 0x00000002L
+-#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK 0x0001FFF0L
+-//DCP4_REGAMMA_CONTROL
+-#define DCP4_REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT 0x0
+-#define DCP4_REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK 0x00000007L
+-//DCP4_REGAMMA_LUT_INDEX
+-#define DCP4_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x0
+-#define DCP4_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK 0x000001FFL
+-//DCP4_REGAMMA_LUT_DATA
+-#define DCP4_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT 0x0
+-#define DCP4_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK 0x0007FFFFL
+-//DCP4_REGAMMA_LUT_WRITE_EN_MASK
+-#define DCP4_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x0
+-#define DCP4_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x00000007L
+-//DCP4_REGAMMA_CNTLA_START_CNTL
+-#define DCP4_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x0
+-#define DCP4_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14
+-#define DCP4_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK 0x0003FFFFL
+-#define DCP4_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
+-//DCP4_REGAMMA_CNTLA_SLOPE_CNTL
+-#define DCP4_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+-#define DCP4_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
+-//DCP4_REGAMMA_CNTLA_END_CNTL1
+-#define DCP4_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x0
+-#define DCP4_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK 0x0000FFFFL
+-//DCP4_REGAMMA_CNTLA_END_CNTL2
+-#define DCP4_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0
+-#define DCP4_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10
+-#define DCP4_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
+-#define DCP4_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xFFFF0000L
+-//DCP4_REGAMMA_CNTLA_REGION_0_1
+-#define DCP4_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+-#define DCP4_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP4_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+-#define DCP4_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP4_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP4_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP4_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP4_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP4_REGAMMA_CNTLA_REGION_2_3
+-#define DCP4_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+-#define DCP4_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP4_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+-#define DCP4_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP4_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP4_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP4_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP4_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP4_REGAMMA_CNTLA_REGION_4_5
+-#define DCP4_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+-#define DCP4_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP4_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+-#define DCP4_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP4_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP4_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP4_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP4_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP4_REGAMMA_CNTLA_REGION_6_7
+-#define DCP4_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+-#define DCP4_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP4_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+-#define DCP4_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP4_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP4_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP4_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP4_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP4_REGAMMA_CNTLA_REGION_8_9
+-#define DCP4_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+-#define DCP4_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP4_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+-#define DCP4_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP4_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP4_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP4_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP4_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP4_REGAMMA_CNTLA_REGION_10_11
+-#define DCP4_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+-#define DCP4_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP4_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+-#define DCP4_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP4_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP4_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP4_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP4_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP4_REGAMMA_CNTLA_REGION_12_13
+-#define DCP4_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+-#define DCP4_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP4_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+-#define DCP4_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP4_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP4_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP4_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP4_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP4_REGAMMA_CNTLA_REGION_14_15
+-#define DCP4_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+-#define DCP4_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP4_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+-#define DCP4_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP4_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP4_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP4_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP4_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP4_REGAMMA_CNTLB_START_CNTL
+-#define DCP4_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x0
+-#define DCP4_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14
+-#define DCP4_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK 0x0003FFFFL
+-#define DCP4_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
+-//DCP4_REGAMMA_CNTLB_SLOPE_CNTL
+-#define DCP4_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+-#define DCP4_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
+-//DCP4_REGAMMA_CNTLB_END_CNTL1
+-#define DCP4_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x0
+-#define DCP4_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK 0x0000FFFFL
+-//DCP4_REGAMMA_CNTLB_END_CNTL2
+-#define DCP4_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0
+-#define DCP4_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10
+-#define DCP4_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
+-#define DCP4_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xFFFF0000L
+-//DCP4_REGAMMA_CNTLB_REGION_0_1
+-#define DCP4_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+-#define DCP4_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP4_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+-#define DCP4_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP4_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP4_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP4_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP4_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP4_REGAMMA_CNTLB_REGION_2_3
+-#define DCP4_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+-#define DCP4_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP4_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+-#define DCP4_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP4_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP4_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP4_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP4_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP4_REGAMMA_CNTLB_REGION_4_5
+-#define DCP4_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+-#define DCP4_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP4_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+-#define DCP4_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP4_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP4_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP4_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP4_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP4_REGAMMA_CNTLB_REGION_6_7
+-#define DCP4_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+-#define DCP4_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP4_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+-#define DCP4_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP4_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP4_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP4_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP4_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP4_REGAMMA_CNTLB_REGION_8_9
+-#define DCP4_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+-#define DCP4_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP4_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+-#define DCP4_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP4_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP4_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP4_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP4_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP4_REGAMMA_CNTLB_REGION_10_11
+-#define DCP4_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+-#define DCP4_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP4_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+-#define DCP4_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP4_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP4_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP4_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP4_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP4_REGAMMA_CNTLB_REGION_12_13
+-#define DCP4_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+-#define DCP4_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP4_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+-#define DCP4_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP4_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP4_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP4_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP4_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP4_REGAMMA_CNTLB_REGION_14_15
+-#define DCP4_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+-#define DCP4_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP4_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+-#define DCP4_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP4_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP4_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP4_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP4_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP4_ALPHA_CONTROL
+-#define DCP4_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT 0x0
+-#define DCP4_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT 0x1
+-#define DCP4_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK 0x00000001L
+-#define DCP4_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK 0x00000002L
+-//DCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS
+-#define DCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT 0x8
+-#define DCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+-//DCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH
+-#define DCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+-#define DCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+-//DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS
+-#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT 0x0
+-#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT 0x18
+-#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT 0x19
+-#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT 0x1a
+-#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT 0x1c
+-#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT 0x1d
+-#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT 0x1e
+-#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK 0x000FFFFFL
+-#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK 0x01000000L
+-#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK 0x02000000L
+-#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK 0x04000000L
+-#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK 0x10000000L
+-#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK 0x20000000L
+-#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK 0x40000000L
+-//DCP4_GRPH_XDMA_FLIP_TIMEOUT
+-#define DCP4_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS__SHIFT 0x0
+-#define DCP4_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK__SHIFT 0x1
+-#define DCP4_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK__SHIFT 0x2
+-#define DCP4_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS_MASK 0x00000001L
+-#define DCP4_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK_MASK 0x00000002L
+-#define DCP4_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK_MASK 0x00000004L
+-//DCP4_GRPH_XDMA_FLIP_AVG_DELAY
+-#define DCP4_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY__SHIFT 0x0
+-#define DCP4_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD__SHIFT 0x10
+-#define DCP4_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY_MASK 0x0000FFFFL
+-#define DCP4_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD_MASK 0x00FF0000L
+-//DCP4_GRPH_SURFACE_COUNTER_CONTROL
+-#define DCP4_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN__SHIFT 0x0
+-#define DCP4_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT__SHIFT 0x1
+-#define DCP4_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED__SHIFT 0x9
+-#define DCP4_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN_MASK 0x00000001L
+-#define DCP4_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT_MASK 0x0000001EL
+-#define DCP4_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_MASK 0x00000200L
+-//DCP4_GRPH_SURFACE_COUNTER_OUTPUT
+-#define DCP4_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN__SHIFT 0x0
+-#define DCP4_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX__SHIFT 0x10
+-#define DCP4_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN_MASK 0x0000FFFFL
+-#define DCP4_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX_MASK 0xFFFF0000L
+-
+-
+-// addressBlock: dce_dc_lb4_dispdec
+-//LB4_LB_DATA_FORMAT
+-#define LB4_LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0
+-#define LB4_LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2
+-#define LB4_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3
+-#define LB4_LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4
+-#define LB4_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5
+-#define LB4_LB_DATA_FORMAT__PREFILL_EN__SHIFT 0x8
+-#define LB4_LB_DATA_FORMAT__PREFETCH__SHIFT 0xc
+-#define LB4_LB_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18
+-#define LB4_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f
+-#define LB4_LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x00000003L
+-#define LB4_LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x00000004L
+-#define LB4_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000008L
+-#define LB4_LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x00000010L
+-#define LB4_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x00000020L
+-#define LB4_LB_DATA_FORMAT__PREFILL_EN_MASK 0x00000100L
+-#define LB4_LB_DATA_FORMAT__PREFETCH_MASK 0x00001000L
+-#define LB4_LB_DATA_FORMAT__REQUEST_MODE_MASK 0x01000000L
+-#define LB4_LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000L
+-//LB4_LB_MEMORY_CTRL
+-#define LB4_LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0
+-#define LB4_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
+-#define LB4_LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14
+-#define LB4_LB_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0x00001FFFL
+-#define LB4_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x000F0000L
+-#define LB4_LB_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x00300000L
+-//LB4_LB_MEMORY_SIZE_STATUS
+-#define LB4_LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0
+-#define LB4_LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0x00001FFFL
+-//LB4_LB_DESKTOP_HEIGHT
+-#define LB4_LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0
+-#define LB4_LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x00007FFFL
+-//LB4_LB_VLINE_START_END
+-#define LB4_LB_VLINE_START_END__VLINE_START__SHIFT 0x0
+-#define LB4_LB_VLINE_START_END__VLINE_END__SHIFT 0x10
+-#define LB4_LB_VLINE_START_END__VLINE_INV__SHIFT 0x1f
+-#define LB4_LB_VLINE_START_END__VLINE_START_MASK 0x00003FFFL
+-#define LB4_LB_VLINE_START_END__VLINE_END_MASK 0x7FFF0000L
+-#define LB4_LB_VLINE_START_END__VLINE_INV_MASK 0x80000000L
+-//LB4_LB_VLINE2_START_END
+-#define LB4_LB_VLINE2_START_END__VLINE2_START__SHIFT 0x0
+-#define LB4_LB_VLINE2_START_END__VLINE2_END__SHIFT 0x10
+-#define LB4_LB_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f
+-#define LB4_LB_VLINE2_START_END__VLINE2_START_MASK 0x00003FFFL
+-#define LB4_LB_VLINE2_START_END__VLINE2_END_MASK 0x7FFF0000L
+-#define LB4_LB_VLINE2_START_END__VLINE2_INV_MASK 0x80000000L
+-//LB4_LB_V_COUNTER
+-#define LB4_LB_V_COUNTER__V_COUNTER__SHIFT 0x0
+-#define LB4_LB_V_COUNTER__V_COUNTER_MASK 0x00007FFFL
+-//LB4_LB_SNAPSHOT_V_COUNTER
+-#define LB4_LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0
+-#define LB4_LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x00007FFFL
+-//LB4_LB_INTERRUPT_MASK
+-#define LB4_LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0
+-#define LB4_LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4
+-#define LB4_LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8
+-#define LB4_LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x00000001L
+-#define LB4_LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x00000010L
+-#define LB4_LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x00000100L
+-//LB4_LB_VLINE_STATUS
+-#define LB4_LB_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0
+-#define LB4_LB_VLINE_STATUS__VLINE_ACK__SHIFT 0x4
+-#define LB4_LB_VLINE_STATUS__VLINE_STAT__SHIFT 0xc
+-#define LB4_LB_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10
+-#define LB4_LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11
+-#define LB4_LB_VLINE_STATUS__VLINE_OCCURRED_MASK 0x00000001L
+-#define LB4_LB_VLINE_STATUS__VLINE_ACK_MASK 0x00000010L
+-#define LB4_LB_VLINE_STATUS__VLINE_STAT_MASK 0x00001000L
+-#define LB4_LB_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x00010000L
+-#define LB4_LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x00020000L
+-//LB4_LB_VLINE2_STATUS
+-#define LB4_LB_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0
+-#define LB4_LB_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4
+-#define LB4_LB_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc
+-#define LB4_LB_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10
+-#define LB4_LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11
+-#define LB4_LB_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x00000001L
+-#define LB4_LB_VLINE2_STATUS__VLINE2_ACK_MASK 0x00000010L
+-#define LB4_LB_VLINE2_STATUS__VLINE2_STAT_MASK 0x00001000L
+-#define LB4_LB_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x00010000L
+-#define LB4_LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x00020000L
+-//LB4_LB_VBLANK_STATUS
+-#define LB4_LB_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0
+-#define LB4_LB_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4
+-#define LB4_LB_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc
+-#define LB4_LB_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10
+-#define LB4_LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11
+-#define LB4_LB_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x00000001L
+-#define LB4_LB_VBLANK_STATUS__VBLANK_ACK_MASK 0x00000010L
+-#define LB4_LB_VBLANK_STATUS__VBLANK_STAT_MASK 0x00001000L
+-#define LB4_LB_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x00010000L
+-#define LB4_LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x00020000L
+-//LB4_LB_SYNC_RESET_SEL
+-#define LB4_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0
+-#define LB4_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4
+-#define LB4_LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8
+-#define LB4_LB_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16
+-#define LB4_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x00000003L
+-#define LB4_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x00000010L
+-#define LB4_LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0x0000FF00L
+-#define LB4_LB_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0x00C00000L
+-//LB4_LB_BLACK_KEYER_R_CR
+-#define LB4_LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4
+-#define LB4_LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0x0000FFF0L
+-//LB4_LB_BLACK_KEYER_G_Y
+-#define LB4_LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4
+-#define LB4_LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0x0000FFF0L
+-//LB4_LB_BLACK_KEYER_B_CB
+-#define LB4_LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4
+-#define LB4_LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0x0000FFF0L
+-//LB4_LB_KEYER_COLOR_CTRL
+-#define LB4_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0
+-#define LB4_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8
+-#define LB4_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x00000001L
+-#define LB4_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x00000100L
+-//LB4_LB_KEYER_COLOR_R_CR
+-#define LB4_LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4
+-#define LB4_LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0x0000FFF0L
+-//LB4_LB_KEYER_COLOR_G_Y
+-#define LB4_LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4
+-#define LB4_LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0x0000FFF0L
+-//LB4_LB_KEYER_COLOR_B_CB
+-#define LB4_LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4
+-#define LB4_LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0x0000FFF0L
+-//LB4_LB_KEYER_COLOR_REP_R_CR
+-#define LB4_LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4
+-#define LB4_LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0x0000FFF0L
+-//LB4_LB_KEYER_COLOR_REP_G_Y
+-#define LB4_LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4
+-#define LB4_LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0x0000FFF0L
+-//LB4_LB_KEYER_COLOR_REP_B_CB
+-#define LB4_LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4
+-#define LB4_LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0x0000FFF0L
+-//LB4_LB_BUFFER_LEVEL_STATUS
+-#define LB4_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0
+-#define LB4_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa
+-#define LB4_LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10
+-#define LB4_LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c
+-#define LB4_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x0000003FL
+-#define LB4_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0x0000FC00L
+-#define LB4_LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0x0FFF0000L
+-#define LB4_LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xF0000000L
+-//LB4_LB_BUFFER_URGENCY_CTRL
+-#define LB4_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0
+-#define LB4_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10
+-#define LB4_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0x00000FFFL
+-#define LB4_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0x0FFF0000L
+-//LB4_LB_BUFFER_URGENCY_STATUS
+-#define LB4_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0
+-#define LB4_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10
+-#define LB4_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0x00000FFFL
+-#define LB4_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x00010000L
+-//LB4_LB_BUFFER_STATUS
+-#define LB4_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0
+-#define LB4_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4
+-#define LB4_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8
+-#define LB4_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc
+-#define LB4_LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10
+-#define LB4_LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14
+-#define LB4_LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18
+-#define LB4_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0x0000000FL
+-#define LB4_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x00000010L
+-#define LB4_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x00000100L
+-#define LB4_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x00001000L
+-#define LB4_LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x00010000L
+-#define LB4_LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x00100000L
+-#define LB4_LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x01000000L
+-//LB4_LB_NO_OUTSTANDING_REQ_STATUS
+-#define LB4_LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0
+-#define LB4_LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x00000001L
+-//LB4_MVP_AFR_FLIP_MODE
+-#define LB4_MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT 0x0
+-#define LB4_MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK 0x00000003L
+-//LB4_MVP_AFR_FLIP_FIFO_CNTL
+-#define LB4_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT 0x0
+-#define LB4_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT 0x4
+-#define LB4_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT 0x8
+-#define LB4_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT 0xc
+-#define LB4_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK 0x0000000FL
+-#define LB4_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK 0x00000010L
+-#define LB4_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK 0x00000100L
+-#define LB4_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK 0x00001000L
+-//LB4_MVP_FLIP_LINE_NUM_INSERT
+-#define LB4_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT 0x0
+-#define LB4_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT 0x8
+-#define LB4_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT 0x18
+-#define LB4_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT 0x1e
+-#define LB4_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK 0x00000003L
+-#define LB4_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK 0x007FFF00L
+-#define LB4_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK 0x3F000000L
+-#define LB4_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK 0x40000000L
+-//LB4_DC_MVP_LB_CONTROL
+-#define LB4_DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT 0x0
+-#define LB4_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT 0x8
+-#define LB4_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT 0xc
+-#define LB4_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT 0x10
+-#define LB4_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT 0x14
+-#define LB4_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT 0x1c
+-#define LB4_DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT 0x1f
+-#define LB4_DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK 0x00000003L
+-#define LB4_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK 0x00000100L
+-#define LB4_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK 0x00001000L
+-#define LB4_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK 0x00010000L
+-#define LB4_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK 0x00100000L
+-#define LB4_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK 0x10000000L
+-#define LB4_DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK 0x80000000L
+-
+-
+-// addressBlock: dce_dc_dcfe4_dispdec
+-//DCFE4_DCFE_CLOCK_CONTROL
+-#define DCFE4_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x4
+-#define DCFE4_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x8
+-#define DCFE4_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0xc
+-#define DCFE4_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE__SHIFT 0xf
+-#define DCFE4_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE__SHIFT 0x11
+-#define DCFE4_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL__SHIFT 0x18
+-#define DCFE4_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE__SHIFT 0x1f
+-#define DCFE4_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x00000010L
+-#define DCFE4_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE_MASK 0x00000100L
+-#define DCFE4_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE_MASK 0x00001000L
+-#define DCFE4_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE_MASK 0x00008000L
+-#define DCFE4_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE_MASK 0x00020000L
+-#define DCFE4_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL_MASK 0x1F000000L
+-#define DCFE4_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE_MASK 0x80000000L
+-//DCFE4_DCFE_SOFT_RESET
+-#define DCFE4_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET__SHIFT 0x0
+-#define DCFE4_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET__SHIFT 0x1
+-#define DCFE4_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET__SHIFT 0x2
+-#define DCFE4_DCFE_SOFT_RESET__SCL_SOFT_RESET__SHIFT 0x3
+-#define DCFE4_DCFE_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4
+-#define DCFE4_DCFE_SOFT_RESET__PSCL_SOFT_RESET__SHIFT 0x5
+-#define DCFE4_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET_MASK 0x00000001L
+-#define DCFE4_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET_MASK 0x00000002L
+-#define DCFE4_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET_MASK 0x00000004L
+-#define DCFE4_DCFE_SOFT_RESET__SCL_SOFT_RESET_MASK 0x00000008L
+-#define DCFE4_DCFE_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x00000010L
+-#define DCFE4_DCFE_SOFT_RESET__PSCL_SOFT_RESET_MASK 0x00000020L
+-//DCFE4_DCFE_MEM_PWR_CTRL
+-#define DCFE4_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE__SHIFT 0x0
+-#define DCFE4_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS__SHIFT 0x2
+-#define DCFE4_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE__SHIFT 0x3
+-#define DCFE4_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS__SHIFT 0x5
+-#define DCFE4_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE__SHIFT 0x6
+-#define DCFE4_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS__SHIFT 0x8
+-#define DCFE4_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE__SHIFT 0x9
+-#define DCFE4_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS__SHIFT 0xb
+-#define DCFE4_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE__SHIFT 0xc
+-#define DCFE4_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS__SHIFT 0xe
+-#define DCFE4_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE__SHIFT 0xf
+-#define DCFE4_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS__SHIFT 0x11
+-#define DCFE4_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE__SHIFT 0x12
+-#define DCFE4_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS__SHIFT 0x14
+-#define DCFE4_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE__SHIFT 0x15
+-#define DCFE4_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS__SHIFT 0x17
+-#define DCFE4_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE__SHIFT 0x18
+-#define DCFE4_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS__SHIFT 0x1a
+-#define DCFE4_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE__SHIFT 0x1b
+-#define DCFE4_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS__SHIFT 0x1d
+-#define DCFE4_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE_MASK 0x00000003L
+-#define DCFE4_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS_MASK 0x00000004L
+-#define DCFE4_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE_MASK 0x00000018L
+-#define DCFE4_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS_MASK 0x00000020L
+-#define DCFE4_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE_MASK 0x000000C0L
+-#define DCFE4_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS_MASK 0x00000100L
+-#define DCFE4_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE_MASK 0x00000600L
+-#define DCFE4_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS_MASK 0x00000800L
+-#define DCFE4_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE_MASK 0x00003000L
+-#define DCFE4_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS_MASK 0x00004000L
+-#define DCFE4_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE_MASK 0x00018000L
+-#define DCFE4_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK 0x00020000L
+-#define DCFE4_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE_MASK 0x000C0000L
+-#define DCFE4_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS_MASK 0x00100000L
+-#define DCFE4_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE_MASK 0x00600000L
+-#define DCFE4_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS_MASK 0x00800000L
+-#define DCFE4_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE_MASK 0x03000000L
+-#define DCFE4_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS_MASK 0x04000000L
+-#define DCFE4_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE_MASK 0x18000000L
+-#define DCFE4_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS_MASK 0x20000000L
+-//DCFE4_DCFE_MEM_PWR_CTRL2
+-#define DCFE4_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL__SHIFT 0x0
+-#define DCFE4_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2
+-#define DCFE4_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4
+-#define DCFE4_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL__SHIFT 0x6
+-#define DCFE4_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL__SHIFT 0x8
+-#define DCFE4_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL__SHIFT 0xa
+-#define DCFE4_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL__SHIFT 0xc
+-#define DCFE4_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL__SHIFT 0xe
+-#define DCFE4_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE__SHIFT 0x10
+-#define DCFE4_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS__SHIFT 0x12
+-#define DCFE4_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE__SHIFT 0x15
+-#define DCFE4_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS__SHIFT 0x17
+-#define DCFE4_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL_MASK 0x00000003L
+-#define DCFE4_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL_MASK 0x0000000CL
+-#define DCFE4_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL_MASK 0x00000030L
+-#define DCFE4_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL_MASK 0x000000C0L
+-#define DCFE4_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL_MASK 0x00000300L
+-#define DCFE4_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL_MASK 0x00000C00L
+-#define DCFE4_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL_MASK 0x00003000L
+-#define DCFE4_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL_MASK 0x0000C000L
+-#define DCFE4_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE_MASK 0x00030000L
+-#define DCFE4_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS_MASK 0x00040000L
+-#define DCFE4_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE_MASK 0x00600000L
+-#define DCFE4_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS_MASK 0x00800000L
+-//DCFE4_DCFE_MEM_PWR_STATUS
+-#define DCFE4_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE__SHIFT 0x0
+-#define DCFE4_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE__SHIFT 0x2
+-#define DCFE4_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE__SHIFT 0x4
+-#define DCFE4_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x6
+-#define DCFE4_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE__SHIFT 0x8
+-#define DCFE4_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE__SHIFT 0xa
+-#define DCFE4_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE__SHIFT 0xc
+-#define DCFE4_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE__SHIFT 0xe
+-#define DCFE4_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT 0x10
+-#define DCFE4_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE__SHIFT 0x12
+-#define DCFE4_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE__SHIFT 0x14
+-#define DCFE4_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE__SHIFT 0x16
+-#define DCFE4_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK 0x00000003L
+-#define DCFE4_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE_MASK 0x0000000CL
+-#define DCFE4_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE_MASK 0x00000030L
+-#define DCFE4_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE_MASK 0x000000C0L
+-#define DCFE4_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE_MASK 0x00000300L
+-#define DCFE4_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE_MASK 0x00000C00L
+-#define DCFE4_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE_MASK 0x00003000L
+-#define DCFE4_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE_MASK 0x0000C000L
+-#define DCFE4_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE_MASK 0x00030000L
+-#define DCFE4_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK 0x000C0000L
+-#define DCFE4_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE_MASK 0x00300000L
+-#define DCFE4_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE_MASK 0x00C00000L
+-//DCFE4_DCFE_MISC
+-#define DCFE4_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN__SHIFT 0x0
+-#define DCFE4_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN_MASK 0x00000001L
+-//DCFE4_DCFE_FLUSH
+-#define DCFE4_DCFE_FLUSH__FLUSH_OCCURED__SHIFT 0x0
+-#define DCFE4_DCFE_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT 0x1
+-#define DCFE4_DCFE_FLUSH__FLUSH_DEEP__SHIFT 0x2
+-#define DCFE4_DCFE_FLUSH__CLEAR_FLUSH_DEEP__SHIFT 0x3
+-#define DCFE4_DCFE_FLUSH__ALL_MC_REQ_RET__SHIFT 0x4
+-#define DCFE4_DCFE_FLUSH__FLUSH_OCCURED_MASK 0x00000001L
+-#define DCFE4_DCFE_FLUSH__CLEAR_FLUSH_OCCURED_MASK 0x00000002L
+-#define DCFE4_DCFE_FLUSH__FLUSH_DEEP_MASK 0x00000004L
+-#define DCFE4_DCFE_FLUSH__CLEAR_FLUSH_DEEP_MASK 0x00000008L
+-#define DCFE4_DCFE_FLUSH__ALL_MC_REQ_RET_MASK 0x00000010L
+-
+-
+-// addressBlock: dce_dc_dc_perfmon7_dispdec
+-//DC_PERFMON7_PERFCOUNTER_CNTL
+-#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+-#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+-#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+-#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+-#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+-#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
+-#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+-#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+-#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+-#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+-#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+-#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
+-#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+-#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+-#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+-#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+-#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+-#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+-#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
+-#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+-#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+-#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+-#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+-#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+-#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
+-#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+-//DC_PERFMON7_PERFCOUNTER_CNTL2
+-#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+-#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+-#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+-#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+-#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+-#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+-#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+-#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+-//DC_PERFMON7_PERFCOUNTER_STATE
+-#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+-#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+-#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+-#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+-#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+-#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+-#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+-#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+-#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+-#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+-#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+-#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+-#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+-#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+-#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+-#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+-#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+-#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+-#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+-#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+-#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+-#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+-#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+-#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+-#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+-#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+-#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+-#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+-#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+-#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+-#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+-#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+-//DC_PERFMON7_PERFMON_CNTL
+-#define DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+-#define DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+-#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+-#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+-#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+-#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+-#define DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+-#define DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+-#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+-#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+-#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+-#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+-//DC_PERFMON7_PERFMON_CNTL2
+-#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+-#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+-#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+-#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+-#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+-#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+-#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+-#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+-//DC_PERFMON7_PERFMON_CVALUE_INT_MISC
+-#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+-#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+-#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+-#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+-#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+-#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+-#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+-#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+-#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+-#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+-#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+-#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+-#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+-#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+-#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+-#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+-#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+-#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+-#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+-#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+-#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+-#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+-#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+-#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+-#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+-#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+-#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+-#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+-#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+-#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+-#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+-#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+-#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+-#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+-//DC_PERFMON7_PERFMON_CVALUE_LOW
+-#define DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+-#define DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+-//DC_PERFMON7_PERFMON_HI
+-#define DC_PERFMON7_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+-#define DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+-#define DC_PERFMON7_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+-#define DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+-//DC_PERFMON7_PERFMON_LOW
+-#define DC_PERFMON7_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+-#define DC_PERFMON7_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dmif_pg4_dispdec
+-//DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1
+-#define DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
+-#define DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
+-#define DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0x0000FFFFL
+-#define DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xFFFF0000L
+-//DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2
+-#define DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
+-#define DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
+-#define DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0x0000FFFFL
+-#define DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xFFFF0000L
+-//DMIF_PG4_DPG_WATERMARK_MASK_CONTROL
+-#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
+-#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x4
+-#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
+-#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK__SHIFT 0xc
+-#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0xf
+-#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x12
+-#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL__SHIFT 0x13
+-#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL__SHIFT 0x14
+-#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000007L
+-#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000070L
+-#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x00000700L
+-#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK_MASK 0x00007000L
+-#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00038000L
+-#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x00040000L
+-#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL_MASK 0x00080000L
+-#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL_MASK 0x3FF00000L
+-//DMIF_PG4_DPG_PIPE_URGENCY_CONTROL
+-#define DMIF_PG4_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
+-#define DMIF_PG4_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
+-#define DMIF_PG4_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0x0000FFFFL
+-#define DMIF_PG4_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xFFFF0000L
+-//DMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL
+-#define DMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK__SHIFT 0x0
+-#define DMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK__SHIFT 0x10
+-#define DMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK_MASK 0x0000FFFFL
+-#define DMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK_MASK 0xFFFF0000L
+-//DMIF_PG4_DPG_PIPE_STUTTER_CONTROL
+-#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
+-#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
+-#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
+-#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
+-#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
+-#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
+-#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
+-#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH__SHIFT 0x10
+-#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x14
+-#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x15
+-#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x16
+-#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x17
+-#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0x1a
+-#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0x1b
+-#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L
+-#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L
+-#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x00000020L
+-#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x00000040L
+-#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x00000080L
+-#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x00000400L
+-#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x00000800L
+-#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH_MASK 0x00010000L
+-#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x00100000L
+-#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x00200000L
+-#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x00400000L
+-#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x00800000L
+-#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x04000000L
+-#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x08000000L
+-//DMIF_PG4_DPG_PIPE_STUTTER_CONTROL2
+-#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x0
+-#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK__SHIFT 0x10
+-#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0x0000FFFFL
+-#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK 0xFFFF0000L
+-//DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL
+-#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE__SHIFT 0x0
+-#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE__SHIFT 0x1
+-#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
+-#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
+-#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
+-#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
+-#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK__SHIFT 0xf
+-#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE_MASK 0x00000001L
+-#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE_MASK 0x00000002L
+-#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L
+-#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x00000100L
+-#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON_MASK 0x00000200L
+-#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT_MASK 0x00000400L
+-#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK_MASK 0xFFFF8000L
+-//DMIF_PG4_DPG_REPEATER_PROGRAM
+-#define DMIF_PG4_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
+-#define DMIF_PG4_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
+-#define DMIF_PG4_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x00000007L
+-#define DMIF_PG4_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x00000070L
+-//DMIF_PG4_DPG_CHK_PRE_PROC_CNTL
+-#define DMIF_PG4_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0
+-#define DMIF_PG4_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x00000001L
+-//DMIF_PG4_DPG_DVMM_STATUS
+-#define DMIF_PG4_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED__SHIFT 0x0
+-#define DMIF_PG4_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED__SHIFT 0x1
+-#define DMIF_PG4_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR__SHIFT 0x4
+-#define DMIF_PG4_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR__SHIFT 0x5
+-#define DMIF_PG4_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_MASK 0x00000001L
+-#define DMIF_PG4_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_MASK 0x00000002L
+-#define DMIF_PG4_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR_MASK 0x00000010L
+-#define DMIF_PG4_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR_MASK 0x00000020L
+-
+-
+-// addressBlock: dce_dc_scl4_dispdec
+-//SCL4_SCL_COEF_RAM_SELECT
+-#define SCL4_SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0
+-#define SCL4_SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8
+-#define SCL4_SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10
+-#define SCL4_SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x0000000FL
+-#define SCL4_SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x00000F00L
+-#define SCL4_SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x00070000L
+-//SCL4_SCL_COEF_RAM_TAP_DATA
+-#define SCL4_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0
+-#define SCL4_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
+-#define SCL4_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10
+-#define SCL4_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
+-#define SCL4_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL
+-#define SCL4_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L
+-#define SCL4_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L
+-#define SCL4_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L
+-//SCL4_SCL_MODE
+-#define SCL4_SCL_MODE__SCL_MODE__SHIFT 0x0
+-#define SCL4_SCL_MODE__SCL_PSCL_EN__SHIFT 0x4
+-#define SCL4_SCL_MODE__SCL_MODE_MASK 0x00000003L
+-#define SCL4_SCL_MODE__SCL_PSCL_EN_MASK 0x00000010L
+-//SCL4_SCL_TAP_CONTROL
+-#define SCL4_SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0
+-#define SCL4_SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x8
+-#define SCL4_SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x00000007L
+-#define SCL4_SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0x00000F00L
+-//SCL4_SCL_CONTROL
+-#define SCL4_SCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
+-#define SCL4_SCL_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4
+-#define SCL4_SCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L
+-#define SCL4_SCL_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x00000010L
+-//SCL4_SCL_BYPASS_CONTROL
+-#define SCL4_SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT 0x0
+-#define SCL4_SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x00000003L
+-//SCL4_SCL_MANUAL_REPLICATE_CONTROL
+-#define SCL4_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
+-#define SCL4_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
+-#define SCL4_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL
+-#define SCL4_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L
+-//SCL4_SCL_AUTOMATIC_MODE_CONTROL
+-#define SCL4_SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0
+-#define SCL4_SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10
+-#define SCL4_SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x00000001L
+-#define SCL4_SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x00010000L
+-//SCL4_SCL_HORZ_FILTER_CONTROL
+-#define SCL4_SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT 0x0
+-#define SCL4_SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+-#define SCL4_SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK 0x00000001L
+-#define SCL4_SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
+-//SCL4_SCL_HORZ_FILTER_SCALE_RATIO
+-#define SCL4_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
+-#define SCL4_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL
+-//SCL4_SCL_HORZ_FILTER_INIT
+-#define SCL4_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
+-#define SCL4_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
+-#define SCL4_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL
+-#define SCL4_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L
+-//SCL4_SCL_VERT_FILTER_CONTROL
+-#define SCL4_SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT 0x0
+-#define SCL4_SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+-#define SCL4_SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK 0x00000001L
+-#define SCL4_SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
+-//SCL4_SCL_VERT_FILTER_SCALE_RATIO
+-#define SCL4_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
+-#define SCL4_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL
+-//SCL4_SCL_VERT_FILTER_INIT
+-#define SCL4_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
+-#define SCL4_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
+-#define SCL4_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL
+-#define SCL4_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x07000000L
+-//SCL4_SCL_VERT_FILTER_INIT_BOT
+-#define SCL4_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
+-#define SCL4_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
+-#define SCL4_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL
+-#define SCL4_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x07000000L
+-//SCL4_SCL_ROUND_OFFSET
+-#define SCL4_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0
+-#define SCL4_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10
+-#define SCL4_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0x0000FFFFL
+-#define SCL4_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xFFFF0000L
+-//SCL4_SCL_UPDATE
+-#define SCL4_SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
+-#define SCL4_SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8
+-#define SCL4_SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10
+-#define SCL4_SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18
+-#define SCL4_SCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L
+-#define SCL4_SCL_UPDATE__SCL_UPDATE_TAKEN_MASK 0x00000100L
+-#define SCL4_SCL_UPDATE__SCL_UPDATE_LOCK_MASK 0x00010000L
+-#define SCL4_SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x01000000L
+-//SCL4_SCL_F_SHARP_CONTROL
+-#define SCL4_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT 0x0
+-#define SCL4_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT 0x4
+-#define SCL4_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT 0x8
+-#define SCL4_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT 0xc
+-#define SCL4_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK 0x00000007L
+-#define SCL4_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK 0x00000010L
+-#define SCL4_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK 0x00000700L
+-#define SCL4_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK 0x00001000L
+-//SCL4_SCL_ALU_CONTROL
+-#define SCL4_SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0
+-#define SCL4_SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x00000001L
+-//SCL4_SCL_COEF_RAM_CONFLICT_STATUS
+-#define SCL4_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT 0x0
+-#define SCL4_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT 0x8
+-#define SCL4_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT 0xc
+-#define SCL4_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10
+-#define SCL4_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK 0x00000001L
+-#define SCL4_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK 0x00000100L
+-#define SCL4_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK 0x00001000L
+-#define SCL4_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK 0x00010000L
+-//SCL4_VIEWPORT_START_SECONDARY
+-#define SCL4_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0
+-#define SCL4_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10
+-#define SCL4_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x00003FFFL
+-#define SCL4_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3FFF0000L
+-//SCL4_VIEWPORT_START
+-#define SCL4_VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0
+-#define SCL4_VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10
+-#define SCL4_VIEWPORT_START__VIEWPORT_Y_START_MASK 0x00003FFFL
+-#define SCL4_VIEWPORT_START__VIEWPORT_X_START_MASK 0x3FFF0000L
+-//SCL4_VIEWPORT_SIZE
+-#define SCL4_VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0
+-#define SCL4_VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10
+-#define SCL4_VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x00003FFFL
+-#define SCL4_VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x3FFF0000L
+-//SCL4_EXT_OVERSCAN_LEFT_RIGHT
+-#define SCL4_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
+-#define SCL4_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
+-#define SCL4_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL
+-#define SCL4_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L
+-//SCL4_EXT_OVERSCAN_TOP_BOTTOM
+-#define SCL4_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
+-#define SCL4_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
+-#define SCL4_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL
+-#define SCL4_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L
+-//SCL4_SCL_MODE_CHANGE_DET1
+-#define SCL4_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0
+-#define SCL4_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4
+-#define SCL4_SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7
+-#define SCL4_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x00000001L
+-#define SCL4_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x00000010L
+-#define SCL4_SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0x0FFFFF80L
+-//SCL4_SCL_MODE_CHANGE_DET2
+-#define SCL4_SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0
+-#define SCL4_SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x001FFFFFL
+-//SCL4_SCL_MODE_CHANGE_DET3
+-#define SCL4_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0
+-#define SCL4_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10
+-#define SCL4_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x00003FFFL
+-#define SCL4_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3FFF0000L
+-//SCL4_SCL_MODE_CHANGE_MASK
+-#define SCL4_SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0
+-#define SCL4_SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x00000001L
+-
+-
+-// addressBlock: dce_dc_blnd4_dispdec
+-//BLND4_BLND_CONTROL
+-#define BLND4_BLND_CONTROL__BLND_GLOBAL_GAIN__SHIFT 0x0
+-#define BLND4_BLND_CONTROL__BLND_MODE__SHIFT 0x8
+-#define BLND4_BLND_CONTROL__BLND_STEREO_TYPE__SHIFT 0xa
+-#define BLND4_BLND_CONTROL__BLND_STEREO_POLARITY__SHIFT 0xc
+-#define BLND4_BLND_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT 0xd
+-#define BLND4_BLND_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10
+-#define BLND4_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x12
+-#define BLND4_BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14
+-#define BLND4_BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18
+-#define BLND4_BLND_CONTROL__BLND_GLOBAL_GAIN_MASK 0x000000FFL
+-#define BLND4_BLND_CONTROL__BLND_MODE_MASK 0x00000300L
+-#define BLND4_BLND_CONTROL__BLND_STEREO_TYPE_MASK 0x00000C00L
+-#define BLND4_BLND_CONTROL__BLND_STEREO_POLARITY_MASK 0x00001000L
+-#define BLND4_BLND_CONTROL__BLND_FEEDTHROUGH_EN_MASK 0x00002000L
+-#define BLND4_BLND_CONTROL__BLND_ALPHA_MODE_MASK 0x00030000L
+-#define BLND4_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00040000L
+-#define BLND4_BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x00100000L
+-#define BLND4_BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xFF000000L
+-//BLND4_BLND_SM_CONTROL2
+-#define BLND4_BLND_SM_CONTROL2__SM_MODE__SHIFT 0x0
+-#define BLND4_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4
+-#define BLND4_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5
+-#define BLND4_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
+-#define BLND4_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
+-#define BLND4_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18
+-#define BLND4_BLND_SM_CONTROL2__SM_MODE_MASK 0x00000007L
+-#define BLND4_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x00000010L
+-#define BLND4_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x00000020L
+-#define BLND4_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L
+-#define BLND4_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L
+-#define BLND4_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x01000000L
+-//BLND4_BLND_CONTROL2
+-#define BLND4_BLND_CONTROL2__PTI_ENABLE__SHIFT 0x0
+-#define BLND4_BLND_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT 0x4
+-#define BLND4_BLND_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT 0x6
+-#define BLND4_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT 0x7
+-#define BLND4_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT 0x8
+-#define BLND4_BLND_CONTROL2__PTI_ENABLE_MASK 0x00000001L
+-#define BLND4_BLND_CONTROL2__PTI_NEW_PIXEL_GAP_MASK 0x00000030L
+-#define BLND4_BLND_CONTROL2__BLND_NEW_PIXEL_MODE_MASK 0x00000040L
+-#define BLND4_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK 0x00000080L
+-#define BLND4_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK 0x00000100L
+-//BLND4_BLND_UPDATE
+-#define BLND4_BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0
+-#define BLND4_BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8
+-#define BLND4_BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10
+-#define BLND4_BLND_UPDATE__BLND_UPDATE_PENDING_MASK 0x00000001L
+-#define BLND4_BLND_UPDATE__BLND_UPDATE_TAKEN_MASK 0x00000100L
+-#define BLND4_BLND_UPDATE__BLND_UPDATE_LOCK_MASK 0x00010000L
+-//BLND4_BLND_UNDERFLOW_INTERRUPT
+-#define BLND4_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0
+-#define BLND4_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8
+-#define BLND4_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc
+-#define BLND4_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10
+-#define BLND4_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x00000001L
+-#define BLND4_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x00000100L
+-#define BLND4_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x00001000L
+-#define BLND4_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x00030000L
+-//BLND4_BLND_V_UPDATE_LOCK
+-#define BLND4_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0
+-#define BLND4_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1
+-#define BLND4_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10
+-#define BLND4_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c
+-#define BLND4_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT 0x1d
+-#define BLND4_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT 0x1f
+-#define BLND4_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x00000001L
+-#define BLND4_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x00000002L
+-#define BLND4_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x00010000L
+-#define BLND4_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000L
+-#define BLND4_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK 0x20000000L
+-#define BLND4_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK 0x80000000L
+-//BLND4_BLND_REG_UPDATE_STATUS
+-#define BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT 0x0
+-#define BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT 0x1
+-#define BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2
+-#define BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3
+-#define BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT 0x6
+-#define BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT 0x7
+-#define BLND4_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT 0x8
+-#define BLND4_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT 0x9
+-#define BLND4_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT 0xa
+-#define BLND4_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT 0xb
+-#define BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK 0x00000001L
+-#define BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK 0x00000002L
+-#define BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK 0x00000004L
+-#define BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK 0x00000008L
+-#define BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK 0x00000040L
+-#define BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK 0x00000080L
+-#define BLND4_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK 0x00000100L
+-#define BLND4_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK 0x00000200L
+-#define BLND4_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK 0x00000400L
+-#define BLND4_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK 0x00000800L
+-
+-
+-// addressBlock: dce_dc_crtc4_dispdec
+-//CRTC4_CRTC_H_BLANK_EARLY_NUM
+-#define CRTC4_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0
+-#define CRTC4_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10
+-#define CRTC4_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x000003FFL
+-#define CRTC4_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x00010000L
+-//CRTC4_CRTC_H_TOTAL
+-#define CRTC4_CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0
+-#define CRTC4_CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x00003FFFL
+-//CRTC4_CRTC_H_BLANK_START_END
+-#define CRTC4_CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0
+-#define CRTC4_CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10
+-#define CRTC4_CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x00003FFFL
+-#define CRTC4_CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3FFF0000L
+-//CRTC4_CRTC_H_SYNC_A
+-#define CRTC4_CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0
+-#define CRTC4_CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10
+-#define CRTC4_CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x00003FFFL
+-#define CRTC4_CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3FFF0000L
+-//CRTC4_CRTC_H_SYNC_A_CNTL
+-#define CRTC4_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0
+-#define CRTC4_CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10
+-#define CRTC4_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11
+-#define CRTC4_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x00000001L
+-#define CRTC4_CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x00010000L
+-#define CRTC4_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x00020000L
+-//CRTC4_CRTC_H_SYNC_B
+-#define CRTC4_CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0
+-#define CRTC4_CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10
+-#define CRTC4_CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x00003FFFL
+-#define CRTC4_CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x3FFF0000L
+-//CRTC4_CRTC_H_SYNC_B_CNTL
+-#define CRTC4_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0
+-#define CRTC4_CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10
+-#define CRTC4_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11
+-#define CRTC4_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x00000001L
+-#define CRTC4_CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x00010000L
+-#define CRTC4_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x00020000L
+-//CRTC4_CRTC_VBI_END
+-#define CRTC4_CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x0
+-#define CRTC4_CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x10
+-#define CRTC4_CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x00003FFFL
+-#define CRTC4_CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x3FFF0000L
+-//CRTC4_CRTC_V_TOTAL
+-#define CRTC4_CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0
+-#define CRTC4_CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x00003FFFL
+-//CRTC4_CRTC_V_TOTAL_MIN
+-#define CRTC4_CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0
+-#define CRTC4_CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x00003FFFL
+-//CRTC4_CRTC_V_TOTAL_MAX
+-#define CRTC4_CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0
+-#define CRTC4_CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10
+-#define CRTC4_CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x00003FFFL
+-#define CRTC4_CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x00010000L
+-//CRTC4_CRTC_V_TOTAL_CONTROL
+-#define CRTC4_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0
+-#define CRTC4_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4
+-#define CRTC4_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8
+-#define CRTC4_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc
+-#define CRTC4_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf
+-#define CRTC4_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10
+-#define CRTC4_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x00000001L
+-#define CRTC4_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x00000010L
+-#define CRTC4_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x00000100L
+-#define CRTC4_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x00001000L
+-#define CRTC4_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00008000L
+-#define CRTC4_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L
+-//CRTC4_CRTC_V_TOTAL_INT_STATUS
+-#define CRTC4_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0
+-#define CRTC4_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4
+-#define CRTC4_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8
+-#define CRTC4_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc
+-#define CRTC4_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L
+-#define CRTC4_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L
+-#define CRTC4_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L
+-#define CRTC4_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L
+-//CRTC4_CRTC_VSYNC_NOM_INT_STATUS
+-#define CRTC4_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0
+-#define CRTC4_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4
+-#define CRTC4_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x00000001L
+-#define CRTC4_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L
+-//CRTC4_CRTC_V_BLANK_START_END
+-#define CRTC4_CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0
+-#define CRTC4_CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10
+-#define CRTC4_CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x00003FFFL
+-#define CRTC4_CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3FFF0000L
+-//CRTC4_CRTC_V_SYNC_A
+-#define CRTC4_CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0
+-#define CRTC4_CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10
+-#define CRTC4_CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x00003FFFL
+-#define CRTC4_CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3FFF0000L
+-//CRTC4_CRTC_V_SYNC_A_CNTL
+-#define CRTC4_CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0
+-#define CRTC4_CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x00000001L
+-//CRTC4_CRTC_V_SYNC_B
+-#define CRTC4_CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0
+-#define CRTC4_CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10
+-#define CRTC4_CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x00003FFFL
+-#define CRTC4_CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x3FFF0000L
+-//CRTC4_CRTC_V_SYNC_B_CNTL
+-#define CRTC4_CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0
+-#define CRTC4_CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x00000001L
+-//CRTC4_CRTC_DTMTEST_CNTL
+-#define CRTC4_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0
+-#define CRTC4_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1
+-#define CRTC4_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x00000001L
+-#define CRTC4_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x0000001EL
+-//CRTC4_CRTC_DTMTEST_STATUS_POSITION
+-#define CRTC4_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0
+-#define CRTC4_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10
+-#define CRTC4_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x00003FFFL
+-#define CRTC4_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x3FFF0000L
+-//CRTC4_CRTC_TRIGA_CNTL
+-#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0
+-#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5
+-#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8
+-#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9
+-#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa
+-#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb
+-#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
+-#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
+-#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14
+-#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18
+-#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f
+-#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x0000001FL
+-#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0x000000E0L
+-#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000100L
+-#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x00000200L
+-#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x00000400L
+-#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x00000800L
+-#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
+-#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
+-#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L
+-#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1F000000L
+-#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000L
+-//CRTC4_CRTC_TRIGA_MANUAL_TRIG
+-#define CRTC4_CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0
+-#define CRTC4_CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x00000001L
+-//CRTC4_CRTC_TRIGB_CNTL
+-#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0
+-#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5
+-#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8
+-#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9
+-#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa
+-#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb
+-#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
+-#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
+-#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14
+-#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18
+-#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f
+-#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x0000001FL
+-#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0x000000E0L
+-#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000100L
+-#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x00000200L
+-#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x00000400L
+-#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x00000800L
+-#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
+-#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
+-#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L
+-#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1F000000L
+-#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000L
+-//CRTC4_CRTC_TRIGB_MANUAL_TRIG
+-#define CRTC4_CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0
+-#define CRTC4_CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x00000001L
+-//CRTC4_CRTC_FORCE_COUNT_NOW_CNTL
+-#define CRTC4_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0
+-#define CRTC4_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4
+-#define CRTC4_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8
+-#define CRTC4_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10
+-#define CRTC4_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18
+-#define CRTC4_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x00000003L
+-#define CRTC4_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L
+-#define CRTC4_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L
+-#define CRTC4_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L
+-#define CRTC4_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L
+-//CRTC4_CRTC_FLOW_CONTROL
+-#define CRTC4_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0
+-#define CRTC4_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8
+-#define CRTC4_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10
+-#define CRTC4_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18
+-#define CRTC4_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL
+-#define CRTC4_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x00000100L
+-#define CRTC4_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L
+-#define CRTC4_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L
+-//CRTC4_CRTC_STEREO_FORCE_NEXT_EYE
+-#define CRTC4_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0
+-#define CRTC4_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER__SHIFT 0x8
+-#define CRTC4_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER__SHIFT 0x10
+-#define CRTC4_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L
+-#define CRTC4_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L
+-#define CRTC4_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L
+-//CRTC4_CRTC_AVSYNC_COUNTER
+-#define CRTC4_CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER__SHIFT 0x0
+-#define CRTC4_CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER_MASK 0xFFFFFFFFL
+-//CRTC4_CRTC_CONTROL
+-#define CRTC4_CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x0
+-#define CRTC4_CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4
+-#define CRTC4_CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8
+-#define CRTC4_CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc
+-#define CRTC4_CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd
+-#define CRTC4_CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe
+-#define CRTC4_CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10
+-#define CRTC4_CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14
+-#define CRTC4_CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d
+-#define CRTC4_CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e
+-#define CRTC4_CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f
+-#define CRTC4_CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x00000001L
+-#define CRTC4_CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x00000010L
+-#define CRTC4_CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x00000300L
+-#define CRTC4_CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x00001000L
+-#define CRTC4_CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x00002000L
+-#define CRTC4_CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x00004000L
+-#define CRTC4_CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x00010000L
+-#define CRTC4_CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x00700000L
+-#define CRTC4_CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000L
+-#define CRTC4_CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L
+-#define CRTC4_CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L
+-//CRTC4_CRTC_BLANK_CONTROL
+-#define CRTC4_CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0
+-#define CRTC4_CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8
+-#define CRTC4_CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10
+-#define CRTC4_CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x00000001L
+-#define CRTC4_CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x00000100L
+-#define CRTC4_CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x00010000L
+-//CRTC4_CRTC_INTERLACE_CONTROL
+-#define CRTC4_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0
+-#define CRTC4_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10
+-#define CRTC4_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x00000001L
+-#define CRTC4_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L
+-//CRTC4_CRTC_INTERLACE_STATUS
+-#define CRTC4_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0
+-#define CRTC4_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1
+-#define CRTC4_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x00000001L
+-#define CRTC4_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x00000002L
+-//CRTC4_CRTC_FIELD_INDICATION_CONTROL
+-#define CRTC4_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0
+-#define CRTC4_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1
+-#define CRTC4_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x00000001L
+-#define CRTC4_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x00000002L
+-//CRTC4_CRTC_PIXEL_DATA_READBACK0
+-#define CRTC4_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0
+-#define CRTC4_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10
+-#define CRTC4_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0x00000FFFL
+-#define CRTC4_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0x0FFF0000L
+-//CRTC4_CRTC_PIXEL_DATA_READBACK1
+-#define CRTC4_CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0
+-#define CRTC4_CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0x00000FFFL
+-//CRTC4_CRTC_STATUS
+-#define CRTC4_CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x0
+-#define CRTC4_CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1
+-#define CRTC4_CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x2
+-#define CRTC4_CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x3
+-#define CRTC4_CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x4
+-#define CRTC4_CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5
+-#define CRTC4_CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x10
+-#define CRTC4_CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11
+-#define CRTC4_CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x12
+-#define CRTC4_CRTC_STATUS__CRTC_V_BLANK_MASK 0x00000001L
+-#define CRTC4_CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x00000002L
+-#define CRTC4_CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x00000004L
+-#define CRTC4_CRTC_STATUS__CRTC_V_UPDATE_MASK 0x00000008L
+-#define CRTC4_CRTC_STATUS__CRTC_V_START_LINE_MASK 0x00000010L
+-#define CRTC4_CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x00000020L
+-#define CRTC4_CRTC_STATUS__CRTC_H_BLANK_MASK 0x00010000L
+-#define CRTC4_CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x00020000L
+-#define CRTC4_CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x00040000L
+-//CRTC4_CRTC_STATUS_POSITION
+-#define CRTC4_CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0
+-#define CRTC4_CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10
+-#define CRTC4_CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x00003FFFL
+-#define CRTC4_CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x3FFF0000L
+-//CRTC4_CRTC_NOM_VERT_POSITION
+-#define CRTC4_CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0
+-#define CRTC4_CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x00003FFFL
+-//CRTC4_CRTC_STATUS_FRAME_COUNT
+-#define CRTC4_CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0
+-#define CRTC4_CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0x00FFFFFFL
+-//CRTC4_CRTC_STATUS_VF_COUNT
+-#define CRTC4_CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0
+-#define CRTC4_CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x3FFFFFFFL
+-//CRTC4_CRTC_STATUS_HV_COUNT
+-#define CRTC4_CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0
+-#define CRTC4_CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x3FFFFFFFL
+-//CRTC4_CRTC_COUNT_CONTROL
+-#define CRTC4_CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0
+-#define CRTC4_CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1
+-#define CRTC4_CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x00000001L
+-#define CRTC4_CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x0000001EL
+-//CRTC4_CRTC_COUNT_RESET
+-#define CRTC4_CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0
+-#define CRTC4_CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x00000001L
+-//CRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE
+-#define CRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0
+-#define CRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L
+-//CRTC4_CRTC_VERT_SYNC_CONTROL
+-#define CRTC4_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0
+-#define CRTC4_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8
+-#define CRTC4_CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10
+-#define CRTC4_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L
+-#define CRTC4_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L
+-#define CRTC4_CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L
+-//CRTC4_CRTC_STEREO_STATUS
+-#define CRTC4_CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0
+-#define CRTC4_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8
+-#define CRTC4_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10
+-#define CRTC4_CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG__SHIFT 0x14
+-#define CRTC4_CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18
+-#define CRTC4_CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x00000001L
+-#define CRTC4_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x00000100L
+-#define CRTC4_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x00010000L
+-#define CRTC4_CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG_MASK 0x00100000L
+-#define CRTC4_CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L
+-//CRTC4_CRTC_STEREO_CONTROL
+-#define CRTC4_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0
+-#define CRTC4_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf
+-#define CRTC4_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10
+-#define CRTC4_CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11
+-#define CRTC4_CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12
+-#define CRTC4_CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM__SHIFT 0x13
+-#define CRTC4_CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14
+-#define CRTC4_CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18
+-#define CRTC4_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00003FFFL
+-#define CRTC4_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L
+-#define CRTC4_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x00010000L
+-#define CRTC4_CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L
+-#define CRTC4_CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L
+-#define CRTC4_CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM_MASK 0x00080000L
+-#define CRTC4_CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L
+-#define CRTC4_CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x01000000L
+-//CRTC4_CRTC_SNAPSHOT_STATUS
+-#define CRTC4_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0
+-#define CRTC4_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1
+-#define CRTC4_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2
+-#define CRTC4_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x00000001L
+-#define CRTC4_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x00000002L
+-#define CRTC4_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L
+-//CRTC4_CRTC_SNAPSHOT_CONTROL
+-#define CRTC4_CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0
+-#define CRTC4_CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L
+-//CRTC4_CRTC_SNAPSHOT_POSITION
+-#define CRTC4_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0
+-#define CRTC4_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10
+-#define CRTC4_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x00003FFFL
+-#define CRTC4_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x3FFF0000L
+-//CRTC4_CRTC_SNAPSHOT_FRAME
+-#define CRTC4_CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0
+-#define CRTC4_CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL
+-//CRTC4_CRTC_START_LINE_CONTROL
+-#define CRTC4_CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0
+-#define CRTC4_CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x1
+-#define CRTC4_CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x2
+-#define CRTC4_CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x8
+-#define CRTC4_CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc
+-#define CRTC4_CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x00000001L
+-#define CRTC4_CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x00000002L
+-#define CRTC4_CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x00000004L
+-#define CRTC4_CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x00000100L
+-#define CRTC4_CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0x000FF000L
+-//CRTC4_CRTC_INTERRUPT_CONTROL
+-#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0
+-#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1
+-#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4
+-#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5
+-#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8
+-#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9
+-#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10
+-#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11
+-#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18
+-#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19
+-#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a
+-#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b
+-#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c
+-#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d
+-#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e
+-#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f
+-#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x00000001L
+-#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x00000002L
+-#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x00000010L
+-#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x00000020L
+-#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L
+-#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L
+-#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L
+-#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L
+-#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x01000000L
+-#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x02000000L
+-#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x04000000L
+-#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x08000000L
+-#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000L
+-#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000L
+-#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L
+-#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L
+-//CRTC4_CRTC_UPDATE_LOCK
+-#define CRTC4_CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0
+-#define CRTC4_CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x00000001L
+-//CRTC4_CRTC_DOUBLE_BUFFER_CONTROL
+-#define CRTC4_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0
+-#define CRTC4_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8
+-#define CRTC4_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10
+-#define CRTC4_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18
+-#define CRTC4_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x19
+-#define CRTC4_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x00000001L
+-#define CRTC4_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x00000100L
+-#define CRTC4_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L
+-#define CRTC4_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x01000000L
+-#define CRTC4_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x02000000L
+-//CRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE
+-#define CRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0
+-#define CRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x00000001L
+-//CRTC4_CRTC_TEST_PATTERN_CONTROL
+-#define CRTC4_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0
+-#define CRTC4_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8
+-#define CRTC4_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10
+-#define CRTC4_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18
+-#define CRTC4_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x00000001L
+-#define CRTC4_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x00000700L
+-#define CRTC4_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L
+-#define CRTC4_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xFF000000L
+-//CRTC4_CRTC_TEST_PATTERN_PARAMETERS
+-#define CRTC4_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0
+-#define CRTC4_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4
+-#define CRTC4_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8
+-#define CRTC4_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc
+-#define CRTC4_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10
+-#define CRTC4_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0x0000000FL
+-#define CRTC4_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0x000000F0L
+-#define CRTC4_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0x00000F00L
+-#define CRTC4_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0x0000F000L
+-#define CRTC4_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xFFFF0000L
+-//CRTC4_CRTC_TEST_PATTERN_COLOR
+-#define CRTC4_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0
+-#define CRTC4_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10
+-#define CRTC4_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0x0000FFFFL
+-#define CRTC4_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x003F0000L
+-//CRTC4_CRTC_MASTER_UPDATE_LOCK
+-#define CRTC4_CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0
+-#define CRTC4_CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8
+-#define CRTC4_CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK__SHIFT 0x10
+-#define CRTC4_CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x00000001L
+-#define CRTC4_CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x00000100L
+-#define CRTC4_CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK_MASK 0x00010000L
+-//CRTC4_CRTC_MASTER_UPDATE_MODE
+-#define CRTC4_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0
+-#define CRTC4_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10
+-#define CRTC4_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x00000007L
+-#define CRTC4_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00030000L
+-//CRTC4_CRTC_MVP_INBAND_CNTL_INSERT
+-#define CRTC4_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0
+-#define CRTC4_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8
+-#define CRTC4_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x00000003L
+-#define CRTC4_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xFFFFFF00L
+-//CRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER
+-#define CRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0
+-#define CRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0x000000FFL
+-//CRTC4_CRTC_MVP_STATUS
+-#define CRTC4_CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0
+-#define CRTC4_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4
+-#define CRTC4_CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10
+-#define CRTC4_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14
+-#define CRTC4_CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x00000001L
+-#define CRTC4_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x00000010L
+-#define CRTC4_CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x00010000L
+-#define CRTC4_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x00100000L
+-//CRTC4_CRTC_MASTER_EN
+-#define CRTC4_CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0
+-#define CRTC4_CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x00000001L
+-//CRTC4_CRTC_ALLOW_STOP_OFF_V_CNT
+-#define CRTC4_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0
+-#define CRTC4_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10
+-#define CRTC4_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0x000000FFL
+-#define CRTC4_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x00010000L
+-//CRTC4_CRTC_V_UPDATE_INT_STATUS
+-#define CRTC4_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0
+-#define CRTC4_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8
+-#define CRTC4_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x00000001L
+-#define CRTC4_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x00000100L
+-//CRTC4_CRTC_OVERSCAN_COLOR
+-#define CRTC4_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0
+-#define CRTC4_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa
+-#define CRTC4_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14
+-#define CRTC4_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x000003FFL
+-#define CRTC4_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0x000FFC00L
+-#define CRTC4_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3FF00000L
+-//CRTC4_CRTC_OVERSCAN_COLOR_EXT
+-#define CRTC4_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0
+-#define CRTC4_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8
+-#define CRTC4_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10
+-#define CRTC4_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x00000003L
+-#define CRTC4_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x00000300L
+-#define CRTC4_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x00030000L
+-//CRTC4_CRTC_BLANK_DATA_COLOR
+-#define CRTC4_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0
+-#define CRTC4_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa
+-#define CRTC4_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14
+-#define CRTC4_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL
+-#define CRTC4_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L
+-#define CRTC4_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L
+-//CRTC4_CRTC_BLANK_DATA_COLOR_EXT
+-#define CRTC4_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0
+-#define CRTC4_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8
+-#define CRTC4_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10
+-#define CRTC4_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x00000003L
+-#define CRTC4_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00000300L
+-#define CRTC4_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x00030000L
+-//CRTC4_CRTC_BLACK_COLOR
+-#define CRTC4_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0
+-#define CRTC4_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa
+-#define CRTC4_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14
+-#define CRTC4_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x000003FFL
+-#define CRTC4_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0x000FFC00L
+-#define CRTC4_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3FF00000L
+-//CRTC4_CRTC_BLACK_COLOR_EXT
+-#define CRTC4_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0
+-#define CRTC4_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8
+-#define CRTC4_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10
+-#define CRTC4_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x00000003L
+-#define CRTC4_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x00000300L
+-#define CRTC4_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x00030000L
+-//CRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION
+-#define CRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0
+-#define CRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10
+-#define CRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00003FFFL
+-#define CRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x3FFF0000L
+-//CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL
+-#define CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4
+-#define CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8
+-#define CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc
+-#define CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10
+-#define CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14
+-#define CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18
+-#define CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L
+-#define CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L
+-#define CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L
+-#define CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L
+-#define CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L
+-#define CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L
+-//CRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION
+-#define CRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0
+-#define CRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00003FFFL
+-//CRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL
+-#define CRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8
+-#define CRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc
+-#define CRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10
+-#define CRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14
+-#define CRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18
+-#define CRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L
+-#define CRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L
+-#define CRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L
+-#define CRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L
+-#define CRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L
+-//CRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION
+-#define CRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0
+-#define CRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00003FFFL
+-//CRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL
+-#define CRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8
+-#define CRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc
+-#define CRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10
+-#define CRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14
+-#define CRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18
+-#define CRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L
+-#define CRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L
+-#define CRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L
+-#define CRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L
+-#define CRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L
+-//CRTC4_CRTC_CRC_CNTL
+-#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0
+-#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4
+-#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8
+-#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc
+-#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
+-#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14
+-#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18
+-#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC_EN_MASK 0x00000001L
+-#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x00000010L
+-#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x00000300L
+-#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x00003000L
+-#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
+-#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x00700000L
+-#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x07000000L
+-//CRTC4_CRTC_CRC0_WINDOWA_X_CONTROL
+-#define CRTC4_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0
+-#define CRTC4_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10
+-#define CRTC4_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x00003FFFL
+-#define CRTC4_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3FFF0000L
+-//CRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL
+-#define CRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0
+-#define CRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10
+-#define CRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x00003FFFL
+-#define CRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3FFF0000L
+-//CRTC4_CRTC_CRC0_WINDOWB_X_CONTROL
+-#define CRTC4_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0
+-#define CRTC4_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10
+-#define CRTC4_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x00003FFFL
+-#define CRTC4_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3FFF0000L
+-//CRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL
+-#define CRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0
+-#define CRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10
+-#define CRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x00003FFFL
+-#define CRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3FFF0000L
+-//CRTC4_CRTC_CRC0_DATA_RG
+-#define CRTC4_CRTC_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0
+-#define CRTC4_CRTC_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10
+-#define CRTC4_CRTC_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL
+-#define CRTC4_CRTC_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L
+-//CRTC4_CRTC_CRC0_DATA_B
+-#define CRTC4_CRTC_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0
+-#define CRTC4_CRTC_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL
+-//CRTC4_CRTC_CRC1_WINDOWA_X_CONTROL
+-#define CRTC4_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0
+-#define CRTC4_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10
+-#define CRTC4_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x00003FFFL
+-#define CRTC4_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3FFF0000L
+-//CRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL
+-#define CRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0
+-#define CRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10
+-#define CRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x00003FFFL
+-#define CRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3FFF0000L
+-//CRTC4_CRTC_CRC1_WINDOWB_X_CONTROL
+-#define CRTC4_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0
+-#define CRTC4_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10
+-#define CRTC4_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x00003FFFL
+-#define CRTC4_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3FFF0000L
+-//CRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL
+-#define CRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0
+-#define CRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10
+-#define CRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x00003FFFL
+-#define CRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3FFF0000L
+-//CRTC4_CRTC_CRC1_DATA_RG
+-#define CRTC4_CRTC_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0
+-#define CRTC4_CRTC_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10
+-#define CRTC4_CRTC_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL
+-#define CRTC4_CRTC_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L
+-//CRTC4_CRTC_CRC1_DATA_B
+-#define CRTC4_CRTC_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0
+-#define CRTC4_CRTC_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL
+-//CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE__SHIFT 0x0
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__SHIFT 0x3
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__SHIFT 0x4
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__SHIFT 0x5
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__SHIFT 0x8
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__SHIFT 0x9
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__SHIFT 0xc
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__SHIFT 0xd
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__SHIFT 0xe
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE__SHIFT 0x18
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE__SHIFT 0x1c
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE_MASK 0x00000003L
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_MASK 0x00000008L
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_MASK 0x00000010L
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_MASK 0x00000060L
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_MASK 0x00000100L
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_MASK 0x00000200L
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_MASK 0x00001000L
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_MASK 0x00002000L
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_MASK 0x00004000L
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE_MASK 0x07000000L
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE_MASK 0x70000000L
+-//CRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X__SHIFT 0x0
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y__SHIFT 0x10
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X_MASK 0x00003FFFL
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y_MASK 0x3FFF0000L
+-//CRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X__SHIFT 0x0
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y__SHIFT 0x10
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X_MASK 0x00003FFFL
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y_MASK 0x3FFF0000L
+-//CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__SHIFT 0x0
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS__SHIFT 0x4
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS__SHIFT 0x8
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__SHIFT 0x10
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__SHIFT 0x14
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__SHIFT 0x1d
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_MASK 0x00000001L
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS_MASK 0x00000010L
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS_MASK 0x00000100L
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_MASK 0x00010000L
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_MASK 0x00100000L
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_MASK 0xE0000000L
+-//CRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE__SHIFT 0x0
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS__SHIFT 0x4
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS__SHIFT 0x8
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR__SHIFT 0x10
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE__SHIFT 0x14
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE_MASK 0x00000001L
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS_MASK 0x00000010L
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS_MASK 0x00000100L
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR_MASK 0x00010000L
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE_MASK 0x00100000L
+-//CRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__SHIFT 0x0
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS__SHIFT 0x4
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS__SHIFT 0x8
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__SHIFT 0x10
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__SHIFT 0x14
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_MASK 0x00000001L
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS_MASK 0x00000010L
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS_MASK 0x00000100L
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_MASK 0x00010000L
+-#define CRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_MASK 0x00100000L
+-//CRTC4_CRTC_STATIC_SCREEN_CONTROL
+-#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0
+-#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10
+-#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18
+-#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19
+-#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a
+-#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b
+-#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c
+-#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e
+-#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f
+-#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL
+-#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L
+-#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x01000000L
+-#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x02000000L
+-#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x04000000L
+-#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x08000000L
+-#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000L
+-#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L
+-#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L
+-//CRTC4_CRTC_3D_STRUCTURE_CONTROL
+-#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0
+-#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4
+-#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8
+-#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc
+-#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10
+-#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11
+-#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12
+-#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x00000001L
+-#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x00000010L
+-#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L
+-#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L
+-#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L
+-#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L
+-#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L
+-//CRTC4_CRTC_GSL_VSYNC_GAP
+-#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0
+-#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8
+-#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10
+-#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11
+-#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13
+-#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14
+-#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17
+-#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18
+-#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL
+-#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L
+-#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L
+-#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x00060000L
+-#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L
+-#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L
+-#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L
+-#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xFF000000L
+-//CRTC4_CRTC_GSL_WINDOW
+-#define CRTC4_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0
+-#define CRTC4_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10
+-#define CRTC4_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x00003FFFL
+-#define CRTC4_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x3FFF0000L
+-//CRTC4_CRTC_GSL_CONTROL
+-#define CRTC4_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0
+-#define CRTC4_CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10
+-#define CRTC4_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c
+-#define CRTC4_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x00003FFFL
+-#define CRTC4_CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x001F0000L
+-#define CRTC4_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L
+-//CRTC4_CRTC_RANGE_TIMING_INT_STATUS
+-#define CRTC4_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0
+-#define CRTC4_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4
+-#define CRTC4_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8
+-#define CRTC4_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc
+-#define CRTC4_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10
+-#define CRTC4_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L
+-#define CRTC4_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L
+-#define CRTC4_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L
+-#define CRTC4_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L
+-#define CRTC4_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L
+-//CRTC4_CRTC_DRR_CONTROL
+-#define CRTC4_CRTC_DRR_CONTROL__CRTC_XDMA_PREFETCH_DELAY__SHIFT 0x0
+-#define CRTC4_CRTC_DRR_CONTROL__CRTC_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0xe
+-#define CRTC4_CRTC_DRR_CONTROL__CRTC_SET_V_TOTAL_MIN_AUTO_DIS__SHIFT 0x1c
+-#define CRTC4_CRTC_DRR_CONTROL__CRTC_DRR_MODE_DBUF_UPDATE_MODE__SHIFT 0x1d
+-#define CRTC4_CRTC_DRR_CONTROL__CRTC_XDMA_PREFETCH_DELAY_MASK 0x00003FFFL
+-#define CRTC4_CRTC_DRR_CONTROL__CRTC_V_TOTAL_LAST_USED_BY_DRR_MASK 0x0FFFC000L
+-#define CRTC4_CRTC_DRR_CONTROL__CRTC_SET_V_TOTAL_MIN_AUTO_DIS_MASK 0x10000000L
+-#define CRTC4_CRTC_DRR_CONTROL__CRTC_DRR_MODE_DBUF_UPDATE_MODE_MASK 0x60000000L
+-
+-
+-// addressBlock: dce_dc_fmt4_dispdec
+-//FMT4_FMT_CLAMP_COMPONENT_R
+-#define FMT4_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0
+-#define FMT4_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10
+-#define FMT4_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL
+-#define FMT4_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L
+-//FMT4_FMT_CLAMP_COMPONENT_G
+-#define FMT4_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0
+-#define FMT4_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10
+-#define FMT4_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL
+-#define FMT4_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L
+-//FMT4_FMT_CLAMP_COMPONENT_B
+-#define FMT4_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0
+-#define FMT4_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10
+-#define FMT4_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL
+-#define FMT4_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L
+-//FMT4_FMT_DYNAMIC_EXP_CNTL
+-#define FMT4_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0
+-#define FMT4_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4
+-#define FMT4_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L
+-#define FMT4_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L
+-//FMT4_FMT_CONTROL
+-#define FMT4_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0
+-#define FMT4_FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT 0x4
+-#define FMT4_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8
+-#define FMT4_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc
+-#define FMT4_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10
+-#define FMT4_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12
+-#define FMT4_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14
+-#define FMT4_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15
+-#define FMT4_FMT_CONTROL__FMT_SRC_SELECT__SHIFT 0x18
+-#define FMT4_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED__SHIFT 0x1e
+-#define FMT4_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_CLEAR__SHIFT 0x1f
+-#define FMT4_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L
+-#define FMT4_FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK 0x00000010L
+-#define FMT4_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L
+-#define FMT4_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L
+-#define FMT4_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L
+-#define FMT4_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L
+-#define FMT4_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L
+-#define FMT4_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L
+-#define FMT4_FMT_CONTROL__FMT_SRC_SELECT_MASK 0x07000000L
+-#define FMT4_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_MASK 0x40000000L
+-#define FMT4_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_CLEAR_MASK 0x80000000L
+-//FMT4_FMT_BIT_DEPTH_CONTROL
+-#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0
+-#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1
+-#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4
+-#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8
+-#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9
+-#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb
+-#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd
+-#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe
+-#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf
+-#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10
+-#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11
+-#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15
+-#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18
+-#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19
+-#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a
+-#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c
+-#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e
+-#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L
+-#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L
+-#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L
+-#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L
+-#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L
+-#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L
+-#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L
+-#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L
+-#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L
+-#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L
+-#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L
+-#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L
+-#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L
+-#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L
+-#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L
+-#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L
+-#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L
+-//FMT4_FMT_DITHER_RAND_R_SEED
+-#define FMT4_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0
+-#define FMT4_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10
+-#define FMT4_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL
+-#define FMT4_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L
+-//FMT4_FMT_DITHER_RAND_G_SEED
+-#define FMT4_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0
+-#define FMT4_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10
+-#define FMT4_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL
+-#define FMT4_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L
+-//FMT4_FMT_DITHER_RAND_B_SEED
+-#define FMT4_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0
+-#define FMT4_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10
+-#define FMT4_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL
+-#define FMT4_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L
+-//FMT4_FMT_CLAMP_CNTL
+-#define FMT4_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0
+-#define FMT4_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10
+-#define FMT4_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L
+-#define FMT4_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L
+-//FMT4_FMT_CRC_CNTL
+-#define FMT4_FMT_CRC_CNTL__FMT_CRC_EN__SHIFT 0x0
+-#define FMT4_FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN__SHIFT 0x1
+-#define FMT4_FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT 0x4
+-#define FMT4_FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING__SHIFT 0x5
+-#define FMT4_FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN__SHIFT 0x6
+-#define FMT4_FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB__SHIFT 0x8
+-#define FMT4_FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE__SHIFT 0x9
+-#define FMT4_FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT 0xc
+-#define FMT4_FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
+-#define FMT4_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT 0x14
+-#define FMT4_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT 0x18
+-#define FMT4_FMT_CRC_CNTL__FMT_CRC_EN_MASK 0x00000001L
+-#define FMT4_FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN_MASK 0x00000002L
+-#define FMT4_FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK 0x00000010L
+-#define FMT4_FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING_MASK 0x00000020L
+-#define FMT4_FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN_MASK 0x00000040L
+-#define FMT4_FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB_MASK 0x00000100L
+-#define FMT4_FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE_MASK 0x00000200L
+-#define FMT4_FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK 0x00003000L
+-#define FMT4_FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
+-#define FMT4_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK 0x00100000L
+-#define FMT4_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK 0x01000000L
+-//FMT4_FMT_CRC_SIG_RED_GREEN_MASK
+-#define FMT4_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT 0x0
+-#define FMT4_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT 0x10
+-#define FMT4_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK 0x0000FFFFL
+-#define FMT4_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L
+-//FMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK
+-#define FMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT 0x0
+-#define FMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT 0x10
+-#define FMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL
+-#define FMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L
+-//FMT4_FMT_CRC_SIG_RED_GREEN
+-#define FMT4_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT 0x0
+-#define FMT4_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT 0x10
+-#define FMT4_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK 0x0000FFFFL
+-#define FMT4_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK 0xFFFF0000L
+-//FMT4_FMT_CRC_SIG_BLUE_CONTROL
+-#define FMT4_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT 0x0
+-#define FMT4_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT 0x10
+-#define FMT4_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK 0x0000FFFFL
+-#define FMT4_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK 0xFFFF0000L
+-//FMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+-#define FMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0
+-#define FMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL
+-//FMT4_FMT_420_HBLANK_EARLY_START
+-#define FMT4_FMT_420_HBLANK_EARLY_START__FMT_420_HBLANK_EARLY_START__SHIFT 0x0
+-#define FMT4_FMT_420_HBLANK_EARLY_START__FMT_420_HBLANK_EARLY_START_MASK 0x00000FFFL
+-
+-
+-// addressBlock: dce_dc_dcp5_dispdec
+-//DCP5_GRPH_ENABLE
+-#define DCP5_GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0
+-#define DCP5_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL__SHIFT 0x1
+-#define DCP5_GRPH_ENABLE__GRPH_ENABLE_MASK 0x00000001L
+-#define DCP5_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL_MASK 0x00000002L
+-//DCP5_GRPH_CONTROL
+-#define DCP5_GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0
+-#define DCP5_GRPH_CONTROL__GRPH_SE_ENABLE__SHIFT 0x2
+-#define DCP5_GRPH_CONTROL__GRPH_Z__SHIFT 0x4
+-#define DCP5_GRPH_CONTROL__GRPH_DIM_TYPE__SHIFT 0x6
+-#define DCP5_GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8
+-#define DCP5_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0xc
+-#define DCP5_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10
+-#define DCP5_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11
+-#define DCP5_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES__SHIFT 0x12
+-#define DCP5_GRPH_CONTROL__GRPH_SW_MODE__SHIFT 0x14
+-#define DCP5_GRPH_CONTROL__GRPH_NUM_PIPES__SHIFT 0x1c
+-#define DCP5_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f
+-#define DCP5_GRPH_CONTROL__GRPH_DEPTH_MASK 0x00000003L
+-#define DCP5_GRPH_CONTROL__GRPH_SE_ENABLE_MASK 0x00000004L
+-#define DCP5_GRPH_CONTROL__GRPH_Z_MASK 0x00000030L
+-#define DCP5_GRPH_CONTROL__GRPH_DIM_TYPE_MASK 0x000000C0L
+-#define DCP5_GRPH_CONTROL__GRPH_FORMAT_MASK 0x00000700L
+-#define DCP5_GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0x00007000L
+-#define DCP5_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x00010000L
+-#define DCP5_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x00020000L
+-#define DCP5_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES_MASK 0x000C0000L
+-#define DCP5_GRPH_CONTROL__GRPH_SW_MODE_MASK 0x01F00000L
+-#define DCP5_GRPH_CONTROL__GRPH_NUM_PIPES_MASK 0x70000000L
+-#define DCP5_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000L
+-//DCP5_GRPH_LUT_10BIT_BYPASS
+-#define DCP5_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT 0x8
+-#define DCP5_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x10
+-#define DCP5_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK 0x00000100L
+-#define DCP5_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x00010000L
+-//DCP5_GRPH_SWAP_CNTL
+-#define DCP5_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0
+-#define DCP5_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4
+-#define DCP5_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6
+-#define DCP5_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8
+-#define DCP5_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT 0xa
+-#define DCP5_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x00000003L
+-#define DCP5_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x00000030L
+-#define DCP5_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0x000000C0L
+-#define DCP5_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x00000300L
+-#define DCP5_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK 0x00000C00L
+-//DCP5_GRPH_PRIMARY_SURFACE_ADDRESS
+-#define DCP5_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT 0x0
+-#define DCP5_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT 0x8
+-#define DCP5_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK 0x00000001L
+-#define DCP5_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+-//DCP5_GRPH_SECONDARY_SURFACE_ADDRESS
+-#define DCP5_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT 0x0
+-#define DCP5_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8
+-#define DCP5_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK 0x00000001L
+-#define DCP5_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+-//DCP5_GRPH_PITCH
+-#define DCP5_GRPH_PITCH__GRPH_PITCH__SHIFT 0x0
+-#define DCP5_GRPH_PITCH__GRPH_PITCH_MASK 0x00007FFFL
+-//DCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+-#define DCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+-#define DCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+-//DCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+-#define DCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+-#define DCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+-//DCP5_GRPH_SURFACE_OFFSET_X
+-#define DCP5_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT 0x0
+-#define DCP5_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK 0x00003FFFL
+-//DCP5_GRPH_SURFACE_OFFSET_Y
+-#define DCP5_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT 0x0
+-#define DCP5_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK 0x00003FFFL
+-//DCP5_GRPH_X_START
+-#define DCP5_GRPH_X_START__GRPH_X_START__SHIFT 0x0
+-#define DCP5_GRPH_X_START__GRPH_X_START_MASK 0x00003FFFL
+-//DCP5_GRPH_Y_START
+-#define DCP5_GRPH_Y_START__GRPH_Y_START__SHIFT 0x0
+-#define DCP5_GRPH_Y_START__GRPH_Y_START_MASK 0x00003FFFL
+-//DCP5_GRPH_X_END
+-#define DCP5_GRPH_X_END__GRPH_X_END__SHIFT 0x0
+-#define DCP5_GRPH_X_END__GRPH_X_END_MASK 0x00007FFFL
+-//DCP5_GRPH_Y_END
+-#define DCP5_GRPH_Y_END__GRPH_Y_END__SHIFT 0x0
+-#define DCP5_GRPH_Y_END__GRPH_Y_END_MASK 0x00007FFFL
+-//DCP5_INPUT_GAMMA_CONTROL
+-#define DCP5_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x0
+-#define DCP5_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK 0x00000001L
+-//DCP5_GRPH_UPDATE
+-#define DCP5_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0
+-#define DCP5_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1
+-#define DCP5_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2
+-#define DCP5_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3
+-#define DCP5_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR__SHIFT 0x8
+-#define DCP5_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE__SHIFT 0x9
+-#define DCP5_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE__SHIFT 0xa
+-#define DCP5_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10
+-#define DCP5_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14
+-#define DCP5_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+-#define DCP5_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c
+-#define DCP5_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x00000001L
+-#define DCP5_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x00000002L
+-#define DCP5_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x00000004L
+-#define DCP5_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x00000008L
+-#define DCP5_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR_MASK 0x00000100L
+-#define DCP5_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE_MASK 0x00000200L
+-#define DCP5_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE_MASK 0x00000400L
+-#define DCP5_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x00010000L
+-#define DCP5_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x00100000L
+-#define DCP5_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
+-#define DCP5_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000L
+-//DCP5_GRPH_FLIP_CONTROL
+-#define DCP5_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT 0x0
+-#define DCP5_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN__SHIFT 0x1
+-#define DCP5_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN__SHIFT 0x4
+-#define DCP5_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT 0x5
+-#define DCP5_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK 0x00000001L
+-#define DCP5_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN_MASK 0x00000002L
+-#define DCP5_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN_MASK 0x00000010L
+-#define DCP5_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK 0x00000020L
+-//DCP5_GRPH_SURFACE_ADDRESS_INUSE
+-#define DCP5_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT 0x8
+-#define DCP5_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK 0xFFFFFF00L
+-//DCP5_GRPH_DFQ_CONTROL
+-#define DCP5_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x0
+-#define DCP5_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x4
+-#define DCP5_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8
+-#define DCP5_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x00000001L
+-#define DCP5_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x00000070L
+-#define DCP5_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x00000700L
+-//DCP5_GRPH_DFQ_STATUS
+-#define DCP5_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x0
+-#define DCP5_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4
+-#define DCP5_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x8
+-#define DCP5_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x9
+-#define DCP5_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0x0000000FL
+-#define DCP5_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0x000000F0L
+-#define DCP5_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x00000100L
+-#define DCP5_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x00000200L
+-//DCP5_GRPH_INTERRUPT_STATUS
+-#define DCP5_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0
+-#define DCP5_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8
+-#define DCP5_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x00000001L
+-#define DCP5_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x00000100L
+-//DCP5_GRPH_INTERRUPT_CONTROL
+-#define DCP5_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0
+-#define DCP5_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8
+-#define DCP5_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x00000001L
+-#define DCP5_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x00000100L
+-//DCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE
+-#define DCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0
+-#define DCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK 0x000000FFL
+-//DCP5_GRPH_COMPRESS_SURFACE_ADDRESS
+-#define DCP5_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT 0x8
+-#define DCP5_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+-//DCP5_GRPH_COMPRESS_PITCH
+-#define DCP5_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT 0x6
+-#define DCP5_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK 0x0001FFC0L
+-//DCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH
+-#define DCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+-#define DCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+-//DCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT
+-#define DCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__SHIFT 0x0
+-#define DCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_MASK 0x000000FFL
+-//DCP5_PRESCALE_GRPH_CONTROL
+-#define DCP5_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT 0x0
+-#define DCP5_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT 0x1
+-#define DCP5_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x2
+-#define DCP5_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT 0x3
+-#define DCP5_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT 0x4
+-#define DCP5_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK 0x00000001L
+-#define DCP5_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x00000002L
+-#define DCP5_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK 0x00000004L
+-#define DCP5_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK 0x00000008L
+-#define DCP5_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK 0x00000010L
+-//DCP5_PRESCALE_VALUES_GRPH_R
+-#define DCP5_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT 0x0
+-#define DCP5_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT 0x10
+-#define DCP5_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK 0x0000FFFFL
+-#define DCP5_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK 0xFFFF0000L
+-//DCP5_PRESCALE_VALUES_GRPH_G
+-#define DCP5_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT 0x0
+-#define DCP5_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT 0x10
+-#define DCP5_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK 0x0000FFFFL
+-#define DCP5_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK 0xFFFF0000L
+-//DCP5_PRESCALE_VALUES_GRPH_B
+-#define DCP5_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT 0x0
+-#define DCP5_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT 0x10
+-#define DCP5_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK 0x0000FFFFL
+-#define DCP5_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK 0xFFFF0000L
+-//DCP5_INPUT_CSC_CONTROL
+-#define DCP5_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT 0x0
+-#define DCP5_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK 0x00000003L
+-//DCP5_INPUT_CSC_C11_C12
+-#define DCP5_INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT 0x0
+-#define DCP5_INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT 0x10
+-#define DCP5_INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK 0x0000FFFFL
+-#define DCP5_INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK 0xFFFF0000L
+-//DCP5_INPUT_CSC_C13_C14
+-#define DCP5_INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT 0x0
+-#define DCP5_INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT 0x10
+-#define DCP5_INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK 0x0000FFFFL
+-#define DCP5_INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK 0xFFFF0000L
+-//DCP5_INPUT_CSC_C21_C22
+-#define DCP5_INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT 0x0
+-#define DCP5_INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT 0x10
+-#define DCP5_INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK 0x0000FFFFL
+-#define DCP5_INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK 0xFFFF0000L
+-//DCP5_INPUT_CSC_C23_C24
+-#define DCP5_INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT 0x0
+-#define DCP5_INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT 0x10
+-#define DCP5_INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK 0x0000FFFFL
+-#define DCP5_INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK 0xFFFF0000L
+-//DCP5_INPUT_CSC_C31_C32
+-#define DCP5_INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT 0x0
+-#define DCP5_INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT 0x10
+-#define DCP5_INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK 0x0000FFFFL
+-#define DCP5_INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK 0xFFFF0000L
+-//DCP5_INPUT_CSC_C33_C34
+-#define DCP5_INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT 0x0
+-#define DCP5_INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT 0x10
+-#define DCP5_INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK 0x0000FFFFL
+-#define DCP5_INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK 0xFFFF0000L
+-//DCP5_OUTPUT_CSC_CONTROL
+-#define DCP5_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT 0x0
+-#define DCP5_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK 0x00000007L
+-//DCP5_OUTPUT_CSC_C11_C12
+-#define DCP5_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT 0x0
+-#define DCP5_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT 0x10
+-#define DCP5_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK 0x0000FFFFL
+-#define DCP5_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK 0xFFFF0000L
+-//DCP5_OUTPUT_CSC_C13_C14
+-#define DCP5_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT 0x0
+-#define DCP5_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT 0x10
+-#define DCP5_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK 0x0000FFFFL
+-#define DCP5_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK 0xFFFF0000L
+-//DCP5_OUTPUT_CSC_C21_C22
+-#define DCP5_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT 0x0
+-#define DCP5_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT 0x10
+-#define DCP5_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK 0x0000FFFFL
+-#define DCP5_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK 0xFFFF0000L
+-//DCP5_OUTPUT_CSC_C23_C24
+-#define DCP5_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT 0x0
+-#define DCP5_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT 0x10
+-#define DCP5_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK 0x0000FFFFL
+-#define DCP5_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK 0xFFFF0000L
+-//DCP5_OUTPUT_CSC_C31_C32
+-#define DCP5_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT 0x0
+-#define DCP5_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT 0x10
+-#define DCP5_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK 0x0000FFFFL
+-#define DCP5_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK 0xFFFF0000L
+-//DCP5_OUTPUT_CSC_C33_C34
+-#define DCP5_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT 0x0
+-#define DCP5_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT 0x10
+-#define DCP5_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK 0x0000FFFFL
+-#define DCP5_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK 0xFFFF0000L
+-//DCP5_COMM_MATRIXA_TRANS_C11_C12
+-#define DCP5_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT 0x0
+-#define DCP5_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT 0x10
+-#define DCP5_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK 0x0000FFFFL
+-#define DCP5_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK 0xFFFF0000L
+-//DCP5_COMM_MATRIXA_TRANS_C13_C14
+-#define DCP5_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT 0x0
+-#define DCP5_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT 0x10
+-#define DCP5_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK 0x0000FFFFL
+-#define DCP5_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK 0xFFFF0000L
+-//DCP5_COMM_MATRIXA_TRANS_C21_C22
+-#define DCP5_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT 0x0
+-#define DCP5_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT 0x10
+-#define DCP5_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK 0x0000FFFFL
+-#define DCP5_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK 0xFFFF0000L
+-//DCP5_COMM_MATRIXA_TRANS_C23_C24
+-#define DCP5_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT 0x0
+-#define DCP5_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT 0x10
+-#define DCP5_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK 0x0000FFFFL
+-#define DCP5_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK 0xFFFF0000L
+-//DCP5_COMM_MATRIXA_TRANS_C31_C32
+-#define DCP5_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT 0x0
+-#define DCP5_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT 0x10
+-#define DCP5_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK 0x0000FFFFL
+-#define DCP5_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK 0xFFFF0000L
+-//DCP5_COMM_MATRIXA_TRANS_C33_C34
+-#define DCP5_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT 0x0
+-#define DCP5_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT 0x10
+-#define DCP5_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK 0x0000FFFFL
+-#define DCP5_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK 0xFFFF0000L
+-//DCP5_COMM_MATRIXB_TRANS_C11_C12
+-#define DCP5_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT 0x0
+-#define DCP5_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT 0x10
+-#define DCP5_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK 0x0000FFFFL
+-#define DCP5_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK 0xFFFF0000L
+-//DCP5_COMM_MATRIXB_TRANS_C13_C14
+-#define DCP5_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT 0x0
+-#define DCP5_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT 0x10
+-#define DCP5_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK 0x0000FFFFL
+-#define DCP5_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK 0xFFFF0000L
+-//DCP5_COMM_MATRIXB_TRANS_C21_C22
+-#define DCP5_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT 0x0
+-#define DCP5_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT 0x10
+-#define DCP5_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK 0x0000FFFFL
+-#define DCP5_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK 0xFFFF0000L
+-//DCP5_COMM_MATRIXB_TRANS_C23_C24
+-#define DCP5_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT 0x0
+-#define DCP5_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT 0x10
+-#define DCP5_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK 0x0000FFFFL
+-#define DCP5_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK 0xFFFF0000L
+-//DCP5_COMM_MATRIXB_TRANS_C31_C32
+-#define DCP5_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT 0x0
+-#define DCP5_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT 0x10
+-#define DCP5_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK 0x0000FFFFL
+-#define DCP5_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK 0xFFFF0000L
+-//DCP5_COMM_MATRIXB_TRANS_C33_C34
+-#define DCP5_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT 0x0
+-#define DCP5_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT 0x10
+-#define DCP5_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK 0x0000FFFFL
+-#define DCP5_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK 0xFFFF0000L
+-//DCP5_DENORM_CONTROL
+-#define DCP5_DENORM_CONTROL__DENORM_MODE__SHIFT 0x0
+-#define DCP5_DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT 0x4
+-#define DCP5_DENORM_CONTROL__DENORM_MODE_MASK 0x00000007L
+-#define DCP5_DENORM_CONTROL__DENORM_14BIT_OUT_MASK 0x00000010L
+-//DCP5_OUT_ROUND_CONTROL
+-#define DCP5_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT 0x0
+-#define DCP5_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK 0x0000000FL
+-//DCP5_OUT_CLAMP_CONTROL_R_CR
+-#define DCP5_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT 0x0
+-#define DCP5_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT 0x10
+-#define DCP5_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK 0x00003FFFL
+-#define DCP5_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK 0x3FFF0000L
+-//DCP5_OUT_CLAMP_CONTROL_G_Y
+-#define DCP5_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT 0x0
+-#define DCP5_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT 0x10
+-#define DCP5_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK 0x00003FFFL
+-#define DCP5_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK 0x3FFF0000L
+-//DCP5_OUT_CLAMP_CONTROL_B_CB
+-#define DCP5_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT 0x0
+-#define DCP5_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT 0x10
+-#define DCP5_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK 0x00003FFFL
+-#define DCP5_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK 0x3FFF0000L
+-//DCP5_KEY_CONTROL
+-#define DCP5_KEY_CONTROL__KEY_MODE__SHIFT 0x1
+-#define DCP5_KEY_CONTROL__KEY_MODE_MASK 0x00000006L
+-//DCP5_KEY_RANGE_ALPHA
+-#define DCP5_KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT 0x0
+-#define DCP5_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT 0x10
+-#define DCP5_KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK 0x0000FFFFL
+-#define DCP5_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK 0xFFFF0000L
+-//DCP5_KEY_RANGE_RED
+-#define DCP5_KEY_RANGE_RED__KEY_RED_LOW__SHIFT 0x0
+-#define DCP5_KEY_RANGE_RED__KEY_RED_HIGH__SHIFT 0x10
+-#define DCP5_KEY_RANGE_RED__KEY_RED_LOW_MASK 0x0000FFFFL
+-#define DCP5_KEY_RANGE_RED__KEY_RED_HIGH_MASK 0xFFFF0000L
+-//DCP5_KEY_RANGE_GREEN
+-#define DCP5_KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT 0x0
+-#define DCP5_KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT 0x10
+-#define DCP5_KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK 0x0000FFFFL
+-#define DCP5_KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK 0xFFFF0000L
+-//DCP5_KEY_RANGE_BLUE
+-#define DCP5_KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT 0x0
+-#define DCP5_KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT 0x10
+-#define DCP5_KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK 0x0000FFFFL
+-#define DCP5_KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK 0xFFFF0000L
+-//DCP5_DEGAMMA_CONTROL
+-#define DCP5_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x0
+-#define DCP5_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT 0x8
+-#define DCP5_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0xc
+-#define DCP5_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x00000003L
+-#define DCP5_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK 0x00000300L
+-#define DCP5_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK 0x00003000L
+-//DCP5_GAMUT_REMAP_CONTROL
+-#define DCP5_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT 0x0
+-#define DCP5_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK 0x00000003L
+-//DCP5_GAMUT_REMAP_C11_C12
+-#define DCP5_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT 0x0
+-#define DCP5_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT 0x10
+-#define DCP5_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK 0x0000FFFFL
+-#define DCP5_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK 0xFFFF0000L
+-//DCP5_GAMUT_REMAP_C13_C14
+-#define DCP5_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT 0x0
+-#define DCP5_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT 0x10
+-#define DCP5_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK 0x0000FFFFL
+-#define DCP5_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK 0xFFFF0000L
+-//DCP5_GAMUT_REMAP_C21_C22
+-#define DCP5_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT 0x0
+-#define DCP5_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT 0x10
+-#define DCP5_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK 0x0000FFFFL
+-#define DCP5_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK 0xFFFF0000L
+-//DCP5_GAMUT_REMAP_C23_C24
+-#define DCP5_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT 0x0
+-#define DCP5_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT 0x10
+-#define DCP5_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK 0x0000FFFFL
+-#define DCP5_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK 0xFFFF0000L
+-//DCP5_GAMUT_REMAP_C31_C32
+-#define DCP5_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT 0x0
+-#define DCP5_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT 0x10
+-#define DCP5_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK 0x0000FFFFL
+-#define DCP5_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK 0xFFFF0000L
+-//DCP5_GAMUT_REMAP_C33_C34
+-#define DCP5_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT 0x0
+-#define DCP5_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT 0x10
+-#define DCP5_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK 0x0000FFFFL
+-#define DCP5_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK 0xFFFF0000L
+-//DCP5_DCP_SPATIAL_DITHER_CNTL
+-#define DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT 0x0
+-#define DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT 0x4
+-#define DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT 0x6
+-#define DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT 0x8
+-#define DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT 0x9
+-#define DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT 0xa
+-#define DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK 0x00000001L
+-#define DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK 0x00000030L
+-#define DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK 0x000000C0L
+-#define DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK 0x00000100L
+-#define DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK 0x00000200L
+-#define DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK 0x00000400L
+-//DCP5_DCP_RANDOM_SEEDS
+-#define DCP5_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT 0x0
+-#define DCP5_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT 0x8
+-#define DCP5_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT 0x10
+-#define DCP5_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK 0x000000FFL
+-#define DCP5_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK 0x0000FF00L
+-#define DCP5_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK 0x00FF0000L
+-//DCP5_DCP_FP_CONVERTED_FIELD
+-#define DCP5_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT 0x0
+-#define DCP5_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14
+-#define DCP5_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK 0x0003FFFFL
+-#define DCP5_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK 0x07F00000L
+-//DCP5_CUR_CONTROL
+-#define DCP5_CUR_CONTROL__CURSOR_EN__SHIFT 0x0
+-#define DCP5_CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT 0x4
+-#define DCP5_CUR_CONTROL__CURSOR_MODE__SHIFT 0x8
+-#define DCP5_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM__SHIFT 0xb
+-#define DCP5_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION__SHIFT 0xc
+-#define DCP5_CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x10
+-#define DCP5_CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT 0x14
+-#define DCP5_CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT 0x18
+-#define DCP5_CUR_CONTROL__CURSOR_EN_MASK 0x00000001L
+-#define DCP5_CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK 0x00000010L
+-#define DCP5_CUR_CONTROL__CURSOR_MODE_MASK 0x00000300L
+-#define DCP5_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM_MASK 0x00000800L
+-#define DCP5_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION_MASK 0x0000F000L
+-#define DCP5_CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00010000L
+-#define DCP5_CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK 0x00100000L
+-#define DCP5_CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK 0x07000000L
+-//DCP5_CUR_SURFACE_ADDRESS
+-#define DCP5_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0
+-#define DCP5_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+-//DCP5_CUR_SIZE
+-#define DCP5_CUR_SIZE__CURSOR_HEIGHT__SHIFT 0x0
+-#define DCP5_CUR_SIZE__CURSOR_WIDTH__SHIFT 0x10
+-#define DCP5_CUR_SIZE__CURSOR_HEIGHT_MASK 0x0000007FL
+-#define DCP5_CUR_SIZE__CURSOR_WIDTH_MASK 0x007F0000L
+-//DCP5_CUR_SURFACE_ADDRESS_HIGH
+-#define DCP5_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+-#define DCP5_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+-//DCP5_CUR_POSITION
+-#define DCP5_CUR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0
+-#define DCP5_CUR_POSITION__CURSOR_X_POSITION__SHIFT 0x10
+-#define DCP5_CUR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL
+-#define DCP5_CUR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L
+-//DCP5_CUR_HOT_SPOT
+-#define DCP5_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0
+-#define DCP5_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10
+-#define DCP5_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x0000007FL
+-#define DCP5_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x007F0000L
+-//DCP5_CUR_COLOR1
+-#define DCP5_CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT 0x0
+-#define DCP5_CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT 0x8
+-#define DCP5_CUR_COLOR1__CUR_COLOR1_RED__SHIFT 0x10
+-#define DCP5_CUR_COLOR1__CUR_COLOR1_BLUE_MASK 0x000000FFL
+-#define DCP5_CUR_COLOR1__CUR_COLOR1_GREEN_MASK 0x0000FF00L
+-#define DCP5_CUR_COLOR1__CUR_COLOR1_RED_MASK 0x00FF0000L
+-//DCP5_CUR_COLOR2
+-#define DCP5_CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT 0x0
+-#define DCP5_CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT 0x8
+-#define DCP5_CUR_COLOR2__CUR_COLOR2_RED__SHIFT 0x10
+-#define DCP5_CUR_COLOR2__CUR_COLOR2_BLUE_MASK 0x000000FFL
+-#define DCP5_CUR_COLOR2__CUR_COLOR2_GREEN_MASK 0x0000FF00L
+-#define DCP5_CUR_COLOR2__CUR_COLOR2_RED_MASK 0x00FF0000L
+-//DCP5_CUR_UPDATE
+-#define DCP5_CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT 0x0
+-#define DCP5_CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT 0x1
+-#define DCP5_CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT 0x10
+-#define DCP5_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+-#define DCP5_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE__SHIFT 0x19
+-#define DCP5_CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK 0x00000001L
+-#define DCP5_CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x00000002L
+-#define DCP5_CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK 0x00010000L
+-#define DCP5_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
+-#define DCP5_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE_MASK 0x06000000L
+-//DCP5_CUR_REQUEST_FILTER_CNTL
+-#define DCP5_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT 0x0
+-#define DCP5_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK 0x00000001L
+-//DCP5_CUR_STEREO_CONTROL
+-#define DCP5_CUR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0
+-#define DCP5_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4
+-#define DCP5_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x10
+-#define DCP5_CUR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L
+-#define DCP5_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x00003FF0L
+-#define DCP5_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0x03FF0000L
+-//DCP5_DC_LUT_RW_MODE
+-#define DCP5_DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT 0x0
+-#define DCP5_DC_LUT_RW_MODE__DC_LUT_ERROR__SHIFT 0x10
+-#define DCP5_DC_LUT_RW_MODE__DC_LUT_ERROR_RST__SHIFT 0x11
+-#define DCP5_DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK 0x00000001L
+-#define DCP5_DC_LUT_RW_MODE__DC_LUT_ERROR_MASK 0x00010000L
+-#define DCP5_DC_LUT_RW_MODE__DC_LUT_ERROR_RST_MASK 0x00020000L
+-//DCP5_DC_LUT_RW_INDEX
+-#define DCP5_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT 0x0
+-#define DCP5_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK 0x000000FFL
+-//DCP5_DC_LUT_SEQ_COLOR
+-#define DCP5_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT 0x0
+-#define DCP5_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK 0x0000FFFFL
+-//DCP5_DC_LUT_PWL_DATA
+-#define DCP5_DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT 0x0
+-#define DCP5_DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT 0x10
+-#define DCP5_DC_LUT_PWL_DATA__DC_LUT_BASE_MASK 0x0000FFFFL
+-#define DCP5_DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK 0xFFFF0000L
+-//DCP5_DC_LUT_30_COLOR
+-#define DCP5_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT 0x0
+-#define DCP5_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT 0xa
+-#define DCP5_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT 0x14
+-#define DCP5_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK 0x000003FFL
+-#define DCP5_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK 0x000FFC00L
+-#define DCP5_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK 0x3FF00000L
+-//DCP5_DC_LUT_VGA_ACCESS_ENABLE
+-#define DCP5_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT 0x0
+-#define DCP5_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK 0x00000001L
+-//DCP5_DC_LUT_WRITE_EN_MASK
+-#define DCP5_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT 0x0
+-#define DCP5_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK 0x00000007L
+-//DCP5_DC_LUT_AUTOFILL
+-#define DCP5_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT 0x0
+-#define DCP5_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT 0x1
+-#define DCP5_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK 0x00000001L
+-#define DCP5_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x00000002L
+-//DCP5_DC_LUT_CONTROL
+-#define DCP5_DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT 0x0
+-#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT 0x4
+-#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT 0x5
+-#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT 0x6
+-#define DCP5_DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT 0x8
+-#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT 0xc
+-#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT 0xd
+-#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT 0xe
+-#define DCP5_DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT 0x10
+-#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT 0x14
+-#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT 0x15
+-#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT 0x16
+-#define DCP5_DC_LUT_CONTROL__DC_LUT_INC_B_MASK 0x0000000FL
+-#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK 0x00000010L
+-#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK 0x00000020L
+-#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK 0x000000C0L
+-#define DCP5_DC_LUT_CONTROL__DC_LUT_INC_G_MASK 0x00000F00L
+-#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK 0x00001000L
+-#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK 0x00002000L
+-#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK 0x0000C000L
+-#define DCP5_DC_LUT_CONTROL__DC_LUT_INC_R_MASK 0x000F0000L
+-#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK 0x00100000L
+-#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK 0x00200000L
+-#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK 0x00C00000L
+-//DCP5_DC_LUT_BLACK_OFFSET_BLUE
+-#define DCP5_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0
+-#define DCP5_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK 0x0000FFFFL
+-//DCP5_DC_LUT_BLACK_OFFSET_GREEN
+-#define DCP5_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0
+-#define DCP5_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK 0x0000FFFFL
+-//DCP5_DC_LUT_BLACK_OFFSET_RED
+-#define DCP5_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT 0x0
+-#define DCP5_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK 0x0000FFFFL
+-//DCP5_DC_LUT_WHITE_OFFSET_BLUE
+-#define DCP5_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT 0x0
+-#define DCP5_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK 0x0000FFFFL
+-//DCP5_DC_LUT_WHITE_OFFSET_GREEN
+-#define DCP5_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT 0x0
+-#define DCP5_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK 0x0000FFFFL
+-//DCP5_DC_LUT_WHITE_OFFSET_RED
+-#define DCP5_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT 0x0
+-#define DCP5_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK 0x0000FFFFL
+-//DCP5_DCP_CRC_CONTROL
+-#define DCP5_DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT 0x0
+-#define DCP5_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x2
+-#define DCP5_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT 0x8
+-#define DCP5_DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK 0x00000001L
+-#define DCP5_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK 0x0000001CL
+-#define DCP5_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK 0x00000300L
+-//DCP5_DCP_CRC_MASK
+-#define DCP5_DCP_CRC_MASK__DCP_CRC_MASK__SHIFT 0x0
+-#define DCP5_DCP_CRC_MASK__DCP_CRC_MASK_MASK 0xFFFFFFFFL
+-//DCP5_DCP_CRC_CURRENT
+-#define DCP5_DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT 0x0
+-#define DCP5_DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK 0xFFFFFFFFL
+-//DCP5_DVMM_PTE_CONTROL
+-#define DCP5_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT 0x0
+-#define DCP5_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT 0x1
+-#define DCP5_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT 0x5
+-#define DCP5_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT 0x9
+-#define DCP5_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT 0x14
+-#define DCP5_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT 0x15
+-#define DCP5_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK 0x00000001L
+-#define DCP5_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK 0x0000001EL
+-#define DCP5_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK 0x000001E0L
+-#define DCP5_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK 0x0007FE00L
+-#define DCP5_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK 0x00100000L
+-#define DCP5_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK 0x00200000L
+-//DCP5_DCP_CRC_LAST
+-#define DCP5_DCP_CRC_LAST__DCP_CRC_LAST__SHIFT 0x0
+-#define DCP5_DCP_CRC_LAST__DCP_CRC_LAST_MASK 0xFFFFFFFFL
+-//DCP5_DVMM_PTE_ARB_CONTROL
+-#define DCP5_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT 0x0
+-#define DCP5_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT 0x8
+-#define DCP5_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK 0x0000003FL
+-#define DCP5_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK 0x0000FF00L
+-//DCP5_GRPH_FLIP_RATE_CNTL
+-#define DCP5_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT 0x0
+-#define DCP5_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT 0x3
+-#define DCP5_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK 0x00000007L
+-#define DCP5_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK 0x00000008L
+-//DCP5_DCP_GSL_CONTROL
+-#define DCP5_DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT 0x0
+-#define DCP5_DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT 0x1
+-#define DCP5_DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x2
+-#define DCP5_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT 0x4
+-#define DCP5_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT 0x14
+-#define DCP5_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP__SHIFT 0x15
+-#define DCP5_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN__SHIFT 0x17
+-#define DCP5_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT 0x18
+-#define DCP5_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC__SHIFT 0x1a
+-#define DCP5_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT 0x1b
+-#define DCP5_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT 0x1c
+-#define DCP5_DCP_GSL_CONTROL__DCP_GSL0_EN_MASK 0x00000001L
+-#define DCP5_DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x00000002L
+-#define DCP5_DCP_GSL_CONTROL__DCP_GSL2_EN_MASK 0x00000004L
+-#define DCP5_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK 0x000FFFF0L
+-#define DCP5_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK 0x00100000L
+-#define DCP5_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_MASK 0x00600000L
+-#define DCP5_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_MASK 0x00800000L
+-#define DCP5_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK 0x03000000L
+-#define DCP5_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_MASK 0x04000000L
+-#define DCP5_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK 0x08000000L
+-#define DCP5_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK 0xF0000000L
+-//DCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK
+-#define DCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT 0x0
+-#define DCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT 0x4
+-#define DCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK 0x0000000FL
+-#define DCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK 0x000001F0L
+-//DCP5_GRPH_STEREOSYNC_FLIP
+-#define DCP5_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0
+-#define DCP5_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x8
+-#define DCP5_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10
+-#define DCP5_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11
+-#define DCP5_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c
+-#define DCP5_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x00000001L
+-#define DCP5_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x00000300L
+-#define DCP5_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x00010000L
+-#define DCP5_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x00020000L
+-#define DCP5_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000L
+-//DCP5_HW_ROTATION
+-#define DCP5_HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT 0x0
+-#define DCP5_HW_ROTATION__GRPH_ROTATION_ANGLE_MASK 0x00000007L
+-//DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL
+-#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT 0x0
+-#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT 0x1
+-#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT 0x4
+-#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK 0x00000001L
+-#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK 0x00000002L
+-#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK 0x0001FFF0L
+-//DCP5_REGAMMA_CONTROL
+-#define DCP5_REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT 0x0
+-#define DCP5_REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK 0x00000007L
+-//DCP5_REGAMMA_LUT_INDEX
+-#define DCP5_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x0
+-#define DCP5_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK 0x000001FFL
+-//DCP5_REGAMMA_LUT_DATA
+-#define DCP5_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT 0x0
+-#define DCP5_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK 0x0007FFFFL
+-//DCP5_REGAMMA_LUT_WRITE_EN_MASK
+-#define DCP5_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x0
+-#define DCP5_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x00000007L
+-//DCP5_REGAMMA_CNTLA_START_CNTL
+-#define DCP5_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x0
+-#define DCP5_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14
+-#define DCP5_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK 0x0003FFFFL
+-#define DCP5_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
+-//DCP5_REGAMMA_CNTLA_SLOPE_CNTL
+-#define DCP5_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+-#define DCP5_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
+-//DCP5_REGAMMA_CNTLA_END_CNTL1
+-#define DCP5_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x0
+-#define DCP5_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK 0x0000FFFFL
+-//DCP5_REGAMMA_CNTLA_END_CNTL2
+-#define DCP5_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0
+-#define DCP5_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10
+-#define DCP5_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
+-#define DCP5_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xFFFF0000L
+-//DCP5_REGAMMA_CNTLA_REGION_0_1
+-#define DCP5_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+-#define DCP5_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP5_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+-#define DCP5_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP5_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP5_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP5_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP5_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP5_REGAMMA_CNTLA_REGION_2_3
+-#define DCP5_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+-#define DCP5_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP5_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+-#define DCP5_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP5_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP5_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP5_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP5_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP5_REGAMMA_CNTLA_REGION_4_5
+-#define DCP5_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+-#define DCP5_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP5_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+-#define DCP5_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP5_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP5_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP5_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP5_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP5_REGAMMA_CNTLA_REGION_6_7
+-#define DCP5_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+-#define DCP5_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP5_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+-#define DCP5_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP5_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP5_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP5_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP5_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP5_REGAMMA_CNTLA_REGION_8_9
+-#define DCP5_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+-#define DCP5_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP5_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+-#define DCP5_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP5_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP5_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP5_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP5_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP5_REGAMMA_CNTLA_REGION_10_11
+-#define DCP5_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+-#define DCP5_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP5_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+-#define DCP5_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP5_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP5_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP5_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP5_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP5_REGAMMA_CNTLA_REGION_12_13
+-#define DCP5_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+-#define DCP5_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP5_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+-#define DCP5_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP5_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP5_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP5_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP5_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP5_REGAMMA_CNTLA_REGION_14_15
+-#define DCP5_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+-#define DCP5_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP5_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+-#define DCP5_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP5_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP5_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP5_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP5_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP5_REGAMMA_CNTLB_START_CNTL
+-#define DCP5_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x0
+-#define DCP5_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14
+-#define DCP5_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK 0x0003FFFFL
+-#define DCP5_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
+-//DCP5_REGAMMA_CNTLB_SLOPE_CNTL
+-#define DCP5_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+-#define DCP5_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
+-//DCP5_REGAMMA_CNTLB_END_CNTL1
+-#define DCP5_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x0
+-#define DCP5_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK 0x0000FFFFL
+-//DCP5_REGAMMA_CNTLB_END_CNTL2
+-#define DCP5_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0
+-#define DCP5_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10
+-#define DCP5_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
+-#define DCP5_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xFFFF0000L
+-//DCP5_REGAMMA_CNTLB_REGION_0_1
+-#define DCP5_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+-#define DCP5_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP5_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+-#define DCP5_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP5_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP5_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP5_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP5_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP5_REGAMMA_CNTLB_REGION_2_3
+-#define DCP5_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+-#define DCP5_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP5_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+-#define DCP5_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP5_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP5_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP5_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP5_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP5_REGAMMA_CNTLB_REGION_4_5
+-#define DCP5_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+-#define DCP5_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP5_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+-#define DCP5_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP5_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP5_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP5_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP5_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP5_REGAMMA_CNTLB_REGION_6_7
+-#define DCP5_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+-#define DCP5_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP5_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+-#define DCP5_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP5_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP5_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP5_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP5_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP5_REGAMMA_CNTLB_REGION_8_9
+-#define DCP5_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+-#define DCP5_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP5_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+-#define DCP5_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP5_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP5_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP5_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP5_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP5_REGAMMA_CNTLB_REGION_10_11
+-#define DCP5_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+-#define DCP5_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP5_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+-#define DCP5_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP5_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP5_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP5_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP5_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP5_REGAMMA_CNTLB_REGION_12_13
+-#define DCP5_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+-#define DCP5_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP5_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+-#define DCP5_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP5_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP5_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP5_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP5_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP5_REGAMMA_CNTLB_REGION_14_15
+-#define DCP5_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+-#define DCP5_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+-#define DCP5_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+-#define DCP5_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+-#define DCP5_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+-#define DCP5_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+-#define DCP5_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+-#define DCP5_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+-//DCP5_ALPHA_CONTROL
+-#define DCP5_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT 0x0
+-#define DCP5_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT 0x1
+-#define DCP5_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK 0x00000001L
+-#define DCP5_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK 0x00000002L
+-//DCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS
+-#define DCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT 0x8
+-#define DCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+-//DCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH
+-#define DCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+-#define DCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+-//DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS
+-#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT 0x0
+-#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT 0x18
+-#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT 0x19
+-#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT 0x1a
+-#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT 0x1c
+-#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT 0x1d
+-#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT 0x1e
+-#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK 0x000FFFFFL
+-#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK 0x01000000L
+-#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK 0x02000000L
+-#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK 0x04000000L
+-#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK 0x10000000L
+-#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK 0x20000000L
+-#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK 0x40000000L
+-//DCP5_GRPH_XDMA_FLIP_TIMEOUT
+-#define DCP5_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS__SHIFT 0x0
+-#define DCP5_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK__SHIFT 0x1
+-#define DCP5_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK__SHIFT 0x2
+-#define DCP5_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS_MASK 0x00000001L
+-#define DCP5_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK_MASK 0x00000002L
+-#define DCP5_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK_MASK 0x00000004L
+-//DCP5_GRPH_XDMA_FLIP_AVG_DELAY
+-#define DCP5_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY__SHIFT 0x0
+-#define DCP5_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD__SHIFT 0x10
+-#define DCP5_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY_MASK 0x0000FFFFL
+-#define DCP5_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD_MASK 0x00FF0000L
+-//DCP5_GRPH_SURFACE_COUNTER_CONTROL
+-#define DCP5_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN__SHIFT 0x0
+-#define DCP5_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT__SHIFT 0x1
+-#define DCP5_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED__SHIFT 0x9
+-#define DCP5_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN_MASK 0x00000001L
+-#define DCP5_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT_MASK 0x0000001EL
+-#define DCP5_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_MASK 0x00000200L
+-//DCP5_GRPH_SURFACE_COUNTER_OUTPUT
+-#define DCP5_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN__SHIFT 0x0
+-#define DCP5_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX__SHIFT 0x10
+-#define DCP5_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN_MASK 0x0000FFFFL
+-#define DCP5_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX_MASK 0xFFFF0000L
+-
+-
+-// addressBlock: dce_dc_lb5_dispdec
+-//LB5_LB_DATA_FORMAT
+-#define LB5_LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0
+-#define LB5_LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2
+-#define LB5_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3
+-#define LB5_LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4
+-#define LB5_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5
+-#define LB5_LB_DATA_FORMAT__PREFILL_EN__SHIFT 0x8
+-#define LB5_LB_DATA_FORMAT__PREFETCH__SHIFT 0xc
+-#define LB5_LB_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18
+-#define LB5_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f
+-#define LB5_LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x00000003L
+-#define LB5_LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x00000004L
+-#define LB5_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000008L
+-#define LB5_LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x00000010L
+-#define LB5_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x00000020L
+-#define LB5_LB_DATA_FORMAT__PREFILL_EN_MASK 0x00000100L
+-#define LB5_LB_DATA_FORMAT__PREFETCH_MASK 0x00001000L
+-#define LB5_LB_DATA_FORMAT__REQUEST_MODE_MASK 0x01000000L
+-#define LB5_LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000L
+-//LB5_LB_MEMORY_CTRL
+-#define LB5_LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0
+-#define LB5_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
+-#define LB5_LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14
+-#define LB5_LB_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0x00001FFFL
+-#define LB5_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x000F0000L
+-#define LB5_LB_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x00300000L
+-//LB5_LB_MEMORY_SIZE_STATUS
+-#define LB5_LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0
+-#define LB5_LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0x00001FFFL
+-//LB5_LB_DESKTOP_HEIGHT
+-#define LB5_LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0
+-#define LB5_LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x00007FFFL
+-//LB5_LB_VLINE_START_END
+-#define LB5_LB_VLINE_START_END__VLINE_START__SHIFT 0x0
+-#define LB5_LB_VLINE_START_END__VLINE_END__SHIFT 0x10
+-#define LB5_LB_VLINE_START_END__VLINE_INV__SHIFT 0x1f
+-#define LB5_LB_VLINE_START_END__VLINE_START_MASK 0x00003FFFL
+-#define LB5_LB_VLINE_START_END__VLINE_END_MASK 0x7FFF0000L
+-#define LB5_LB_VLINE_START_END__VLINE_INV_MASK 0x80000000L
+-//LB5_LB_VLINE2_START_END
+-#define LB5_LB_VLINE2_START_END__VLINE2_START__SHIFT 0x0
+-#define LB5_LB_VLINE2_START_END__VLINE2_END__SHIFT 0x10
+-#define LB5_LB_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f
+-#define LB5_LB_VLINE2_START_END__VLINE2_START_MASK 0x00003FFFL
+-#define LB5_LB_VLINE2_START_END__VLINE2_END_MASK 0x7FFF0000L
+-#define LB5_LB_VLINE2_START_END__VLINE2_INV_MASK 0x80000000L
+-//LB5_LB_V_COUNTER
+-#define LB5_LB_V_COUNTER__V_COUNTER__SHIFT 0x0
+-#define LB5_LB_V_COUNTER__V_COUNTER_MASK 0x00007FFFL
+-//LB5_LB_SNAPSHOT_V_COUNTER
+-#define LB5_LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0
+-#define LB5_LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x00007FFFL
+-//LB5_LB_INTERRUPT_MASK
+-#define LB5_LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0
+-#define LB5_LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4
+-#define LB5_LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8
+-#define LB5_LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x00000001L
+-#define LB5_LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x00000010L
+-#define LB5_LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x00000100L
+-//LB5_LB_VLINE_STATUS
+-#define LB5_LB_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0
+-#define LB5_LB_VLINE_STATUS__VLINE_ACK__SHIFT 0x4
+-#define LB5_LB_VLINE_STATUS__VLINE_STAT__SHIFT 0xc
+-#define LB5_LB_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10
+-#define LB5_LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11
+-#define LB5_LB_VLINE_STATUS__VLINE_OCCURRED_MASK 0x00000001L
+-#define LB5_LB_VLINE_STATUS__VLINE_ACK_MASK 0x00000010L
+-#define LB5_LB_VLINE_STATUS__VLINE_STAT_MASK 0x00001000L
+-#define LB5_LB_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x00010000L
+-#define LB5_LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x00020000L
+-//LB5_LB_VLINE2_STATUS
+-#define LB5_LB_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0
+-#define LB5_LB_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4
+-#define LB5_LB_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc
+-#define LB5_LB_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10
+-#define LB5_LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11
+-#define LB5_LB_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x00000001L
+-#define LB5_LB_VLINE2_STATUS__VLINE2_ACK_MASK 0x00000010L
+-#define LB5_LB_VLINE2_STATUS__VLINE2_STAT_MASK 0x00001000L
+-#define LB5_LB_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x00010000L
+-#define LB5_LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x00020000L
+-//LB5_LB_VBLANK_STATUS
+-#define LB5_LB_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0
+-#define LB5_LB_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4
+-#define LB5_LB_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc
+-#define LB5_LB_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10
+-#define LB5_LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11
+-#define LB5_LB_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x00000001L
+-#define LB5_LB_VBLANK_STATUS__VBLANK_ACK_MASK 0x00000010L
+-#define LB5_LB_VBLANK_STATUS__VBLANK_STAT_MASK 0x00001000L
+-#define LB5_LB_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x00010000L
+-#define LB5_LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x00020000L
+-//LB5_LB_SYNC_RESET_SEL
+-#define LB5_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0
+-#define LB5_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4
+-#define LB5_LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8
+-#define LB5_LB_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16
+-#define LB5_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x00000003L
+-#define LB5_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x00000010L
+-#define LB5_LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0x0000FF00L
+-#define LB5_LB_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0x00C00000L
+-//LB5_LB_BLACK_KEYER_R_CR
+-#define LB5_LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4
+-#define LB5_LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0x0000FFF0L
+-//LB5_LB_BLACK_KEYER_G_Y
+-#define LB5_LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4
+-#define LB5_LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0x0000FFF0L
+-//LB5_LB_BLACK_KEYER_B_CB
+-#define LB5_LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4
+-#define LB5_LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0x0000FFF0L
+-//LB5_LB_KEYER_COLOR_CTRL
+-#define LB5_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0
+-#define LB5_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8
+-#define LB5_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x00000001L
+-#define LB5_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x00000100L
+-//LB5_LB_KEYER_COLOR_R_CR
+-#define LB5_LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4
+-#define LB5_LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0x0000FFF0L
+-//LB5_LB_KEYER_COLOR_G_Y
+-#define LB5_LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4
+-#define LB5_LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0x0000FFF0L
+-//LB5_LB_KEYER_COLOR_B_CB
+-#define LB5_LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4
+-#define LB5_LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0x0000FFF0L
+-//LB5_LB_KEYER_COLOR_REP_R_CR
+-#define LB5_LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4
+-#define LB5_LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0x0000FFF0L
+-//LB5_LB_KEYER_COLOR_REP_G_Y
+-#define LB5_LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4
+-#define LB5_LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0x0000FFF0L
+-//LB5_LB_KEYER_COLOR_REP_B_CB
+-#define LB5_LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4
+-#define LB5_LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0x0000FFF0L
+-//LB5_LB_BUFFER_LEVEL_STATUS
+-#define LB5_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0
+-#define LB5_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa
+-#define LB5_LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10
+-#define LB5_LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c
+-#define LB5_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x0000003FL
+-#define LB5_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0x0000FC00L
+-#define LB5_LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0x0FFF0000L
+-#define LB5_LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xF0000000L
+-//LB5_LB_BUFFER_URGENCY_CTRL
+-#define LB5_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0
+-#define LB5_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10
+-#define LB5_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0x00000FFFL
+-#define LB5_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0x0FFF0000L
+-//LB5_LB_BUFFER_URGENCY_STATUS
+-#define LB5_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0
+-#define LB5_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10
+-#define LB5_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0x00000FFFL
+-#define LB5_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x00010000L
+-//LB5_LB_BUFFER_STATUS
+-#define LB5_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0
+-#define LB5_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4
+-#define LB5_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8
+-#define LB5_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc
+-#define LB5_LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10
+-#define LB5_LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14
+-#define LB5_LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18
+-#define LB5_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0x0000000FL
+-#define LB5_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x00000010L
+-#define LB5_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x00000100L
+-#define LB5_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x00001000L
+-#define LB5_LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x00010000L
+-#define LB5_LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x00100000L
+-#define LB5_LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x01000000L
+-//LB5_LB_NO_OUTSTANDING_REQ_STATUS
+-#define LB5_LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0
+-#define LB5_LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x00000001L
+-//LB5_MVP_AFR_FLIP_MODE
+-#define LB5_MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT 0x0
+-#define LB5_MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK 0x00000003L
+-//LB5_MVP_AFR_FLIP_FIFO_CNTL
+-#define LB5_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT 0x0
+-#define LB5_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT 0x4
+-#define LB5_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT 0x8
+-#define LB5_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT 0xc
+-#define LB5_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK 0x0000000FL
+-#define LB5_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK 0x00000010L
+-#define LB5_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK 0x00000100L
+-#define LB5_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK 0x00001000L
+-//LB5_MVP_FLIP_LINE_NUM_INSERT
+-#define LB5_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT 0x0
+-#define LB5_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT 0x8
+-#define LB5_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT 0x18
+-#define LB5_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT 0x1e
+-#define LB5_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK 0x00000003L
+-#define LB5_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK 0x007FFF00L
+-#define LB5_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK 0x3F000000L
+-#define LB5_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK 0x40000000L
+-//LB5_DC_MVP_LB_CONTROL
+-#define LB5_DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT 0x0
+-#define LB5_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT 0x8
+-#define LB5_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT 0xc
+-#define LB5_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT 0x10
+-#define LB5_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT 0x14
+-#define LB5_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT 0x1c
+-#define LB5_DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT 0x1f
+-#define LB5_DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK 0x00000003L
+-#define LB5_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK 0x00000100L
+-#define LB5_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK 0x00001000L
+-#define LB5_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK 0x00010000L
+-#define LB5_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK 0x00100000L
+-#define LB5_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK 0x10000000L
+-#define LB5_DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK 0x80000000L
+-
+-
+-// addressBlock: dce_dc_dcfe5_dispdec
+-//DCFE5_DCFE_CLOCK_CONTROL
+-#define DCFE5_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x4
+-#define DCFE5_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x8
+-#define DCFE5_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0xc
+-#define DCFE5_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE__SHIFT 0xf
+-#define DCFE5_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE__SHIFT 0x11
+-#define DCFE5_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL__SHIFT 0x18
+-#define DCFE5_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE__SHIFT 0x1f
+-#define DCFE5_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x00000010L
+-#define DCFE5_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE_MASK 0x00000100L
+-#define DCFE5_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE_MASK 0x00001000L
+-#define DCFE5_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE_MASK 0x00008000L
+-#define DCFE5_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE_MASK 0x00020000L
+-#define DCFE5_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL_MASK 0x1F000000L
+-#define DCFE5_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE_MASK 0x80000000L
+-//DCFE5_DCFE_SOFT_RESET
+-#define DCFE5_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET__SHIFT 0x0
+-#define DCFE5_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET__SHIFT 0x1
+-#define DCFE5_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET__SHIFT 0x2
+-#define DCFE5_DCFE_SOFT_RESET__SCL_SOFT_RESET__SHIFT 0x3
+-#define DCFE5_DCFE_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4
+-#define DCFE5_DCFE_SOFT_RESET__PSCL_SOFT_RESET__SHIFT 0x5
+-#define DCFE5_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET_MASK 0x00000001L
+-#define DCFE5_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET_MASK 0x00000002L
+-#define DCFE5_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET_MASK 0x00000004L
+-#define DCFE5_DCFE_SOFT_RESET__SCL_SOFT_RESET_MASK 0x00000008L
+-#define DCFE5_DCFE_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x00000010L
+-#define DCFE5_DCFE_SOFT_RESET__PSCL_SOFT_RESET_MASK 0x00000020L
+-//DCFE5_DCFE_MEM_PWR_CTRL
+-#define DCFE5_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE__SHIFT 0x0
+-#define DCFE5_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS__SHIFT 0x2
+-#define DCFE5_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE__SHIFT 0x3
+-#define DCFE5_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS__SHIFT 0x5
+-#define DCFE5_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE__SHIFT 0x6
+-#define DCFE5_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS__SHIFT 0x8
+-#define DCFE5_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE__SHIFT 0x9
+-#define DCFE5_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS__SHIFT 0xb
+-#define DCFE5_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE__SHIFT 0xc
+-#define DCFE5_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS__SHIFT 0xe
+-#define DCFE5_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE__SHIFT 0xf
+-#define DCFE5_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS__SHIFT 0x11
+-#define DCFE5_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE__SHIFT 0x12
+-#define DCFE5_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS__SHIFT 0x14
+-#define DCFE5_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE__SHIFT 0x15
+-#define DCFE5_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS__SHIFT 0x17
+-#define DCFE5_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE__SHIFT 0x18
+-#define DCFE5_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS__SHIFT 0x1a
+-#define DCFE5_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE__SHIFT 0x1b
+-#define DCFE5_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS__SHIFT 0x1d
+-#define DCFE5_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE_MASK 0x00000003L
+-#define DCFE5_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS_MASK 0x00000004L
+-#define DCFE5_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE_MASK 0x00000018L
+-#define DCFE5_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS_MASK 0x00000020L
+-#define DCFE5_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE_MASK 0x000000C0L
+-#define DCFE5_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS_MASK 0x00000100L
+-#define DCFE5_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE_MASK 0x00000600L
+-#define DCFE5_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS_MASK 0x00000800L
+-#define DCFE5_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE_MASK 0x00003000L
+-#define DCFE5_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS_MASK 0x00004000L
+-#define DCFE5_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE_MASK 0x00018000L
+-#define DCFE5_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK 0x00020000L
+-#define DCFE5_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE_MASK 0x000C0000L
+-#define DCFE5_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS_MASK 0x00100000L
+-#define DCFE5_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE_MASK 0x00600000L
+-#define DCFE5_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS_MASK 0x00800000L
+-#define DCFE5_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE_MASK 0x03000000L
+-#define DCFE5_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS_MASK 0x04000000L
+-#define DCFE5_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE_MASK 0x18000000L
+-#define DCFE5_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS_MASK 0x20000000L
+-//DCFE5_DCFE_MEM_PWR_CTRL2
+-#define DCFE5_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL__SHIFT 0x0
+-#define DCFE5_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2
+-#define DCFE5_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4
+-#define DCFE5_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL__SHIFT 0x6
+-#define DCFE5_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL__SHIFT 0x8
+-#define DCFE5_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL__SHIFT 0xa
+-#define DCFE5_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL__SHIFT 0xc
+-#define DCFE5_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL__SHIFT 0xe
+-#define DCFE5_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE__SHIFT 0x10
+-#define DCFE5_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS__SHIFT 0x12
+-#define DCFE5_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE__SHIFT 0x15
+-#define DCFE5_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS__SHIFT 0x17
+-#define DCFE5_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL_MASK 0x00000003L
+-#define DCFE5_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL_MASK 0x0000000CL
+-#define DCFE5_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL_MASK 0x00000030L
+-#define DCFE5_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL_MASK 0x000000C0L
+-#define DCFE5_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL_MASK 0x00000300L
+-#define DCFE5_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL_MASK 0x00000C00L
+-#define DCFE5_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL_MASK 0x00003000L
+-#define DCFE5_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL_MASK 0x0000C000L
+-#define DCFE5_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE_MASK 0x00030000L
+-#define DCFE5_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS_MASK 0x00040000L
+-#define DCFE5_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE_MASK 0x00600000L
+-#define DCFE5_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS_MASK 0x00800000L
+-//DCFE5_DCFE_MEM_PWR_STATUS
+-#define DCFE5_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE__SHIFT 0x0
+-#define DCFE5_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE__SHIFT 0x2
+-#define DCFE5_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE__SHIFT 0x4
+-#define DCFE5_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x6
+-#define DCFE5_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE__SHIFT 0x8
+-#define DCFE5_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE__SHIFT 0xa
+-#define DCFE5_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE__SHIFT 0xc
+-#define DCFE5_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE__SHIFT 0xe
+-#define DCFE5_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT 0x10
+-#define DCFE5_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE__SHIFT 0x12
+-#define DCFE5_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE__SHIFT 0x14
+-#define DCFE5_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE__SHIFT 0x16
+-#define DCFE5_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK 0x00000003L
+-#define DCFE5_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE_MASK 0x0000000CL
+-#define DCFE5_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE_MASK 0x00000030L
+-#define DCFE5_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE_MASK 0x000000C0L
+-#define DCFE5_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE_MASK 0x00000300L
+-#define DCFE5_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE_MASK 0x00000C00L
+-#define DCFE5_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE_MASK 0x00003000L
+-#define DCFE5_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE_MASK 0x0000C000L
+-#define DCFE5_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE_MASK 0x00030000L
+-#define DCFE5_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK 0x000C0000L
+-#define DCFE5_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE_MASK 0x00300000L
+-#define DCFE5_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE_MASK 0x00C00000L
+-//DCFE5_DCFE_MISC
+-#define DCFE5_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN__SHIFT 0x0
+-#define DCFE5_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN_MASK 0x00000001L
+-//DCFE5_DCFE_FLUSH
+-#define DCFE5_DCFE_FLUSH__FLUSH_OCCURED__SHIFT 0x0
+-#define DCFE5_DCFE_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT 0x1
+-#define DCFE5_DCFE_FLUSH__FLUSH_DEEP__SHIFT 0x2
+-#define DCFE5_DCFE_FLUSH__CLEAR_FLUSH_DEEP__SHIFT 0x3
+-#define DCFE5_DCFE_FLUSH__ALL_MC_REQ_RET__SHIFT 0x4
+-#define DCFE5_DCFE_FLUSH__FLUSH_OCCURED_MASK 0x00000001L
+-#define DCFE5_DCFE_FLUSH__CLEAR_FLUSH_OCCURED_MASK 0x00000002L
+-#define DCFE5_DCFE_FLUSH__FLUSH_DEEP_MASK 0x00000004L
+-#define DCFE5_DCFE_FLUSH__CLEAR_FLUSH_DEEP_MASK 0x00000008L
+-#define DCFE5_DCFE_FLUSH__ALL_MC_REQ_RET_MASK 0x00000010L
+-
+-
+-// addressBlock: dce_dc_dc_perfmon8_dispdec
+-//DC_PERFMON8_PERFCOUNTER_CNTL
+-#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+-#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+-#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+-#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+-#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+-#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
+-#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+-#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+-#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+-#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+-#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+-#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
+-#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+-#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+-#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+-#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+-#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+-#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+-#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
+-#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+-#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+-#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+-#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+-#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+-#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
+-#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+-//DC_PERFMON8_PERFCOUNTER_CNTL2
+-#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+-#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+-#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+-#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+-#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+-#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+-#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+-#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+-//DC_PERFMON8_PERFCOUNTER_STATE
+-#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+-#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+-#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+-#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+-#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+-#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+-#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+-#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+-#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+-#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+-#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+-#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+-#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+-#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+-#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+-#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+-#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+-#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+-#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+-#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+-#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+-#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+-#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+-#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+-#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+-#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+-#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+-#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+-#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+-#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+-#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+-#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+-//DC_PERFMON8_PERFMON_CNTL
+-#define DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+-#define DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+-#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+-#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+-#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+-#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+-#define DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+-#define DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+-#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+-#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+-#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+-#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+-//DC_PERFMON8_PERFMON_CNTL2
+-#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+-#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+-#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+-#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+-#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+-#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+-#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+-#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+-//DC_PERFMON8_PERFMON_CVALUE_INT_MISC
+-#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+-#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+-#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+-#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+-#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+-#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+-#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+-#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+-#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+-#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+-#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+-#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+-#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+-#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+-#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+-#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+-#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+-#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+-#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+-#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+-#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+-#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+-#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+-#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+-#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+-#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+-#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+-#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+-#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+-#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+-#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+-#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+-#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+-#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+-//DC_PERFMON8_PERFMON_CVALUE_LOW
+-#define DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+-#define DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+-//DC_PERFMON8_PERFMON_HI
+-#define DC_PERFMON8_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+-#define DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+-#define DC_PERFMON8_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+-#define DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+-//DC_PERFMON8_PERFMON_LOW
+-#define DC_PERFMON8_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+-#define DC_PERFMON8_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dmif_pg5_dispdec
+-//DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1
+-#define DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
+-#define DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
+-#define DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0x0000FFFFL
+-#define DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xFFFF0000L
+-//DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2
+-#define DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
+-#define DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
+-#define DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0x0000FFFFL
+-#define DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xFFFF0000L
+-//DMIF_PG5_DPG_WATERMARK_MASK_CONTROL
+-#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
+-#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x4
+-#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
+-#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK__SHIFT 0xc
+-#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0xf
+-#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x12
+-#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL__SHIFT 0x13
+-#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL__SHIFT 0x14
+-#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000007L
+-#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000070L
+-#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x00000700L
+-#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK_MASK 0x00007000L
+-#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00038000L
+-#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x00040000L
+-#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL_MASK 0x00080000L
+-#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL_MASK 0x3FF00000L
+-//DMIF_PG5_DPG_PIPE_URGENCY_CONTROL
+-#define DMIF_PG5_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
+-#define DMIF_PG5_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
+-#define DMIF_PG5_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0x0000FFFFL
+-#define DMIF_PG5_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xFFFF0000L
+-//DMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL
+-#define DMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK__SHIFT 0x0
+-#define DMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK__SHIFT 0x10
+-#define DMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK_MASK 0x0000FFFFL
+-#define DMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK_MASK 0xFFFF0000L
+-//DMIF_PG5_DPG_PIPE_STUTTER_CONTROL
+-#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
+-#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
+-#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
+-#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
+-#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
+-#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
+-#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
+-#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH__SHIFT 0x10
+-#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x14
+-#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x15
+-#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x16
+-#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x17
+-#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0x1a
+-#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0x1b
+-#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L
+-#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L
+-#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x00000020L
+-#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x00000040L
+-#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x00000080L
+-#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x00000400L
+-#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x00000800L
+-#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH_MASK 0x00010000L
+-#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x00100000L
+-#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x00200000L
+-#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x00400000L
+-#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x00800000L
+-#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x04000000L
+-#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x08000000L
+-//DMIF_PG5_DPG_PIPE_STUTTER_CONTROL2
+-#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x0
+-#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK__SHIFT 0x10
+-#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0x0000FFFFL
+-#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK 0xFFFF0000L
+-//DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL
+-#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE__SHIFT 0x0
+-#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE__SHIFT 0x1
+-#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
+-#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
+-#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
+-#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
+-#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK__SHIFT 0xf
+-#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE_MASK 0x00000001L
+-#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE_MASK 0x00000002L
+-#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L
+-#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x00000100L
+-#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON_MASK 0x00000200L
+-#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT_MASK 0x00000400L
+-#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK_MASK 0xFFFF8000L
+-//DMIF_PG5_DPG_REPEATER_PROGRAM
+-#define DMIF_PG5_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
+-#define DMIF_PG5_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
+-#define DMIF_PG5_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x00000007L
+-#define DMIF_PG5_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x00000070L
+-//DMIF_PG5_DPG_CHK_PRE_PROC_CNTL
+-#define DMIF_PG5_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0
+-#define DMIF_PG5_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x00000001L
+-//DMIF_PG5_DPG_DVMM_STATUS
+-#define DMIF_PG5_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED__SHIFT 0x0
+-#define DMIF_PG5_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED__SHIFT 0x1
+-#define DMIF_PG5_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR__SHIFT 0x4
+-#define DMIF_PG5_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR__SHIFT 0x5
+-#define DMIF_PG5_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_MASK 0x00000001L
+-#define DMIF_PG5_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_MASK 0x00000002L
+-#define DMIF_PG5_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR_MASK 0x00000010L
+-#define DMIF_PG5_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR_MASK 0x00000020L
+-
+-
+-// addressBlock: dce_dc_scl5_dispdec
+-//SCL5_SCL_COEF_RAM_SELECT
+-#define SCL5_SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0
+-#define SCL5_SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8
+-#define SCL5_SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10
+-#define SCL5_SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x0000000FL
+-#define SCL5_SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x00000F00L
+-#define SCL5_SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x00070000L
+-//SCL5_SCL_COEF_RAM_TAP_DATA
+-#define SCL5_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0
+-#define SCL5_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
+-#define SCL5_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10
+-#define SCL5_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
+-#define SCL5_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL
+-#define SCL5_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L
+-#define SCL5_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L
+-#define SCL5_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L
+-//SCL5_SCL_MODE
+-#define SCL5_SCL_MODE__SCL_MODE__SHIFT 0x0
+-#define SCL5_SCL_MODE__SCL_PSCL_EN__SHIFT 0x4
+-#define SCL5_SCL_MODE__SCL_MODE_MASK 0x00000003L
+-#define SCL5_SCL_MODE__SCL_PSCL_EN_MASK 0x00000010L
+-//SCL5_SCL_TAP_CONTROL
+-#define SCL5_SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0
+-#define SCL5_SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x8
+-#define SCL5_SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x00000007L
+-#define SCL5_SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0x00000F00L
+-//SCL5_SCL_CONTROL
+-#define SCL5_SCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
+-#define SCL5_SCL_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4
+-#define SCL5_SCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L
+-#define SCL5_SCL_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x00000010L
+-//SCL5_SCL_BYPASS_CONTROL
+-#define SCL5_SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT 0x0
+-#define SCL5_SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x00000003L
+-//SCL5_SCL_MANUAL_REPLICATE_CONTROL
+-#define SCL5_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
+-#define SCL5_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
+-#define SCL5_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL
+-#define SCL5_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L
+-//SCL5_SCL_AUTOMATIC_MODE_CONTROL
+-#define SCL5_SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0
+-#define SCL5_SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10
+-#define SCL5_SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x00000001L
+-#define SCL5_SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x00010000L
+-//SCL5_SCL_HORZ_FILTER_CONTROL
+-#define SCL5_SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT 0x0
+-#define SCL5_SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+-#define SCL5_SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK 0x00000001L
+-#define SCL5_SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
+-//SCL5_SCL_HORZ_FILTER_SCALE_RATIO
+-#define SCL5_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
+-#define SCL5_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL
+-//SCL5_SCL_HORZ_FILTER_INIT
+-#define SCL5_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
+-#define SCL5_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
+-#define SCL5_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL
+-#define SCL5_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L
+-//SCL5_SCL_VERT_FILTER_CONTROL
+-#define SCL5_SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT 0x0
+-#define SCL5_SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+-#define SCL5_SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK 0x00000001L
+-#define SCL5_SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
+-//SCL5_SCL_VERT_FILTER_SCALE_RATIO
+-#define SCL5_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
+-#define SCL5_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL
+-//SCL5_SCL_VERT_FILTER_INIT
+-#define SCL5_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
+-#define SCL5_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
+-#define SCL5_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL
+-#define SCL5_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x07000000L
+-//SCL5_SCL_VERT_FILTER_INIT_BOT
+-#define SCL5_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
+-#define SCL5_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
+-#define SCL5_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL
+-#define SCL5_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x07000000L
+-//SCL5_SCL_ROUND_OFFSET
+-#define SCL5_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0
+-#define SCL5_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10
+-#define SCL5_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0x0000FFFFL
+-#define SCL5_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xFFFF0000L
+-//SCL5_SCL_UPDATE
+-#define SCL5_SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
+-#define SCL5_SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8
+-#define SCL5_SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10
+-#define SCL5_SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18
+-#define SCL5_SCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L
+-#define SCL5_SCL_UPDATE__SCL_UPDATE_TAKEN_MASK 0x00000100L
+-#define SCL5_SCL_UPDATE__SCL_UPDATE_LOCK_MASK 0x00010000L
+-#define SCL5_SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x01000000L
+-//SCL5_SCL_F_SHARP_CONTROL
+-#define SCL5_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT 0x0
+-#define SCL5_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT 0x4
+-#define SCL5_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT 0x8
+-#define SCL5_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT 0xc
+-#define SCL5_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK 0x00000007L
+-#define SCL5_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK 0x00000010L
+-#define SCL5_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK 0x00000700L
+-#define SCL5_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK 0x00001000L
+-//SCL5_SCL_ALU_CONTROL
+-#define SCL5_SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0
+-#define SCL5_SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x00000001L
+-//SCL5_SCL_COEF_RAM_CONFLICT_STATUS
+-#define SCL5_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT 0x0
+-#define SCL5_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT 0x8
+-#define SCL5_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT 0xc
+-#define SCL5_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10
+-#define SCL5_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK 0x00000001L
+-#define SCL5_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK 0x00000100L
+-#define SCL5_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK 0x00001000L
+-#define SCL5_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK 0x00010000L
+-//SCL5_VIEWPORT_START_SECONDARY
+-#define SCL5_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0
+-#define SCL5_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10
+-#define SCL5_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x00003FFFL
+-#define SCL5_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3FFF0000L
+-//SCL5_VIEWPORT_START
+-#define SCL5_VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0
+-#define SCL5_VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10
+-#define SCL5_VIEWPORT_START__VIEWPORT_Y_START_MASK 0x00003FFFL
+-#define SCL5_VIEWPORT_START__VIEWPORT_X_START_MASK 0x3FFF0000L
+-//SCL5_VIEWPORT_SIZE
+-#define SCL5_VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0
+-#define SCL5_VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10
+-#define SCL5_VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x00003FFFL
+-#define SCL5_VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x3FFF0000L
+-//SCL5_EXT_OVERSCAN_LEFT_RIGHT
+-#define SCL5_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
+-#define SCL5_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
+-#define SCL5_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL
+-#define SCL5_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L
+-//SCL5_EXT_OVERSCAN_TOP_BOTTOM
+-#define SCL5_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
+-#define SCL5_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
+-#define SCL5_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL
+-#define SCL5_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L
+-//SCL5_SCL_MODE_CHANGE_DET1
+-#define SCL5_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0
+-#define SCL5_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4
+-#define SCL5_SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7
+-#define SCL5_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x00000001L
+-#define SCL5_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x00000010L
+-#define SCL5_SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0x0FFFFF80L
+-//SCL5_SCL_MODE_CHANGE_DET2
+-#define SCL5_SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0
+-#define SCL5_SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x001FFFFFL
+-//SCL5_SCL_MODE_CHANGE_DET3
+-#define SCL5_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0
+-#define SCL5_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10
+-#define SCL5_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x00003FFFL
+-#define SCL5_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3FFF0000L
+-//SCL5_SCL_MODE_CHANGE_MASK
+-#define SCL5_SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0
+-#define SCL5_SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x00000001L
+-
+-
+-// addressBlock: dce_dc_blnd5_dispdec
+-//BLND5_BLND_CONTROL
+-#define BLND5_BLND_CONTROL__BLND_GLOBAL_GAIN__SHIFT 0x0
+-#define BLND5_BLND_CONTROL__BLND_MODE__SHIFT 0x8
+-#define BLND5_BLND_CONTROL__BLND_STEREO_TYPE__SHIFT 0xa
+-#define BLND5_BLND_CONTROL__BLND_STEREO_POLARITY__SHIFT 0xc
+-#define BLND5_BLND_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT 0xd
+-#define BLND5_BLND_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10
+-#define BLND5_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x12
+-#define BLND5_BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14
+-#define BLND5_BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18
+-#define BLND5_BLND_CONTROL__BLND_GLOBAL_GAIN_MASK 0x000000FFL
+-#define BLND5_BLND_CONTROL__BLND_MODE_MASK 0x00000300L
+-#define BLND5_BLND_CONTROL__BLND_STEREO_TYPE_MASK 0x00000C00L
+-#define BLND5_BLND_CONTROL__BLND_STEREO_POLARITY_MASK 0x00001000L
+-#define BLND5_BLND_CONTROL__BLND_FEEDTHROUGH_EN_MASK 0x00002000L
+-#define BLND5_BLND_CONTROL__BLND_ALPHA_MODE_MASK 0x00030000L
+-#define BLND5_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00040000L
+-#define BLND5_BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x00100000L
+-#define BLND5_BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xFF000000L
+-//BLND5_BLND_SM_CONTROL2
+-#define BLND5_BLND_SM_CONTROL2__SM_MODE__SHIFT 0x0
+-#define BLND5_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4
+-#define BLND5_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5
+-#define BLND5_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
+-#define BLND5_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
+-#define BLND5_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18
+-#define BLND5_BLND_SM_CONTROL2__SM_MODE_MASK 0x00000007L
+-#define BLND5_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x00000010L
+-#define BLND5_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x00000020L
+-#define BLND5_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L
+-#define BLND5_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L
+-#define BLND5_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x01000000L
+-//BLND5_BLND_CONTROL2
+-#define BLND5_BLND_CONTROL2__PTI_ENABLE__SHIFT 0x0
+-#define BLND5_BLND_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT 0x4
+-#define BLND5_BLND_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT 0x6
+-#define BLND5_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT 0x7
+-#define BLND5_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT 0x8
+-#define BLND5_BLND_CONTROL2__PTI_ENABLE_MASK 0x00000001L
+-#define BLND5_BLND_CONTROL2__PTI_NEW_PIXEL_GAP_MASK 0x00000030L
+-#define BLND5_BLND_CONTROL2__BLND_NEW_PIXEL_MODE_MASK 0x00000040L
+-#define BLND5_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK 0x00000080L
+-#define BLND5_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK 0x00000100L
+-//BLND5_BLND_UPDATE
+-#define BLND5_BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0
+-#define BLND5_BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8
+-#define BLND5_BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10
+-#define BLND5_BLND_UPDATE__BLND_UPDATE_PENDING_MASK 0x00000001L
+-#define BLND5_BLND_UPDATE__BLND_UPDATE_TAKEN_MASK 0x00000100L
+-#define BLND5_BLND_UPDATE__BLND_UPDATE_LOCK_MASK 0x00010000L
+-//BLND5_BLND_UNDERFLOW_INTERRUPT
+-#define BLND5_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0
+-#define BLND5_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8
+-#define BLND5_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc
+-#define BLND5_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10
+-#define BLND5_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x00000001L
+-#define BLND5_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x00000100L
+-#define BLND5_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x00001000L
+-#define BLND5_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x00030000L
+-//BLND5_BLND_V_UPDATE_LOCK
+-#define BLND5_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0
+-#define BLND5_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1
+-#define BLND5_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10
+-#define BLND5_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c
+-#define BLND5_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT 0x1d
+-#define BLND5_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT 0x1f
+-#define BLND5_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x00000001L
+-#define BLND5_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x00000002L
+-#define BLND5_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x00010000L
+-#define BLND5_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000L
+-#define BLND5_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK 0x20000000L
+-#define BLND5_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK 0x80000000L
+-//BLND5_BLND_REG_UPDATE_STATUS
+-#define BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT 0x0
+-#define BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT 0x1
+-#define BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2
+-#define BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3
+-#define BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT 0x6
+-#define BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT 0x7
+-#define BLND5_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT 0x8
+-#define BLND5_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT 0x9
+-#define BLND5_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT 0xa
+-#define BLND5_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT 0xb
+-#define BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK 0x00000001L
+-#define BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK 0x00000002L
+-#define BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK 0x00000004L
+-#define BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK 0x00000008L
+-#define BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK 0x00000040L
+-#define BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK 0x00000080L
+-#define BLND5_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK 0x00000100L
+-#define BLND5_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK 0x00000200L
+-#define BLND5_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK 0x00000400L
+-#define BLND5_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK 0x00000800L
+-
+-
+-// addressBlock: dce_dc_crtc5_dispdec
+-//CRTC5_CRTC_H_BLANK_EARLY_NUM
+-#define CRTC5_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0
+-#define CRTC5_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10
+-#define CRTC5_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x000003FFL
+-#define CRTC5_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x00010000L
+-//CRTC5_CRTC_H_TOTAL
+-#define CRTC5_CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0
+-#define CRTC5_CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x00003FFFL
+-//CRTC5_CRTC_H_BLANK_START_END
+-#define CRTC5_CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0
+-#define CRTC5_CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10
+-#define CRTC5_CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x00003FFFL
+-#define CRTC5_CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3FFF0000L
+-//CRTC5_CRTC_H_SYNC_A
+-#define CRTC5_CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0
+-#define CRTC5_CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10
+-#define CRTC5_CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x00003FFFL
+-#define CRTC5_CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3FFF0000L
+-//CRTC5_CRTC_H_SYNC_A_CNTL
+-#define CRTC5_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0
+-#define CRTC5_CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10
+-#define CRTC5_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11
+-#define CRTC5_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x00000001L
+-#define CRTC5_CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x00010000L
+-#define CRTC5_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x00020000L
+-//CRTC5_CRTC_H_SYNC_B
+-#define CRTC5_CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0
+-#define CRTC5_CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10
+-#define CRTC5_CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x00003FFFL
+-#define CRTC5_CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x3FFF0000L
+-//CRTC5_CRTC_H_SYNC_B_CNTL
+-#define CRTC5_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0
+-#define CRTC5_CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10
+-#define CRTC5_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11
+-#define CRTC5_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x00000001L
+-#define CRTC5_CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x00010000L
+-#define CRTC5_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x00020000L
+-//CRTC5_CRTC_VBI_END
+-#define CRTC5_CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x0
+-#define CRTC5_CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x10
+-#define CRTC5_CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x00003FFFL
+-#define CRTC5_CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x3FFF0000L
+-//CRTC5_CRTC_V_TOTAL
+-#define CRTC5_CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0
+-#define CRTC5_CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x00003FFFL
+-//CRTC5_CRTC_V_TOTAL_MIN
+-#define CRTC5_CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0
+-#define CRTC5_CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x00003FFFL
+-//CRTC5_CRTC_V_TOTAL_MAX
+-#define CRTC5_CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0
+-#define CRTC5_CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10
+-#define CRTC5_CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x00003FFFL
+-#define CRTC5_CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x00010000L
+-//CRTC5_CRTC_V_TOTAL_CONTROL
+-#define CRTC5_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0
+-#define CRTC5_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4
+-#define CRTC5_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8
+-#define CRTC5_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc
+-#define CRTC5_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf
+-#define CRTC5_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10
+-#define CRTC5_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x00000001L
+-#define CRTC5_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x00000010L
+-#define CRTC5_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x00000100L
+-#define CRTC5_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x00001000L
+-#define CRTC5_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00008000L
+-#define CRTC5_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L
+-//CRTC5_CRTC_V_TOTAL_INT_STATUS
+-#define CRTC5_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0
+-#define CRTC5_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4
+-#define CRTC5_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8
+-#define CRTC5_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc
+-#define CRTC5_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L
+-#define CRTC5_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L
+-#define CRTC5_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L
+-#define CRTC5_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L
+-//CRTC5_CRTC_VSYNC_NOM_INT_STATUS
+-#define CRTC5_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0
+-#define CRTC5_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4
+-#define CRTC5_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x00000001L
+-#define CRTC5_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L
+-//CRTC5_CRTC_V_BLANK_START_END
+-#define CRTC5_CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0
+-#define CRTC5_CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10
+-#define CRTC5_CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x00003FFFL
+-#define CRTC5_CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3FFF0000L
+-//CRTC5_CRTC_V_SYNC_A
+-#define CRTC5_CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0
+-#define CRTC5_CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10
+-#define CRTC5_CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x00003FFFL
+-#define CRTC5_CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3FFF0000L
+-//CRTC5_CRTC_V_SYNC_A_CNTL
+-#define CRTC5_CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0
+-#define CRTC5_CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x00000001L
+-//CRTC5_CRTC_V_SYNC_B
+-#define CRTC5_CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0
+-#define CRTC5_CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10
+-#define CRTC5_CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x00003FFFL
+-#define CRTC5_CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x3FFF0000L
+-//CRTC5_CRTC_V_SYNC_B_CNTL
+-#define CRTC5_CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0
+-#define CRTC5_CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x00000001L
+-//CRTC5_CRTC_DTMTEST_CNTL
+-#define CRTC5_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0
+-#define CRTC5_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1
+-#define CRTC5_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x00000001L
+-#define CRTC5_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x0000001EL
+-//CRTC5_CRTC_DTMTEST_STATUS_POSITION
+-#define CRTC5_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0
+-#define CRTC5_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10
+-#define CRTC5_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x00003FFFL
+-#define CRTC5_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x3FFF0000L
+-//CRTC5_CRTC_TRIGA_CNTL
+-#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0
+-#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5
+-#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8
+-#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9
+-#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa
+-#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb
+-#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
+-#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
+-#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14
+-#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18
+-#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f
+-#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x0000001FL
+-#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0x000000E0L
+-#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000100L
+-#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x00000200L
+-#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x00000400L
+-#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x00000800L
+-#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
+-#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
+-#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L
+-#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1F000000L
+-#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000L
+-//CRTC5_CRTC_TRIGA_MANUAL_TRIG
+-#define CRTC5_CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0
+-#define CRTC5_CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x00000001L
+-//CRTC5_CRTC_TRIGB_CNTL
+-#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0
+-#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5
+-#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8
+-#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9
+-#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa
+-#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb
+-#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
+-#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
+-#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14
+-#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18
+-#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f
+-#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x0000001FL
+-#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0x000000E0L
+-#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000100L
+-#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x00000200L
+-#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x00000400L
+-#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x00000800L
+-#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
+-#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
+-#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L
+-#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1F000000L
+-#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000L
+-//CRTC5_CRTC_TRIGB_MANUAL_TRIG
+-#define CRTC5_CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0
+-#define CRTC5_CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x00000001L
+-//CRTC5_CRTC_FORCE_COUNT_NOW_CNTL
+-#define CRTC5_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0
+-#define CRTC5_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4
+-#define CRTC5_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8
+-#define CRTC5_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10
+-#define CRTC5_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18
+-#define CRTC5_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x00000003L
+-#define CRTC5_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L
+-#define CRTC5_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L
+-#define CRTC5_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L
+-#define CRTC5_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L
+-//CRTC5_CRTC_FLOW_CONTROL
+-#define CRTC5_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0
+-#define CRTC5_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8
+-#define CRTC5_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10
+-#define CRTC5_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18
+-#define CRTC5_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL
+-#define CRTC5_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x00000100L
+-#define CRTC5_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L
+-#define CRTC5_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L
+-//CRTC5_CRTC_STEREO_FORCE_NEXT_EYE
+-#define CRTC5_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0
+-#define CRTC5_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER__SHIFT 0x8
+-#define CRTC5_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER__SHIFT 0x10
+-#define CRTC5_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L
+-#define CRTC5_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L
+-#define CRTC5_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L
+-//CRTC5_CRTC_AVSYNC_COUNTER
+-#define CRTC5_CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER__SHIFT 0x0
+-#define CRTC5_CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER_MASK 0xFFFFFFFFL
+-//CRTC5_CRTC_CONTROL
+-#define CRTC5_CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x0
+-#define CRTC5_CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4
+-#define CRTC5_CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8
+-#define CRTC5_CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc
+-#define CRTC5_CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd
+-#define CRTC5_CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe
+-#define CRTC5_CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10
+-#define CRTC5_CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14
+-#define CRTC5_CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d
+-#define CRTC5_CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e
+-#define CRTC5_CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f
+-#define CRTC5_CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x00000001L
+-#define CRTC5_CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x00000010L
+-#define CRTC5_CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x00000300L
+-#define CRTC5_CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x00001000L
+-#define CRTC5_CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x00002000L
+-#define CRTC5_CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x00004000L
+-#define CRTC5_CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x00010000L
+-#define CRTC5_CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x00700000L
+-#define CRTC5_CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000L
+-#define CRTC5_CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L
+-#define CRTC5_CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L
+-//CRTC5_CRTC_BLANK_CONTROL
+-#define CRTC5_CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0
+-#define CRTC5_CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8
+-#define CRTC5_CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10
+-#define CRTC5_CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x00000001L
+-#define CRTC5_CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x00000100L
+-#define CRTC5_CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x00010000L
+-//CRTC5_CRTC_INTERLACE_CONTROL
+-#define CRTC5_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0
+-#define CRTC5_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10
+-#define CRTC5_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x00000001L
+-#define CRTC5_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L
+-//CRTC5_CRTC_INTERLACE_STATUS
+-#define CRTC5_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0
+-#define CRTC5_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1
+-#define CRTC5_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x00000001L
+-#define CRTC5_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x00000002L
+-//CRTC5_CRTC_FIELD_INDICATION_CONTROL
+-#define CRTC5_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0
+-#define CRTC5_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1
+-#define CRTC5_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x00000001L
+-#define CRTC5_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x00000002L
+-//CRTC5_CRTC_PIXEL_DATA_READBACK0
+-#define CRTC5_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0
+-#define CRTC5_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10
+-#define CRTC5_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0x00000FFFL
+-#define CRTC5_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0x0FFF0000L
+-//CRTC5_CRTC_PIXEL_DATA_READBACK1
+-#define CRTC5_CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0
+-#define CRTC5_CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0x00000FFFL
+-//CRTC5_CRTC_STATUS
+-#define CRTC5_CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x0
+-#define CRTC5_CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1
+-#define CRTC5_CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x2
+-#define CRTC5_CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x3
+-#define CRTC5_CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x4
+-#define CRTC5_CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5
+-#define CRTC5_CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x10
+-#define CRTC5_CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11
+-#define CRTC5_CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x12
+-#define CRTC5_CRTC_STATUS__CRTC_V_BLANK_MASK 0x00000001L
+-#define CRTC5_CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x00000002L
+-#define CRTC5_CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x00000004L
+-#define CRTC5_CRTC_STATUS__CRTC_V_UPDATE_MASK 0x00000008L
+-#define CRTC5_CRTC_STATUS__CRTC_V_START_LINE_MASK 0x00000010L
+-#define CRTC5_CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x00000020L
+-#define CRTC5_CRTC_STATUS__CRTC_H_BLANK_MASK 0x00010000L
+-#define CRTC5_CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x00020000L
+-#define CRTC5_CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x00040000L
+-//CRTC5_CRTC_STATUS_POSITION
+-#define CRTC5_CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0
+-#define CRTC5_CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10
+-#define CRTC5_CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x00003FFFL
+-#define CRTC5_CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x3FFF0000L
+-//CRTC5_CRTC_NOM_VERT_POSITION
+-#define CRTC5_CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0
+-#define CRTC5_CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x00003FFFL
+-//CRTC5_CRTC_STATUS_FRAME_COUNT
+-#define CRTC5_CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0
+-#define CRTC5_CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0x00FFFFFFL
+-//CRTC5_CRTC_STATUS_VF_COUNT
+-#define CRTC5_CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0
+-#define CRTC5_CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x3FFFFFFFL
+-//CRTC5_CRTC_STATUS_HV_COUNT
+-#define CRTC5_CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0
+-#define CRTC5_CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x3FFFFFFFL
+-//CRTC5_CRTC_COUNT_CONTROL
+-#define CRTC5_CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0
+-#define CRTC5_CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1
+-#define CRTC5_CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x00000001L
+-#define CRTC5_CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x0000001EL
+-//CRTC5_CRTC_COUNT_RESET
+-#define CRTC5_CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0
+-#define CRTC5_CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x00000001L
+-//CRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE
+-#define CRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0
+-#define CRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L
+-//CRTC5_CRTC_VERT_SYNC_CONTROL
+-#define CRTC5_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0
+-#define CRTC5_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8
+-#define CRTC5_CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10
+-#define CRTC5_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L
+-#define CRTC5_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L
+-#define CRTC5_CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L
+-//CRTC5_CRTC_STEREO_STATUS
+-#define CRTC5_CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0
+-#define CRTC5_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8
+-#define CRTC5_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10
+-#define CRTC5_CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG__SHIFT 0x14
+-#define CRTC5_CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18
+-#define CRTC5_CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x00000001L
+-#define CRTC5_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x00000100L
+-#define CRTC5_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x00010000L
+-#define CRTC5_CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG_MASK 0x00100000L
+-#define CRTC5_CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L
+-//CRTC5_CRTC_STEREO_CONTROL
+-#define CRTC5_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0
+-#define CRTC5_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf
+-#define CRTC5_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10
+-#define CRTC5_CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11
+-#define CRTC5_CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12
+-#define CRTC5_CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM__SHIFT 0x13
+-#define CRTC5_CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14
+-#define CRTC5_CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18
+-#define CRTC5_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00003FFFL
+-#define CRTC5_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L
+-#define CRTC5_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x00010000L
+-#define CRTC5_CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L
+-#define CRTC5_CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L
+-#define CRTC5_CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM_MASK 0x00080000L
+-#define CRTC5_CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L
+-#define CRTC5_CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x01000000L
+-//CRTC5_CRTC_SNAPSHOT_STATUS
+-#define CRTC5_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0
+-#define CRTC5_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1
+-#define CRTC5_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2
+-#define CRTC5_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x00000001L
+-#define CRTC5_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x00000002L
+-#define CRTC5_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L
+-//CRTC5_CRTC_SNAPSHOT_CONTROL
+-#define CRTC5_CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0
+-#define CRTC5_CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L
+-//CRTC5_CRTC_SNAPSHOT_POSITION
+-#define CRTC5_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0
+-#define CRTC5_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10
+-#define CRTC5_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x00003FFFL
+-#define CRTC5_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x3FFF0000L
+-//CRTC5_CRTC_SNAPSHOT_FRAME
+-#define CRTC5_CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0
+-#define CRTC5_CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL
+-//CRTC5_CRTC_START_LINE_CONTROL
+-#define CRTC5_CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0
+-#define CRTC5_CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x1
+-#define CRTC5_CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x2
+-#define CRTC5_CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x8
+-#define CRTC5_CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc
+-#define CRTC5_CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x00000001L
+-#define CRTC5_CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x00000002L
+-#define CRTC5_CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x00000004L
+-#define CRTC5_CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x00000100L
+-#define CRTC5_CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0x000FF000L
+-//CRTC5_CRTC_INTERRUPT_CONTROL
+-#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0
+-#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1
+-#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4
+-#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5
+-#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8
+-#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9
+-#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10
+-#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11
+-#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18
+-#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19
+-#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a
+-#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b
+-#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c
+-#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d
+-#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e
+-#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f
+-#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x00000001L
+-#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x00000002L
+-#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x00000010L
+-#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x00000020L
+-#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L
+-#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L
+-#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L
+-#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L
+-#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x01000000L
+-#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x02000000L
+-#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x04000000L
+-#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x08000000L
+-#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000L
+-#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000L
+-#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L
+-#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L
+-//CRTC5_CRTC_UPDATE_LOCK
+-#define CRTC5_CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0
+-#define CRTC5_CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x00000001L
+-//CRTC5_CRTC_DOUBLE_BUFFER_CONTROL
+-#define CRTC5_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0
+-#define CRTC5_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8
+-#define CRTC5_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10
+-#define CRTC5_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18
+-#define CRTC5_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x19
+-#define CRTC5_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x00000001L
+-#define CRTC5_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x00000100L
+-#define CRTC5_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L
+-#define CRTC5_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x01000000L
+-#define CRTC5_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x02000000L
+-//CRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE
+-#define CRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0
+-#define CRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x00000001L
+-//CRTC5_CRTC_TEST_PATTERN_CONTROL
+-#define CRTC5_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0
+-#define CRTC5_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8
+-#define CRTC5_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10
+-#define CRTC5_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18
+-#define CRTC5_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x00000001L
+-#define CRTC5_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x00000700L
+-#define CRTC5_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L
+-#define CRTC5_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xFF000000L
+-//CRTC5_CRTC_TEST_PATTERN_PARAMETERS
+-#define CRTC5_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0
+-#define CRTC5_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4
+-#define CRTC5_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8
+-#define CRTC5_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc
+-#define CRTC5_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10
+-#define CRTC5_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0x0000000FL
+-#define CRTC5_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0x000000F0L
+-#define CRTC5_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0x00000F00L
+-#define CRTC5_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0x0000F000L
+-#define CRTC5_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xFFFF0000L
+-//CRTC5_CRTC_TEST_PATTERN_COLOR
+-#define CRTC5_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0
+-#define CRTC5_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10
+-#define CRTC5_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0x0000FFFFL
+-#define CRTC5_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x003F0000L
+-//CRTC5_CRTC_MASTER_UPDATE_LOCK
+-#define CRTC5_CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0
+-#define CRTC5_CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8
+-#define CRTC5_CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK__SHIFT 0x10
+-#define CRTC5_CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x00000001L
+-#define CRTC5_CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x00000100L
+-#define CRTC5_CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK_MASK 0x00010000L
+-//CRTC5_CRTC_MASTER_UPDATE_MODE
+-#define CRTC5_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0
+-#define CRTC5_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10
+-#define CRTC5_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x00000007L
+-#define CRTC5_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00030000L
+-//CRTC5_CRTC_MVP_INBAND_CNTL_INSERT
+-#define CRTC5_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0
+-#define CRTC5_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8
+-#define CRTC5_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x00000003L
+-#define CRTC5_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xFFFFFF00L
+-//CRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER
+-#define CRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0
+-#define CRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0x000000FFL
+-//CRTC5_CRTC_MVP_STATUS
+-#define CRTC5_CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0
+-#define CRTC5_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4
+-#define CRTC5_CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10
+-#define CRTC5_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14
+-#define CRTC5_CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x00000001L
+-#define CRTC5_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x00000010L
+-#define CRTC5_CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x00010000L
+-#define CRTC5_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x00100000L
+-//CRTC5_CRTC_MASTER_EN
+-#define CRTC5_CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0
+-#define CRTC5_CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x00000001L
+-//CRTC5_CRTC_ALLOW_STOP_OFF_V_CNT
+-#define CRTC5_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0
+-#define CRTC5_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10
+-#define CRTC5_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0x000000FFL
+-#define CRTC5_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x00010000L
+-//CRTC5_CRTC_V_UPDATE_INT_STATUS
+-#define CRTC5_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0
+-#define CRTC5_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8
+-#define CRTC5_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x00000001L
+-#define CRTC5_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x00000100L
+-//CRTC5_CRTC_OVERSCAN_COLOR
+-#define CRTC5_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0
+-#define CRTC5_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa
+-#define CRTC5_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14
+-#define CRTC5_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x000003FFL
+-#define CRTC5_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0x000FFC00L
+-#define CRTC5_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3FF00000L
+-//CRTC5_CRTC_OVERSCAN_COLOR_EXT
+-#define CRTC5_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0
+-#define CRTC5_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8
+-#define CRTC5_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10
+-#define CRTC5_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x00000003L
+-#define CRTC5_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x00000300L
+-#define CRTC5_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x00030000L
+-//CRTC5_CRTC_BLANK_DATA_COLOR
+-#define CRTC5_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0
+-#define CRTC5_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa
+-#define CRTC5_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14
+-#define CRTC5_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL
+-#define CRTC5_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L
+-#define CRTC5_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L
+-//CRTC5_CRTC_BLANK_DATA_COLOR_EXT
+-#define CRTC5_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0
+-#define CRTC5_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8
+-#define CRTC5_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10
+-#define CRTC5_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x00000003L
+-#define CRTC5_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00000300L
+-#define CRTC5_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x00030000L
+-//CRTC5_CRTC_BLACK_COLOR
+-#define CRTC5_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0
+-#define CRTC5_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa
+-#define CRTC5_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14
+-#define CRTC5_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x000003FFL
+-#define CRTC5_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0x000FFC00L
+-#define CRTC5_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3FF00000L
+-//CRTC5_CRTC_BLACK_COLOR_EXT
+-#define CRTC5_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0
+-#define CRTC5_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8
+-#define CRTC5_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10
+-#define CRTC5_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x00000003L
+-#define CRTC5_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x00000300L
+-#define CRTC5_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x00030000L
+-//CRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION
+-#define CRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0
+-#define CRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10
+-#define CRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00003FFFL
+-#define CRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x3FFF0000L
+-//CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL
+-#define CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4
+-#define CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8
+-#define CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc
+-#define CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10
+-#define CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14
+-#define CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18
+-#define CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L
+-#define CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L
+-#define CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L
+-#define CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L
+-#define CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L
+-#define CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L
+-//CRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION
+-#define CRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0
+-#define CRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00003FFFL
+-//CRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL
+-#define CRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8
+-#define CRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc
+-#define CRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10
+-#define CRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14
+-#define CRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18
+-#define CRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L
+-#define CRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L
+-#define CRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L
+-#define CRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L
+-#define CRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L
+-//CRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION
+-#define CRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0
+-#define CRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00003FFFL
+-//CRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL
+-#define CRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8
+-#define CRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc
+-#define CRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10
+-#define CRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14
+-#define CRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18
+-#define CRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L
+-#define CRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L
+-#define CRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L
+-#define CRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L
+-#define CRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L
+-//CRTC5_CRTC_CRC_CNTL
+-#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0
+-#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4
+-#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8
+-#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc
+-#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
+-#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14
+-#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18
+-#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC_EN_MASK 0x00000001L
+-#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x00000010L
+-#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x00000300L
+-#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x00003000L
+-#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
+-#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x00700000L
+-#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x07000000L
+-//CRTC5_CRTC_CRC0_WINDOWA_X_CONTROL
+-#define CRTC5_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0
+-#define CRTC5_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10
+-#define CRTC5_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x00003FFFL
+-#define CRTC5_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3FFF0000L
+-//CRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL
+-#define CRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0
+-#define CRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10
+-#define CRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x00003FFFL
+-#define CRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3FFF0000L
+-//CRTC5_CRTC_CRC0_WINDOWB_X_CONTROL
+-#define CRTC5_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0
+-#define CRTC5_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10
+-#define CRTC5_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x00003FFFL
+-#define CRTC5_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3FFF0000L
+-//CRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL
+-#define CRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0
+-#define CRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10
+-#define CRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x00003FFFL
+-#define CRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3FFF0000L
+-//CRTC5_CRTC_CRC0_DATA_RG
+-#define CRTC5_CRTC_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0
+-#define CRTC5_CRTC_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10
+-#define CRTC5_CRTC_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL
+-#define CRTC5_CRTC_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L
+-//CRTC5_CRTC_CRC0_DATA_B
+-#define CRTC5_CRTC_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0
+-#define CRTC5_CRTC_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL
+-//CRTC5_CRTC_CRC1_WINDOWA_X_CONTROL
+-#define CRTC5_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0
+-#define CRTC5_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10
+-#define CRTC5_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x00003FFFL
+-#define CRTC5_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3FFF0000L
+-//CRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL
+-#define CRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0
+-#define CRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10
+-#define CRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x00003FFFL
+-#define CRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3FFF0000L
+-//CRTC5_CRTC_CRC1_WINDOWB_X_CONTROL
+-#define CRTC5_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0
+-#define CRTC5_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10
+-#define CRTC5_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x00003FFFL
+-#define CRTC5_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3FFF0000L
+-//CRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL
+-#define CRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0
+-#define CRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10
+-#define CRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x00003FFFL
+-#define CRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3FFF0000L
+-//CRTC5_CRTC_CRC1_DATA_RG
+-#define CRTC5_CRTC_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0
+-#define CRTC5_CRTC_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10
+-#define CRTC5_CRTC_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL
+-#define CRTC5_CRTC_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L
+-//CRTC5_CRTC_CRC1_DATA_B
+-#define CRTC5_CRTC_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0
+-#define CRTC5_CRTC_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL
+-//CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE__SHIFT 0x0
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__SHIFT 0x3
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__SHIFT 0x4
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__SHIFT 0x5
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__SHIFT 0x8
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__SHIFT 0x9
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__SHIFT 0xc
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__SHIFT 0xd
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__SHIFT 0xe
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE__SHIFT 0x18
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE__SHIFT 0x1c
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE_MASK 0x00000003L
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_MASK 0x00000008L
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_MASK 0x00000010L
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_MASK 0x00000060L
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_MASK 0x00000100L
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_MASK 0x00000200L
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_MASK 0x00001000L
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_MASK 0x00002000L
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_MASK 0x00004000L
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE_MASK 0x07000000L
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE_MASK 0x70000000L
+-//CRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X__SHIFT 0x0
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y__SHIFT 0x10
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X_MASK 0x00003FFFL
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y_MASK 0x3FFF0000L
+-//CRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X__SHIFT 0x0
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y__SHIFT 0x10
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X_MASK 0x00003FFFL
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y_MASK 0x3FFF0000L
+-//CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__SHIFT 0x0
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS__SHIFT 0x4
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS__SHIFT 0x8
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__SHIFT 0x10
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__SHIFT 0x14
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__SHIFT 0x1d
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_MASK 0x00000001L
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS_MASK 0x00000010L
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS_MASK 0x00000100L
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_MASK 0x00010000L
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_MASK 0x00100000L
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_MASK 0xE0000000L
+-//CRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE__SHIFT 0x0
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS__SHIFT 0x4
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS__SHIFT 0x8
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR__SHIFT 0x10
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE__SHIFT 0x14
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE_MASK 0x00000001L
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS_MASK 0x00000010L
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS_MASK 0x00000100L
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR_MASK 0x00010000L
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE_MASK 0x00100000L
+-//CRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__SHIFT 0x0
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS__SHIFT 0x4
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS__SHIFT 0x8
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__SHIFT 0x10
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__SHIFT 0x14
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_MASK 0x00000001L
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS_MASK 0x00000010L
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS_MASK 0x00000100L
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_MASK 0x00010000L
+-#define CRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_MASK 0x00100000L
+-//CRTC5_CRTC_STATIC_SCREEN_CONTROL
+-#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0
+-#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10
+-#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18
+-#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19
+-#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a
+-#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b
+-#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c
+-#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e
+-#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f
+-#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL
+-#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L
+-#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x01000000L
+-#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x02000000L
+-#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x04000000L
+-#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x08000000L
+-#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000L
+-#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L
+-#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L
+-//CRTC5_CRTC_3D_STRUCTURE_CONTROL
+-#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0
+-#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4
+-#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8
+-#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc
+-#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10
+-#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11
+-#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12
+-#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x00000001L
+-#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x00000010L
+-#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L
+-#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L
+-#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L
+-#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L
+-#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L
+-//CRTC5_CRTC_GSL_VSYNC_GAP
+-#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0
+-#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8
+-#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10
+-#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11
+-#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13
+-#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14
+-#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17
+-#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18
+-#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL
+-#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L
+-#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L
+-#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x00060000L
+-#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L
+-#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L
+-#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L
+-#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xFF000000L
+-//CRTC5_CRTC_GSL_WINDOW
+-#define CRTC5_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0
+-#define CRTC5_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10
+-#define CRTC5_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x00003FFFL
+-#define CRTC5_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x3FFF0000L
+-//CRTC5_CRTC_GSL_CONTROL
+-#define CRTC5_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0
+-#define CRTC5_CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10
+-#define CRTC5_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c
+-#define CRTC5_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x00003FFFL
+-#define CRTC5_CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x001F0000L
+-#define CRTC5_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L
+-//CRTC5_CRTC_RANGE_TIMING_INT_STATUS
+-#define CRTC5_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0
+-#define CRTC5_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4
+-#define CRTC5_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8
+-#define CRTC5_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc
+-#define CRTC5_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10
+-#define CRTC5_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L
+-#define CRTC5_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L
+-#define CRTC5_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L
+-#define CRTC5_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L
+-#define CRTC5_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L
+-//CRTC5_CRTC_DRR_CONTROL
+-#define CRTC5_CRTC_DRR_CONTROL__CRTC_XDMA_PREFETCH_DELAY__SHIFT 0x0
+-#define CRTC5_CRTC_DRR_CONTROL__CRTC_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0xe
+-#define CRTC5_CRTC_DRR_CONTROL__CRTC_SET_V_TOTAL_MIN_AUTO_DIS__SHIFT 0x1c
+-#define CRTC5_CRTC_DRR_CONTROL__CRTC_DRR_MODE_DBUF_UPDATE_MODE__SHIFT 0x1d
+-#define CRTC5_CRTC_DRR_CONTROL__CRTC_XDMA_PREFETCH_DELAY_MASK 0x00003FFFL
+-#define CRTC5_CRTC_DRR_CONTROL__CRTC_V_TOTAL_LAST_USED_BY_DRR_MASK 0x0FFFC000L
+-#define CRTC5_CRTC_DRR_CONTROL__CRTC_SET_V_TOTAL_MIN_AUTO_DIS_MASK 0x10000000L
+-#define CRTC5_CRTC_DRR_CONTROL__CRTC_DRR_MODE_DBUF_UPDATE_MODE_MASK 0x60000000L
+-
+-
+-// addressBlock: dce_dc_fmt5_dispdec
+-//FMT5_FMT_CLAMP_COMPONENT_R
+-#define FMT5_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0
+-#define FMT5_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10
+-#define FMT5_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL
+-#define FMT5_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L
+-//FMT5_FMT_CLAMP_COMPONENT_G
+-#define FMT5_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0
+-#define FMT5_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10
+-#define FMT5_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL
+-#define FMT5_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L
+-//FMT5_FMT_CLAMP_COMPONENT_B
+-#define FMT5_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0
+-#define FMT5_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10
+-#define FMT5_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL
+-#define FMT5_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L
+-//FMT5_FMT_DYNAMIC_EXP_CNTL
+-#define FMT5_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0
+-#define FMT5_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4
+-#define FMT5_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L
+-#define FMT5_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L
+-//FMT5_FMT_CONTROL
+-#define FMT5_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0
+-#define FMT5_FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT 0x4
+-#define FMT5_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8
+-#define FMT5_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc
+-#define FMT5_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10
+-#define FMT5_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12
+-#define FMT5_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14
+-#define FMT5_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15
+-#define FMT5_FMT_CONTROL__FMT_SRC_SELECT__SHIFT 0x18
+-#define FMT5_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED__SHIFT 0x1e
+-#define FMT5_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_CLEAR__SHIFT 0x1f
+-#define FMT5_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L
+-#define FMT5_FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK 0x00000010L
+-#define FMT5_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L
+-#define FMT5_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L
+-#define FMT5_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L
+-#define FMT5_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L
+-#define FMT5_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L
+-#define FMT5_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L
+-#define FMT5_FMT_CONTROL__FMT_SRC_SELECT_MASK 0x07000000L
+-#define FMT5_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_MASK 0x40000000L
+-#define FMT5_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_CLEAR_MASK 0x80000000L
+-//FMT5_FMT_BIT_DEPTH_CONTROL
+-#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0
+-#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1
+-#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4
+-#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8
+-#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9
+-#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb
+-#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd
+-#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe
+-#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf
+-#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10
+-#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11
+-#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15
+-#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18
+-#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19
+-#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a
+-#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c
+-#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e
+-#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L
+-#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L
+-#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L
+-#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L
+-#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L
+-#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L
+-#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L
+-#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L
+-#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L
+-#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L
+-#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L
+-#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L
+-#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L
+-#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L
+-#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L
+-#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L
+-#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L
+-//FMT5_FMT_DITHER_RAND_R_SEED
+-#define FMT5_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0
+-#define FMT5_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10
+-#define FMT5_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL
+-#define FMT5_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L
+-//FMT5_FMT_DITHER_RAND_G_SEED
+-#define FMT5_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0
+-#define FMT5_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10
+-#define FMT5_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL
+-#define FMT5_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L
+-//FMT5_FMT_DITHER_RAND_B_SEED
+-#define FMT5_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0
+-#define FMT5_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10
+-#define FMT5_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL
+-#define FMT5_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L
+-//FMT5_FMT_CLAMP_CNTL
+-#define FMT5_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0
+-#define FMT5_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10
+-#define FMT5_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L
+-#define FMT5_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L
+-//FMT5_FMT_CRC_CNTL
+-#define FMT5_FMT_CRC_CNTL__FMT_CRC_EN__SHIFT 0x0
+-#define FMT5_FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN__SHIFT 0x1
+-#define FMT5_FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT 0x4
+-#define FMT5_FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING__SHIFT 0x5
+-#define FMT5_FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN__SHIFT 0x6
+-#define FMT5_FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB__SHIFT 0x8
+-#define FMT5_FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE__SHIFT 0x9
+-#define FMT5_FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT 0xc
+-#define FMT5_FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
+-#define FMT5_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT 0x14
+-#define FMT5_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT 0x18
+-#define FMT5_FMT_CRC_CNTL__FMT_CRC_EN_MASK 0x00000001L
+-#define FMT5_FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN_MASK 0x00000002L
+-#define FMT5_FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK 0x00000010L
+-#define FMT5_FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING_MASK 0x00000020L
+-#define FMT5_FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN_MASK 0x00000040L
+-#define FMT5_FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB_MASK 0x00000100L
+-#define FMT5_FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE_MASK 0x00000200L
+-#define FMT5_FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK 0x00003000L
+-#define FMT5_FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
+-#define FMT5_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK 0x00100000L
+-#define FMT5_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK 0x01000000L
+-//FMT5_FMT_CRC_SIG_RED_GREEN_MASK
+-#define FMT5_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT 0x0
+-#define FMT5_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT 0x10
+-#define FMT5_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK 0x0000FFFFL
+-#define FMT5_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L
+-//FMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK
+-#define FMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT 0x0
+-#define FMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT 0x10
+-#define FMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL
+-#define FMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L
+-//FMT5_FMT_CRC_SIG_RED_GREEN
+-#define FMT5_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT 0x0
+-#define FMT5_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT 0x10
+-#define FMT5_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK 0x0000FFFFL
+-#define FMT5_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK 0xFFFF0000L
+-//FMT5_FMT_CRC_SIG_BLUE_CONTROL
+-#define FMT5_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT 0x0
+-#define FMT5_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT 0x10
+-#define FMT5_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK 0x0000FFFFL
+-#define FMT5_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK 0xFFFF0000L
+-//FMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+-#define FMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0
+-#define FMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL
+-//FMT5_FMT_420_HBLANK_EARLY_START
+-#define FMT5_FMT_420_HBLANK_EARLY_START__FMT_420_HBLANK_EARLY_START__SHIFT 0x0
+-#define FMT5_FMT_420_HBLANK_EARLY_START__FMT_420_HBLANK_EARLY_START_MASK 0x00000FFFL
+-
+-
+-// addressBlock: dce_dc_unp0_dispdec
+-//UNP0_UNP_GRPH_ENABLE
+-#define UNP0_UNP_GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0
+-#define UNP0_UNP_GRPH_ENABLE__GRPH_ENABLE_MASK 0x00000001L
+-//UNP0_UNP_GRPH_CONTROL
+-#define UNP0_UNP_GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0
+-#define UNP0_UNP_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x2
+-#define UNP0_UNP_GRPH_CONTROL__GRPH_Z__SHIFT 0x4
+-#define UNP0_UNP_GRPH_CONTROL__GRPH_BANK_WIDTH_L__SHIFT 0x6
+-#define UNP0_UNP_GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8
+-#define UNP0_UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT_L__SHIFT 0xb
+-#define UNP0_UNP_GRPH_CONTROL__GRPH_TILE_SPLIT_L__SHIFT 0xd
+-#define UNP0_UNP_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10
+-#define UNP0_UNP_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11
+-#define UNP0_UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_L__SHIFT 0x12
+-#define UNP0_UNP_GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x14
+-#define UNP0_UNP_GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT 0x18
+-#define UNP0_UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE_L__SHIFT 0x1d
+-#define UNP0_UNP_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f
+-#define UNP0_UNP_GRPH_CONTROL__GRPH_DEPTH_MASK 0x00000003L
+-#define UNP0_UNP_GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0x0000000CL
+-#define UNP0_UNP_GRPH_CONTROL__GRPH_Z_MASK 0x00000030L
+-#define UNP0_UNP_GRPH_CONTROL__GRPH_BANK_WIDTH_L_MASK 0x000000C0L
+-#define UNP0_UNP_GRPH_CONTROL__GRPH_FORMAT_MASK 0x00000700L
+-#define UNP0_UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT_L_MASK 0x00001800L
+-#define UNP0_UNP_GRPH_CONTROL__GRPH_TILE_SPLIT_L_MASK 0x0000E000L
+-#define UNP0_UNP_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x00010000L
+-#define UNP0_UNP_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x00020000L
+-#define UNP0_UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_L_MASK 0x000C0000L
+-#define UNP0_UNP_GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0x00F00000L
+-#define UNP0_UNP_GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1F000000L
+-#define UNP0_UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE_L_MASK 0x60000000L
+-#define UNP0_UNP_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000L
+-//UNP0_UNP_GRPH_CONTROL_C
+-#define UNP0_UNP_GRPH_CONTROL_C__GRPH_BANK_WIDTH_C__SHIFT 0x6
+-#define UNP0_UNP_GRPH_CONTROL_C__GRPH_BANK_HEIGHT_C__SHIFT 0xb
+-#define UNP0_UNP_GRPH_CONTROL_C__GRPH_TILE_SPLIT_C__SHIFT 0xd
+-#define UNP0_UNP_GRPH_CONTROL_C__GRPH_MACRO_TILE_ASPECT_C__SHIFT 0x12
+-#define UNP0_UNP_GRPH_CONTROL_C__GRPH_MICRO_TILE_MODE_C__SHIFT 0x1d
+-#define UNP0_UNP_GRPH_CONTROL_C__GRPH_BANK_WIDTH_C_MASK 0x000000C0L
+-#define UNP0_UNP_GRPH_CONTROL_C__GRPH_BANK_HEIGHT_C_MASK 0x00001800L
+-#define UNP0_UNP_GRPH_CONTROL_C__GRPH_TILE_SPLIT_C_MASK 0x0000E000L
+-#define UNP0_UNP_GRPH_CONTROL_C__GRPH_MACRO_TILE_ASPECT_C_MASK 0x000C0000L
+-#define UNP0_UNP_GRPH_CONTROL_C__GRPH_MICRO_TILE_MODE_C_MASK 0x60000000L
+-//UNP0_UNP_GRPH_CONTROL_EXP
+-#define UNP0_UNP_GRPH_CONTROL_EXP__VIDEO_FORMAT__SHIFT 0x0
+-#define UNP0_UNP_GRPH_CONTROL_EXP__VIDEO_FORMAT_MASK 0x00000007L
+-//UNP0_UNP_GRPH_SWAP_CNTL
+-#define UNP0_UNP_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0
+-#define UNP0_UNP_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4
+-#define UNP0_UNP_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6
+-#define UNP0_UNP_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8
+-#define UNP0_UNP_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x00000003L
+-#define UNP0_UNP_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x00000030L
+-#define UNP0_UNP_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0x000000C0L
+-#define UNP0_UNP_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x00000300L
+-//UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L
+-#define UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L__SHIFT 0x8
+-#define UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L_MASK 0xFFFFFF00L
+-//UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C
+-#define UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x8
+-#define UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFF00L
+-//UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L
+-#define UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
+-#define UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_MASK 0x000000FFL
+-//UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C
+-#define UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+-#define UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x000000FFL
+-//UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L
+-#define UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__SHIFT 0x8
+-#define UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_MASK 0xFFFFFF00L
+-//UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C
+-#define UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__SHIFT 0x8
+-#define UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_MASK 0xFFFFFF00L
+-//UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L
+-#define UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
+-#define UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_MASK 0x000000FFL
+-//UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C
+-#define UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+-#define UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_MASK 0x000000FFL
+-//UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L
+-#define UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_SURFACE_ADDRESS_L__SHIFT 0x8
+-#define UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_SURFACE_ADDRESS_L_MASK 0xFFFFFF00L
+-//UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C
+-#define UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x8
+-#define UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFF00L
+-//UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L
+-#define UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
+-#define UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_MASK 0x000000FFL
+-//UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C
+-#define UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+-#define UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x000000FFL
+-//UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L
+-#define UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__SHIFT 0x8
+-#define UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_MASK 0xFFFFFF00L
+-//UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C
+-#define UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__SHIFT 0x8
+-#define UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_MASK 0xFFFFFF00L
+-//UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L
+-#define UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
+-#define UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_MASK 0x000000FFL
+-//UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C
+-#define UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+-#define UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_MASK 0x000000FFL
+-//UNP0_UNP_GRPH_PITCH_L
+-#define UNP0_UNP_GRPH_PITCH_L__GRPH_PITCH_L__SHIFT 0x0
+-#define UNP0_UNP_GRPH_PITCH_L__GRPH_PITCH_L_MASK 0x00007FFFL
+-//UNP0_UNP_GRPH_PITCH_C
+-#define UNP0_UNP_GRPH_PITCH_C__GRPH_PITCH_C__SHIFT 0x0
+-#define UNP0_UNP_GRPH_PITCH_C__GRPH_PITCH_C_MASK 0x00007FFFL
+-//UNP0_UNP_GRPH_SURFACE_OFFSET_X_L
+-#define UNP0_UNP_GRPH_SURFACE_OFFSET_X_L__GRPH_SURFACE_OFFSET_X_L__SHIFT 0x0
+-#define UNP0_UNP_GRPH_SURFACE_OFFSET_X_L__GRPH_SURFACE_OFFSET_X_L_MASK 0x00003FFFL
+-//UNP0_UNP_GRPH_SURFACE_OFFSET_X_C
+-#define UNP0_UNP_GRPH_SURFACE_OFFSET_X_C__GRPH_SURFACE_OFFSET_X_C__SHIFT 0x0
+-#define UNP0_UNP_GRPH_SURFACE_OFFSET_X_C__GRPH_SURFACE_OFFSET_X_C_MASK 0x00003FFFL
+-//UNP0_UNP_GRPH_SURFACE_OFFSET_Y_L
+-#define UNP0_UNP_GRPH_SURFACE_OFFSET_Y_L__GRPH_SURFACE_OFFSET_Y_L__SHIFT 0x0
+-#define UNP0_UNP_GRPH_SURFACE_OFFSET_Y_L__GRPH_SURFACE_OFFSET_Y_L_MASK 0x00003FFFL
+-//UNP0_UNP_GRPH_SURFACE_OFFSET_Y_C
+-#define UNP0_UNP_GRPH_SURFACE_OFFSET_Y_C__GRPH_SURFACE_OFFSET_Y_C__SHIFT 0x0
+-#define UNP0_UNP_GRPH_SURFACE_OFFSET_Y_C__GRPH_SURFACE_OFFSET_Y_C_MASK 0x00003FFFL
+-//UNP0_UNP_GRPH_X_START_L
+-#define UNP0_UNP_GRPH_X_START_L__GRPH_X_START_L__SHIFT 0x0
+-#define UNP0_UNP_GRPH_X_START_L__GRPH_X_START_L_MASK 0x00003FFFL
+-//UNP0_UNP_GRPH_X_START_C
+-#define UNP0_UNP_GRPH_X_START_C__GRPH_X_START_C__SHIFT 0x0
+-#define UNP0_UNP_GRPH_X_START_C__GRPH_X_START_C_MASK 0x00003FFFL
+-//UNP0_UNP_GRPH_Y_START_L
+-#define UNP0_UNP_GRPH_Y_START_L__GRPH_Y_START_L__SHIFT 0x0
+-#define UNP0_UNP_GRPH_Y_START_L__GRPH_Y_START_L_MASK 0x00003FFFL
+-//UNP0_UNP_GRPH_Y_START_C
+-#define UNP0_UNP_GRPH_Y_START_C__GRPH_Y_START_C__SHIFT 0x0
+-#define UNP0_UNP_GRPH_Y_START_C__GRPH_Y_START_C_MASK 0x00003FFFL
+-//UNP0_UNP_GRPH_X_END_L
+-#define UNP0_UNP_GRPH_X_END_L__GRPH_X_END_L__SHIFT 0x0
+-#define UNP0_UNP_GRPH_X_END_L__GRPH_X_END_L_MASK 0x00007FFFL
+-//UNP0_UNP_GRPH_X_END_C
+-#define UNP0_UNP_GRPH_X_END_C__GRPH_X_END_C__SHIFT 0x0
+-#define UNP0_UNP_GRPH_X_END_C__GRPH_X_END_C_MASK 0x00007FFFL
+-//UNP0_UNP_GRPH_Y_END_L
+-#define UNP0_UNP_GRPH_Y_END_L__GRPH_Y_END_L__SHIFT 0x0
+-#define UNP0_UNP_GRPH_Y_END_L__GRPH_Y_END_L_MASK 0x00007FFFL
+-//UNP0_UNP_GRPH_Y_END_C
+-#define UNP0_UNP_GRPH_Y_END_C__GRPH_Y_END_C__SHIFT 0x0
+-#define UNP0_UNP_GRPH_Y_END_C__GRPH_Y_END_C_MASK 0x00007FFFL
+-//UNP0_UNP_GRPH_UPDATE
+-#define UNP0_UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0
+-#define UNP0_UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1
+-#define UNP0_UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2
+-#define UNP0_UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3
+-#define UNP0_UNP_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10
+-#define UNP0_UNP_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14
+-#define UNP0_UNP_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+-#define UNP0_UNP_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c
+-#define UNP0_UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x00000001L
+-#define UNP0_UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x00000002L
+-#define UNP0_UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x00000004L
+-#define UNP0_UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x00000008L
+-#define UNP0_UNP_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x00010000L
+-#define UNP0_UNP_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x00100000L
+-#define UNP0_UNP_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
+-#define UNP0_UNP_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000L
+-//UNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT
+-#define UNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L__SHIFT 0x0
+-#define UNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C__SHIFT 0x8
+-#define UNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L_MASK 0x000000FFL
+-#define UNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C_MASK 0x0000FF00L
+-//UNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L
+-#define UNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L__GRPH_SURFACE_ADDRESS_INUSE_L__SHIFT 0x8
+-#define UNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L__GRPH_SURFACE_ADDRESS_INUSE_L_MASK 0xFFFFFF00L
+-//UNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C
+-#define UNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C__GRPH_SURFACE_ADDRESS_INUSE_C__SHIFT 0x8
+-#define UNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C__GRPH_SURFACE_ADDRESS_INUSE_C_MASK 0xFFFFFF00L
+-//UNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L
+-#define UNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__SHIFT 0x0
+-#define UNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_MASK 0x000000FFL
+-//UNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C
+-#define UNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__SHIFT 0x0
+-#define UNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_MASK 0x000000FFL
+-//UNP0_UNP_DVMM_PTE_CONTROL
+-#define UNP0_UNP_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT 0x0
+-#define UNP0_UNP_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT 0x1
+-#define UNP0_UNP_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT 0x5
+-#define UNP0_UNP_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT 0x9
+-#define UNP0_UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT 0x14
+-#define UNP0_UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT 0x15
+-#define UNP0_UNP_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK 0x00000001L
+-#define UNP0_UNP_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK 0x0000001EL
+-#define UNP0_UNP_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK 0x000001E0L
+-#define UNP0_UNP_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK 0x0007FE00L
+-#define UNP0_UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK 0x00100000L
+-#define UNP0_UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK 0x00200000L
+-//UNP0_UNP_DVMM_PTE_CONTROL_C
+-#define UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_USE_SINGLE_PTE_C__SHIFT 0x0
+-#define UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_WIDTH_C__SHIFT 0x1
+-#define UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_HEIGHT_C__SHIFT 0x5
+-#define UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_MIN_PTE_BEFORE_FLIP_C__SHIFT 0x9
+-#define UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE0_C__SHIFT 0x14
+-#define UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE1_C__SHIFT 0x15
+-#define UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_USE_SINGLE_PTE_C_MASK 0x00000001L
+-#define UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_WIDTH_C_MASK 0x0000001EL
+-#define UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_HEIGHT_C_MASK 0x000001E0L
+-#define UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_MIN_PTE_BEFORE_FLIP_C_MASK 0x0007FE00L
+-#define UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE0_C_MASK 0x00100000L
+-#define UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE1_C_MASK 0x00200000L
+-//UNP0_UNP_DVMM_PTE_ARB_CONTROL
+-#define UNP0_UNP_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT 0x0
+-#define UNP0_UNP_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT 0x8
+-#define UNP0_UNP_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK 0x0000003FL
+-#define UNP0_UNP_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK 0x0000FF00L
+-//UNP0_UNP_DVMM_PTE_ARB_CONTROL_C
+-#define UNP0_UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_PTE_REQ_PER_CHUNK_C__SHIFT 0x0
+-#define UNP0_UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_MAX_PTE_REQ_OUTSTANDING_C__SHIFT 0x8
+-#define UNP0_UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_PTE_REQ_PER_CHUNK_C_MASK 0x0000003FL
+-#define UNP0_UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_MAX_PTE_REQ_OUTSTANDING_C_MASK 0x0000FF00L
+-//UNP0_UNP_GRPH_INTERRUPT_STATUS
+-#define UNP0_UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0
+-#define UNP0_UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8
+-#define UNP0_UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x00000001L
+-#define UNP0_UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x00000100L
+-//UNP0_UNP_GRPH_INTERRUPT_CONTROL
+-#define UNP0_UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0
+-#define UNP0_UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8
+-#define UNP0_UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x00000001L
+-#define UNP0_UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x00000100L
+-//UNP0_UNP_GRPH_STEREOSYNC_FLIP
+-#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0
+-#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x4
+-#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_EN__SHIFT 0x8
+-#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_MODE__SHIFT 0xc
+-#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10
+-#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11
+-#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_BOTTOM_SURFACE_PENDING__SHIFT 0x12
+-#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_BOTTOM_SURFACE_PENDING__SHIFT 0x13
+-#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c
+-#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x00000001L
+-#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x00000030L
+-#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_EN_MASK 0x00000100L
+-#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_MODE_MASK 0x00003000L
+-#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x00010000L
+-#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x00020000L
+-#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_BOTTOM_SURFACE_PENDING_MASK 0x00040000L
+-#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_BOTTOM_SURFACE_PENDING_MASK 0x00080000L
+-#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000L
+-//UNP0_UNP_FLIP_CONTROL
+-#define UNP0_UNP_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT 0x0
+-#define UNP0_UNP_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK 0x00000001L
+-//UNP0_UNP_CRC_CONTROL
+-#define UNP0_UNP_CRC_CONTROL__UNP_CRC_ENABLE__SHIFT 0x0
+-#define UNP0_UNP_CRC_CONTROL__UNP_CRC_SOURCE_SEL__SHIFT 0x2
+-#define UNP0_UNP_CRC_CONTROL__UNP_CRC_LINE_SEL__SHIFT 0x8
+-#define UNP0_UNP_CRC_CONTROL__UNP_CRC_ENABLE_MASK 0x00000001L
+-#define UNP0_UNP_CRC_CONTROL__UNP_CRC_SOURCE_SEL_MASK 0x0000001CL
+-#define UNP0_UNP_CRC_CONTROL__UNP_CRC_LINE_SEL_MASK 0x00000300L
+-//UNP0_UNP_CRC_MASK
+-#define UNP0_UNP_CRC_MASK__UNP_CRC_MASK__SHIFT 0x0
+-#define UNP0_UNP_CRC_MASK__UNP_CRC_MASK_MASK 0xFFFFFFFFL
+-//UNP0_UNP_CRC_CURRENT
+-#define UNP0_UNP_CRC_CURRENT__UNP_CRC_CURRENT__SHIFT 0x0
+-#define UNP0_UNP_CRC_CURRENT__UNP_CRC_CURRENT_MASK 0xFFFFFFFFL
+-//UNP0_UNP_CRC_LAST
+-#define UNP0_UNP_CRC_LAST__UNP_CRC_LAST__SHIFT 0x0
+-#define UNP0_UNP_CRC_LAST__UNP_CRC_LAST_MASK 0xFFFFFFFFL
+-//UNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK
+-#define UNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK__UNP_LB_GAP_BETWEEN_CHUNK__SHIFT 0x4
+-#define UNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK__UNP_LB_GAP_BETWEEN_CHUNK_MASK 0x000001F0L
+-//UNP0_UNP_HW_ROTATION
+-#define UNP0_UNP_HW_ROTATION__ROTATION_ANGLE__SHIFT 0x0
+-#define UNP0_UNP_HW_ROTATION__PIXEL_DROP__SHIFT 0x4
+-#define UNP0_UNP_HW_ROTATION__BUFFER_MODE__SHIFT 0x8
+-#define UNP0_UNP_HW_ROTATION__ROTATION_ANGLE_MASK 0x00000007L
+-#define UNP0_UNP_HW_ROTATION__PIXEL_DROP_MASK 0x00000010L
+-#define UNP0_UNP_HW_ROTATION__BUFFER_MODE_MASK 0x00000100L
+-
+-
+-// addressBlock: dce_dc_lbv0_dispdec
+-//LBV0_LBV_DATA_FORMAT
+-#define LBV0_LBV_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0
+-#define LBV0_LBV_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2
+-#define LBV0_LBV_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3
+-#define LBV0_LBV_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4
+-#define LBV0_LBV_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5
+-#define LBV0_LBV_DATA_FORMAT__DITHER_EN__SHIFT 0x6
+-#define LBV0_LBV_DATA_FORMAT__DOWNSCALE_PREFETCH_EN__SHIFT 0x7
+-#define LBV0_LBV_DATA_FORMAT__PREFETCH__SHIFT 0xc
+-#define LBV0_LBV_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18
+-#define LBV0_LBV_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f
+-#define LBV0_LBV_DATA_FORMAT__PIXEL_DEPTH_MASK 0x00000003L
+-#define LBV0_LBV_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x00000004L
+-#define LBV0_LBV_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000008L
+-#define LBV0_LBV_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x00000010L
+-#define LBV0_LBV_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x00000020L
+-#define LBV0_LBV_DATA_FORMAT__DITHER_EN_MASK 0x00000040L
+-#define LBV0_LBV_DATA_FORMAT__DOWNSCALE_PREFETCH_EN_MASK 0x00000080L
+-#define LBV0_LBV_DATA_FORMAT__PREFETCH_MASK 0x00001000L
+-#define LBV0_LBV_DATA_FORMAT__REQUEST_MODE_MASK 0x01000000L
+-#define LBV0_LBV_DATA_FORMAT__ALPHA_EN_MASK 0x80000000L
+-//LBV0_LBV_MEMORY_CTRL
+-#define LBV0_LBV_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0
+-#define LBV0_LBV_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
+-#define LBV0_LBV_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14
+-#define LBV0_LBV_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0x00000FFFL
+-#define LBV0_LBV_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x000F0000L
+-#define LBV0_LBV_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x00300000L
+-//LBV0_LBV_MEMORY_SIZE_STATUS
+-#define LBV0_LBV_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0
+-#define LBV0_LBV_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0x00000FFFL
+-//LBV0_LBV_DESKTOP_HEIGHT
+-#define LBV0_LBV_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0
+-#define LBV0_LBV_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x00007FFFL
+-//LBV0_LBV_VLINE_START_END
+-#define LBV0_LBV_VLINE_START_END__VLINE_START__SHIFT 0x0
+-#define LBV0_LBV_VLINE_START_END__VLINE_END__SHIFT 0x10
+-#define LBV0_LBV_VLINE_START_END__VLINE_INV__SHIFT 0x1f
+-#define LBV0_LBV_VLINE_START_END__VLINE_START_MASK 0x00003FFFL
+-#define LBV0_LBV_VLINE_START_END__VLINE_END_MASK 0x7FFF0000L
+-#define LBV0_LBV_VLINE_START_END__VLINE_INV_MASK 0x80000000L
+-//LBV0_LBV_VLINE2_START_END
+-#define LBV0_LBV_VLINE2_START_END__VLINE2_START__SHIFT 0x0
+-#define LBV0_LBV_VLINE2_START_END__VLINE2_END__SHIFT 0x10
+-#define LBV0_LBV_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f
+-#define LBV0_LBV_VLINE2_START_END__VLINE2_START_MASK 0x00003FFFL
+-#define LBV0_LBV_VLINE2_START_END__VLINE2_END_MASK 0x7FFF0000L
+-#define LBV0_LBV_VLINE2_START_END__VLINE2_INV_MASK 0x80000000L
+-//LBV0_LBV_V_COUNTER
+-#define LBV0_LBV_V_COUNTER__V_COUNTER__SHIFT 0x0
+-#define LBV0_LBV_V_COUNTER__V_COUNTER_MASK 0x00007FFFL
+-//LBV0_LBV_SNAPSHOT_V_COUNTER
+-#define LBV0_LBV_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0
+-#define LBV0_LBV_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x00007FFFL
+-//LBV0_LBV_V_COUNTER_CHROMA
+-#define LBV0_LBV_V_COUNTER_CHROMA__V_COUNTER_CHROMA__SHIFT 0x0
+-#define LBV0_LBV_V_COUNTER_CHROMA__V_COUNTER_CHROMA_MASK 0x00007FFFL
+-//LBV0_LBV_SNAPSHOT_V_COUNTER_CHROMA
+-#define LBV0_LBV_SNAPSHOT_V_COUNTER_CHROMA__SNAPSHOT_V_COUNTER_CHROMA__SHIFT 0x0
+-#define LBV0_LBV_SNAPSHOT_V_COUNTER_CHROMA__SNAPSHOT_V_COUNTER_CHROMA_MASK 0x00007FFFL
+-//LBV0_LBV_INTERRUPT_MASK
+-#define LBV0_LBV_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0
+-#define LBV0_LBV_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4
+-#define LBV0_LBV_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8
+-#define LBV0_LBV_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x00000001L
+-#define LBV0_LBV_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x00000010L
+-#define LBV0_LBV_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x00000100L
+-//LBV0_LBV_VLINE_STATUS
+-#define LBV0_LBV_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0
+-#define LBV0_LBV_VLINE_STATUS__VLINE_ACK__SHIFT 0x4
+-#define LBV0_LBV_VLINE_STATUS__VLINE_STAT__SHIFT 0xc
+-#define LBV0_LBV_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10
+-#define LBV0_LBV_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11
+-#define LBV0_LBV_VLINE_STATUS__VLINE_OCCURRED_MASK 0x00000001L
+-#define LBV0_LBV_VLINE_STATUS__VLINE_ACK_MASK 0x00000010L
+-#define LBV0_LBV_VLINE_STATUS__VLINE_STAT_MASK 0x00001000L
+-#define LBV0_LBV_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x00010000L
+-#define LBV0_LBV_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x00020000L
+-//LBV0_LBV_VLINE2_STATUS
+-#define LBV0_LBV_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0
+-#define LBV0_LBV_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4
+-#define LBV0_LBV_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc
+-#define LBV0_LBV_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10
+-#define LBV0_LBV_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11
+-#define LBV0_LBV_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x00000001L
+-#define LBV0_LBV_VLINE2_STATUS__VLINE2_ACK_MASK 0x00000010L
+-#define LBV0_LBV_VLINE2_STATUS__VLINE2_STAT_MASK 0x00001000L
+-#define LBV0_LBV_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x00010000L
+-#define LBV0_LBV_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x00020000L
+-//LBV0_LBV_VBLANK_STATUS
+-#define LBV0_LBV_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0
+-#define LBV0_LBV_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4
+-#define LBV0_LBV_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc
+-#define LBV0_LBV_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10
+-#define LBV0_LBV_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11
+-#define LBV0_LBV_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x00000001L
+-#define LBV0_LBV_VBLANK_STATUS__VBLANK_ACK_MASK 0x00000010L
+-#define LBV0_LBV_VBLANK_STATUS__VBLANK_STAT_MASK 0x00001000L
+-#define LBV0_LBV_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x00010000L
+-#define LBV0_LBV_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x00020000L
+-//LBV0_LBV_SYNC_RESET_SEL
+-#define LBV0_LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0
+-#define LBV0_LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4
+-#define LBV0_LBV_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8
+-#define LBV0_LBV_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16
+-#define LBV0_LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x00000003L
+-#define LBV0_LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x00000010L
+-#define LBV0_LBV_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0x0000FF00L
+-#define LBV0_LBV_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0x00C00000L
+-//LBV0_LBV_BLACK_KEYER_R_CR
+-#define LBV0_LBV_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4
+-#define LBV0_LBV_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0x0000FFF0L
+-//LBV0_LBV_BLACK_KEYER_G_Y
+-#define LBV0_LBV_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4
+-#define LBV0_LBV_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0x0000FFF0L
+-//LBV0_LBV_BLACK_KEYER_B_CB
+-#define LBV0_LBV_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4
+-#define LBV0_LBV_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0x0000FFF0L
+-//LBV0_LBV_KEYER_COLOR_CTRL
+-#define LBV0_LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0
+-#define LBV0_LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8
+-#define LBV0_LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x00000001L
+-#define LBV0_LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x00000100L
+-//LBV0_LBV_KEYER_COLOR_R_CR
+-#define LBV0_LBV_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4
+-#define LBV0_LBV_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0x0000FFF0L
+-//LBV0_LBV_KEYER_COLOR_G_Y
+-#define LBV0_LBV_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4
+-#define LBV0_LBV_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0x0000FFF0L
+-//LBV0_LBV_KEYER_COLOR_B_CB
+-#define LBV0_LBV_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4
+-#define LBV0_LBV_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0x0000FFF0L
+-//LBV0_LBV_KEYER_COLOR_REP_R_CR
+-#define LBV0_LBV_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4
+-#define LBV0_LBV_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0x0000FFF0L
+-//LBV0_LBV_KEYER_COLOR_REP_G_Y
+-#define LBV0_LBV_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4
+-#define LBV0_LBV_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0x0000FFF0L
+-//LBV0_LBV_KEYER_COLOR_REP_B_CB
+-#define LBV0_LBV_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4
+-#define LBV0_LBV_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0x0000FFF0L
+-//LBV0_LBV_BUFFER_LEVEL_STATUS
+-#define LBV0_LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0
+-#define LBV0_LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa
+-#define LBV0_LBV_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10
+-#define LBV0_LBV_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c
+-#define LBV0_LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x0000003FL
+-#define LBV0_LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0x0000FC00L
+-#define LBV0_LBV_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0x0FFF0000L
+-#define LBV0_LBV_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xF0000000L
+-//LBV0_LBV_BUFFER_URGENCY_CTRL
+-#define LBV0_LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0
+-#define LBV0_LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10
+-#define LBV0_LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0x00000FFFL
+-#define LBV0_LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0x0FFF0000L
+-//LBV0_LBV_BUFFER_URGENCY_STATUS
+-#define LBV0_LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0
+-#define LBV0_LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10
+-#define LBV0_LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0x00000FFFL
+-#define LBV0_LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x00010000L
+-//LBV0_LBV_BUFFER_STATUS
+-#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0
+-#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4
+-#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8
+-#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc
+-#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10
+-#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14
+-#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18
+-#define LBV0_LBV_BUFFER_STATUS__LB_ENABLE_HIGH_THROUGHPUT__SHIFT 0x19
+-#define LBV0_LBV_BUFFER_STATUS__LB_HIGH_THROUGHPUT_CNTL__SHIFT 0x1a
+-#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0x0000000FL
+-#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x00000010L
+-#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x00000100L
+-#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x00001000L
+-#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x00010000L
+-#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x00100000L
+-#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x01000000L
+-#define LBV0_LBV_BUFFER_STATUS__LB_ENABLE_HIGH_THROUGHPUT_MASK 0x02000000L
+-#define LBV0_LBV_BUFFER_STATUS__LB_HIGH_THROUGHPUT_CNTL_MASK 0x1C000000L
+-//LBV0_LBV_NO_OUTSTANDING_REQ_STATUS
+-#define LBV0_LBV_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0
+-#define LBV0_LBV_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x00000001L
+-
+-
+-// addressBlock: dce_dc_sclv0_dispdec
+-//SCLV0_SCLV_COEF_RAM_SELECT
+-#define SCLV0_SCLV_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0
+-#define SCLV0_SCLV_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8
+-#define SCLV0_SCLV_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10
+-#define SCLV0_SCLV_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x00000003L
+-#define SCLV0_SCLV_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x00007F00L
+-#define SCLV0_SCLV_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x00030000L
+-//SCLV0_SCLV_COEF_RAM_TAP_DATA
+-#define SCLV0_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0
+-#define SCLV0_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
+-#define SCLV0_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10
+-#define SCLV0_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
+-#define SCLV0_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL
+-#define SCLV0_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L
+-#define SCLV0_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L
+-#define SCLV0_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L
+-//SCLV0_SCLV_MODE
+-#define SCLV0_SCLV_MODE__SCL_MODE__SHIFT 0x0
+-#define SCLV0_SCLV_MODE__SCL_MODE_C__SHIFT 0x2
+-#define SCLV0_SCLV_MODE__SCL_PSCL_EN__SHIFT 0x4
+-#define SCLV0_SCLV_MODE__SCL_PSCL_EN_C__SHIFT 0x5
+-#define SCLV0_SCLV_MODE__SCL_INTERLACE_SOURCE__SHIFT 0x8
+-#define SCLV0_SCLV_MODE__SCL_MODE_MASK 0x00000003L
+-#define SCLV0_SCLV_MODE__SCL_MODE_C_MASK 0x0000000CL
+-#define SCLV0_SCLV_MODE__SCL_PSCL_EN_MASK 0x00000010L
+-#define SCLV0_SCLV_MODE__SCL_PSCL_EN_C_MASK 0x00000020L
+-#define SCLV0_SCLV_MODE__SCL_INTERLACE_SOURCE_MASK 0x00000300L
+-//SCLV0_SCLV_TAP_CONTROL
+-#define SCLV0_SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0
+-#define SCLV0_SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x4
+-#define SCLV0_SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_C__SHIFT 0x8
+-#define SCLV0_SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_C__SHIFT 0xc
+-#define SCLV0_SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x00000007L
+-#define SCLV0_SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0x00000070L
+-#define SCLV0_SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_C_MASK 0x00000700L
+-#define SCLV0_SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_C_MASK 0x00007000L
+-//SCLV0_SCLV_CONTROL
+-#define SCLV0_SCLV_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
+-#define SCLV0_SCLV_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4
+-#define SCLV0_SCLV_CONTROL__SCL_TOTAL_PHASE__SHIFT 0x8
+-#define SCLV0_SCLV_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L
+-#define SCLV0_SCLV_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x00000010L
+-#define SCLV0_SCLV_CONTROL__SCL_TOTAL_PHASE_MASK 0x00000100L
+-//SCLV0_SCLV_MANUAL_REPLICATE_CONTROL
+-#define SCLV0_SCLV_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
+-#define SCLV0_SCLV_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
+-#define SCLV0_SCLV_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL
+-#define SCLV0_SCLV_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L
+-//SCLV0_SCLV_AUTOMATIC_MODE_CONTROL
+-#define SCLV0_SCLV_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0
+-#define SCLV0_SCLV_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10
+-#define SCLV0_SCLV_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x00000001L
+-#define SCLV0_SCLV_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x00010000L
+-//SCLV0_SCLV_HORZ_FILTER_CONTROL
+-#define SCLV0_SCLV_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+-#define SCLV0_SCLV_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
+-//SCLV0_SCLV_HORZ_FILTER_SCALE_RATIO
+-#define SCLV0_SCLV_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
+-#define SCLV0_SCLV_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL
+-//SCLV0_SCLV_HORZ_FILTER_INIT
+-#define SCLV0_SCLV_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
+-#define SCLV0_SCLV_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
+-#define SCLV0_SCLV_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL
+-#define SCLV0_SCLV_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L
+-//SCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_C
+-#define SCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0
+-#define SCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x03FFFFFFL
+-//SCLV0_SCLV_HORZ_FILTER_INIT_C
+-#define SCLV0_SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0
+-#define SCLV0_SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18
+-#define SCLV0_SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL
+-#define SCLV0_SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L
+-//SCLV0_SCLV_VERT_FILTER_CONTROL
+-#define SCLV0_SCLV_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+-#define SCLV0_SCLV_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
+-//SCLV0_SCLV_VERT_FILTER_SCALE_RATIO
+-#define SCLV0_SCLV_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
+-#define SCLV0_SCLV_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL
+-//SCLV0_SCLV_VERT_FILTER_INIT
+-#define SCLV0_SCLV_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
+-#define SCLV0_SCLV_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
+-#define SCLV0_SCLV_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL
+-#define SCLV0_SCLV_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x07000000L
+-//SCLV0_SCLV_VERT_FILTER_INIT_BOT
+-#define SCLV0_SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
+-#define SCLV0_SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
+-#define SCLV0_SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL
+-#define SCLV0_SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x07000000L
+-//SCLV0_SCLV_VERT_FILTER_SCALE_RATIO_C
+-#define SCLV0_SCLV_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0
+-#define SCLV0_SCLV_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x03FFFFFFL
+-//SCLV0_SCLV_VERT_FILTER_INIT_C
+-#define SCLV0_SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0
+-#define SCLV0_SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18
+-#define SCLV0_SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL
+-#define SCLV0_SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x07000000L
+-//SCLV0_SCLV_VERT_FILTER_INIT_BOT_C
+-#define SCLV0_SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0
+-#define SCLV0_SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18
+-#define SCLV0_SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL
+-#define SCLV0_SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x07000000L
+-//SCLV0_SCLV_ROUND_OFFSET
+-#define SCLV0_SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0
+-#define SCLV0_SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10
+-#define SCLV0_SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0x0000FFFFL
+-#define SCLV0_SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xFFFF0000L
+-//SCLV0_SCLV_UPDATE
+-#define SCLV0_SCLV_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
+-#define SCLV0_SCLV_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8
+-#define SCLV0_SCLV_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10
+-#define SCLV0_SCLV_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18
+-#define SCLV0_SCLV_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L
+-#define SCLV0_SCLV_UPDATE__SCL_UPDATE_TAKEN_MASK 0x00000100L
+-#define SCLV0_SCLV_UPDATE__SCL_UPDATE_LOCK_MASK 0x00010000L
+-#define SCLV0_SCLV_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x01000000L
+-//SCLV0_SCLV_ALU_CONTROL
+-#define SCLV0_SCLV_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0
+-#define SCLV0_SCLV_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x00000001L
+-//SCLV0_SCLV_VIEWPORT_START
+-#define SCLV0_SCLV_VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0
+-#define SCLV0_SCLV_VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10
+-#define SCLV0_SCLV_VIEWPORT_START__VIEWPORT_Y_START_MASK 0x00003FFFL
+-#define SCLV0_SCLV_VIEWPORT_START__VIEWPORT_X_START_MASK 0x3FFF0000L
+-//SCLV0_SCLV_VIEWPORT_START_SECONDARY
+-#define SCLV0_SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0
+-#define SCLV0_SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10
+-#define SCLV0_SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x00003FFFL
+-#define SCLV0_SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3FFF0000L
+-//SCLV0_SCLV_VIEWPORT_SIZE
+-#define SCLV0_SCLV_VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0
+-#define SCLV0_SCLV_VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10
+-#define SCLV0_SCLV_VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x00001FFFL
+-#define SCLV0_SCLV_VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x1FFF0000L
+-//SCLV0_SCLV_VIEWPORT_START_C
+-#define SCLV0_SCLV_VIEWPORT_START_C__VIEWPORT_Y_START_C__SHIFT 0x0
+-#define SCLV0_SCLV_VIEWPORT_START_C__VIEWPORT_X_START_C__SHIFT 0x10
+-#define SCLV0_SCLV_VIEWPORT_START_C__VIEWPORT_Y_START_C_MASK 0x00003FFFL
+-#define SCLV0_SCLV_VIEWPORT_START_C__VIEWPORT_X_START_C_MASK 0x3FFF0000L
+-//SCLV0_SCLV_VIEWPORT_START_SECONDARY_C
+-#define SCLV0_SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_Y_START_SECONDARY_C__SHIFT 0x0
+-#define SCLV0_SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_X_START_SECONDARY_C__SHIFT 0x10
+-#define SCLV0_SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_Y_START_SECONDARY_C_MASK 0x00003FFFL
+-#define SCLV0_SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_X_START_SECONDARY_C_MASK 0x3FFF0000L
+-//SCLV0_SCLV_VIEWPORT_SIZE_C
+-#define SCLV0_SCLV_VIEWPORT_SIZE_C__VIEWPORT_HEIGHT_C__SHIFT 0x0
+-#define SCLV0_SCLV_VIEWPORT_SIZE_C__VIEWPORT_WIDTH_C__SHIFT 0x10
+-#define SCLV0_SCLV_VIEWPORT_SIZE_C__VIEWPORT_HEIGHT_C_MASK 0x00001FFFL
+-#define SCLV0_SCLV_VIEWPORT_SIZE_C__VIEWPORT_WIDTH_C_MASK 0x1FFF0000L
+-//SCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT
+-#define SCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
+-#define SCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
+-#define SCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL
+-#define SCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L
+-//SCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM
+-#define SCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
+-#define SCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
+-#define SCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL
+-#define SCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L
+-//SCLV0_SCLV_MODE_CHANGE_DET1
+-#define SCLV0_SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0
+-#define SCLV0_SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4
+-#define SCLV0_SCLV_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7
+-#define SCLV0_SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x00000001L
+-#define SCLV0_SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x00000010L
+-#define SCLV0_SCLV_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0x0FFFFF80L
+-//SCLV0_SCLV_MODE_CHANGE_DET2
+-#define SCLV0_SCLV_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0
+-#define SCLV0_SCLV_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x001FFFFFL
+-//SCLV0_SCLV_MODE_CHANGE_DET3
+-#define SCLV0_SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0
+-#define SCLV0_SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10
+-#define SCLV0_SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x00003FFFL
+-#define SCLV0_SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3FFF0000L
+-//SCLV0_SCLV_MODE_CHANGE_MASK
+-#define SCLV0_SCLV_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0
+-#define SCLV0_SCLV_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x00000001L
+-//SCLV0_SCLV_HORZ_FILTER_INIT_BOT
+-#define SCLV0_SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_FRAC_BOT__SHIFT 0x0
+-#define SCLV0_SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_INT_BOT__SHIFT 0x18
+-#define SCLV0_SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_FRAC_BOT_MASK 0x00FFFFFFL
+-#define SCLV0_SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_INT_BOT_MASK 0x0F000000L
+-//SCLV0_SCLV_HORZ_FILTER_INIT_BOT_C
+-#define SCLV0_SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_FRAC_BOT_C__SHIFT 0x0
+-#define SCLV0_SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_INT_BOT_C__SHIFT 0x18
+-#define SCLV0_SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL
+-#define SCLV0_SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_INT_BOT_C_MASK 0x0F000000L
+-
+-
+-// addressBlock: dce_dc_col_man0_dispdec
+-//COL_MAN0_COL_MAN_UPDATE
+-#define COL_MAN0_COL_MAN_UPDATE__COL_MAN_UPDATE_PENDING__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_UPDATE__COL_MAN_UPDATE_TAKEN__SHIFT 0x1
+-#define COL_MAN0_COL_MAN_UPDATE__COL_MAN_UPDATE_LOCK__SHIFT 0x10
+-#define COL_MAN0_COL_MAN_UPDATE__COL_MAN_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+-#define COL_MAN0_COL_MAN_UPDATE__COL_MAN_UPDATE_PENDING_MASK 0x00000001L
+-#define COL_MAN0_COL_MAN_UPDATE__COL_MAN_UPDATE_TAKEN_MASK 0x00000002L
+-#define COL_MAN0_COL_MAN_UPDATE__COL_MAN_UPDATE_LOCK_MASK 0x00010000L
+-#define COL_MAN0_COL_MAN_UPDATE__COL_MAN_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
+-//COL_MAN0_COL_MAN_INPUT_CSC_CONTROL
+-#define COL_MAN0_COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_MODE__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_INPUT_TYPE__SHIFT 0x8
+-#define COL_MAN0_COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_CONVERSION_MODE__SHIFT 0x10
+-#define COL_MAN0_COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_MODE_MASK 0x00000003L
+-#define COL_MAN0_COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_INPUT_TYPE_MASK 0x00000300L
+-#define COL_MAN0_COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_CONVERSION_MODE_MASK 0x00010000L
+-//COL_MAN0_INPUT_CSC_C11_C12_A
+-#define COL_MAN0_INPUT_CSC_C11_C12_A__INPUT_CSC_C11_A__SHIFT 0x0
+-#define COL_MAN0_INPUT_CSC_C11_C12_A__INPUT_CSC_C12_A__SHIFT 0x10
+-#define COL_MAN0_INPUT_CSC_C11_C12_A__INPUT_CSC_C11_A_MASK 0x0000FFFFL
+-#define COL_MAN0_INPUT_CSC_C11_C12_A__INPUT_CSC_C12_A_MASK 0xFFFF0000L
+-//COL_MAN0_INPUT_CSC_C13_C14_A
+-#define COL_MAN0_INPUT_CSC_C13_C14_A__INPUT_CSC_C13_A__SHIFT 0x0
+-#define COL_MAN0_INPUT_CSC_C13_C14_A__INPUT_CSC_C14_A__SHIFT 0x10
+-#define COL_MAN0_INPUT_CSC_C13_C14_A__INPUT_CSC_C13_A_MASK 0x0000FFFFL
+-#define COL_MAN0_INPUT_CSC_C13_C14_A__INPUT_CSC_C14_A_MASK 0xFFFF0000L
+-//COL_MAN0_INPUT_CSC_C21_C22_A
+-#define COL_MAN0_INPUT_CSC_C21_C22_A__INPUT_CSC_C21_A__SHIFT 0x0
+-#define COL_MAN0_INPUT_CSC_C21_C22_A__INPUT_CSC_C22_A__SHIFT 0x10
+-#define COL_MAN0_INPUT_CSC_C21_C22_A__INPUT_CSC_C21_A_MASK 0x0000FFFFL
+-#define COL_MAN0_INPUT_CSC_C21_C22_A__INPUT_CSC_C22_A_MASK 0xFFFF0000L
+-//COL_MAN0_INPUT_CSC_C23_C24_A
+-#define COL_MAN0_INPUT_CSC_C23_C24_A__INPUT_CSC_C23_A__SHIFT 0x0
+-#define COL_MAN0_INPUT_CSC_C23_C24_A__INPUT_CSC_C24_A__SHIFT 0x10
+-#define COL_MAN0_INPUT_CSC_C23_C24_A__INPUT_CSC_C23_A_MASK 0x0000FFFFL
+-#define COL_MAN0_INPUT_CSC_C23_C24_A__INPUT_CSC_C24_A_MASK 0xFFFF0000L
+-//COL_MAN0_INPUT_CSC_C31_C32_A
+-#define COL_MAN0_INPUT_CSC_C31_C32_A__INPUT_CSC_C31_A__SHIFT 0x0
+-#define COL_MAN0_INPUT_CSC_C31_C32_A__INPUT_CSC_C32_A__SHIFT 0x10
+-#define COL_MAN0_INPUT_CSC_C31_C32_A__INPUT_CSC_C31_A_MASK 0x0000FFFFL
+-#define COL_MAN0_INPUT_CSC_C31_C32_A__INPUT_CSC_C32_A_MASK 0xFFFF0000L
+-//COL_MAN0_INPUT_CSC_C33_C34_A
+-#define COL_MAN0_INPUT_CSC_C33_C34_A__INPUT_CSC_C33_A__SHIFT 0x0
+-#define COL_MAN0_INPUT_CSC_C33_C34_A__INPUT_CSC_C34_A__SHIFT 0x10
+-#define COL_MAN0_INPUT_CSC_C33_C34_A__INPUT_CSC_C33_A_MASK 0x0000FFFFL
+-#define COL_MAN0_INPUT_CSC_C33_C34_A__INPUT_CSC_C34_A_MASK 0xFFFF0000L
+-//COL_MAN0_INPUT_CSC_C11_C12_B
+-#define COL_MAN0_INPUT_CSC_C11_C12_B__INPUT_CSC_C11_B__SHIFT 0x0
+-#define COL_MAN0_INPUT_CSC_C11_C12_B__INPUT_CSC_C12_B__SHIFT 0x10
+-#define COL_MAN0_INPUT_CSC_C11_C12_B__INPUT_CSC_C11_B_MASK 0x0000FFFFL
+-#define COL_MAN0_INPUT_CSC_C11_C12_B__INPUT_CSC_C12_B_MASK 0xFFFF0000L
+-//COL_MAN0_INPUT_CSC_C13_C14_B
+-#define COL_MAN0_INPUT_CSC_C13_C14_B__INPUT_CSC_C13_B__SHIFT 0x0
+-#define COL_MAN0_INPUT_CSC_C13_C14_B__INPUT_CSC_C14_B__SHIFT 0x10
+-#define COL_MAN0_INPUT_CSC_C13_C14_B__INPUT_CSC_C13_B_MASK 0x0000FFFFL
+-#define COL_MAN0_INPUT_CSC_C13_C14_B__INPUT_CSC_C14_B_MASK 0xFFFF0000L
+-//COL_MAN0_INPUT_CSC_C21_C22_B
+-#define COL_MAN0_INPUT_CSC_C21_C22_B__INPUT_CSC_C21_B__SHIFT 0x0
+-#define COL_MAN0_INPUT_CSC_C21_C22_B__INPUT_CSC_C22_B__SHIFT 0x10
+-#define COL_MAN0_INPUT_CSC_C21_C22_B__INPUT_CSC_C21_B_MASK 0x0000FFFFL
+-#define COL_MAN0_INPUT_CSC_C21_C22_B__INPUT_CSC_C22_B_MASK 0xFFFF0000L
+-//COL_MAN0_INPUT_CSC_C23_C24_B
+-#define COL_MAN0_INPUT_CSC_C23_C24_B__INPUT_CSC_C23_B__SHIFT 0x0
+-#define COL_MAN0_INPUT_CSC_C23_C24_B__INPUT_CSC_C24_B__SHIFT 0x10
+-#define COL_MAN0_INPUT_CSC_C23_C24_B__INPUT_CSC_C23_B_MASK 0x0000FFFFL
+-#define COL_MAN0_INPUT_CSC_C23_C24_B__INPUT_CSC_C24_B_MASK 0xFFFF0000L
+-//COL_MAN0_INPUT_CSC_C31_C32_B
+-#define COL_MAN0_INPUT_CSC_C31_C32_B__INPUT_CSC_C31_B__SHIFT 0x0
+-#define COL_MAN0_INPUT_CSC_C31_C32_B__INPUT_CSC_C32_B__SHIFT 0x10
+-#define COL_MAN0_INPUT_CSC_C31_C32_B__INPUT_CSC_C31_B_MASK 0x0000FFFFL
+-#define COL_MAN0_INPUT_CSC_C31_C32_B__INPUT_CSC_C32_B_MASK 0xFFFF0000L
+-//COL_MAN0_INPUT_CSC_C33_C34_B
+-#define COL_MAN0_INPUT_CSC_C33_C34_B__INPUT_CSC_C33_B__SHIFT 0x0
+-#define COL_MAN0_INPUT_CSC_C33_C34_B__INPUT_CSC_C34_B__SHIFT 0x10
+-#define COL_MAN0_INPUT_CSC_C33_C34_B__INPUT_CSC_C33_B_MASK 0x0000FFFFL
+-#define COL_MAN0_INPUT_CSC_C33_C34_B__INPUT_CSC_C34_B_MASK 0xFFFF0000L
+-//COL_MAN0_PRESCALE_CONTROL
+-#define COL_MAN0_PRESCALE_CONTROL__PRESCALE_MODE__SHIFT 0x0
+-#define COL_MAN0_PRESCALE_CONTROL__PRESCALE_MODE_MASK 0x00000003L
+-//COL_MAN0_PRESCALE_VALUES_R
+-#define COL_MAN0_PRESCALE_VALUES_R__PRESCALE_BIAS_R__SHIFT 0x0
+-#define COL_MAN0_PRESCALE_VALUES_R__PRESCALE_SCALE_R__SHIFT 0x10
+-#define COL_MAN0_PRESCALE_VALUES_R__PRESCALE_BIAS_R_MASK 0x0000FFFFL
+-#define COL_MAN0_PRESCALE_VALUES_R__PRESCALE_SCALE_R_MASK 0xFFFF0000L
+-//COL_MAN0_PRESCALE_VALUES_G
+-#define COL_MAN0_PRESCALE_VALUES_G__PRESCALE_BIAS_G__SHIFT 0x0
+-#define COL_MAN0_PRESCALE_VALUES_G__PRESCALE_SCALE_G__SHIFT 0x10
+-#define COL_MAN0_PRESCALE_VALUES_G__PRESCALE_BIAS_G_MASK 0x0000FFFFL
+-#define COL_MAN0_PRESCALE_VALUES_G__PRESCALE_SCALE_G_MASK 0xFFFF0000L
+-//COL_MAN0_PRESCALE_VALUES_B
+-#define COL_MAN0_PRESCALE_VALUES_B__PRESCALE_BIAS_B__SHIFT 0x0
+-#define COL_MAN0_PRESCALE_VALUES_B__PRESCALE_SCALE_B__SHIFT 0x10
+-#define COL_MAN0_PRESCALE_VALUES_B__PRESCALE_BIAS_B_MASK 0x0000FFFFL
+-#define COL_MAN0_PRESCALE_VALUES_B__PRESCALE_SCALE_B_MASK 0xFFFF0000L
+-//COL_MAN0_COL_MAN_OUTPUT_CSC_CONTROL
+-#define COL_MAN0_COL_MAN_OUTPUT_CSC_CONTROL__OUTPUT_CSC_MODE__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_OUTPUT_CSC_CONTROL__OUTPUT_CSC_MODE_MASK 0x00000007L
+-//COL_MAN0_OUTPUT_CSC_C11_C12_A
+-#define COL_MAN0_OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C11_A__SHIFT 0x0
+-#define COL_MAN0_OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C12_A__SHIFT 0x10
+-#define COL_MAN0_OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C11_A_MASK 0x0000FFFFL
+-#define COL_MAN0_OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C12_A_MASK 0xFFFF0000L
+-//COL_MAN0_OUTPUT_CSC_C13_C14_A
+-#define COL_MAN0_OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C13_A__SHIFT 0x0
+-#define COL_MAN0_OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C14_A__SHIFT 0x10
+-#define COL_MAN0_OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C13_A_MASK 0x0000FFFFL
+-#define COL_MAN0_OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C14_A_MASK 0xFFFF0000L
+-//COL_MAN0_OUTPUT_CSC_C21_C22_A
+-#define COL_MAN0_OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C21_A__SHIFT 0x0
+-#define COL_MAN0_OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C22_A__SHIFT 0x10
+-#define COL_MAN0_OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C21_A_MASK 0x0000FFFFL
+-#define COL_MAN0_OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C22_A_MASK 0xFFFF0000L
+-//COL_MAN0_OUTPUT_CSC_C23_C24_A
+-#define COL_MAN0_OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C23_A__SHIFT 0x0
+-#define COL_MAN0_OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C24_A__SHIFT 0x10
+-#define COL_MAN0_OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C23_A_MASK 0x0000FFFFL
+-#define COL_MAN0_OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C24_A_MASK 0xFFFF0000L
+-//COL_MAN0_OUTPUT_CSC_C31_C32_A
+-#define COL_MAN0_OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C31_A__SHIFT 0x0
+-#define COL_MAN0_OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C32_A__SHIFT 0x10
+-#define COL_MAN0_OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C31_A_MASK 0x0000FFFFL
+-#define COL_MAN0_OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C32_A_MASK 0xFFFF0000L
+-//COL_MAN0_OUTPUT_CSC_C33_C34_A
+-#define COL_MAN0_OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C33_A__SHIFT 0x0
+-#define COL_MAN0_OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C34_A__SHIFT 0x10
+-#define COL_MAN0_OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C33_A_MASK 0x0000FFFFL
+-#define COL_MAN0_OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C34_A_MASK 0xFFFF0000L
+-//COL_MAN0_OUTPUT_CSC_C11_C12_B
+-#define COL_MAN0_OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C11_B__SHIFT 0x0
+-#define COL_MAN0_OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C12_B__SHIFT 0x10
+-#define COL_MAN0_OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C11_B_MASK 0x0000FFFFL
+-#define COL_MAN0_OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C12_B_MASK 0xFFFF0000L
+-//COL_MAN0_OUTPUT_CSC_C13_C14_B
+-#define COL_MAN0_OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C13_B__SHIFT 0x0
+-#define COL_MAN0_OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C14_B__SHIFT 0x10
+-#define COL_MAN0_OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C13_B_MASK 0x0000FFFFL
+-#define COL_MAN0_OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C14_B_MASK 0xFFFF0000L
+-//COL_MAN0_OUTPUT_CSC_C21_C22_B
+-#define COL_MAN0_OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C21_B__SHIFT 0x0
+-#define COL_MAN0_OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C22_B__SHIFT 0x10
+-#define COL_MAN0_OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C21_B_MASK 0x0000FFFFL
+-#define COL_MAN0_OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C22_B_MASK 0xFFFF0000L
+-//COL_MAN0_OUTPUT_CSC_C23_C24_B
+-#define COL_MAN0_OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C23_B__SHIFT 0x0
+-#define COL_MAN0_OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C24_B__SHIFT 0x10
+-#define COL_MAN0_OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C23_B_MASK 0x0000FFFFL
+-#define COL_MAN0_OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C24_B_MASK 0xFFFF0000L
+-//COL_MAN0_OUTPUT_CSC_C31_C32_B
+-#define COL_MAN0_OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C31_B__SHIFT 0x0
+-#define COL_MAN0_OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C32_B__SHIFT 0x10
+-#define COL_MAN0_OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C31_B_MASK 0x0000FFFFL
+-#define COL_MAN0_OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C32_B_MASK 0xFFFF0000L
+-//COL_MAN0_OUTPUT_CSC_C33_C34_B
+-#define COL_MAN0_OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C33_B__SHIFT 0x0
+-#define COL_MAN0_OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C34_B__SHIFT 0x10
+-#define COL_MAN0_OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C33_B_MASK 0x0000FFFFL
+-#define COL_MAN0_OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C34_B_MASK 0xFFFF0000L
+-//COL_MAN0_DENORM_CLAMP_CONTROL
+-#define COL_MAN0_DENORM_CLAMP_CONTROL__DENORM_MODE__SHIFT 0x0
+-#define COL_MAN0_DENORM_CLAMP_CONTROL__DENORM_10BIT_OUT__SHIFT 0x8
+-#define COL_MAN0_DENORM_CLAMP_CONTROL__DENORM_MODE_MASK 0x00000003L
+-#define COL_MAN0_DENORM_CLAMP_CONTROL__DENORM_10BIT_OUT_MASK 0x00000100L
+-//COL_MAN0_DENORM_CLAMP_RANGE_R_CR
+-#define COL_MAN0_DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MAX_R_CR__SHIFT 0x0
+-#define COL_MAN0_DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MIN_R_CR__SHIFT 0xc
+-#define COL_MAN0_DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MAX_R_CR_MASK 0x00000FFFL
+-#define COL_MAN0_DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MIN_R_CR_MASK 0x00FFF000L
+-//COL_MAN0_DENORM_CLAMP_RANGE_G_Y
+-#define COL_MAN0_DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MAX_G_Y__SHIFT 0x0
+-#define COL_MAN0_DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MIN_G_Y__SHIFT 0xc
+-#define COL_MAN0_DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MAX_G_Y_MASK 0x00000FFFL
+-#define COL_MAN0_DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MIN_G_Y_MASK 0x00FFF000L
+-//COL_MAN0_DENORM_CLAMP_RANGE_B_CB
+-#define COL_MAN0_DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MAX_B_CB__SHIFT 0x0
+-#define COL_MAN0_DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MIN_B_CB__SHIFT 0xc
+-#define COL_MAN0_DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MAX_B_CB_MASK 0x00000FFFL
+-#define COL_MAN0_DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MIN_B_CB_MASK 0x00FFF000L
+-//COL_MAN0_COL_MAN_FP_CONVERTED_FIELD
+-#define COL_MAN0_COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_DATA__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14
+-#define COL_MAN0_COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_DATA_MASK 0x0003FFFFL
+-#define COL_MAN0_COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_INDEX_MASK 0x07F00000L
+-//COL_MAN0_COL_MAN_REGAMMA_CONTROL
+-#define COL_MAN0_COL_MAN_REGAMMA_CONTROL__COL_MAN_REGAMMA_MODE__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_REGAMMA_CONTROL__COL_MAN_REGAMMA_MODE_MASK 0x00000007L
+-//COL_MAN0_COL_MAN_REGAMMA_LUT_INDEX
+-#define COL_MAN0_COL_MAN_REGAMMA_LUT_INDEX__COL_MAN_REGAMMA_LUT_INDEX__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_REGAMMA_LUT_INDEX__COL_MAN_REGAMMA_LUT_INDEX_MASK 0x000001FFL
+-//COL_MAN0_COL_MAN_REGAMMA_LUT_DATA
+-#define COL_MAN0_COL_MAN_REGAMMA_LUT_DATA__COL_MAN_REGAMMA_LUT_DATA__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_REGAMMA_LUT_DATA__COL_MAN_REGAMMA_LUT_DATA_MASK 0x0007FFFFL
+-//COL_MAN0_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK
+-#define COL_MAN0_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK__COL_MAN_REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK__COL_MAN_REGAMMA_LUT_WRITE_EN_MASK_MASK 0x00000007L
+-//COL_MAN0_COL_MAN_REGAMMA_CNTLA_START_CNTL
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_START_CNTL__COL_MAN_REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_START_CNTL__COL_MAN_REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_START_CNTL__COL_MAN_REGAMMA_CNTLA_EXP_REGION_START_MASK 0x0003FFFFL
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_START_CNTL__COL_MAN_REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
+-//COL_MAN0_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL__COL_MAN_REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL__COL_MAN_REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
+-//COL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL1
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL1__COL_MAN_REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL1__COL_MAN_REGAMMA_CNTLA_EXP_REGION_END_MASK 0x0000FFFFL
+-//COL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL2
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL2__COL_MAN_REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL2__COL_MAN_REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL2__COL_MAN_REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL2__COL_MAN_REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xFFFF0000L
+-//COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xb
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0xf
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1b
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00003800L
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x00FF8000L
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x38000000L
+-//COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xb
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0xf
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1b
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00003800L
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x00FF8000L
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x38000000L
+-//COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xb
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0xf
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1b
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00003800L
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x00FF8000L
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x38000000L
+-//COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xb
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0xf
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1b
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00003800L
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x00FF8000L
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x38000000L
+-//COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xb
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0xf
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1b
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00003800L
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x00FF8000L
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x38000000L
+-//COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xb
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0xf
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1b
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00003800L
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x00FF8000L
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x38000000L
+-//COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xb
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0xf
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1b
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00003800L
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x00FF8000L
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x38000000L
+-//COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xb
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0xf
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1b
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00003800L
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x00FF8000L
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x38000000L
+-//COL_MAN0_COL_MAN_REGAMMA_CNTLB_START_CNTL
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_START_CNTL__COL_MAN_REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_START_CNTL__COL_MAN_REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_START_CNTL__COL_MAN_REGAMMA_CNTLB_EXP_REGION_START_MASK 0x0003FFFFL
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_START_CNTL__COL_MAN_REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
+-//COL_MAN0_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL__COL_MAN_REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL__COL_MAN_REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
+-//COL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL1
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL1__COL_MAN_REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL1__COL_MAN_REGAMMA_CNTLB_EXP_REGION_END_MASK 0x0000FFFFL
+-//COL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL2
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL2__COL_MAN_REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL2__COL_MAN_REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL2__COL_MAN_REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL2__COL_MAN_REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xFFFF0000L
+-//COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xb
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0xf
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1b
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00003800L
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x00FF8000L
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x38000000L
+-//COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xb
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0xf
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1b
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00003800L
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x00FF8000L
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x38000000L
+-//COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xb
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0xf
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1b
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00003800L
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x00FF8000L
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x38000000L
+-//COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xb
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0xf
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1b
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00003800L
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x00FF8000L
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x38000000L
+-//COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xb
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0xf
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1b
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00003800L
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x00FF8000L
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x38000000L
+-//COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xb
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0xf
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1b
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00003800L
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x00FF8000L
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x38000000L
+-//COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xb
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0xf
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1b
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00003800L
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x00FF8000L
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x38000000L
+-//COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xb
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0xf
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1b
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00003800L
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x00FF8000L
+-#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x38000000L
+-//COL_MAN0_PACK_FIFO_ERROR
+-#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_OCCURED__SHIFT 0x0
+-#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_ACK__SHIFT 0x1
+-#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_OCCURED__SHIFT 0x8
+-#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_ACK__SHIFT 0x9
+-#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_OCCURED__SHIFT 0x10
+-#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_ACK__SHIFT 0x11
+-#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_OCCURED__SHIFT 0x18
+-#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_ACK__SHIFT 0x19
+-#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_OCCURED_MASK 0x00000001L
+-#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_ACK_MASK 0x00000002L
+-#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_OCCURED_MASK 0x00000100L
+-#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_ACK_MASK 0x00000200L
+-#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_OCCURED_MASK 0x00010000L
+-#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_ACK_MASK 0x00020000L
+-#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_OCCURED_MASK 0x01000000L
+-#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_ACK_MASK 0x02000000L
+-//COL_MAN0_OUTPUT_FIFO_ERROR
+-#define COL_MAN0_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_OCCURED__SHIFT 0x0
+-#define COL_MAN0_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_ACK__SHIFT 0x1
+-#define COL_MAN0_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_OCCURED__SHIFT 0x8
+-#define COL_MAN0_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_ACK__SHIFT 0x9
+-#define COL_MAN0_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_OCCURED_MASK 0x00000001L
+-#define COL_MAN0_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_ACK_MASK 0x00000002L
+-#define COL_MAN0_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_OCCURED_MASK 0x00000100L
+-#define COL_MAN0_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_ACK_MASK 0x00000200L
+-//COL_MAN0_INPUT_GAMMA_LUT_AUTOFILL
+-#define COL_MAN0_INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL__SHIFT 0x0
+-#define COL_MAN0_INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL_DONE__SHIFT 0x1
+-#define COL_MAN0_INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL_MASK 0x00000001L
+-#define COL_MAN0_INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL_DONE_MASK 0x00000002L
+-//COL_MAN0_INPUT_GAMMA_LUT_RW_INDEX
+-#define COL_MAN0_INPUT_GAMMA_LUT_RW_INDEX__INPUT_GAMMA_LUT_RW_INDEX__SHIFT 0x0
+-#define COL_MAN0_INPUT_GAMMA_LUT_RW_INDEX__INPUT_GAMMA_LUT_RW_INDEX_MASK 0x000000FFL
+-//COL_MAN0_INPUT_GAMMA_LUT_SEQ_COLOR
+-#define COL_MAN0_INPUT_GAMMA_LUT_SEQ_COLOR__INPUT_GAMMA_LUT_SEQ_COLOR__SHIFT 0x0
+-#define COL_MAN0_INPUT_GAMMA_LUT_SEQ_COLOR__INPUT_GAMMA_LUT_SEQ_COLOR_MASK 0x0000FFFFL
+-//COL_MAN0_INPUT_GAMMA_LUT_PWL_DATA
+-#define COL_MAN0_INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_BASE__SHIFT 0x0
+-#define COL_MAN0_INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_DELTA__SHIFT 0x10
+-#define COL_MAN0_INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_BASE_MASK 0x0000FFFFL
+-#define COL_MAN0_INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_DELTA_MASK 0xFFFF0000L
+-//COL_MAN0_INPUT_GAMMA_LUT_30_COLOR
+-#define COL_MAN0_INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_BLUE__SHIFT 0x0
+-#define COL_MAN0_INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_GREEN__SHIFT 0xa
+-#define COL_MAN0_INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_RED__SHIFT 0x14
+-#define COL_MAN0_INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_BLUE_MASK 0x000003FFL
+-#define COL_MAN0_INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_GREEN_MASK 0x000FFC00L
+-#define COL_MAN0_INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_RED_MASK 0x3FF00000L
+-//COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1
+-#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_MODE__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_LUT_10BIT_BYPASS_EN__SHIFT 0x1a
+-#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_MODE_MASK 0x00000003L
+-#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_LUT_10BIT_BYPASS_EN_MASK 0x04000000L
+-//COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2
+-#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_B__SHIFT 0x1
+-#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_SIGNED_EN__SHIFT 0x5
+-#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_FORMAT__SHIFT 0x6
+-#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_G__SHIFT 0x8
+-#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_SIGNED_EN__SHIFT 0xc
+-#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_FORMAT__SHIFT 0xd
+-#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_R__SHIFT 0xf
+-#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_SIGNED_EN__SHIFT 0x13
+-#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_FORMAT__SHIFT 0x14
+-#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_RW_MODE__SHIFT 0x16
+-#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_WRITE_EN_MASK__SHIFT 0x17
+-#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_VGA_ACCESS_ENABLE__SHIFT 0x1a
+-#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x1b
+-#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_B_MASK 0x0000001EL
+-#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_SIGNED_EN_MASK 0x00000020L
+-#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_FORMAT_MASK 0x000000C0L
+-#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_G_MASK 0x00000F00L
+-#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_SIGNED_EN_MASK 0x00001000L
+-#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_FORMAT_MASK 0x00006000L
+-#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_R_MASK 0x00078000L
+-#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_SIGNED_EN_MASK 0x00080000L
+-#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_FORMAT_MASK 0x00300000L
+-#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_RW_MODE_MASK 0x00400000L
+-#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_WRITE_EN_MASK_MASK 0x03800000L
+-#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_VGA_ACCESS_ENABLE_MASK 0x04000000L
+-#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x08000000L
+-//COL_MAN0_INPUT_GAMMA_BW_OFFSETS_B
+-#define COL_MAN0_INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_BLACK_OFFSET_B__SHIFT 0x0
+-#define COL_MAN0_INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_WHITE_OFFSET_B__SHIFT 0x10
+-#define COL_MAN0_INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_BLACK_OFFSET_B_MASK 0x0000FFFFL
+-#define COL_MAN0_INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_WHITE_OFFSET_B_MASK 0xFFFF0000L
+-//COL_MAN0_INPUT_GAMMA_BW_OFFSETS_G
+-#define COL_MAN0_INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_BLACK_OFFSET_G__SHIFT 0x0
+-#define COL_MAN0_INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_WHITE_OFFSET_G__SHIFT 0x10
+-#define COL_MAN0_INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_BLACK_OFFSET_G_MASK 0x0000FFFFL
+-#define COL_MAN0_INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_WHITE_OFFSET_G_MASK 0xFFFF0000L
+-//COL_MAN0_INPUT_GAMMA_BW_OFFSETS_R
+-#define COL_MAN0_INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_BLACK_OFFSET_R__SHIFT 0x0
+-#define COL_MAN0_INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_WHITE_OFFSET_R__SHIFT 0x10
+-#define COL_MAN0_INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_BLACK_OFFSET_R_MASK 0x0000FFFFL
+-#define COL_MAN0_INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_WHITE_OFFSET_R_MASK 0xFFFF0000L
+-//COL_MAN0_COL_MAN_DEGAMMA_CONTROL
+-#define COL_MAN0_COL_MAN_DEGAMMA_CONTROL__COL_MAN_DEGAMMA_MODE__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_DEGAMMA_CONTROL__COL_MAN_DEGAMMA_MODE_MASK 0x00000003L
+-//COL_MAN0_COL_MAN_GAMUT_REMAP_CONTROL
+-#define COL_MAN0_COL_MAN_GAMUT_REMAP_CONTROL__COL_MAN_GAMUT_REMAP_MODE__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_GAMUT_REMAP_CONTROL__COL_MAN_GAMUT_REMAP_MODE_MASK 0x00000003L
+-//COL_MAN0_COL_MAN_GAMUT_REMAP_C11_C12
+-#define COL_MAN0_COL_MAN_GAMUT_REMAP_C11_C12__COL_MAN_GAMUT_REMAP_C11__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_GAMUT_REMAP_C11_C12__COL_MAN_GAMUT_REMAP_C12__SHIFT 0x10
+-#define COL_MAN0_COL_MAN_GAMUT_REMAP_C11_C12__COL_MAN_GAMUT_REMAP_C11_MASK 0x0000FFFFL
+-#define COL_MAN0_COL_MAN_GAMUT_REMAP_C11_C12__COL_MAN_GAMUT_REMAP_C12_MASK 0xFFFF0000L
+-//COL_MAN0_COL_MAN_GAMUT_REMAP_C13_C14
+-#define COL_MAN0_COL_MAN_GAMUT_REMAP_C13_C14__COL_MAN_GAMUT_REMAP_C13__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_GAMUT_REMAP_C13_C14__COL_MAN_GAMUT_REMAP_C14__SHIFT 0x10
+-#define COL_MAN0_COL_MAN_GAMUT_REMAP_C13_C14__COL_MAN_GAMUT_REMAP_C13_MASK 0x0000FFFFL
+-#define COL_MAN0_COL_MAN_GAMUT_REMAP_C13_C14__COL_MAN_GAMUT_REMAP_C14_MASK 0xFFFF0000L
+-//COL_MAN0_COL_MAN_GAMUT_REMAP_C21_C22
+-#define COL_MAN0_COL_MAN_GAMUT_REMAP_C21_C22__COL_MAN_GAMUT_REMAP_C21__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_GAMUT_REMAP_C21_C22__COL_MAN_GAMUT_REMAP_C22__SHIFT 0x10
+-#define COL_MAN0_COL_MAN_GAMUT_REMAP_C21_C22__COL_MAN_GAMUT_REMAP_C21_MASK 0x0000FFFFL
+-#define COL_MAN0_COL_MAN_GAMUT_REMAP_C21_C22__COL_MAN_GAMUT_REMAP_C22_MASK 0xFFFF0000L
+-//COL_MAN0_COL_MAN_GAMUT_REMAP_C23_C24
+-#define COL_MAN0_COL_MAN_GAMUT_REMAP_C23_C24__COL_MAN_GAMUT_REMAP_C23__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_GAMUT_REMAP_C23_C24__COL_MAN_GAMUT_REMAP_C24__SHIFT 0x10
+-#define COL_MAN0_COL_MAN_GAMUT_REMAP_C23_C24__COL_MAN_GAMUT_REMAP_C23_MASK 0x0000FFFFL
+-#define COL_MAN0_COL_MAN_GAMUT_REMAP_C23_C24__COL_MAN_GAMUT_REMAP_C24_MASK 0xFFFF0000L
+-//COL_MAN0_COL_MAN_GAMUT_REMAP_C31_C32
+-#define COL_MAN0_COL_MAN_GAMUT_REMAP_C31_C32__COL_MAN_GAMUT_REMAP_C31__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_GAMUT_REMAP_C31_C32__COL_MAN_GAMUT_REMAP_C32__SHIFT 0x10
+-#define COL_MAN0_COL_MAN_GAMUT_REMAP_C31_C32__COL_MAN_GAMUT_REMAP_C31_MASK 0x0000FFFFL
+-#define COL_MAN0_COL_MAN_GAMUT_REMAP_C31_C32__COL_MAN_GAMUT_REMAP_C32_MASK 0xFFFF0000L
+-//COL_MAN0_COL_MAN_GAMUT_REMAP_C33_C34
+-#define COL_MAN0_COL_MAN_GAMUT_REMAP_C33_C34__COL_MAN_GAMUT_REMAP_C33__SHIFT 0x0
+-#define COL_MAN0_COL_MAN_GAMUT_REMAP_C33_C34__COL_MAN_GAMUT_REMAP_C34__SHIFT 0x10
+-#define COL_MAN0_COL_MAN_GAMUT_REMAP_C33_C34__COL_MAN_GAMUT_REMAP_C33_MASK 0x0000FFFFL
+-#define COL_MAN0_COL_MAN_GAMUT_REMAP_C33_C34__COL_MAN_GAMUT_REMAP_C34_MASK 0xFFFF0000L
+-
+-
+-// addressBlock: dce_dc_dcfev0_dispdec
+-//DCFEV0_DCFEV_CLOCK_CONTROL
+-#define DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_R_DCFEV_GATE_DISABLE__SHIFT 0x3
+-#define DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_G_UNP_GATE_DISABLE__SHIFT 0x7
+-#define DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_G_SCLV_GATE_DISABLE__SHIFT 0x9
+-#define DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_G_COL_MAN_GATE_DISABLE__SHIFT 0xb
+-#define DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_G_PSCLV_GATE_DISABLE__SHIFT 0xd
+-#define DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_G_CRTC_GATE_DISABLE__SHIFT 0xf
+-#define DCFEV0_DCFEV_CLOCK_CONTROL__DCFEV_TEST_CLK_SEL__SHIFT 0x18
+-#define DCFEV0_DCFEV_CLOCK_CONTROL__DCFEV_CLOCK_ENABLE__SHIFT 0x1f
+-#define DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_R_DCFEV_GATE_DISABLE_MASK 0x00000008L
+-#define DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_G_UNP_GATE_DISABLE_MASK 0x00000080L
+-#define DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_G_SCLV_GATE_DISABLE_MASK 0x00000200L
+-#define DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_G_COL_MAN_GATE_DISABLE_MASK 0x00000800L
+-#define DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_G_PSCLV_GATE_DISABLE_MASK 0x00002000L
+-#define DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_G_CRTC_GATE_DISABLE_MASK 0x00008000L
+-#define DCFEV0_DCFEV_CLOCK_CONTROL__DCFEV_TEST_CLK_SEL_MASK 0x1F000000L
+-#define DCFEV0_DCFEV_CLOCK_CONTROL__DCFEV_CLOCK_ENABLE_MASK 0x80000000L
+-//DCFEV0_DCFEV_SOFT_RESET
+-#define DCFEV0_DCFEV_SOFT_RESET__UNP_PIXPIPE_SOFT_RESET__SHIFT 0x0
+-#define DCFEV0_DCFEV_SOFT_RESET__UNP_REQ_SOFT_RESET__SHIFT 0x1
+-#define DCFEV0_DCFEV_SOFT_RESET__SCLV_ALU_SOFT_RESET__SHIFT 0x2
+-#define DCFEV0_DCFEV_SOFT_RESET__SCLV_SOFT_RESET__SHIFT 0x3
+-#define DCFEV0_DCFEV_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4
+-#define DCFEV0_DCFEV_SOFT_RESET__PSCLV_SOFT_RESET__SHIFT 0x5
+-#define DCFEV0_DCFEV_SOFT_RESET__COL_MAN_SOFT_RESET__SHIFT 0x6
+-#define DCFEV0_DCFEV_SOFT_RESET__UNP_PIXPIPE_SOFT_RESET_MASK 0x00000001L
+-#define DCFEV0_DCFEV_SOFT_RESET__UNP_REQ_SOFT_RESET_MASK 0x00000002L
+-#define DCFEV0_DCFEV_SOFT_RESET__SCLV_ALU_SOFT_RESET_MASK 0x00000004L
+-#define DCFEV0_DCFEV_SOFT_RESET__SCLV_SOFT_RESET_MASK 0x00000008L
+-#define DCFEV0_DCFEV_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x00000010L
+-#define DCFEV0_DCFEV_SOFT_RESET__PSCLV_SOFT_RESET_MASK 0x00000020L
+-#define DCFEV0_DCFEV_SOFT_RESET__COL_MAN_SOFT_RESET_MASK 0x00000040L
+-//DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL
+-#define DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x3
+-#define DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVL_GATE_DIS__SHIFT 0x4
+-#define DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVC_GATE_DIS__SHIFT 0x5
+-#define DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SOFT_RESET__SHIFT 0x6
+-#define DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_TEST_CLK_SEL__SHIFT 0x18
+-#define DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_BUFFER_MODE__SHIFT 0x1f
+-#define DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SCLK_G_DMIFTRK_GATE_DIS_MASK 0x00000008L
+-#define DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVL_GATE_DIS_MASK 0x00000010L
+-#define DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVC_GATE_DIS_MASK 0x00000020L
+-#define DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SOFT_RESET_MASK 0x00000040L
+-#define DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_TEST_CLK_SEL_MASK 0x1F000000L
+-#define DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_BUFFER_MODE_MASK 0x80000000L
+-//DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_SEL__SHIFT 0x0
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_0_FORCE__SHIFT 0x2
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_1_FORCE__SHIFT 0x3
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_2_FORCE__SHIFT 0x4
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_3_FORCE__SHIFT 0x5
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_4_FORCE__SHIFT 0x6
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_0_FORCE__SHIFT 0x7
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_1_FORCE__SHIFT 0x8
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_2_FORCE__SHIFT 0x9
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_3_FORCE__SHIFT 0xa
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_4_FORCE__SHIFT 0xb
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_SEL_MASK 0x00000003L
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_0_FORCE_MASK 0x00000004L
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_1_FORCE_MASK 0x00000008L
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_2_FORCE_MASK 0x00000010L
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_3_FORCE_MASK 0x00000020L
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_4_FORCE_MASK 0x00000040L
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_0_FORCE_MASK 0x00000080L
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_1_FORCE_MASK 0x00000100L
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_2_FORCE_MASK 0x00000200L
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_3_FORCE_MASK 0x00000400L
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_4_FORCE_MASK 0x00000800L
+-//DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_0_STATE__SHIFT 0x0
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_1_STATE__SHIFT 0x2
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_2_STATE__SHIFT 0x4
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_3_STATE__SHIFT 0x6
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_4_STATE__SHIFT 0x8
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_0_STATE__SHIFT 0xa
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_1_STATE__SHIFT 0xc
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_2_STATE__SHIFT 0xe
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_3_STATE__SHIFT 0x10
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_4_STATE__SHIFT 0x12
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_0_STATE_MASK 0x00000003L
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_1_STATE_MASK 0x0000000CL
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_2_STATE_MASK 0x00000030L
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_3_STATE_MASK 0x000000C0L
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_4_STATE_MASK 0x00000300L
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_0_STATE_MASK 0x00000C00L
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_1_STATE_MASK 0x00003000L
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_2_STATE_MASK 0x0000C000L
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_3_STATE_MASK 0x00030000L
+-#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_4_STATE_MASK 0x000C0000L
+-//DCFEV0_DCFEV_MEM_PWR_CTRL
+-#define DCFEV0_DCFEV_MEM_PWR_CTRL__COL_MAN_REGAMMA_MEM_PWR_FORCE__SHIFT 0x0
+-#define DCFEV0_DCFEV_MEM_PWR_CTRL__COL_MAN_REGAMMA_MEM_PWR_DIS__SHIFT 0x2
+-#define DCFEV0_DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_FORCE__SHIFT 0x3
+-#define DCFEV0_DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_DIS__SHIFT 0x5
+-#define DCFEV0_DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_FORCE__SHIFT 0x6
+-#define DCFEV0_DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_DIS__SHIFT 0x8
+-#define DCFEV0_DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_FORCE__SHIFT 0x9
+-#define DCFEV0_DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_DIS__SHIFT 0xb
+-#define DCFEV0_DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_FORCE__SHIFT 0xc
+-#define DCFEV0_DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_DIS__SHIFT 0xe
+-#define DCFEV0_DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_FORCE__SHIFT 0xf
+-#define DCFEV0_DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_DIS__SHIFT 0x11
+-#define DCFEV0_DCFEV_MEM_PWR_CTRL__COL_MAN_REGAMMA_MEM_PWR_FORCE_MASK 0x00000003L
+-#define DCFEV0_DCFEV_MEM_PWR_CTRL__COL_MAN_REGAMMA_MEM_PWR_DIS_MASK 0x00000004L
+-#define DCFEV0_DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_FORCE_MASK 0x00000018L
+-#define DCFEV0_DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_DIS_MASK 0x00000020L
+-#define DCFEV0_DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_FORCE_MASK 0x000000C0L
+-#define DCFEV0_DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_DIS_MASK 0x00000100L
+-#define DCFEV0_DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_FORCE_MASK 0x00000600L
+-#define DCFEV0_DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_DIS_MASK 0x00000800L
+-#define DCFEV0_DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_FORCE_MASK 0x00003000L
+-#define DCFEV0_DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_DIS_MASK 0x00004000L
+-#define DCFEV0_DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_FORCE_MASK 0x00018000L
+-#define DCFEV0_DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_DIS_MASK 0x00020000L
+-//DCFEV0_DCFEV_MEM_PWR_CTRL2
+-#define DCFEV0_DCFEV_MEM_PWR_CTRL2__COL_MAN_REGAMMA_MEM_PWR_MODE_SEL__SHIFT 0x0
+-#define DCFEV0_DCFEV_MEM_PWR_CTRL2__COL_MAN_INPUT_GAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2
+-#define DCFEV0_DCFEV_MEM_PWR_CTRL2__SCLV_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4
+-#define DCFEV0_DCFEV_MEM_PWR_CTRL2__LBV_MEM_PWR_MODE_SEL__SHIFT 0x6
+-#define DCFEV0_DCFEV_MEM_PWR_CTRL2__COL_MAN_REGAMMA_MEM_PWR_MODE_SEL_MASK 0x00000003L
+-#define DCFEV0_DCFEV_MEM_PWR_CTRL2__COL_MAN_INPUT_GAMMA_MEM_PWR_MODE_SEL_MASK 0x0000000CL
+-#define DCFEV0_DCFEV_MEM_PWR_CTRL2__SCLV_COEFF_MEM_PWR_MODE_SEL_MASK 0x00000030L
+-#define DCFEV0_DCFEV_MEM_PWR_CTRL2__LBV_MEM_PWR_MODE_SEL_MASK 0x000000C0L
+-//DCFEV0_DCFEV_MEM_PWR_STATUS
+-#define DCFEV0_DCFEV_MEM_PWR_STATUS__COL_MAN_REGAMMA_MEM_PWR_STATE__SHIFT 0x0
+-#define DCFEV0_DCFEV_MEM_PWR_STATUS__COL_MAN_INPUT_GAMMA_MEM_PWR_STATE__SHIFT 0x2
+-#define DCFEV0_DCFEV_MEM_PWR_STATUS__SCLV_COEFF_MEM_PWR_STATE__SHIFT 0x4
+-#define DCFEV0_DCFEV_MEM_PWR_STATUS__LBV0_MEM_PWR_STATE__SHIFT 0x6
+-#define DCFEV0_DCFEV_MEM_PWR_STATUS__LBV1_MEM_PWR_STATE__SHIFT 0x8
+-#define DCFEV0_DCFEV_MEM_PWR_STATUS__LBV2_MEM_PWR_STATE__SHIFT 0xa
+-#define DCFEV0_DCFEV_MEM_PWR_STATUS__LBV3_MEM_PWR_STATE__SHIFT 0xc
+-#define DCFEV0_DCFEV_MEM_PWR_STATUS__COL_MAN_REGAMMA_MEM_PWR_STATE_MASK 0x00000003L
+-#define DCFEV0_DCFEV_MEM_PWR_STATUS__COL_MAN_INPUT_GAMMA_MEM_PWR_STATE_MASK 0x0000000CL
+-#define DCFEV0_DCFEV_MEM_PWR_STATUS__SCLV_COEFF_MEM_PWR_STATE_MASK 0x00000030L
+-#define DCFEV0_DCFEV_MEM_PWR_STATUS__LBV0_MEM_PWR_STATE_MASK 0x000000C0L
+-#define DCFEV0_DCFEV_MEM_PWR_STATUS__LBV1_MEM_PWR_STATE_MASK 0x00000300L
+-#define DCFEV0_DCFEV_MEM_PWR_STATUS__LBV2_MEM_PWR_STATE_MASK 0x00000C00L
+-#define DCFEV0_DCFEV_MEM_PWR_STATUS__LBV3_MEM_PWR_STATE_MASK 0x00003000L
+-//DCFEV0_DCFEV_L_FLUSH
+-#define DCFEV0_DCFEV_L_FLUSH__FLUSH_OCCURED__SHIFT 0x0
+-#define DCFEV0_DCFEV_L_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT 0x1
+-#define DCFEV0_DCFEV_L_FLUSH__FLUSH_DEEP__SHIFT 0x2
+-#define DCFEV0_DCFEV_L_FLUSH__CLEAR_FLUSH_DEEP__SHIFT 0x3
+-#define DCFEV0_DCFEV_L_FLUSH__ALL_MC_REQ_RET__SHIFT 0x4
+-#define DCFEV0_DCFEV_L_FLUSH__FLUSH_OCCURED_MASK 0x00000001L
+-#define DCFEV0_DCFEV_L_FLUSH__CLEAR_FLUSH_OCCURED_MASK 0x00000002L
+-#define DCFEV0_DCFEV_L_FLUSH__FLUSH_DEEP_MASK 0x00000004L
+-#define DCFEV0_DCFEV_L_FLUSH__CLEAR_FLUSH_DEEP_MASK 0x00000008L
+-#define DCFEV0_DCFEV_L_FLUSH__ALL_MC_REQ_RET_MASK 0x00000010L
+-//DCFEV0_DCFEV_C_FLUSH
+-#define DCFEV0_DCFEV_C_FLUSH__FLUSH_OCCURED__SHIFT 0x0
+-#define DCFEV0_DCFEV_C_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT 0x1
+-#define DCFEV0_DCFEV_C_FLUSH__FLUSH_DEEP__SHIFT 0x2
+-#define DCFEV0_DCFEV_C_FLUSH__CLEAR_FLUSH_DEEP__SHIFT 0x3
+-#define DCFEV0_DCFEV_C_FLUSH__ALL_MC_REQ_RET__SHIFT 0x4
+-#define DCFEV0_DCFEV_C_FLUSH__FLUSH_OCCURED_MASK 0x00000001L
+-#define DCFEV0_DCFEV_C_FLUSH__CLEAR_FLUSH_OCCURED_MASK 0x00000002L
+-#define DCFEV0_DCFEV_C_FLUSH__FLUSH_DEEP_MASK 0x00000004L
+-#define DCFEV0_DCFEV_C_FLUSH__CLEAR_FLUSH_DEEP_MASK 0x00000008L
+-#define DCFEV0_DCFEV_C_FLUSH__ALL_MC_REQ_RET_MASK 0x00000010L
+-//DCFEV0_DCFEV_MISC
+-#define DCFEV0_DCFEV_MISC__DCFEV_DPG_ALLOW_SR_ECO_EN__SHIFT 0x0
+-#define DCFEV0_DCFEV_MISC__DCFEV_DPG_ALLOW_SR_ECO_EN_MASK 0x00000001L
+-
+-
+-// addressBlock: dce_dc_dc_perfmon11_dispdec
+-//DC_PERFMON11_PERFCOUNTER_CNTL
+-#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+-#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+-#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+-#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+-#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+-#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
+-#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+-#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+-#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+-#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+-#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+-#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
+-#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+-#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+-#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+-#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+-#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+-#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+-#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
+-#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+-#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+-#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+-#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+-#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+-#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
+-#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+-//DC_PERFMON11_PERFCOUNTER_CNTL2
+-#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+-#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+-#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+-#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+-#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+-#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+-#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+-#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+-//DC_PERFMON11_PERFCOUNTER_STATE
+-#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+-#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+-#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+-#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+-#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+-#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+-#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+-#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+-#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+-#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+-#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+-#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+-#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+-#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+-#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+-#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+-#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+-#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+-#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+-#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+-#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+-#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+-#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+-#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+-#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+-#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+-#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+-#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+-#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+-#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+-#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+-#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+-//DC_PERFMON11_PERFMON_CNTL
+-#define DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+-#define DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+-#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+-#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+-#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+-#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+-#define DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+-#define DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+-#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+-#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+-#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+-#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+-//DC_PERFMON11_PERFMON_CNTL2
+-#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+-#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+-#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+-#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+-#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+-#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+-#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+-#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+-//DC_PERFMON11_PERFMON_CVALUE_INT_MISC
+-#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+-#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+-#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+-#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+-#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+-#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+-#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+-#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+-#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+-#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+-#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+-#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+-#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+-#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+-#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+-#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+-#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+-#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+-#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+-#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+-#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+-#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+-#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+-#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+-#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+-#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+-#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+-#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+-#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+-#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+-#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+-#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+-#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+-#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+-//DC_PERFMON11_PERFMON_CVALUE_LOW
+-#define DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+-#define DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+-//DC_PERFMON11_PERFMON_HI
+-#define DC_PERFMON11_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+-#define DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+-#define DC_PERFMON11_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+-#define DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+-//DC_PERFMON11_PERFMON_LOW
+-#define DC_PERFMON11_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+-#define DC_PERFMON11_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dmifv_pg0_dispdec
+-//DMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1
+-#define DMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
+-#define DMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
+-#define DMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0x0000FFFFL
+-#define DMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xFFFF0000L
+-//DMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2
+-#define DMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
+-#define DMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
+-#define DMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0x0000FFFFL
+-#define DMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xFFFF0000L
+-//DMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL
+-#define DMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
+-#define DMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
+-#define DMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x10
+-#define DMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x18
+-#define DMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000003L
+-#define DMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x00000300L
+-#define DMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00030000L
+-#define DMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x01000000L
+-//DMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL
+-#define DMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
+-#define DMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
+-#define DMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0x0000FFFFL
+-#define DMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xFFFF0000L
+-//DMIFV_PG0_DPGV0_PIPE_DPM_CONTROL
+-#define DMIFV_PG0_DPGV0_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x0
+-#define DMIFV_PG0_DPGV0_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x00000001L
+-//DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL
+-#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
+-#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
+-#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
+-#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
+-#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
+-#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x8
+-#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x9
+-#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
+-#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
+-#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x10
+-#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L
+-#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L
+-#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x00000020L
+-#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x00000040L
+-#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x00000080L
+-#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x00000100L
+-#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x00000200L
+-#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x00000400L
+-#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x00000800L
+-#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xFFFF0000L
+-//DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL
+-#define DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x0
+-#define DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
+-#define DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
+-#define DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
+-#define DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
+-#define DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x10
+-#define DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x00000001L
+-#define DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L
+-#define DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x00000100L
+-#define DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000200L
+-#define DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000400L
+-#define DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xFFFF0000L
+-//DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH
+-#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x0
+-#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x4
+-#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x5
+-#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x6
+-#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x7
+-#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x8
+-#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x9
+-#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0xa
+-#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0xb
+-#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x00000001L
+-#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x00000010L
+-#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x00000020L
+-#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x00000040L
+-#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x00000080L
+-#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x00000100L
+-#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x00000200L
+-#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x00000400L
+-#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x00000800L
+-//DMIFV_PG0_DPGV0_REPEATER_PROGRAM
+-#define DMIFV_PG0_DPGV0_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
+-#define DMIFV_PG0_DPGV0_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
+-#define DMIFV_PG0_DPGV0_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x00000007L
+-#define DMIFV_PG0_DPGV0_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x00000070L
+-//DMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL
+-#define DMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0
+-#define DMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x00000001L
+-//DMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1
+-#define DMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
+-#define DMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
+-#define DMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0x0000FFFFL
+-#define DMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xFFFF0000L
+-//DMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2
+-#define DMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
+-#define DMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
+-#define DMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0x0000FFFFL
+-#define DMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xFFFF0000L
+-//DMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL
+-#define DMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
+-#define DMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
+-#define DMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x10
+-#define DMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x18
+-#define DMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000003L
+-#define DMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x00000300L
+-#define DMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00030000L
+-#define DMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x01000000L
+-//DMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL
+-#define DMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
+-#define DMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
+-#define DMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0x0000FFFFL
+-#define DMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xFFFF0000L
+-//DMIFV_PG0_DPGV1_PIPE_DPM_CONTROL
+-#define DMIFV_PG0_DPGV1_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x0
+-#define DMIFV_PG0_DPGV1_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x00000001L
+-//DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL
+-#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
+-#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
+-#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
+-#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
+-#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
+-#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x8
+-#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x9
+-#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
+-#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
+-#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x10
+-#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L
+-#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L
+-#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x00000020L
+-#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x00000040L
+-#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x00000080L
+-#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x00000100L
+-#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x00000200L
+-#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x00000400L
+-#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x00000800L
+-#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xFFFF0000L
+-//DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL
+-#define DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x0
+-#define DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
+-#define DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
+-#define DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
+-#define DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
+-#define DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x10
+-#define DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x00000001L
+-#define DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L
+-#define DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x00000100L
+-#define DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000200L
+-#define DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000400L
+-#define DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xFFFF0000L
+-//DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH
+-#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x0
+-#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x4
+-#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x5
+-#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x6
+-#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x7
+-#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x8
+-#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x9
+-#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0xa
+-#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0xb
+-#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x00000001L
+-#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x00000010L
+-#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x00000020L
+-#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x00000040L
+-#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x00000080L
+-#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x00000100L
+-#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x00000200L
+-#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x00000400L
+-#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x00000800L
+-//DMIFV_PG0_DPGV1_REPEATER_PROGRAM
+-#define DMIFV_PG0_DPGV1_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
+-#define DMIFV_PG0_DPGV1_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
+-#define DMIFV_PG0_DPGV1_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x00000007L
+-#define DMIFV_PG0_DPGV1_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x00000070L
+-//DMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL
+-#define DMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0
+-#define DMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x00000001L
+-
+-
+-// addressBlock: dce_dc_blndv0_dispdec
+-//BLNDV0_BLNDV_CONTROL
+-#define BLNDV0_BLNDV_CONTROL__BLND_GLOBAL_GAIN__SHIFT 0x0
+-#define BLNDV0_BLNDV_CONTROL__BLND_MODE__SHIFT 0x8
+-#define BLNDV0_BLNDV_CONTROL__BLND_STEREO_TYPE__SHIFT 0xa
+-#define BLNDV0_BLNDV_CONTROL__BLND_STEREO_POLARITY__SHIFT 0xc
+-#define BLNDV0_BLNDV_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT 0xd
+-#define BLNDV0_BLNDV_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10
+-#define BLNDV0_BLNDV_CONTROL__BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x12
+-#define BLNDV0_BLNDV_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14
+-#define BLNDV0_BLNDV_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18
+-#define BLNDV0_BLNDV_CONTROL__BLND_GLOBAL_GAIN_MASK 0x000000FFL
+-#define BLNDV0_BLNDV_CONTROL__BLND_MODE_MASK 0x00000300L
+-#define BLNDV0_BLNDV_CONTROL__BLND_STEREO_TYPE_MASK 0x00000C00L
+-#define BLNDV0_BLNDV_CONTROL__BLND_STEREO_POLARITY_MASK 0x00001000L
+-#define BLNDV0_BLNDV_CONTROL__BLND_FEEDTHROUGH_EN_MASK 0x00002000L
+-#define BLNDV0_BLNDV_CONTROL__BLND_ALPHA_MODE_MASK 0x00030000L
+-#define BLNDV0_BLNDV_CONTROL__BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00040000L
+-#define BLNDV0_BLNDV_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x00100000L
+-#define BLNDV0_BLNDV_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xFF000000L
+-//BLNDV0_BLNDV_SM_CONTROL2
+-#define BLNDV0_BLNDV_SM_CONTROL2__SM_MODE__SHIFT 0x0
+-#define BLNDV0_BLNDV_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4
+-#define BLNDV0_BLNDV_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5
+-#define BLNDV0_BLNDV_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
+-#define BLNDV0_BLNDV_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
+-#define BLNDV0_BLNDV_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18
+-#define BLNDV0_BLNDV_SM_CONTROL2__SM_MODE_MASK 0x00000007L
+-#define BLNDV0_BLNDV_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x00000010L
+-#define BLNDV0_BLNDV_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x00000020L
+-#define BLNDV0_BLNDV_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L
+-#define BLNDV0_BLNDV_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L
+-#define BLNDV0_BLNDV_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x01000000L
+-//BLNDV0_BLNDV_CONTROL2
+-#define BLNDV0_BLNDV_CONTROL2__PTI_ENABLE__SHIFT 0x0
+-#define BLNDV0_BLNDV_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT 0x4
+-#define BLNDV0_BLNDV_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT 0x6
+-#define BLNDV0_BLNDV_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT 0x7
+-#define BLNDV0_BLNDV_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT 0x8
+-#define BLNDV0_BLNDV_CONTROL2__PTI_ENABLE_MASK 0x00000001L
+-#define BLNDV0_BLNDV_CONTROL2__PTI_NEW_PIXEL_GAP_MASK 0x00000030L
+-#define BLNDV0_BLNDV_CONTROL2__BLND_NEW_PIXEL_MODE_MASK 0x00000040L
+-#define BLNDV0_BLNDV_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK 0x00000080L
+-#define BLNDV0_BLNDV_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK 0x00000100L
+-//BLNDV0_BLNDV_UPDATE
+-#define BLNDV0_BLNDV_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0
+-#define BLNDV0_BLNDV_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8
+-#define BLNDV0_BLNDV_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10
+-#define BLNDV0_BLNDV_UPDATE__BLND_UPDATE_PENDING_MASK 0x00000001L
+-#define BLNDV0_BLNDV_UPDATE__BLND_UPDATE_TAKEN_MASK 0x00000100L
+-#define BLNDV0_BLNDV_UPDATE__BLND_UPDATE_LOCK_MASK 0x00010000L
+-//BLNDV0_BLNDV_UNDERFLOW_INTERRUPT
+-#define BLNDV0_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0
+-#define BLNDV0_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8
+-#define BLNDV0_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc
+-#define BLNDV0_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10
+-#define BLNDV0_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x00000001L
+-#define BLNDV0_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x00000100L
+-#define BLNDV0_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x00001000L
+-#define BLNDV0_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x00030000L
+-//BLNDV0_BLNDV_V_UPDATE_LOCK
+-#define BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0
+-#define BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1
+-#define BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10
+-#define BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c
+-#define BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT 0x1d
+-#define BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT 0x1f
+-#define BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x00000001L
+-#define BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x00000002L
+-#define BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x00010000L
+-#define BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000L
+-#define BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK 0x20000000L
+-#define BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK 0x80000000L
+-//BLNDV0_BLNDV_REG_UPDATE_STATUS
+-#define BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT 0x0
+-#define BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT 0x1
+-#define BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2
+-#define BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3
+-#define BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT 0x6
+-#define BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT 0x7
+-#define BLNDV0_BLNDV_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT 0x8
+-#define BLNDV0_BLNDV_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT 0x9
+-#define BLNDV0_BLNDV_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT 0xa
+-#define BLNDV0_BLNDV_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT 0xb
+-#define BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK 0x00000001L
+-#define BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK 0x00000002L
+-#define BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK 0x00000004L
+-#define BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK 0x00000008L
+-#define BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK 0x00000040L
+-#define BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK 0x00000080L
+-#define BLNDV0_BLNDV_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK 0x00000100L
+-#define BLNDV0_BLNDV_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK 0x00000200L
+-#define BLNDV0_BLNDV_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK 0x00000400L
+-#define BLNDV0_BLNDV_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK 0x00000800L
+-
+-
+-// addressBlock: dce_dc_crtcv0_dispdec
+-//CRTCV0_CRTCV_H_BLANK_EARLY_NUM
+-#define CRTCV0_CRTCV_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0
+-#define CRTCV0_CRTCV_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10
+-#define CRTCV0_CRTCV_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x000003FFL
+-#define CRTCV0_CRTCV_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x00010000L
+-//CRTCV0_CRTCV_H_TOTAL
+-#define CRTCV0_CRTCV_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0
+-#define CRTCV0_CRTCV_H_TOTAL__CRTC_H_TOTAL_MASK 0x00003FFFL
+-//CRTCV0_CRTCV_H_BLANK_START_END
+-#define CRTCV0_CRTCV_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0
+-#define CRTCV0_CRTCV_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10
+-#define CRTCV0_CRTCV_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x00003FFFL
+-#define CRTCV0_CRTCV_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3FFF0000L
+-//CRTCV0_CRTCV_H_SYNC_A
+-#define CRTCV0_CRTCV_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0
+-#define CRTCV0_CRTCV_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10
+-#define CRTCV0_CRTCV_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x00003FFFL
+-#define CRTCV0_CRTCV_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3FFF0000L
+-//CRTCV0_CRTCV_H_SYNC_A_CNTL
+-#define CRTCV0_CRTCV_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0
+-#define CRTCV0_CRTCV_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10
+-#define CRTCV0_CRTCV_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11
+-#define CRTCV0_CRTCV_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x00000001L
+-#define CRTCV0_CRTCV_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x00010000L
+-#define CRTCV0_CRTCV_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x00020000L
+-//CRTCV0_CRTCV_H_SYNC_B
+-#define CRTCV0_CRTCV_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0
+-#define CRTCV0_CRTCV_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10
+-#define CRTCV0_CRTCV_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x00003FFFL
+-#define CRTCV0_CRTCV_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x3FFF0000L
+-//CRTCV0_CRTCV_H_SYNC_B_CNTL
+-#define CRTCV0_CRTCV_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0
+-#define CRTCV0_CRTCV_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10
+-#define CRTCV0_CRTCV_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11
+-#define CRTCV0_CRTCV_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x00000001L
+-#define CRTCV0_CRTCV_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x00010000L
+-#define CRTCV0_CRTCV_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x00020000L
+-//CRTCV0_CRTCV_VBI_END
+-#define CRTCV0_CRTCV_VBI_END__CRTC_VBI_V_END__SHIFT 0x0
+-#define CRTCV0_CRTCV_VBI_END__CRTC_VBI_H_END__SHIFT 0x10
+-#define CRTCV0_CRTCV_VBI_END__CRTC_VBI_V_END_MASK 0x00003FFFL
+-#define CRTCV0_CRTCV_VBI_END__CRTC_VBI_H_END_MASK 0x3FFF0000L
+-//CRTCV0_CRTCV_V_TOTAL
+-#define CRTCV0_CRTCV_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0
+-#define CRTCV0_CRTCV_V_TOTAL__CRTC_V_TOTAL_MASK 0x00003FFFL
+-//CRTCV0_CRTCV_V_TOTAL_MIN
+-#define CRTCV0_CRTCV_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0
+-#define CRTCV0_CRTCV_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x00003FFFL
+-//CRTCV0_CRTCV_V_TOTAL_MAX
+-#define CRTCV0_CRTCV_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0
+-#define CRTCV0_CRTCV_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10
+-#define CRTCV0_CRTCV_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x00003FFFL
+-#define CRTCV0_CRTCV_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x00010000L
+-//CRTCV0_CRTCV_V_TOTAL_CONTROL
+-#define CRTCV0_CRTCV_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0
+-#define CRTCV0_CRTCV_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4
+-#define CRTCV0_CRTCV_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8
+-#define CRTCV0_CRTCV_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc
+-#define CRTCV0_CRTCV_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf
+-#define CRTCV0_CRTCV_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10
+-#define CRTCV0_CRTCV_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x00000001L
+-#define CRTCV0_CRTCV_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x00000010L
+-#define CRTCV0_CRTCV_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x00000100L
+-#define CRTCV0_CRTCV_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x00001000L
+-#define CRTCV0_CRTCV_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00008000L
+-#define CRTCV0_CRTCV_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L
+-//CRTCV0_CRTCV_V_TOTAL_INT_STATUS
+-#define CRTCV0_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0
+-#define CRTCV0_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4
+-#define CRTCV0_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8
+-#define CRTCV0_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc
+-#define CRTCV0_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L
+-#define CRTCV0_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L
+-#define CRTCV0_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L
+-#define CRTCV0_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L
+-//CRTCV0_CRTCV_VSYNC_NOM_INT_STATUS
+-#define CRTCV0_CRTCV_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0
+-#define CRTCV0_CRTCV_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4
+-#define CRTCV0_CRTCV_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x00000001L
+-#define CRTCV0_CRTCV_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L
+-//CRTCV0_CRTCV_V_BLANK_START_END
+-#define CRTCV0_CRTCV_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0
+-#define CRTCV0_CRTCV_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10
+-#define CRTCV0_CRTCV_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x00003FFFL
+-#define CRTCV0_CRTCV_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3FFF0000L
+-//CRTCV0_CRTCV_V_SYNC_A
+-#define CRTCV0_CRTCV_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0
+-#define CRTCV0_CRTCV_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10
+-#define CRTCV0_CRTCV_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x00003FFFL
+-#define CRTCV0_CRTCV_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3FFF0000L
+-//CRTCV0_CRTCV_V_SYNC_A_CNTL
+-#define CRTCV0_CRTCV_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0
+-#define CRTCV0_CRTCV_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x00000001L
+-//CRTCV0_CRTCV_V_SYNC_B
+-#define CRTCV0_CRTCV_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0
+-#define CRTCV0_CRTCV_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10
+-#define CRTCV0_CRTCV_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x00003FFFL
+-#define CRTCV0_CRTCV_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x3FFF0000L
+-//CRTCV0_CRTCV_V_SYNC_B_CNTL
+-#define CRTCV0_CRTCV_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0
+-#define CRTCV0_CRTCV_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x00000001L
+-//CRTCV0_CRTCV_DTMTEST_CNTL
+-#define CRTCV0_CRTCV_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0
+-#define CRTCV0_CRTCV_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1
+-#define CRTCV0_CRTCV_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x00000001L
+-#define CRTCV0_CRTCV_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x0000001EL
+-//CRTCV0_CRTCV_DTMTEST_STATUS_POSITION
+-#define CRTCV0_CRTCV_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0
+-#define CRTCV0_CRTCV_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10
+-#define CRTCV0_CRTCV_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x00003FFFL
+-#define CRTCV0_CRTCV_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x3FFF0000L
+-//CRTCV0_CRTCV_TRIGA_CNTL
+-#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0
+-#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5
+-#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8
+-#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9
+-#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa
+-#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb
+-#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
+-#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
+-#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14
+-#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18
+-#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f
+-#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x0000001FL
+-#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0x000000E0L
+-#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000100L
+-#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x00000200L
+-#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x00000400L
+-#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x00000800L
+-#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
+-#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
+-#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L
+-#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1F000000L
+-#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000L
+-//CRTCV0_CRTCV_TRIGA_MANUAL_TRIG
+-#define CRTCV0_CRTCV_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0
+-#define CRTCV0_CRTCV_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x00000001L
+-//CRTCV0_CRTCV_TRIGB_CNTL
+-#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0
+-#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5
+-#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8
+-#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9
+-#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa
+-#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb
+-#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
+-#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
+-#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14
+-#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18
+-#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f
+-#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x0000001FL
+-#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0x000000E0L
+-#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000100L
+-#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x00000200L
+-#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x00000400L
+-#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x00000800L
+-#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
+-#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
+-#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L
+-#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1F000000L
+-#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000L
+-//CRTCV0_CRTCV_TRIGB_MANUAL_TRIG
+-#define CRTCV0_CRTCV_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0
+-#define CRTCV0_CRTCV_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x00000001L
+-//CRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL
+-#define CRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0
+-#define CRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4
+-#define CRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8
+-#define CRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10
+-#define CRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18
+-#define CRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x00000003L
+-#define CRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L
+-#define CRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L
+-#define CRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L
+-#define CRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L
+-//CRTCV0_CRTCV_FLOW_CONTROL
+-#define CRTCV0_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0
+-#define CRTCV0_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8
+-#define CRTCV0_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10
+-#define CRTCV0_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18
+-#define CRTCV0_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL
+-#define CRTCV0_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x00000100L
+-#define CRTCV0_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L
+-#define CRTCV0_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L
+-//CRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE
+-#define CRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0
+-#define CRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER__SHIFT 0x8
+-#define CRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER__SHIFT 0x10
+-#define CRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L
+-#define CRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L
+-#define CRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L
+-//CRTCV0_CRTCV_AVSYNC_COUNTER
+-#define CRTCV0_CRTCV_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER__SHIFT 0x0
+-#define CRTCV0_CRTCV_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER_MASK 0xFFFFFFFFL
+-//CRTCV0_CRTCV_CONTROL
+-#define CRTCV0_CRTCV_CONTROL__CRTC_MASTER_EN__SHIFT 0x0
+-#define CRTCV0_CRTCV_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4
+-#define CRTCV0_CRTCV_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8
+-#define CRTCV0_CRTCV_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc
+-#define CRTCV0_CRTCV_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd
+-#define CRTCV0_CRTCV_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe
+-#define CRTCV0_CRTCV_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10
+-#define CRTCV0_CRTCV_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14
+-#define CRTCV0_CRTCV_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d
+-#define CRTCV0_CRTCV_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e
+-#define CRTCV0_CRTCV_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f
+-#define CRTCV0_CRTCV_CONTROL__CRTC_MASTER_EN_MASK 0x00000001L
+-#define CRTCV0_CRTCV_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x00000010L
+-#define CRTCV0_CRTCV_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x00000300L
+-#define CRTCV0_CRTCV_CONTROL__CRTC_START_POINT_CNTL_MASK 0x00001000L
+-#define CRTCV0_CRTCV_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x00002000L
+-#define CRTCV0_CRTCV_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x00004000L
+-#define CRTCV0_CRTCV_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x00010000L
+-#define CRTCV0_CRTCV_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x00700000L
+-#define CRTCV0_CRTCV_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000L
+-#define CRTCV0_CRTCV_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L
+-#define CRTCV0_CRTCV_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L
+-//CRTCV0_CRTCV_BLANK_CONTROL
+-#define CRTCV0_CRTCV_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0
+-#define CRTCV0_CRTCV_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8
+-#define CRTCV0_CRTCV_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10
+-#define CRTCV0_CRTCV_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x00000001L
+-#define CRTCV0_CRTCV_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x00000100L
+-#define CRTCV0_CRTCV_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x00010000L
+-//CRTCV0_CRTCV_INTERLACE_CONTROL
+-#define CRTCV0_CRTCV_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0
+-#define CRTCV0_CRTCV_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10
+-#define CRTCV0_CRTCV_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x00000001L
+-#define CRTCV0_CRTCV_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L
+-//CRTCV0_CRTCV_INTERLACE_STATUS
+-#define CRTCV0_CRTCV_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0
+-#define CRTCV0_CRTCV_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1
+-#define CRTCV0_CRTCV_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x00000001L
+-#define CRTCV0_CRTCV_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x00000002L
+-//CRTCV0_CRTCV_FIELD_INDICATION_CONTROL
+-#define CRTCV0_CRTCV_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0
+-#define CRTCV0_CRTCV_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1
+-#define CRTCV0_CRTCV_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x00000001L
+-#define CRTCV0_CRTCV_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x00000002L
+-//CRTCV0_CRTCV_PIXEL_DATA_READBACK0
+-#define CRTCV0_CRTCV_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0
+-#define CRTCV0_CRTCV_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10
+-#define CRTCV0_CRTCV_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0x00000FFFL
+-#define CRTCV0_CRTCV_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0x0FFF0000L
+-//CRTCV0_CRTCV_PIXEL_DATA_READBACK1
+-#define CRTCV0_CRTCV_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0
+-#define CRTCV0_CRTCV_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0x00000FFFL
+-//CRTCV0_CRTCV_STATUS
+-#define CRTCV0_CRTCV_STATUS__CRTC_V_BLANK__SHIFT 0x0
+-#define CRTCV0_CRTCV_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1
+-#define CRTCV0_CRTCV_STATUS__CRTC_V_SYNC_A__SHIFT 0x2
+-#define CRTCV0_CRTCV_STATUS__CRTC_V_UPDATE__SHIFT 0x3
+-#define CRTCV0_CRTCV_STATUS__CRTC_V_START_LINE__SHIFT 0x4
+-#define CRTCV0_CRTCV_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5
+-#define CRTCV0_CRTCV_STATUS__CRTC_H_BLANK__SHIFT 0x10
+-#define CRTCV0_CRTCV_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11
+-#define CRTCV0_CRTCV_STATUS__CRTC_H_SYNC_A__SHIFT 0x12
+-#define CRTCV0_CRTCV_STATUS__CRTC_V_BLANK_MASK 0x00000001L
+-#define CRTCV0_CRTCV_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x00000002L
+-#define CRTCV0_CRTCV_STATUS__CRTC_V_SYNC_A_MASK 0x00000004L
+-#define CRTCV0_CRTCV_STATUS__CRTC_V_UPDATE_MASK 0x00000008L
+-#define CRTCV0_CRTCV_STATUS__CRTC_V_START_LINE_MASK 0x00000010L
+-#define CRTCV0_CRTCV_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x00000020L
+-#define CRTCV0_CRTCV_STATUS__CRTC_H_BLANK_MASK 0x00010000L
+-#define CRTCV0_CRTCV_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x00020000L
+-#define CRTCV0_CRTCV_STATUS__CRTC_H_SYNC_A_MASK 0x00040000L
+-//CRTCV0_CRTCV_STATUS_POSITION
+-#define CRTCV0_CRTCV_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0
+-#define CRTCV0_CRTCV_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10
+-#define CRTCV0_CRTCV_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x00003FFFL
+-#define CRTCV0_CRTCV_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x3FFF0000L
+-//CRTCV0_CRTCV_NOM_VERT_POSITION
+-#define CRTCV0_CRTCV_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0
+-#define CRTCV0_CRTCV_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x00003FFFL
+-//CRTCV0_CRTCV_STATUS_FRAME_COUNT
+-#define CRTCV0_CRTCV_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0
+-#define CRTCV0_CRTCV_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0x00FFFFFFL
+-//CRTCV0_CRTCV_STATUS_VF_COUNT
+-#define CRTCV0_CRTCV_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0
+-#define CRTCV0_CRTCV_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x3FFFFFFFL
+-//CRTCV0_CRTCV_STATUS_HV_COUNT
+-#define CRTCV0_CRTCV_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0
+-#define CRTCV0_CRTCV_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x3FFFFFFFL
+-//CRTCV0_CRTCV_COUNT_CONTROL
+-#define CRTCV0_CRTCV_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0
+-#define CRTCV0_CRTCV_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1
+-#define CRTCV0_CRTCV_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x00000001L
+-#define CRTCV0_CRTCV_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x0000001EL
+-//CRTCV0_CRTCV_COUNT_RESET
+-#define CRTCV0_CRTCV_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0
+-#define CRTCV0_CRTCV_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x00000001L
+-//CRTCV0_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE
+-#define CRTCV0_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0
+-#define CRTCV0_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L
+-//CRTCV0_CRTCV_VERT_SYNC_CONTROL
+-#define CRTCV0_CRTCV_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0
+-#define CRTCV0_CRTCV_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8
+-#define CRTCV0_CRTCV_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10
+-#define CRTCV0_CRTCV_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L
+-#define CRTCV0_CRTCV_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L
+-#define CRTCV0_CRTCV_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L
+-//CRTCV0_CRTCV_STEREO_STATUS
+-#define CRTCV0_CRTCV_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0
+-#define CRTCV0_CRTCV_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8
+-#define CRTCV0_CRTCV_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10
+-#define CRTCV0_CRTCV_STEREO_STATUS__CRTC_STEREO_EYE_FLAG__SHIFT 0x14
+-#define CRTCV0_CRTCV_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18
+-#define CRTCV0_CRTCV_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x00000001L
+-#define CRTCV0_CRTCV_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x00000100L
+-#define CRTCV0_CRTCV_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x00010000L
+-#define CRTCV0_CRTCV_STEREO_STATUS__CRTC_STEREO_EYE_FLAG_MASK 0x00100000L
+-#define CRTCV0_CRTCV_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L
+-//CRTCV0_CRTCV_STEREO_CONTROL
+-#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0
+-#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf
+-#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10
+-#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11
+-#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12
+-#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM__SHIFT 0x13
+-#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14
+-#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18
+-#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00003FFFL
+-#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L
+-#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x00010000L
+-#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L
+-#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L
+-#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM_MASK 0x00080000L
+-#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L
+-#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x01000000L
+-//CRTCV0_CRTCV_SNAPSHOT_STATUS
+-#define CRTCV0_CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0
+-#define CRTCV0_CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1
+-#define CRTCV0_CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2
+-#define CRTCV0_CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x00000001L
+-#define CRTCV0_CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x00000002L
+-#define CRTCV0_CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L
+-//CRTCV0_CRTCV_SNAPSHOT_CONTROL
+-#define CRTCV0_CRTCV_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0
+-#define CRTCV0_CRTCV_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L
+-//CRTCV0_CRTCV_SNAPSHOT_POSITION
+-#define CRTCV0_CRTCV_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0
+-#define CRTCV0_CRTCV_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10
+-#define CRTCV0_CRTCV_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x00003FFFL
+-#define CRTCV0_CRTCV_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x3FFF0000L
+-//CRTCV0_CRTCV_SNAPSHOT_FRAME
+-#define CRTCV0_CRTCV_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0
+-#define CRTCV0_CRTCV_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL
+-//CRTCV0_CRTCV_START_LINE_CONTROL
+-#define CRTCV0_CRTCV_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0
+-#define CRTCV0_CRTCV_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x1
+-#define CRTCV0_CRTCV_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x2
+-#define CRTCV0_CRTCV_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x8
+-#define CRTCV0_CRTCV_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc
+-#define CRTCV0_CRTCV_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x00000001L
+-#define CRTCV0_CRTCV_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x00000002L
+-#define CRTCV0_CRTCV_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x00000004L
+-#define CRTCV0_CRTCV_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x00000100L
+-#define CRTCV0_CRTCV_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0x000FF000L
+-//CRTCV0_CRTCV_INTERRUPT_CONTROL
+-#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0
+-#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1
+-#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4
+-#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5
+-#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8
+-#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9
+-#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10
+-#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11
+-#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18
+-#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19
+-#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a
+-#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b
+-#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c
+-#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d
+-#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e
+-#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f
+-#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x00000001L
+-#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x00000002L
+-#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x00000010L
+-#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x00000020L
+-#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L
+-#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L
+-#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L
+-#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L
+-#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x01000000L
+-#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x02000000L
+-#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x04000000L
+-#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x08000000L
+-#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000L
+-#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000L
+-#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L
+-#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L
+-//CRTCV0_CRTCV_UPDATE_LOCK
+-#define CRTCV0_CRTCV_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0
+-#define CRTCV0_CRTCV_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x00000001L
+-//CRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL
+-#define CRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0
+-#define CRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8
+-#define CRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10
+-#define CRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18
+-#define CRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x19
+-#define CRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x00000001L
+-#define CRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x00000100L
+-#define CRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L
+-#define CRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x01000000L
+-#define CRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x02000000L
+-//CRTCV0_CRTCV_VGA_PARAMETER_CAPTURE_MODE
+-#define CRTCV0_CRTCV_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0
+-#define CRTCV0_CRTCV_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x00000001L
+-//CRTCV0_CRTCV_TEST_PATTERN_CONTROL
+-#define CRTCV0_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0
+-#define CRTCV0_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8
+-#define CRTCV0_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10
+-#define CRTCV0_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18
+-#define CRTCV0_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x00000001L
+-#define CRTCV0_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x00000700L
+-#define CRTCV0_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L
+-#define CRTCV0_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xFF000000L
+-//CRTCV0_CRTCV_TEST_PATTERN_PARAMETERS
+-#define CRTCV0_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0
+-#define CRTCV0_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4
+-#define CRTCV0_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8
+-#define CRTCV0_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc
+-#define CRTCV0_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10
+-#define CRTCV0_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0x0000000FL
+-#define CRTCV0_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0x000000F0L
+-#define CRTCV0_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0x00000F00L
+-#define CRTCV0_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0x0000F000L
+-#define CRTCV0_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xFFFF0000L
+-//CRTCV0_CRTCV_TEST_PATTERN_COLOR
+-#define CRTCV0_CRTCV_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0
+-#define CRTCV0_CRTCV_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10
+-#define CRTCV0_CRTCV_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0x0000FFFFL
+-#define CRTCV0_CRTCV_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x003F0000L
+-//CRTCV0_CRTCV_MASTER_UPDATE_LOCK
+-#define CRTCV0_CRTCV_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0
+-#define CRTCV0_CRTCV_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8
+-#define CRTCV0_CRTCV_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK__SHIFT 0x10
+-#define CRTCV0_CRTCV_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x00000001L
+-#define CRTCV0_CRTCV_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x00000100L
+-#define CRTCV0_CRTCV_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK_MASK 0x00010000L
+-//CRTCV0_CRTCV_MASTER_UPDATE_MODE
+-#define CRTCV0_CRTCV_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0
+-#define CRTCV0_CRTCV_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10
+-#define CRTCV0_CRTCV_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x00000007L
+-#define CRTCV0_CRTCV_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00030000L
+-//CRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT
+-#define CRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0
+-#define CRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8
+-#define CRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x00000003L
+-#define CRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xFFFFFF00L
+-//CRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER
+-#define CRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0
+-#define CRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0x000000FFL
+-//CRTCV0_CRTCV_MVP_STATUS
+-#define CRTCV0_CRTCV_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0
+-#define CRTCV0_CRTCV_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4
+-#define CRTCV0_CRTCV_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10
+-#define CRTCV0_CRTCV_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14
+-#define CRTCV0_CRTCV_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x00000001L
+-#define CRTCV0_CRTCV_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x00000010L
+-#define CRTCV0_CRTCV_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x00010000L
+-#define CRTCV0_CRTCV_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x00100000L
+-//CRTCV0_CRTCV_MASTER_EN
+-#define CRTCV0_CRTCV_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0
+-#define CRTCV0_CRTCV_MASTER_EN__CRTC_MASTER_EN_MASK 0x00000001L
+-//CRTCV0_CRTCV_ALLOW_STOP_OFF_V_CNT
+-#define CRTCV0_CRTCV_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0
+-#define CRTCV0_CRTCV_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10
+-#define CRTCV0_CRTCV_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0x000000FFL
+-#define CRTCV0_CRTCV_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x00010000L
+-//CRTCV0_CRTCV_V_UPDATE_INT_STATUS
+-#define CRTCV0_CRTCV_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0
+-#define CRTCV0_CRTCV_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8
+-#define CRTCV0_CRTCV_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x00000001L
+-#define CRTCV0_CRTCV_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x00000100L
+-//CRTCV0_CRTCV_OVERSCAN_COLOR
+-#define CRTCV0_CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0
+-#define CRTCV0_CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa
+-#define CRTCV0_CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14
+-#define CRTCV0_CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x000003FFL
+-#define CRTCV0_CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0x000FFC00L
+-#define CRTCV0_CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3FF00000L
+-//CRTCV0_CRTCV_OVERSCAN_COLOR_EXT
+-#define CRTCV0_CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0
+-#define CRTCV0_CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8
+-#define CRTCV0_CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10
+-#define CRTCV0_CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x00000003L
+-#define CRTCV0_CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x00000300L
+-#define CRTCV0_CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x00030000L
+-//CRTCV0_CRTCV_BLANK_DATA_COLOR
+-#define CRTCV0_CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0
+-#define CRTCV0_CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa
+-#define CRTCV0_CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14
+-#define CRTCV0_CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL
+-#define CRTCV0_CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L
+-#define CRTCV0_CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L
+-//CRTCV0_CRTCV_BLANK_DATA_COLOR_EXT
+-#define CRTCV0_CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0
+-#define CRTCV0_CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8
+-#define CRTCV0_CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10
+-#define CRTCV0_CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x00000003L
+-#define CRTCV0_CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00000300L
+-#define CRTCV0_CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x00030000L
+-//CRTCV0_CRTCV_BLACK_COLOR
+-#define CRTCV0_CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0
+-#define CRTCV0_CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa
+-#define CRTCV0_CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14
+-#define CRTCV0_CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x000003FFL
+-#define CRTCV0_CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0x000FFC00L
+-#define CRTCV0_CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3FF00000L
+-//CRTCV0_CRTCV_BLACK_COLOR_EXT
+-#define CRTCV0_CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0
+-#define CRTCV0_CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8
+-#define CRTCV0_CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10
+-#define CRTCV0_CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x00000003L
+-#define CRTCV0_CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x00000300L
+-#define CRTCV0_CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x00030000L
+-//CRTCV0_CRTCV_VERTICAL_INTERRUPT0_POSITION
+-#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0
+-#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10
+-#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00003FFFL
+-#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x3FFF0000L
+-//CRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL
+-#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4
+-#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8
+-#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc
+-#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10
+-#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14
+-#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18
+-#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L
+-#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L
+-#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L
+-#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L
+-#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L
+-#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L
+-//CRTCV0_CRTCV_VERTICAL_INTERRUPT1_POSITION
+-#define CRTCV0_CRTCV_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0
+-#define CRTCV0_CRTCV_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00003FFFL
+-//CRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL
+-#define CRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8
+-#define CRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc
+-#define CRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10
+-#define CRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14
+-#define CRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18
+-#define CRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L
+-#define CRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L
+-#define CRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L
+-#define CRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L
+-#define CRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L
+-//CRTCV0_CRTCV_VERTICAL_INTERRUPT2_POSITION
+-#define CRTCV0_CRTCV_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0
+-#define CRTCV0_CRTCV_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00003FFFL
+-//CRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL
+-#define CRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8
+-#define CRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc
+-#define CRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10
+-#define CRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14
+-#define CRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18
+-#define CRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L
+-#define CRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L
+-#define CRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L
+-#define CRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L
+-#define CRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L
+-//CRTCV0_CRTCV_CRC_CNTL
+-#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0
+-#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4
+-#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8
+-#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc
+-#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
+-#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14
+-#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18
+-#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC_EN_MASK 0x00000001L
+-#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x00000010L
+-#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x00000300L
+-#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x00003000L
+-#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
+-#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x00700000L
+-#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x07000000L
+-//CRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL
+-#define CRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0
+-#define CRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10
+-#define CRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x00003FFFL
+-#define CRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3FFF0000L
+-//CRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL
+-#define CRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0
+-#define CRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10
+-#define CRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x00003FFFL
+-#define CRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3FFF0000L
+-//CRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL
+-#define CRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0
+-#define CRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10
+-#define CRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x00003FFFL
+-#define CRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3FFF0000L
+-//CRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL
+-#define CRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0
+-#define CRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10
+-#define CRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x00003FFFL
+-#define CRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3FFF0000L
+-//CRTCV0_CRTCV_CRC0_DATA_RG
+-#define CRTCV0_CRTCV_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0
+-#define CRTCV0_CRTCV_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10
+-#define CRTCV0_CRTCV_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL
+-#define CRTCV0_CRTCV_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L
+-//CRTCV0_CRTCV_CRC0_DATA_B
+-#define CRTCV0_CRTCV_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0
+-#define CRTCV0_CRTCV_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL
+-//CRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL
+-#define CRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0
+-#define CRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10
+-#define CRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x00003FFFL
+-#define CRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3FFF0000L
+-//CRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL
+-#define CRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0
+-#define CRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10
+-#define CRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x00003FFFL
+-#define CRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3FFF0000L
+-//CRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL
+-#define CRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0
+-#define CRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10
+-#define CRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x00003FFFL
+-#define CRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3FFF0000L
+-//CRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL
+-#define CRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0
+-#define CRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10
+-#define CRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x00003FFFL
+-#define CRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3FFF0000L
+-//CRTCV0_CRTCV_CRC1_DATA_RG
+-#define CRTCV0_CRTCV_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0
+-#define CRTCV0_CRTCV_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10
+-#define CRTCV0_CRTCV_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL
+-#define CRTCV0_CRTCV_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L
+-//CRTCV0_CRTCV_CRC1_DATA_B
+-#define CRTCV0_CRTCV_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0
+-#define CRTCV0_CRTCV_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL
+-//CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE__SHIFT 0x0
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__SHIFT 0x3
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__SHIFT 0x4
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__SHIFT 0x5
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__SHIFT 0x8
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__SHIFT 0x9
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__SHIFT 0xc
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__SHIFT 0xd
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__SHIFT 0xe
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE__SHIFT 0x18
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE__SHIFT 0x1c
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE_MASK 0x00000003L
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_MASK 0x00000008L
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_MASK 0x00000010L
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_MASK 0x00000060L
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_MASK 0x00000100L
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_MASK 0x00000200L
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_MASK 0x00001000L
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_MASK 0x00002000L
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_MASK 0x00004000L
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE_MASK 0x07000000L
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE_MASK 0x70000000L
+-//CRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_START
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X__SHIFT 0x0
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y__SHIFT 0x10
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X_MASK 0x00003FFFL
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y_MASK 0x3FFF0000L
+-//CRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_END
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X__SHIFT 0x0
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y__SHIFT 0x10
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X_MASK 0x00003FFFL
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y_MASK 0x3FFF0000L
+-//CRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__SHIFT 0x0
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS__SHIFT 0x4
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS__SHIFT 0x8
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__SHIFT 0x10
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__SHIFT 0x14
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__SHIFT 0x1d
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_MASK 0x00000001L
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS_MASK 0x00000010L
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS_MASK 0x00000100L
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_MASK 0x00010000L
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_MASK 0x00100000L
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_MASK 0xE0000000L
+-//CRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE__SHIFT 0x0
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS__SHIFT 0x4
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS__SHIFT 0x8
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR__SHIFT 0x10
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE__SHIFT 0x14
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE_MASK 0x00000001L
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS_MASK 0x00000010L
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS_MASK 0x00000100L
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR_MASK 0x00010000L
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE_MASK 0x00100000L
+-//CRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__SHIFT 0x0
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS__SHIFT 0x4
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS__SHIFT 0x8
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__SHIFT 0x10
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__SHIFT 0x14
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_MASK 0x00000001L
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS_MASK 0x00000010L
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS_MASK 0x00000100L
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_MASK 0x00010000L
+-#define CRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_MASK 0x00100000L
+-//CRTCV0_CRTCV_STATIC_SCREEN_CONTROL
+-#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0
+-#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10
+-#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18
+-#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19
+-#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a
+-#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b
+-#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c
+-#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL
+-#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L
+-#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x01000000L
+-#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x02000000L
+-#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x04000000L
+-#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x08000000L
+-#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000L
+-//CRTCV0_CRTCV_3D_STRUCTURE_CONTROL
+-#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0
+-#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4
+-#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8
+-#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc
+-#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10
+-#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11
+-#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12
+-#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x00000001L
+-#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x00000010L
+-#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L
+-#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L
+-#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L
+-#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L
+-#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L
+-//CRTCV0_CRTCV_GSL_VSYNC_GAP
+-#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0
+-#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8
+-#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10
+-#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11
+-#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13
+-#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14
+-#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17
+-#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18
+-#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL
+-#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L
+-#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L
+-#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x00060000L
+-#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L
+-#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L
+-#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L
+-#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xFF000000L
+-//CRTCV0_CRTCV_GSL_WINDOW
+-#define CRTCV0_CRTCV_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0
+-#define CRTCV0_CRTCV_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10
+-#define CRTCV0_CRTCV_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x00003FFFL
+-#define CRTCV0_CRTCV_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x3FFF0000L
+-//CRTCV0_CRTCV_GSL_CONTROL
+-#define CRTCV0_CRTCV_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0
+-#define CRTCV0_CRTCV_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10
+-#define CRTCV0_CRTCV_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c
+-#define CRTCV0_CRTCV_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x00003FFFL
+-#define CRTCV0_CRTCV_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x001F0000L
+-#define CRTCV0_CRTCV_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L
+-
+-
+-// addressBlock: dce_dc_unp1_dispdec
+-//UNP1_UNP_GRPH_ENABLE
+-#define UNP1_UNP_GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0
+-#define UNP1_UNP_GRPH_ENABLE__GRPH_ENABLE_MASK 0x00000001L
+-//UNP1_UNP_GRPH_CONTROL
+-#define UNP1_UNP_GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0
+-#define UNP1_UNP_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x2
+-#define UNP1_UNP_GRPH_CONTROL__GRPH_Z__SHIFT 0x4
+-#define UNP1_UNP_GRPH_CONTROL__GRPH_BANK_WIDTH_L__SHIFT 0x6
+-#define UNP1_UNP_GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8
+-#define UNP1_UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT_L__SHIFT 0xb
+-#define UNP1_UNP_GRPH_CONTROL__GRPH_TILE_SPLIT_L__SHIFT 0xd
+-#define UNP1_UNP_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10
+-#define UNP1_UNP_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11
+-#define UNP1_UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_L__SHIFT 0x12
+-#define UNP1_UNP_GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x14
+-#define UNP1_UNP_GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT 0x18
+-#define UNP1_UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE_L__SHIFT 0x1d
+-#define UNP1_UNP_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f
+-#define UNP1_UNP_GRPH_CONTROL__GRPH_DEPTH_MASK 0x00000003L
+-#define UNP1_UNP_GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0x0000000CL
+-#define UNP1_UNP_GRPH_CONTROL__GRPH_Z_MASK 0x00000030L
+-#define UNP1_UNP_GRPH_CONTROL__GRPH_BANK_WIDTH_L_MASK 0x000000C0L
+-#define UNP1_UNP_GRPH_CONTROL__GRPH_FORMAT_MASK 0x00000700L
+-#define UNP1_UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT_L_MASK 0x00001800L
+-#define UNP1_UNP_GRPH_CONTROL__GRPH_TILE_SPLIT_L_MASK 0x0000E000L
+-#define UNP1_UNP_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x00010000L
+-#define UNP1_UNP_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x00020000L
+-#define UNP1_UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_L_MASK 0x000C0000L
+-#define UNP1_UNP_GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0x00F00000L
+-#define UNP1_UNP_GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1F000000L
+-#define UNP1_UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE_L_MASK 0x60000000L
+-#define UNP1_UNP_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000L
+-//UNP1_UNP_GRPH_CONTROL_C
+-#define UNP1_UNP_GRPH_CONTROL_C__GRPH_BANK_WIDTH_C__SHIFT 0x6
+-#define UNP1_UNP_GRPH_CONTROL_C__GRPH_BANK_HEIGHT_C__SHIFT 0xb
+-#define UNP1_UNP_GRPH_CONTROL_C__GRPH_TILE_SPLIT_C__SHIFT 0xd
+-#define UNP1_UNP_GRPH_CONTROL_C__GRPH_MACRO_TILE_ASPECT_C__SHIFT 0x12
+-#define UNP1_UNP_GRPH_CONTROL_C__GRPH_MICRO_TILE_MODE_C__SHIFT 0x1d
+-#define UNP1_UNP_GRPH_CONTROL_C__GRPH_BANK_WIDTH_C_MASK 0x000000C0L
+-#define UNP1_UNP_GRPH_CONTROL_C__GRPH_BANK_HEIGHT_C_MASK 0x00001800L
+-#define UNP1_UNP_GRPH_CONTROL_C__GRPH_TILE_SPLIT_C_MASK 0x0000E000L
+-#define UNP1_UNP_GRPH_CONTROL_C__GRPH_MACRO_TILE_ASPECT_C_MASK 0x000C0000L
+-#define UNP1_UNP_GRPH_CONTROL_C__GRPH_MICRO_TILE_MODE_C_MASK 0x60000000L
+-//UNP1_UNP_GRPH_CONTROL_EXP
+-#define UNP1_UNP_GRPH_CONTROL_EXP__VIDEO_FORMAT__SHIFT 0x0
+-#define UNP1_UNP_GRPH_CONTROL_EXP__VIDEO_FORMAT_MASK 0x00000007L
+-//UNP1_UNP_GRPH_SWAP_CNTL
+-#define UNP1_UNP_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0
+-#define UNP1_UNP_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4
+-#define UNP1_UNP_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6
+-#define UNP1_UNP_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8
+-#define UNP1_UNP_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x00000003L
+-#define UNP1_UNP_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x00000030L
+-#define UNP1_UNP_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0x000000C0L
+-#define UNP1_UNP_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x00000300L
+-//UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L
+-#define UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L__SHIFT 0x8
+-#define UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L_MASK 0xFFFFFF00L
+-//UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C
+-#define UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x8
+-#define UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFF00L
+-//UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L
+-#define UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
+-#define UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_MASK 0x000000FFL
+-//UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C
+-#define UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+-#define UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x000000FFL
+-//UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L
+-#define UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__SHIFT 0x8
+-#define UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_MASK 0xFFFFFF00L
+-//UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C
+-#define UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__SHIFT 0x8
+-#define UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_MASK 0xFFFFFF00L
+-//UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L
+-#define UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
+-#define UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_MASK 0x000000FFL
+-//UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C
+-#define UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+-#define UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_MASK 0x000000FFL
+-//UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L
+-#define UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_SURFACE_ADDRESS_L__SHIFT 0x8
+-#define UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_SURFACE_ADDRESS_L_MASK 0xFFFFFF00L
+-//UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C
+-#define UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x8
+-#define UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFF00L
+-//UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L
+-#define UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
+-#define UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_MASK 0x000000FFL
+-//UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C
+-#define UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+-#define UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x000000FFL
+-//UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L
+-#define UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__SHIFT 0x8
+-#define UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_MASK 0xFFFFFF00L
+-//UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C
+-#define UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__SHIFT 0x8
+-#define UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_MASK 0xFFFFFF00L
+-//UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L
+-#define UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
+-#define UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_MASK 0x000000FFL
+-//UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C
+-#define UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+-#define UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_MASK 0x000000FFL
+-//UNP1_UNP_GRPH_PITCH_L
+-#define UNP1_UNP_GRPH_PITCH_L__GRPH_PITCH_L__SHIFT 0x0
+-#define UNP1_UNP_GRPH_PITCH_L__GRPH_PITCH_L_MASK 0x00007FFFL
+-//UNP1_UNP_GRPH_PITCH_C
+-#define UNP1_UNP_GRPH_PITCH_C__GRPH_PITCH_C__SHIFT 0x0
+-#define UNP1_UNP_GRPH_PITCH_C__GRPH_PITCH_C_MASK 0x00007FFFL
+-//UNP1_UNP_GRPH_SURFACE_OFFSET_X_L
+-#define UNP1_UNP_GRPH_SURFACE_OFFSET_X_L__GRPH_SURFACE_OFFSET_X_L__SHIFT 0x0
+-#define UNP1_UNP_GRPH_SURFACE_OFFSET_X_L__GRPH_SURFACE_OFFSET_X_L_MASK 0x00003FFFL
+-//UNP1_UNP_GRPH_SURFACE_OFFSET_X_C
+-#define UNP1_UNP_GRPH_SURFACE_OFFSET_X_C__GRPH_SURFACE_OFFSET_X_C__SHIFT 0x0
+-#define UNP1_UNP_GRPH_SURFACE_OFFSET_X_C__GRPH_SURFACE_OFFSET_X_C_MASK 0x00003FFFL
+-//UNP1_UNP_GRPH_SURFACE_OFFSET_Y_L
+-#define UNP1_UNP_GRPH_SURFACE_OFFSET_Y_L__GRPH_SURFACE_OFFSET_Y_L__SHIFT 0x0
+-#define UNP1_UNP_GRPH_SURFACE_OFFSET_Y_L__GRPH_SURFACE_OFFSET_Y_L_MASK 0x00003FFFL
+-//UNP1_UNP_GRPH_SURFACE_OFFSET_Y_C
+-#define UNP1_UNP_GRPH_SURFACE_OFFSET_Y_C__GRPH_SURFACE_OFFSET_Y_C__SHIFT 0x0
+-#define UNP1_UNP_GRPH_SURFACE_OFFSET_Y_C__GRPH_SURFACE_OFFSET_Y_C_MASK 0x00003FFFL
+-//UNP1_UNP_GRPH_X_START_L
+-#define UNP1_UNP_GRPH_X_START_L__GRPH_X_START_L__SHIFT 0x0
+-#define UNP1_UNP_GRPH_X_START_L__GRPH_X_START_L_MASK 0x00003FFFL
+-//UNP1_UNP_GRPH_X_START_C
+-#define UNP1_UNP_GRPH_X_START_C__GRPH_X_START_C__SHIFT 0x0
+-#define UNP1_UNP_GRPH_X_START_C__GRPH_X_START_C_MASK 0x00003FFFL
+-//UNP1_UNP_GRPH_Y_START_L
+-#define UNP1_UNP_GRPH_Y_START_L__GRPH_Y_START_L__SHIFT 0x0
+-#define UNP1_UNP_GRPH_Y_START_L__GRPH_Y_START_L_MASK 0x00003FFFL
+-//UNP1_UNP_GRPH_Y_START_C
+-#define UNP1_UNP_GRPH_Y_START_C__GRPH_Y_START_C__SHIFT 0x0
+-#define UNP1_UNP_GRPH_Y_START_C__GRPH_Y_START_C_MASK 0x00003FFFL
+-//UNP1_UNP_GRPH_X_END_L
+-#define UNP1_UNP_GRPH_X_END_L__GRPH_X_END_L__SHIFT 0x0
+-#define UNP1_UNP_GRPH_X_END_L__GRPH_X_END_L_MASK 0x00007FFFL
+-//UNP1_UNP_GRPH_X_END_C
+-#define UNP1_UNP_GRPH_X_END_C__GRPH_X_END_C__SHIFT 0x0
+-#define UNP1_UNP_GRPH_X_END_C__GRPH_X_END_C_MASK 0x00007FFFL
+-//UNP1_UNP_GRPH_Y_END_L
+-#define UNP1_UNP_GRPH_Y_END_L__GRPH_Y_END_L__SHIFT 0x0
+-#define UNP1_UNP_GRPH_Y_END_L__GRPH_Y_END_L_MASK 0x00007FFFL
+-//UNP1_UNP_GRPH_Y_END_C
+-#define UNP1_UNP_GRPH_Y_END_C__GRPH_Y_END_C__SHIFT 0x0
+-#define UNP1_UNP_GRPH_Y_END_C__GRPH_Y_END_C_MASK 0x00007FFFL
+-//UNP1_UNP_GRPH_UPDATE
+-#define UNP1_UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0
+-#define UNP1_UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1
+-#define UNP1_UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2
+-#define UNP1_UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3
+-#define UNP1_UNP_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10
+-#define UNP1_UNP_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14
+-#define UNP1_UNP_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+-#define UNP1_UNP_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c
+-#define UNP1_UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x00000001L
+-#define UNP1_UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x00000002L
+-#define UNP1_UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x00000004L
+-#define UNP1_UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x00000008L
+-#define UNP1_UNP_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x00010000L
+-#define UNP1_UNP_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x00100000L
+-#define UNP1_UNP_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
+-#define UNP1_UNP_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000L
+-//UNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT
+-#define UNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L__SHIFT 0x0
+-#define UNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C__SHIFT 0x8
+-#define UNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L_MASK 0x000000FFL
+-#define UNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C_MASK 0x0000FF00L
+-//UNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L
+-#define UNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L__GRPH_SURFACE_ADDRESS_INUSE_L__SHIFT 0x8
+-#define UNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L__GRPH_SURFACE_ADDRESS_INUSE_L_MASK 0xFFFFFF00L
+-//UNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C
+-#define UNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C__GRPH_SURFACE_ADDRESS_INUSE_C__SHIFT 0x8
+-#define UNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C__GRPH_SURFACE_ADDRESS_INUSE_C_MASK 0xFFFFFF00L
+-//UNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L
+-#define UNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__SHIFT 0x0
+-#define UNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_MASK 0x000000FFL
+-//UNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C
+-#define UNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__SHIFT 0x0
+-#define UNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_MASK 0x000000FFL
+-//UNP1_UNP_DVMM_PTE_CONTROL
+-#define UNP1_UNP_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT 0x0
+-#define UNP1_UNP_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT 0x1
+-#define UNP1_UNP_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT 0x5
+-#define UNP1_UNP_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT 0x9
+-#define UNP1_UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT 0x14
+-#define UNP1_UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT 0x15
+-#define UNP1_UNP_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK 0x00000001L
+-#define UNP1_UNP_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK 0x0000001EL
+-#define UNP1_UNP_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK 0x000001E0L
+-#define UNP1_UNP_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK 0x0007FE00L
+-#define UNP1_UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK 0x00100000L
+-#define UNP1_UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK 0x00200000L
+-//UNP1_UNP_DVMM_PTE_CONTROL_C
+-#define UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_USE_SINGLE_PTE_C__SHIFT 0x0
+-#define UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_WIDTH_C__SHIFT 0x1
+-#define UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_HEIGHT_C__SHIFT 0x5
+-#define UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_MIN_PTE_BEFORE_FLIP_C__SHIFT 0x9
+-#define UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE0_C__SHIFT 0x14
+-#define UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE1_C__SHIFT 0x15
+-#define UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_USE_SINGLE_PTE_C_MASK 0x00000001L
+-#define UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_WIDTH_C_MASK 0x0000001EL
+-#define UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_HEIGHT_C_MASK 0x000001E0L
+-#define UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_MIN_PTE_BEFORE_FLIP_C_MASK 0x0007FE00L
+-#define UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE0_C_MASK 0x00100000L
+-#define UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE1_C_MASK 0x00200000L
+-//UNP1_UNP_DVMM_PTE_ARB_CONTROL
+-#define UNP1_UNP_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT 0x0
+-#define UNP1_UNP_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT 0x8
+-#define UNP1_UNP_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK 0x0000003FL
+-#define UNP1_UNP_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK 0x0000FF00L
+-//UNP1_UNP_DVMM_PTE_ARB_CONTROL_C
+-#define UNP1_UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_PTE_REQ_PER_CHUNK_C__SHIFT 0x0
+-#define UNP1_UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_MAX_PTE_REQ_OUTSTANDING_C__SHIFT 0x8
+-#define UNP1_UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_PTE_REQ_PER_CHUNK_C_MASK 0x0000003FL
+-#define UNP1_UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_MAX_PTE_REQ_OUTSTANDING_C_MASK 0x0000FF00L
+-//UNP1_UNP_GRPH_INTERRUPT_STATUS
+-#define UNP1_UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0
+-#define UNP1_UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8
+-#define UNP1_UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x00000001L
+-#define UNP1_UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x00000100L
+-//UNP1_UNP_GRPH_INTERRUPT_CONTROL
+-#define UNP1_UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0
+-#define UNP1_UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8
+-#define UNP1_UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x00000001L
+-#define UNP1_UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x00000100L
+-//UNP1_UNP_GRPH_STEREOSYNC_FLIP
+-#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0
+-#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x4
+-#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_EN__SHIFT 0x8
+-#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_MODE__SHIFT 0xc
+-#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10
+-#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11
+-#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_BOTTOM_SURFACE_PENDING__SHIFT 0x12
+-#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_BOTTOM_SURFACE_PENDING__SHIFT 0x13
+-#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c
+-#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x00000001L
+-#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x00000030L
+-#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_EN_MASK 0x00000100L
+-#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_MODE_MASK 0x00003000L
+-#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x00010000L
+-#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x00020000L
+-#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_BOTTOM_SURFACE_PENDING_MASK 0x00040000L
+-#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_BOTTOM_SURFACE_PENDING_MASK 0x00080000L
+-#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000L
+-//UNP1_UNP_FLIP_CONTROL
+-#define UNP1_UNP_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT 0x0
+-#define UNP1_UNP_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK 0x00000001L
+-//UNP1_UNP_CRC_CONTROL
+-#define UNP1_UNP_CRC_CONTROL__UNP_CRC_ENABLE__SHIFT 0x0
+-#define UNP1_UNP_CRC_CONTROL__UNP_CRC_SOURCE_SEL__SHIFT 0x2
+-#define UNP1_UNP_CRC_CONTROL__UNP_CRC_LINE_SEL__SHIFT 0x8
+-#define UNP1_UNP_CRC_CONTROL__UNP_CRC_ENABLE_MASK 0x00000001L
+-#define UNP1_UNP_CRC_CONTROL__UNP_CRC_SOURCE_SEL_MASK 0x0000001CL
+-#define UNP1_UNP_CRC_CONTROL__UNP_CRC_LINE_SEL_MASK 0x00000300L
+-//UNP1_UNP_CRC_MASK
+-#define UNP1_UNP_CRC_MASK__UNP_CRC_MASK__SHIFT 0x0
+-#define UNP1_UNP_CRC_MASK__UNP_CRC_MASK_MASK 0xFFFFFFFFL
+-//UNP1_UNP_CRC_CURRENT
+-#define UNP1_UNP_CRC_CURRENT__UNP_CRC_CURRENT__SHIFT 0x0
+-#define UNP1_UNP_CRC_CURRENT__UNP_CRC_CURRENT_MASK 0xFFFFFFFFL
+-//UNP1_UNP_CRC_LAST
+-#define UNP1_UNP_CRC_LAST__UNP_CRC_LAST__SHIFT 0x0
+-#define UNP1_UNP_CRC_LAST__UNP_CRC_LAST_MASK 0xFFFFFFFFL
+-//UNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK
+-#define UNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK__UNP_LB_GAP_BETWEEN_CHUNK__SHIFT 0x4
+-#define UNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK__UNP_LB_GAP_BETWEEN_CHUNK_MASK 0x000001F0L
+-//UNP1_UNP_HW_ROTATION
+-#define UNP1_UNP_HW_ROTATION__ROTATION_ANGLE__SHIFT 0x0
+-#define UNP1_UNP_HW_ROTATION__PIXEL_DROP__SHIFT 0x4
+-#define UNP1_UNP_HW_ROTATION__BUFFER_MODE__SHIFT 0x8
+-#define UNP1_UNP_HW_ROTATION__ROTATION_ANGLE_MASK 0x00000007L
+-#define UNP1_UNP_HW_ROTATION__PIXEL_DROP_MASK 0x00000010L
+-#define UNP1_UNP_HW_ROTATION__BUFFER_MODE_MASK 0x00000100L
+-
+-
+-// addressBlock: dce_dc_lbv1_dispdec
+-//LBV1_LBV_DATA_FORMAT
+-#define LBV1_LBV_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0
+-#define LBV1_LBV_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2
+-#define LBV1_LBV_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3
+-#define LBV1_LBV_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4
+-#define LBV1_LBV_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5
+-#define LBV1_LBV_DATA_FORMAT__DITHER_EN__SHIFT 0x6
+-#define LBV1_LBV_DATA_FORMAT__DOWNSCALE_PREFETCH_EN__SHIFT 0x7
+-#define LBV1_LBV_DATA_FORMAT__PREFETCH__SHIFT 0xc
+-#define LBV1_LBV_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18
+-#define LBV1_LBV_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f
+-#define LBV1_LBV_DATA_FORMAT__PIXEL_DEPTH_MASK 0x00000003L
+-#define LBV1_LBV_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x00000004L
+-#define LBV1_LBV_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000008L
+-#define LBV1_LBV_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x00000010L
+-#define LBV1_LBV_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x00000020L
+-#define LBV1_LBV_DATA_FORMAT__DITHER_EN_MASK 0x00000040L
+-#define LBV1_LBV_DATA_FORMAT__DOWNSCALE_PREFETCH_EN_MASK 0x00000080L
+-#define LBV1_LBV_DATA_FORMAT__PREFETCH_MASK 0x00001000L
+-#define LBV1_LBV_DATA_FORMAT__REQUEST_MODE_MASK 0x01000000L
+-#define LBV1_LBV_DATA_FORMAT__ALPHA_EN_MASK 0x80000000L
+-//LBV1_LBV_MEMORY_CTRL
+-#define LBV1_LBV_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0
+-#define LBV1_LBV_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
+-#define LBV1_LBV_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14
+-#define LBV1_LBV_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0x00000FFFL
+-#define LBV1_LBV_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x000F0000L
+-#define LBV1_LBV_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x00300000L
+-//LBV1_LBV_MEMORY_SIZE_STATUS
+-#define LBV1_LBV_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0
+-#define LBV1_LBV_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0x00000FFFL
+-//LBV1_LBV_DESKTOP_HEIGHT
+-#define LBV1_LBV_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0
+-#define LBV1_LBV_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x00007FFFL
+-//LBV1_LBV_VLINE_START_END
+-#define LBV1_LBV_VLINE_START_END__VLINE_START__SHIFT 0x0
+-#define LBV1_LBV_VLINE_START_END__VLINE_END__SHIFT 0x10
+-#define LBV1_LBV_VLINE_START_END__VLINE_INV__SHIFT 0x1f
+-#define LBV1_LBV_VLINE_START_END__VLINE_START_MASK 0x00003FFFL
+-#define LBV1_LBV_VLINE_START_END__VLINE_END_MASK 0x7FFF0000L
+-#define LBV1_LBV_VLINE_START_END__VLINE_INV_MASK 0x80000000L
+-//LBV1_LBV_VLINE2_START_END
+-#define LBV1_LBV_VLINE2_START_END__VLINE2_START__SHIFT 0x0
+-#define LBV1_LBV_VLINE2_START_END__VLINE2_END__SHIFT 0x10
+-#define LBV1_LBV_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f
+-#define LBV1_LBV_VLINE2_START_END__VLINE2_START_MASK 0x00003FFFL
+-#define LBV1_LBV_VLINE2_START_END__VLINE2_END_MASK 0x7FFF0000L
+-#define LBV1_LBV_VLINE2_START_END__VLINE2_INV_MASK 0x80000000L
+-//LBV1_LBV_V_COUNTER
+-#define LBV1_LBV_V_COUNTER__V_COUNTER__SHIFT 0x0
+-#define LBV1_LBV_V_COUNTER__V_COUNTER_MASK 0x00007FFFL
+-//LBV1_LBV_SNAPSHOT_V_COUNTER
+-#define LBV1_LBV_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0
+-#define LBV1_LBV_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x00007FFFL
+-//LBV1_LBV_V_COUNTER_CHROMA
+-#define LBV1_LBV_V_COUNTER_CHROMA__V_COUNTER_CHROMA__SHIFT 0x0
+-#define LBV1_LBV_V_COUNTER_CHROMA__V_COUNTER_CHROMA_MASK 0x00007FFFL
+-//LBV1_LBV_SNAPSHOT_V_COUNTER_CHROMA
+-#define LBV1_LBV_SNAPSHOT_V_COUNTER_CHROMA__SNAPSHOT_V_COUNTER_CHROMA__SHIFT 0x0
+-#define LBV1_LBV_SNAPSHOT_V_COUNTER_CHROMA__SNAPSHOT_V_COUNTER_CHROMA_MASK 0x00007FFFL
+-//LBV1_LBV_INTERRUPT_MASK
+-#define LBV1_LBV_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0
+-#define LBV1_LBV_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4
+-#define LBV1_LBV_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8
+-#define LBV1_LBV_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x00000001L
+-#define LBV1_LBV_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x00000010L
+-#define LBV1_LBV_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x00000100L
+-//LBV1_LBV_VLINE_STATUS
+-#define LBV1_LBV_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0
+-#define LBV1_LBV_VLINE_STATUS__VLINE_ACK__SHIFT 0x4
+-#define LBV1_LBV_VLINE_STATUS__VLINE_STAT__SHIFT 0xc
+-#define LBV1_LBV_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10
+-#define LBV1_LBV_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11
+-#define LBV1_LBV_VLINE_STATUS__VLINE_OCCURRED_MASK 0x00000001L
+-#define LBV1_LBV_VLINE_STATUS__VLINE_ACK_MASK 0x00000010L
+-#define LBV1_LBV_VLINE_STATUS__VLINE_STAT_MASK 0x00001000L
+-#define LBV1_LBV_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x00010000L
+-#define LBV1_LBV_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x00020000L
+-//LBV1_LBV_VLINE2_STATUS
+-#define LBV1_LBV_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0
+-#define LBV1_LBV_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4
+-#define LBV1_LBV_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc
+-#define LBV1_LBV_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10
+-#define LBV1_LBV_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11
+-#define LBV1_LBV_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x00000001L
+-#define LBV1_LBV_VLINE2_STATUS__VLINE2_ACK_MASK 0x00000010L
+-#define LBV1_LBV_VLINE2_STATUS__VLINE2_STAT_MASK 0x00001000L
+-#define LBV1_LBV_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x00010000L
+-#define LBV1_LBV_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x00020000L
+-//LBV1_LBV_VBLANK_STATUS
+-#define LBV1_LBV_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0
+-#define LBV1_LBV_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4
+-#define LBV1_LBV_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc
+-#define LBV1_LBV_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10
+-#define LBV1_LBV_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11
+-#define LBV1_LBV_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x00000001L
+-#define LBV1_LBV_VBLANK_STATUS__VBLANK_ACK_MASK 0x00000010L
+-#define LBV1_LBV_VBLANK_STATUS__VBLANK_STAT_MASK 0x00001000L
+-#define LBV1_LBV_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x00010000L
+-#define LBV1_LBV_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x00020000L
+-//LBV1_LBV_SYNC_RESET_SEL
+-#define LBV1_LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0
+-#define LBV1_LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4
+-#define LBV1_LBV_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8
+-#define LBV1_LBV_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16
+-#define LBV1_LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x00000003L
+-#define LBV1_LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x00000010L
+-#define LBV1_LBV_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0x0000FF00L
+-#define LBV1_LBV_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0x00C00000L
+-//LBV1_LBV_BLACK_KEYER_R_CR
+-#define LBV1_LBV_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4
+-#define LBV1_LBV_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0x0000FFF0L
+-//LBV1_LBV_BLACK_KEYER_G_Y
+-#define LBV1_LBV_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4
+-#define LBV1_LBV_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0x0000FFF0L
+-//LBV1_LBV_BLACK_KEYER_B_CB
+-#define LBV1_LBV_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4
+-#define LBV1_LBV_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0x0000FFF0L
+-//LBV1_LBV_KEYER_COLOR_CTRL
+-#define LBV1_LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0
+-#define LBV1_LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8
+-#define LBV1_LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x00000001L
+-#define LBV1_LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x00000100L
+-//LBV1_LBV_KEYER_COLOR_R_CR
+-#define LBV1_LBV_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4
+-#define LBV1_LBV_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0x0000FFF0L
+-//LBV1_LBV_KEYER_COLOR_G_Y
+-#define LBV1_LBV_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4
+-#define LBV1_LBV_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0x0000FFF0L
+-//LBV1_LBV_KEYER_COLOR_B_CB
+-#define LBV1_LBV_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4
+-#define LBV1_LBV_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0x0000FFF0L
+-//LBV1_LBV_KEYER_COLOR_REP_R_CR
+-#define LBV1_LBV_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4
+-#define LBV1_LBV_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0x0000FFF0L
+-//LBV1_LBV_KEYER_COLOR_REP_G_Y
+-#define LBV1_LBV_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4
+-#define LBV1_LBV_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0x0000FFF0L
+-//LBV1_LBV_KEYER_COLOR_REP_B_CB
+-#define LBV1_LBV_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4
+-#define LBV1_LBV_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0x0000FFF0L
+-//LBV1_LBV_BUFFER_LEVEL_STATUS
+-#define LBV1_LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0
+-#define LBV1_LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa
+-#define LBV1_LBV_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10
+-#define LBV1_LBV_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c
+-#define LBV1_LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x0000003FL
+-#define LBV1_LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0x0000FC00L
+-#define LBV1_LBV_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0x0FFF0000L
+-#define LBV1_LBV_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xF0000000L
+-//LBV1_LBV_BUFFER_URGENCY_CTRL
+-#define LBV1_LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0
+-#define LBV1_LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10
+-#define LBV1_LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0x00000FFFL
+-#define LBV1_LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0x0FFF0000L
+-//LBV1_LBV_BUFFER_URGENCY_STATUS
+-#define LBV1_LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0
+-#define LBV1_LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10
+-#define LBV1_LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0x00000FFFL
+-#define LBV1_LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x00010000L
+-//LBV1_LBV_BUFFER_STATUS
+-#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0
+-#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4
+-#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8
+-#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc
+-#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10
+-#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14
+-#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18
+-#define LBV1_LBV_BUFFER_STATUS__LB_ENABLE_HIGH_THROUGHPUT__SHIFT 0x19
+-#define LBV1_LBV_BUFFER_STATUS__LB_HIGH_THROUGHPUT_CNTL__SHIFT 0x1a
+-#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0x0000000FL
+-#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x00000010L
+-#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x00000100L
+-#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x00001000L
+-#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x00010000L
+-#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x00100000L
+-#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x01000000L
+-#define LBV1_LBV_BUFFER_STATUS__LB_ENABLE_HIGH_THROUGHPUT_MASK 0x02000000L
+-#define LBV1_LBV_BUFFER_STATUS__LB_HIGH_THROUGHPUT_CNTL_MASK 0x1C000000L
+-//LBV1_LBV_NO_OUTSTANDING_REQ_STATUS
+-#define LBV1_LBV_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0
+-#define LBV1_LBV_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x00000001L
+-
+-
+-// addressBlock: dce_dc_sclv1_dispdec
+-//SCLV1_SCLV_COEF_RAM_SELECT
+-#define SCLV1_SCLV_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0
+-#define SCLV1_SCLV_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8
+-#define SCLV1_SCLV_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10
+-#define SCLV1_SCLV_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x00000003L
+-#define SCLV1_SCLV_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x00007F00L
+-#define SCLV1_SCLV_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x00030000L
+-//SCLV1_SCLV_COEF_RAM_TAP_DATA
+-#define SCLV1_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0
+-#define SCLV1_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
+-#define SCLV1_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10
+-#define SCLV1_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
+-#define SCLV1_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL
+-#define SCLV1_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L
+-#define SCLV1_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L
+-#define SCLV1_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L
+-//SCLV1_SCLV_MODE
+-#define SCLV1_SCLV_MODE__SCL_MODE__SHIFT 0x0
+-#define SCLV1_SCLV_MODE__SCL_MODE_C__SHIFT 0x2
+-#define SCLV1_SCLV_MODE__SCL_PSCL_EN__SHIFT 0x4
+-#define SCLV1_SCLV_MODE__SCL_PSCL_EN_C__SHIFT 0x5
+-#define SCLV1_SCLV_MODE__SCL_INTERLACE_SOURCE__SHIFT 0x8
+-#define SCLV1_SCLV_MODE__SCL_MODE_MASK 0x00000003L
+-#define SCLV1_SCLV_MODE__SCL_MODE_C_MASK 0x0000000CL
+-#define SCLV1_SCLV_MODE__SCL_PSCL_EN_MASK 0x00000010L
+-#define SCLV1_SCLV_MODE__SCL_PSCL_EN_C_MASK 0x00000020L
+-#define SCLV1_SCLV_MODE__SCL_INTERLACE_SOURCE_MASK 0x00000300L
+-//SCLV1_SCLV_TAP_CONTROL
+-#define SCLV1_SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0
+-#define SCLV1_SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x4
+-#define SCLV1_SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_C__SHIFT 0x8
+-#define SCLV1_SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_C__SHIFT 0xc
+-#define SCLV1_SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x00000007L
+-#define SCLV1_SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0x00000070L
+-#define SCLV1_SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_C_MASK 0x00000700L
+-#define SCLV1_SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_C_MASK 0x00007000L
+-//SCLV1_SCLV_CONTROL
+-#define SCLV1_SCLV_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
+-#define SCLV1_SCLV_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4
+-#define SCLV1_SCLV_CONTROL__SCL_TOTAL_PHASE__SHIFT 0x8
+-#define SCLV1_SCLV_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L
+-#define SCLV1_SCLV_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x00000010L
+-#define SCLV1_SCLV_CONTROL__SCL_TOTAL_PHASE_MASK 0x00000100L
+-//SCLV1_SCLV_MANUAL_REPLICATE_CONTROL
+-#define SCLV1_SCLV_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
+-#define SCLV1_SCLV_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
+-#define SCLV1_SCLV_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL
+-#define SCLV1_SCLV_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L
+-//SCLV1_SCLV_AUTOMATIC_MODE_CONTROL
+-#define SCLV1_SCLV_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0
+-#define SCLV1_SCLV_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10
+-#define SCLV1_SCLV_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x00000001L
+-#define SCLV1_SCLV_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x00010000L
+-//SCLV1_SCLV_HORZ_FILTER_CONTROL
+-#define SCLV1_SCLV_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+-#define SCLV1_SCLV_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
+-//SCLV1_SCLV_HORZ_FILTER_SCALE_RATIO
+-#define SCLV1_SCLV_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
+-#define SCLV1_SCLV_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL
+-//SCLV1_SCLV_HORZ_FILTER_INIT
+-#define SCLV1_SCLV_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
+-#define SCLV1_SCLV_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
+-#define SCLV1_SCLV_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL
+-#define SCLV1_SCLV_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L
+-//SCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_C
+-#define SCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0
+-#define SCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x03FFFFFFL
+-//SCLV1_SCLV_HORZ_FILTER_INIT_C
+-#define SCLV1_SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0
+-#define SCLV1_SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18
+-#define SCLV1_SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL
+-#define SCLV1_SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L
+-//SCLV1_SCLV_VERT_FILTER_CONTROL
+-#define SCLV1_SCLV_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+-#define SCLV1_SCLV_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
+-//SCLV1_SCLV_VERT_FILTER_SCALE_RATIO
+-#define SCLV1_SCLV_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
+-#define SCLV1_SCLV_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL
+-//SCLV1_SCLV_VERT_FILTER_INIT
+-#define SCLV1_SCLV_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
+-#define SCLV1_SCLV_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
+-#define SCLV1_SCLV_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL
+-#define SCLV1_SCLV_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x07000000L
+-//SCLV1_SCLV_VERT_FILTER_INIT_BOT
+-#define SCLV1_SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
+-#define SCLV1_SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
+-#define SCLV1_SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL
+-#define SCLV1_SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x07000000L
+-//SCLV1_SCLV_VERT_FILTER_SCALE_RATIO_C
+-#define SCLV1_SCLV_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0
+-#define SCLV1_SCLV_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x03FFFFFFL
+-//SCLV1_SCLV_VERT_FILTER_INIT_C
+-#define SCLV1_SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0
+-#define SCLV1_SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18
+-#define SCLV1_SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL
+-#define SCLV1_SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x07000000L
+-//SCLV1_SCLV_VERT_FILTER_INIT_BOT_C
+-#define SCLV1_SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0
+-#define SCLV1_SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18
+-#define SCLV1_SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL
+-#define SCLV1_SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x07000000L
+-//SCLV1_SCLV_ROUND_OFFSET
+-#define SCLV1_SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0
+-#define SCLV1_SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10
+-#define SCLV1_SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0x0000FFFFL
+-#define SCLV1_SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xFFFF0000L
+-//SCLV1_SCLV_UPDATE
+-#define SCLV1_SCLV_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
+-#define SCLV1_SCLV_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8
+-#define SCLV1_SCLV_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10
+-#define SCLV1_SCLV_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18
+-#define SCLV1_SCLV_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L
+-#define SCLV1_SCLV_UPDATE__SCL_UPDATE_TAKEN_MASK 0x00000100L
+-#define SCLV1_SCLV_UPDATE__SCL_UPDATE_LOCK_MASK 0x00010000L
+-#define SCLV1_SCLV_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x01000000L
+-//SCLV1_SCLV_ALU_CONTROL
+-#define SCLV1_SCLV_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0
+-#define SCLV1_SCLV_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x00000001L
+-//SCLV1_SCLV_VIEWPORT_START
+-#define SCLV1_SCLV_VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0
+-#define SCLV1_SCLV_VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10
+-#define SCLV1_SCLV_VIEWPORT_START__VIEWPORT_Y_START_MASK 0x00003FFFL
+-#define SCLV1_SCLV_VIEWPORT_START__VIEWPORT_X_START_MASK 0x3FFF0000L
+-//SCLV1_SCLV_VIEWPORT_START_SECONDARY
+-#define SCLV1_SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0
+-#define SCLV1_SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10
+-#define SCLV1_SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x00003FFFL
+-#define SCLV1_SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3FFF0000L
+-//SCLV1_SCLV_VIEWPORT_SIZE
+-#define SCLV1_SCLV_VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0
+-#define SCLV1_SCLV_VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10
+-#define SCLV1_SCLV_VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x00001FFFL
+-#define SCLV1_SCLV_VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x1FFF0000L
+-//SCLV1_SCLV_VIEWPORT_START_C
+-#define SCLV1_SCLV_VIEWPORT_START_C__VIEWPORT_Y_START_C__SHIFT 0x0
+-#define SCLV1_SCLV_VIEWPORT_START_C__VIEWPORT_X_START_C__SHIFT 0x10
+-#define SCLV1_SCLV_VIEWPORT_START_C__VIEWPORT_Y_START_C_MASK 0x00003FFFL
+-#define SCLV1_SCLV_VIEWPORT_START_C__VIEWPORT_X_START_C_MASK 0x3FFF0000L
+-//SCLV1_SCLV_VIEWPORT_START_SECONDARY_C
+-#define SCLV1_SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_Y_START_SECONDARY_C__SHIFT 0x0
+-#define SCLV1_SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_X_START_SECONDARY_C__SHIFT 0x10
+-#define SCLV1_SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_Y_START_SECONDARY_C_MASK 0x00003FFFL
+-#define SCLV1_SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_X_START_SECONDARY_C_MASK 0x3FFF0000L
+-//SCLV1_SCLV_VIEWPORT_SIZE_C
+-#define SCLV1_SCLV_VIEWPORT_SIZE_C__VIEWPORT_HEIGHT_C__SHIFT 0x0
+-#define SCLV1_SCLV_VIEWPORT_SIZE_C__VIEWPORT_WIDTH_C__SHIFT 0x10
+-#define SCLV1_SCLV_VIEWPORT_SIZE_C__VIEWPORT_HEIGHT_C_MASK 0x00001FFFL
+-#define SCLV1_SCLV_VIEWPORT_SIZE_C__VIEWPORT_WIDTH_C_MASK 0x1FFF0000L
+-//SCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT
+-#define SCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
+-#define SCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
+-#define SCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL
+-#define SCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L
+-//SCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM
+-#define SCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
+-#define SCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
+-#define SCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL
+-#define SCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L
+-//SCLV1_SCLV_MODE_CHANGE_DET1
+-#define SCLV1_SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0
+-#define SCLV1_SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4
+-#define SCLV1_SCLV_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7
+-#define SCLV1_SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x00000001L
+-#define SCLV1_SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x00000010L
+-#define SCLV1_SCLV_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0x0FFFFF80L
+-//SCLV1_SCLV_MODE_CHANGE_DET2
+-#define SCLV1_SCLV_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0
+-#define SCLV1_SCLV_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x001FFFFFL
+-//SCLV1_SCLV_MODE_CHANGE_DET3
+-#define SCLV1_SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0
+-#define SCLV1_SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10
+-#define SCLV1_SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x00003FFFL
+-#define SCLV1_SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3FFF0000L
+-//SCLV1_SCLV_MODE_CHANGE_MASK
+-#define SCLV1_SCLV_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0
+-#define SCLV1_SCLV_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x00000001L
+-//SCLV1_SCLV_HORZ_FILTER_INIT_BOT
+-#define SCLV1_SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_FRAC_BOT__SHIFT 0x0
+-#define SCLV1_SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_INT_BOT__SHIFT 0x18
+-#define SCLV1_SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_FRAC_BOT_MASK 0x00FFFFFFL
+-#define SCLV1_SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_INT_BOT_MASK 0x0F000000L
+-//SCLV1_SCLV_HORZ_FILTER_INIT_BOT_C
+-#define SCLV1_SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_FRAC_BOT_C__SHIFT 0x0
+-#define SCLV1_SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_INT_BOT_C__SHIFT 0x18
+-#define SCLV1_SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL
+-#define SCLV1_SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_INT_BOT_C_MASK 0x0F000000L
+-
+-
+-// addressBlock: dce_dc_col_man1_dispdec
+-//COL_MAN1_COL_MAN_UPDATE
+-#define COL_MAN1_COL_MAN_UPDATE__COL_MAN_UPDATE_PENDING__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_UPDATE__COL_MAN_UPDATE_TAKEN__SHIFT 0x1
+-#define COL_MAN1_COL_MAN_UPDATE__COL_MAN_UPDATE_LOCK__SHIFT 0x10
+-#define COL_MAN1_COL_MAN_UPDATE__COL_MAN_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+-#define COL_MAN1_COL_MAN_UPDATE__COL_MAN_UPDATE_PENDING_MASK 0x00000001L
+-#define COL_MAN1_COL_MAN_UPDATE__COL_MAN_UPDATE_TAKEN_MASK 0x00000002L
+-#define COL_MAN1_COL_MAN_UPDATE__COL_MAN_UPDATE_LOCK_MASK 0x00010000L
+-#define COL_MAN1_COL_MAN_UPDATE__COL_MAN_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
+-//COL_MAN1_COL_MAN_INPUT_CSC_CONTROL
+-#define COL_MAN1_COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_MODE__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_INPUT_TYPE__SHIFT 0x8
+-#define COL_MAN1_COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_CONVERSION_MODE__SHIFT 0x10
+-#define COL_MAN1_COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_MODE_MASK 0x00000003L
+-#define COL_MAN1_COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_INPUT_TYPE_MASK 0x00000300L
+-#define COL_MAN1_COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_CONVERSION_MODE_MASK 0x00010000L
+-//COL_MAN1_INPUT_CSC_C11_C12_A
+-#define COL_MAN1_INPUT_CSC_C11_C12_A__INPUT_CSC_C11_A__SHIFT 0x0
+-#define COL_MAN1_INPUT_CSC_C11_C12_A__INPUT_CSC_C12_A__SHIFT 0x10
+-#define COL_MAN1_INPUT_CSC_C11_C12_A__INPUT_CSC_C11_A_MASK 0x0000FFFFL
+-#define COL_MAN1_INPUT_CSC_C11_C12_A__INPUT_CSC_C12_A_MASK 0xFFFF0000L
+-//COL_MAN1_INPUT_CSC_C13_C14_A
+-#define COL_MAN1_INPUT_CSC_C13_C14_A__INPUT_CSC_C13_A__SHIFT 0x0
+-#define COL_MAN1_INPUT_CSC_C13_C14_A__INPUT_CSC_C14_A__SHIFT 0x10
+-#define COL_MAN1_INPUT_CSC_C13_C14_A__INPUT_CSC_C13_A_MASK 0x0000FFFFL
+-#define COL_MAN1_INPUT_CSC_C13_C14_A__INPUT_CSC_C14_A_MASK 0xFFFF0000L
+-//COL_MAN1_INPUT_CSC_C21_C22_A
+-#define COL_MAN1_INPUT_CSC_C21_C22_A__INPUT_CSC_C21_A__SHIFT 0x0
+-#define COL_MAN1_INPUT_CSC_C21_C22_A__INPUT_CSC_C22_A__SHIFT 0x10
+-#define COL_MAN1_INPUT_CSC_C21_C22_A__INPUT_CSC_C21_A_MASK 0x0000FFFFL
+-#define COL_MAN1_INPUT_CSC_C21_C22_A__INPUT_CSC_C22_A_MASK 0xFFFF0000L
+-//COL_MAN1_INPUT_CSC_C23_C24_A
+-#define COL_MAN1_INPUT_CSC_C23_C24_A__INPUT_CSC_C23_A__SHIFT 0x0
+-#define COL_MAN1_INPUT_CSC_C23_C24_A__INPUT_CSC_C24_A__SHIFT 0x10
+-#define COL_MAN1_INPUT_CSC_C23_C24_A__INPUT_CSC_C23_A_MASK 0x0000FFFFL
+-#define COL_MAN1_INPUT_CSC_C23_C24_A__INPUT_CSC_C24_A_MASK 0xFFFF0000L
+-//COL_MAN1_INPUT_CSC_C31_C32_A
+-#define COL_MAN1_INPUT_CSC_C31_C32_A__INPUT_CSC_C31_A__SHIFT 0x0
+-#define COL_MAN1_INPUT_CSC_C31_C32_A__INPUT_CSC_C32_A__SHIFT 0x10
+-#define COL_MAN1_INPUT_CSC_C31_C32_A__INPUT_CSC_C31_A_MASK 0x0000FFFFL
+-#define COL_MAN1_INPUT_CSC_C31_C32_A__INPUT_CSC_C32_A_MASK 0xFFFF0000L
+-//COL_MAN1_INPUT_CSC_C33_C34_A
+-#define COL_MAN1_INPUT_CSC_C33_C34_A__INPUT_CSC_C33_A__SHIFT 0x0
+-#define COL_MAN1_INPUT_CSC_C33_C34_A__INPUT_CSC_C34_A__SHIFT 0x10
+-#define COL_MAN1_INPUT_CSC_C33_C34_A__INPUT_CSC_C33_A_MASK 0x0000FFFFL
+-#define COL_MAN1_INPUT_CSC_C33_C34_A__INPUT_CSC_C34_A_MASK 0xFFFF0000L
+-//COL_MAN1_INPUT_CSC_C11_C12_B
+-#define COL_MAN1_INPUT_CSC_C11_C12_B__INPUT_CSC_C11_B__SHIFT 0x0
+-#define COL_MAN1_INPUT_CSC_C11_C12_B__INPUT_CSC_C12_B__SHIFT 0x10
+-#define COL_MAN1_INPUT_CSC_C11_C12_B__INPUT_CSC_C11_B_MASK 0x0000FFFFL
+-#define COL_MAN1_INPUT_CSC_C11_C12_B__INPUT_CSC_C12_B_MASK 0xFFFF0000L
+-//COL_MAN1_INPUT_CSC_C13_C14_B
+-#define COL_MAN1_INPUT_CSC_C13_C14_B__INPUT_CSC_C13_B__SHIFT 0x0
+-#define COL_MAN1_INPUT_CSC_C13_C14_B__INPUT_CSC_C14_B__SHIFT 0x10
+-#define COL_MAN1_INPUT_CSC_C13_C14_B__INPUT_CSC_C13_B_MASK 0x0000FFFFL
+-#define COL_MAN1_INPUT_CSC_C13_C14_B__INPUT_CSC_C14_B_MASK 0xFFFF0000L
+-//COL_MAN1_INPUT_CSC_C21_C22_B
+-#define COL_MAN1_INPUT_CSC_C21_C22_B__INPUT_CSC_C21_B__SHIFT 0x0
+-#define COL_MAN1_INPUT_CSC_C21_C22_B__INPUT_CSC_C22_B__SHIFT 0x10
+-#define COL_MAN1_INPUT_CSC_C21_C22_B__INPUT_CSC_C21_B_MASK 0x0000FFFFL
+-#define COL_MAN1_INPUT_CSC_C21_C22_B__INPUT_CSC_C22_B_MASK 0xFFFF0000L
+-//COL_MAN1_INPUT_CSC_C23_C24_B
+-#define COL_MAN1_INPUT_CSC_C23_C24_B__INPUT_CSC_C23_B__SHIFT 0x0
+-#define COL_MAN1_INPUT_CSC_C23_C24_B__INPUT_CSC_C24_B__SHIFT 0x10
+-#define COL_MAN1_INPUT_CSC_C23_C24_B__INPUT_CSC_C23_B_MASK 0x0000FFFFL
+-#define COL_MAN1_INPUT_CSC_C23_C24_B__INPUT_CSC_C24_B_MASK 0xFFFF0000L
+-//COL_MAN1_INPUT_CSC_C31_C32_B
+-#define COL_MAN1_INPUT_CSC_C31_C32_B__INPUT_CSC_C31_B__SHIFT 0x0
+-#define COL_MAN1_INPUT_CSC_C31_C32_B__INPUT_CSC_C32_B__SHIFT 0x10
+-#define COL_MAN1_INPUT_CSC_C31_C32_B__INPUT_CSC_C31_B_MASK 0x0000FFFFL
+-#define COL_MAN1_INPUT_CSC_C31_C32_B__INPUT_CSC_C32_B_MASK 0xFFFF0000L
+-//COL_MAN1_INPUT_CSC_C33_C34_B
+-#define COL_MAN1_INPUT_CSC_C33_C34_B__INPUT_CSC_C33_B__SHIFT 0x0
+-#define COL_MAN1_INPUT_CSC_C33_C34_B__INPUT_CSC_C34_B__SHIFT 0x10
+-#define COL_MAN1_INPUT_CSC_C33_C34_B__INPUT_CSC_C33_B_MASK 0x0000FFFFL
+-#define COL_MAN1_INPUT_CSC_C33_C34_B__INPUT_CSC_C34_B_MASK 0xFFFF0000L
+-//COL_MAN1_PRESCALE_CONTROL
+-#define COL_MAN1_PRESCALE_CONTROL__PRESCALE_MODE__SHIFT 0x0
+-#define COL_MAN1_PRESCALE_CONTROL__PRESCALE_MODE_MASK 0x00000003L
+-//COL_MAN1_PRESCALE_VALUES_R
+-#define COL_MAN1_PRESCALE_VALUES_R__PRESCALE_BIAS_R__SHIFT 0x0
+-#define COL_MAN1_PRESCALE_VALUES_R__PRESCALE_SCALE_R__SHIFT 0x10
+-#define COL_MAN1_PRESCALE_VALUES_R__PRESCALE_BIAS_R_MASK 0x0000FFFFL
+-#define COL_MAN1_PRESCALE_VALUES_R__PRESCALE_SCALE_R_MASK 0xFFFF0000L
+-//COL_MAN1_PRESCALE_VALUES_G
+-#define COL_MAN1_PRESCALE_VALUES_G__PRESCALE_BIAS_G__SHIFT 0x0
+-#define COL_MAN1_PRESCALE_VALUES_G__PRESCALE_SCALE_G__SHIFT 0x10
+-#define COL_MAN1_PRESCALE_VALUES_G__PRESCALE_BIAS_G_MASK 0x0000FFFFL
+-#define COL_MAN1_PRESCALE_VALUES_G__PRESCALE_SCALE_G_MASK 0xFFFF0000L
+-//COL_MAN1_PRESCALE_VALUES_B
+-#define COL_MAN1_PRESCALE_VALUES_B__PRESCALE_BIAS_B__SHIFT 0x0
+-#define COL_MAN1_PRESCALE_VALUES_B__PRESCALE_SCALE_B__SHIFT 0x10
+-#define COL_MAN1_PRESCALE_VALUES_B__PRESCALE_BIAS_B_MASK 0x0000FFFFL
+-#define COL_MAN1_PRESCALE_VALUES_B__PRESCALE_SCALE_B_MASK 0xFFFF0000L
+-//COL_MAN1_COL_MAN_OUTPUT_CSC_CONTROL
+-#define COL_MAN1_COL_MAN_OUTPUT_CSC_CONTROL__OUTPUT_CSC_MODE__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_OUTPUT_CSC_CONTROL__OUTPUT_CSC_MODE_MASK 0x00000007L
+-//COL_MAN1_OUTPUT_CSC_C11_C12_A
+-#define COL_MAN1_OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C11_A__SHIFT 0x0
+-#define COL_MAN1_OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C12_A__SHIFT 0x10
+-#define COL_MAN1_OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C11_A_MASK 0x0000FFFFL
+-#define COL_MAN1_OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C12_A_MASK 0xFFFF0000L
+-//COL_MAN1_OUTPUT_CSC_C13_C14_A
+-#define COL_MAN1_OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C13_A__SHIFT 0x0
+-#define COL_MAN1_OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C14_A__SHIFT 0x10
+-#define COL_MAN1_OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C13_A_MASK 0x0000FFFFL
+-#define COL_MAN1_OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C14_A_MASK 0xFFFF0000L
+-//COL_MAN1_OUTPUT_CSC_C21_C22_A
+-#define COL_MAN1_OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C21_A__SHIFT 0x0
+-#define COL_MAN1_OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C22_A__SHIFT 0x10
+-#define COL_MAN1_OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C21_A_MASK 0x0000FFFFL
+-#define COL_MAN1_OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C22_A_MASK 0xFFFF0000L
+-//COL_MAN1_OUTPUT_CSC_C23_C24_A
+-#define COL_MAN1_OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C23_A__SHIFT 0x0
+-#define COL_MAN1_OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C24_A__SHIFT 0x10
+-#define COL_MAN1_OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C23_A_MASK 0x0000FFFFL
+-#define COL_MAN1_OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C24_A_MASK 0xFFFF0000L
+-//COL_MAN1_OUTPUT_CSC_C31_C32_A
+-#define COL_MAN1_OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C31_A__SHIFT 0x0
+-#define COL_MAN1_OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C32_A__SHIFT 0x10
+-#define COL_MAN1_OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C31_A_MASK 0x0000FFFFL
+-#define COL_MAN1_OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C32_A_MASK 0xFFFF0000L
+-//COL_MAN1_OUTPUT_CSC_C33_C34_A
+-#define COL_MAN1_OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C33_A__SHIFT 0x0
+-#define COL_MAN1_OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C34_A__SHIFT 0x10
+-#define COL_MAN1_OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C33_A_MASK 0x0000FFFFL
+-#define COL_MAN1_OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C34_A_MASK 0xFFFF0000L
+-//COL_MAN1_OUTPUT_CSC_C11_C12_B
+-#define COL_MAN1_OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C11_B__SHIFT 0x0
+-#define COL_MAN1_OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C12_B__SHIFT 0x10
+-#define COL_MAN1_OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C11_B_MASK 0x0000FFFFL
+-#define COL_MAN1_OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C12_B_MASK 0xFFFF0000L
+-//COL_MAN1_OUTPUT_CSC_C13_C14_B
+-#define COL_MAN1_OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C13_B__SHIFT 0x0
+-#define COL_MAN1_OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C14_B__SHIFT 0x10
+-#define COL_MAN1_OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C13_B_MASK 0x0000FFFFL
+-#define COL_MAN1_OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C14_B_MASK 0xFFFF0000L
+-//COL_MAN1_OUTPUT_CSC_C21_C22_B
+-#define COL_MAN1_OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C21_B__SHIFT 0x0
+-#define COL_MAN1_OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C22_B__SHIFT 0x10
+-#define COL_MAN1_OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C21_B_MASK 0x0000FFFFL
+-#define COL_MAN1_OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C22_B_MASK 0xFFFF0000L
+-//COL_MAN1_OUTPUT_CSC_C23_C24_B
+-#define COL_MAN1_OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C23_B__SHIFT 0x0
+-#define COL_MAN1_OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C24_B__SHIFT 0x10
+-#define COL_MAN1_OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C23_B_MASK 0x0000FFFFL
+-#define COL_MAN1_OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C24_B_MASK 0xFFFF0000L
+-//COL_MAN1_OUTPUT_CSC_C31_C32_B
+-#define COL_MAN1_OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C31_B__SHIFT 0x0
+-#define COL_MAN1_OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C32_B__SHIFT 0x10
+-#define COL_MAN1_OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C31_B_MASK 0x0000FFFFL
+-#define COL_MAN1_OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C32_B_MASK 0xFFFF0000L
+-//COL_MAN1_OUTPUT_CSC_C33_C34_B
+-#define COL_MAN1_OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C33_B__SHIFT 0x0
+-#define COL_MAN1_OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C34_B__SHIFT 0x10
+-#define COL_MAN1_OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C33_B_MASK 0x0000FFFFL
+-#define COL_MAN1_OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C34_B_MASK 0xFFFF0000L
+-//COL_MAN1_DENORM_CLAMP_CONTROL
+-#define COL_MAN1_DENORM_CLAMP_CONTROL__DENORM_MODE__SHIFT 0x0
+-#define COL_MAN1_DENORM_CLAMP_CONTROL__DENORM_10BIT_OUT__SHIFT 0x8
+-#define COL_MAN1_DENORM_CLAMP_CONTROL__DENORM_MODE_MASK 0x00000003L
+-#define COL_MAN1_DENORM_CLAMP_CONTROL__DENORM_10BIT_OUT_MASK 0x00000100L
+-//COL_MAN1_DENORM_CLAMP_RANGE_R_CR
+-#define COL_MAN1_DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MAX_R_CR__SHIFT 0x0
+-#define COL_MAN1_DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MIN_R_CR__SHIFT 0xc
+-#define COL_MAN1_DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MAX_R_CR_MASK 0x00000FFFL
+-#define COL_MAN1_DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MIN_R_CR_MASK 0x00FFF000L
+-//COL_MAN1_DENORM_CLAMP_RANGE_G_Y
+-#define COL_MAN1_DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MAX_G_Y__SHIFT 0x0
+-#define COL_MAN1_DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MIN_G_Y__SHIFT 0xc
+-#define COL_MAN1_DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MAX_G_Y_MASK 0x00000FFFL
+-#define COL_MAN1_DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MIN_G_Y_MASK 0x00FFF000L
+-//COL_MAN1_DENORM_CLAMP_RANGE_B_CB
+-#define COL_MAN1_DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MAX_B_CB__SHIFT 0x0
+-#define COL_MAN1_DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MIN_B_CB__SHIFT 0xc
+-#define COL_MAN1_DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MAX_B_CB_MASK 0x00000FFFL
+-#define COL_MAN1_DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MIN_B_CB_MASK 0x00FFF000L
+-//COL_MAN1_COL_MAN_FP_CONVERTED_FIELD
+-#define COL_MAN1_COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_DATA__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14
+-#define COL_MAN1_COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_DATA_MASK 0x0003FFFFL
+-#define COL_MAN1_COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_INDEX_MASK 0x07F00000L
+-//COL_MAN1_COL_MAN_REGAMMA_CONTROL
+-#define COL_MAN1_COL_MAN_REGAMMA_CONTROL__COL_MAN_REGAMMA_MODE__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_REGAMMA_CONTROL__COL_MAN_REGAMMA_MODE_MASK 0x00000007L
+-//COL_MAN1_COL_MAN_REGAMMA_LUT_INDEX
+-#define COL_MAN1_COL_MAN_REGAMMA_LUT_INDEX__COL_MAN_REGAMMA_LUT_INDEX__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_REGAMMA_LUT_INDEX__COL_MAN_REGAMMA_LUT_INDEX_MASK 0x000001FFL
+-//COL_MAN1_COL_MAN_REGAMMA_LUT_DATA
+-#define COL_MAN1_COL_MAN_REGAMMA_LUT_DATA__COL_MAN_REGAMMA_LUT_DATA__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_REGAMMA_LUT_DATA__COL_MAN_REGAMMA_LUT_DATA_MASK 0x0007FFFFL
+-//COL_MAN1_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK
+-#define COL_MAN1_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK__COL_MAN_REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK__COL_MAN_REGAMMA_LUT_WRITE_EN_MASK_MASK 0x00000007L
+-//COL_MAN1_COL_MAN_REGAMMA_CNTLA_START_CNTL
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_START_CNTL__COL_MAN_REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_START_CNTL__COL_MAN_REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_START_CNTL__COL_MAN_REGAMMA_CNTLA_EXP_REGION_START_MASK 0x0003FFFFL
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_START_CNTL__COL_MAN_REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
+-//COL_MAN1_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL__COL_MAN_REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL__COL_MAN_REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
+-//COL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL1
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL1__COL_MAN_REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL1__COL_MAN_REGAMMA_CNTLA_EXP_REGION_END_MASK 0x0000FFFFL
+-//COL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL2
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL2__COL_MAN_REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL2__COL_MAN_REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL2__COL_MAN_REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL2__COL_MAN_REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xFFFF0000L
+-//COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xb
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0xf
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1b
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00003800L
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x00FF8000L
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x38000000L
+-//COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xb
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0xf
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1b
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00003800L
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x00FF8000L
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x38000000L
+-//COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xb
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0xf
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1b
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00003800L
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x00FF8000L
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x38000000L
+-//COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xb
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0xf
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1b
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00003800L
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x00FF8000L
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x38000000L
+-//COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xb
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0xf
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1b
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00003800L
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x00FF8000L
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x38000000L
+-//COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xb
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0xf
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1b
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00003800L
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x00FF8000L
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x38000000L
+-//COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xb
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0xf
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1b
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00003800L
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x00FF8000L
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x38000000L
+-//COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xb
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0xf
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1b
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00003800L
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x00FF8000L
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x38000000L
+-//COL_MAN1_COL_MAN_REGAMMA_CNTLB_START_CNTL
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_START_CNTL__COL_MAN_REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_START_CNTL__COL_MAN_REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_START_CNTL__COL_MAN_REGAMMA_CNTLB_EXP_REGION_START_MASK 0x0003FFFFL
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_START_CNTL__COL_MAN_REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
+-//COL_MAN1_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL__COL_MAN_REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL__COL_MAN_REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
+-//COL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL1
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL1__COL_MAN_REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL1__COL_MAN_REGAMMA_CNTLB_EXP_REGION_END_MASK 0x0000FFFFL
+-//COL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL2
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL2__COL_MAN_REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL2__COL_MAN_REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL2__COL_MAN_REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL2__COL_MAN_REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xFFFF0000L
+-//COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xb
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0xf
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1b
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00003800L
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x00FF8000L
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x38000000L
+-//COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xb
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0xf
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1b
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00003800L
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x00FF8000L
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x38000000L
+-//COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xb
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0xf
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1b
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00003800L
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x00FF8000L
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x38000000L
+-//COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xb
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0xf
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1b
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00003800L
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x00FF8000L
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x38000000L
+-//COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xb
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0xf
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1b
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00003800L
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x00FF8000L
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x38000000L
+-//COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xb
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0xf
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1b
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00003800L
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x00FF8000L
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x38000000L
+-//COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xb
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0xf
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1b
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00003800L
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x00FF8000L
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x38000000L
+-//COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xb
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0xf
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1b
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00003800L
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x00FF8000L
+-#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x38000000L
+-//COL_MAN1_PACK_FIFO_ERROR
+-#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_OCCURED__SHIFT 0x0
+-#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_ACK__SHIFT 0x1
+-#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_OCCURED__SHIFT 0x8
+-#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_ACK__SHIFT 0x9
+-#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_OCCURED__SHIFT 0x10
+-#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_ACK__SHIFT 0x11
+-#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_OCCURED__SHIFT 0x18
+-#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_ACK__SHIFT 0x19
+-#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_OCCURED_MASK 0x00000001L
+-#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_ACK_MASK 0x00000002L
+-#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_OCCURED_MASK 0x00000100L
+-#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_ACK_MASK 0x00000200L
+-#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_OCCURED_MASK 0x00010000L
+-#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_ACK_MASK 0x00020000L
+-#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_OCCURED_MASK 0x01000000L
+-#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_ACK_MASK 0x02000000L
+-//COL_MAN1_OUTPUT_FIFO_ERROR
+-#define COL_MAN1_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_OCCURED__SHIFT 0x0
+-#define COL_MAN1_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_ACK__SHIFT 0x1
+-#define COL_MAN1_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_OCCURED__SHIFT 0x8
+-#define COL_MAN1_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_ACK__SHIFT 0x9
+-#define COL_MAN1_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_OCCURED_MASK 0x00000001L
+-#define COL_MAN1_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_ACK_MASK 0x00000002L
+-#define COL_MAN1_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_OCCURED_MASK 0x00000100L
+-#define COL_MAN1_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_ACK_MASK 0x00000200L
+-//COL_MAN1_INPUT_GAMMA_LUT_AUTOFILL
+-#define COL_MAN1_INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL__SHIFT 0x0
+-#define COL_MAN1_INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL_DONE__SHIFT 0x1
+-#define COL_MAN1_INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL_MASK 0x00000001L
+-#define COL_MAN1_INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL_DONE_MASK 0x00000002L
+-//COL_MAN1_INPUT_GAMMA_LUT_RW_INDEX
+-#define COL_MAN1_INPUT_GAMMA_LUT_RW_INDEX__INPUT_GAMMA_LUT_RW_INDEX__SHIFT 0x0
+-#define COL_MAN1_INPUT_GAMMA_LUT_RW_INDEX__INPUT_GAMMA_LUT_RW_INDEX_MASK 0x000000FFL
+-//COL_MAN1_INPUT_GAMMA_LUT_SEQ_COLOR
+-#define COL_MAN1_INPUT_GAMMA_LUT_SEQ_COLOR__INPUT_GAMMA_LUT_SEQ_COLOR__SHIFT 0x0
+-#define COL_MAN1_INPUT_GAMMA_LUT_SEQ_COLOR__INPUT_GAMMA_LUT_SEQ_COLOR_MASK 0x0000FFFFL
+-//COL_MAN1_INPUT_GAMMA_LUT_PWL_DATA
+-#define COL_MAN1_INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_BASE__SHIFT 0x0
+-#define COL_MAN1_INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_DELTA__SHIFT 0x10
+-#define COL_MAN1_INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_BASE_MASK 0x0000FFFFL
+-#define COL_MAN1_INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_DELTA_MASK 0xFFFF0000L
+-//COL_MAN1_INPUT_GAMMA_LUT_30_COLOR
+-#define COL_MAN1_INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_BLUE__SHIFT 0x0
+-#define COL_MAN1_INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_GREEN__SHIFT 0xa
+-#define COL_MAN1_INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_RED__SHIFT 0x14
+-#define COL_MAN1_INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_BLUE_MASK 0x000003FFL
+-#define COL_MAN1_INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_GREEN_MASK 0x000FFC00L
+-#define COL_MAN1_INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_RED_MASK 0x3FF00000L
+-//COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1
+-#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_MODE__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_LUT_10BIT_BYPASS_EN__SHIFT 0x1a
+-#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_MODE_MASK 0x00000003L
+-#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_LUT_10BIT_BYPASS_EN_MASK 0x04000000L
+-//COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2
+-#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_B__SHIFT 0x1
+-#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_SIGNED_EN__SHIFT 0x5
+-#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_FORMAT__SHIFT 0x6
+-#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_G__SHIFT 0x8
+-#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_SIGNED_EN__SHIFT 0xc
+-#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_FORMAT__SHIFT 0xd
+-#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_R__SHIFT 0xf
+-#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_SIGNED_EN__SHIFT 0x13
+-#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_FORMAT__SHIFT 0x14
+-#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_RW_MODE__SHIFT 0x16
+-#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_WRITE_EN_MASK__SHIFT 0x17
+-#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_VGA_ACCESS_ENABLE__SHIFT 0x1a
+-#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x1b
+-#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_B_MASK 0x0000001EL
+-#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_SIGNED_EN_MASK 0x00000020L
+-#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_FORMAT_MASK 0x000000C0L
+-#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_G_MASK 0x00000F00L
+-#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_SIGNED_EN_MASK 0x00001000L
+-#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_FORMAT_MASK 0x00006000L
+-#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_R_MASK 0x00078000L
+-#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_SIGNED_EN_MASK 0x00080000L
+-#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_FORMAT_MASK 0x00300000L
+-#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_RW_MODE_MASK 0x00400000L
+-#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_WRITE_EN_MASK_MASK 0x03800000L
+-#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_VGA_ACCESS_ENABLE_MASK 0x04000000L
+-#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x08000000L
+-//COL_MAN1_INPUT_GAMMA_BW_OFFSETS_B
+-#define COL_MAN1_INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_BLACK_OFFSET_B__SHIFT 0x0
+-#define COL_MAN1_INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_WHITE_OFFSET_B__SHIFT 0x10
+-#define COL_MAN1_INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_BLACK_OFFSET_B_MASK 0x0000FFFFL
+-#define COL_MAN1_INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_WHITE_OFFSET_B_MASK 0xFFFF0000L
+-//COL_MAN1_INPUT_GAMMA_BW_OFFSETS_G
+-#define COL_MAN1_INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_BLACK_OFFSET_G__SHIFT 0x0
+-#define COL_MAN1_INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_WHITE_OFFSET_G__SHIFT 0x10
+-#define COL_MAN1_INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_BLACK_OFFSET_G_MASK 0x0000FFFFL
+-#define COL_MAN1_INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_WHITE_OFFSET_G_MASK 0xFFFF0000L
+-//COL_MAN1_INPUT_GAMMA_BW_OFFSETS_R
+-#define COL_MAN1_INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_BLACK_OFFSET_R__SHIFT 0x0
+-#define COL_MAN1_INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_WHITE_OFFSET_R__SHIFT 0x10
+-#define COL_MAN1_INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_BLACK_OFFSET_R_MASK 0x0000FFFFL
+-#define COL_MAN1_INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_WHITE_OFFSET_R_MASK 0xFFFF0000L
+-//COL_MAN1_COL_MAN_DEGAMMA_CONTROL
+-#define COL_MAN1_COL_MAN_DEGAMMA_CONTROL__COL_MAN_DEGAMMA_MODE__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_DEGAMMA_CONTROL__COL_MAN_DEGAMMA_MODE_MASK 0x00000003L
+-//COL_MAN1_COL_MAN_GAMUT_REMAP_CONTROL
+-#define COL_MAN1_COL_MAN_GAMUT_REMAP_CONTROL__COL_MAN_GAMUT_REMAP_MODE__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_GAMUT_REMAP_CONTROL__COL_MAN_GAMUT_REMAP_MODE_MASK 0x00000003L
+-//COL_MAN1_COL_MAN_GAMUT_REMAP_C11_C12
+-#define COL_MAN1_COL_MAN_GAMUT_REMAP_C11_C12__COL_MAN_GAMUT_REMAP_C11__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_GAMUT_REMAP_C11_C12__COL_MAN_GAMUT_REMAP_C12__SHIFT 0x10
+-#define COL_MAN1_COL_MAN_GAMUT_REMAP_C11_C12__COL_MAN_GAMUT_REMAP_C11_MASK 0x0000FFFFL
+-#define COL_MAN1_COL_MAN_GAMUT_REMAP_C11_C12__COL_MAN_GAMUT_REMAP_C12_MASK 0xFFFF0000L
+-//COL_MAN1_COL_MAN_GAMUT_REMAP_C13_C14
+-#define COL_MAN1_COL_MAN_GAMUT_REMAP_C13_C14__COL_MAN_GAMUT_REMAP_C13__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_GAMUT_REMAP_C13_C14__COL_MAN_GAMUT_REMAP_C14__SHIFT 0x10
+-#define COL_MAN1_COL_MAN_GAMUT_REMAP_C13_C14__COL_MAN_GAMUT_REMAP_C13_MASK 0x0000FFFFL
+-#define COL_MAN1_COL_MAN_GAMUT_REMAP_C13_C14__COL_MAN_GAMUT_REMAP_C14_MASK 0xFFFF0000L
+-//COL_MAN1_COL_MAN_GAMUT_REMAP_C21_C22
+-#define COL_MAN1_COL_MAN_GAMUT_REMAP_C21_C22__COL_MAN_GAMUT_REMAP_C21__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_GAMUT_REMAP_C21_C22__COL_MAN_GAMUT_REMAP_C22__SHIFT 0x10
+-#define COL_MAN1_COL_MAN_GAMUT_REMAP_C21_C22__COL_MAN_GAMUT_REMAP_C21_MASK 0x0000FFFFL
+-#define COL_MAN1_COL_MAN_GAMUT_REMAP_C21_C22__COL_MAN_GAMUT_REMAP_C22_MASK 0xFFFF0000L
+-//COL_MAN1_COL_MAN_GAMUT_REMAP_C23_C24
+-#define COL_MAN1_COL_MAN_GAMUT_REMAP_C23_C24__COL_MAN_GAMUT_REMAP_C23__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_GAMUT_REMAP_C23_C24__COL_MAN_GAMUT_REMAP_C24__SHIFT 0x10
+-#define COL_MAN1_COL_MAN_GAMUT_REMAP_C23_C24__COL_MAN_GAMUT_REMAP_C23_MASK 0x0000FFFFL
+-#define COL_MAN1_COL_MAN_GAMUT_REMAP_C23_C24__COL_MAN_GAMUT_REMAP_C24_MASK 0xFFFF0000L
+-//COL_MAN1_COL_MAN_GAMUT_REMAP_C31_C32
+-#define COL_MAN1_COL_MAN_GAMUT_REMAP_C31_C32__COL_MAN_GAMUT_REMAP_C31__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_GAMUT_REMAP_C31_C32__COL_MAN_GAMUT_REMAP_C32__SHIFT 0x10
+-#define COL_MAN1_COL_MAN_GAMUT_REMAP_C31_C32__COL_MAN_GAMUT_REMAP_C31_MASK 0x0000FFFFL
+-#define COL_MAN1_COL_MAN_GAMUT_REMAP_C31_C32__COL_MAN_GAMUT_REMAP_C32_MASK 0xFFFF0000L
+-//COL_MAN1_COL_MAN_GAMUT_REMAP_C33_C34
+-#define COL_MAN1_COL_MAN_GAMUT_REMAP_C33_C34__COL_MAN_GAMUT_REMAP_C33__SHIFT 0x0
+-#define COL_MAN1_COL_MAN_GAMUT_REMAP_C33_C34__COL_MAN_GAMUT_REMAP_C34__SHIFT 0x10
+-#define COL_MAN1_COL_MAN_GAMUT_REMAP_C33_C34__COL_MAN_GAMUT_REMAP_C33_MASK 0x0000FFFFL
+-#define COL_MAN1_COL_MAN_GAMUT_REMAP_C33_C34__COL_MAN_GAMUT_REMAP_C34_MASK 0xFFFF0000L
+-
+-
+-// addressBlock: dce_dc_dcfev1_dispdec
+-//DCFEV1_DCFEV_CLOCK_CONTROL
+-#define DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_R_DCFEV_GATE_DISABLE__SHIFT 0x3
+-#define DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_G_UNP_GATE_DISABLE__SHIFT 0x7
+-#define DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_G_SCLV_GATE_DISABLE__SHIFT 0x9
+-#define DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_G_COL_MAN_GATE_DISABLE__SHIFT 0xb
+-#define DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_G_PSCLV_GATE_DISABLE__SHIFT 0xd
+-#define DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_G_CRTC_GATE_DISABLE__SHIFT 0xf
+-#define DCFEV1_DCFEV_CLOCK_CONTROL__DCFEV_TEST_CLK_SEL__SHIFT 0x18
+-#define DCFEV1_DCFEV_CLOCK_CONTROL__DCFEV_CLOCK_ENABLE__SHIFT 0x1f
+-#define DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_R_DCFEV_GATE_DISABLE_MASK 0x00000008L
+-#define DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_G_UNP_GATE_DISABLE_MASK 0x00000080L
+-#define DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_G_SCLV_GATE_DISABLE_MASK 0x00000200L
+-#define DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_G_COL_MAN_GATE_DISABLE_MASK 0x00000800L
+-#define DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_G_PSCLV_GATE_DISABLE_MASK 0x00002000L
+-#define DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_G_CRTC_GATE_DISABLE_MASK 0x00008000L
+-#define DCFEV1_DCFEV_CLOCK_CONTROL__DCFEV_TEST_CLK_SEL_MASK 0x1F000000L
+-#define DCFEV1_DCFEV_CLOCK_CONTROL__DCFEV_CLOCK_ENABLE_MASK 0x80000000L
+-//DCFEV1_DCFEV_SOFT_RESET
+-#define DCFEV1_DCFEV_SOFT_RESET__UNP_PIXPIPE_SOFT_RESET__SHIFT 0x0
+-#define DCFEV1_DCFEV_SOFT_RESET__UNP_REQ_SOFT_RESET__SHIFT 0x1
+-#define DCFEV1_DCFEV_SOFT_RESET__SCLV_ALU_SOFT_RESET__SHIFT 0x2
+-#define DCFEV1_DCFEV_SOFT_RESET__SCLV_SOFT_RESET__SHIFT 0x3
+-#define DCFEV1_DCFEV_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4
+-#define DCFEV1_DCFEV_SOFT_RESET__PSCLV_SOFT_RESET__SHIFT 0x5
+-#define DCFEV1_DCFEV_SOFT_RESET__COL_MAN_SOFT_RESET__SHIFT 0x6
+-#define DCFEV1_DCFEV_SOFT_RESET__UNP_PIXPIPE_SOFT_RESET_MASK 0x00000001L
+-#define DCFEV1_DCFEV_SOFT_RESET__UNP_REQ_SOFT_RESET_MASK 0x00000002L
+-#define DCFEV1_DCFEV_SOFT_RESET__SCLV_ALU_SOFT_RESET_MASK 0x00000004L
+-#define DCFEV1_DCFEV_SOFT_RESET__SCLV_SOFT_RESET_MASK 0x00000008L
+-#define DCFEV1_DCFEV_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x00000010L
+-#define DCFEV1_DCFEV_SOFT_RESET__PSCLV_SOFT_RESET_MASK 0x00000020L
+-#define DCFEV1_DCFEV_SOFT_RESET__COL_MAN_SOFT_RESET_MASK 0x00000040L
+-//DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL
+-#define DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x3
+-#define DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVL_GATE_DIS__SHIFT 0x4
+-#define DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVC_GATE_DIS__SHIFT 0x5
+-#define DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SOFT_RESET__SHIFT 0x6
+-#define DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_TEST_CLK_SEL__SHIFT 0x18
+-#define DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_BUFFER_MODE__SHIFT 0x1f
+-#define DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SCLK_G_DMIFTRK_GATE_DIS_MASK 0x00000008L
+-#define DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVL_GATE_DIS_MASK 0x00000010L
+-#define DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVC_GATE_DIS_MASK 0x00000020L
+-#define DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SOFT_RESET_MASK 0x00000040L
+-#define DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_TEST_CLK_SEL_MASK 0x1F000000L
+-#define DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_BUFFER_MODE_MASK 0x80000000L
+-//DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_SEL__SHIFT 0x0
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_0_FORCE__SHIFT 0x2
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_1_FORCE__SHIFT 0x3
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_2_FORCE__SHIFT 0x4
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_3_FORCE__SHIFT 0x5
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_4_FORCE__SHIFT 0x6
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_0_FORCE__SHIFT 0x7
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_1_FORCE__SHIFT 0x8
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_2_FORCE__SHIFT 0x9
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_3_FORCE__SHIFT 0xa
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_4_FORCE__SHIFT 0xb
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_SEL_MASK 0x00000003L
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_0_FORCE_MASK 0x00000004L
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_1_FORCE_MASK 0x00000008L
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_2_FORCE_MASK 0x00000010L
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_3_FORCE_MASK 0x00000020L
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_4_FORCE_MASK 0x00000040L
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_0_FORCE_MASK 0x00000080L
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_1_FORCE_MASK 0x00000100L
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_2_FORCE_MASK 0x00000200L
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_3_FORCE_MASK 0x00000400L
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_4_FORCE_MASK 0x00000800L
+-//DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_0_STATE__SHIFT 0x0
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_1_STATE__SHIFT 0x2
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_2_STATE__SHIFT 0x4
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_3_STATE__SHIFT 0x6
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_4_STATE__SHIFT 0x8
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_0_STATE__SHIFT 0xa
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_1_STATE__SHIFT 0xc
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_2_STATE__SHIFT 0xe
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_3_STATE__SHIFT 0x10
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_4_STATE__SHIFT 0x12
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_0_STATE_MASK 0x00000003L
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_1_STATE_MASK 0x0000000CL
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_2_STATE_MASK 0x00000030L
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_3_STATE_MASK 0x000000C0L
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_4_STATE_MASK 0x00000300L
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_0_STATE_MASK 0x00000C00L
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_1_STATE_MASK 0x00003000L
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_2_STATE_MASK 0x0000C000L
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_3_STATE_MASK 0x00030000L
+-#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_4_STATE_MASK 0x000C0000L
+-//DCFEV1_DCFEV_MEM_PWR_CTRL
+-#define DCFEV1_DCFEV_MEM_PWR_CTRL__COL_MAN_REGAMMA_MEM_PWR_FORCE__SHIFT 0x0
+-#define DCFEV1_DCFEV_MEM_PWR_CTRL__COL_MAN_REGAMMA_MEM_PWR_DIS__SHIFT 0x2
+-#define DCFEV1_DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_FORCE__SHIFT 0x3
+-#define DCFEV1_DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_DIS__SHIFT 0x5
+-#define DCFEV1_DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_FORCE__SHIFT 0x6
+-#define DCFEV1_DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_DIS__SHIFT 0x8
+-#define DCFEV1_DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_FORCE__SHIFT 0x9
+-#define DCFEV1_DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_DIS__SHIFT 0xb
+-#define DCFEV1_DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_FORCE__SHIFT 0xc
+-#define DCFEV1_DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_DIS__SHIFT 0xe
+-#define DCFEV1_DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_FORCE__SHIFT 0xf
+-#define DCFEV1_DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_DIS__SHIFT 0x11
+-#define DCFEV1_DCFEV_MEM_PWR_CTRL__COL_MAN_REGAMMA_MEM_PWR_FORCE_MASK 0x00000003L
+-#define DCFEV1_DCFEV_MEM_PWR_CTRL__COL_MAN_REGAMMA_MEM_PWR_DIS_MASK 0x00000004L
+-#define DCFEV1_DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_FORCE_MASK 0x00000018L
+-#define DCFEV1_DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_DIS_MASK 0x00000020L
+-#define DCFEV1_DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_FORCE_MASK 0x000000C0L
+-#define DCFEV1_DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_DIS_MASK 0x00000100L
+-#define DCFEV1_DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_FORCE_MASK 0x00000600L
+-#define DCFEV1_DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_DIS_MASK 0x00000800L
+-#define DCFEV1_DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_FORCE_MASK 0x00003000L
+-#define DCFEV1_DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_DIS_MASK 0x00004000L
+-#define DCFEV1_DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_FORCE_MASK 0x00018000L
+-#define DCFEV1_DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_DIS_MASK 0x00020000L
+-//DCFEV1_DCFEV_MEM_PWR_CTRL2
+-#define DCFEV1_DCFEV_MEM_PWR_CTRL2__COL_MAN_REGAMMA_MEM_PWR_MODE_SEL__SHIFT 0x0
+-#define DCFEV1_DCFEV_MEM_PWR_CTRL2__COL_MAN_INPUT_GAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2
+-#define DCFEV1_DCFEV_MEM_PWR_CTRL2__SCLV_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4
+-#define DCFEV1_DCFEV_MEM_PWR_CTRL2__LBV_MEM_PWR_MODE_SEL__SHIFT 0x6
+-#define DCFEV1_DCFEV_MEM_PWR_CTRL2__COL_MAN_REGAMMA_MEM_PWR_MODE_SEL_MASK 0x00000003L
+-#define DCFEV1_DCFEV_MEM_PWR_CTRL2__COL_MAN_INPUT_GAMMA_MEM_PWR_MODE_SEL_MASK 0x0000000CL
+-#define DCFEV1_DCFEV_MEM_PWR_CTRL2__SCLV_COEFF_MEM_PWR_MODE_SEL_MASK 0x00000030L
+-#define DCFEV1_DCFEV_MEM_PWR_CTRL2__LBV_MEM_PWR_MODE_SEL_MASK 0x000000C0L
+-//DCFEV1_DCFEV_MEM_PWR_STATUS
+-#define DCFEV1_DCFEV_MEM_PWR_STATUS__COL_MAN_REGAMMA_MEM_PWR_STATE__SHIFT 0x0
+-#define DCFEV1_DCFEV_MEM_PWR_STATUS__COL_MAN_INPUT_GAMMA_MEM_PWR_STATE__SHIFT 0x2
+-#define DCFEV1_DCFEV_MEM_PWR_STATUS__SCLV_COEFF_MEM_PWR_STATE__SHIFT 0x4
+-#define DCFEV1_DCFEV_MEM_PWR_STATUS__LBV0_MEM_PWR_STATE__SHIFT 0x6
+-#define DCFEV1_DCFEV_MEM_PWR_STATUS__LBV1_MEM_PWR_STATE__SHIFT 0x8
+-#define DCFEV1_DCFEV_MEM_PWR_STATUS__LBV2_MEM_PWR_STATE__SHIFT 0xa
+-#define DCFEV1_DCFEV_MEM_PWR_STATUS__LBV3_MEM_PWR_STATE__SHIFT 0xc
+-#define DCFEV1_DCFEV_MEM_PWR_STATUS__COL_MAN_REGAMMA_MEM_PWR_STATE_MASK 0x00000003L
+-#define DCFEV1_DCFEV_MEM_PWR_STATUS__COL_MAN_INPUT_GAMMA_MEM_PWR_STATE_MASK 0x0000000CL
+-#define DCFEV1_DCFEV_MEM_PWR_STATUS__SCLV_COEFF_MEM_PWR_STATE_MASK 0x00000030L
+-#define DCFEV1_DCFEV_MEM_PWR_STATUS__LBV0_MEM_PWR_STATE_MASK 0x000000C0L
+-#define DCFEV1_DCFEV_MEM_PWR_STATUS__LBV1_MEM_PWR_STATE_MASK 0x00000300L
+-#define DCFEV1_DCFEV_MEM_PWR_STATUS__LBV2_MEM_PWR_STATE_MASK 0x00000C00L
+-#define DCFEV1_DCFEV_MEM_PWR_STATUS__LBV3_MEM_PWR_STATE_MASK 0x00003000L
+-//DCFEV1_DCFEV_L_FLUSH
+-#define DCFEV1_DCFEV_L_FLUSH__FLUSH_OCCURED__SHIFT 0x0
+-#define DCFEV1_DCFEV_L_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT 0x1
+-#define DCFEV1_DCFEV_L_FLUSH__FLUSH_DEEP__SHIFT 0x2
+-#define DCFEV1_DCFEV_L_FLUSH__CLEAR_FLUSH_DEEP__SHIFT 0x3
+-#define DCFEV1_DCFEV_L_FLUSH__ALL_MC_REQ_RET__SHIFT 0x4
+-#define DCFEV1_DCFEV_L_FLUSH__FLUSH_OCCURED_MASK 0x00000001L
+-#define DCFEV1_DCFEV_L_FLUSH__CLEAR_FLUSH_OCCURED_MASK 0x00000002L
+-#define DCFEV1_DCFEV_L_FLUSH__FLUSH_DEEP_MASK 0x00000004L
+-#define DCFEV1_DCFEV_L_FLUSH__CLEAR_FLUSH_DEEP_MASK 0x00000008L
+-#define DCFEV1_DCFEV_L_FLUSH__ALL_MC_REQ_RET_MASK 0x00000010L
+-//DCFEV1_DCFEV_C_FLUSH
+-#define DCFEV1_DCFEV_C_FLUSH__FLUSH_OCCURED__SHIFT 0x0
+-#define DCFEV1_DCFEV_C_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT 0x1
+-#define DCFEV1_DCFEV_C_FLUSH__FLUSH_DEEP__SHIFT 0x2
+-#define DCFEV1_DCFEV_C_FLUSH__CLEAR_FLUSH_DEEP__SHIFT 0x3
+-#define DCFEV1_DCFEV_C_FLUSH__ALL_MC_REQ_RET__SHIFT 0x4
+-#define DCFEV1_DCFEV_C_FLUSH__FLUSH_OCCURED_MASK 0x00000001L
+-#define DCFEV1_DCFEV_C_FLUSH__CLEAR_FLUSH_OCCURED_MASK 0x00000002L
+-#define DCFEV1_DCFEV_C_FLUSH__FLUSH_DEEP_MASK 0x00000004L
+-#define DCFEV1_DCFEV_C_FLUSH__CLEAR_FLUSH_DEEP_MASK 0x00000008L
+-#define DCFEV1_DCFEV_C_FLUSH__ALL_MC_REQ_RET_MASK 0x00000010L
+-//DCFEV1_DCFEV_MISC
+-#define DCFEV1_DCFEV_MISC__DCFEV_DPG_ALLOW_SR_ECO_EN__SHIFT 0x0
+-#define DCFEV1_DCFEV_MISC__DCFEV_DPG_ALLOW_SR_ECO_EN_MASK 0x00000001L
+-
+-
+-// addressBlock: dce_dc_dc_perfmon12_dispdec
+-//DC_PERFMON12_PERFCOUNTER_CNTL
+-#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+-#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+-#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+-#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+-#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+-#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
+-#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+-#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+-#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+-#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+-#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+-#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
+-#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+-#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+-#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+-#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+-#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+-#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+-#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
+-#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+-#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+-#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+-#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+-#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+-#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
+-#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+-//DC_PERFMON12_PERFCOUNTER_CNTL2
+-#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+-#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+-#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+-#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+-#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+-#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+-#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+-#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+-//DC_PERFMON12_PERFCOUNTER_STATE
+-#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+-#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+-#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+-#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+-#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+-#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+-#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+-#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+-#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+-#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+-#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+-#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+-#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+-#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+-#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+-#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+-#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+-#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+-#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+-#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+-#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+-#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+-#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+-#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+-#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+-#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+-#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+-#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+-#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+-#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+-#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+-#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+-//DC_PERFMON12_PERFMON_CNTL
+-#define DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+-#define DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+-#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+-#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+-#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+-#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+-#define DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+-#define DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+-#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+-#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+-#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+-#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+-//DC_PERFMON12_PERFMON_CNTL2
+-#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+-#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+-#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+-#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+-#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+-#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+-#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+-#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+-//DC_PERFMON12_PERFMON_CVALUE_INT_MISC
+-#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+-#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+-#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+-#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+-#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+-#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+-#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+-#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+-#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+-#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+-#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+-#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+-#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+-#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+-#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+-#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+-#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+-#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+-#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+-#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+-#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+-#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+-#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+-#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+-#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+-#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+-#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+-#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+-#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+-#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+-#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+-#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+-#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+-#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+-//DC_PERFMON12_PERFMON_CVALUE_LOW
+-#define DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+-#define DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+-//DC_PERFMON12_PERFMON_HI
+-#define DC_PERFMON12_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+-#define DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+-#define DC_PERFMON12_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+-#define DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+-//DC_PERFMON12_PERFMON_LOW
+-#define DC_PERFMON12_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+-#define DC_PERFMON12_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dmifv_pg1_dispdec
+-//DMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1
+-#define DMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
+-#define DMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
+-#define DMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0x0000FFFFL
+-#define DMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xFFFF0000L
+-//DMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2
+-#define DMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
+-#define DMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
+-#define DMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0x0000FFFFL
+-#define DMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xFFFF0000L
+-//DMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL
+-#define DMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
+-#define DMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
+-#define DMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x10
+-#define DMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x18
+-#define DMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000003L
+-#define DMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x00000300L
+-#define DMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00030000L
+-#define DMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x01000000L
+-//DMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL
+-#define DMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
+-#define DMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
+-#define DMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0x0000FFFFL
+-#define DMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xFFFF0000L
+-//DMIFV_PG1_DPGV0_PIPE_DPM_CONTROL
+-#define DMIFV_PG1_DPGV0_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x0
+-#define DMIFV_PG1_DPGV0_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x00000001L
+-//DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL
+-#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
+-#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
+-#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
+-#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
+-#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
+-#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x8
+-#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x9
+-#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
+-#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
+-#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x10
+-#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L
+-#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L
+-#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x00000020L
+-#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x00000040L
+-#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x00000080L
+-#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x00000100L
+-#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x00000200L
+-#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x00000400L
+-#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x00000800L
+-#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xFFFF0000L
+-//DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL
+-#define DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x0
+-#define DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
+-#define DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
+-#define DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
+-#define DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
+-#define DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x10
+-#define DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x00000001L
+-#define DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L
+-#define DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x00000100L
+-#define DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000200L
+-#define DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000400L
+-#define DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xFFFF0000L
+-//DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH
+-#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x0
+-#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x4
+-#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x5
+-#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x6
+-#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x7
+-#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x8
+-#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x9
+-#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0xa
+-#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0xb
+-#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x00000001L
+-#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x00000010L
+-#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x00000020L
+-#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x00000040L
+-#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x00000080L
+-#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x00000100L
+-#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x00000200L
+-#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x00000400L
+-#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x00000800L
+-//DMIFV_PG1_DPGV0_REPEATER_PROGRAM
+-#define DMIFV_PG1_DPGV0_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
+-#define DMIFV_PG1_DPGV0_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
+-#define DMIFV_PG1_DPGV0_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x00000007L
+-#define DMIFV_PG1_DPGV0_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x00000070L
+-//DMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL
+-#define DMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0
+-#define DMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x00000001L
+-//DMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1
+-#define DMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
+-#define DMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
+-#define DMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0x0000FFFFL
+-#define DMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xFFFF0000L
+-//DMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2
+-#define DMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
+-#define DMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
+-#define DMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0x0000FFFFL
+-#define DMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xFFFF0000L
+-//DMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL
+-#define DMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
+-#define DMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
+-#define DMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x10
+-#define DMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x18
+-#define DMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000003L
+-#define DMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x00000300L
+-#define DMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00030000L
+-#define DMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x01000000L
+-//DMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL
+-#define DMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
+-#define DMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
+-#define DMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0x0000FFFFL
+-#define DMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xFFFF0000L
+-//DMIFV_PG1_DPGV1_PIPE_DPM_CONTROL
+-#define DMIFV_PG1_DPGV1_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x0
+-#define DMIFV_PG1_DPGV1_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x00000001L
+-//DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL
+-#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
+-#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
+-#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
+-#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
+-#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
+-#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x8
+-#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x9
+-#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
+-#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
+-#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x10
+-#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L
+-#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L
+-#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x00000020L
+-#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x00000040L
+-#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x00000080L
+-#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x00000100L
+-#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x00000200L
+-#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x00000400L
+-#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x00000800L
+-#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xFFFF0000L
+-//DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL
+-#define DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x0
+-#define DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
+-#define DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
+-#define DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
+-#define DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
+-#define DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x10
+-#define DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x00000001L
+-#define DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L
+-#define DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x00000100L
+-#define DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000200L
+-#define DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000400L
+-#define DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xFFFF0000L
+-//DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH
+-#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x0
+-#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x4
+-#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x5
+-#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x6
+-#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x7
+-#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x8
+-#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x9
+-#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0xa
+-#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0xb
+-#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x00000001L
+-#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x00000010L
+-#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x00000020L
+-#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x00000040L
+-#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x00000080L
+-#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x00000100L
+-#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x00000200L
+-#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x00000400L
+-#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x00000800L
+-//DMIFV_PG1_DPGV1_REPEATER_PROGRAM
+-#define DMIFV_PG1_DPGV1_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
+-#define DMIFV_PG1_DPGV1_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
+-#define DMIFV_PG1_DPGV1_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x00000007L
+-#define DMIFV_PG1_DPGV1_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x00000070L
+-//DMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL
+-#define DMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0
+-#define DMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x00000001L
+-
+-
+-// addressBlock: dce_dc_blndv1_dispdec
+-//BLNDV1_BLNDV_CONTROL
+-#define BLNDV1_BLNDV_CONTROL__BLND_GLOBAL_GAIN__SHIFT 0x0
+-#define BLNDV1_BLNDV_CONTROL__BLND_MODE__SHIFT 0x8
+-#define BLNDV1_BLNDV_CONTROL__BLND_STEREO_TYPE__SHIFT 0xa
+-#define BLNDV1_BLNDV_CONTROL__BLND_STEREO_POLARITY__SHIFT 0xc
+-#define BLNDV1_BLNDV_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT 0xd
+-#define BLNDV1_BLNDV_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10
+-#define BLNDV1_BLNDV_CONTROL__BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x12
+-#define BLNDV1_BLNDV_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14
+-#define BLNDV1_BLNDV_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18
+-#define BLNDV1_BLNDV_CONTROL__BLND_GLOBAL_GAIN_MASK 0x000000FFL
+-#define BLNDV1_BLNDV_CONTROL__BLND_MODE_MASK 0x00000300L
+-#define BLNDV1_BLNDV_CONTROL__BLND_STEREO_TYPE_MASK 0x00000C00L
+-#define BLNDV1_BLNDV_CONTROL__BLND_STEREO_POLARITY_MASK 0x00001000L
+-#define BLNDV1_BLNDV_CONTROL__BLND_FEEDTHROUGH_EN_MASK 0x00002000L
+-#define BLNDV1_BLNDV_CONTROL__BLND_ALPHA_MODE_MASK 0x00030000L
+-#define BLNDV1_BLNDV_CONTROL__BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00040000L
+-#define BLNDV1_BLNDV_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x00100000L
+-#define BLNDV1_BLNDV_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xFF000000L
+-//BLNDV1_BLNDV_SM_CONTROL2
+-#define BLNDV1_BLNDV_SM_CONTROL2__SM_MODE__SHIFT 0x0
+-#define BLNDV1_BLNDV_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4
+-#define BLNDV1_BLNDV_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5
+-#define BLNDV1_BLNDV_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
+-#define BLNDV1_BLNDV_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
+-#define BLNDV1_BLNDV_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18
+-#define BLNDV1_BLNDV_SM_CONTROL2__SM_MODE_MASK 0x00000007L
+-#define BLNDV1_BLNDV_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x00000010L
+-#define BLNDV1_BLNDV_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x00000020L
+-#define BLNDV1_BLNDV_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L
+-#define BLNDV1_BLNDV_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L
+-#define BLNDV1_BLNDV_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x01000000L
+-//BLNDV1_BLNDV_CONTROL2
+-#define BLNDV1_BLNDV_CONTROL2__PTI_ENABLE__SHIFT 0x0
+-#define BLNDV1_BLNDV_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT 0x4
+-#define BLNDV1_BLNDV_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT 0x6
+-#define BLNDV1_BLNDV_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT 0x7
+-#define BLNDV1_BLNDV_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT 0x8
+-#define BLNDV1_BLNDV_CONTROL2__PTI_ENABLE_MASK 0x00000001L
+-#define BLNDV1_BLNDV_CONTROL2__PTI_NEW_PIXEL_GAP_MASK 0x00000030L
+-#define BLNDV1_BLNDV_CONTROL2__BLND_NEW_PIXEL_MODE_MASK 0x00000040L
+-#define BLNDV1_BLNDV_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK 0x00000080L
+-#define BLNDV1_BLNDV_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK 0x00000100L
+-//BLNDV1_BLNDV_UPDATE
+-#define BLNDV1_BLNDV_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0
+-#define BLNDV1_BLNDV_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8
+-#define BLNDV1_BLNDV_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10
+-#define BLNDV1_BLNDV_UPDATE__BLND_UPDATE_PENDING_MASK 0x00000001L
+-#define BLNDV1_BLNDV_UPDATE__BLND_UPDATE_TAKEN_MASK 0x00000100L
+-#define BLNDV1_BLNDV_UPDATE__BLND_UPDATE_LOCK_MASK 0x00010000L
+-//BLNDV1_BLNDV_UNDERFLOW_INTERRUPT
+-#define BLNDV1_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0
+-#define BLNDV1_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8
+-#define BLNDV1_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc
+-#define BLNDV1_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10
+-#define BLNDV1_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x00000001L
+-#define BLNDV1_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x00000100L
+-#define BLNDV1_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x00001000L
+-#define BLNDV1_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x00030000L
+-//BLNDV1_BLNDV_V_UPDATE_LOCK
+-#define BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0
+-#define BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1
+-#define BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10
+-#define BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c
+-#define BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT 0x1d
+-#define BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT 0x1f
+-#define BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x00000001L
+-#define BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x00000002L
+-#define BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x00010000L
+-#define BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000L
+-#define BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK 0x20000000L
+-#define BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK 0x80000000L
+-//BLNDV1_BLNDV_REG_UPDATE_STATUS
+-#define BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT 0x0
+-#define BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT 0x1
+-#define BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2
+-#define BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3
+-#define BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT 0x6
+-#define BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT 0x7
+-#define BLNDV1_BLNDV_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT 0x8
+-#define BLNDV1_BLNDV_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT 0x9
+-#define BLNDV1_BLNDV_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT 0xa
+-#define BLNDV1_BLNDV_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT 0xb
+-#define BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK 0x00000001L
+-#define BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK 0x00000002L
+-#define BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK 0x00000004L
+-#define BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK 0x00000008L
+-#define BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK 0x00000040L
+-#define BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK 0x00000080L
+-#define BLNDV1_BLNDV_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK 0x00000100L
+-#define BLNDV1_BLNDV_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK 0x00000200L
+-#define BLNDV1_BLNDV_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK 0x00000400L
+-#define BLNDV1_BLNDV_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK 0x00000800L
+-
+-
+-// addressBlock: dce_dc_crtcv1_dispdec
+-//CRTCV1_CRTCV_H_BLANK_EARLY_NUM
+-#define CRTCV1_CRTCV_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0
+-#define CRTCV1_CRTCV_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10
+-#define CRTCV1_CRTCV_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x000003FFL
+-#define CRTCV1_CRTCV_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x00010000L
+-//CRTCV1_CRTCV_H_TOTAL
+-#define CRTCV1_CRTCV_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0
+-#define CRTCV1_CRTCV_H_TOTAL__CRTC_H_TOTAL_MASK 0x00003FFFL
+-//CRTCV1_CRTCV_H_BLANK_START_END
+-#define CRTCV1_CRTCV_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0
+-#define CRTCV1_CRTCV_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10
+-#define CRTCV1_CRTCV_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x00003FFFL
+-#define CRTCV1_CRTCV_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3FFF0000L
+-//CRTCV1_CRTCV_H_SYNC_A
+-#define CRTCV1_CRTCV_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0
+-#define CRTCV1_CRTCV_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10
+-#define CRTCV1_CRTCV_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x00003FFFL
+-#define CRTCV1_CRTCV_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3FFF0000L
+-//CRTCV1_CRTCV_H_SYNC_A_CNTL
+-#define CRTCV1_CRTCV_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0
+-#define CRTCV1_CRTCV_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10
+-#define CRTCV1_CRTCV_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11
+-#define CRTCV1_CRTCV_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x00000001L
+-#define CRTCV1_CRTCV_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x00010000L
+-#define CRTCV1_CRTCV_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x00020000L
+-//CRTCV1_CRTCV_H_SYNC_B
+-#define CRTCV1_CRTCV_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0
+-#define CRTCV1_CRTCV_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10
+-#define CRTCV1_CRTCV_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x00003FFFL
+-#define CRTCV1_CRTCV_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x3FFF0000L
+-//CRTCV1_CRTCV_H_SYNC_B_CNTL
+-#define CRTCV1_CRTCV_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0
+-#define CRTCV1_CRTCV_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10
+-#define CRTCV1_CRTCV_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11
+-#define CRTCV1_CRTCV_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x00000001L
+-#define CRTCV1_CRTCV_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x00010000L
+-#define CRTCV1_CRTCV_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x00020000L
+-//CRTCV1_CRTCV_VBI_END
+-#define CRTCV1_CRTCV_VBI_END__CRTC_VBI_V_END__SHIFT 0x0
+-#define CRTCV1_CRTCV_VBI_END__CRTC_VBI_H_END__SHIFT 0x10
+-#define CRTCV1_CRTCV_VBI_END__CRTC_VBI_V_END_MASK 0x00003FFFL
+-#define CRTCV1_CRTCV_VBI_END__CRTC_VBI_H_END_MASK 0x3FFF0000L
+-//CRTCV1_CRTCV_V_TOTAL
+-#define CRTCV1_CRTCV_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0
+-#define CRTCV1_CRTCV_V_TOTAL__CRTC_V_TOTAL_MASK 0x00003FFFL
+-//CRTCV1_CRTCV_V_TOTAL_MIN
+-#define CRTCV1_CRTCV_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0
+-#define CRTCV1_CRTCV_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x00003FFFL
+-//CRTCV1_CRTCV_V_TOTAL_MAX
+-#define CRTCV1_CRTCV_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0
+-#define CRTCV1_CRTCV_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10
+-#define CRTCV1_CRTCV_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x00003FFFL
+-#define CRTCV1_CRTCV_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x00010000L
+-//CRTCV1_CRTCV_V_TOTAL_CONTROL
+-#define CRTCV1_CRTCV_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0
+-#define CRTCV1_CRTCV_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4
+-#define CRTCV1_CRTCV_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8
+-#define CRTCV1_CRTCV_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc
+-#define CRTCV1_CRTCV_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf
+-#define CRTCV1_CRTCV_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10
+-#define CRTCV1_CRTCV_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x00000001L
+-#define CRTCV1_CRTCV_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x00000010L
+-#define CRTCV1_CRTCV_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x00000100L
+-#define CRTCV1_CRTCV_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x00001000L
+-#define CRTCV1_CRTCV_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00008000L
+-#define CRTCV1_CRTCV_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L
+-//CRTCV1_CRTCV_V_TOTAL_INT_STATUS
+-#define CRTCV1_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0
+-#define CRTCV1_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4
+-#define CRTCV1_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8
+-#define CRTCV1_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc
+-#define CRTCV1_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L
+-#define CRTCV1_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L
+-#define CRTCV1_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L
+-#define CRTCV1_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L
+-//CRTCV1_CRTCV_VSYNC_NOM_INT_STATUS
+-#define CRTCV1_CRTCV_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0
+-#define CRTCV1_CRTCV_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4
+-#define CRTCV1_CRTCV_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x00000001L
+-#define CRTCV1_CRTCV_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L
+-//CRTCV1_CRTCV_V_BLANK_START_END
+-#define CRTCV1_CRTCV_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0
+-#define CRTCV1_CRTCV_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10
+-#define CRTCV1_CRTCV_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x00003FFFL
+-#define CRTCV1_CRTCV_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3FFF0000L
+-//CRTCV1_CRTCV_V_SYNC_A
+-#define CRTCV1_CRTCV_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0
+-#define CRTCV1_CRTCV_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10
+-#define CRTCV1_CRTCV_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x00003FFFL
+-#define CRTCV1_CRTCV_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3FFF0000L
+-//CRTCV1_CRTCV_V_SYNC_A_CNTL
+-#define CRTCV1_CRTCV_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0
+-#define CRTCV1_CRTCV_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x00000001L
+-//CRTCV1_CRTCV_V_SYNC_B
+-#define CRTCV1_CRTCV_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0
+-#define CRTCV1_CRTCV_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10
+-#define CRTCV1_CRTCV_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x00003FFFL
+-#define CRTCV1_CRTCV_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x3FFF0000L
+-//CRTCV1_CRTCV_V_SYNC_B_CNTL
+-#define CRTCV1_CRTCV_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0
+-#define CRTCV1_CRTCV_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x00000001L
+-//CRTCV1_CRTCV_DTMTEST_CNTL
+-#define CRTCV1_CRTCV_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0
+-#define CRTCV1_CRTCV_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1
+-#define CRTCV1_CRTCV_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x00000001L
+-#define CRTCV1_CRTCV_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x0000001EL
+-//CRTCV1_CRTCV_DTMTEST_STATUS_POSITION
+-#define CRTCV1_CRTCV_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0
+-#define CRTCV1_CRTCV_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10
+-#define CRTCV1_CRTCV_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x00003FFFL
+-#define CRTCV1_CRTCV_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x3FFF0000L
+-//CRTCV1_CRTCV_TRIGA_CNTL
+-#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0
+-#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5
+-#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8
+-#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9
+-#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa
+-#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb
+-#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
+-#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
+-#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14
+-#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18
+-#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f
+-#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x0000001FL
+-#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0x000000E0L
+-#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000100L
+-#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x00000200L
+-#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x00000400L
+-#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x00000800L
+-#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
+-#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
+-#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L
+-#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1F000000L
+-#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000L
+-//CRTCV1_CRTCV_TRIGA_MANUAL_TRIG
+-#define CRTCV1_CRTCV_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0
+-#define CRTCV1_CRTCV_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x00000001L
+-//CRTCV1_CRTCV_TRIGB_CNTL
+-#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0
+-#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5
+-#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8
+-#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9
+-#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa
+-#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb
+-#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
+-#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
+-#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14
+-#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18
+-#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f
+-#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x0000001FL
+-#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0x000000E0L
+-#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000100L
+-#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x00000200L
+-#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x00000400L
+-#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x00000800L
+-#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
+-#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
+-#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L
+-#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1F000000L
+-#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000L
+-//CRTCV1_CRTCV_TRIGB_MANUAL_TRIG
+-#define CRTCV1_CRTCV_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0
+-#define CRTCV1_CRTCV_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x00000001L
+-//CRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL
+-#define CRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0
+-#define CRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4
+-#define CRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8
+-#define CRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10
+-#define CRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18
+-#define CRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x00000003L
+-#define CRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L
+-#define CRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L
+-#define CRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L
+-#define CRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L
+-//CRTCV1_CRTCV_FLOW_CONTROL
+-#define CRTCV1_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0
+-#define CRTCV1_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8
+-#define CRTCV1_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10
+-#define CRTCV1_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18
+-#define CRTCV1_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL
+-#define CRTCV1_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x00000100L
+-#define CRTCV1_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L
+-#define CRTCV1_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L
+-//CRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE
+-#define CRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0
+-#define CRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER__SHIFT 0x8
+-#define CRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER__SHIFT 0x10
+-#define CRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L
+-#define CRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L
+-#define CRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L
+-//CRTCV1_CRTCV_AVSYNC_COUNTER
+-#define CRTCV1_CRTCV_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER__SHIFT 0x0
+-#define CRTCV1_CRTCV_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER_MASK 0xFFFFFFFFL
+-//CRTCV1_CRTCV_CONTROL
+-#define CRTCV1_CRTCV_CONTROL__CRTC_MASTER_EN__SHIFT 0x0
+-#define CRTCV1_CRTCV_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4
+-#define CRTCV1_CRTCV_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8
+-#define CRTCV1_CRTCV_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc
+-#define CRTCV1_CRTCV_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd
+-#define CRTCV1_CRTCV_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe
+-#define CRTCV1_CRTCV_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10
+-#define CRTCV1_CRTCV_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14
+-#define CRTCV1_CRTCV_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d
+-#define CRTCV1_CRTCV_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e
+-#define CRTCV1_CRTCV_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f
+-#define CRTCV1_CRTCV_CONTROL__CRTC_MASTER_EN_MASK 0x00000001L
+-#define CRTCV1_CRTCV_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x00000010L
+-#define CRTCV1_CRTCV_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x00000300L
+-#define CRTCV1_CRTCV_CONTROL__CRTC_START_POINT_CNTL_MASK 0x00001000L
+-#define CRTCV1_CRTCV_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x00002000L
+-#define CRTCV1_CRTCV_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x00004000L
+-#define CRTCV1_CRTCV_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x00010000L
+-#define CRTCV1_CRTCV_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x00700000L
+-#define CRTCV1_CRTCV_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000L
+-#define CRTCV1_CRTCV_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L
+-#define CRTCV1_CRTCV_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L
+-//CRTCV1_CRTCV_BLANK_CONTROL
+-#define CRTCV1_CRTCV_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0
+-#define CRTCV1_CRTCV_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8
+-#define CRTCV1_CRTCV_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10
+-#define CRTCV1_CRTCV_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x00000001L
+-#define CRTCV1_CRTCV_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x00000100L
+-#define CRTCV1_CRTCV_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x00010000L
+-//CRTCV1_CRTCV_INTERLACE_CONTROL
+-#define CRTCV1_CRTCV_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0
+-#define CRTCV1_CRTCV_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10
+-#define CRTCV1_CRTCV_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x00000001L
+-#define CRTCV1_CRTCV_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L
+-//CRTCV1_CRTCV_INTERLACE_STATUS
+-#define CRTCV1_CRTCV_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0
+-#define CRTCV1_CRTCV_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1
+-#define CRTCV1_CRTCV_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x00000001L
+-#define CRTCV1_CRTCV_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x00000002L
+-//CRTCV1_CRTCV_FIELD_INDICATION_CONTROL
+-#define CRTCV1_CRTCV_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0
+-#define CRTCV1_CRTCV_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1
+-#define CRTCV1_CRTCV_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x00000001L
+-#define CRTCV1_CRTCV_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x00000002L
+-//CRTCV1_CRTCV_PIXEL_DATA_READBACK0
+-#define CRTCV1_CRTCV_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0
+-#define CRTCV1_CRTCV_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10
+-#define CRTCV1_CRTCV_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0x00000FFFL
+-#define CRTCV1_CRTCV_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0x0FFF0000L
+-//CRTCV1_CRTCV_PIXEL_DATA_READBACK1
+-#define CRTCV1_CRTCV_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0
+-#define CRTCV1_CRTCV_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0x00000FFFL
+-//CRTCV1_CRTCV_STATUS
+-#define CRTCV1_CRTCV_STATUS__CRTC_V_BLANK__SHIFT 0x0
+-#define CRTCV1_CRTCV_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1
+-#define CRTCV1_CRTCV_STATUS__CRTC_V_SYNC_A__SHIFT 0x2
+-#define CRTCV1_CRTCV_STATUS__CRTC_V_UPDATE__SHIFT 0x3
+-#define CRTCV1_CRTCV_STATUS__CRTC_V_START_LINE__SHIFT 0x4
+-#define CRTCV1_CRTCV_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5
+-#define CRTCV1_CRTCV_STATUS__CRTC_H_BLANK__SHIFT 0x10
+-#define CRTCV1_CRTCV_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11
+-#define CRTCV1_CRTCV_STATUS__CRTC_H_SYNC_A__SHIFT 0x12
+-#define CRTCV1_CRTCV_STATUS__CRTC_V_BLANK_MASK 0x00000001L
+-#define CRTCV1_CRTCV_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x00000002L
+-#define CRTCV1_CRTCV_STATUS__CRTC_V_SYNC_A_MASK 0x00000004L
+-#define CRTCV1_CRTCV_STATUS__CRTC_V_UPDATE_MASK 0x00000008L
+-#define CRTCV1_CRTCV_STATUS__CRTC_V_START_LINE_MASK 0x00000010L
+-#define CRTCV1_CRTCV_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x00000020L
+-#define CRTCV1_CRTCV_STATUS__CRTC_H_BLANK_MASK 0x00010000L
+-#define CRTCV1_CRTCV_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x00020000L
+-#define CRTCV1_CRTCV_STATUS__CRTC_H_SYNC_A_MASK 0x00040000L
+-//CRTCV1_CRTCV_STATUS_POSITION
+-#define CRTCV1_CRTCV_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0
+-#define CRTCV1_CRTCV_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10
+-#define CRTCV1_CRTCV_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x00003FFFL
+-#define CRTCV1_CRTCV_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x3FFF0000L
+-//CRTCV1_CRTCV_NOM_VERT_POSITION
+-#define CRTCV1_CRTCV_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0
+-#define CRTCV1_CRTCV_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x00003FFFL
+-//CRTCV1_CRTCV_STATUS_FRAME_COUNT
+-#define CRTCV1_CRTCV_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0
+-#define CRTCV1_CRTCV_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0x00FFFFFFL
+-//CRTCV1_CRTCV_STATUS_VF_COUNT
+-#define CRTCV1_CRTCV_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0
+-#define CRTCV1_CRTCV_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x3FFFFFFFL
+-//CRTCV1_CRTCV_STATUS_HV_COUNT
+-#define CRTCV1_CRTCV_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0
+-#define CRTCV1_CRTCV_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x3FFFFFFFL
+-//CRTCV1_CRTCV_COUNT_CONTROL
+-#define CRTCV1_CRTCV_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0
+-#define CRTCV1_CRTCV_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1
+-#define CRTCV1_CRTCV_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x00000001L
+-#define CRTCV1_CRTCV_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x0000001EL
+-//CRTCV1_CRTCV_COUNT_RESET
+-#define CRTCV1_CRTCV_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0
+-#define CRTCV1_CRTCV_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x00000001L
+-//CRTCV1_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE
+-#define CRTCV1_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0
+-#define CRTCV1_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L
+-//CRTCV1_CRTCV_VERT_SYNC_CONTROL
+-#define CRTCV1_CRTCV_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0
+-#define CRTCV1_CRTCV_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8
+-#define CRTCV1_CRTCV_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10
+-#define CRTCV1_CRTCV_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L
+-#define CRTCV1_CRTCV_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L
+-#define CRTCV1_CRTCV_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L
+-//CRTCV1_CRTCV_STEREO_STATUS
+-#define CRTCV1_CRTCV_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0
+-#define CRTCV1_CRTCV_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8
+-#define CRTCV1_CRTCV_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10
+-#define CRTCV1_CRTCV_STEREO_STATUS__CRTC_STEREO_EYE_FLAG__SHIFT 0x14
+-#define CRTCV1_CRTCV_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18
+-#define CRTCV1_CRTCV_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x00000001L
+-#define CRTCV1_CRTCV_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x00000100L
+-#define CRTCV1_CRTCV_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x00010000L
+-#define CRTCV1_CRTCV_STEREO_STATUS__CRTC_STEREO_EYE_FLAG_MASK 0x00100000L
+-#define CRTCV1_CRTCV_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L
+-//CRTCV1_CRTCV_STEREO_CONTROL
+-#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0
+-#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf
+-#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10
+-#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11
+-#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12
+-#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM__SHIFT 0x13
+-#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14
+-#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18
+-#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00003FFFL
+-#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L
+-#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x00010000L
+-#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L
+-#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L
+-#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM_MASK 0x00080000L
+-#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L
+-#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x01000000L
+-//CRTCV1_CRTCV_SNAPSHOT_STATUS
+-#define CRTCV1_CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0
+-#define CRTCV1_CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1
+-#define CRTCV1_CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2
+-#define CRTCV1_CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x00000001L
+-#define CRTCV1_CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x00000002L
+-#define CRTCV1_CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L
+-//CRTCV1_CRTCV_SNAPSHOT_CONTROL
+-#define CRTCV1_CRTCV_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0
+-#define CRTCV1_CRTCV_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L
+-//CRTCV1_CRTCV_SNAPSHOT_POSITION
+-#define CRTCV1_CRTCV_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0
+-#define CRTCV1_CRTCV_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10
+-#define CRTCV1_CRTCV_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x00003FFFL
+-#define CRTCV1_CRTCV_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x3FFF0000L
+-//CRTCV1_CRTCV_SNAPSHOT_FRAME
+-#define CRTCV1_CRTCV_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0
+-#define CRTCV1_CRTCV_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL
+-//CRTCV1_CRTCV_START_LINE_CONTROL
+-#define CRTCV1_CRTCV_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0
+-#define CRTCV1_CRTCV_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x1
+-#define CRTCV1_CRTCV_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x2
+-#define CRTCV1_CRTCV_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x8
+-#define CRTCV1_CRTCV_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc
+-#define CRTCV1_CRTCV_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x00000001L
+-#define CRTCV1_CRTCV_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x00000002L
+-#define CRTCV1_CRTCV_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x00000004L
+-#define CRTCV1_CRTCV_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x00000100L
+-#define CRTCV1_CRTCV_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0x000FF000L
+-//CRTCV1_CRTCV_INTERRUPT_CONTROL
+-#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0
+-#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1
+-#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4
+-#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5
+-#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8
+-#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9
+-#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10
+-#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11
+-#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18
+-#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19
+-#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a
+-#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b
+-#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c
+-#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d
+-#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e
+-#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f
+-#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x00000001L
+-#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x00000002L
+-#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x00000010L
+-#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x00000020L
+-#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L
+-#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L
+-#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L
+-#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L
+-#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x01000000L
+-#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x02000000L
+-#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x04000000L
+-#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x08000000L
+-#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000L
+-#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000L
+-#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L
+-#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L
+-//CRTCV1_CRTCV_UPDATE_LOCK
+-#define CRTCV1_CRTCV_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0
+-#define CRTCV1_CRTCV_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x00000001L
+-//CRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL
+-#define CRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0
+-#define CRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8
+-#define CRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10
+-#define CRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18
+-#define CRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x19
+-#define CRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x00000001L
+-#define CRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x00000100L
+-#define CRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L
+-#define CRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x01000000L
+-#define CRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x02000000L
+-//CRTCV1_CRTCV_VGA_PARAMETER_CAPTURE_MODE
+-#define CRTCV1_CRTCV_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0
+-#define CRTCV1_CRTCV_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x00000001L
+-//CRTCV1_CRTCV_TEST_PATTERN_CONTROL
+-#define CRTCV1_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0
+-#define CRTCV1_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8
+-#define CRTCV1_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10
+-#define CRTCV1_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18
+-#define CRTCV1_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x00000001L
+-#define CRTCV1_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x00000700L
+-#define CRTCV1_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L
+-#define CRTCV1_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xFF000000L
+-//CRTCV1_CRTCV_TEST_PATTERN_PARAMETERS
+-#define CRTCV1_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0
+-#define CRTCV1_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4
+-#define CRTCV1_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8
+-#define CRTCV1_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc
+-#define CRTCV1_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10
+-#define CRTCV1_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0x0000000FL
+-#define CRTCV1_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0x000000F0L
+-#define CRTCV1_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0x00000F00L
+-#define CRTCV1_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0x0000F000L
+-#define CRTCV1_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xFFFF0000L
+-//CRTCV1_CRTCV_TEST_PATTERN_COLOR
+-#define CRTCV1_CRTCV_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0
+-#define CRTCV1_CRTCV_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10
+-#define CRTCV1_CRTCV_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0x0000FFFFL
+-#define CRTCV1_CRTCV_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x003F0000L
+-//CRTCV1_CRTCV_MASTER_UPDATE_LOCK
+-#define CRTCV1_CRTCV_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0
+-#define CRTCV1_CRTCV_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8
+-#define CRTCV1_CRTCV_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK__SHIFT 0x10
+-#define CRTCV1_CRTCV_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x00000001L
+-#define CRTCV1_CRTCV_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x00000100L
+-#define CRTCV1_CRTCV_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK_MASK 0x00010000L
+-//CRTCV1_CRTCV_MASTER_UPDATE_MODE
+-#define CRTCV1_CRTCV_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0
+-#define CRTCV1_CRTCV_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10
+-#define CRTCV1_CRTCV_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x00000007L
+-#define CRTCV1_CRTCV_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00030000L
+-//CRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT
+-#define CRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0
+-#define CRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8
+-#define CRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x00000003L
+-#define CRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xFFFFFF00L
+-//CRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER
+-#define CRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0
+-#define CRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0x000000FFL
+-//CRTCV1_CRTCV_MVP_STATUS
+-#define CRTCV1_CRTCV_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0
+-#define CRTCV1_CRTCV_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4
+-#define CRTCV1_CRTCV_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10
+-#define CRTCV1_CRTCV_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14
+-#define CRTCV1_CRTCV_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x00000001L
+-#define CRTCV1_CRTCV_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x00000010L
+-#define CRTCV1_CRTCV_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x00010000L
+-#define CRTCV1_CRTCV_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x00100000L
+-//CRTCV1_CRTCV_MASTER_EN
+-#define CRTCV1_CRTCV_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0
+-#define CRTCV1_CRTCV_MASTER_EN__CRTC_MASTER_EN_MASK 0x00000001L
+-//CRTCV1_CRTCV_ALLOW_STOP_OFF_V_CNT
+-#define CRTCV1_CRTCV_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0
+-#define CRTCV1_CRTCV_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10
+-#define CRTCV1_CRTCV_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0x000000FFL
+-#define CRTCV1_CRTCV_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x00010000L
+-//CRTCV1_CRTCV_V_UPDATE_INT_STATUS
+-#define CRTCV1_CRTCV_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0
+-#define CRTCV1_CRTCV_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8
+-#define CRTCV1_CRTCV_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x00000001L
+-#define CRTCV1_CRTCV_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x00000100L
+-//CRTCV1_CRTCV_OVERSCAN_COLOR
+-#define CRTCV1_CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0
+-#define CRTCV1_CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa
+-#define CRTCV1_CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14
+-#define CRTCV1_CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x000003FFL
+-#define CRTCV1_CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0x000FFC00L
+-#define CRTCV1_CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3FF00000L
+-//CRTCV1_CRTCV_OVERSCAN_COLOR_EXT
+-#define CRTCV1_CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0
+-#define CRTCV1_CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8
+-#define CRTCV1_CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10
+-#define CRTCV1_CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x00000003L
+-#define CRTCV1_CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x00000300L
+-#define CRTCV1_CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x00030000L
+-//CRTCV1_CRTCV_BLANK_DATA_COLOR
+-#define CRTCV1_CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0
+-#define CRTCV1_CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa
+-#define CRTCV1_CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14
+-#define CRTCV1_CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL
+-#define CRTCV1_CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L
+-#define CRTCV1_CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L
+-//CRTCV1_CRTCV_BLANK_DATA_COLOR_EXT
+-#define CRTCV1_CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0
+-#define CRTCV1_CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8
+-#define CRTCV1_CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10
+-#define CRTCV1_CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x00000003L
+-#define CRTCV1_CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00000300L
+-#define CRTCV1_CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x00030000L
+-//CRTCV1_CRTCV_BLACK_COLOR
+-#define CRTCV1_CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0
+-#define CRTCV1_CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa
+-#define CRTCV1_CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14
+-#define CRTCV1_CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x000003FFL
+-#define CRTCV1_CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0x000FFC00L
+-#define CRTCV1_CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3FF00000L
+-//CRTCV1_CRTCV_BLACK_COLOR_EXT
+-#define CRTCV1_CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0
+-#define CRTCV1_CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8
+-#define CRTCV1_CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10
+-#define CRTCV1_CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x00000003L
+-#define CRTCV1_CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x00000300L
+-#define CRTCV1_CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x00030000L
+-//CRTCV1_CRTCV_VERTICAL_INTERRUPT0_POSITION
+-#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0
+-#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10
+-#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00003FFFL
+-#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x3FFF0000L
+-//CRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL
+-#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4
+-#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8
+-#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc
+-#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10
+-#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14
+-#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18
+-#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L
+-#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L
+-#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L
+-#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L
+-#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L
+-#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L
+-//CRTCV1_CRTCV_VERTICAL_INTERRUPT1_POSITION
+-#define CRTCV1_CRTCV_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0
+-#define CRTCV1_CRTCV_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00003FFFL
+-//CRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL
+-#define CRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8
+-#define CRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc
+-#define CRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10
+-#define CRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14
+-#define CRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18
+-#define CRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L
+-#define CRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L
+-#define CRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L
+-#define CRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L
+-#define CRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L
+-//CRTCV1_CRTCV_VERTICAL_INTERRUPT2_POSITION
+-#define CRTCV1_CRTCV_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0
+-#define CRTCV1_CRTCV_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00003FFFL
+-//CRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL
+-#define CRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8
+-#define CRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc
+-#define CRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10
+-#define CRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14
+-#define CRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18
+-#define CRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L
+-#define CRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L
+-#define CRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L
+-#define CRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L
+-#define CRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L
+-//CRTCV1_CRTCV_CRC_CNTL
+-#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0
+-#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4
+-#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8
+-#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc
+-#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
+-#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14
+-#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18
+-#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC_EN_MASK 0x00000001L
+-#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x00000010L
+-#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x00000300L
+-#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x00003000L
+-#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
+-#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x00700000L
+-#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x07000000L
+-//CRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL
+-#define CRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0
+-#define CRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10
+-#define CRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x00003FFFL
+-#define CRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3FFF0000L
+-//CRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL
+-#define CRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0
+-#define CRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10
+-#define CRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x00003FFFL
+-#define CRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3FFF0000L
+-//CRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL
+-#define CRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0
+-#define CRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10
+-#define CRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x00003FFFL
+-#define CRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3FFF0000L
+-//CRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL
+-#define CRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0
+-#define CRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10
+-#define CRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x00003FFFL
+-#define CRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3FFF0000L
+-//CRTCV1_CRTCV_CRC0_DATA_RG
+-#define CRTCV1_CRTCV_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0
+-#define CRTCV1_CRTCV_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10
+-#define CRTCV1_CRTCV_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL
+-#define CRTCV1_CRTCV_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L
+-//CRTCV1_CRTCV_CRC0_DATA_B
+-#define CRTCV1_CRTCV_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0
+-#define CRTCV1_CRTCV_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL
+-//CRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL
+-#define CRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0
+-#define CRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10
+-#define CRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x00003FFFL
+-#define CRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3FFF0000L
+-//CRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL
+-#define CRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0
+-#define CRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10
+-#define CRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x00003FFFL
+-#define CRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3FFF0000L
+-//CRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL
+-#define CRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0
+-#define CRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10
+-#define CRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x00003FFFL
+-#define CRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3FFF0000L
+-//CRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL
+-#define CRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0
+-#define CRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10
+-#define CRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x00003FFFL
+-#define CRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3FFF0000L
+-//CRTCV1_CRTCV_CRC1_DATA_RG
+-#define CRTCV1_CRTCV_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0
+-#define CRTCV1_CRTCV_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10
+-#define CRTCV1_CRTCV_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL
+-#define CRTCV1_CRTCV_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L
+-//CRTCV1_CRTCV_CRC1_DATA_B
+-#define CRTCV1_CRTCV_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0
+-#define CRTCV1_CRTCV_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL
+-//CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE__SHIFT 0x0
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__SHIFT 0x3
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__SHIFT 0x4
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__SHIFT 0x5
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__SHIFT 0x8
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__SHIFT 0x9
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__SHIFT 0xc
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__SHIFT 0xd
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__SHIFT 0xe
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE__SHIFT 0x18
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE__SHIFT 0x1c
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE_MASK 0x00000003L
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_MASK 0x00000008L
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_MASK 0x00000010L
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_MASK 0x00000060L
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_MASK 0x00000100L
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_MASK 0x00000200L
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_MASK 0x00001000L
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_MASK 0x00002000L
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_MASK 0x00004000L
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE_MASK 0x07000000L
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE_MASK 0x70000000L
+-//CRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_START
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X__SHIFT 0x0
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y__SHIFT 0x10
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X_MASK 0x00003FFFL
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y_MASK 0x3FFF0000L
+-//CRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_END
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X__SHIFT 0x0
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y__SHIFT 0x10
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X_MASK 0x00003FFFL
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y_MASK 0x3FFF0000L
+-//CRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__SHIFT 0x0
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS__SHIFT 0x4
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS__SHIFT 0x8
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__SHIFT 0x10
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__SHIFT 0x14
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__SHIFT 0x1d
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_MASK 0x00000001L
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS_MASK 0x00000010L
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS_MASK 0x00000100L
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_MASK 0x00010000L
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_MASK 0x00100000L
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_MASK 0xE0000000L
+-//CRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE__SHIFT 0x0
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS__SHIFT 0x4
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS__SHIFT 0x8
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR__SHIFT 0x10
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE__SHIFT 0x14
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE_MASK 0x00000001L
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS_MASK 0x00000010L
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS_MASK 0x00000100L
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR_MASK 0x00010000L
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE_MASK 0x00100000L
+-//CRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__SHIFT 0x0
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS__SHIFT 0x4
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS__SHIFT 0x8
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__SHIFT 0x10
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__SHIFT 0x14
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_MASK 0x00000001L
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS_MASK 0x00000010L
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS_MASK 0x00000100L
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_MASK 0x00010000L
+-#define CRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_MASK 0x00100000L
+-//CRTCV1_CRTCV_STATIC_SCREEN_CONTROL
+-#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0
+-#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10
+-#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18
+-#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19
+-#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a
+-#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b
+-#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c
+-#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL
+-#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L
+-#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x01000000L
+-#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x02000000L
+-#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x04000000L
+-#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x08000000L
+-#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000L
+-//CRTCV1_CRTCV_3D_STRUCTURE_CONTROL
+-#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0
+-#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4
+-#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8
+-#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc
+-#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10
+-#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11
+-#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12
+-#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x00000001L
+-#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x00000010L
+-#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L
+-#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L
+-#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L
+-#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L
+-#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L
+-//CRTCV1_CRTCV_GSL_VSYNC_GAP
+-#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0
+-#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8
+-#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10
+-#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11
+-#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13
+-#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14
+-#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17
+-#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18
+-#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL
+-#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L
+-#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L
+-#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x00060000L
+-#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L
+-#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L
+-#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L
+-#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xFF000000L
+-//CRTCV1_CRTCV_GSL_WINDOW
+-#define CRTCV1_CRTCV_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0
+-#define CRTCV1_CRTCV_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10
+-#define CRTCV1_CRTCV_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x00003FFFL
+-#define CRTCV1_CRTCV_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x3FFF0000L
+-//CRTCV1_CRTCV_GSL_CONTROL
+-#define CRTCV1_CRTCV_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0
+-#define CRTCV1_CRTCV_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10
+-#define CRTCV1_CRTCV_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c
+-#define CRTCV1_CRTCV_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x00003FFFL
+-#define CRTCV1_CRTCV_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x001F0000L
+-#define CRTCV1_CRTCV_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L
+-
+-
+-// addressBlock: dce_dc_hpd0_dispdec
+-//HPD0_DC_HPD_INT_STATUS
+-#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0
+-#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1
+-#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4
+-#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8
+-#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
+-#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
+-#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L
+-#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L
+-#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L
+-#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L
+-#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L
+-#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L
+-//HPD0_DC_HPD_INT_CONTROL
+-#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0
+-#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8
+-#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10
+-#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14
+-#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18
+-#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L
+-#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L
+-#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L
+-#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L
+-#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L
+-//HPD0_DC_HPD_CONTROL
+-#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0
+-#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10
+-#define HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c
+-#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL
+-#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L
+-#define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L
+-//HPD0_DC_HPD_FAST_TRAIN_CNTL
+-#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0
+-#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
+-#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18
+-#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
+-#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL
+-#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L
+-#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L
+-#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L
+-//HPD0_DC_HPD_TOGGLE_FILT_CNTL
+-#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0
+-#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14
+-#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL
+-#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L
+-
+-
+-// addressBlock: dce_dc_hpd1_dispdec
+-//HPD1_DC_HPD_INT_STATUS
+-#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0
+-#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1
+-#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4
+-#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8
+-#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
+-#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
+-#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L
+-#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L
+-#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L
+-#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L
+-#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L
+-#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L
+-//HPD1_DC_HPD_INT_CONTROL
+-#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0
+-#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8
+-#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10
+-#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14
+-#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18
+-#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L
+-#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L
+-#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L
+-#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L
+-#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L
+-//HPD1_DC_HPD_CONTROL
+-#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0
+-#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10
+-#define HPD1_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c
+-#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL
+-#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L
+-#define HPD1_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L
+-//HPD1_DC_HPD_FAST_TRAIN_CNTL
+-#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0
+-#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
+-#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18
+-#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
+-#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL
+-#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L
+-#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L
+-#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L
+-//HPD1_DC_HPD_TOGGLE_FILT_CNTL
+-#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0
+-#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14
+-#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL
+-#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L
+-
+-
+-// addressBlock: dce_dc_hpd2_dispdec
+-//HPD2_DC_HPD_INT_STATUS
+-#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0
+-#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1
+-#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4
+-#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8
+-#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
+-#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
+-#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L
+-#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L
+-#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L
+-#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L
+-#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L
+-#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L
+-//HPD2_DC_HPD_INT_CONTROL
+-#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0
+-#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8
+-#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10
+-#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14
+-#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18
+-#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L
+-#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L
+-#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L
+-#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L
+-#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L
+-//HPD2_DC_HPD_CONTROL
+-#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0
+-#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10
+-#define HPD2_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c
+-#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL
+-#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L
+-#define HPD2_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L
+-//HPD2_DC_HPD_FAST_TRAIN_CNTL
+-#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0
+-#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
+-#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18
+-#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
+-#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL
+-#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L
+-#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L
+-#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L
+-//HPD2_DC_HPD_TOGGLE_FILT_CNTL
+-#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0
+-#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14
+-#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL
+-#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L
+-
+-
+-// addressBlock: dce_dc_hpd3_dispdec
+-//HPD3_DC_HPD_INT_STATUS
+-#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0
+-#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1
+-#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4
+-#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8
+-#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
+-#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
+-#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L
+-#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L
+-#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L
+-#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L
+-#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L
+-#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L
+-//HPD3_DC_HPD_INT_CONTROL
+-#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0
+-#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8
+-#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10
+-#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14
+-#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18
+-#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L
+-#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L
+-#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L
+-#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L
+-#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L
+-//HPD3_DC_HPD_CONTROL
+-#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0
+-#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10
+-#define HPD3_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c
+-#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL
+-#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L
+-#define HPD3_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L
+-//HPD3_DC_HPD_FAST_TRAIN_CNTL
+-#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0
+-#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
+-#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18
+-#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
+-#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL
+-#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L
+-#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L
+-#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L
+-//HPD3_DC_HPD_TOGGLE_FILT_CNTL
+-#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0
+-#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14
+-#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL
+-#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L
+-
+-
+-// addressBlock: dce_dc_hpd4_dispdec
+-//HPD4_DC_HPD_INT_STATUS
+-#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0
+-#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1
+-#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4
+-#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8
+-#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
+-#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
+-#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L
+-#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L
+-#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L
+-#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L
+-#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L
+-#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L
+-//HPD4_DC_HPD_INT_CONTROL
+-#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0
+-#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8
+-#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10
+-#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14
+-#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18
+-#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L
+-#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L
+-#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L
+-#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L
+-#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L
+-//HPD4_DC_HPD_CONTROL
+-#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0
+-#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10
+-#define HPD4_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c
+-#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL
+-#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L
+-#define HPD4_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L
+-//HPD4_DC_HPD_FAST_TRAIN_CNTL
+-#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0
+-#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
+-#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18
+-#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
+-#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL
+-#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L
+-#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L
+-#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L
+-//HPD4_DC_HPD_TOGGLE_FILT_CNTL
+-#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0
+-#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14
+-#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL
+-#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L
+-
+-
+-// addressBlock: dce_dc_hpd5_dispdec
+-//HPD5_DC_HPD_INT_STATUS
+-#define HPD5_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0
+-#define HPD5_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1
+-#define HPD5_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4
+-#define HPD5_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8
+-#define HPD5_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
+-#define HPD5_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
+-#define HPD5_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L
+-#define HPD5_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L
+-#define HPD5_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L
+-#define HPD5_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L
+-#define HPD5_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L
+-#define HPD5_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L
+-//HPD5_DC_HPD_INT_CONTROL
+-#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0
+-#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8
+-#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10
+-#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14
+-#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18
+-#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L
+-#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L
+-#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L
+-#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L
+-#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L
+-//HPD5_DC_HPD_CONTROL
+-#define HPD5_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0
+-#define HPD5_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10
+-#define HPD5_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c
+-#define HPD5_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL
+-#define HPD5_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L
+-#define HPD5_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L
+-//HPD5_DC_HPD_FAST_TRAIN_CNTL
+-#define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0
+-#define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
+-#define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18
+-#define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
+-#define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL
+-#define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L
+-#define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L
+-#define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L
+-//HPD5_DC_HPD_TOGGLE_FILT_CNTL
+-#define HPD5_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0
+-#define HPD5_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14
+-#define HPD5_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL
+-#define HPD5_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L
+-
+-
+-// addressBlock: dce_dc_dc_perfmon2_dispdec
+-//DC_PERFMON2_PERFCOUNTER_CNTL
+-#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+-#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+-#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+-#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+-#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+-#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
+-#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+-#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+-#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+-#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+-#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+-#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
+-#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+-#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+-#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+-#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+-#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+-#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+-#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
+-#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+-#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+-#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+-#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+-#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+-#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
+-#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+-//DC_PERFMON2_PERFCOUNTER_CNTL2
+-#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+-#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+-#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+-#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+-#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+-#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+-#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+-#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+-//DC_PERFMON2_PERFCOUNTER_STATE
+-#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+-#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+-#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+-#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+-#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+-#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+-#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+-#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+-#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+-#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+-#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+-#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+-#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+-#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+-#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+-#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+-#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+-#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+-#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+-#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+-#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+-#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+-#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+-#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+-#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+-#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+-#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+-#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+-#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+-#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+-#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+-#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+-//DC_PERFMON2_PERFMON_CNTL
+-#define DC_PERFMON2_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+-#define DC_PERFMON2_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+-#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+-#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+-#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+-#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+-#define DC_PERFMON2_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+-#define DC_PERFMON2_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+-#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+-#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+-#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+-#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+-//DC_PERFMON2_PERFMON_CNTL2
+-#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+-#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+-#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+-#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+-#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+-#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+-#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+-#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+-//DC_PERFMON2_PERFMON_CVALUE_INT_MISC
+-#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+-#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+-#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+-#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+-#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+-#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+-#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+-#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+-#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+-#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+-#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+-#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+-#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+-#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+-#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+-#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+-#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+-#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+-#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+-#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+-#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+-#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+-#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+-#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+-#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+-#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+-#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+-#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+-#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+-#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+-#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+-#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+-#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+-#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+-//DC_PERFMON2_PERFMON_CVALUE_LOW
+-#define DC_PERFMON2_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+-#define DC_PERFMON2_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+-//DC_PERFMON2_PERFMON_HI
+-#define DC_PERFMON2_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+-#define DC_PERFMON2_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+-#define DC_PERFMON2_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+-#define DC_PERFMON2_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+-//DC_PERFMON2_PERFMON_LOW
+-#define DC_PERFMON2_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+-#define DC_PERFMON2_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dp_aux0_dispdec
+-//DP_AUX0_AUX_CONTROL
+-#define DP_AUX0_AUX_CONTROL__AUX_EN__SHIFT 0x0
+-#define DP_AUX0_AUX_CONTROL__AUX_RESET__SHIFT 0x4
+-#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5
+-#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8
+-#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc
+-#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10
+-#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12
+-#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14
+-#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18
+-#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c
+-#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d
+-#define DP_AUX0_AUX_CONTROL__SPARE_0__SHIFT 0x1e
+-#define DP_AUX0_AUX_CONTROL__SPARE_1__SHIFT 0x1f
+-#define DP_AUX0_AUX_CONTROL__AUX_EN_MASK 0x00000001L
+-#define DP_AUX0_AUX_CONTROL__AUX_RESET_MASK 0x00000010L
+-#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L
+-#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L
+-#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L
+-#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L
+-#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L
+-#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L
+-#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L
+-#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L
+-#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L
+-#define DP_AUX0_AUX_CONTROL__SPARE_0_MASK 0x40000000L
+-#define DP_AUX0_AUX_CONTROL__SPARE_1_MASK 0x80000000L
+-//DP_AUX0_AUX_SW_CONTROL
+-#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0
+-#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2
+-#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4
+-#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10
+-#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L
+-#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L
+-#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L
+-#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L
+-//DP_AUX0_AUX_ARB_CONTROL
+-#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0
+-#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2
+-#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8
+-#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa
+-#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10
+-#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10
+-#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11
+-#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18
+-#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18
+-#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19
+-#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L
+-#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL
+-#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L
+-#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L
+-#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L
+-#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L
+-#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L
+-#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L
+-#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L
+-#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L
+-//DP_AUX0_AUX_INTERRUPT_CONTROL
+-#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0
+-#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1
+-#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2
+-#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4
+-#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5
+-#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6
+-#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8
+-#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9
+-#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa
+-#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc
+-#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd
+-#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe
+-#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L
+-#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L
+-#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L
+-#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L
+-#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L
+-#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L
+-#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L
+-#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L
+-#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L
+-#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L
+-#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L
+-#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L
+-//DP_AUX0_AUX_SW_STATUS
+-#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0
+-#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1
+-#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4
+-#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7
+-#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8
+-#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9
+-#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa
+-#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb
+-#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc
+-#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe
+-#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11
+-#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12
+-#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13
+-#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14
+-#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16
+-#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17
+-#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18
+-#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e
+-#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L
+-#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L
+-#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L
+-#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L
+-#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L
+-#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L
+-#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L
+-#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L
+-#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+-#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L
+-#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L
+-#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L
+-#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L
+-#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L
+-#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L
+-#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L
+-#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L
+-#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xC0000000L
+-//DP_AUX0_AUX_LS_STATUS
+-#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0
+-#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1
+-#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4
+-#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7
+-#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8
+-#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9
+-#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa
+-#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb
+-#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc
+-#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe
+-#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11
+-#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12
+-#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13
+-#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14
+-#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16
+-#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17
+-#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18
+-#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d
+-#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e
+-#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f
+-#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L
+-#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L
+-#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L
+-#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L
+-#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L
+-#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L
+-#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L
+-#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L
+-#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+-#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L
+-#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L
+-#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L
+-#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L
+-#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L
+-#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L
+-#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L
+-#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L
+-#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L
+-#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L
+-#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L
+-//DP_AUX0_AUX_SW_DATA
+-#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0
+-#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8
+-#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10
+-#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f
+-#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L
+-#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L
+-#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L
+-#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L
+-//DP_AUX0_AUX_LS_DATA
+-#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8
+-#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10
+-#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L
+-#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L
+-//DP_AUX0_AUX_DPHY_TX_REF_CONTROL
+-#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0
+-#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4
+-#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10
+-#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L
+-#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L
+-#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L
+-//DP_AUX0_AUX_DPHY_TX_CONTROL
+-#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0
+-#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8
+-#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10
+-#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x00000007L
+-#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L
+-#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L
+-//DP_AUX0_AUX_DPHY_RX_CONTROL0
+-#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4
+-#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8
+-#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc
+-#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10
+-#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11
+-#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12
+-#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13
+-#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14
+-#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18
+-#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c
+-#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L
+-#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L
+-#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L
+-#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L
+-#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L
+-#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L
+-#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L
+-#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L
+-#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x07000000L
+-#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L
+-//DP_AUX0_AUX_DPHY_RX_CONTROL1
+-#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0
+-#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL
+-//DP_AUX0_AUX_DPHY_TX_STATUS
+-#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0
+-#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4
+-#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10
+-#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L
+-#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L
+-#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L
+-//DP_AUX0_AUX_DPHY_RX_STATUS
+-#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0
+-#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8
+-#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10
+-#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15
+-#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L
+-#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L
+-#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L
+-#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L
+-//DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL
+-#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0
+-#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8
+-#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10
+-#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14
+-#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL
+-#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L
+-#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L
+-#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L
+-//DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS
+-#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0
+-#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4
+-#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8
+-#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9
+-#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10
+-#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14
+-#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15
+-#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16
+-#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17
+-#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18
+-#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19
+-#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c
+-#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L
+-#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L
+-#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L
+-#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L
+-#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L
+-#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L
+-#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L
+-#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L
+-#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L
+-#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L
+-#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L
+-#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L
+-//DP_AUX0_AUX_GTC_SYNC_STATUS
+-#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0
+-#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1
+-#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4
+-#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7
+-#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8
+-#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9
+-#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa
+-#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb
+-#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc
+-#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe
+-#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11
+-#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12
+-#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13
+-#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14
+-#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16
+-#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17
+-#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18
+-#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d
+-#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e
+-#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L
+-#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L
+-#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L
+-#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L
+-#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L
+-#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L
+-#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L
+-#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L
+-#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+-#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L
+-#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L
+-#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L
+-#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L
+-#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L
+-#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L
+-#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L
+-#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L
+-#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L
+-#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L
+-
+-
+-// addressBlock: dce_dc_dp_aux1_dispdec
+-//DP_AUX1_AUX_CONTROL
+-#define DP_AUX1_AUX_CONTROL__AUX_EN__SHIFT 0x0
+-#define DP_AUX1_AUX_CONTROL__AUX_RESET__SHIFT 0x4
+-#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5
+-#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8
+-#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc
+-#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10
+-#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12
+-#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14
+-#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18
+-#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c
+-#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d
+-#define DP_AUX1_AUX_CONTROL__SPARE_0__SHIFT 0x1e
+-#define DP_AUX1_AUX_CONTROL__SPARE_1__SHIFT 0x1f
+-#define DP_AUX1_AUX_CONTROL__AUX_EN_MASK 0x00000001L
+-#define DP_AUX1_AUX_CONTROL__AUX_RESET_MASK 0x00000010L
+-#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L
+-#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L
+-#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L
+-#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L
+-#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L
+-#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L
+-#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L
+-#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L
+-#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L
+-#define DP_AUX1_AUX_CONTROL__SPARE_0_MASK 0x40000000L
+-#define DP_AUX1_AUX_CONTROL__SPARE_1_MASK 0x80000000L
+-//DP_AUX1_AUX_SW_CONTROL
+-#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0
+-#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2
+-#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4
+-#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10
+-#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L
+-#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L
+-#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L
+-#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L
+-//DP_AUX1_AUX_ARB_CONTROL
+-#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0
+-#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2
+-#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8
+-#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa
+-#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10
+-#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10
+-#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11
+-#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18
+-#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18
+-#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19
+-#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L
+-#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL
+-#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L
+-#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L
+-#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L
+-#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L
+-#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L
+-#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L
+-#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L
+-#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L
+-//DP_AUX1_AUX_INTERRUPT_CONTROL
+-#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0
+-#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1
+-#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2
+-#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4
+-#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5
+-#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6
+-#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8
+-#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9
+-#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa
+-#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc
+-#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd
+-#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe
+-#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L
+-#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L
+-#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L
+-#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L
+-#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L
+-#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L
+-#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L
+-#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L
+-#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L
+-#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L
+-#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L
+-#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L
+-//DP_AUX1_AUX_SW_STATUS
+-#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0
+-#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1
+-#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4
+-#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7
+-#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8
+-#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9
+-#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa
+-#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb
+-#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc
+-#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe
+-#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11
+-#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12
+-#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13
+-#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14
+-#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16
+-#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17
+-#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18
+-#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e
+-#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L
+-#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L
+-#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L
+-#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L
+-#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L
+-#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L
+-#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L
+-#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L
+-#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+-#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L
+-#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L
+-#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L
+-#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L
+-#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L
+-#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L
+-#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L
+-#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L
+-#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xC0000000L
+-//DP_AUX1_AUX_LS_STATUS
+-#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0
+-#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1
+-#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4
+-#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7
+-#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8
+-#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9
+-#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa
+-#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb
+-#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc
+-#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe
+-#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11
+-#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12
+-#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13
+-#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14
+-#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16
+-#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17
+-#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18
+-#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d
+-#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e
+-#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f
+-#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L
+-#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L
+-#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L
+-#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L
+-#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L
+-#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L
+-#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L
+-#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L
+-#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+-#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L
+-#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L
+-#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L
+-#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L
+-#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L
+-#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L
+-#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L
+-#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L
+-#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L
+-#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L
+-#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L
+-//DP_AUX1_AUX_SW_DATA
+-#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0
+-#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8
+-#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10
+-#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f
+-#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L
+-#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L
+-#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L
+-#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L
+-//DP_AUX1_AUX_LS_DATA
+-#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8
+-#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10
+-#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L
+-#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L
+-//DP_AUX1_AUX_DPHY_TX_REF_CONTROL
+-#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0
+-#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4
+-#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10
+-#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L
+-#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L
+-#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L
+-//DP_AUX1_AUX_DPHY_TX_CONTROL
+-#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0
+-#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8
+-#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10
+-#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x00000007L
+-#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L
+-#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L
+-//DP_AUX1_AUX_DPHY_RX_CONTROL0
+-#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4
+-#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8
+-#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc
+-#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10
+-#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11
+-#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12
+-#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13
+-#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14
+-#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18
+-#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c
+-#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L
+-#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L
+-#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L
+-#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L
+-#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L
+-#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L
+-#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L
+-#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L
+-#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x07000000L
+-#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L
+-//DP_AUX1_AUX_DPHY_RX_CONTROL1
+-#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0
+-#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL
+-//DP_AUX1_AUX_DPHY_TX_STATUS
+-#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0
+-#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4
+-#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10
+-#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L
+-#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L
+-#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L
+-//DP_AUX1_AUX_DPHY_RX_STATUS
+-#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0
+-#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8
+-#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10
+-#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15
+-#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L
+-#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L
+-#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L
+-#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L
+-//DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL
+-#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0
+-#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8
+-#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10
+-#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14
+-#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL
+-#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L
+-#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L
+-#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L
+-//DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS
+-#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0
+-#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4
+-#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8
+-#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9
+-#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10
+-#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14
+-#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15
+-#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16
+-#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17
+-#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18
+-#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19
+-#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c
+-#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L
+-#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L
+-#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L
+-#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L
+-#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L
+-#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L
+-#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L
+-#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L
+-#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L
+-#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L
+-#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L
+-#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L
+-//DP_AUX1_AUX_GTC_SYNC_STATUS
+-#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0
+-#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1
+-#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4
+-#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7
+-#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8
+-#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9
+-#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa
+-#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb
+-#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc
+-#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe
+-#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11
+-#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12
+-#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13
+-#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14
+-#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16
+-#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17
+-#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18
+-#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d
+-#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e
+-#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L
+-#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L
+-#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L
+-#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L
+-#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L
+-#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L
+-#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L
+-#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L
+-#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+-#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L
+-#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L
+-#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L
+-#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L
+-#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L
+-#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L
+-#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L
+-#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L
+-#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L
+-#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L
+-
+-
+-// addressBlock: dce_dc_dp_aux2_dispdec
+-//DP_AUX2_AUX_CONTROL
+-#define DP_AUX2_AUX_CONTROL__AUX_EN__SHIFT 0x0
+-#define DP_AUX2_AUX_CONTROL__AUX_RESET__SHIFT 0x4
+-#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5
+-#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8
+-#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc
+-#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10
+-#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12
+-#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14
+-#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18
+-#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c
+-#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d
+-#define DP_AUX2_AUX_CONTROL__SPARE_0__SHIFT 0x1e
+-#define DP_AUX2_AUX_CONTROL__SPARE_1__SHIFT 0x1f
+-#define DP_AUX2_AUX_CONTROL__AUX_EN_MASK 0x00000001L
+-#define DP_AUX2_AUX_CONTROL__AUX_RESET_MASK 0x00000010L
+-#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L
+-#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L
+-#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L
+-#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L
+-#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L
+-#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L
+-#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L
+-#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L
+-#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L
+-#define DP_AUX2_AUX_CONTROL__SPARE_0_MASK 0x40000000L
+-#define DP_AUX2_AUX_CONTROL__SPARE_1_MASK 0x80000000L
+-//DP_AUX2_AUX_SW_CONTROL
+-#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0
+-#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2
+-#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4
+-#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10
+-#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L
+-#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L
+-#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L
+-#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L
+-//DP_AUX2_AUX_ARB_CONTROL
+-#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0
+-#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2
+-#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8
+-#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa
+-#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10
+-#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10
+-#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11
+-#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18
+-#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18
+-#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19
+-#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L
+-#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL
+-#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L
+-#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L
+-#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L
+-#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L
+-#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L
+-#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L
+-#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L
+-#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L
+-//DP_AUX2_AUX_INTERRUPT_CONTROL
+-#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0
+-#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1
+-#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2
+-#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4
+-#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5
+-#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6
+-#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8
+-#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9
+-#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa
+-#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc
+-#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd
+-#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe
+-#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L
+-#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L
+-#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L
+-#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L
+-#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L
+-#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L
+-#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L
+-#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L
+-#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L
+-#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L
+-#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L
+-#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L
+-//DP_AUX2_AUX_SW_STATUS
+-#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0
+-#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1
+-#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4
+-#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7
+-#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8
+-#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9
+-#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa
+-#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb
+-#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc
+-#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe
+-#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11
+-#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12
+-#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13
+-#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14
+-#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16
+-#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17
+-#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18
+-#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e
+-#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L
+-#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L
+-#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L
+-#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L
+-#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L
+-#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L
+-#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L
+-#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L
+-#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+-#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L
+-#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L
+-#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L
+-#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L
+-#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L
+-#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L
+-#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L
+-#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L
+-#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xC0000000L
+-//DP_AUX2_AUX_LS_STATUS
+-#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0
+-#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1
+-#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4
+-#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7
+-#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8
+-#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9
+-#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa
+-#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb
+-#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc
+-#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe
+-#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11
+-#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12
+-#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13
+-#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14
+-#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16
+-#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17
+-#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18
+-#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d
+-#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e
+-#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f
+-#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L
+-#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L
+-#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L
+-#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L
+-#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L
+-#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L
+-#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L
+-#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L
+-#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+-#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L
+-#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L
+-#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L
+-#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L
+-#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L
+-#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L
+-#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L
+-#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L
+-#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L
+-#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L
+-#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L
+-//DP_AUX2_AUX_SW_DATA
+-#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0
+-#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8
+-#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10
+-#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f
+-#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L
+-#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L
+-#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L
+-#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L
+-//DP_AUX2_AUX_LS_DATA
+-#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8
+-#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10
+-#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L
+-#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L
+-//DP_AUX2_AUX_DPHY_TX_REF_CONTROL
+-#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0
+-#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4
+-#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10
+-#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L
+-#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L
+-#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L
+-//DP_AUX2_AUX_DPHY_TX_CONTROL
+-#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0
+-#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8
+-#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10
+-#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x00000007L
+-#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L
+-#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L
+-//DP_AUX2_AUX_DPHY_RX_CONTROL0
+-#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4
+-#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8
+-#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc
+-#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10
+-#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11
+-#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12
+-#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13
+-#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14
+-#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18
+-#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c
+-#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L
+-#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L
+-#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L
+-#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L
+-#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L
+-#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L
+-#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L
+-#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L
+-#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x07000000L
+-#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L
+-//DP_AUX2_AUX_DPHY_RX_CONTROL1
+-#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0
+-#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL
+-//DP_AUX2_AUX_DPHY_TX_STATUS
+-#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0
+-#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4
+-#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10
+-#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L
+-#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L
+-#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L
+-//DP_AUX2_AUX_DPHY_RX_STATUS
+-#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0
+-#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8
+-#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10
+-#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15
+-#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L
+-#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L
+-#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L
+-#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L
+-//DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL
+-#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0
+-#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8
+-#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10
+-#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14
+-#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL
+-#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L
+-#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L
+-#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L
+-//DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS
+-#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0
+-#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4
+-#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8
+-#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9
+-#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10
+-#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14
+-#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15
+-#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16
+-#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17
+-#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18
+-#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19
+-#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c
+-#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L
+-#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L
+-#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L
+-#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L
+-#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L
+-#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L
+-#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L
+-#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L
+-#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L
+-#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L
+-#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L
+-#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L
+-//DP_AUX2_AUX_GTC_SYNC_STATUS
+-#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0
+-#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1
+-#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4
+-#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7
+-#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8
+-#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9
+-#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa
+-#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb
+-#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc
+-#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe
+-#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11
+-#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12
+-#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13
+-#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14
+-#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16
+-#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17
+-#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18
+-#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d
+-#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e
+-#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L
+-#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L
+-#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L
+-#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L
+-#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L
+-#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L
+-#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L
+-#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L
+-#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+-#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L
+-#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L
+-#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L
+-#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L
+-#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L
+-#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L
+-#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L
+-#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L
+-#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L
+-#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L
+-
+-
+-// addressBlock: dce_dc_dp_aux3_dispdec
+-//DP_AUX3_AUX_CONTROL
+-#define DP_AUX3_AUX_CONTROL__AUX_EN__SHIFT 0x0
+-#define DP_AUX3_AUX_CONTROL__AUX_RESET__SHIFT 0x4
+-#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5
+-#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8
+-#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc
+-#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10
+-#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12
+-#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14
+-#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18
+-#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c
+-#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d
+-#define DP_AUX3_AUX_CONTROL__SPARE_0__SHIFT 0x1e
+-#define DP_AUX3_AUX_CONTROL__SPARE_1__SHIFT 0x1f
+-#define DP_AUX3_AUX_CONTROL__AUX_EN_MASK 0x00000001L
+-#define DP_AUX3_AUX_CONTROL__AUX_RESET_MASK 0x00000010L
+-#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L
+-#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L
+-#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L
+-#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L
+-#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L
+-#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L
+-#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L
+-#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L
+-#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L
+-#define DP_AUX3_AUX_CONTROL__SPARE_0_MASK 0x40000000L
+-#define DP_AUX3_AUX_CONTROL__SPARE_1_MASK 0x80000000L
+-//DP_AUX3_AUX_SW_CONTROL
+-#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0
+-#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2
+-#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4
+-#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10
+-#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L
+-#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L
+-#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L
+-#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L
+-//DP_AUX3_AUX_ARB_CONTROL
+-#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0
+-#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2
+-#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8
+-#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa
+-#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10
+-#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10
+-#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11
+-#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18
+-#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18
+-#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19
+-#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L
+-#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL
+-#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L
+-#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L
+-#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L
+-#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L
+-#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L
+-#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L
+-#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L
+-#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L
+-//DP_AUX3_AUX_INTERRUPT_CONTROL
+-#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0
+-#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1
+-#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2
+-#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4
+-#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5
+-#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6
+-#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8
+-#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9
+-#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa
+-#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc
+-#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd
+-#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe
+-#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L
+-#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L
+-#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L
+-#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L
+-#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L
+-#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L
+-#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L
+-#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L
+-#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L
+-#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L
+-#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L
+-#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L
+-//DP_AUX3_AUX_SW_STATUS
+-#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0
+-#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1
+-#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4
+-#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7
+-#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8
+-#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9
+-#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa
+-#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb
+-#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc
+-#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe
+-#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11
+-#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12
+-#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13
+-#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14
+-#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16
+-#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17
+-#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18
+-#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e
+-#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L
+-#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L
+-#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L
+-#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L
+-#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L
+-#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L
+-#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L
+-#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L
+-#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+-#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L
+-#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L
+-#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L
+-#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L
+-#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L
+-#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L
+-#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L
+-#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L
+-#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xC0000000L
+-//DP_AUX3_AUX_LS_STATUS
+-#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0
+-#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1
+-#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4
+-#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7
+-#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8
+-#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9
+-#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa
+-#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb
+-#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc
+-#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe
+-#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11
+-#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12
+-#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13
+-#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14
+-#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16
+-#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17
+-#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18
+-#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d
+-#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e
+-#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f
+-#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L
+-#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L
+-#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L
+-#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L
+-#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L
+-#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L
+-#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L
+-#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L
+-#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+-#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L
+-#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L
+-#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L
+-#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L
+-#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L
+-#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L
+-#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L
+-#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L
+-#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L
+-#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L
+-#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L
+-//DP_AUX3_AUX_SW_DATA
+-#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0
+-#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8
+-#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10
+-#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f
+-#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L
+-#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L
+-#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L
+-#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L
+-//DP_AUX3_AUX_LS_DATA
+-#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8
+-#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10
+-#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L
+-#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L
+-//DP_AUX3_AUX_DPHY_TX_REF_CONTROL
+-#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0
+-#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4
+-#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10
+-#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L
+-#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L
+-#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L
+-//DP_AUX3_AUX_DPHY_TX_CONTROL
+-#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0
+-#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8
+-#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10
+-#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x00000007L
+-#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L
+-#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L
+-//DP_AUX3_AUX_DPHY_RX_CONTROL0
+-#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4
+-#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8
+-#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc
+-#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10
+-#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11
+-#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12
+-#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13
+-#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14
+-#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18
+-#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c
+-#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L
+-#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L
+-#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L
+-#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L
+-#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L
+-#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L
+-#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L
+-#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L
+-#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x07000000L
+-#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L
+-//DP_AUX3_AUX_DPHY_RX_CONTROL1
+-#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0
+-#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL
+-//DP_AUX3_AUX_DPHY_TX_STATUS
+-#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0
+-#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4
+-#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10
+-#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L
+-#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L
+-#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L
+-//DP_AUX3_AUX_DPHY_RX_STATUS
+-#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0
+-#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8
+-#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10
+-#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15
+-#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L
+-#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L
+-#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L
+-#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L
+-//DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL
+-#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0
+-#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8
+-#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10
+-#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14
+-#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL
+-#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L
+-#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L
+-#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L
+-//DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS
+-#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0
+-#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4
+-#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8
+-#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9
+-#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10
+-#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14
+-#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15
+-#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16
+-#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17
+-#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18
+-#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19
+-#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c
+-#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L
+-#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L
+-#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L
+-#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L
+-#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L
+-#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L
+-#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L
+-#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L
+-#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L
+-#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L
+-#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L
+-#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L
+-//DP_AUX3_AUX_GTC_SYNC_STATUS
+-#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0
+-#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1
+-#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4
+-#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7
+-#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8
+-#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9
+-#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa
+-#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb
+-#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc
+-#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe
+-#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11
+-#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12
+-#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13
+-#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14
+-#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16
+-#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17
+-#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18
+-#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d
+-#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e
+-#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L
+-#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L
+-#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L
+-#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L
+-#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L
+-#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L
+-#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L
+-#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L
+-#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+-#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L
+-#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L
+-#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L
+-#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L
+-#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L
+-#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L
+-#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L
+-#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L
+-#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L
+-#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L
+-
+-
+-// addressBlock: dce_dc_dp_aux4_dispdec
+-//DP_AUX4_AUX_CONTROL
+-#define DP_AUX4_AUX_CONTROL__AUX_EN__SHIFT 0x0
+-#define DP_AUX4_AUX_CONTROL__AUX_RESET__SHIFT 0x4
+-#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5
+-#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8
+-#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc
+-#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10
+-#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12
+-#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14
+-#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18
+-#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c
+-#define DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d
+-#define DP_AUX4_AUX_CONTROL__SPARE_0__SHIFT 0x1e
+-#define DP_AUX4_AUX_CONTROL__SPARE_1__SHIFT 0x1f
+-#define DP_AUX4_AUX_CONTROL__AUX_EN_MASK 0x00000001L
+-#define DP_AUX4_AUX_CONTROL__AUX_RESET_MASK 0x00000010L
+-#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L
+-#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L
+-#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L
+-#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L
+-#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L
+-#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L
+-#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L
+-#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L
+-#define DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L
+-#define DP_AUX4_AUX_CONTROL__SPARE_0_MASK 0x40000000L
+-#define DP_AUX4_AUX_CONTROL__SPARE_1_MASK 0x80000000L
+-//DP_AUX4_AUX_SW_CONTROL
+-#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0
+-#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2
+-#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4
+-#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10
+-#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L
+-#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L
+-#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L
+-#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L
+-//DP_AUX4_AUX_ARB_CONTROL
+-#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0
+-#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2
+-#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8
+-#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa
+-#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10
+-#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10
+-#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11
+-#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18
+-#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18
+-#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19
+-#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L
+-#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL
+-#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L
+-#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L
+-#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L
+-#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L
+-#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L
+-#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L
+-#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L
+-#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L
+-//DP_AUX4_AUX_INTERRUPT_CONTROL
+-#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0
+-#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1
+-#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2
+-#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4
+-#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5
+-#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6
+-#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8
+-#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9
+-#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa
+-#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc
+-#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd
+-#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe
+-#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L
+-#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L
+-#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L
+-#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L
+-#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L
+-#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L
+-#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L
+-#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L
+-#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L
+-#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L
+-#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L
+-#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L
+-//DP_AUX4_AUX_SW_STATUS
+-#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0
+-#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1
+-#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4
+-#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7
+-#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8
+-#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9
+-#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa
+-#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb
+-#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc
+-#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe
+-#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11
+-#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12
+-#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13
+-#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14
+-#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16
+-#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17
+-#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18
+-#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e
+-#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L
+-#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L
+-#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L
+-#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L
+-#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L
+-#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L
+-#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L
+-#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L
+-#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+-#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L
+-#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L
+-#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L
+-#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L
+-#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L
+-#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L
+-#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L
+-#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L
+-#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xC0000000L
+-//DP_AUX4_AUX_LS_STATUS
+-#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0
+-#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1
+-#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4
+-#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7
+-#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8
+-#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9
+-#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa
+-#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb
+-#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc
+-#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe
+-#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11
+-#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12
+-#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13
+-#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14
+-#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16
+-#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17
+-#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18
+-#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d
+-#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e
+-#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f
+-#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L
+-#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L
+-#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L
+-#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L
+-#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L
+-#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L
+-#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L
+-#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L
+-#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+-#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L
+-#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L
+-#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L
+-#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L
+-#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L
+-#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L
+-#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L
+-#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L
+-#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L
+-#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L
+-#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L
+-//DP_AUX4_AUX_SW_DATA
+-#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0
+-#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8
+-#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10
+-#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f
+-#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L
+-#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L
+-#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L
+-#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L
+-//DP_AUX4_AUX_LS_DATA
+-#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8
+-#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10
+-#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L
+-#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L
+-//DP_AUX4_AUX_DPHY_TX_REF_CONTROL
+-#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0
+-#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4
+-#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10
+-#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L
+-#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L
+-#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L
+-//DP_AUX4_AUX_DPHY_TX_CONTROL
+-#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0
+-#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8
+-#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10
+-#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x00000007L
+-#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L
+-#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L
+-//DP_AUX4_AUX_DPHY_RX_CONTROL0
+-#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4
+-#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8
+-#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc
+-#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10
+-#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11
+-#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12
+-#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13
+-#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14
+-#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18
+-#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c
+-#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L
+-#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L
+-#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L
+-#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L
+-#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L
+-#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L
+-#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L
+-#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L
+-#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x07000000L
+-#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L
+-//DP_AUX4_AUX_DPHY_RX_CONTROL1
+-#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0
+-#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL
+-//DP_AUX4_AUX_DPHY_TX_STATUS
+-#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0
+-#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4
+-#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10
+-#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L
+-#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L
+-#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L
+-//DP_AUX4_AUX_DPHY_RX_STATUS
+-#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0
+-#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8
+-#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10
+-#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15
+-#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L
+-#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L
+-#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L
+-#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L
+-//DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL
+-#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0
+-#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8
+-#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10
+-#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14
+-#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL
+-#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L
+-#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L
+-#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L
+-//DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS
+-#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0
+-#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4
+-#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8
+-#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9
+-#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10
+-#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14
+-#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15
+-#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16
+-#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17
+-#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18
+-#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19
+-#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c
+-#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L
+-#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L
+-#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L
+-#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L
+-#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L
+-#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L
+-#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L
+-#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L
+-#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L
+-#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L
+-#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L
+-#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L
+-//DP_AUX4_AUX_GTC_SYNC_STATUS
+-#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0
+-#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1
+-#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4
+-#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7
+-#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8
+-#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9
+-#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa
+-#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb
+-#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc
+-#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe
+-#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11
+-#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12
+-#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13
+-#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14
+-#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16
+-#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17
+-#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18
+-#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d
+-#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e
+-#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L
+-#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L
+-#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L
+-#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L
+-#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L
+-#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L
+-#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L
+-#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L
+-#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+-#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L
+-#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L
+-#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L
+-#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L
+-#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L
+-#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L
+-#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L
+-#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L
+-#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L
+-#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L
+-
+-
+-// addressBlock: dce_dc_dp_aux5_dispdec
+-//DP_AUX5_AUX_CONTROL
+-#define DP_AUX5_AUX_CONTROL__AUX_EN__SHIFT 0x0
+-#define DP_AUX5_AUX_CONTROL__AUX_RESET__SHIFT 0x4
+-#define DP_AUX5_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5
+-#define DP_AUX5_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8
+-#define DP_AUX5_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc
+-#define DP_AUX5_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10
+-#define DP_AUX5_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12
+-#define DP_AUX5_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14
+-#define DP_AUX5_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18
+-#define DP_AUX5_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c
+-#define DP_AUX5_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d
+-#define DP_AUX5_AUX_CONTROL__SPARE_0__SHIFT 0x1e
+-#define DP_AUX5_AUX_CONTROL__SPARE_1__SHIFT 0x1f
+-#define DP_AUX5_AUX_CONTROL__AUX_EN_MASK 0x00000001L
+-#define DP_AUX5_AUX_CONTROL__AUX_RESET_MASK 0x00000010L
+-#define DP_AUX5_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L
+-#define DP_AUX5_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L
+-#define DP_AUX5_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L
+-#define DP_AUX5_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L
+-#define DP_AUX5_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L
+-#define DP_AUX5_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L
+-#define DP_AUX5_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L
+-#define DP_AUX5_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L
+-#define DP_AUX5_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L
+-#define DP_AUX5_AUX_CONTROL__SPARE_0_MASK 0x40000000L
+-#define DP_AUX5_AUX_CONTROL__SPARE_1_MASK 0x80000000L
+-//DP_AUX5_AUX_SW_CONTROL
+-#define DP_AUX5_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0
+-#define DP_AUX5_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2
+-#define DP_AUX5_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4
+-#define DP_AUX5_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10
+-#define DP_AUX5_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L
+-#define DP_AUX5_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L
+-#define DP_AUX5_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L
+-#define DP_AUX5_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L
+-//DP_AUX5_AUX_ARB_CONTROL
+-#define DP_AUX5_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0
+-#define DP_AUX5_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2
+-#define DP_AUX5_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8
+-#define DP_AUX5_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa
+-#define DP_AUX5_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10
+-#define DP_AUX5_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10
+-#define DP_AUX5_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11
+-#define DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18
+-#define DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18
+-#define DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19
+-#define DP_AUX5_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L
+-#define DP_AUX5_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL
+-#define DP_AUX5_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L
+-#define DP_AUX5_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L
+-#define DP_AUX5_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L
+-#define DP_AUX5_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L
+-#define DP_AUX5_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L
+-#define DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L
+-#define DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L
+-#define DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L
+-//DP_AUX5_AUX_INTERRUPT_CONTROL
+-#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0
+-#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1
+-#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2
+-#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4
+-#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5
+-#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6
+-#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8
+-#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9
+-#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa
+-#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc
+-#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd
+-#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe
+-#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L
+-#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L
+-#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L
+-#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L
+-#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L
+-#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L
+-#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L
+-#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L
+-#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L
+-#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L
+-#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L
+-#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L
+-//DP_AUX5_AUX_SW_STATUS
+-#define DP_AUX5_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0
+-#define DP_AUX5_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1
+-#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4
+-#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7
+-#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8
+-#define DP_AUX5_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9
+-#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa
+-#define DP_AUX5_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb
+-#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc
+-#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe
+-#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11
+-#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12
+-#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13
+-#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14
+-#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16
+-#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17
+-#define DP_AUX5_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18
+-#define DP_AUX5_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e
+-#define DP_AUX5_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L
+-#define DP_AUX5_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L
+-#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L
+-#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L
+-#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L
+-#define DP_AUX5_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L
+-#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L
+-#define DP_AUX5_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L
+-#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+-#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L
+-#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L
+-#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L
+-#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L
+-#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L
+-#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L
+-#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L
+-#define DP_AUX5_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L
+-#define DP_AUX5_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xC0000000L
+-//DP_AUX5_AUX_LS_STATUS
+-#define DP_AUX5_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0
+-#define DP_AUX5_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1
+-#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4
+-#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7
+-#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8
+-#define DP_AUX5_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9
+-#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa
+-#define DP_AUX5_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb
+-#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc
+-#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe
+-#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11
+-#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12
+-#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13
+-#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14
+-#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16
+-#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17
+-#define DP_AUX5_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18
+-#define DP_AUX5_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d
+-#define DP_AUX5_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e
+-#define DP_AUX5_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f
+-#define DP_AUX5_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L
+-#define DP_AUX5_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L
+-#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L
+-#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L
+-#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L
+-#define DP_AUX5_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L
+-#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L
+-#define DP_AUX5_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L
+-#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+-#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L
+-#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L
+-#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L
+-#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L
+-#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L
+-#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L
+-#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L
+-#define DP_AUX5_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L
+-#define DP_AUX5_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L
+-#define DP_AUX5_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L
+-#define DP_AUX5_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L
+-//DP_AUX5_AUX_SW_DATA
+-#define DP_AUX5_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0
+-#define DP_AUX5_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8
+-#define DP_AUX5_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10
+-#define DP_AUX5_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f
+-#define DP_AUX5_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L
+-#define DP_AUX5_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L
+-#define DP_AUX5_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L
+-#define DP_AUX5_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L
+-//DP_AUX5_AUX_LS_DATA
+-#define DP_AUX5_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8
+-#define DP_AUX5_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10
+-#define DP_AUX5_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L
+-#define DP_AUX5_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L
+-//DP_AUX5_AUX_DPHY_TX_REF_CONTROL
+-#define DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0
+-#define DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4
+-#define DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10
+-#define DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L
+-#define DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L
+-#define DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L
+-//DP_AUX5_AUX_DPHY_TX_CONTROL
+-#define DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0
+-#define DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8
+-#define DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10
+-#define DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x00000007L
+-#define DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L
+-#define DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L
+-//DP_AUX5_AUX_DPHY_RX_CONTROL0
+-#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4
+-#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8
+-#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc
+-#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10
+-#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11
+-#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12
+-#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13
+-#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14
+-#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18
+-#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c
+-#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L
+-#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L
+-#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L
+-#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L
+-#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L
+-#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L
+-#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L
+-#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L
+-#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x07000000L
+-#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L
+-//DP_AUX5_AUX_DPHY_RX_CONTROL1
+-#define DP_AUX5_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0
+-#define DP_AUX5_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL
+-//DP_AUX5_AUX_DPHY_TX_STATUS
+-#define DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0
+-#define DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4
+-#define DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10
+-#define DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L
+-#define DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L
+-#define DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L
+-//DP_AUX5_AUX_DPHY_RX_STATUS
+-#define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0
+-#define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8
+-#define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10
+-#define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15
+-#define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L
+-#define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L
+-#define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L
+-#define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L
+-//DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL
+-#define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0
+-#define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8
+-#define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10
+-#define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14
+-#define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL
+-#define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L
+-#define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L
+-#define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L
+-//DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS
+-#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0
+-#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4
+-#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8
+-#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9
+-#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10
+-#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14
+-#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15
+-#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16
+-#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17
+-#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18
+-#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19
+-#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c
+-#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L
+-#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L
+-#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L
+-#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L
+-#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L
+-#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L
+-#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L
+-#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L
+-#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L
+-#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L
+-#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L
+-#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L
+-//DP_AUX5_AUX_GTC_SYNC_STATUS
+-#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0
+-#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1
+-#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4
+-#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7
+-#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8
+-#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9
+-#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa
+-#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb
+-#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc
+-#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe
+-#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11
+-#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12
+-#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13
+-#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14
+-#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16
+-#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17
+-#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18
+-#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d
+-#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e
+-#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L
+-#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L
+-#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L
+-#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L
+-#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L
+-#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L
+-#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L
+-#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L
+-#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+-#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L
+-#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L
+-#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L
+-#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L
+-#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L
+-#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L
+-#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L
+-#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L
+-#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L
+-#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L
+-
+-
+-// addressBlock: dce_dc_dig0_dispdec
+-//DIG0_DIG_FE_CNTL
+-#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0
+-#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4
+-#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8
+-#define DIG0_DIG_FE_CNTL__DIG_START__SHIFT 0xa
+-#define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18
+-#define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c
+-#define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e
+-#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L
+-#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L
+-#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L
+-#define DIG0_DIG_FE_CNTL__DIG_START_MASK 0x00000400L
+-#define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L
+-#define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L
+-#define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L
+-//DIG0_DIG_OUTPUT_CRC_CNTL
+-#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0
+-#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4
+-#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8
+-#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L
+-#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L
+-#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L
+-//DIG0_DIG_OUTPUT_CRC_RESULT
+-#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0
+-#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL
+-//DIG0_DIG_CLOCK_PATTERN
+-#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0
+-#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL
+-//DIG0_DIG_TEST_PATTERN
+-#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0
+-#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1
+-#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4
+-#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5
+-#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6
+-#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10
+-#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L
+-#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L
+-#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L
+-#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L
+-#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L
+-#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L
+-//DIG0_DIG_RANDOM_PATTERN_SEED
+-#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0
+-#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18
+-#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL
+-#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L
+-//DIG0_DIG_FIFO_STATUS
+-#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0
+-#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
+-#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
+-#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8
+-#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
+-#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
+-#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16
+-#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a
+-#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d
+-#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
+-#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
+-#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L
+-#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L
+-#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL
+-#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L
+-#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L
+-#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L
+-#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L
+-#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L
+-#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L
+-#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L
+-#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L
+-//DIG0_HDMI_CONTROL
+-#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0
+-#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1
+-#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2
+-#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3
+-#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4
+-#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8
+-#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9
+-#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18
+-#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c
+-#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L
+-#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L
+-#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L
+-#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L
+-#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L
+-#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L
+-#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L
+-#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L
+-#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L
+-//DIG0_HDMI_STATUS
+-#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0
+-#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10
+-#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14
+-#define DIG0_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b
+-#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L
+-#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L
+-#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L
+-#define DIG0_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L
+-//DIG0_HDMI_AUDIO_PACKET_CONTROL
+-#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4
+-#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10
+-#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L
+-#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L
+-//DIG0_HDMI_ACR_PACKET_CONTROL
+-#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0
+-#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1
+-#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4
+-#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8
+-#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc
+-#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10
+-#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f
+-#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L
+-#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L
+-#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L
+-#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L
+-#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L
+-#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L
+-#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L
+-//DIG0_HDMI_VBI_PACKET_CONTROL
+-#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0
+-#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4
+-#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5
+-#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8
+-#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9
+-#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10
+-#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L
+-#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L
+-#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L
+-#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L
+-#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L
+-#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L
+-//DIG0_HDMI_INFOFRAME_CONTROL0
+-#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x0
+-#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x1
+-#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4
+-#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5
+-#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8
+-#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9
+-#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x00000001L
+-#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x00000002L
+-#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L
+-#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L
+-#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L
+-#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L
+-//DIG0_HDMI_INFOFRAME_CONTROL1
+-#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x0
+-#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8
+-#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10
+-#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x0000003FL
+-#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L
+-#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L
+-//DIG0_HDMI_GENERIC_PACKET_CONTROL0
+-#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0
+-#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1
+-#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4
+-#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5
+-#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10
+-#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18
+-#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L
+-#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L
+-#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L
+-#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L
+-#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003F0000L
+-#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3F000000L
+-//DIG0_AFMT_INTERRUPT_STATUS
+-//DIG0_HDMI_GC
+-#define DIG0_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0
+-#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2
+-#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4
+-#define DIG0_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8
+-#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc
+-#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L
+-#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L
+-#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L
+-#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L
+-#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L
+-//DIG0_AFMT_AUDIO_PACKET_CONTROL2
+-#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0
+-#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1
+-#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8
+-#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10
+-#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18
+-#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c
+-#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L
+-#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L
+-#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L
+-#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L
+-#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L
+-#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L
+-//DIG0_AFMT_ISRC1_0
+-#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0
+-#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6
+-#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7
+-#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L
+-#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L
+-#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L
+-//DIG0_AFMT_ISRC1_1
+-#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0
+-#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8
+-#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10
+-#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18
+-#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL
+-#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L
+-#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L
+-#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L
+-//DIG0_AFMT_ISRC1_2
+-#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0
+-#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8
+-#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10
+-#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18
+-#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL
+-#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L
+-#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L
+-#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L
+-//DIG0_AFMT_ISRC1_3
+-#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0
+-#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8
+-#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10
+-#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18
+-#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL
+-#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L
+-#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L
+-#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L
+-//DIG0_AFMT_ISRC1_4
+-#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0
+-#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8
+-#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10
+-#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18
+-#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL
+-#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L
+-#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L
+-#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L
+-//DIG0_AFMT_ISRC2_0
+-#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0
+-#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8
+-#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10
+-#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18
+-#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL
+-#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L
+-#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L
+-#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L
+-//DIG0_AFMT_ISRC2_1
+-#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0
+-#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8
+-#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10
+-#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18
+-#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL
+-#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L
+-#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L
+-#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L
+-//DIG0_AFMT_ISRC2_2
+-#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0
+-#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8
+-#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10
+-#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18
+-#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL
+-#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L
+-#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L
+-#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L
+-//DIG0_AFMT_ISRC2_3
+-#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0
+-#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8
+-#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10
+-#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18
+-#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL
+-#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L
+-#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L
+-#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L
+-//DIG0_AFMT_AVI_INFO0
+-#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x0
+-#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x8
+-#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0xa
+-#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0xc
+-#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0xd
+-#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x10
+-#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x14
+-#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x16
+-#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x18
+-#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x1a
+-#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x1c
+-#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x1f
+-#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0x000000FFL
+-#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x00000300L
+-#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0x00000C00L
+-#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x00001000L
+-#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x0000E000L
+-#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0x000F0000L
+-#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x00300000L
+-#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0x00C00000L
+-#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x03000000L
+-#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0x0C000000L
+-#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000L
+-#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000L
+-//DIG0_AFMT_AVI_INFO1
+-#define DIG0_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x0
+-#define DIG0_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x8
+-#define DIG0_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0xc
+-#define DIG0_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0xe
+-#define DIG0_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x10
+-#define DIG0_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x000000FFL
+-#define DIG0_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0x00000F00L
+-#define DIG0_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x00003000L
+-#define DIG0_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0x0000C000L
+-#define DIG0_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xFFFF0000L
+-//DIG0_AFMT_AVI_INFO2
+-#define DIG0_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x0
+-#define DIG0_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x10
+-#define DIG0_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0x0000FFFFL
+-#define DIG0_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xFFFF0000L
+-//DIG0_AFMT_AVI_INFO3
+-#define DIG0_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x0
+-#define DIG0_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x18
+-#define DIG0_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0x0000FFFFL
+-#define DIG0_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xFF000000L
+-//DIG0_AFMT_MPEG_INFO0
+-#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0
+-#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8
+-#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10
+-#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18
+-#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL
+-#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L
+-#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L
+-#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L
+-//DIG0_AFMT_MPEG_INFO1
+-#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0
+-#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8
+-#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc
+-#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL
+-#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L
+-#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L
+-//DIG0_AFMT_GENERIC_HDR
+-#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0
+-#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8
+-#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10
+-#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18
+-#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL
+-#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L
+-#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L
+-#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L
+-//DIG0_AFMT_GENERIC_0
+-#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0
+-#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8
+-#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10
+-#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18
+-#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL
+-#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L
+-#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L
+-#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L
+-//DIG0_AFMT_GENERIC_1
+-#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0
+-#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8
+-#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10
+-#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18
+-#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL
+-#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L
+-#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L
+-#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L
+-//DIG0_AFMT_GENERIC_2
+-#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0
+-#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8
+-#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10
+-#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18
+-#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL
+-#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L
+-#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L
+-#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L
+-//DIG0_AFMT_GENERIC_3
+-#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0
+-#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8
+-#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10
+-#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18
+-#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL
+-#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L
+-#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L
+-#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L
+-//DIG0_AFMT_GENERIC_4
+-#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0
+-#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8
+-#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10
+-#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18
+-#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL
+-#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L
+-#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L
+-#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L
+-//DIG0_AFMT_GENERIC_5
+-#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0
+-#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8
+-#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10
+-#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18
+-#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL
+-#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L
+-#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L
+-#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L
+-//DIG0_AFMT_GENERIC_6
+-#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0
+-#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8
+-#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10
+-#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18
+-#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL
+-#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L
+-#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L
+-#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L
+-//DIG0_AFMT_GENERIC_7
+-#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0
+-#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8
+-#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10
+-#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18
+-#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL
+-#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L
+-#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L
+-#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L
+-//DIG0_HDMI_GENERIC_PACKET_CONTROL1
+-#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0
+-#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1
+-#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4
+-#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5
+-#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10
+-#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18
+-#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L
+-#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L
+-#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L
+-#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L
+-#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003F0000L
+-#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3F000000L
+-//DIG0_HDMI_ACR_32_0
+-#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc
+-#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L
+-//DIG0_HDMI_ACR_32_1
+-#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0
+-#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL
+-//DIG0_HDMI_ACR_44_0
+-#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc
+-#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L
+-//DIG0_HDMI_ACR_44_1
+-#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0
+-#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL
+-//DIG0_HDMI_ACR_48_0
+-#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc
+-#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L
+-//DIG0_HDMI_ACR_48_1
+-#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0
+-#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL
+-//DIG0_HDMI_ACR_STATUS_0
+-#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc
+-#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L
+-//DIG0_HDMI_ACR_STATUS_1
+-#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0
+-#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL
+-//DIG0_AFMT_AUDIO_INFO0
+-#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0
+-#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8
+-#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb
+-#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10
+-#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18
+-#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL
+-#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L
+-#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L
+-#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L
+-#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L
+-//DIG0_AFMT_AUDIO_INFO1
+-#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0
+-#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb
+-#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf
+-#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10
+-#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL
+-#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L
+-#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L
+-#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L
+-//DIG0_AFMT_60958_0
+-#define DIG0_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0
+-#define DIG0_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1
+-#define DIG0_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2
+-#define DIG0_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3
+-#define DIG0_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6
+-#define DIG0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8
+-#define DIG0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10
+-#define DIG0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14
+-#define DIG0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18
+-#define DIG0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c
+-#define DIG0_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
+-#define DIG0_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
+-#define DIG0_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L
+-#define DIG0_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L
+-#define DIG0_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L
+-#define DIG0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L
+-#define DIG0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L
+-#define DIG0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L
+-#define DIG0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L
+-#define DIG0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L
+-//DIG0_AFMT_60958_1
+-#define DIG0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0
+-#define DIG0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4
+-#define DIG0_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10
+-#define DIG0_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12
+-#define DIG0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14
+-#define DIG0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL
+-#define DIG0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L
+-#define DIG0_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L
+-#define DIG0_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L
+-#define DIG0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L
+-//DIG0_AFMT_AUDIO_CRC_CONTROL
+-#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0
+-#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4
+-#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8
+-#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc
+-#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10
+-#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L
+-#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L
+-#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L
+-#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L
+-#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L
+-//DIG0_AFMT_RAMP_CONTROL0
+-#define DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0
+-#define DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f
+-#define DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL
+-#define DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L
+-//DIG0_AFMT_RAMP_CONTROL1
+-#define DIG0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0
+-#define DIG0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18
+-#define DIG0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL
+-#define DIG0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L
+-//DIG0_AFMT_RAMP_CONTROL2
+-#define DIG0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0
+-#define DIG0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL
+-//DIG0_AFMT_RAMP_CONTROL3
+-#define DIG0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0
+-#define DIG0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL
+-//DIG0_AFMT_60958_2
+-#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+-#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+-#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8
+-#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc
+-#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10
+-#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14
+-#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+-#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+-#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L
+-#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L
+-#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L
+-#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L
+-//DIG0_AFMT_AUDIO_CRC_RESULT
+-#define DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0
+-#define DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8
+-#define DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L
+-#define DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L
+-//DIG0_AFMT_STATUS
+-#define DIG0_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4
+-#define DIG0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8
+-#define DIG0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18
+-#define DIG0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e
+-#define DIG0_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L
+-#define DIG0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L
+-#define DIG0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L
+-#define DIG0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L
+-//DIG0_AFMT_AUDIO_PACKET_CONTROL
+-#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0
+-#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb
+-#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc
+-#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe
+-#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17
+-#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18
+-#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a
+-#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e
+-#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L
+-#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L
+-#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L
+-#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L
+-#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L
+-#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L
+-#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L
+-#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L
+-//DIG0_AFMT_VBI_PACKET_CONTROL
+-#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x2
+-#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x3
+-#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1e
+-#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x00000004L
+-#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x00000008L
+-#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xC0000000L
+-//DIG0_AFMT_INFOFRAME_CONTROL0
+-#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6
+-#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7
+-#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa
+-#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L
+-#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L
+-#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L
+-//DIG0_AFMT_AUDIO_SRC_CONTROL
+-#define DIG0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0
+-#define DIG0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L
+-//DIG0_DIG_BE_CNTL
+-#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0
+-#define DIG0_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1
+-#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8
+-#define DIG0_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10
+-#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c
+-#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L
+-#define DIG0_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L
+-#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L
+-#define DIG0_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L
+-#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L
+-//DIG0_DIG_BE_EN_CNTL
+-#define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0
+-#define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8
+-#define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L
+-#define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L
+-//DIG0_TMDS_CNTL
+-#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0
+-#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L
+-//DIG0_TMDS_CONTROL_CHAR
+-#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0
+-#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1
+-#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2
+-#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3
+-#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L
+-#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L
+-#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L
+-#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L
+-//DIG0_TMDS_CONTROL0_FEEDBACK
+-#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0
+-#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8
+-#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L
+-#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L
+-//DIG0_TMDS_STEREOSYNC_CTL_SEL
+-#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0
+-#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L
+-//DIG0_TMDS_SYNC_CHAR_PATTERN_0_1
+-#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0
+-#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10
+-#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL
+-#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L
+-//DIG0_TMDS_SYNC_CHAR_PATTERN_2_3
+-#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0
+-#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10
+-#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL
+-#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L
+-//DIG0_TMDS_CTL_BITS
+-#define DIG0_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0
+-#define DIG0_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8
+-#define DIG0_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10
+-#define DIG0_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18
+-#define DIG0_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L
+-#define DIG0_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L
+-#define DIG0_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L
+-#define DIG0_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L
+-//DIG0_TMDS_DCBALANCER_CONTROL
+-#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0
+-#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8
+-#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10
+-#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18
+-#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L
+-#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L
+-#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L
+-#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L
+-//DIG0_TMDS_CTL0_1_GEN_CNTL
+-#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0
+-#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4
+-#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7
+-#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8
+-#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa
+-#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb
+-#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc
+-#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10
+-#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14
+-#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17
+-#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18
+-#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a
+-#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b
+-#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c
+-#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f
+-#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL
+-#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L
+-#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L
+-#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L
+-#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L
+-#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L
+-#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L
+-#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L
+-#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L
+-#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L
+-#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L
+-#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L
+-#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L
+-#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L
+-#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L
+-//DIG0_TMDS_CTL2_3_GEN_CNTL
+-#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0
+-#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4
+-#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7
+-#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8
+-#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa
+-#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb
+-#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc
+-#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10
+-#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14
+-#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17
+-#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18
+-#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a
+-#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b
+-#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c
+-#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL
+-#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L
+-#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L
+-#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L
+-#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L
+-#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L
+-#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L
+-#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L
+-#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L
+-#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L
+-#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L
+-#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L
+-#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L
+-#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L
+-//DIG0_DIG_VERSION
+-#define DIG0_DIG_VERSION__DIG_TYPE__SHIFT 0x0
+-#define DIG0_DIG_VERSION__DIG_TYPE_MASK 0x00000001L
+-//DIG0_DIG_LANE_ENABLE
+-#define DIG0_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0
+-#define DIG0_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1
+-#define DIG0_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2
+-#define DIG0_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3
+-#define DIG0_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8
+-#define DIG0_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L
+-#define DIG0_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L
+-#define DIG0_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L
+-#define DIG0_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L
+-#define DIG0_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L
+-//DIG0_AFMT_CNTL
+-#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0
+-#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8
+-#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L
+-#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L
+-
+-
+-// addressBlock: dce_dc_dp0_dispdec
+-//DP0_DP_LINK_CNTL
+-#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4
+-#define DP0_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8
+-#define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11
+-#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L
+-#define DP0_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L
+-#define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L
+-//DP0_DP_PIXEL_FORMAT
+-#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0
+-#define DP0_DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x8
+-#define DP0_DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x10
+-#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18
+-#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L
+-#define DP0_DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x00000100L
+-#define DP0_DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x00010000L
+-#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L
+-//DP0_DP_MSA_COLORIMETRY
+-#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x0
+-#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x8
+-#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE__SHIFT 0x9
+-#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE__SHIFT 0x11
+-#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0x000000FFL
+-#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x00000100L
+-#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_MASK 0x00000200L
+-#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE_MASK 0x00020000L
+-//DP0_DP_CONFIG
+-#define DP0_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0
+-#define DP0_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L
+-//DP0_DP_VID_STREAM_CNTL
+-#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0
+-#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8
+-#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10
+-#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14
+-#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L
+-#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L
+-#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L
+-#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L
+-//DP0_DP_STEER_FIFO
+-#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0
+-#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4
+-#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5
+-#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6
+-#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7
+-#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8
+-#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc
+-#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L
+-#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L
+-#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L
+-#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L
+-#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L
+-#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L
+-#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L
+-//DP0_DP_MSA_MISC
+-#define DP0_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x3
+-#define DP0_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8
+-#define DP0_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10
+-#define DP0_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18
+-#define DP0_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x00000078L
+-#define DP0_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L
+-#define DP0_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L
+-#define DP0_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L
+-//DP0_DP_VID_TIMING
+-#define DP0_DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x0
+-#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4
+-#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8
+-#define DP0_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN__SHIFT 0x9
+-#define DP0_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18
+-#define DP0_DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x00000001L
+-#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L
+-#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L
+-#define DP0_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN_MASK 0x00000200L
+-#define DP0_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L
+-//DP0_DP_VID_N
+-#define DP0_DP_VID_N__DP_VID_N__SHIFT 0x0
+-#define DP0_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL
+-//DP0_DP_VID_M
+-#define DP0_DP_VID_M__DP_VID_M__SHIFT 0x0
+-#define DP0_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL
+-//DP0_DP_LINK_FRAMING_CNTL
+-#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0
+-#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18
+-#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c
+-#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL
+-#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L
+-#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L
+-//DP0_DP_HBR2_EYE_PATTERN
+-#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0
+-#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L
+-//DP0_DP_VID_MSA_VBID
+-#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0
+-#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x10
+-#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18
+-#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL
+-#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x00010000L
+-#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L
+-//DP0_DP_VID_INTERRUPT_CNTL
+-#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0
+-#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1
+-#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2
+-#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L
+-#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L
+-#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L
+-//DP0_DP_DPHY_CNTL
+-#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0
+-#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1
+-#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2
+-#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3
+-#define DP0_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10
+-#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18
+-#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L
+-#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L
+-#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L
+-#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L
+-#define DP0_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L
+-#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L
+-//DP0_DP_DPHY_TRAINING_PATTERN_SEL
+-#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0
+-#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L
+-//DP0_DP_DPHY_SYM0
+-#define DP0_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0
+-#define DP0_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa
+-#define DP0_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14
+-#define DP0_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL
+-#define DP0_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L
+-#define DP0_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L
+-//DP0_DP_DPHY_SYM1
+-#define DP0_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0
+-#define DP0_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa
+-#define DP0_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14
+-#define DP0_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL
+-#define DP0_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L
+-#define DP0_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L
+-//DP0_DP_DPHY_SYM2
+-#define DP0_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0
+-#define DP0_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa
+-#define DP0_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL
+-#define DP0_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L
+-//DP0_DP_DPHY_8B10B_CNTL
+-#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8
+-#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10
+-#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18
+-#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L
+-#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L
+-#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L
+-//DP0_DP_DPHY_PRBS_CNTL
+-#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0
+-#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4
+-#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8
+-#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L
+-#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L
+-#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L
+-//DP0_DP_DPHY_SCRAM_CNTL
+-#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0
+-#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4
+-#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8
+-#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18
+-#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L
+-#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L
+-#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L
+-#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L
+-//DP0_DP_DPHY_CRC_EN
+-#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0
+-#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4
+-#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8
+-#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L
+-#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L
+-#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L
+-//DP0_DP_DPHY_CRC_CNTL
+-#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0
+-#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4
+-#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10
+-#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L
+-#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L
+-#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L
+-//DP0_DP_DPHY_CRC_RESULT
+-#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0
+-#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8
+-#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10
+-#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18
+-#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL
+-#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L
+-#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L
+-#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L
+-//DP0_DP_DPHY_CRC_MST_CNTL
+-#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0
+-#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8
+-#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL
+-#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L
+-//DP0_DP_DPHY_CRC_MST_STATUS
+-#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0
+-#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8
+-#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10
+-#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L
+-#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L
+-#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L
+-//DP0_DP_DPHY_FAST_TRAINING
+-#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0
+-#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1
+-#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2
+-#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8
+-#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14
+-#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L
+-#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L
+-#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L
+-#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L
+-#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L
+-//DP0_DP_DPHY_FAST_TRAINING_STATUS
+-#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0
+-#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4
+-#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8
+-#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc
+-#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L
+-#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L
+-#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L
+-#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L
+-//DP0_DP_MSA_V_TIMING_OVERRIDE1
+-#define DP0_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x0
+-#define DP0_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x4
+-#define DP0_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x00000001L
+-#define DP0_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x0003FFF0L
+-//DP0_DP_MSA_V_TIMING_OVERRIDE2
+-#define DP0_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x0
+-#define DP0_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x10
+-#define DP0_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x00003FFFL
+-#define DP0_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x3FFF0000L
+-//DP0_DP_SEC_CNTL
+-#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0
+-#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4
+-#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8
+-#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc
+-#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10
+-#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14
+-#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15
+-#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16
+-#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17
+-#define DP0_DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x18
+-#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c
+-#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L
+-#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L
+-#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L
+-#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L
+-#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L
+-#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L
+-#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L
+-#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L
+-#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L
+-#define DP0_DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x01000000L
+-#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L
+-//DP0_DP_SEC_CNTL1
+-#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0
+-#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4
+-#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5
+-#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6
+-#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7
+-#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10
+-#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L
+-#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L
+-#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L
+-#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L
+-#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L
+-#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L
+-//DP0_DP_SEC_FRAMING1
+-#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0
+-#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+-#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL
+-#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+-//DP0_DP_SEC_FRAMING2
+-#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0
+-#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+-#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL
+-#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+-//DP0_DP_SEC_FRAMING3
+-#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0
+-#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10
+-#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL
+-#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+-//DP0_DP_SEC_FRAMING4
+-#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14
+-#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18
+-#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c
+-#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d
+-#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L
+-#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L
+-#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L
+-#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L
+-//DP0_DP_SEC_AUD_N
+-#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0
+-#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL
+-//DP0_DP_SEC_AUD_N_READBACK
+-#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0
+-#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL
+-//DP0_DP_SEC_AUD_M
+-#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0
+-#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL
+-//DP0_DP_SEC_AUD_M_READBACK
+-#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0
+-#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL
+-//DP0_DP_SEC_TIMESTAMP
+-#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0
+-#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L
+-//DP0_DP_SEC_PACKET_CNTL
+-#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1
+-#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4
+-#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8
+-#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10
+-#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL
+-#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L
+-#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L
+-#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L
+-//DP0_DP_MSE_RATE_CNTL
+-#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0
+-#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a
+-#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL
+-#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L
+-//DP0_DP_MSE_RATE_UPDATE
+-#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0
+-#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L
+-//DP0_DP_MSE_SAT0
+-#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0
+-#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8
+-#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10
+-#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18
+-#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L
+-#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L
+-#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L
+-#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L
+-//DP0_DP_MSE_SAT1
+-#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0
+-#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8
+-#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10
+-#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18
+-#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L
+-#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L
+-#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L
+-#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L
+-//DP0_DP_MSE_SAT2
+-#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0
+-#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8
+-#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10
+-#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18
+-#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L
+-#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L
+-#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L
+-#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L
+-//DP0_DP_MSE_SAT_UPDATE
+-#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0
+-#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8
+-#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L
+-#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L
+-//DP0_DP_MSE_LINK_TIMING
+-#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0
+-#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10
+-#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL
+-#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L
+-//DP0_DP_MSE_MISC_CNTL
+-#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0
+-#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4
+-#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8
+-#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L
+-#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L
+-#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L
+-//DP0_DP_DPHY_BS_SR_SWAP_CNTL
+-#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0
+-#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf
+-#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10
+-#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL
+-#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L
+-#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L
+-//DP0_DP_DPHY_HBR2_PATTERN_CONTROL
+-#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0
+-#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L
+-//DP0_DP_MSE_SAT0_STATUS
+-#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0
+-#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8
+-#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10
+-#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18
+-#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L
+-#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L
+-#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L
+-#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L
+-//DP0_DP_MSE_SAT1_STATUS
+-#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0
+-#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8
+-#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10
+-#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18
+-#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L
+-#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L
+-#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L
+-#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L
+-//DP0_DP_MSE_SAT2_STATUS
+-#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0
+-#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8
+-#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10
+-#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18
+-#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L
+-#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L
+-#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L
+-#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L
+-
+-
+-// addressBlock: dce_dc_dig1_dispdec
+-//DIG1_DIG_FE_CNTL
+-#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0
+-#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4
+-#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8
+-#define DIG1_DIG_FE_CNTL__DIG_START__SHIFT 0xa
+-#define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18
+-#define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c
+-#define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e
+-#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L
+-#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L
+-#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L
+-#define DIG1_DIG_FE_CNTL__DIG_START_MASK 0x00000400L
+-#define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L
+-#define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L
+-#define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L
+-//DIG1_DIG_OUTPUT_CRC_CNTL
+-#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0
+-#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4
+-#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8
+-#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L
+-#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L
+-#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L
+-//DIG1_DIG_OUTPUT_CRC_RESULT
+-#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0
+-#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL
+-//DIG1_DIG_CLOCK_PATTERN
+-#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0
+-#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL
+-//DIG1_DIG_TEST_PATTERN
+-#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0
+-#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1
+-#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4
+-#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5
+-#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6
+-#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10
+-#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L
+-#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L
+-#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L
+-#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L
+-#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L
+-#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L
+-//DIG1_DIG_RANDOM_PATTERN_SEED
+-#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0
+-#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18
+-#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL
+-#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L
+-//DIG1_DIG_FIFO_STATUS
+-#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0
+-#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
+-#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
+-#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8
+-#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
+-#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
+-#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16
+-#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a
+-#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d
+-#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
+-#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
+-#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L
+-#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L
+-#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL
+-#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L
+-#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L
+-#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L
+-#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L
+-#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L
+-#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L
+-#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L
+-#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L
+-//DIG1_HDMI_CONTROL
+-#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0
+-#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1
+-#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2
+-#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3
+-#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4
+-#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8
+-#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9
+-#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18
+-#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c
+-#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L
+-#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L
+-#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L
+-#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L
+-#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L
+-#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L
+-#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L
+-#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L
+-#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L
+-//DIG1_HDMI_STATUS
+-#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0
+-#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10
+-#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14
+-#define DIG1_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b
+-#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L
+-#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L
+-#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L
+-#define DIG1_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L
+-//DIG1_HDMI_AUDIO_PACKET_CONTROL
+-#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4
+-#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10
+-#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L
+-#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L
+-//DIG1_HDMI_ACR_PACKET_CONTROL
+-#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0
+-#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1
+-#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4
+-#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8
+-#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc
+-#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10
+-#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f
+-#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L
+-#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L
+-#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L
+-#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L
+-#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L
+-#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L
+-#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L
+-//DIG1_HDMI_VBI_PACKET_CONTROL
+-#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0
+-#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4
+-#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5
+-#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8
+-#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9
+-#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10
+-#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L
+-#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L
+-#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L
+-#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L
+-#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L
+-#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L
+-//DIG1_HDMI_INFOFRAME_CONTROL0
+-#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x0
+-#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x1
+-#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4
+-#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5
+-#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8
+-#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9
+-#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x00000001L
+-#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x00000002L
+-#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L
+-#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L
+-#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L
+-#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L
+-//DIG1_HDMI_INFOFRAME_CONTROL1
+-#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x0
+-#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8
+-#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10
+-#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x0000003FL
+-#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L
+-#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L
+-//DIG1_HDMI_GENERIC_PACKET_CONTROL0
+-#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0
+-#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1
+-#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4
+-#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5
+-#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10
+-#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18
+-#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L
+-#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L
+-#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L
+-#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L
+-#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003F0000L
+-#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3F000000L
+-//DIG1_AFMT_INTERRUPT_STATUS
+-//DIG1_HDMI_GC
+-#define DIG1_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0
+-#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2
+-#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4
+-#define DIG1_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8
+-#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc
+-#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L
+-#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L
+-#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L
+-#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L
+-#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L
+-//DIG1_AFMT_AUDIO_PACKET_CONTROL2
+-#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0
+-#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1
+-#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8
+-#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10
+-#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18
+-#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c
+-#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L
+-#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L
+-#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L
+-#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L
+-#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L
+-#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L
+-//DIG1_AFMT_ISRC1_0
+-#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0
+-#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6
+-#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7
+-#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L
+-#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L
+-#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L
+-//DIG1_AFMT_ISRC1_1
+-#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0
+-#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8
+-#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10
+-#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18
+-#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL
+-#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L
+-#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L
+-#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L
+-//DIG1_AFMT_ISRC1_2
+-#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0
+-#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8
+-#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10
+-#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18
+-#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL
+-#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L
+-#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L
+-#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L
+-//DIG1_AFMT_ISRC1_3
+-#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0
+-#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8
+-#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10
+-#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18
+-#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL
+-#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L
+-#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L
+-#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L
+-//DIG1_AFMT_ISRC1_4
+-#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0
+-#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8
+-#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10
+-#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18
+-#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL
+-#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L
+-#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L
+-#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L
+-//DIG1_AFMT_ISRC2_0
+-#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0
+-#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8
+-#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10
+-#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18
+-#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL
+-#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L
+-#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L
+-#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L
+-//DIG1_AFMT_ISRC2_1
+-#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0
+-#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8
+-#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10
+-#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18
+-#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL
+-#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L
+-#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L
+-#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L
+-//DIG1_AFMT_ISRC2_2
+-#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0
+-#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8
+-#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10
+-#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18
+-#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL
+-#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L
+-#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L
+-#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L
+-//DIG1_AFMT_ISRC2_3
+-#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0
+-#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8
+-#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10
+-#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18
+-#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL
+-#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L
+-#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L
+-#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L
+-//DIG1_AFMT_AVI_INFO0
+-#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x0
+-#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x8
+-#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0xa
+-#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0xc
+-#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0xd
+-#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x10
+-#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x14
+-#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x16
+-#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x18
+-#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x1a
+-#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x1c
+-#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x1f
+-#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0x000000FFL
+-#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x00000300L
+-#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0x00000C00L
+-#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x00001000L
+-#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x0000E000L
+-#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0x000F0000L
+-#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x00300000L
+-#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0x00C00000L
+-#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x03000000L
+-#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0x0C000000L
+-#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000L
+-#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000L
+-//DIG1_AFMT_AVI_INFO1
+-#define DIG1_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x0
+-#define DIG1_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x8
+-#define DIG1_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0xc
+-#define DIG1_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0xe
+-#define DIG1_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x10
+-#define DIG1_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x000000FFL
+-#define DIG1_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0x00000F00L
+-#define DIG1_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x00003000L
+-#define DIG1_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0x0000C000L
+-#define DIG1_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xFFFF0000L
+-//DIG1_AFMT_AVI_INFO2
+-#define DIG1_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x0
+-#define DIG1_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x10
+-#define DIG1_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0x0000FFFFL
+-#define DIG1_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xFFFF0000L
+-//DIG1_AFMT_AVI_INFO3
+-#define DIG1_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x0
+-#define DIG1_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x18
+-#define DIG1_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0x0000FFFFL
+-#define DIG1_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xFF000000L
+-//DIG1_AFMT_MPEG_INFO0
+-#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0
+-#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8
+-#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10
+-#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18
+-#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL
+-#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L
+-#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L
+-#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L
+-//DIG1_AFMT_MPEG_INFO1
+-#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0
+-#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8
+-#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc
+-#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL
+-#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L
+-#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L
+-//DIG1_AFMT_GENERIC_HDR
+-#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0
+-#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8
+-#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10
+-#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18
+-#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL
+-#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L
+-#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L
+-#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L
+-//DIG1_AFMT_GENERIC_0
+-#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0
+-#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8
+-#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10
+-#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18
+-#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL
+-#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L
+-#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L
+-#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L
+-//DIG1_AFMT_GENERIC_1
+-#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0
+-#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8
+-#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10
+-#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18
+-#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL
+-#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L
+-#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L
+-#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L
+-//DIG1_AFMT_GENERIC_2
+-#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0
+-#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8
+-#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10
+-#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18
+-#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL
+-#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L
+-#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L
+-#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L
+-//DIG1_AFMT_GENERIC_3
+-#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0
+-#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8
+-#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10
+-#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18
+-#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL
+-#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L
+-#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L
+-#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L
+-//DIG1_AFMT_GENERIC_4
+-#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0
+-#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8
+-#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10
+-#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18
+-#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL
+-#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L
+-#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L
+-#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L
+-//DIG1_AFMT_GENERIC_5
+-#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0
+-#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8
+-#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10
+-#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18
+-#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL
+-#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L
+-#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L
+-#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L
+-//DIG1_AFMT_GENERIC_6
+-#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0
+-#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8
+-#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10
+-#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18
+-#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL
+-#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L
+-#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L
+-#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L
+-//DIG1_AFMT_GENERIC_7
+-#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0
+-#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8
+-#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10
+-#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18
+-#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL
+-#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L
+-#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L
+-#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L
+-//DIG1_HDMI_GENERIC_PACKET_CONTROL1
+-#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0
+-#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1
+-#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4
+-#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5
+-#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10
+-#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18
+-#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L
+-#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L
+-#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L
+-#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L
+-#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003F0000L
+-#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3F000000L
+-//DIG1_HDMI_ACR_32_0
+-#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc
+-#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L
+-//DIG1_HDMI_ACR_32_1
+-#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0
+-#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL
+-//DIG1_HDMI_ACR_44_0
+-#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc
+-#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L
+-//DIG1_HDMI_ACR_44_1
+-#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0
+-#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL
+-//DIG1_HDMI_ACR_48_0
+-#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc
+-#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L
+-//DIG1_HDMI_ACR_48_1
+-#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0
+-#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL
+-//DIG1_HDMI_ACR_STATUS_0
+-#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc
+-#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L
+-//DIG1_HDMI_ACR_STATUS_1
+-#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0
+-#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL
+-//DIG1_AFMT_AUDIO_INFO0
+-#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0
+-#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8
+-#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb
+-#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10
+-#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18
+-#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL
+-#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L
+-#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L
+-#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L
+-#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L
+-//DIG1_AFMT_AUDIO_INFO1
+-#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0
+-#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb
+-#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf
+-#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10
+-#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL
+-#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L
+-#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L
+-#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L
+-//DIG1_AFMT_60958_0
+-#define DIG1_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0
+-#define DIG1_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1
+-#define DIG1_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2
+-#define DIG1_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3
+-#define DIG1_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6
+-#define DIG1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8
+-#define DIG1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10
+-#define DIG1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14
+-#define DIG1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18
+-#define DIG1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c
+-#define DIG1_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
+-#define DIG1_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
+-#define DIG1_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L
+-#define DIG1_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L
+-#define DIG1_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L
+-#define DIG1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L
+-#define DIG1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L
+-#define DIG1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L
+-#define DIG1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L
+-#define DIG1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L
+-//DIG1_AFMT_60958_1
+-#define DIG1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0
+-#define DIG1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4
+-#define DIG1_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10
+-#define DIG1_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12
+-#define DIG1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14
+-#define DIG1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL
+-#define DIG1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L
+-#define DIG1_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L
+-#define DIG1_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L
+-#define DIG1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L
+-//DIG1_AFMT_AUDIO_CRC_CONTROL
+-#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0
+-#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4
+-#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8
+-#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc
+-#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10
+-#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L
+-#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L
+-#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L
+-#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L
+-#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L
+-//DIG1_AFMT_RAMP_CONTROL0
+-#define DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0
+-#define DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f
+-#define DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL
+-#define DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L
+-//DIG1_AFMT_RAMP_CONTROL1
+-#define DIG1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0
+-#define DIG1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18
+-#define DIG1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL
+-#define DIG1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L
+-//DIG1_AFMT_RAMP_CONTROL2
+-#define DIG1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0
+-#define DIG1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL
+-//DIG1_AFMT_RAMP_CONTROL3
+-#define DIG1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0
+-#define DIG1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL
+-//DIG1_AFMT_60958_2
+-#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+-#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+-#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8
+-#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc
+-#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10
+-#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14
+-#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+-#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+-#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L
+-#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L
+-#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L
+-#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L
+-//DIG1_AFMT_AUDIO_CRC_RESULT
+-#define DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0
+-#define DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8
+-#define DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L
+-#define DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L
+-//DIG1_AFMT_STATUS
+-#define DIG1_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4
+-#define DIG1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8
+-#define DIG1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18
+-#define DIG1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e
+-#define DIG1_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L
+-#define DIG1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L
+-#define DIG1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L
+-#define DIG1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L
+-//DIG1_AFMT_AUDIO_PACKET_CONTROL
+-#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0
+-#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb
+-#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc
+-#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe
+-#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17
+-#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18
+-#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a
+-#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e
+-#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L
+-#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L
+-#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L
+-#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L
+-#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L
+-#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L
+-#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L
+-#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L
+-//DIG1_AFMT_VBI_PACKET_CONTROL
+-#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x2
+-#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x3
+-#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1e
+-#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x00000004L
+-#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x00000008L
+-#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xC0000000L
+-//DIG1_AFMT_INFOFRAME_CONTROL0
+-#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6
+-#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7
+-#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa
+-#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L
+-#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L
+-#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L
+-//DIG1_AFMT_AUDIO_SRC_CONTROL
+-#define DIG1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0
+-#define DIG1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L
+-//DIG1_DIG_BE_CNTL
+-#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0
+-#define DIG1_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1
+-#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8
+-#define DIG1_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10
+-#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c
+-#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L
+-#define DIG1_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L
+-#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L
+-#define DIG1_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L
+-#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L
+-//DIG1_DIG_BE_EN_CNTL
+-#define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0
+-#define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8
+-#define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L
+-#define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L
+-//DIG1_TMDS_CNTL
+-#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0
+-#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L
+-//DIG1_TMDS_CONTROL_CHAR
+-#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0
+-#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1
+-#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2
+-#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3
+-#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L
+-#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L
+-#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L
+-#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L
+-//DIG1_TMDS_CONTROL0_FEEDBACK
+-#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0
+-#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8
+-#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L
+-#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L
+-//DIG1_TMDS_STEREOSYNC_CTL_SEL
+-#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0
+-#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L
+-//DIG1_TMDS_SYNC_CHAR_PATTERN_0_1
+-#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0
+-#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10
+-#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL
+-#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L
+-//DIG1_TMDS_SYNC_CHAR_PATTERN_2_3
+-#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0
+-#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10
+-#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL
+-#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L
+-//DIG1_TMDS_CTL_BITS
+-#define DIG1_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0
+-#define DIG1_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8
+-#define DIG1_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10
+-#define DIG1_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18
+-#define DIG1_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L
+-#define DIG1_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L
+-#define DIG1_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L
+-#define DIG1_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L
+-//DIG1_TMDS_DCBALANCER_CONTROL
+-#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0
+-#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8
+-#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10
+-#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18
+-#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L
+-#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L
+-#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L
+-#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L
+-//DIG1_TMDS_CTL0_1_GEN_CNTL
+-#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0
+-#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4
+-#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7
+-#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8
+-#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa
+-#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb
+-#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc
+-#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10
+-#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14
+-#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17
+-#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18
+-#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a
+-#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b
+-#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c
+-#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f
+-#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL
+-#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L
+-#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L
+-#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L
+-#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L
+-#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L
+-#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L
+-#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L
+-#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L
+-#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L
+-#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L
+-#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L
+-#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L
+-#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L
+-#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L
+-//DIG1_TMDS_CTL2_3_GEN_CNTL
+-#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0
+-#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4
+-#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7
+-#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8
+-#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa
+-#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb
+-#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc
+-#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10
+-#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14
+-#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17
+-#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18
+-#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a
+-#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b
+-#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c
+-#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL
+-#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L
+-#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L
+-#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L
+-#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L
+-#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L
+-#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L
+-#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L
+-#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L
+-#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L
+-#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L
+-#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L
+-#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L
+-#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L
+-//DIG1_DIG_VERSION
+-#define DIG1_DIG_VERSION__DIG_TYPE__SHIFT 0x0
+-#define DIG1_DIG_VERSION__DIG_TYPE_MASK 0x00000001L
+-//DIG1_DIG_LANE_ENABLE
+-#define DIG1_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0
+-#define DIG1_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1
+-#define DIG1_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2
+-#define DIG1_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3
+-#define DIG1_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8
+-#define DIG1_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L
+-#define DIG1_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L
+-#define DIG1_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L
+-#define DIG1_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L
+-#define DIG1_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L
+-//DIG1_AFMT_CNTL
+-#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0
+-#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8
+-#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L
+-#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L
+-
+-
+-// addressBlock: dce_dc_dp1_dispdec
+-//DP1_DP_LINK_CNTL
+-#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4
+-#define DP1_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8
+-#define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11
+-#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L
+-#define DP1_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L
+-#define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L
+-//DP1_DP_PIXEL_FORMAT
+-#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0
+-#define DP1_DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x8
+-#define DP1_DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x10
+-#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18
+-#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L
+-#define DP1_DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x00000100L
+-#define DP1_DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x00010000L
+-#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L
+-//DP1_DP_MSA_COLORIMETRY
+-#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x0
+-#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x8
+-#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE__SHIFT 0x9
+-#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE__SHIFT 0x11
+-#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0x000000FFL
+-#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x00000100L
+-#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_MASK 0x00000200L
+-#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE_MASK 0x00020000L
+-//DP1_DP_CONFIG
+-#define DP1_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0
+-#define DP1_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L
+-//DP1_DP_VID_STREAM_CNTL
+-#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0
+-#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8
+-#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10
+-#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14
+-#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L
+-#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L
+-#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L
+-#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L
+-//DP1_DP_STEER_FIFO
+-#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0
+-#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4
+-#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5
+-#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6
+-#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7
+-#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8
+-#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc
+-#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L
+-#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L
+-#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L
+-#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L
+-#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L
+-#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L
+-#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L
+-//DP1_DP_MSA_MISC
+-#define DP1_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x3
+-#define DP1_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8
+-#define DP1_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10
+-#define DP1_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18
+-#define DP1_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x00000078L
+-#define DP1_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L
+-#define DP1_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L
+-#define DP1_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L
+-//DP1_DP_VID_TIMING
+-#define DP1_DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x0
+-#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4
+-#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8
+-#define DP1_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN__SHIFT 0x9
+-#define DP1_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18
+-#define DP1_DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x00000001L
+-#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L
+-#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L
+-#define DP1_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN_MASK 0x00000200L
+-#define DP1_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L
+-//DP1_DP_VID_N
+-#define DP1_DP_VID_N__DP_VID_N__SHIFT 0x0
+-#define DP1_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL
+-//DP1_DP_VID_M
+-#define DP1_DP_VID_M__DP_VID_M__SHIFT 0x0
+-#define DP1_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL
+-//DP1_DP_LINK_FRAMING_CNTL
+-#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0
+-#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18
+-#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c
+-#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL
+-#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L
+-#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L
+-//DP1_DP_HBR2_EYE_PATTERN
+-#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0
+-#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L
+-//DP1_DP_VID_MSA_VBID
+-#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0
+-#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x10
+-#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18
+-#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL
+-#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x00010000L
+-#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L
+-//DP1_DP_VID_INTERRUPT_CNTL
+-#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0
+-#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1
+-#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2
+-#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L
+-#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L
+-#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L
+-//DP1_DP_DPHY_CNTL
+-#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0
+-#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1
+-#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2
+-#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3
+-#define DP1_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10
+-#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18
+-#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L
+-#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L
+-#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L
+-#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L
+-#define DP1_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L
+-#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L
+-//DP1_DP_DPHY_TRAINING_PATTERN_SEL
+-#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0
+-#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L
+-//DP1_DP_DPHY_SYM0
+-#define DP1_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0
+-#define DP1_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa
+-#define DP1_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14
+-#define DP1_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL
+-#define DP1_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L
+-#define DP1_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L
+-//DP1_DP_DPHY_SYM1
+-#define DP1_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0
+-#define DP1_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa
+-#define DP1_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14
+-#define DP1_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL
+-#define DP1_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L
+-#define DP1_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L
+-//DP1_DP_DPHY_SYM2
+-#define DP1_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0
+-#define DP1_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa
+-#define DP1_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL
+-#define DP1_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L
+-//DP1_DP_DPHY_8B10B_CNTL
+-#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8
+-#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10
+-#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18
+-#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L
+-#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L
+-#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L
+-//DP1_DP_DPHY_PRBS_CNTL
+-#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0
+-#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4
+-#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8
+-#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L
+-#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L
+-#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L
+-//DP1_DP_DPHY_SCRAM_CNTL
+-#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0
+-#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4
+-#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8
+-#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18
+-#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L
+-#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L
+-#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L
+-#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L
+-//DP1_DP_DPHY_CRC_EN
+-#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0
+-#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4
+-#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8
+-#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L
+-#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L
+-#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L
+-//DP1_DP_DPHY_CRC_CNTL
+-#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0
+-#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4
+-#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10
+-#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L
+-#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L
+-#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L
+-//DP1_DP_DPHY_CRC_RESULT
+-#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0
+-#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8
+-#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10
+-#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18
+-#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL
+-#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L
+-#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L
+-#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L
+-//DP1_DP_DPHY_CRC_MST_CNTL
+-#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0
+-#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8
+-#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL
+-#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L
+-//DP1_DP_DPHY_CRC_MST_STATUS
+-#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0
+-#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8
+-#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10
+-#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L
+-#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L
+-#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L
+-//DP1_DP_DPHY_FAST_TRAINING
+-#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0
+-#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1
+-#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2
+-#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8
+-#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14
+-#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L
+-#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L
+-#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L
+-#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L
+-#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L
+-//DP1_DP_DPHY_FAST_TRAINING_STATUS
+-#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0
+-#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4
+-#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8
+-#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc
+-#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L
+-#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L
+-#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L
+-#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L
+-//DP1_DP_MSA_V_TIMING_OVERRIDE1
+-#define DP1_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x0
+-#define DP1_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x4
+-#define DP1_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x00000001L
+-#define DP1_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x0003FFF0L
+-//DP1_DP_MSA_V_TIMING_OVERRIDE2
+-#define DP1_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x0
+-#define DP1_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x10
+-#define DP1_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x00003FFFL
+-#define DP1_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x3FFF0000L
+-//DP1_DP_SEC_CNTL
+-#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0
+-#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4
+-#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8
+-#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc
+-#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10
+-#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14
+-#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15
+-#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16
+-#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17
+-#define DP1_DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x18
+-#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c
+-#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L
+-#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L
+-#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L
+-#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L
+-#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L
+-#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L
+-#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L
+-#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L
+-#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L
+-#define DP1_DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x01000000L
+-#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L
+-//DP1_DP_SEC_CNTL1
+-#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0
+-#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4
+-#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5
+-#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6
+-#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7
+-#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10
+-#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L
+-#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L
+-#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L
+-#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L
+-#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L
+-#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L
+-//DP1_DP_SEC_FRAMING1
+-#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0
+-#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+-#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL
+-#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+-//DP1_DP_SEC_FRAMING2
+-#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0
+-#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+-#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL
+-#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+-//DP1_DP_SEC_FRAMING3
+-#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0
+-#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10
+-#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL
+-#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+-//DP1_DP_SEC_FRAMING4
+-#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14
+-#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18
+-#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c
+-#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d
+-#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L
+-#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L
+-#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L
+-#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L
+-//DP1_DP_SEC_AUD_N
+-#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0
+-#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL
+-//DP1_DP_SEC_AUD_N_READBACK
+-#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0
+-#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL
+-//DP1_DP_SEC_AUD_M
+-#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0
+-#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL
+-//DP1_DP_SEC_AUD_M_READBACK
+-#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0
+-#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL
+-//DP1_DP_SEC_TIMESTAMP
+-#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0
+-#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L
+-//DP1_DP_SEC_PACKET_CNTL
+-#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1
+-#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4
+-#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8
+-#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10
+-#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL
+-#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L
+-#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L
+-#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L
+-//DP1_DP_MSE_RATE_CNTL
+-#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0
+-#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a
+-#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL
+-#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L
+-//DP1_DP_MSE_RATE_UPDATE
+-#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0
+-#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L
+-//DP1_DP_MSE_SAT0
+-#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0
+-#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8
+-#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10
+-#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18
+-#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L
+-#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L
+-#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L
+-#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L
+-//DP1_DP_MSE_SAT1
+-#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0
+-#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8
+-#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10
+-#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18
+-#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L
+-#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L
+-#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L
+-#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L
+-//DP1_DP_MSE_SAT2
+-#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0
+-#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8
+-#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10
+-#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18
+-#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L
+-#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L
+-#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L
+-#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L
+-//DP1_DP_MSE_SAT_UPDATE
+-#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0
+-#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8
+-#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L
+-#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L
+-//DP1_DP_MSE_LINK_TIMING
+-#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0
+-#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10
+-#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL
+-#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L
+-//DP1_DP_MSE_MISC_CNTL
+-#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0
+-#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4
+-#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8
+-#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L
+-#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L
+-#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L
+-//DP1_DP_DPHY_BS_SR_SWAP_CNTL
+-#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0
+-#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf
+-#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10
+-#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL
+-#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L
+-#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L
+-//DP1_DP_DPHY_HBR2_PATTERN_CONTROL
+-#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0
+-#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L
+-//DP1_DP_MSE_SAT0_STATUS
+-#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0
+-#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8
+-#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10
+-#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18
+-#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L
+-#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L
+-#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L
+-#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L
+-//DP1_DP_MSE_SAT1_STATUS
+-#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0
+-#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8
+-#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10
+-#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18
+-#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L
+-#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L
+-#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L
+-#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L
+-//DP1_DP_MSE_SAT2_STATUS
+-#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0
+-#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8
+-#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10
+-#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18
+-#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L
+-#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L
+-#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L
+-#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L
+-
+-
+-// addressBlock: dce_dc_dig2_dispdec
+-//DIG2_DIG_FE_CNTL
+-#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0
+-#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4
+-#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8
+-#define DIG2_DIG_FE_CNTL__DIG_START__SHIFT 0xa
+-#define DIG2_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18
+-#define DIG2_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c
+-#define DIG2_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e
+-#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L
+-#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L
+-#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L
+-#define DIG2_DIG_FE_CNTL__DIG_START_MASK 0x00000400L
+-#define DIG2_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L
+-#define DIG2_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L
+-#define DIG2_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L
+-//DIG2_DIG_OUTPUT_CRC_CNTL
+-#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0
+-#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4
+-#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8
+-#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L
+-#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L
+-#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L
+-//DIG2_DIG_OUTPUT_CRC_RESULT
+-#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0
+-#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL
+-//DIG2_DIG_CLOCK_PATTERN
+-#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0
+-#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL
+-//DIG2_DIG_TEST_PATTERN
+-#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0
+-#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1
+-#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4
+-#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5
+-#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6
+-#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10
+-#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L
+-#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L
+-#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L
+-#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L
+-#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L
+-#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L
+-//DIG2_DIG_RANDOM_PATTERN_SEED
+-#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0
+-#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18
+-#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL
+-#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L
+-//DIG2_DIG_FIFO_STATUS
+-#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0
+-#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
+-#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
+-#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8
+-#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
+-#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
+-#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16
+-#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a
+-#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d
+-#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
+-#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
+-#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L
+-#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L
+-#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL
+-#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L
+-#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L
+-#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L
+-#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L
+-#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L
+-#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L
+-#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L
+-#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L
+-//DIG2_HDMI_CONTROL
+-#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0
+-#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1
+-#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2
+-#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3
+-#define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4
+-#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8
+-#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9
+-#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18
+-#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c
+-#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L
+-#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L
+-#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L
+-#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L
+-#define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L
+-#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L
+-#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L
+-#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L
+-#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L
+-//DIG2_HDMI_STATUS
+-#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0
+-#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10
+-#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14
+-#define DIG2_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b
+-#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L
+-#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L
+-#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L
+-#define DIG2_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L
+-//DIG2_HDMI_AUDIO_PACKET_CONTROL
+-#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4
+-#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10
+-#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L
+-#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L
+-//DIG2_HDMI_ACR_PACKET_CONTROL
+-#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0
+-#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1
+-#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4
+-#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8
+-#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc
+-#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10
+-#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f
+-#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L
+-#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L
+-#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L
+-#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L
+-#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L
+-#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L
+-#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L
+-//DIG2_HDMI_VBI_PACKET_CONTROL
+-#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0
+-#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4
+-#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5
+-#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8
+-#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9
+-#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10
+-#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L
+-#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L
+-#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L
+-#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L
+-#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L
+-#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L
+-//DIG2_HDMI_INFOFRAME_CONTROL0
+-#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x0
+-#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x1
+-#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4
+-#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5
+-#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8
+-#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9
+-#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x00000001L
+-#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x00000002L
+-#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L
+-#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L
+-#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L
+-#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L
+-//DIG2_HDMI_INFOFRAME_CONTROL1
+-#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x0
+-#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8
+-#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10
+-#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x0000003FL
+-#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L
+-#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L
+-//DIG2_HDMI_GENERIC_PACKET_CONTROL0
+-#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0
+-#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1
+-#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4
+-#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5
+-#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10
+-#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18
+-#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L
+-#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L
+-#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L
+-#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L
+-#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003F0000L
+-#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3F000000L
+-//DIG2_AFMT_INTERRUPT_STATUS
+-//DIG2_HDMI_GC
+-#define DIG2_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0
+-#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2
+-#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4
+-#define DIG2_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8
+-#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc
+-#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L
+-#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L
+-#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L
+-#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L
+-#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L
+-//DIG2_AFMT_AUDIO_PACKET_CONTROL2
+-#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0
+-#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1
+-#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8
+-#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10
+-#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18
+-#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c
+-#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L
+-#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L
+-#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L
+-#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L
+-#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L
+-#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L
+-//DIG2_AFMT_ISRC1_0
+-#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0
+-#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6
+-#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7
+-#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L
+-#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L
+-#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L
+-//DIG2_AFMT_ISRC1_1
+-#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0
+-#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8
+-#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10
+-#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18
+-#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL
+-#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L
+-#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L
+-#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L
+-//DIG2_AFMT_ISRC1_2
+-#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0
+-#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8
+-#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10
+-#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18
+-#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL
+-#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L
+-#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L
+-#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L
+-//DIG2_AFMT_ISRC1_3
+-#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0
+-#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8
+-#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10
+-#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18
+-#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL
+-#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L
+-#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L
+-#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L
+-//DIG2_AFMT_ISRC1_4
+-#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0
+-#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8
+-#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10
+-#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18
+-#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL
+-#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L
+-#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L
+-#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L
+-//DIG2_AFMT_ISRC2_0
+-#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0
+-#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8
+-#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10
+-#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18
+-#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL
+-#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L
+-#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L
+-#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L
+-//DIG2_AFMT_ISRC2_1
+-#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0
+-#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8
+-#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10
+-#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18
+-#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL
+-#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L
+-#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L
+-#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L
+-//DIG2_AFMT_ISRC2_2
+-#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0
+-#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8
+-#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10
+-#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18
+-#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL
+-#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L
+-#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L
+-#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L
+-//DIG2_AFMT_ISRC2_3
+-#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0
+-#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8
+-#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10
+-#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18
+-#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL
+-#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L
+-#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L
+-#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L
+-//DIG2_AFMT_AVI_INFO0
+-#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x0
+-#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x8
+-#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0xa
+-#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0xc
+-#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0xd
+-#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x10
+-#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x14
+-#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x16
+-#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x18
+-#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x1a
+-#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x1c
+-#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x1f
+-#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0x000000FFL
+-#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x00000300L
+-#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0x00000C00L
+-#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x00001000L
+-#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x0000E000L
+-#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0x000F0000L
+-#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x00300000L
+-#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0x00C00000L
+-#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x03000000L
+-#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0x0C000000L
+-#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000L
+-#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000L
+-//DIG2_AFMT_AVI_INFO1
+-#define DIG2_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x0
+-#define DIG2_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x8
+-#define DIG2_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0xc
+-#define DIG2_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0xe
+-#define DIG2_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x10
+-#define DIG2_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x000000FFL
+-#define DIG2_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0x00000F00L
+-#define DIG2_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x00003000L
+-#define DIG2_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0x0000C000L
+-#define DIG2_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xFFFF0000L
+-//DIG2_AFMT_AVI_INFO2
+-#define DIG2_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x0
+-#define DIG2_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x10
+-#define DIG2_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0x0000FFFFL
+-#define DIG2_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xFFFF0000L
+-//DIG2_AFMT_AVI_INFO3
+-#define DIG2_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x0
+-#define DIG2_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x18
+-#define DIG2_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0x0000FFFFL
+-#define DIG2_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xFF000000L
+-//DIG2_AFMT_MPEG_INFO0
+-#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0
+-#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8
+-#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10
+-#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18
+-#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL
+-#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L
+-#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L
+-#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L
+-//DIG2_AFMT_MPEG_INFO1
+-#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0
+-#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8
+-#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc
+-#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL
+-#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L
+-#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L
+-//DIG2_AFMT_GENERIC_HDR
+-#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0
+-#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8
+-#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10
+-#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18
+-#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL
+-#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L
+-#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L
+-#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L
+-//DIG2_AFMT_GENERIC_0
+-#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0
+-#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8
+-#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10
+-#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18
+-#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL
+-#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L
+-#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L
+-#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L
+-//DIG2_AFMT_GENERIC_1
+-#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0
+-#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8
+-#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10
+-#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18
+-#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL
+-#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L
+-#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L
+-#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L
+-//DIG2_AFMT_GENERIC_2
+-#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0
+-#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8
+-#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10
+-#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18
+-#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL
+-#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L
+-#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L
+-#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L
+-//DIG2_AFMT_GENERIC_3
+-#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0
+-#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8
+-#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10
+-#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18
+-#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL
+-#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L
+-#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L
+-#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L
+-//DIG2_AFMT_GENERIC_4
+-#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0
+-#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8
+-#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10
+-#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18
+-#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL
+-#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L
+-#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L
+-#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L
+-//DIG2_AFMT_GENERIC_5
+-#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0
+-#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8
+-#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10
+-#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18
+-#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL
+-#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L
+-#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L
+-#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L
+-//DIG2_AFMT_GENERIC_6
+-#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0
+-#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8
+-#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10
+-#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18
+-#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL
+-#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L
+-#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L
+-#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L
+-//DIG2_AFMT_GENERIC_7
+-#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0
+-#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8
+-#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10
+-#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18
+-#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL
+-#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L
+-#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L
+-#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L
+-//DIG2_HDMI_GENERIC_PACKET_CONTROL1
+-#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0
+-#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1
+-#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4
+-#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5
+-#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10
+-#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18
+-#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L
+-#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L
+-#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L
+-#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L
+-#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003F0000L
+-#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3F000000L
+-//DIG2_HDMI_ACR_32_0
+-#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc
+-#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L
+-//DIG2_HDMI_ACR_32_1
+-#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0
+-#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL
+-//DIG2_HDMI_ACR_44_0
+-#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc
+-#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L
+-//DIG2_HDMI_ACR_44_1
+-#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0
+-#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL
+-//DIG2_HDMI_ACR_48_0
+-#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc
+-#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L
+-//DIG2_HDMI_ACR_48_1
+-#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0
+-#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL
+-//DIG2_HDMI_ACR_STATUS_0
+-#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc
+-#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L
+-//DIG2_HDMI_ACR_STATUS_1
+-#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0
+-#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL
+-//DIG2_AFMT_AUDIO_INFO0
+-#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0
+-#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8
+-#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb
+-#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10
+-#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18
+-#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL
+-#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L
+-#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L
+-#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L
+-#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L
+-//DIG2_AFMT_AUDIO_INFO1
+-#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0
+-#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb
+-#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf
+-#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10
+-#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL
+-#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L
+-#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L
+-#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L
+-//DIG2_AFMT_60958_0
+-#define DIG2_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0
+-#define DIG2_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1
+-#define DIG2_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2
+-#define DIG2_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3
+-#define DIG2_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6
+-#define DIG2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8
+-#define DIG2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10
+-#define DIG2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14
+-#define DIG2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18
+-#define DIG2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c
+-#define DIG2_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
+-#define DIG2_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
+-#define DIG2_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L
+-#define DIG2_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L
+-#define DIG2_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L
+-#define DIG2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L
+-#define DIG2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L
+-#define DIG2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L
+-#define DIG2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L
+-#define DIG2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L
+-//DIG2_AFMT_60958_1
+-#define DIG2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0
+-#define DIG2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4
+-#define DIG2_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10
+-#define DIG2_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12
+-#define DIG2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14
+-#define DIG2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL
+-#define DIG2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L
+-#define DIG2_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L
+-#define DIG2_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L
+-#define DIG2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L
+-//DIG2_AFMT_AUDIO_CRC_CONTROL
+-#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0
+-#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4
+-#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8
+-#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc
+-#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10
+-#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L
+-#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L
+-#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L
+-#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L
+-#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L
+-//DIG2_AFMT_RAMP_CONTROL0
+-#define DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0
+-#define DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f
+-#define DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL
+-#define DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L
+-//DIG2_AFMT_RAMP_CONTROL1
+-#define DIG2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0
+-#define DIG2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18
+-#define DIG2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL
+-#define DIG2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L
+-//DIG2_AFMT_RAMP_CONTROL2
+-#define DIG2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0
+-#define DIG2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL
+-//DIG2_AFMT_RAMP_CONTROL3
+-#define DIG2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0
+-#define DIG2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL
+-//DIG2_AFMT_60958_2
+-#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+-#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+-#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8
+-#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc
+-#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10
+-#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14
+-#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+-#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+-#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L
+-#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L
+-#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L
+-#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L
+-//DIG2_AFMT_AUDIO_CRC_RESULT
+-#define DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0
+-#define DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8
+-#define DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L
+-#define DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L
+-//DIG2_AFMT_STATUS
+-#define DIG2_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4
+-#define DIG2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8
+-#define DIG2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18
+-#define DIG2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e
+-#define DIG2_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L
+-#define DIG2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L
+-#define DIG2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L
+-#define DIG2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L
+-//DIG2_AFMT_AUDIO_PACKET_CONTROL
+-#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0
+-#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb
+-#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc
+-#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe
+-#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17
+-#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18
+-#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a
+-#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e
+-#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L
+-#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L
+-#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L
+-#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L
+-#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L
+-#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L
+-#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L
+-#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L
+-//DIG2_AFMT_VBI_PACKET_CONTROL
+-#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x2
+-#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x3
+-#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1e
+-#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x00000004L
+-#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x00000008L
+-#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xC0000000L
+-//DIG2_AFMT_INFOFRAME_CONTROL0
+-#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6
+-#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7
+-#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa
+-#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L
+-#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L
+-#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L
+-//DIG2_AFMT_AUDIO_SRC_CONTROL
+-#define DIG2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0
+-#define DIG2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L
+-//DIG2_DIG_BE_CNTL
+-#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0
+-#define DIG2_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1
+-#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8
+-#define DIG2_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10
+-#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c
+-#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L
+-#define DIG2_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L
+-#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L
+-#define DIG2_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L
+-#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L
+-//DIG2_DIG_BE_EN_CNTL
+-#define DIG2_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0
+-#define DIG2_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8
+-#define DIG2_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L
+-#define DIG2_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L
+-//DIG2_TMDS_CNTL
+-#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0
+-#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L
+-//DIG2_TMDS_CONTROL_CHAR
+-#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0
+-#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1
+-#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2
+-#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3
+-#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L
+-#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L
+-#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L
+-#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L
+-//DIG2_TMDS_CONTROL0_FEEDBACK
+-#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0
+-#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8
+-#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L
+-#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L
+-//DIG2_TMDS_STEREOSYNC_CTL_SEL
+-#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0
+-#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L
+-//DIG2_TMDS_SYNC_CHAR_PATTERN_0_1
+-#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0
+-#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10
+-#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL
+-#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L
+-//DIG2_TMDS_SYNC_CHAR_PATTERN_2_3
+-#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0
+-#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10
+-#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL
+-#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L
+-//DIG2_TMDS_CTL_BITS
+-#define DIG2_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0
+-#define DIG2_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8
+-#define DIG2_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10
+-#define DIG2_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18
+-#define DIG2_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L
+-#define DIG2_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L
+-#define DIG2_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L
+-#define DIG2_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L
+-//DIG2_TMDS_DCBALANCER_CONTROL
+-#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0
+-#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8
+-#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10
+-#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18
+-#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L
+-#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L
+-#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L
+-#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L
+-//DIG2_TMDS_CTL0_1_GEN_CNTL
+-#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0
+-#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4
+-#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7
+-#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8
+-#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa
+-#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb
+-#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc
+-#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10
+-#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14
+-#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17
+-#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18
+-#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a
+-#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b
+-#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c
+-#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f
+-#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL
+-#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L
+-#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L
+-#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L
+-#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L
+-#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L
+-#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L
+-#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L
+-#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L
+-#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L
+-#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L
+-#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L
+-#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L
+-#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L
+-#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L
+-//DIG2_TMDS_CTL2_3_GEN_CNTL
+-#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0
+-#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4
+-#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7
+-#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8
+-#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa
+-#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb
+-#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc
+-#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10
+-#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14
+-#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17
+-#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18
+-#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a
+-#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b
+-#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c
+-#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL
+-#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L
+-#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L
+-#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L
+-#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L
+-#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L
+-#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L
+-#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L
+-#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L
+-#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L
+-#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L
+-#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L
+-#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L
+-#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L
+-//DIG2_DIG_VERSION
+-#define DIG2_DIG_VERSION__DIG_TYPE__SHIFT 0x0
+-#define DIG2_DIG_VERSION__DIG_TYPE_MASK 0x00000001L
+-//DIG2_DIG_LANE_ENABLE
+-#define DIG2_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0
+-#define DIG2_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1
+-#define DIG2_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2
+-#define DIG2_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3
+-#define DIG2_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8
+-#define DIG2_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L
+-#define DIG2_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L
+-#define DIG2_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L
+-#define DIG2_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L
+-#define DIG2_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L
+-//DIG2_AFMT_CNTL
+-#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0
+-#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8
+-#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L
+-#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L
+-
+-
+-// addressBlock: dce_dc_dp2_dispdec
+-//DP2_DP_LINK_CNTL
+-#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4
+-#define DP2_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8
+-#define DP2_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11
+-#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L
+-#define DP2_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L
+-#define DP2_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L
+-//DP2_DP_PIXEL_FORMAT
+-#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0
+-#define DP2_DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x8
+-#define DP2_DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x10
+-#define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18
+-#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L
+-#define DP2_DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x00000100L
+-#define DP2_DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x00010000L
+-#define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L
+-//DP2_DP_MSA_COLORIMETRY
+-#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x0
+-#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x8
+-#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE__SHIFT 0x9
+-#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE__SHIFT 0x11
+-#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0x000000FFL
+-#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x00000100L
+-#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_MASK 0x00000200L
+-#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE_MASK 0x00020000L
+-//DP2_DP_CONFIG
+-#define DP2_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0
+-#define DP2_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L
+-//DP2_DP_VID_STREAM_CNTL
+-#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0
+-#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8
+-#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10
+-#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14
+-#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L
+-#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L
+-#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L
+-#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L
+-//DP2_DP_STEER_FIFO
+-#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0
+-#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4
+-#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5
+-#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6
+-#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7
+-#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8
+-#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc
+-#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L
+-#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L
+-#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L
+-#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L
+-#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L
+-#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L
+-#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L
+-//DP2_DP_MSA_MISC
+-#define DP2_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x3
+-#define DP2_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8
+-#define DP2_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10
+-#define DP2_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18
+-#define DP2_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x00000078L
+-#define DP2_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L
+-#define DP2_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L
+-#define DP2_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L
+-//DP2_DP_VID_TIMING
+-#define DP2_DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x0
+-#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4
+-#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8
+-#define DP2_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN__SHIFT 0x9
+-#define DP2_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18
+-#define DP2_DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x00000001L
+-#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L
+-#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L
+-#define DP2_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN_MASK 0x00000200L
+-#define DP2_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L
+-//DP2_DP_VID_N
+-#define DP2_DP_VID_N__DP_VID_N__SHIFT 0x0
+-#define DP2_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL
+-//DP2_DP_VID_M
+-#define DP2_DP_VID_M__DP_VID_M__SHIFT 0x0
+-#define DP2_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL
+-//DP2_DP_LINK_FRAMING_CNTL
+-#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0
+-#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18
+-#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c
+-#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL
+-#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L
+-#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L
+-//DP2_DP_HBR2_EYE_PATTERN
+-#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0
+-#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L
+-//DP2_DP_VID_MSA_VBID
+-#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0
+-#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x10
+-#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18
+-#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL
+-#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x00010000L
+-#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L
+-//DP2_DP_VID_INTERRUPT_CNTL
+-#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0
+-#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1
+-#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2
+-#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L
+-#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L
+-#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L
+-//DP2_DP_DPHY_CNTL
+-#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0
+-#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1
+-#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2
+-#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3
+-#define DP2_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10
+-#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18
+-#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L
+-#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L
+-#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L
+-#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L
+-#define DP2_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L
+-#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L
+-//DP2_DP_DPHY_TRAINING_PATTERN_SEL
+-#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0
+-#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L
+-//DP2_DP_DPHY_SYM0
+-#define DP2_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0
+-#define DP2_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa
+-#define DP2_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14
+-#define DP2_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL
+-#define DP2_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L
+-#define DP2_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L
+-//DP2_DP_DPHY_SYM1
+-#define DP2_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0
+-#define DP2_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa
+-#define DP2_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14
+-#define DP2_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL
+-#define DP2_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L
+-#define DP2_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L
+-//DP2_DP_DPHY_SYM2
+-#define DP2_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0
+-#define DP2_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa
+-#define DP2_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL
+-#define DP2_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L
+-//DP2_DP_DPHY_8B10B_CNTL
+-#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8
+-#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10
+-#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18
+-#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L
+-#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L
+-#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L
+-//DP2_DP_DPHY_PRBS_CNTL
+-#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0
+-#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4
+-#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8
+-#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L
+-#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L
+-#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L
+-//DP2_DP_DPHY_SCRAM_CNTL
+-#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0
+-#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4
+-#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8
+-#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18
+-#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L
+-#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L
+-#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L
+-#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L
+-//DP2_DP_DPHY_CRC_EN
+-#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0
+-#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4
+-#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8
+-#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L
+-#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L
+-#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L
+-//DP2_DP_DPHY_CRC_CNTL
+-#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0
+-#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4
+-#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10
+-#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L
+-#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L
+-#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L
+-//DP2_DP_DPHY_CRC_RESULT
+-#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0
+-#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8
+-#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10
+-#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18
+-#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL
+-#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L
+-#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L
+-#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L
+-//DP2_DP_DPHY_CRC_MST_CNTL
+-#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0
+-#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8
+-#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL
+-#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L
+-//DP2_DP_DPHY_CRC_MST_STATUS
+-#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0
+-#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8
+-#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10
+-#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L
+-#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L
+-#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L
+-//DP2_DP_DPHY_FAST_TRAINING
+-#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0
+-#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1
+-#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2
+-#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8
+-#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14
+-#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L
+-#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L
+-#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L
+-#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L
+-#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L
+-//DP2_DP_DPHY_FAST_TRAINING_STATUS
+-#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0
+-#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4
+-#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8
+-#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc
+-#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L
+-#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L
+-#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L
+-#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L
+-//DP2_DP_MSA_V_TIMING_OVERRIDE1
+-#define DP2_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x0
+-#define DP2_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x4
+-#define DP2_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x00000001L
+-#define DP2_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x0003FFF0L
+-//DP2_DP_MSA_V_TIMING_OVERRIDE2
+-#define DP2_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x0
+-#define DP2_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x10
+-#define DP2_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x00003FFFL
+-#define DP2_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x3FFF0000L
+-//DP2_DP_SEC_CNTL
+-#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0
+-#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4
+-#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8
+-#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc
+-#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10
+-#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14
+-#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15
+-#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16
+-#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17
+-#define DP2_DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x18
+-#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c
+-#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L
+-#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L
+-#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L
+-#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L
+-#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L
+-#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L
+-#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L
+-#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L
+-#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L
+-#define DP2_DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x01000000L
+-#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L
+-//DP2_DP_SEC_CNTL1
+-#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0
+-#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4
+-#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5
+-#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6
+-#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7
+-#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10
+-#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L
+-#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L
+-#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L
+-#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L
+-#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L
+-#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L
+-//DP2_DP_SEC_FRAMING1
+-#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0
+-#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+-#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL
+-#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+-//DP2_DP_SEC_FRAMING2
+-#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0
+-#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+-#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL
+-#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+-//DP2_DP_SEC_FRAMING3
+-#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0
+-#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10
+-#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL
+-#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+-//DP2_DP_SEC_FRAMING4
+-#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14
+-#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18
+-#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c
+-#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d
+-#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L
+-#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L
+-#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L
+-#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L
+-//DP2_DP_SEC_AUD_N
+-#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0
+-#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL
+-//DP2_DP_SEC_AUD_N_READBACK
+-#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0
+-#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL
+-//DP2_DP_SEC_AUD_M
+-#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0
+-#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL
+-//DP2_DP_SEC_AUD_M_READBACK
+-#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0
+-#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL
+-//DP2_DP_SEC_TIMESTAMP
+-#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0
+-#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L
+-//DP2_DP_SEC_PACKET_CNTL
+-#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1
+-#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4
+-#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8
+-#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10
+-#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL
+-#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L
+-#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L
+-#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L
+-//DP2_DP_MSE_RATE_CNTL
+-#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0
+-#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a
+-#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL
+-#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L
+-//DP2_DP_MSE_RATE_UPDATE
+-#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0
+-#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L
+-//DP2_DP_MSE_SAT0
+-#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0
+-#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8
+-#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10
+-#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18
+-#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L
+-#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L
+-#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L
+-#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L
+-//DP2_DP_MSE_SAT1
+-#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0
+-#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8
+-#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10
+-#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18
+-#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L
+-#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L
+-#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L
+-#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L
+-//DP2_DP_MSE_SAT2
+-#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0
+-#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8
+-#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10
+-#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18
+-#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L
+-#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L
+-#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L
+-#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L
+-//DP2_DP_MSE_SAT_UPDATE
+-#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0
+-#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8
+-#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L
+-#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L
+-//DP2_DP_MSE_LINK_TIMING
+-#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0
+-#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10
+-#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL
+-#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L
+-//DP2_DP_MSE_MISC_CNTL
+-#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0
+-#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4
+-#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8
+-#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L
+-#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L
+-#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L
+-//DP2_DP_DPHY_BS_SR_SWAP_CNTL
+-#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0
+-#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf
+-#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10
+-#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL
+-#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L
+-#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L
+-//DP2_DP_DPHY_HBR2_PATTERN_CONTROL
+-#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0
+-#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L
+-//DP2_DP_MSE_SAT0_STATUS
+-#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0
+-#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8
+-#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10
+-#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18
+-#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L
+-#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L
+-#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L
+-#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L
+-//DP2_DP_MSE_SAT1_STATUS
+-#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0
+-#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8
+-#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10
+-#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18
+-#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L
+-#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L
+-#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L
+-#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L
+-//DP2_DP_MSE_SAT2_STATUS
+-#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0
+-#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8
+-#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10
+-#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18
+-#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L
+-#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L
+-#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L
+-#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L
+-
+-
+-// addressBlock: dce_dc_dig3_dispdec
+-//DIG3_DIG_FE_CNTL
+-#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0
+-#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4
+-#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8
+-#define DIG3_DIG_FE_CNTL__DIG_START__SHIFT 0xa
+-#define DIG3_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18
+-#define DIG3_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c
+-#define DIG3_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e
+-#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L
+-#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L
+-#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L
+-#define DIG3_DIG_FE_CNTL__DIG_START_MASK 0x00000400L
+-#define DIG3_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L
+-#define DIG3_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L
+-#define DIG3_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L
+-//DIG3_DIG_OUTPUT_CRC_CNTL
+-#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0
+-#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4
+-#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8
+-#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L
+-#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L
+-#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L
+-//DIG3_DIG_OUTPUT_CRC_RESULT
+-#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0
+-#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL
+-//DIG3_DIG_CLOCK_PATTERN
+-#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0
+-#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL
+-//DIG3_DIG_TEST_PATTERN
+-#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0
+-#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1
+-#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4
+-#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5
+-#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6
+-#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10
+-#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L
+-#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L
+-#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L
+-#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L
+-#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L
+-#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L
+-//DIG3_DIG_RANDOM_PATTERN_SEED
+-#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0
+-#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18
+-#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL
+-#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L
+-//DIG3_DIG_FIFO_STATUS
+-#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0
+-#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
+-#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
+-#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8
+-#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
+-#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
+-#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16
+-#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a
+-#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d
+-#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
+-#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
+-#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L
+-#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L
+-#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL
+-#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L
+-#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L
+-#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L
+-#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L
+-#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L
+-#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L
+-#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L
+-#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L
+-//DIG3_HDMI_CONTROL
+-#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0
+-#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1
+-#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2
+-#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3
+-#define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4
+-#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8
+-#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9
+-#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18
+-#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c
+-#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L
+-#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L
+-#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L
+-#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L
+-#define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L
+-#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L
+-#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L
+-#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L
+-#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L
+-//DIG3_HDMI_STATUS
+-#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0
+-#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10
+-#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14
+-#define DIG3_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b
+-#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L
+-#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L
+-#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L
+-#define DIG3_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L
+-//DIG3_HDMI_AUDIO_PACKET_CONTROL
+-#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4
+-#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10
+-#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L
+-#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L
+-//DIG3_HDMI_ACR_PACKET_CONTROL
+-#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0
+-#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1
+-#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4
+-#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8
+-#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc
+-#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10
+-#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f
+-#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L
+-#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L
+-#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L
+-#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L
+-#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L
+-#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L
+-#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L
+-//DIG3_HDMI_VBI_PACKET_CONTROL
+-#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0
+-#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4
+-#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5
+-#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8
+-#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9
+-#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10
+-#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L
+-#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L
+-#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L
+-#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L
+-#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L
+-#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L
+-//DIG3_HDMI_INFOFRAME_CONTROL0
+-#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x0
+-#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x1
+-#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4
+-#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5
+-#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8
+-#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9
+-#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x00000001L
+-#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x00000002L
+-#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L
+-#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L
+-#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L
+-#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L
+-//DIG3_HDMI_INFOFRAME_CONTROL1
+-#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x0
+-#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8
+-#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10
+-#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x0000003FL
+-#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L
+-#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L
+-//DIG3_HDMI_GENERIC_PACKET_CONTROL0
+-#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0
+-#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1
+-#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4
+-#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5
+-#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10
+-#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18
+-#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L
+-#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L
+-#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L
+-#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L
+-#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003F0000L
+-#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3F000000L
+-//DIG3_AFMT_INTERRUPT_STATUS
+-//DIG3_HDMI_GC
+-#define DIG3_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0
+-#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2
+-#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4
+-#define DIG3_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8
+-#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc
+-#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L
+-#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L
+-#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L
+-#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L
+-#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L
+-//DIG3_AFMT_AUDIO_PACKET_CONTROL2
+-#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0
+-#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1
+-#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8
+-#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10
+-#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18
+-#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c
+-#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L
+-#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L
+-#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L
+-#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L
+-#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L
+-#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L
+-//DIG3_AFMT_ISRC1_0
+-#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0
+-#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6
+-#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7
+-#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L
+-#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L
+-#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L
+-//DIG3_AFMT_ISRC1_1
+-#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0
+-#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8
+-#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10
+-#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18
+-#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL
+-#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L
+-#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L
+-#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L
+-//DIG3_AFMT_ISRC1_2
+-#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0
+-#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8
+-#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10
+-#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18
+-#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL
+-#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L
+-#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L
+-#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L
+-//DIG3_AFMT_ISRC1_3
+-#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0
+-#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8
+-#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10
+-#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18
+-#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL
+-#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L
+-#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L
+-#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L
+-//DIG3_AFMT_ISRC1_4
+-#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0
+-#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8
+-#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10
+-#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18
+-#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL
+-#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L
+-#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L
+-#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L
+-//DIG3_AFMT_ISRC2_0
+-#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0
+-#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8
+-#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10
+-#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18
+-#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL
+-#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L
+-#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L
+-#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L
+-//DIG3_AFMT_ISRC2_1
+-#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0
+-#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8
+-#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10
+-#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18
+-#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL
+-#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L
+-#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L
+-#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L
+-//DIG3_AFMT_ISRC2_2
+-#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0
+-#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8
+-#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10
+-#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18
+-#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL
+-#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L
+-#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L
+-#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L
+-//DIG3_AFMT_ISRC2_3
+-#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0
+-#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8
+-#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10
+-#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18
+-#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL
+-#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L
+-#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L
+-#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L
+-//DIG3_AFMT_AVI_INFO0
+-#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x0
+-#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x8
+-#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0xa
+-#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0xc
+-#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0xd
+-#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x10
+-#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x14
+-#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x16
+-#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x18
+-#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x1a
+-#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x1c
+-#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x1f
+-#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0x000000FFL
+-#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x00000300L
+-#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0x00000C00L
+-#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x00001000L
+-#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x0000E000L
+-#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0x000F0000L
+-#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x00300000L
+-#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0x00C00000L
+-#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x03000000L
+-#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0x0C000000L
+-#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000L
+-#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000L
+-//DIG3_AFMT_AVI_INFO1
+-#define DIG3_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x0
+-#define DIG3_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x8
+-#define DIG3_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0xc
+-#define DIG3_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0xe
+-#define DIG3_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x10
+-#define DIG3_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x000000FFL
+-#define DIG3_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0x00000F00L
+-#define DIG3_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x00003000L
+-#define DIG3_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0x0000C000L
+-#define DIG3_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xFFFF0000L
+-//DIG3_AFMT_AVI_INFO2
+-#define DIG3_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x0
+-#define DIG3_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x10
+-#define DIG3_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0x0000FFFFL
+-#define DIG3_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xFFFF0000L
+-//DIG3_AFMT_AVI_INFO3
+-#define DIG3_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x0
+-#define DIG3_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x18
+-#define DIG3_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0x0000FFFFL
+-#define DIG3_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xFF000000L
+-//DIG3_AFMT_MPEG_INFO0
+-#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0
+-#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8
+-#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10
+-#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18
+-#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL
+-#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L
+-#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L
+-#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L
+-//DIG3_AFMT_MPEG_INFO1
+-#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0
+-#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8
+-#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc
+-#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL
+-#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L
+-#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L
+-//DIG3_AFMT_GENERIC_HDR
+-#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0
+-#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8
+-#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10
+-#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18
+-#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL
+-#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L
+-#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L
+-#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L
+-//DIG3_AFMT_GENERIC_0
+-#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0
+-#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8
+-#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10
+-#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18
+-#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL
+-#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L
+-#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L
+-#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L
+-//DIG3_AFMT_GENERIC_1
+-#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0
+-#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8
+-#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10
+-#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18
+-#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL
+-#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L
+-#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L
+-#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L
+-//DIG3_AFMT_GENERIC_2
+-#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0
+-#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8
+-#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10
+-#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18
+-#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL
+-#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L
+-#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L
+-#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L
+-//DIG3_AFMT_GENERIC_3
+-#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0
+-#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8
+-#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10
+-#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18
+-#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL
+-#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L
+-#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L
+-#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L
+-//DIG3_AFMT_GENERIC_4
+-#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0
+-#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8
+-#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10
+-#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18
+-#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL
+-#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L
+-#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L
+-#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L
+-//DIG3_AFMT_GENERIC_5
+-#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0
+-#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8
+-#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10
+-#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18
+-#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL
+-#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L
+-#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L
+-#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L
+-//DIG3_AFMT_GENERIC_6
+-#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0
+-#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8
+-#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10
+-#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18
+-#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL
+-#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L
+-#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L
+-#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L
+-//DIG3_AFMT_GENERIC_7
+-#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0
+-#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8
+-#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10
+-#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18
+-#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL
+-#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L
+-#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L
+-#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L
+-//DIG3_HDMI_GENERIC_PACKET_CONTROL1
+-#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0
+-#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1
+-#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4
+-#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5
+-#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10
+-#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18
+-#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L
+-#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L
+-#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L
+-#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L
+-#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003F0000L
+-#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3F000000L
+-//DIG3_HDMI_ACR_32_0
+-#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc
+-#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L
+-//DIG3_HDMI_ACR_32_1
+-#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0
+-#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL
+-//DIG3_HDMI_ACR_44_0
+-#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc
+-#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L
+-//DIG3_HDMI_ACR_44_1
+-#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0
+-#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL
+-//DIG3_HDMI_ACR_48_0
+-#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc
+-#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L
+-//DIG3_HDMI_ACR_48_1
+-#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0
+-#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL
+-//DIG3_HDMI_ACR_STATUS_0
+-#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc
+-#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L
+-//DIG3_HDMI_ACR_STATUS_1
+-#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0
+-#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL
+-//DIG3_AFMT_AUDIO_INFO0
+-#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0
+-#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8
+-#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb
+-#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10
+-#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18
+-#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL
+-#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L
+-#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L
+-#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L
+-#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L
+-//DIG3_AFMT_AUDIO_INFO1
+-#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0
+-#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb
+-#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf
+-#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10
+-#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL
+-#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L
+-#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L
+-#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L
+-//DIG3_AFMT_60958_0
+-#define DIG3_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0
+-#define DIG3_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1
+-#define DIG3_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2
+-#define DIG3_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3
+-#define DIG3_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6
+-#define DIG3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8
+-#define DIG3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10
+-#define DIG3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14
+-#define DIG3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18
+-#define DIG3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c
+-#define DIG3_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
+-#define DIG3_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
+-#define DIG3_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L
+-#define DIG3_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L
+-#define DIG3_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L
+-#define DIG3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L
+-#define DIG3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L
+-#define DIG3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L
+-#define DIG3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L
+-#define DIG3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L
+-//DIG3_AFMT_60958_1
+-#define DIG3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0
+-#define DIG3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4
+-#define DIG3_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10
+-#define DIG3_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12
+-#define DIG3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14
+-#define DIG3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL
+-#define DIG3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L
+-#define DIG3_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L
+-#define DIG3_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L
+-#define DIG3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L
+-//DIG3_AFMT_AUDIO_CRC_CONTROL
+-#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0
+-#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4
+-#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8
+-#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc
+-#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10
+-#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L
+-#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L
+-#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L
+-#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L
+-#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L
+-//DIG3_AFMT_RAMP_CONTROL0
+-#define DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0
+-#define DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f
+-#define DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL
+-#define DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L
+-//DIG3_AFMT_RAMP_CONTROL1
+-#define DIG3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0
+-#define DIG3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18
+-#define DIG3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL
+-#define DIG3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L
+-//DIG3_AFMT_RAMP_CONTROL2
+-#define DIG3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0
+-#define DIG3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL
+-//DIG3_AFMT_RAMP_CONTROL3
+-#define DIG3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0
+-#define DIG3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL
+-//DIG3_AFMT_60958_2
+-#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+-#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+-#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8
+-#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc
+-#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10
+-#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14
+-#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+-#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+-#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L
+-#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L
+-#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L
+-#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L
+-//DIG3_AFMT_AUDIO_CRC_RESULT
+-#define DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0
+-#define DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8
+-#define DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L
+-#define DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L
+-//DIG3_AFMT_STATUS
+-#define DIG3_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4
+-#define DIG3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8
+-#define DIG3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18
+-#define DIG3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e
+-#define DIG3_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L
+-#define DIG3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L
+-#define DIG3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L
+-#define DIG3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L
+-//DIG3_AFMT_AUDIO_PACKET_CONTROL
+-#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0
+-#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb
+-#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc
+-#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe
+-#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17
+-#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18
+-#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a
+-#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e
+-#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L
+-#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L
+-#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L
+-#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L
+-#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L
+-#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L
+-#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L
+-#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L
+-//DIG3_AFMT_VBI_PACKET_CONTROL
+-#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x2
+-#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x3
+-#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1e
+-#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x00000004L
+-#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x00000008L
+-#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xC0000000L
+-//DIG3_AFMT_INFOFRAME_CONTROL0
+-#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6
+-#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7
+-#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa
+-#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L
+-#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L
+-#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L
+-//DIG3_AFMT_AUDIO_SRC_CONTROL
+-#define DIG3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0
+-#define DIG3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L
+-//DIG3_DIG_BE_CNTL
+-#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0
+-#define DIG3_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1
+-#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8
+-#define DIG3_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10
+-#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c
+-#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L
+-#define DIG3_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L
+-#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L
+-#define DIG3_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L
+-#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L
+-//DIG3_DIG_BE_EN_CNTL
+-#define DIG3_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0
+-#define DIG3_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8
+-#define DIG3_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L
+-#define DIG3_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L
+-//DIG3_TMDS_CNTL
+-#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0
+-#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L
+-//DIG3_TMDS_CONTROL_CHAR
+-#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0
+-#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1
+-#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2
+-#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3
+-#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L
+-#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L
+-#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L
+-#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L
+-//DIG3_TMDS_CONTROL0_FEEDBACK
+-#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0
+-#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8
+-#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L
+-#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L
+-//DIG3_TMDS_STEREOSYNC_CTL_SEL
+-#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0
+-#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L
+-//DIG3_TMDS_SYNC_CHAR_PATTERN_0_1
+-#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0
+-#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10
+-#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL
+-#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L
+-//DIG3_TMDS_SYNC_CHAR_PATTERN_2_3
+-#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0
+-#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10
+-#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL
+-#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L
+-//DIG3_TMDS_CTL_BITS
+-#define DIG3_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0
+-#define DIG3_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8
+-#define DIG3_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10
+-#define DIG3_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18
+-#define DIG3_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L
+-#define DIG3_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L
+-#define DIG3_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L
+-#define DIG3_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L
+-//DIG3_TMDS_DCBALANCER_CONTROL
+-#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0
+-#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8
+-#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10
+-#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18
+-#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L
+-#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L
+-#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L
+-#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L
+-//DIG3_TMDS_CTL0_1_GEN_CNTL
+-#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0
+-#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4
+-#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7
+-#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8
+-#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa
+-#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb
+-#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc
+-#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10
+-#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14
+-#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17
+-#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18
+-#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a
+-#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b
+-#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c
+-#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f
+-#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL
+-#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L
+-#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L
+-#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L
+-#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L
+-#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L
+-#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L
+-#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L
+-#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L
+-#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L
+-#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L
+-#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L
+-#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L
+-#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L
+-#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L
+-//DIG3_TMDS_CTL2_3_GEN_CNTL
+-#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0
+-#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4
+-#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7
+-#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8
+-#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa
+-#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb
+-#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc
+-#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10
+-#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14
+-#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17
+-#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18
+-#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a
+-#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b
+-#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c
+-#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL
+-#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L
+-#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L
+-#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L
+-#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L
+-#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L
+-#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L
+-#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L
+-#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L
+-#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L
+-#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L
+-#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L
+-#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L
+-#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L
+-//DIG3_DIG_VERSION
+-#define DIG3_DIG_VERSION__DIG_TYPE__SHIFT 0x0
+-#define DIG3_DIG_VERSION__DIG_TYPE_MASK 0x00000001L
+-//DIG3_DIG_LANE_ENABLE
+-#define DIG3_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0
+-#define DIG3_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1
+-#define DIG3_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2
+-#define DIG3_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3
+-#define DIG3_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8
+-#define DIG3_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L
+-#define DIG3_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L
+-#define DIG3_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L
+-#define DIG3_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L
+-#define DIG3_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L
+-//DIG3_AFMT_CNTL
+-#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0
+-#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8
+-#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L
+-#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L
+-
+-
+-// addressBlock: dce_dc_dp3_dispdec
+-//DP3_DP_LINK_CNTL
+-#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4
+-#define DP3_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8
+-#define DP3_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11
+-#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L
+-#define DP3_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L
+-#define DP3_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L
+-//DP3_DP_PIXEL_FORMAT
+-#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0
+-#define DP3_DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x8
+-#define DP3_DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x10
+-#define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18
+-#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L
+-#define DP3_DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x00000100L
+-#define DP3_DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x00010000L
+-#define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L
+-//DP3_DP_MSA_COLORIMETRY
+-#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x0
+-#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x8
+-#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE__SHIFT 0x9
+-#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE__SHIFT 0x11
+-#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0x000000FFL
+-#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x00000100L
+-#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_MASK 0x00000200L
+-#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE_MASK 0x00020000L
+-//DP3_DP_CONFIG
+-#define DP3_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0
+-#define DP3_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L
+-//DP3_DP_VID_STREAM_CNTL
+-#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0
+-#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8
+-#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10
+-#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14
+-#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L
+-#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L
+-#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L
+-#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L
+-//DP3_DP_STEER_FIFO
+-#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0
+-#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4
+-#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5
+-#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6
+-#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7
+-#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8
+-#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc
+-#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L
+-#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L
+-#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L
+-#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L
+-#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L
+-#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L
+-#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L
+-//DP3_DP_MSA_MISC
+-#define DP3_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x3
+-#define DP3_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8
+-#define DP3_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10
+-#define DP3_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18
+-#define DP3_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x00000078L
+-#define DP3_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L
+-#define DP3_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L
+-#define DP3_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L
+-//DP3_DP_VID_TIMING
+-#define DP3_DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x0
+-#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4
+-#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8
+-#define DP3_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN__SHIFT 0x9
+-#define DP3_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18
+-#define DP3_DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x00000001L
+-#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L
+-#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L
+-#define DP3_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN_MASK 0x00000200L
+-#define DP3_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L
+-//DP3_DP_VID_N
+-#define DP3_DP_VID_N__DP_VID_N__SHIFT 0x0
+-#define DP3_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL
+-//DP3_DP_VID_M
+-#define DP3_DP_VID_M__DP_VID_M__SHIFT 0x0
+-#define DP3_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL
+-//DP3_DP_LINK_FRAMING_CNTL
+-#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0
+-#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18
+-#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c
+-#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL
+-#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L
+-#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L
+-//DP3_DP_HBR2_EYE_PATTERN
+-#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0
+-#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L
+-//DP3_DP_VID_MSA_VBID
+-#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0
+-#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x10
+-#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18
+-#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL
+-#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x00010000L
+-#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L
+-//DP3_DP_VID_INTERRUPT_CNTL
+-#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0
+-#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1
+-#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2
+-#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L
+-#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L
+-#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L
+-//DP3_DP_DPHY_CNTL
+-#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0
+-#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1
+-#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2
+-#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3
+-#define DP3_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10
+-#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18
+-#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L
+-#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L
+-#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L
+-#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L
+-#define DP3_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L
+-#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L
+-//DP3_DP_DPHY_TRAINING_PATTERN_SEL
+-#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0
+-#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L
+-//DP3_DP_DPHY_SYM0
+-#define DP3_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0
+-#define DP3_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa
+-#define DP3_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14
+-#define DP3_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL
+-#define DP3_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L
+-#define DP3_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L
+-//DP3_DP_DPHY_SYM1
+-#define DP3_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0
+-#define DP3_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa
+-#define DP3_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14
+-#define DP3_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL
+-#define DP3_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L
+-#define DP3_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L
+-//DP3_DP_DPHY_SYM2
+-#define DP3_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0
+-#define DP3_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa
+-#define DP3_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL
+-#define DP3_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L
+-//DP3_DP_DPHY_8B10B_CNTL
+-#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8
+-#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10
+-#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18
+-#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L
+-#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L
+-#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L
+-//DP3_DP_DPHY_PRBS_CNTL
+-#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0
+-#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4
+-#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8
+-#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L
+-#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L
+-#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L
+-//DP3_DP_DPHY_SCRAM_CNTL
+-#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0
+-#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4
+-#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8
+-#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18
+-#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L
+-#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L
+-#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L
+-#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L
+-//DP3_DP_DPHY_CRC_EN
+-#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0
+-#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4
+-#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8
+-#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L
+-#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L
+-#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L
+-//DP3_DP_DPHY_CRC_CNTL
+-#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0
+-#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4
+-#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10
+-#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L
+-#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L
+-#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L
+-//DP3_DP_DPHY_CRC_RESULT
+-#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0
+-#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8
+-#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10
+-#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18
+-#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL
+-#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L
+-#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L
+-#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L
+-//DP3_DP_DPHY_CRC_MST_CNTL
+-#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0
+-#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8
+-#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL
+-#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L
+-//DP3_DP_DPHY_CRC_MST_STATUS
+-#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0
+-#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8
+-#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10
+-#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L
+-#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L
+-#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L
+-//DP3_DP_DPHY_FAST_TRAINING
+-#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0
+-#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1
+-#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2
+-#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8
+-#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14
+-#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L
+-#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L
+-#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L
+-#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L
+-#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L
+-//DP3_DP_DPHY_FAST_TRAINING_STATUS
+-#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0
+-#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4
+-#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8
+-#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc
+-#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L
+-#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L
+-#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L
+-#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L
+-//DP3_DP_MSA_V_TIMING_OVERRIDE1
+-#define DP3_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x0
+-#define DP3_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x4
+-#define DP3_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x00000001L
+-#define DP3_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x0003FFF0L
+-//DP3_DP_MSA_V_TIMING_OVERRIDE2
+-#define DP3_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x0
+-#define DP3_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x10
+-#define DP3_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x00003FFFL
+-#define DP3_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x3FFF0000L
+-//DP3_DP_SEC_CNTL
+-#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0
+-#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4
+-#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8
+-#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc
+-#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10
+-#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14
+-#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15
+-#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16
+-#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17
+-#define DP3_DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x18
+-#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c
+-#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L
+-#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L
+-#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L
+-#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L
+-#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L
+-#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L
+-#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L
+-#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L
+-#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L
+-#define DP3_DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x01000000L
+-#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L
+-//DP3_DP_SEC_CNTL1
+-#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0
+-#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4
+-#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5
+-#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6
+-#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7
+-#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10
+-#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L
+-#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L
+-#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L
+-#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L
+-#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L
+-#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L
+-//DP3_DP_SEC_FRAMING1
+-#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0
+-#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+-#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL
+-#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+-//DP3_DP_SEC_FRAMING2
+-#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0
+-#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+-#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL
+-#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+-//DP3_DP_SEC_FRAMING3
+-#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0
+-#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10
+-#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL
+-#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+-//DP3_DP_SEC_FRAMING4
+-#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14
+-#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18
+-#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c
+-#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d
+-#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L
+-#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L
+-#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L
+-#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L
+-//DP3_DP_SEC_AUD_N
+-#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0
+-#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL
+-//DP3_DP_SEC_AUD_N_READBACK
+-#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0
+-#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL
+-//DP3_DP_SEC_AUD_M
+-#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0
+-#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL
+-//DP3_DP_SEC_AUD_M_READBACK
+-#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0
+-#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL
+-//DP3_DP_SEC_TIMESTAMP
+-#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0
+-#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L
+-//DP3_DP_SEC_PACKET_CNTL
+-#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1
+-#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4
+-#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8
+-#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10
+-#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL
+-#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L
+-#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L
+-#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L
+-//DP3_DP_MSE_RATE_CNTL
+-#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0
+-#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a
+-#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL
+-#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L
+-//DP3_DP_MSE_RATE_UPDATE
+-#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0
+-#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L
+-//DP3_DP_MSE_SAT0
+-#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0
+-#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8
+-#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10
+-#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18
+-#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L
+-#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L
+-#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L
+-#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L
+-//DP3_DP_MSE_SAT1
+-#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0
+-#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8
+-#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10
+-#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18
+-#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L
+-#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L
+-#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L
+-#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L
+-//DP3_DP_MSE_SAT2
+-#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0
+-#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8
+-#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10
+-#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18
+-#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L
+-#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L
+-#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L
+-#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L
+-//DP3_DP_MSE_SAT_UPDATE
+-#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0
+-#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8
+-#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L
+-#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L
+-//DP3_DP_MSE_LINK_TIMING
+-#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0
+-#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10
+-#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL
+-#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L
+-//DP3_DP_MSE_MISC_CNTL
+-#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0
+-#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4
+-#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8
+-#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L
+-#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L
+-#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L
+-//DP3_DP_DPHY_BS_SR_SWAP_CNTL
+-#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0
+-#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf
+-#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10
+-#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL
+-#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L
+-#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L
+-//DP3_DP_DPHY_HBR2_PATTERN_CONTROL
+-#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0
+-#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L
+-//DP3_DP_MSE_SAT0_STATUS
+-#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0
+-#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8
+-#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10
+-#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18
+-#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L
+-#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L
+-#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L
+-#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L
+-//DP3_DP_MSE_SAT1_STATUS
+-#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0
+-#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8
+-#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10
+-#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18
+-#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L
+-#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L
+-#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L
+-#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L
+-//DP3_DP_MSE_SAT2_STATUS
+-#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0
+-#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8
+-#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10
+-#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18
+-#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L
+-#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L
+-#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L
+-#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L
+-
+-
+-// addressBlock: dce_dc_dig4_dispdec
+-//DIG4_DIG_FE_CNTL
+-#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0
+-#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4
+-#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8
+-#define DIG4_DIG_FE_CNTL__DIG_START__SHIFT 0xa
+-#define DIG4_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18
+-#define DIG4_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c
+-#define DIG4_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e
+-#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L
+-#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L
+-#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L
+-#define DIG4_DIG_FE_CNTL__DIG_START_MASK 0x00000400L
+-#define DIG4_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L
+-#define DIG4_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L
+-#define DIG4_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L
+-//DIG4_DIG_OUTPUT_CRC_CNTL
+-#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0
+-#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4
+-#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8
+-#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L
+-#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L
+-#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L
+-//DIG4_DIG_OUTPUT_CRC_RESULT
+-#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0
+-#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL
+-//DIG4_DIG_CLOCK_PATTERN
+-#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0
+-#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL
+-//DIG4_DIG_TEST_PATTERN
+-#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0
+-#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1
+-#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4
+-#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5
+-#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6
+-#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10
+-#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L
+-#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L
+-#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L
+-#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L
+-#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L
+-#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L
+-//DIG4_DIG_RANDOM_PATTERN_SEED
+-#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0
+-#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18
+-#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL
+-#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L
+-//DIG4_DIG_FIFO_STATUS
+-#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0
+-#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
+-#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
+-#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8
+-#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
+-#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
+-#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16
+-#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a
+-#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d
+-#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
+-#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
+-#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L
+-#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L
+-#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL
+-#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L
+-#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L
+-#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L
+-#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L
+-#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L
+-#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L
+-#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L
+-#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L
+-//DIG4_HDMI_CONTROL
+-#define DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0
+-#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1
+-#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2
+-#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3
+-#define DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4
+-#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8
+-#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9
+-#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18
+-#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c
+-#define DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L
+-#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L
+-#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L
+-#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L
+-#define DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L
+-#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L
+-#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L
+-#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L
+-#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L
+-//DIG4_HDMI_STATUS
+-#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0
+-#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10
+-#define DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14
+-#define DIG4_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b
+-#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L
+-#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L
+-#define DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L
+-#define DIG4_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L
+-//DIG4_HDMI_AUDIO_PACKET_CONTROL
+-#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4
+-#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10
+-#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L
+-#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L
+-//DIG4_HDMI_ACR_PACKET_CONTROL
+-#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0
+-#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1
+-#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4
+-#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8
+-#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc
+-#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10
+-#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f
+-#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L
+-#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L
+-#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L
+-#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L
+-#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L
+-#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L
+-#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L
+-//DIG4_HDMI_VBI_PACKET_CONTROL
+-#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0
+-#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4
+-#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5
+-#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8
+-#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9
+-#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10
+-#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L
+-#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L
+-#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L
+-#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L
+-#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L
+-#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L
+-//DIG4_HDMI_INFOFRAME_CONTROL0
+-#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x0
+-#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x1
+-#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4
+-#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5
+-#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8
+-#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9
+-#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x00000001L
+-#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x00000002L
+-#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L
+-#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L
+-#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L
+-#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L
+-//DIG4_HDMI_INFOFRAME_CONTROL1
+-#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x0
+-#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8
+-#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10
+-#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x0000003FL
+-#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L
+-#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L
+-//DIG4_HDMI_GENERIC_PACKET_CONTROL0
+-#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0
+-#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1
+-#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4
+-#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5
+-#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10
+-#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18
+-#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L
+-#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L
+-#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L
+-#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L
+-#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003F0000L
+-#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3F000000L
+-//DIG4_AFMT_INTERRUPT_STATUS
+-//DIG4_HDMI_GC
+-#define DIG4_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0
+-#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2
+-#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4
+-#define DIG4_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8
+-#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc
+-#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L
+-#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L
+-#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L
+-#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L
+-#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L
+-//DIG4_AFMT_AUDIO_PACKET_CONTROL2
+-#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0
+-#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1
+-#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8
+-#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10
+-#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18
+-#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c
+-#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L
+-#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L
+-#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L
+-#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L
+-#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L
+-#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L
+-//DIG4_AFMT_ISRC1_0
+-#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0
+-#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6
+-#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7
+-#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L
+-#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L
+-#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L
+-//DIG4_AFMT_ISRC1_1
+-#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0
+-#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8
+-#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10
+-#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18
+-#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL
+-#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L
+-#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L
+-#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L
+-//DIG4_AFMT_ISRC1_2
+-#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0
+-#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8
+-#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10
+-#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18
+-#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL
+-#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L
+-#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L
+-#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L
+-//DIG4_AFMT_ISRC1_3
+-#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0
+-#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8
+-#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10
+-#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18
+-#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL
+-#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L
+-#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L
+-#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L
+-//DIG4_AFMT_ISRC1_4
+-#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0
+-#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8
+-#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10
+-#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18
+-#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL
+-#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L
+-#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L
+-#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L
+-//DIG4_AFMT_ISRC2_0
+-#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0
+-#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8
+-#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10
+-#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18
+-#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL
+-#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L
+-#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L
+-#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L
+-//DIG4_AFMT_ISRC2_1
+-#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0
+-#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8
+-#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10
+-#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18
+-#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL
+-#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L
+-#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L
+-#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L
+-//DIG4_AFMT_ISRC2_2
+-#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0
+-#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8
+-#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10
+-#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18
+-#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL
+-#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L
+-#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L
+-#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L
+-//DIG4_AFMT_ISRC2_3
+-#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0
+-#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8
+-#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10
+-#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18
+-#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL
+-#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L
+-#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L
+-#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L
+-//DIG4_AFMT_AVI_INFO0
+-#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x0
+-#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x8
+-#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0xa
+-#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0xc
+-#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0xd
+-#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x10
+-#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x14
+-#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x16
+-#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x18
+-#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x1a
+-#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x1c
+-#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x1f
+-#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0x000000FFL
+-#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x00000300L
+-#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0x00000C00L
+-#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x00001000L
+-#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x0000E000L
+-#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0x000F0000L
+-#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x00300000L
+-#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0x00C00000L
+-#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x03000000L
+-#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0x0C000000L
+-#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000L
+-#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000L
+-//DIG4_AFMT_AVI_INFO1
+-#define DIG4_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x0
+-#define DIG4_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x8
+-#define DIG4_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0xc
+-#define DIG4_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0xe
+-#define DIG4_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x10
+-#define DIG4_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x000000FFL
+-#define DIG4_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0x00000F00L
+-#define DIG4_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x00003000L
+-#define DIG4_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0x0000C000L
+-#define DIG4_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xFFFF0000L
+-//DIG4_AFMT_AVI_INFO2
+-#define DIG4_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x0
+-#define DIG4_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x10
+-#define DIG4_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0x0000FFFFL
+-#define DIG4_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xFFFF0000L
+-//DIG4_AFMT_AVI_INFO3
+-#define DIG4_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x0
+-#define DIG4_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x18
+-#define DIG4_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0x0000FFFFL
+-#define DIG4_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xFF000000L
+-//DIG4_AFMT_MPEG_INFO0
+-#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0
+-#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8
+-#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10
+-#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18
+-#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL
+-#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L
+-#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L
+-#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L
+-//DIG4_AFMT_MPEG_INFO1
+-#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0
+-#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8
+-#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc
+-#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL
+-#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L
+-#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L
+-//DIG4_AFMT_GENERIC_HDR
+-#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0
+-#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8
+-#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10
+-#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18
+-#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL
+-#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L
+-#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L
+-#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L
+-//DIG4_AFMT_GENERIC_0
+-#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0
+-#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8
+-#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10
+-#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18
+-#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL
+-#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L
+-#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L
+-#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L
+-//DIG4_AFMT_GENERIC_1
+-#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0
+-#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8
+-#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10
+-#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18
+-#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL
+-#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L
+-#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L
+-#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L
+-//DIG4_AFMT_GENERIC_2
+-#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0
+-#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8
+-#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10
+-#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18
+-#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL
+-#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L
+-#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L
+-#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L
+-//DIG4_AFMT_GENERIC_3
+-#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0
+-#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8
+-#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10
+-#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18
+-#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL
+-#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L
+-#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L
+-#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L
+-//DIG4_AFMT_GENERIC_4
+-#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0
+-#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8
+-#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10
+-#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18
+-#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL
+-#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L
+-#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L
+-#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L
+-//DIG4_AFMT_GENERIC_5
+-#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0
+-#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8
+-#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10
+-#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18
+-#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL
+-#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L
+-#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L
+-#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L
+-//DIG4_AFMT_GENERIC_6
+-#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0
+-#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8
+-#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10
+-#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18
+-#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL
+-#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L
+-#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L
+-#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L
+-//DIG4_AFMT_GENERIC_7
+-#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0
+-#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8
+-#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10
+-#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18
+-#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL
+-#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L
+-#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L
+-#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L
+-//DIG4_HDMI_GENERIC_PACKET_CONTROL1
+-#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0
+-#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1
+-#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4
+-#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5
+-#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10
+-#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18
+-#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L
+-#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L
+-#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L
+-#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L
+-#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003F0000L
+-#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3F000000L
+-//DIG4_HDMI_ACR_32_0
+-#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc
+-#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L
+-//DIG4_HDMI_ACR_32_1
+-#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0
+-#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL
+-//DIG4_HDMI_ACR_44_0
+-#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc
+-#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L
+-//DIG4_HDMI_ACR_44_1
+-#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0
+-#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL
+-//DIG4_HDMI_ACR_48_0
+-#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc
+-#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L
+-//DIG4_HDMI_ACR_48_1
+-#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0
+-#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL
+-//DIG4_HDMI_ACR_STATUS_0
+-#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc
+-#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L
+-//DIG4_HDMI_ACR_STATUS_1
+-#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0
+-#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL
+-//DIG4_AFMT_AUDIO_INFO0
+-#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0
+-#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8
+-#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb
+-#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10
+-#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18
+-#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL
+-#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L
+-#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L
+-#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L
+-#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L
+-//DIG4_AFMT_AUDIO_INFO1
+-#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0
+-#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb
+-#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf
+-#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10
+-#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL
+-#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L
+-#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L
+-#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L
+-//DIG4_AFMT_60958_0
+-#define DIG4_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0
+-#define DIG4_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1
+-#define DIG4_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2
+-#define DIG4_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3
+-#define DIG4_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6
+-#define DIG4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8
+-#define DIG4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10
+-#define DIG4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14
+-#define DIG4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18
+-#define DIG4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c
+-#define DIG4_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
+-#define DIG4_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
+-#define DIG4_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L
+-#define DIG4_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L
+-#define DIG4_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L
+-#define DIG4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L
+-#define DIG4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L
+-#define DIG4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L
+-#define DIG4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L
+-#define DIG4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L
+-//DIG4_AFMT_60958_1
+-#define DIG4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0
+-#define DIG4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4
+-#define DIG4_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10
+-#define DIG4_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12
+-#define DIG4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14
+-#define DIG4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL
+-#define DIG4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L
+-#define DIG4_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L
+-#define DIG4_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L
+-#define DIG4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L
+-//DIG4_AFMT_AUDIO_CRC_CONTROL
+-#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0
+-#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4
+-#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8
+-#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc
+-#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10
+-#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L
+-#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L
+-#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L
+-#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L
+-#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L
+-//DIG4_AFMT_RAMP_CONTROL0
+-#define DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0
+-#define DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f
+-#define DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL
+-#define DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L
+-//DIG4_AFMT_RAMP_CONTROL1
+-#define DIG4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0
+-#define DIG4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18
+-#define DIG4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL
+-#define DIG4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L
+-//DIG4_AFMT_RAMP_CONTROL2
+-#define DIG4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0
+-#define DIG4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL
+-//DIG4_AFMT_RAMP_CONTROL3
+-#define DIG4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0
+-#define DIG4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL
+-//DIG4_AFMT_60958_2
+-#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+-#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+-#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8
+-#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc
+-#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10
+-#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14
+-#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+-#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+-#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L
+-#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L
+-#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L
+-#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L
+-//DIG4_AFMT_AUDIO_CRC_RESULT
+-#define DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0
+-#define DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8
+-#define DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L
+-#define DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L
+-//DIG4_AFMT_STATUS
+-#define DIG4_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4
+-#define DIG4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8
+-#define DIG4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18
+-#define DIG4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e
+-#define DIG4_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L
+-#define DIG4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L
+-#define DIG4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L
+-#define DIG4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L
+-//DIG4_AFMT_AUDIO_PACKET_CONTROL
+-#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0
+-#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb
+-#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc
+-#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe
+-#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17
+-#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18
+-#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a
+-#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e
+-#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L
+-#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L
+-#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L
+-#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L
+-#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L
+-#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L
+-#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L
+-#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L
+-//DIG4_AFMT_VBI_PACKET_CONTROL
+-#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x2
+-#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x3
+-#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1e
+-#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x00000004L
+-#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x00000008L
+-#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xC0000000L
+-//DIG4_AFMT_INFOFRAME_CONTROL0
+-#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6
+-#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7
+-#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa
+-#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L
+-#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L
+-#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L
+-//DIG4_AFMT_AUDIO_SRC_CONTROL
+-#define DIG4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0
+-#define DIG4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L
+-//DIG4_DIG_BE_CNTL
+-#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0
+-#define DIG4_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1
+-#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8
+-#define DIG4_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10
+-#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c
+-#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L
+-#define DIG4_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L
+-#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L
+-#define DIG4_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L
+-#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L
+-//DIG4_DIG_BE_EN_CNTL
+-#define DIG4_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0
+-#define DIG4_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8
+-#define DIG4_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L
+-#define DIG4_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L
+-//DIG4_TMDS_CNTL
+-#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0
+-#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L
+-//DIG4_TMDS_CONTROL_CHAR
+-#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0
+-#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1
+-#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2
+-#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3
+-#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L
+-#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L
+-#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L
+-#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L
+-//DIG4_TMDS_CONTROL0_FEEDBACK
+-#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0
+-#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8
+-#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L
+-#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L
+-//DIG4_TMDS_STEREOSYNC_CTL_SEL
+-#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0
+-#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L
+-//DIG4_TMDS_SYNC_CHAR_PATTERN_0_1
+-#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0
+-#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10
+-#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL
+-#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L
+-//DIG4_TMDS_SYNC_CHAR_PATTERN_2_3
+-#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0
+-#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10
+-#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL
+-#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L
+-//DIG4_TMDS_CTL_BITS
+-#define DIG4_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0
+-#define DIG4_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8
+-#define DIG4_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10
+-#define DIG4_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18
+-#define DIG4_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L
+-#define DIG4_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L
+-#define DIG4_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L
+-#define DIG4_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L
+-//DIG4_TMDS_DCBALANCER_CONTROL
+-#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0
+-#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8
+-#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10
+-#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18
+-#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L
+-#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L
+-#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L
+-#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L
+-//DIG4_TMDS_CTL0_1_GEN_CNTL
+-#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0
+-#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4
+-#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7
+-#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8
+-#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa
+-#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb
+-#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc
+-#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10
+-#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14
+-#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17
+-#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18
+-#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a
+-#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b
+-#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c
+-#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f
+-#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL
+-#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L
+-#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L
+-#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L
+-#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L
+-#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L
+-#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L
+-#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L
+-#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L
+-#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L
+-#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L
+-#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L
+-#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L
+-#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L
+-#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L
+-//DIG4_TMDS_CTL2_3_GEN_CNTL
+-#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0
+-#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4
+-#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7
+-#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8
+-#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa
+-#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb
+-#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc
+-#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10
+-#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14
+-#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17
+-#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18
+-#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a
+-#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b
+-#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c
+-#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL
+-#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L
+-#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L
+-#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L
+-#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L
+-#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L
+-#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L
+-#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L
+-#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L
+-#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L
+-#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L
+-#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L
+-#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L
+-#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L
+-//DIG4_DIG_VERSION
+-#define DIG4_DIG_VERSION__DIG_TYPE__SHIFT 0x0
+-#define DIG4_DIG_VERSION__DIG_TYPE_MASK 0x00000001L
+-//DIG4_DIG_LANE_ENABLE
+-#define DIG4_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0
+-#define DIG4_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1
+-#define DIG4_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2
+-#define DIG4_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3
+-#define DIG4_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8
+-#define DIG4_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L
+-#define DIG4_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L
+-#define DIG4_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L
+-#define DIG4_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L
+-#define DIG4_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L
+-//DIG4_AFMT_CNTL
+-#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0
+-#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8
+-#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L
+-#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L
+-
+-
+-// addressBlock: dce_dc_dp4_dispdec
+-//DP4_DP_LINK_CNTL
+-#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4
+-#define DP4_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8
+-#define DP4_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11
+-#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L
+-#define DP4_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L
+-#define DP4_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L
+-//DP4_DP_PIXEL_FORMAT
+-#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0
+-#define DP4_DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x8
+-#define DP4_DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x10
+-#define DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18
+-#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L
+-#define DP4_DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x00000100L
+-#define DP4_DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x00010000L
+-#define DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L
+-//DP4_DP_MSA_COLORIMETRY
+-#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x0
+-#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x8
+-#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE__SHIFT 0x9
+-#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE__SHIFT 0x11
+-#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0x000000FFL
+-#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x00000100L
+-#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_MASK 0x00000200L
+-#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE_MASK 0x00020000L
+-//DP4_DP_CONFIG
+-#define DP4_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0
+-#define DP4_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L
+-//DP4_DP_VID_STREAM_CNTL
+-#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0
+-#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8
+-#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10
+-#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14
+-#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L
+-#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L
+-#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L
+-#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L
+-//DP4_DP_STEER_FIFO
+-#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0
+-#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4
+-#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5
+-#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6
+-#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7
+-#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8
+-#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc
+-#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L
+-#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L
+-#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L
+-#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L
+-#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L
+-#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L
+-#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L
+-//DP4_DP_MSA_MISC
+-#define DP4_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x3
+-#define DP4_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8
+-#define DP4_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10
+-#define DP4_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18
+-#define DP4_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x00000078L
+-#define DP4_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L
+-#define DP4_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L
+-#define DP4_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L
+-//DP4_DP_VID_TIMING
+-#define DP4_DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x0
+-#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4
+-#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8
+-#define DP4_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN__SHIFT 0x9
+-#define DP4_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18
+-#define DP4_DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x00000001L
+-#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L
+-#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L
+-#define DP4_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN_MASK 0x00000200L
+-#define DP4_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L
+-//DP4_DP_VID_N
+-#define DP4_DP_VID_N__DP_VID_N__SHIFT 0x0
+-#define DP4_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL
+-//DP4_DP_VID_M
+-#define DP4_DP_VID_M__DP_VID_M__SHIFT 0x0
+-#define DP4_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL
+-//DP4_DP_LINK_FRAMING_CNTL
+-#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0
+-#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18
+-#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c
+-#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL
+-#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L
+-#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L
+-//DP4_DP_HBR2_EYE_PATTERN
+-#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0
+-#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L
+-//DP4_DP_VID_MSA_VBID
+-#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0
+-#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x10
+-#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18
+-#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL
+-#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x00010000L
+-#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L
+-//DP4_DP_VID_INTERRUPT_CNTL
+-#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0
+-#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1
+-#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2
+-#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L
+-#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L
+-#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L
+-//DP4_DP_DPHY_CNTL
+-#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0
+-#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1
+-#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2
+-#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3
+-#define DP4_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10
+-#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18
+-#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L
+-#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L
+-#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L
+-#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L
+-#define DP4_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L
+-#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L
+-//DP4_DP_DPHY_TRAINING_PATTERN_SEL
+-#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0
+-#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L
+-//DP4_DP_DPHY_SYM0
+-#define DP4_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0
+-#define DP4_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa
+-#define DP4_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14
+-#define DP4_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL
+-#define DP4_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L
+-#define DP4_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L
+-//DP4_DP_DPHY_SYM1
+-#define DP4_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0
+-#define DP4_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa
+-#define DP4_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14
+-#define DP4_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL
+-#define DP4_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L
+-#define DP4_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L
+-//DP4_DP_DPHY_SYM2
+-#define DP4_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0
+-#define DP4_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa
+-#define DP4_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL
+-#define DP4_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L
+-//DP4_DP_DPHY_8B10B_CNTL
+-#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8
+-#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10
+-#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18
+-#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L
+-#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L
+-#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L
+-//DP4_DP_DPHY_PRBS_CNTL
+-#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0
+-#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4
+-#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8
+-#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L
+-#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L
+-#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L
+-//DP4_DP_DPHY_SCRAM_CNTL
+-#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0
+-#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4
+-#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8
+-#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18
+-#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L
+-#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L
+-#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L
+-#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L
+-//DP4_DP_DPHY_CRC_EN
+-#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0
+-#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4
+-#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8
+-#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L
+-#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L
+-#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L
+-//DP4_DP_DPHY_CRC_CNTL
+-#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0
+-#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4
+-#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10
+-#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L
+-#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L
+-#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L
+-//DP4_DP_DPHY_CRC_RESULT
+-#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0
+-#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8
+-#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10
+-#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18
+-#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL
+-#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L
+-#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L
+-#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L
+-//DP4_DP_DPHY_CRC_MST_CNTL
+-#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0
+-#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8
+-#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL
+-#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L
+-//DP4_DP_DPHY_CRC_MST_STATUS
+-#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0
+-#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8
+-#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10
+-#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L
+-#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L
+-#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L
+-//DP4_DP_DPHY_FAST_TRAINING
+-#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0
+-#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1
+-#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2
+-#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8
+-#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14
+-#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L
+-#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L
+-#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L
+-#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L
+-#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L
+-//DP4_DP_DPHY_FAST_TRAINING_STATUS
+-#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0
+-#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4
+-#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8
+-#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc
+-#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L
+-#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L
+-#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L
+-#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L
+-//DP4_DP_MSA_V_TIMING_OVERRIDE1
+-#define DP4_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x0
+-#define DP4_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x4
+-#define DP4_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x00000001L
+-#define DP4_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x0003FFF0L
+-//DP4_DP_MSA_V_TIMING_OVERRIDE2
+-#define DP4_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x0
+-#define DP4_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x10
+-#define DP4_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x00003FFFL
+-#define DP4_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x3FFF0000L
+-//DP4_DP_SEC_CNTL
+-#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0
+-#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4
+-#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8
+-#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc
+-#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10
+-#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14
+-#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15
+-#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16
+-#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17
+-#define DP4_DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x18
+-#define DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c
+-#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L
+-#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L
+-#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L
+-#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L
+-#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L
+-#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L
+-#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L
+-#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L
+-#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L
+-#define DP4_DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x01000000L
+-#define DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L
+-//DP4_DP_SEC_CNTL1
+-#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0
+-#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4
+-#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5
+-#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6
+-#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7
+-#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10
+-#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L
+-#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L
+-#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L
+-#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L
+-#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L
+-#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L
+-//DP4_DP_SEC_FRAMING1
+-#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0
+-#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+-#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL
+-#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+-//DP4_DP_SEC_FRAMING2
+-#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0
+-#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+-#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL
+-#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+-//DP4_DP_SEC_FRAMING3
+-#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0
+-#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10
+-#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL
+-#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+-//DP4_DP_SEC_FRAMING4
+-#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14
+-#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18
+-#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c
+-#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d
+-#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L
+-#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L
+-#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L
+-#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L
+-//DP4_DP_SEC_AUD_N
+-#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0
+-#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL
+-//DP4_DP_SEC_AUD_N_READBACK
+-#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0
+-#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL
+-//DP4_DP_SEC_AUD_M
+-#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0
+-#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL
+-//DP4_DP_SEC_AUD_M_READBACK
+-#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0
+-#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL
+-//DP4_DP_SEC_TIMESTAMP
+-#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0
+-#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L
+-//DP4_DP_SEC_PACKET_CNTL
+-#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1
+-#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4
+-#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8
+-#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10
+-#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL
+-#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L
+-#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L
+-#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L
+-//DP4_DP_MSE_RATE_CNTL
+-#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0
+-#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a
+-#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL
+-#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L
+-//DP4_DP_MSE_RATE_UPDATE
+-#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0
+-#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L
+-//DP4_DP_MSE_SAT0
+-#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0
+-#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8
+-#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10
+-#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18
+-#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L
+-#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L
+-#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L
+-#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L
+-//DP4_DP_MSE_SAT1
+-#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0
+-#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8
+-#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10
+-#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18
+-#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L
+-#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L
+-#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L
+-#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L
+-//DP4_DP_MSE_SAT2
+-#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0
+-#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8
+-#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10
+-#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18
+-#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L
+-#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L
+-#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L
+-#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L
+-//DP4_DP_MSE_SAT_UPDATE
+-#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0
+-#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8
+-#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L
+-#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L
+-//DP4_DP_MSE_LINK_TIMING
+-#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0
+-#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10
+-#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL
+-#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L
+-//DP4_DP_MSE_MISC_CNTL
+-#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0
+-#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4
+-#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8
+-#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L
+-#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L
+-#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L
+-//DP4_DP_DPHY_BS_SR_SWAP_CNTL
+-#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0
+-#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf
+-#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10
+-#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL
+-#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L
+-#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L
+-//DP4_DP_DPHY_HBR2_PATTERN_CONTROL
+-#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0
+-#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L
+-//DP4_DP_MSE_SAT0_STATUS
+-#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0
+-#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8
+-#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10
+-#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18
+-#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L
+-#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L
+-#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L
+-#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L
+-//DP4_DP_MSE_SAT1_STATUS
+-#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0
+-#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8
+-#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10
+-#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18
+-#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L
+-#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L
+-#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L
+-#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L
+-//DP4_DP_MSE_SAT2_STATUS
+-#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0
+-#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8
+-#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10
+-#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18
+-#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L
+-#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L
+-#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L
+-#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L
+-
+-
+-// addressBlock: dce_dc_dig5_dispdec
+-//DIG5_DIG_FE_CNTL
+-#define DIG5_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0
+-#define DIG5_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4
+-#define DIG5_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8
+-#define DIG5_DIG_FE_CNTL__DIG_START__SHIFT 0xa
+-#define DIG5_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18
+-#define DIG5_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c
+-#define DIG5_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e
+-#define DIG5_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L
+-#define DIG5_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L
+-#define DIG5_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L
+-#define DIG5_DIG_FE_CNTL__DIG_START_MASK 0x00000400L
+-#define DIG5_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L
+-#define DIG5_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L
+-#define DIG5_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L
+-//DIG5_DIG_OUTPUT_CRC_CNTL
+-#define DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0
+-#define DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4
+-#define DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8
+-#define DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L
+-#define DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L
+-#define DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L
+-//DIG5_DIG_OUTPUT_CRC_RESULT
+-#define DIG5_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0
+-#define DIG5_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL
+-//DIG5_DIG_CLOCK_PATTERN
+-#define DIG5_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0
+-#define DIG5_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL
+-//DIG5_DIG_TEST_PATTERN
+-#define DIG5_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0
+-#define DIG5_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1
+-#define DIG5_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4
+-#define DIG5_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5
+-#define DIG5_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6
+-#define DIG5_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10
+-#define DIG5_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L
+-#define DIG5_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L
+-#define DIG5_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L
+-#define DIG5_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L
+-#define DIG5_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L
+-#define DIG5_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L
+-//DIG5_DIG_RANDOM_PATTERN_SEED
+-#define DIG5_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0
+-#define DIG5_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18
+-#define DIG5_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL
+-#define DIG5_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L
+-//DIG5_DIG_FIFO_STATUS
+-#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0
+-#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
+-#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
+-#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8
+-#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
+-#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
+-#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16
+-#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a
+-#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d
+-#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
+-#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
+-#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L
+-#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L
+-#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL
+-#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L
+-#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L
+-#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L
+-#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L
+-#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L
+-#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L
+-#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L
+-#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L
+-//DIG5_HDMI_CONTROL
+-#define DIG5_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0
+-#define DIG5_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1
+-#define DIG5_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2
+-#define DIG5_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3
+-#define DIG5_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4
+-#define DIG5_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8
+-#define DIG5_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9
+-#define DIG5_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18
+-#define DIG5_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c
+-#define DIG5_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L
+-#define DIG5_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L
+-#define DIG5_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L
+-#define DIG5_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L
+-#define DIG5_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L
+-#define DIG5_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L
+-#define DIG5_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L
+-#define DIG5_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L
+-#define DIG5_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L
+-//DIG5_HDMI_STATUS
+-#define DIG5_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0
+-#define DIG5_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10
+-#define DIG5_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14
+-#define DIG5_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b
+-#define DIG5_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L
+-#define DIG5_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L
+-#define DIG5_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L
+-#define DIG5_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L
+-//DIG5_HDMI_AUDIO_PACKET_CONTROL
+-#define DIG5_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4
+-#define DIG5_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10
+-#define DIG5_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L
+-#define DIG5_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L
+-//DIG5_HDMI_ACR_PACKET_CONTROL
+-#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0
+-#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1
+-#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4
+-#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8
+-#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc
+-#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10
+-#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f
+-#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L
+-#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L
+-#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L
+-#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L
+-#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L
+-#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L
+-#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L
+-//DIG5_HDMI_VBI_PACKET_CONTROL
+-#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0
+-#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4
+-#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5
+-#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8
+-#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9
+-#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10
+-#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L
+-#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L
+-#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L
+-#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L
+-#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L
+-#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L
+-//DIG5_HDMI_INFOFRAME_CONTROL0
+-#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x0
+-#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x1
+-#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4
+-#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5
+-#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8
+-#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9
+-#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x00000001L
+-#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x00000002L
+-#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L
+-#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L
+-#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L
+-#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L
+-//DIG5_HDMI_INFOFRAME_CONTROL1
+-#define DIG5_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x0
+-#define DIG5_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8
+-#define DIG5_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10
+-#define DIG5_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x0000003FL
+-#define DIG5_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L
+-#define DIG5_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L
+-//DIG5_HDMI_GENERIC_PACKET_CONTROL0
+-#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0
+-#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1
+-#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4
+-#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5
+-#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10
+-#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18
+-#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L
+-#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L
+-#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L
+-#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L
+-#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003F0000L
+-#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3F000000L
+-//DIG5_AFMT_INTERRUPT_STATUS
+-//DIG5_HDMI_GC
+-#define DIG5_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0
+-#define DIG5_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2
+-#define DIG5_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4
+-#define DIG5_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8
+-#define DIG5_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc
+-#define DIG5_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L
+-#define DIG5_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L
+-#define DIG5_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L
+-#define DIG5_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L
+-#define DIG5_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L
+-//DIG5_AFMT_AUDIO_PACKET_CONTROL2
+-#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0
+-#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1
+-#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8
+-#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10
+-#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18
+-#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c
+-#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L
+-#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L
+-#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L
+-#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L
+-#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L
+-#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L
+-//DIG5_AFMT_ISRC1_0
+-#define DIG5_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0
+-#define DIG5_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6
+-#define DIG5_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7
+-#define DIG5_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L
+-#define DIG5_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L
+-#define DIG5_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L
+-//DIG5_AFMT_ISRC1_1
+-#define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0
+-#define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8
+-#define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10
+-#define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18
+-#define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL
+-#define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L
+-#define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L
+-#define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L
+-//DIG5_AFMT_ISRC1_2
+-#define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0
+-#define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8
+-#define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10
+-#define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18
+-#define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL
+-#define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L
+-#define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L
+-#define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L
+-//DIG5_AFMT_ISRC1_3
+-#define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0
+-#define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8
+-#define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10
+-#define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18
+-#define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL
+-#define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L
+-#define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L
+-#define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L
+-//DIG5_AFMT_ISRC1_4
+-#define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0
+-#define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8
+-#define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10
+-#define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18
+-#define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL
+-#define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L
+-#define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L
+-#define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L
+-//DIG5_AFMT_ISRC2_0
+-#define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0
+-#define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8
+-#define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10
+-#define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18
+-#define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL
+-#define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L
+-#define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L
+-#define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L
+-//DIG5_AFMT_ISRC2_1
+-#define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0
+-#define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8
+-#define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10
+-#define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18
+-#define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL
+-#define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L
+-#define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L
+-#define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L
+-//DIG5_AFMT_ISRC2_2
+-#define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0
+-#define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8
+-#define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10
+-#define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18
+-#define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL
+-#define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L
+-#define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L
+-#define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L
+-//DIG5_AFMT_ISRC2_3
+-#define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0
+-#define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8
+-#define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10
+-#define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18
+-#define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL
+-#define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L
+-#define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L
+-#define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L
+-//DIG5_AFMT_AVI_INFO0
+-#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x0
+-#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x8
+-#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0xa
+-#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0xc
+-#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0xd
+-#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x10
+-#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x14
+-#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x16
+-#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x18
+-#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x1a
+-#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x1c
+-#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x1f
+-#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0x000000FFL
+-#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x00000300L
+-#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0x00000C00L
+-#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x00001000L
+-#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x0000E000L
+-#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0x000F0000L
+-#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x00300000L
+-#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0x00C00000L
+-#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x03000000L
+-#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0x0C000000L
+-#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000L
+-#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000L
+-//DIG5_AFMT_AVI_INFO1
+-#define DIG5_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x0
+-#define DIG5_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x8
+-#define DIG5_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0xc
+-#define DIG5_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0xe
+-#define DIG5_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x10
+-#define DIG5_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x000000FFL
+-#define DIG5_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0x00000F00L
+-#define DIG5_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x00003000L
+-#define DIG5_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0x0000C000L
+-#define DIG5_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xFFFF0000L
+-//DIG5_AFMT_AVI_INFO2
+-#define DIG5_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x0
+-#define DIG5_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x10
+-#define DIG5_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0x0000FFFFL
+-#define DIG5_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xFFFF0000L
+-//DIG5_AFMT_AVI_INFO3
+-#define DIG5_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x0
+-#define DIG5_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x18
+-#define DIG5_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0x0000FFFFL
+-#define DIG5_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xFF000000L
+-//DIG5_AFMT_MPEG_INFO0
+-#define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0
+-#define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8
+-#define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10
+-#define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18
+-#define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL
+-#define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L
+-#define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L
+-#define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L
+-//DIG5_AFMT_MPEG_INFO1
+-#define DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0
+-#define DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8
+-#define DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc
+-#define DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL
+-#define DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L
+-#define DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L
+-//DIG5_AFMT_GENERIC_HDR
+-#define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0
+-#define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8
+-#define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10
+-#define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18
+-#define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL
+-#define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L
+-#define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L
+-#define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L
+-//DIG5_AFMT_GENERIC_0
+-#define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0
+-#define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8
+-#define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10
+-#define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18
+-#define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL
+-#define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L
+-#define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L
+-#define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L
+-//DIG5_AFMT_GENERIC_1
+-#define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0
+-#define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8
+-#define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10
+-#define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18
+-#define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL
+-#define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L
+-#define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L
+-#define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L
+-//DIG5_AFMT_GENERIC_2
+-#define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0
+-#define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8
+-#define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10
+-#define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18
+-#define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL
+-#define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L
+-#define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L
+-#define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L
+-//DIG5_AFMT_GENERIC_3
+-#define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0
+-#define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8
+-#define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10
+-#define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18
+-#define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL
+-#define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L
+-#define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L
+-#define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L
+-//DIG5_AFMT_GENERIC_4
+-#define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0
+-#define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8
+-#define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10
+-#define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18
+-#define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL
+-#define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L
+-#define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L
+-#define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L
+-//DIG5_AFMT_GENERIC_5
+-#define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0
+-#define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8
+-#define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10
+-#define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18
+-#define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL
+-#define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L
+-#define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L
+-#define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L
+-//DIG5_AFMT_GENERIC_6
+-#define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0
+-#define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8
+-#define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10
+-#define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18
+-#define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL
+-#define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L
+-#define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L
+-#define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L
+-//DIG5_AFMT_GENERIC_7
+-#define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0
+-#define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8
+-#define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10
+-#define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18
+-#define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL
+-#define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L
+-#define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L
+-#define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L
+-//DIG5_HDMI_GENERIC_PACKET_CONTROL1
+-#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0
+-#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1
+-#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4
+-#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5
+-#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10
+-#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18
+-#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L
+-#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L
+-#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L
+-#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L
+-#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003F0000L
+-#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3F000000L
+-//DIG5_HDMI_ACR_32_0
+-#define DIG5_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc
+-#define DIG5_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L
+-//DIG5_HDMI_ACR_32_1
+-#define DIG5_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0
+-#define DIG5_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL
+-//DIG5_HDMI_ACR_44_0
+-#define DIG5_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc
+-#define DIG5_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L
+-//DIG5_HDMI_ACR_44_1
+-#define DIG5_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0
+-#define DIG5_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL
+-//DIG5_HDMI_ACR_48_0
+-#define DIG5_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc
+-#define DIG5_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L
+-//DIG5_HDMI_ACR_48_1
+-#define DIG5_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0
+-#define DIG5_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL
+-//DIG5_HDMI_ACR_STATUS_0
+-#define DIG5_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc
+-#define DIG5_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L
+-//DIG5_HDMI_ACR_STATUS_1
+-#define DIG5_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0
+-#define DIG5_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL
+-//DIG5_AFMT_AUDIO_INFO0
+-#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0
+-#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8
+-#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb
+-#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10
+-#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18
+-#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL
+-#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L
+-#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L
+-#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L
+-#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L
+-//DIG5_AFMT_AUDIO_INFO1
+-#define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0
+-#define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb
+-#define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf
+-#define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10
+-#define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL
+-#define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L
+-#define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L
+-#define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L
+-//DIG5_AFMT_60958_0
+-#define DIG5_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0
+-#define DIG5_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1
+-#define DIG5_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2
+-#define DIG5_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3
+-#define DIG5_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6
+-#define DIG5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8
+-#define DIG5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10
+-#define DIG5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14
+-#define DIG5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18
+-#define DIG5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c
+-#define DIG5_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
+-#define DIG5_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
+-#define DIG5_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L
+-#define DIG5_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L
+-#define DIG5_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L
+-#define DIG5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L
+-#define DIG5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L
+-#define DIG5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L
+-#define DIG5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L
+-#define DIG5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L
+-//DIG5_AFMT_60958_1
+-#define DIG5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0
+-#define DIG5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4
+-#define DIG5_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10
+-#define DIG5_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12
+-#define DIG5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14
+-#define DIG5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL
+-#define DIG5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L
+-#define DIG5_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L
+-#define DIG5_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L
+-#define DIG5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L
+-//DIG5_AFMT_AUDIO_CRC_CONTROL
+-#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0
+-#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4
+-#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8
+-#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc
+-#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10
+-#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L
+-#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L
+-#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L
+-#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L
+-#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L
+-//DIG5_AFMT_RAMP_CONTROL0
+-#define DIG5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0
+-#define DIG5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f
+-#define DIG5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL
+-#define DIG5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L
+-//DIG5_AFMT_RAMP_CONTROL1
+-#define DIG5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0
+-#define DIG5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18
+-#define DIG5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL
+-#define DIG5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L
+-//DIG5_AFMT_RAMP_CONTROL2
+-#define DIG5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0
+-#define DIG5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL
+-//DIG5_AFMT_RAMP_CONTROL3
+-#define DIG5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0
+-#define DIG5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL
+-//DIG5_AFMT_60958_2
+-#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+-#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+-#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8
+-#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc
+-#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10
+-#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14
+-#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+-#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+-#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L
+-#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L
+-#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L
+-#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L
+-//DIG5_AFMT_AUDIO_CRC_RESULT
+-#define DIG5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0
+-#define DIG5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8
+-#define DIG5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L
+-#define DIG5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L
+-//DIG5_AFMT_STATUS
+-#define DIG5_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4
+-#define DIG5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8
+-#define DIG5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18
+-#define DIG5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e
+-#define DIG5_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L
+-#define DIG5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L
+-#define DIG5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L
+-#define DIG5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L
+-//DIG5_AFMT_AUDIO_PACKET_CONTROL
+-#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0
+-#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb
+-#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc
+-#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe
+-#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17
+-#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18
+-#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a
+-#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e
+-#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L
+-#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L
+-#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L
+-#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L
+-#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L
+-#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L
+-#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L
+-#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L
+-//DIG5_AFMT_VBI_PACKET_CONTROL
+-#define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x2
+-#define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x3
+-#define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1e
+-#define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x00000004L
+-#define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x00000008L
+-#define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xC0000000L
+-//DIG5_AFMT_INFOFRAME_CONTROL0
+-#define DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6
+-#define DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7
+-#define DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa
+-#define DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L
+-#define DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L
+-#define DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L
+-//DIG5_AFMT_AUDIO_SRC_CONTROL
+-#define DIG5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0
+-#define DIG5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L
+-//DIG5_DIG_BE_CNTL
+-#define DIG5_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0
+-#define DIG5_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1
+-#define DIG5_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8
+-#define DIG5_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10
+-#define DIG5_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c
+-#define DIG5_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L
+-#define DIG5_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L
+-#define DIG5_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L
+-#define DIG5_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L
+-#define DIG5_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L
+-//DIG5_DIG_BE_EN_CNTL
+-#define DIG5_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0
+-#define DIG5_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8
+-#define DIG5_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L
+-#define DIG5_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L
+-//DIG5_TMDS_CNTL
+-#define DIG5_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0
+-#define DIG5_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L
+-//DIG5_TMDS_CONTROL_CHAR
+-#define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0
+-#define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1
+-#define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2
+-#define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3
+-#define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L
+-#define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L
+-#define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L
+-#define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L
+-//DIG5_TMDS_CONTROL0_FEEDBACK
+-#define DIG5_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0
+-#define DIG5_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8
+-#define DIG5_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L
+-#define DIG5_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L
+-//DIG5_TMDS_STEREOSYNC_CTL_SEL
+-#define DIG5_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0
+-#define DIG5_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L
+-//DIG5_TMDS_SYNC_CHAR_PATTERN_0_1
+-#define DIG5_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0
+-#define DIG5_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10
+-#define DIG5_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL
+-#define DIG5_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L
+-//DIG5_TMDS_SYNC_CHAR_PATTERN_2_3
+-#define DIG5_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0
+-#define DIG5_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10
+-#define DIG5_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL
+-#define DIG5_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L
+-//DIG5_TMDS_CTL_BITS
+-#define DIG5_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0
+-#define DIG5_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8
+-#define DIG5_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10
+-#define DIG5_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18
+-#define DIG5_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L
+-#define DIG5_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L
+-#define DIG5_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L
+-#define DIG5_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L
+-//DIG5_TMDS_DCBALANCER_CONTROL
+-#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0
+-#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8
+-#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10
+-#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18
+-#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L
+-#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L
+-#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L
+-#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L
+-//DIG5_TMDS_CTL0_1_GEN_CNTL
+-#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0
+-#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4
+-#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7
+-#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8
+-#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa
+-#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb
+-#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc
+-#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10
+-#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14
+-#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17
+-#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18
+-#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a
+-#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b
+-#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c
+-#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f
+-#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL
+-#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L
+-#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L
+-#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L
+-#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L
+-#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L
+-#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L
+-#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L
+-#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L
+-#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L
+-#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L
+-#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L
+-#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L
+-#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L
+-#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L
+-//DIG5_TMDS_CTL2_3_GEN_CNTL
+-#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0
+-#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4
+-#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7
+-#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8
+-#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa
+-#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb
+-#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc
+-#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10
+-#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14
+-#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17
+-#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18
+-#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a
+-#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b
+-#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c
+-#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL
+-#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L
+-#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L
+-#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L
+-#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L
+-#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L
+-#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L
+-#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L
+-#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L
+-#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L
+-#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L
+-#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L
+-#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L
+-#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L
+-//DIG5_DIG_VERSION
+-#define DIG5_DIG_VERSION__DIG_TYPE__SHIFT 0x0
+-#define DIG5_DIG_VERSION__DIG_TYPE_MASK 0x00000001L
+-//DIG5_DIG_LANE_ENABLE
+-#define DIG5_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0
+-#define DIG5_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1
+-#define DIG5_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2
+-#define DIG5_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3
+-#define DIG5_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8
+-#define DIG5_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L
+-#define DIG5_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L
+-#define DIG5_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L
+-#define DIG5_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L
+-#define DIG5_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L
+-//DIG5_AFMT_CNTL
+-#define DIG5_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0
+-#define DIG5_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8
+-#define DIG5_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L
+-#define DIG5_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L
+-
+-
+-// addressBlock: dce_dc_dp5_dispdec
+-//DP5_DP_LINK_CNTL
+-#define DP5_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4
+-#define DP5_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8
+-#define DP5_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11
+-#define DP5_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L
+-#define DP5_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L
+-#define DP5_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L
+-//DP5_DP_PIXEL_FORMAT
+-#define DP5_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0
+-#define DP5_DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x8
+-#define DP5_DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x10
+-#define DP5_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18
+-#define DP5_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L
+-#define DP5_DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x00000100L
+-#define DP5_DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x00010000L
+-#define DP5_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L
+-//DP5_DP_MSA_COLORIMETRY
+-#define DP5_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x0
+-#define DP5_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x8
+-#define DP5_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE__SHIFT 0x9
+-#define DP5_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE__SHIFT 0x11
+-#define DP5_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0x000000FFL
+-#define DP5_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x00000100L
+-#define DP5_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_MASK 0x00000200L
+-#define DP5_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE_MASK 0x00020000L
+-//DP5_DP_CONFIG
+-#define DP5_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0
+-#define DP5_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L
+-//DP5_DP_VID_STREAM_CNTL
+-#define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0
+-#define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8
+-#define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10
+-#define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14
+-#define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L
+-#define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L
+-#define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L
+-#define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L
+-//DP5_DP_STEER_FIFO
+-#define DP5_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0
+-#define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4
+-#define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5
+-#define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6
+-#define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7
+-#define DP5_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8
+-#define DP5_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc
+-#define DP5_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L
+-#define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L
+-#define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L
+-#define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L
+-#define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L
+-#define DP5_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L
+-#define DP5_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L
+-//DP5_DP_MSA_MISC
+-#define DP5_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x3
+-#define DP5_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8
+-#define DP5_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10
+-#define DP5_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18
+-#define DP5_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x00000078L
+-#define DP5_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L
+-#define DP5_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L
+-#define DP5_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L
+-//DP5_DP_VID_TIMING
+-#define DP5_DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x0
+-#define DP5_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4
+-#define DP5_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8
+-#define DP5_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN__SHIFT 0x9
+-#define DP5_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18
+-#define DP5_DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x00000001L
+-#define DP5_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L
+-#define DP5_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L
+-#define DP5_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN_MASK 0x00000200L
+-#define DP5_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L
+-//DP5_DP_VID_N
+-#define DP5_DP_VID_N__DP_VID_N__SHIFT 0x0
+-#define DP5_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL
+-//DP5_DP_VID_M
+-#define DP5_DP_VID_M__DP_VID_M__SHIFT 0x0
+-#define DP5_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL
+-//DP5_DP_LINK_FRAMING_CNTL
+-#define DP5_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0
+-#define DP5_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18
+-#define DP5_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c
+-#define DP5_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL
+-#define DP5_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L
+-#define DP5_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L
+-//DP5_DP_HBR2_EYE_PATTERN
+-#define DP5_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0
+-#define DP5_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L
+-//DP5_DP_VID_MSA_VBID
+-#define DP5_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0
+-#define DP5_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x10
+-#define DP5_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18
+-#define DP5_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL
+-#define DP5_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x00010000L
+-#define DP5_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L
+-//DP5_DP_VID_INTERRUPT_CNTL
+-#define DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0
+-#define DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1
+-#define DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2
+-#define DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L
+-#define DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L
+-#define DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L
+-//DP5_DP_DPHY_CNTL
+-#define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0
+-#define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1
+-#define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2
+-#define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3
+-#define DP5_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10
+-#define DP5_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18
+-#define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L
+-#define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L
+-#define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L
+-#define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L
+-#define DP5_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L
+-#define DP5_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L
+-//DP5_DP_DPHY_TRAINING_PATTERN_SEL
+-#define DP5_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0
+-#define DP5_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L
+-//DP5_DP_DPHY_SYM0
+-#define DP5_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0
+-#define DP5_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa
+-#define DP5_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14
+-#define DP5_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL
+-#define DP5_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L
+-#define DP5_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L
+-//DP5_DP_DPHY_SYM1
+-#define DP5_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0
+-#define DP5_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa
+-#define DP5_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14
+-#define DP5_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL
+-#define DP5_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L
+-#define DP5_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L
+-//DP5_DP_DPHY_SYM2
+-#define DP5_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0
+-#define DP5_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa
+-#define DP5_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL
+-#define DP5_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L
+-//DP5_DP_DPHY_8B10B_CNTL
+-#define DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8
+-#define DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10
+-#define DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18
+-#define DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L
+-#define DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L
+-#define DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L
+-//DP5_DP_DPHY_PRBS_CNTL
+-#define DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0
+-#define DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4
+-#define DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8
+-#define DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L
+-#define DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L
+-#define DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L
+-//DP5_DP_DPHY_SCRAM_CNTL
+-#define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0
+-#define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4
+-#define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8
+-#define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18
+-#define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L
+-#define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L
+-#define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L
+-#define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L
+-//DP5_DP_DPHY_CRC_EN
+-#define DP5_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0
+-#define DP5_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4
+-#define DP5_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8
+-#define DP5_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L
+-#define DP5_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L
+-#define DP5_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L
+-//DP5_DP_DPHY_CRC_CNTL
+-#define DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0
+-#define DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4
+-#define DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10
+-#define DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L
+-#define DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L
+-#define DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L
+-//DP5_DP_DPHY_CRC_RESULT
+-#define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0
+-#define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8
+-#define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10
+-#define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18
+-#define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL
+-#define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L
+-#define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L
+-#define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L
+-//DP5_DP_DPHY_CRC_MST_CNTL
+-#define DP5_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0
+-#define DP5_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8
+-#define DP5_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL
+-#define DP5_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L
+-//DP5_DP_DPHY_CRC_MST_STATUS
+-#define DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0
+-#define DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8
+-#define DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10
+-#define DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L
+-#define DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L
+-#define DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L
+-//DP5_DP_DPHY_FAST_TRAINING
+-#define DP5_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0
+-#define DP5_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1
+-#define DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2
+-#define DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8
+-#define DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14
+-#define DP5_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L
+-#define DP5_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L
+-#define DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L
+-#define DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L
+-#define DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L
+-//DP5_DP_DPHY_FAST_TRAINING_STATUS
+-#define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0
+-#define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4
+-#define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8
+-#define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc
+-#define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L
+-#define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L
+-#define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L
+-#define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L
+-//DP5_DP_MSA_V_TIMING_OVERRIDE1
+-#define DP5_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x0
+-#define DP5_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x4
+-#define DP5_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x00000001L
+-#define DP5_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x0003FFF0L
+-//DP5_DP_MSA_V_TIMING_OVERRIDE2
+-#define DP5_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x0
+-#define DP5_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x10
+-#define DP5_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x00003FFFL
+-#define DP5_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x3FFF0000L
+-//DP5_DP_SEC_CNTL
+-#define DP5_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0
+-#define DP5_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4
+-#define DP5_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8
+-#define DP5_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc
+-#define DP5_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10
+-#define DP5_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14
+-#define DP5_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15
+-#define DP5_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16
+-#define DP5_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17
+-#define DP5_DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x18
+-#define DP5_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c
+-#define DP5_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L
+-#define DP5_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L
+-#define DP5_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L
+-#define DP5_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L
+-#define DP5_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L
+-#define DP5_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L
+-#define DP5_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L
+-#define DP5_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L
+-#define DP5_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L
+-#define DP5_DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x01000000L
+-#define DP5_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L
+-//DP5_DP_SEC_CNTL1
+-#define DP5_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0
+-#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4
+-#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5
+-#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6
+-#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7
+-#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10
+-#define DP5_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L
+-#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L
+-#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L
+-#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L
+-#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L
+-#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L
+-//DP5_DP_SEC_FRAMING1
+-#define DP5_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0
+-#define DP5_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+-#define DP5_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL
+-#define DP5_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+-//DP5_DP_SEC_FRAMING2
+-#define DP5_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0
+-#define DP5_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+-#define DP5_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL
+-#define DP5_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+-//DP5_DP_SEC_FRAMING3
+-#define DP5_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0
+-#define DP5_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10
+-#define DP5_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL
+-#define DP5_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+-//DP5_DP_SEC_FRAMING4
+-#define DP5_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14
+-#define DP5_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18
+-#define DP5_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c
+-#define DP5_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d
+-#define DP5_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L
+-#define DP5_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L
+-#define DP5_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L
+-#define DP5_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L
+-//DP5_DP_SEC_AUD_N
+-#define DP5_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0
+-#define DP5_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL
+-//DP5_DP_SEC_AUD_N_READBACK
+-#define DP5_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0
+-#define DP5_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL
+-//DP5_DP_SEC_AUD_M
+-#define DP5_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0
+-#define DP5_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL
+-//DP5_DP_SEC_AUD_M_READBACK
+-#define DP5_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0
+-#define DP5_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL
+-//DP5_DP_SEC_TIMESTAMP
+-#define DP5_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0
+-#define DP5_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L
+-//DP5_DP_SEC_PACKET_CNTL
+-#define DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1
+-#define DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4
+-#define DP5_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8
+-#define DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10
+-#define DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL
+-#define DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L
+-#define DP5_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L
+-#define DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L
+-//DP5_DP_MSE_RATE_CNTL
+-#define DP5_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0
+-#define DP5_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a
+-#define DP5_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL
+-#define DP5_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L
+-//DP5_DP_MSE_RATE_UPDATE
+-#define DP5_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0
+-#define DP5_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L
+-//DP5_DP_MSE_SAT0
+-#define DP5_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0
+-#define DP5_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8
+-#define DP5_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10
+-#define DP5_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18
+-#define DP5_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L
+-#define DP5_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L
+-#define DP5_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L
+-#define DP5_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L
+-//DP5_DP_MSE_SAT1
+-#define DP5_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0
+-#define DP5_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8
+-#define DP5_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10
+-#define DP5_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18
+-#define DP5_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L
+-#define DP5_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L
+-#define DP5_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L
+-#define DP5_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L
+-//DP5_DP_MSE_SAT2
+-#define DP5_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0
+-#define DP5_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8
+-#define DP5_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10
+-#define DP5_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18
+-#define DP5_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L
+-#define DP5_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L
+-#define DP5_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L
+-#define DP5_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L
+-//DP5_DP_MSE_SAT_UPDATE
+-#define DP5_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0
+-#define DP5_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8
+-#define DP5_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L
+-#define DP5_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L
+-//DP5_DP_MSE_LINK_TIMING
+-#define DP5_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0
+-#define DP5_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10
+-#define DP5_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL
+-#define DP5_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L
+-//DP5_DP_MSE_MISC_CNTL
+-#define DP5_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0
+-#define DP5_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4
+-#define DP5_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8
+-#define DP5_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L
+-#define DP5_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L
+-#define DP5_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L
+-//DP5_DP_DPHY_BS_SR_SWAP_CNTL
+-#define DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0
+-#define DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf
+-#define DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10
+-#define DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL
+-#define DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L
+-#define DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L
+-//DP5_DP_DPHY_HBR2_PATTERN_CONTROL
+-#define DP5_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0
+-#define DP5_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L
+-//DP5_DP_MSE_SAT0_STATUS
+-#define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0
+-#define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8
+-#define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10
+-#define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18
+-#define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L
+-#define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L
+-#define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L
+-#define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L
+-//DP5_DP_MSE_SAT1_STATUS
+-#define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0
+-#define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8
+-#define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10
+-#define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18
+-#define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L
+-#define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L
+-#define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L
+-#define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L
+-//DP5_DP_MSE_SAT2_STATUS
+-#define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0
+-#define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8
+-#define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10
+-#define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18
+-#define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L
+-#define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L
+-#define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L
+-#define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L
+-
+-
+-// addressBlock: dce_dc_dig6_dispdec
+-//DIG6_DIG_FE_CNTL
+-#define DIG6_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0
+-#define DIG6_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4
+-#define DIG6_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8
+-#define DIG6_DIG_FE_CNTL__DIG_START__SHIFT 0xa
+-#define DIG6_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18
+-#define DIG6_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c
+-#define DIG6_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e
+-#define DIG6_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L
+-#define DIG6_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L
+-#define DIG6_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L
+-#define DIG6_DIG_FE_CNTL__DIG_START_MASK 0x00000400L
+-#define DIG6_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L
+-#define DIG6_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L
+-#define DIG6_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L
+-//DIG6_DIG_OUTPUT_CRC_CNTL
+-#define DIG6_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0
+-#define DIG6_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4
+-#define DIG6_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8
+-#define DIG6_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L
+-#define DIG6_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L
+-#define DIG6_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L
+-//DIG6_DIG_OUTPUT_CRC_RESULT
+-#define DIG6_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0
+-#define DIG6_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL
+-//DIG6_DIG_CLOCK_PATTERN
+-#define DIG6_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0
+-#define DIG6_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL
+-//DIG6_DIG_TEST_PATTERN
+-#define DIG6_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0
+-#define DIG6_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1
+-#define DIG6_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4
+-#define DIG6_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5
+-#define DIG6_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6
+-#define DIG6_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10
+-#define DIG6_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L
+-#define DIG6_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L
+-#define DIG6_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L
+-#define DIG6_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L
+-#define DIG6_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L
+-#define DIG6_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L
+-//DIG6_DIG_RANDOM_PATTERN_SEED
+-#define DIG6_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0
+-#define DIG6_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18
+-#define DIG6_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL
+-#define DIG6_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L
+-//DIG6_DIG_FIFO_STATUS
+-#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0
+-#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
+-#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
+-#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8
+-#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
+-#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
+-#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16
+-#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a
+-#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d
+-#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
+-#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
+-#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L
+-#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L
+-#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL
+-#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L
+-#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L
+-#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L
+-#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L
+-#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L
+-#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L
+-#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L
+-#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L
+-//DIG6_HDMI_CONTROL
+-#define DIG6_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0
+-#define DIG6_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1
+-#define DIG6_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2
+-#define DIG6_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3
+-#define DIG6_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4
+-#define DIG6_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8
+-#define DIG6_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9
+-#define DIG6_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18
+-#define DIG6_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c
+-#define DIG6_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L
+-#define DIG6_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L
+-#define DIG6_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L
+-#define DIG6_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L
+-#define DIG6_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L
+-#define DIG6_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L
+-#define DIG6_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L
+-#define DIG6_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L
+-#define DIG6_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L
+-//DIG6_HDMI_STATUS
+-#define DIG6_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0
+-#define DIG6_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10
+-#define DIG6_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14
+-#define DIG6_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b
+-#define DIG6_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L
+-#define DIG6_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L
+-#define DIG6_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L
+-#define DIG6_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L
+-//DIG6_HDMI_AUDIO_PACKET_CONTROL
+-#define DIG6_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4
+-#define DIG6_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10
+-#define DIG6_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L
+-#define DIG6_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L
+-//DIG6_HDMI_ACR_PACKET_CONTROL
+-#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0
+-#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1
+-#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4
+-#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8
+-#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc
+-#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10
+-#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f
+-#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L
+-#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L
+-#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L
+-#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L
+-#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L
+-#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L
+-#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L
+-//DIG6_HDMI_VBI_PACKET_CONTROL
+-#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0
+-#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4
+-#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5
+-#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8
+-#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9
+-#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10
+-#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L
+-#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L
+-#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L
+-#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L
+-#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L
+-#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L
+-//DIG6_HDMI_INFOFRAME_CONTROL0
+-#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x0
+-#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x1
+-#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4
+-#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5
+-#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8
+-#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9
+-#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x00000001L
+-#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x00000002L
+-#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L
+-#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L
+-#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L
+-#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L
+-//DIG6_HDMI_INFOFRAME_CONTROL1
+-#define DIG6_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x0
+-#define DIG6_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8
+-#define DIG6_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10
+-#define DIG6_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x0000003FL
+-#define DIG6_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L
+-#define DIG6_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L
+-//DIG6_HDMI_GENERIC_PACKET_CONTROL0
+-#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0
+-#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1
+-#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4
+-#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5
+-#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10
+-#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18
+-#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L
+-#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L
+-#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L
+-#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L
+-#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003F0000L
+-#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3F000000L
+-//DIG6_AFMT_INTERRUPT_STATUS
+-//DIG6_HDMI_GC
+-#define DIG6_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0
+-#define DIG6_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2
+-#define DIG6_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4
+-#define DIG6_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8
+-#define DIG6_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc
+-#define DIG6_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L
+-#define DIG6_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L
+-#define DIG6_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L
+-#define DIG6_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L
+-#define DIG6_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L
+-//DIG6_AFMT_AUDIO_PACKET_CONTROL2
+-#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0
+-#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1
+-#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8
+-#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10
+-#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18
+-#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c
+-#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L
+-#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L
+-#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L
+-#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L
+-#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L
+-#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L
+-//DIG6_AFMT_ISRC1_0
+-#define DIG6_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0
+-#define DIG6_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6
+-#define DIG6_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7
+-#define DIG6_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L
+-#define DIG6_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L
+-#define DIG6_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L
+-//DIG6_AFMT_ISRC1_1
+-#define DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0
+-#define DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8
+-#define DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10
+-#define DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18
+-#define DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL
+-#define DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L
+-#define DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L
+-#define DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L
+-//DIG6_AFMT_ISRC1_2
+-#define DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0
+-#define DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8
+-#define DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10
+-#define DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18
+-#define DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL
+-#define DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L
+-#define DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L
+-#define DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L
+-//DIG6_AFMT_ISRC1_3
+-#define DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0
+-#define DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8
+-#define DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10
+-#define DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18
+-#define DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL
+-#define DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L
+-#define DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L
+-#define DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L
+-//DIG6_AFMT_ISRC1_4
+-#define DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0
+-#define DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8
+-#define DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10
+-#define DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18
+-#define DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL
+-#define DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L
+-#define DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L
+-#define DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L
+-//DIG6_AFMT_ISRC2_0
+-#define DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0
+-#define DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8
+-#define DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10
+-#define DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18
+-#define DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL
+-#define DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L
+-#define DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L
+-#define DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L
+-//DIG6_AFMT_ISRC2_1
+-#define DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0
+-#define DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8
+-#define DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10
+-#define DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18
+-#define DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL
+-#define DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L
+-#define DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L
+-#define DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L
+-//DIG6_AFMT_ISRC2_2
+-#define DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0
+-#define DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8
+-#define DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10
+-#define DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18
+-#define DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL
+-#define DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L
+-#define DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L
+-#define DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L
+-//DIG6_AFMT_ISRC2_3
+-#define DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0
+-#define DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8
+-#define DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10
+-#define DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18
+-#define DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL
+-#define DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L
+-#define DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L
+-#define DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L
+-//DIG6_AFMT_AVI_INFO0
+-#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x0
+-#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x8
+-#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0xa
+-#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0xc
+-#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0xd
+-#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x10
+-#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x14
+-#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x16
+-#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x18
+-#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x1a
+-#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x1c
+-#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x1f
+-#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0x000000FFL
+-#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x00000300L
+-#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0x00000C00L
+-#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x00001000L
+-#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x0000E000L
+-#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0x000F0000L
+-#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x00300000L
+-#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0x00C00000L
+-#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x03000000L
+-#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0x0C000000L
+-#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000L
+-#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000L
+-//DIG6_AFMT_AVI_INFO1
+-#define DIG6_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x0
+-#define DIG6_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x8
+-#define DIG6_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0xc
+-#define DIG6_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0xe
+-#define DIG6_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x10
+-#define DIG6_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x000000FFL
+-#define DIG6_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0x00000F00L
+-#define DIG6_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x00003000L
+-#define DIG6_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0x0000C000L
+-#define DIG6_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xFFFF0000L
+-//DIG6_AFMT_AVI_INFO2
+-#define DIG6_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x0
+-#define DIG6_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x10
+-#define DIG6_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0x0000FFFFL
+-#define DIG6_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xFFFF0000L
+-//DIG6_AFMT_AVI_INFO3
+-#define DIG6_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x0
+-#define DIG6_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x18
+-#define DIG6_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0x0000FFFFL
+-#define DIG6_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xFF000000L
+-//DIG6_AFMT_MPEG_INFO0
+-#define DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0
+-#define DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8
+-#define DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10
+-#define DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18
+-#define DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL
+-#define DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L
+-#define DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L
+-#define DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L
+-//DIG6_AFMT_MPEG_INFO1
+-#define DIG6_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0
+-#define DIG6_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8
+-#define DIG6_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc
+-#define DIG6_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL
+-#define DIG6_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L
+-#define DIG6_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L
+-//DIG6_AFMT_GENERIC_HDR
+-#define DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0
+-#define DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8
+-#define DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10
+-#define DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18
+-#define DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL
+-#define DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L
+-#define DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L
+-#define DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L
+-//DIG6_AFMT_GENERIC_0
+-#define DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0
+-#define DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8
+-#define DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10
+-#define DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18
+-#define DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL
+-#define DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L
+-#define DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L
+-#define DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L
+-//DIG6_AFMT_GENERIC_1
+-#define DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0
+-#define DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8
+-#define DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10
+-#define DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18
+-#define DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL
+-#define DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L
+-#define DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L
+-#define DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L
+-//DIG6_AFMT_GENERIC_2
+-#define DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0
+-#define DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8
+-#define DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10
+-#define DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18
+-#define DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL
+-#define DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L
+-#define DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L
+-#define DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L
+-//DIG6_AFMT_GENERIC_3
+-#define DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0
+-#define DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8
+-#define DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10
+-#define DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18
+-#define DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL
+-#define DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L
+-#define DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L
+-#define DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L
+-//DIG6_AFMT_GENERIC_4
+-#define DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0
+-#define DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8
+-#define DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10
+-#define DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18
+-#define DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL
+-#define DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L
+-#define DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L
+-#define DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L
+-//DIG6_AFMT_GENERIC_5
+-#define DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0
+-#define DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8
+-#define DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10
+-#define DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18
+-#define DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL
+-#define DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L
+-#define DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L
+-#define DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L
+-//DIG6_AFMT_GENERIC_6
+-#define DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0
+-#define DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8
+-#define DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10
+-#define DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18
+-#define DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL
+-#define DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L
+-#define DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L
+-#define DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L
+-//DIG6_AFMT_GENERIC_7
+-#define DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0
+-#define DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8
+-#define DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10
+-#define DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18
+-#define DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL
+-#define DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L
+-#define DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L
+-#define DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L
+-//DIG6_HDMI_GENERIC_PACKET_CONTROL1
+-#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0
+-#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1
+-#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4
+-#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5
+-#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10
+-#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18
+-#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L
+-#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L
+-#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L
+-#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L
+-#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003F0000L
+-#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3F000000L
+-//DIG6_HDMI_ACR_32_0
+-#define DIG6_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc
+-#define DIG6_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L
+-//DIG6_HDMI_ACR_32_1
+-#define DIG6_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0
+-#define DIG6_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL
+-//DIG6_HDMI_ACR_44_0
+-#define DIG6_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc
+-#define DIG6_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L
+-//DIG6_HDMI_ACR_44_1
+-#define DIG6_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0
+-#define DIG6_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL
+-//DIG6_HDMI_ACR_48_0
+-#define DIG6_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc
+-#define DIG6_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L
+-//DIG6_HDMI_ACR_48_1
+-#define DIG6_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0
+-#define DIG6_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL
+-//DIG6_HDMI_ACR_STATUS_0
+-#define DIG6_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc
+-#define DIG6_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L
+-//DIG6_HDMI_ACR_STATUS_1
+-#define DIG6_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0
+-#define DIG6_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL
+-//DIG6_AFMT_AUDIO_INFO0
+-#define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0
+-#define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8
+-#define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb
+-#define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10
+-#define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18
+-#define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL
+-#define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L
+-#define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L
+-#define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L
+-#define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L
+-//DIG6_AFMT_AUDIO_INFO1
+-#define DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0
+-#define DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb
+-#define DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf
+-#define DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10
+-#define DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL
+-#define DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L
+-#define DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L
+-#define DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L
+-//DIG6_AFMT_60958_0
+-#define DIG6_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0
+-#define DIG6_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1
+-#define DIG6_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2
+-#define DIG6_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3
+-#define DIG6_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6
+-#define DIG6_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8
+-#define DIG6_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10
+-#define DIG6_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14
+-#define DIG6_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18
+-#define DIG6_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c
+-#define DIG6_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
+-#define DIG6_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
+-#define DIG6_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L
+-#define DIG6_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L
+-#define DIG6_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L
+-#define DIG6_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L
+-#define DIG6_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L
+-#define DIG6_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L
+-#define DIG6_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L
+-#define DIG6_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L
+-//DIG6_AFMT_60958_1
+-#define DIG6_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0
+-#define DIG6_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4
+-#define DIG6_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10
+-#define DIG6_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12
+-#define DIG6_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14
+-#define DIG6_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL
+-#define DIG6_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L
+-#define DIG6_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L
+-#define DIG6_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L
+-#define DIG6_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L
+-//DIG6_AFMT_AUDIO_CRC_CONTROL
+-#define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0
+-#define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4
+-#define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8
+-#define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc
+-#define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10
+-#define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L
+-#define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L
+-#define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L
+-#define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L
+-#define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L
+-//DIG6_AFMT_RAMP_CONTROL0
+-#define DIG6_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0
+-#define DIG6_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f
+-#define DIG6_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL
+-#define DIG6_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L
+-//DIG6_AFMT_RAMP_CONTROL1
+-#define DIG6_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0
+-#define DIG6_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18
+-#define DIG6_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL
+-#define DIG6_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L
+-//DIG6_AFMT_RAMP_CONTROL2
+-#define DIG6_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0
+-#define DIG6_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL
+-//DIG6_AFMT_RAMP_CONTROL3
+-#define DIG6_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0
+-#define DIG6_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL
+-//DIG6_AFMT_60958_2
+-#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+-#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+-#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8
+-#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc
+-#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10
+-#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14
+-#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+-#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+-#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L
+-#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L
+-#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L
+-#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L
+-//DIG6_AFMT_AUDIO_CRC_RESULT
+-#define DIG6_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0
+-#define DIG6_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8
+-#define DIG6_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L
+-#define DIG6_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L
+-//DIG6_AFMT_STATUS
+-#define DIG6_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4
+-#define DIG6_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8
+-#define DIG6_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18
+-#define DIG6_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e
+-#define DIG6_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L
+-#define DIG6_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L
+-#define DIG6_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L
+-#define DIG6_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L
+-//DIG6_AFMT_AUDIO_PACKET_CONTROL
+-#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0
+-#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb
+-#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc
+-#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe
+-#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17
+-#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18
+-#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a
+-#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e
+-#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L
+-#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L
+-#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L
+-#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L
+-#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L
+-#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L
+-#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L
+-#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L
+-//DIG6_AFMT_VBI_PACKET_CONTROL
+-#define DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x2
+-#define DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x3
+-#define DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1e
+-#define DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x00000004L
+-#define DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x00000008L
+-#define DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xC0000000L
+-//DIG6_AFMT_INFOFRAME_CONTROL0
+-#define DIG6_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6
+-#define DIG6_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7
+-#define DIG6_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa
+-#define DIG6_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L
+-#define DIG6_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L
+-#define DIG6_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L
+-//DIG6_AFMT_AUDIO_SRC_CONTROL
+-#define DIG6_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0
+-#define DIG6_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L
+-//DIG6_DIG_BE_CNTL
+-#define DIG6_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0
+-#define DIG6_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1
+-#define DIG6_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8
+-#define DIG6_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10
+-#define DIG6_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c
+-#define DIG6_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L
+-#define DIG6_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L
+-#define DIG6_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L
+-#define DIG6_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L
+-#define DIG6_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L
+-//DIG6_DIG_BE_EN_CNTL
+-#define DIG6_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0
+-#define DIG6_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8
+-#define DIG6_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L
+-#define DIG6_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L
+-//DIG6_TMDS_CNTL
+-#define DIG6_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0
+-#define DIG6_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L
+-//DIG6_TMDS_CONTROL_CHAR
+-#define DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0
+-#define DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1
+-#define DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2
+-#define DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3
+-#define DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L
+-#define DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L
+-#define DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L
+-#define DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L
+-//DIG6_TMDS_CONTROL0_FEEDBACK
+-#define DIG6_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0
+-#define DIG6_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8
+-#define DIG6_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L
+-#define DIG6_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L
+-//DIG6_TMDS_STEREOSYNC_CTL_SEL
+-#define DIG6_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0
+-#define DIG6_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L
+-//DIG6_TMDS_SYNC_CHAR_PATTERN_0_1
+-#define DIG6_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0
+-#define DIG6_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10
+-#define DIG6_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL
+-#define DIG6_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L
+-//DIG6_TMDS_SYNC_CHAR_PATTERN_2_3
+-#define DIG6_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0
+-#define DIG6_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10
+-#define DIG6_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL
+-#define DIG6_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L
+-//DIG6_TMDS_CTL_BITS
+-#define DIG6_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0
+-#define DIG6_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8
+-#define DIG6_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10
+-#define DIG6_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18
+-#define DIG6_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L
+-#define DIG6_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L
+-#define DIG6_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L
+-#define DIG6_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L
+-//DIG6_TMDS_DCBALANCER_CONTROL
+-#define DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0
+-#define DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8
+-#define DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10
+-#define DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18
+-#define DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L
+-#define DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L
+-#define DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L
+-#define DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L
+-//DIG6_TMDS_CTL0_1_GEN_CNTL
+-#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0
+-#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4
+-#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7
+-#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8
+-#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa
+-#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb
+-#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc
+-#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10
+-#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14
+-#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17
+-#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18
+-#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a
+-#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b
+-#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c
+-#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f
+-#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL
+-#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L
+-#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L
+-#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L
+-#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L
+-#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L
+-#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L
+-#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L
+-#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L
+-#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L
+-#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L
+-#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L
+-#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L
+-#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L
+-#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L
+-//DIG6_TMDS_CTL2_3_GEN_CNTL
+-#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0
+-#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4
+-#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7
+-#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8
+-#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa
+-#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb
+-#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc
+-#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10
+-#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14
+-#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17
+-#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18
+-#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a
+-#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b
+-#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c
+-#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL
+-#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L
+-#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L
+-#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L
+-#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L
+-#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L
+-#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L
+-#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L
+-#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L
+-#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L
+-#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L
+-#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L
+-#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L
+-#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L
+-//DIG6_DIG_VERSION
+-#define DIG6_DIG_VERSION__DIG_TYPE__SHIFT 0x0
+-#define DIG6_DIG_VERSION__DIG_TYPE_MASK 0x00000001L
+-//DIG6_DIG_LANE_ENABLE
+-#define DIG6_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0
+-#define DIG6_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1
+-#define DIG6_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2
+-#define DIG6_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3
+-#define DIG6_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8
+-#define DIG6_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L
+-#define DIG6_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L
+-#define DIG6_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L
+-#define DIG6_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L
+-#define DIG6_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L
+-//DIG6_AFMT_CNTL
+-#define DIG6_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0
+-#define DIG6_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8
+-#define DIG6_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L
+-#define DIG6_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L
+-
+-
+-// addressBlock: dce_dc_dp6_dispdec
+-//DP6_DP_LINK_CNTL
+-#define DP6_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4
+-#define DP6_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8
+-#define DP6_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11
+-#define DP6_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L
+-#define DP6_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L
+-#define DP6_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L
+-//DP6_DP_PIXEL_FORMAT
+-#define DP6_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0
+-#define DP6_DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x8
+-#define DP6_DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x10
+-#define DP6_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18
+-#define DP6_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L
+-#define DP6_DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x00000100L
+-#define DP6_DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x00010000L
+-#define DP6_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L
+-//DP6_DP_MSA_COLORIMETRY
+-#define DP6_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x0
+-#define DP6_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x8
+-#define DP6_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE__SHIFT 0x9
+-#define DP6_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE__SHIFT 0x11
+-#define DP6_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0x000000FFL
+-#define DP6_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x00000100L
+-#define DP6_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_MASK 0x00000200L
+-#define DP6_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE_MASK 0x00020000L
+-//DP6_DP_CONFIG
+-#define DP6_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0
+-#define DP6_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L
+-//DP6_DP_VID_STREAM_CNTL
+-#define DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0
+-#define DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8
+-#define DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10
+-#define DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14
+-#define DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L
+-#define DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L
+-#define DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L
+-#define DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L
+-//DP6_DP_STEER_FIFO
+-#define DP6_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0
+-#define DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4
+-#define DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5
+-#define DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6
+-#define DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7
+-#define DP6_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8
+-#define DP6_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc
+-#define DP6_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L
+-#define DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L
+-#define DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L
+-#define DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L
+-#define DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L
+-#define DP6_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L
+-#define DP6_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L
+-//DP6_DP_MSA_MISC
+-#define DP6_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x3
+-#define DP6_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8
+-#define DP6_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10
+-#define DP6_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18
+-#define DP6_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x00000078L
+-#define DP6_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L
+-#define DP6_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L
+-#define DP6_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L
+-//DP6_DP_VID_TIMING
+-#define DP6_DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x0
+-#define DP6_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4
+-#define DP6_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8
+-#define DP6_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN__SHIFT 0x9
+-#define DP6_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18
+-#define DP6_DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x00000001L
+-#define DP6_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L
+-#define DP6_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L
+-#define DP6_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN_MASK 0x00000200L
+-#define DP6_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L
+-//DP6_DP_VID_N
+-#define DP6_DP_VID_N__DP_VID_N__SHIFT 0x0
+-#define DP6_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL
+-//DP6_DP_VID_M
+-#define DP6_DP_VID_M__DP_VID_M__SHIFT 0x0
+-#define DP6_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL
+-//DP6_DP_LINK_FRAMING_CNTL
+-#define DP6_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0
+-#define DP6_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18
+-#define DP6_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c
+-#define DP6_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL
+-#define DP6_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L
+-#define DP6_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L
+-//DP6_DP_HBR2_EYE_PATTERN
+-#define DP6_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0
+-#define DP6_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L
+-//DP6_DP_VID_MSA_VBID
+-#define DP6_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0
+-#define DP6_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x10
+-#define DP6_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18
+-#define DP6_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL
+-#define DP6_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x00010000L
+-#define DP6_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L
+-//DP6_DP_VID_INTERRUPT_CNTL
+-#define DP6_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0
+-#define DP6_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1
+-#define DP6_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2
+-#define DP6_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L
+-#define DP6_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L
+-#define DP6_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L
+-//DP6_DP_DPHY_CNTL
+-#define DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0
+-#define DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1
+-#define DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2
+-#define DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3
+-#define DP6_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10
+-#define DP6_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18
+-#define DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L
+-#define DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L
+-#define DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L
+-#define DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L
+-#define DP6_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L
+-#define DP6_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L
+-//DP6_DP_DPHY_TRAINING_PATTERN_SEL
+-#define DP6_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0
+-#define DP6_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L
+-//DP6_DP_DPHY_SYM0
+-#define DP6_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0
+-#define DP6_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa
+-#define DP6_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14
+-#define DP6_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL
+-#define DP6_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L
+-#define DP6_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L
+-//DP6_DP_DPHY_SYM1
+-#define DP6_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0
+-#define DP6_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa
+-#define DP6_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14
+-#define DP6_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL
+-#define DP6_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L
+-#define DP6_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L
+-//DP6_DP_DPHY_SYM2
+-#define DP6_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0
+-#define DP6_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa
+-#define DP6_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL
+-#define DP6_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L
+-//DP6_DP_DPHY_8B10B_CNTL
+-#define DP6_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8
+-#define DP6_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10
+-#define DP6_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18
+-#define DP6_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L
+-#define DP6_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L
+-#define DP6_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L
+-//DP6_DP_DPHY_PRBS_CNTL
+-#define DP6_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0
+-#define DP6_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4
+-#define DP6_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8
+-#define DP6_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L
+-#define DP6_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L
+-#define DP6_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L
+-//DP6_DP_DPHY_SCRAM_CNTL
+-#define DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0
+-#define DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4
+-#define DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8
+-#define DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18
+-#define DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L
+-#define DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L
+-#define DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L
+-#define DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L
+-//DP6_DP_DPHY_CRC_EN
+-#define DP6_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0
+-#define DP6_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4
+-#define DP6_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8
+-#define DP6_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L
+-#define DP6_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L
+-#define DP6_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L
+-//DP6_DP_DPHY_CRC_CNTL
+-#define DP6_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0
+-#define DP6_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4
+-#define DP6_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10
+-#define DP6_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L
+-#define DP6_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L
+-#define DP6_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L
+-//DP6_DP_DPHY_CRC_RESULT
+-#define DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0
+-#define DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8
+-#define DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10
+-#define DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18
+-#define DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL
+-#define DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L
+-#define DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L
+-#define DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L
+-//DP6_DP_DPHY_CRC_MST_CNTL
+-#define DP6_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0
+-#define DP6_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8
+-#define DP6_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL
+-#define DP6_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L
+-//DP6_DP_DPHY_CRC_MST_STATUS
+-#define DP6_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0
+-#define DP6_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8
+-#define DP6_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10
+-#define DP6_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L
+-#define DP6_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L
+-#define DP6_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L
+-//DP6_DP_DPHY_FAST_TRAINING
+-#define DP6_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0
+-#define DP6_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1
+-#define DP6_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2
+-#define DP6_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8
+-#define DP6_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14
+-#define DP6_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L
+-#define DP6_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L
+-#define DP6_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L
+-#define DP6_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L
+-#define DP6_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L
+-//DP6_DP_DPHY_FAST_TRAINING_STATUS
+-#define DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0
+-#define DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4
+-#define DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8
+-#define DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc
+-#define DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L
+-#define DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L
+-#define DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L
+-#define DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L
+-//DP6_DP_MSA_V_TIMING_OVERRIDE1
+-#define DP6_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x0
+-#define DP6_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x4
+-#define DP6_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x00000001L
+-#define DP6_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x0003FFF0L
+-//DP6_DP_MSA_V_TIMING_OVERRIDE2
+-#define DP6_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x0
+-#define DP6_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x10
+-#define DP6_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x00003FFFL
+-#define DP6_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x3FFF0000L
+-//DP6_DP_SEC_CNTL
+-#define DP6_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0
+-#define DP6_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4
+-#define DP6_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8
+-#define DP6_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc
+-#define DP6_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10
+-#define DP6_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14
+-#define DP6_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15
+-#define DP6_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16
+-#define DP6_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17
+-#define DP6_DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x18
+-#define DP6_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c
+-#define DP6_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L
+-#define DP6_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L
+-#define DP6_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L
+-#define DP6_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L
+-#define DP6_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L
+-#define DP6_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L
+-#define DP6_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L
+-#define DP6_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L
+-#define DP6_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L
+-#define DP6_DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x01000000L
+-#define DP6_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L
+-//DP6_DP_SEC_CNTL1
+-#define DP6_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0
+-#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4
+-#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5
+-#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6
+-#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7
+-#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10
+-#define DP6_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L
+-#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L
+-#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L
+-#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L
+-#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L
+-#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L
+-//DP6_DP_SEC_FRAMING1
+-#define DP6_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0
+-#define DP6_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+-#define DP6_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL
+-#define DP6_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+-//DP6_DP_SEC_FRAMING2
+-#define DP6_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0
+-#define DP6_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+-#define DP6_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL
+-#define DP6_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+-//DP6_DP_SEC_FRAMING3
+-#define DP6_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0
+-#define DP6_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10
+-#define DP6_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL
+-#define DP6_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+-//DP6_DP_SEC_FRAMING4
+-#define DP6_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14
+-#define DP6_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18
+-#define DP6_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c
+-#define DP6_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d
+-#define DP6_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L
+-#define DP6_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L
+-#define DP6_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L
+-#define DP6_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L
+-//DP6_DP_SEC_AUD_N
+-#define DP6_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0
+-#define DP6_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL
+-//DP6_DP_SEC_AUD_N_READBACK
+-#define DP6_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0
+-#define DP6_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL
+-//DP6_DP_SEC_AUD_M
+-#define DP6_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0
+-#define DP6_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL
+-//DP6_DP_SEC_AUD_M_READBACK
+-#define DP6_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0
+-#define DP6_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL
+-//DP6_DP_SEC_TIMESTAMP
+-#define DP6_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0
+-#define DP6_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L
+-//DP6_DP_SEC_PACKET_CNTL
+-#define DP6_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1
+-#define DP6_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4
+-#define DP6_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8
+-#define DP6_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10
+-#define DP6_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL
+-#define DP6_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L
+-#define DP6_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L
+-#define DP6_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L
+-//DP6_DP_MSE_RATE_CNTL
+-#define DP6_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0
+-#define DP6_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a
+-#define DP6_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL
+-#define DP6_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L
+-//DP6_DP_MSE_RATE_UPDATE
+-#define DP6_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0
+-#define DP6_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L
+-//DP6_DP_MSE_SAT0
+-#define DP6_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0
+-#define DP6_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8
+-#define DP6_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10
+-#define DP6_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18
+-#define DP6_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L
+-#define DP6_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L
+-#define DP6_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L
+-#define DP6_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L
+-//DP6_DP_MSE_SAT1
+-#define DP6_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0
+-#define DP6_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8
+-#define DP6_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10
+-#define DP6_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18
+-#define DP6_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L
+-#define DP6_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L
+-#define DP6_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L
+-#define DP6_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L
+-//DP6_DP_MSE_SAT2
+-#define DP6_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0
+-#define DP6_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8
+-#define DP6_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10
+-#define DP6_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18
+-#define DP6_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L
+-#define DP6_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L
+-#define DP6_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L
+-#define DP6_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L
+-//DP6_DP_MSE_SAT_UPDATE
+-#define DP6_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0
+-#define DP6_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8
+-#define DP6_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L
+-#define DP6_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L
+-//DP6_DP_MSE_LINK_TIMING
+-#define DP6_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0
+-#define DP6_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10
+-#define DP6_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL
+-#define DP6_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L
+-//DP6_DP_MSE_MISC_CNTL
+-#define DP6_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0
+-#define DP6_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4
+-#define DP6_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8
+-#define DP6_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L
+-#define DP6_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L
+-#define DP6_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L
+-//DP6_DP_DPHY_BS_SR_SWAP_CNTL
+-#define DP6_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0
+-#define DP6_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf
+-#define DP6_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10
+-#define DP6_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL
+-#define DP6_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L
+-#define DP6_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L
+-//DP6_DP_DPHY_HBR2_PATTERN_CONTROL
+-#define DP6_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0
+-#define DP6_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L
+-//DP6_DP_MSE_SAT0_STATUS
+-#define DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0
+-#define DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8
+-#define DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10
+-#define DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18
+-#define DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L
+-#define DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L
+-#define DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L
+-#define DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L
+-//DP6_DP_MSE_SAT1_STATUS
+-#define DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0
+-#define DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8
+-#define DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10
+-#define DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18
+-#define DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L
+-#define DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L
+-#define DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L
+-#define DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L
+-//DP6_DP_MSE_SAT2_STATUS
+-#define DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0
+-#define DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8
+-#define DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10
+-#define DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18
+-#define DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L
+-#define DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L
+-#define DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L
+-#define DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L
+-
+-
+-// addressBlock: dce_dc_dcio_uniphy0_dispdec
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dc_combophycmregs0_dispdec
+-//DC_COMBOPHYCMREGS0_COMMON_FUSE1
+-#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_valid__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated0__SHIFT 0x1
+-#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_ron_override_val__SHIFT 0x3
+-#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated1__SHIFT 0x9
+-#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0xa
+-#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated2__SHIFT 0xc
+-#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_rtt_override_val__SHIFT 0xd
+-#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated3__SHIFT 0x13
+-#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0x14
+-#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_refresh_cal_en__SHIFT 0x16
+-#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_spare__SHIFT 0x17
+-#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_valid_MASK 0x00000001L
+-#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated0_MASK 0x00000006L
+-#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_ron_override_val_MASK 0x000001F8L
+-#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated1_MASK 0x00000200L
+-#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x00000C00L
+-#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated2_MASK 0x00001000L
+-#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_rtt_override_val_MASK 0x0007E000L
+-#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated3_MASK 0x00080000L
+-#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x00300000L
+-#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_refresh_cal_en_MASK 0x00400000L
+-#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_spare_MASK 0xFF800000L
+-//DC_COMBOPHYCMREGS0_COMMON_FUSE2
+-#define DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_valid__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_unpopulated__SHIFT 0x1
+-#define DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_tx_fifo_ptr__SHIFT 0x9
+-#define DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_spare__SHIFT 0xe
+-#define DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_valid_MASK 0x00000001L
+-#define DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_unpopulated_MASK 0x000001FEL
+-#define DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_tx_fifo_ptr_MASK 0x00003E00L
+-#define DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_spare_MASK 0xFFFFC000L
+-//DC_COMBOPHYCMREGS0_COMMON_FUSE3
+-#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_valid__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_unpopulated__SHIFT 0x1
+-#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_ei_det_thresh_sel__SHIFT 0xa
+-#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d
+-#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_valid_MASK 0x00000001L
+-#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_unpopulated_MASK 0x000003FEL
+-#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_ei_det_thresh_sel_MASK 0x00001C00L
+-#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_spare_MASK 0xE0000000L
+-//DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM
+-#define DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8
+-#define DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10
+-#define DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18
+-#define DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0x000000FFL
+-#define DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0x0000FF00L
+-#define DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0x00FF0000L
+-#define DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xFF000000L
+-//DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT
+-#define DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4
+-#define DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT__vprot_en__SHIFT 0xb
+-#define DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT__pgdelay_MASK 0x0000000FL
+-#define DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT__pgmask_MASK 0x000003F0L
+-#define DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT__vprot_en_MASK 0x00000800L
+-//DC_COMBOPHYCMREGS0_COMMON_TXCNTRL
+-#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__clkgate_dis__SHIFT 0x5
+-#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT 0x6
+-#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT 0x9
+-#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT 0xc
+-#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__dual_dvi_mstr_en__SHIFT 0xf
+-#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__dual_dvi_en__SHIFT 0x10
+-#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK 0x0000001FL
+-#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__clkgate_dis_MASK 0x00000020L
+-#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK 0x000001C0L
+-#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK 0x00000E00L
+-#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK 0x00007000L
+-#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__dual_dvi_mstr_en_MASK 0x00008000L
+-#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__dual_dvi_en_MASK 0x00010000L
+-//DC_COMBOPHYCMREGS0_COMMON_TMDP
+-#define DC_COMBOPHYCMREGS0_COMMON_TMDP__tmdp_spare__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS0_COMMON_TMDP__tmdp_spare_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS
+-#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_0_reset_l__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_1_reset_l__SHIFT 0x1
+-#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_2_reset_l__SHIFT 0x2
+-#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_3_reset_l__SHIFT 0x3
+-#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_4_reset_l__SHIFT 0x4
+-#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_5_reset_l__SHIFT 0x5
+-#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_6_reset_l__SHIFT 0x6
+-#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_7_reset_l__SHIFT 0x7
+-#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_0_reset_l_MASK 0x00000001L
+-#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_1_reset_l_MASK 0x00000002L
+-#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_2_reset_l_MASK 0x00000004L
+-#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_3_reset_l_MASK 0x00000008L
+-#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_4_reset_l_MASK 0x00000010L
+-#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_5_reset_l_MASK 0x00000020L
+-#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_6_reset_l_MASK 0x00000040L
+-#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_7_reset_l_MASK 0x00000080L
+-//DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL
+-#define DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT 0x1
+-#define DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT 0x15
+-#define DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__zcalcode_override_MASK 0x00000001L
+-#define DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK 0x0000003EL
+-#define DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK 0x00200000L
+-//DC_COMBOPHYCMREGS0_COMMON_DISP_RFU1
+-#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU1__rfu_value1__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU1__rfu_value1_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS0_COMMON_DISP_RFU2
+-#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU2__rfu_value2__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU2__rfu_value2_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS0_COMMON_DISP_RFU3
+-#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU3__rfu_value3__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU3__rfu_value3_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS0_COMMON_DISP_RFU4
+-#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU4__rfu_value4__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU4__rfu_value4_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS0_COMMON_DISP_RFU5
+-#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU5__rfu_value5__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU5__rfu_value5_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS0_COMMON_DISP_RFU6
+-#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU6__rfu_value6__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU6__rfu_value6_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS0_COMMON_DISP_RFU7
+-#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU7__rfu_value7__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU7__rfu_value7_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dc_combophytxregs0_dispdec
+-//DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK 0x00000100L
+-//DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0
+-#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0__txmarg_sel_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0__deemph_sel_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0__tx_margin_en_MASK 0x00000020L
+-//DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x1
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT 0xa
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT 0xc
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT 0xd
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT 0xe
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT 0xf
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT 0x10
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT 0x14
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT 0x16
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x00000006L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0x000000E0L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK 0x00000300L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK 0x00000C00L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK 0x00001000L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK 0x00002000L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK 0x00004000L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK 0x00008000L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK 0x000F0000L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK 0x00100000L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK 0x00C00000L
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0__rfu_value0__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0__rfu_value0_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0__rfu_value1__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0__rfu_value1_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0__rfu_value2__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0__rfu_value2_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0__rfu_value3__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0__rfu_value3_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0__rfu_value4__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0__rfu_value4_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0__rfu_value5__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0__rfu_value5_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0__rfu_value6__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0__rfu_value6_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0__rfu_value7__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0__rfu_value7_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0__rfu_value8__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0__rfu_value8_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0__rfu_value9__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0__rfu_value9_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0__rfu_value10__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0__rfu_value10_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0__rfu_value11__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0__rfu_value11_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0__rfu_value12__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0__rfu_value12_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK 0x00000100L
+-//DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1
+-#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1__txmarg_sel_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1__deemph_sel_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1__tx_margin_en_MASK 0x00000020L
+-//DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x1
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT 0xa
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT 0xc
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT 0xd
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT 0xe
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT 0xf
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT 0x10
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT 0x14
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT 0x16
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x00000006L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0x000000E0L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK 0x00000300L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK 0x00000C00L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK 0x00001000L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK 0x00002000L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK 0x00004000L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK 0x00008000L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK 0x000F0000L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK 0x00100000L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK 0x00C00000L
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1__rfu_value0__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1__rfu_value0_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1__rfu_value1__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1__rfu_value1_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1__rfu_value2__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1__rfu_value2_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1__rfu_value3__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1__rfu_value3_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1__rfu_value4__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1__rfu_value4_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1__rfu_value5__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1__rfu_value5_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1__rfu_value6__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1__rfu_value6_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1__rfu_value7__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1__rfu_value7_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1__rfu_value8__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1__rfu_value8_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1__rfu_value9__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1__rfu_value9_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1__rfu_value10__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1__rfu_value10_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1__rfu_value11__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1__rfu_value11_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1__rfu_value12__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1__rfu_value12_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK 0x00000100L
+-//DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2
+-#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2__txmarg_sel_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2__deemph_sel_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2__tx_margin_en_MASK 0x00000020L
+-//DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x1
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT 0xa
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT 0xc
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT 0xd
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT 0xe
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT 0xf
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT 0x10
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT 0x14
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT 0x16
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x00000006L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0x000000E0L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK 0x00000300L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK 0x00000C00L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK 0x00001000L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK 0x00002000L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK 0x00004000L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK 0x00008000L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK 0x000F0000L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK 0x00100000L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK 0x00C00000L
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2__rfu_value0__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2__rfu_value0_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2__rfu_value1__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2__rfu_value1_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2__rfu_value2__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2__rfu_value2_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2__rfu_value3__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2__rfu_value3_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2__rfu_value4__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2__rfu_value4_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2__rfu_value5__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2__rfu_value5_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2__rfu_value6__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2__rfu_value6_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2__rfu_value7__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2__rfu_value7_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2__rfu_value8__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2__rfu_value8_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2__rfu_value9__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2__rfu_value9_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2__rfu_value10__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2__rfu_value10_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2__rfu_value11__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2__rfu_value11_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2__rfu_value12__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2__rfu_value12_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK 0x00000100L
+-//DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3
+-#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3__txmarg_sel_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3__deemph_sel_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3__tx_margin_en_MASK 0x00000020L
+-//DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x1
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT 0xa
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT 0xc
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT 0xd
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT 0xe
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT 0xf
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT 0x10
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT 0x14
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT 0x16
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x00000006L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0x000000E0L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK 0x00000300L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK 0x00000C00L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK 0x00001000L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK 0x00002000L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK 0x00004000L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK 0x00008000L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK 0x000F0000L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK 0x00100000L
+-#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK 0x00C00000L
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3__rfu_value0__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3__rfu_value0_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3__rfu_value1__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3__rfu_value1_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3__rfu_value2__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3__rfu_value2_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3__rfu_value3__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3__rfu_value3_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3__rfu_value4__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3__rfu_value4_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3__rfu_value5__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3__rfu_value5_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3__rfu_value6__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3__rfu_value6_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3__rfu_value7__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3__rfu_value7_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3__rfu_value8__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3__rfu_value8_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3__rfu_value9__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3__rfu_value9_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3__rfu_value10__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3__rfu_value10_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3__rfu_value11__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3__rfu_value11_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3__rfu_value12__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3__rfu_value12_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dc_combophypllregs0_dispdec
+-//DC_COMBOPHYPLLREGS0_FREQ_CTRL0
+-#define DC_COMBOPHYPLLREGS0_FREQ_CTRL0__fcw0_frac__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS0_FREQ_CTRL0__fcw0_int__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS0_FREQ_CTRL0__fcw0_frac_MASK 0x0000FFFFL
+-#define DC_COMBOPHYPLLREGS0_FREQ_CTRL0__fcw0_int_MASK 0x01FF0000L
+-//DC_COMBOPHYPLLREGS0_FREQ_CTRL1
+-#define DC_COMBOPHYPLLREGS0_FREQ_CTRL1__fcw1_frac__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS0_FREQ_CTRL1__fcw1_int__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS0_FREQ_CTRL1__fcw1_frac_MASK 0x0000FFFFL
+-#define DC_COMBOPHYPLLREGS0_FREQ_CTRL1__fcw1_int_MASK 0x01FF0000L
+-//DC_COMBOPHYPLLREGS0_FREQ_CTRL2
+-#define DC_COMBOPHYPLLREGS0_FREQ_CTRL2__fcw_denom__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS0_FREQ_CTRL2__fcw_slew_frac__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS0_FREQ_CTRL2__fcw_denom_MASK 0x0000FFFFL
+-#define DC_COMBOPHYPLLREGS0_FREQ_CTRL2__fcw_slew_frac_MASK 0xFFFF0000L
+-//DC_COMBOPHYPLLREGS0_FREQ_CTRL3
+-#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__refclk_div__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__vco_pre_div__SHIFT 0x3
+-#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__fracn_en__SHIFT 0x6
+-#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__ssc_en__SHIFT 0x8
+-#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__fcw_sel__SHIFT 0xa
+-#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__freq_jump_en__SHIFT 0xc
+-#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__tdc_resolution__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__dpll_cfg_1__SHIFT 0x18
+-#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__refclk_div_MASK 0x00000003L
+-#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__vco_pre_div_MASK 0x00000018L
+-#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__fracn_en_MASK 0x00000040L
+-#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__ssc_en_MASK 0x00000100L
+-#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__fcw_sel_MASK 0x00000400L
+-#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__freq_jump_en_MASK 0x00001000L
+-#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__tdc_resolution_MASK 0x00FF0000L
+-#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__dpll_cfg_1_MASK 0xFF000000L
+-//DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE
+-#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gi_coarse_mant__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gi_coarse_exp__SHIFT 0x2
+-#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gp_coarse_mant__SHIFT 0x7
+-#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gp_coarse_exp__SHIFT 0xc
+-#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__nctl_coarse_res__SHIFT 0x11
+-#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT 0x18
+-#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gi_coarse_mant_MASK 0x00000003L
+-#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gi_coarse_exp_MASK 0x0000003CL
+-#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gp_coarse_mant_MASK 0x00000780L
+-#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gp_coarse_exp_MASK 0x0000F000L
+-#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__nctl_coarse_res_MASK 0x007E0000L
+-#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__nctl_coarse_frac_res_MASK 0x03000000L
+-//DC_COMBOPHYPLLREGS0_BW_CTRL_FINE
+-#define DC_COMBOPHYPLLREGS0_BW_CTRL_FINE__dpll_cfg_3__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS0_BW_CTRL_FINE__dpll_cfg_3_MASK 0x000003FFL
+-//DC_COMBOPHYPLLREGS0_CAL_CTRL
+-#define DC_COMBOPHYPLLREGS0_CAL_CTRL__bypass_freq_lock__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS0_CAL_CTRL__tdc_cal_en__SHIFT 0x1
+-#define DC_COMBOPHYPLLREGS0_CAL_CTRL__tdc_cal_ctrl__SHIFT 0x3
+-#define DC_COMBOPHYPLLREGS0_CAL_CTRL__meas_win_sel__SHIFT 0x9
+-#define DC_COMBOPHYPLLREGS0_CAL_CTRL__kdco_cal_dis__SHIFT 0xb
+-#define DC_COMBOPHYPLLREGS0_CAL_CTRL__kdco_ratio__SHIFT 0xd
+-#define DC_COMBOPHYPLLREGS0_CAL_CTRL__kdco_incr_cal_dis__SHIFT 0x16
+-#define DC_COMBOPHYPLLREGS0_CAL_CTRL__nctl_adj_dis__SHIFT 0x17
+-#define DC_COMBOPHYPLLREGS0_CAL_CTRL__refclk_rate__SHIFT 0x18
+-#define DC_COMBOPHYPLLREGS0_CAL_CTRL__bypass_freq_lock_MASK 0x00000001L
+-#define DC_COMBOPHYPLLREGS0_CAL_CTRL__tdc_cal_en_MASK 0x00000002L
+-#define DC_COMBOPHYPLLREGS0_CAL_CTRL__tdc_cal_ctrl_MASK 0x000001F8L
+-#define DC_COMBOPHYPLLREGS0_CAL_CTRL__meas_win_sel_MASK 0x00000600L
+-#define DC_COMBOPHYPLLREGS0_CAL_CTRL__kdco_cal_dis_MASK 0x00000800L
+-#define DC_COMBOPHYPLLREGS0_CAL_CTRL__kdco_ratio_MASK 0x001FE000L
+-#define DC_COMBOPHYPLLREGS0_CAL_CTRL__kdco_incr_cal_dis_MASK 0x00400000L
+-#define DC_COMBOPHYPLLREGS0_CAL_CTRL__nctl_adj_dis_MASK 0x00800000L
+-#define DC_COMBOPHYPLLREGS0_CAL_CTRL__refclk_rate_MASK 0xFF000000L
+-//DC_COMBOPHYPLLREGS0_LOOP_CTRL
+-#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__fbdiv_mask_en__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__fb_slip_dis__SHIFT 0x2
+-#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__clk_tdc_sel__SHIFT 0x4
+-#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__clk_nctl_sel__SHIFT 0x7
+-#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__sig_del_patt_sel__SHIFT 0xa
+-#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__nctl_sig_del_dis__SHIFT 0xc
+-#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__fbclk_track_refclk__SHIFT 0xe
+-#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__prbs_en__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__tdc_clk_gate_en__SHIFT 0x12
+-#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__phase_offset__SHIFT 0x14
+-#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__fbdiv_mask_en_MASK 0x00000001L
+-#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__fb_slip_dis_MASK 0x00000004L
+-#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__clk_tdc_sel_MASK 0x00000030L
+-#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__clk_nctl_sel_MASK 0x00000180L
+-#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__sig_del_patt_sel_MASK 0x00000400L
+-#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__nctl_sig_del_dis_MASK 0x00001000L
+-#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__fbclk_track_refclk_MASK 0x00004000L
+-#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__prbs_en_MASK 0x00010000L
+-#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__tdc_clk_gate_en_MASK 0x00040000L
+-#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__phase_offset_MASK 0x07F00000L
+-//DC_COMBOPHYPLLREGS0_VREG_CFG
+-#define DC_COMBOPHYPLLREGS0_VREG_CFG__bleeder_ac__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS0_VREG_CFG__bleeder_en__SHIFT 0x1
+-#define DC_COMBOPHYPLLREGS0_VREG_CFG__is_1p2__SHIFT 0x2
+-#define DC_COMBOPHYPLLREGS0_VREG_CFG__reg_obs_sel__SHIFT 0x3
+-#define DC_COMBOPHYPLLREGS0_VREG_CFG__reg_on_mode__SHIFT 0x5
+-#define DC_COMBOPHYPLLREGS0_VREG_CFG__rlad_tap_sel__SHIFT 0x7
+-#define DC_COMBOPHYPLLREGS0_VREG_CFG__reg_off_hi__SHIFT 0xb
+-#define DC_COMBOPHYPLLREGS0_VREG_CFG__reg_off_lo__SHIFT 0xc
+-#define DC_COMBOPHYPLLREGS0_VREG_CFG__scale_driver__SHIFT 0xd
+-#define DC_COMBOPHYPLLREGS0_VREG_CFG__sel_bump__SHIFT 0xf
+-#define DC_COMBOPHYPLLREGS0_VREG_CFG__sel_rladder_x__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS0_VREG_CFG__short_rc_filt_x__SHIFT 0x11
+-#define DC_COMBOPHYPLLREGS0_VREG_CFG__vref_pwr_on__SHIFT 0x12
+-#define DC_COMBOPHYPLLREGS0_VREG_CFG__dpll_cfg_2__SHIFT 0x14
+-#define DC_COMBOPHYPLLREGS0_VREG_CFG__bleeder_ac_MASK 0x00000001L
+-#define DC_COMBOPHYPLLREGS0_VREG_CFG__bleeder_en_MASK 0x00000002L
+-#define DC_COMBOPHYPLLREGS0_VREG_CFG__is_1p2_MASK 0x00000004L
+-#define DC_COMBOPHYPLLREGS0_VREG_CFG__reg_obs_sel_MASK 0x00000018L
+-#define DC_COMBOPHYPLLREGS0_VREG_CFG__reg_on_mode_MASK 0x00000060L
+-#define DC_COMBOPHYPLLREGS0_VREG_CFG__rlad_tap_sel_MASK 0x00000780L
+-#define DC_COMBOPHYPLLREGS0_VREG_CFG__reg_off_hi_MASK 0x00000800L
+-#define DC_COMBOPHYPLLREGS0_VREG_CFG__reg_off_lo_MASK 0x00001000L
+-#define DC_COMBOPHYPLLREGS0_VREG_CFG__scale_driver_MASK 0x00006000L
+-#define DC_COMBOPHYPLLREGS0_VREG_CFG__sel_bump_MASK 0x00008000L
+-#define DC_COMBOPHYPLLREGS0_VREG_CFG__sel_rladder_x_MASK 0x00010000L
+-#define DC_COMBOPHYPLLREGS0_VREG_CFG__short_rc_filt_x_MASK 0x00020000L
+-#define DC_COMBOPHYPLLREGS0_VREG_CFG__vref_pwr_on_MASK 0x00040000L
+-#define DC_COMBOPHYPLLREGS0_VREG_CFG__dpll_cfg_2_MASK 0x0FF00000L
+-//DC_COMBOPHYPLLREGS0_OBSERVE0
+-#define DC_COMBOPHYPLLREGS0_OBSERVE0__lock_det_tdc_steps__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS0_OBSERVE0__clear_sticky_lock__SHIFT 0x6
+-#define DC_COMBOPHYPLLREGS0_OBSERVE0__lock_det_dis__SHIFT 0x8
+-#define DC_COMBOPHYPLLREGS0_OBSERVE0__dco_cfg__SHIFT 0xa
+-#define DC_COMBOPHYPLLREGS0_OBSERVE0__anaobs_sel__SHIFT 0x15
+-#define DC_COMBOPHYPLLREGS0_OBSERVE0__lock_det_tdc_steps_MASK 0x0000001FL
+-#define DC_COMBOPHYPLLREGS0_OBSERVE0__clear_sticky_lock_MASK 0x00000040L
+-#define DC_COMBOPHYPLLREGS0_OBSERVE0__lock_det_dis_MASK 0x00000100L
+-#define DC_COMBOPHYPLLREGS0_OBSERVE0__dco_cfg_MASK 0x0003FC00L
+-#define DC_COMBOPHYPLLREGS0_OBSERVE0__anaobs_sel_MASK 0x00E00000L
+-//DC_COMBOPHYPLLREGS0_OBSERVE1
+-#define DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_sel__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_trig_sel__SHIFT 0x5
+-#define DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_div__SHIFT 0xa
+-#define DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_trig_div__SHIFT 0xd
+-#define DC_COMBOPHYPLLREGS0_OBSERVE1__lock_timer__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_sel_MASK 0x0000000FL
+-#define DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_trig_sel_MASK 0x000001E0L
+-#define DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_div_MASK 0x00000C00L
+-#define DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_trig_div_MASK 0x00006000L
+-#define DC_COMBOPHYPLLREGS0_OBSERVE1__lock_timer_MASK 0x3FFF0000L
+-//DC_COMBOPHYPLLREGS0_DFT_OUT
+-#define DC_COMBOPHYPLLREGS0_DFT_OUT__dft_data__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS0_DFT_OUT__dft_data_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dcio_uniphy1_dispdec
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dc_combophycmregs1_dispdec
+-//DC_COMBOPHYCMREGS1_COMMON_FUSE1
+-#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_valid__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated0__SHIFT 0x1
+-#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_ron_override_val__SHIFT 0x3
+-#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated1__SHIFT 0x9
+-#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0xa
+-#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated2__SHIFT 0xc
+-#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_rtt_override_val__SHIFT 0xd
+-#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated3__SHIFT 0x13
+-#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0x14
+-#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_refresh_cal_en__SHIFT 0x16
+-#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_spare__SHIFT 0x17
+-#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_valid_MASK 0x00000001L
+-#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated0_MASK 0x00000006L
+-#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_ron_override_val_MASK 0x000001F8L
+-#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated1_MASK 0x00000200L
+-#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x00000C00L
+-#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated2_MASK 0x00001000L
+-#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_rtt_override_val_MASK 0x0007E000L
+-#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated3_MASK 0x00080000L
+-#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x00300000L
+-#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_refresh_cal_en_MASK 0x00400000L
+-#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_spare_MASK 0xFF800000L
+-//DC_COMBOPHYCMREGS1_COMMON_FUSE2
+-#define DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_valid__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_unpopulated__SHIFT 0x1
+-#define DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_tx_fifo_ptr__SHIFT 0x9
+-#define DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_spare__SHIFT 0xe
+-#define DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_valid_MASK 0x00000001L
+-#define DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_unpopulated_MASK 0x000001FEL
+-#define DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_tx_fifo_ptr_MASK 0x00003E00L
+-#define DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_spare_MASK 0xFFFFC000L
+-//DC_COMBOPHYCMREGS1_COMMON_FUSE3
+-#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_valid__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_unpopulated__SHIFT 0x1
+-#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_ei_det_thresh_sel__SHIFT 0xa
+-#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d
+-#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_valid_MASK 0x00000001L
+-#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_unpopulated_MASK 0x000003FEL
+-#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_ei_det_thresh_sel_MASK 0x00001C00L
+-#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_spare_MASK 0xE0000000L
+-//DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM
+-#define DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8
+-#define DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10
+-#define DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18
+-#define DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0x000000FFL
+-#define DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0x0000FF00L
+-#define DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0x00FF0000L
+-#define DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xFF000000L
+-//DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT
+-#define DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4
+-#define DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT__vprot_en__SHIFT 0xb
+-#define DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT__pgdelay_MASK 0x0000000FL
+-#define DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT__pgmask_MASK 0x000003F0L
+-#define DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT__vprot_en_MASK 0x00000800L
+-//DC_COMBOPHYCMREGS1_COMMON_TXCNTRL
+-#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__clkgate_dis__SHIFT 0x5
+-#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT 0x6
+-#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT 0x9
+-#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT 0xc
+-#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__dual_dvi_mstr_en__SHIFT 0xf
+-#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__dual_dvi_en__SHIFT 0x10
+-#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK 0x0000001FL
+-#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__clkgate_dis_MASK 0x00000020L
+-#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK 0x000001C0L
+-#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK 0x00000E00L
+-#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK 0x00007000L
+-#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__dual_dvi_mstr_en_MASK 0x00008000L
+-#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__dual_dvi_en_MASK 0x00010000L
+-//DC_COMBOPHYCMREGS1_COMMON_TMDP
+-#define DC_COMBOPHYCMREGS1_COMMON_TMDP__tmdp_spare__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS1_COMMON_TMDP__tmdp_spare_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS
+-#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_0_reset_l__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_1_reset_l__SHIFT 0x1
+-#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_2_reset_l__SHIFT 0x2
+-#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_3_reset_l__SHIFT 0x3
+-#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_4_reset_l__SHIFT 0x4
+-#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_5_reset_l__SHIFT 0x5
+-#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_6_reset_l__SHIFT 0x6
+-#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_7_reset_l__SHIFT 0x7
+-#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_0_reset_l_MASK 0x00000001L
+-#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_1_reset_l_MASK 0x00000002L
+-#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_2_reset_l_MASK 0x00000004L
+-#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_3_reset_l_MASK 0x00000008L
+-#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_4_reset_l_MASK 0x00000010L
+-#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_5_reset_l_MASK 0x00000020L
+-#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_6_reset_l_MASK 0x00000040L
+-#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_7_reset_l_MASK 0x00000080L
+-//DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL
+-#define DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT 0x1
+-#define DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT 0x15
+-#define DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__zcalcode_override_MASK 0x00000001L
+-#define DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK 0x0000003EL
+-#define DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK 0x00200000L
+-//DC_COMBOPHYCMREGS1_COMMON_DISP_RFU1
+-#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU1__rfu_value1__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU1__rfu_value1_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS1_COMMON_DISP_RFU2
+-#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU2__rfu_value2__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU2__rfu_value2_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS1_COMMON_DISP_RFU3
+-#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU3__rfu_value3__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU3__rfu_value3_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS1_COMMON_DISP_RFU4
+-#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU4__rfu_value4__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU4__rfu_value4_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS1_COMMON_DISP_RFU5
+-#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU5__rfu_value5__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU5__rfu_value5_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS1_COMMON_DISP_RFU6
+-#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU6__rfu_value6__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU6__rfu_value6_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS1_COMMON_DISP_RFU7
+-#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU7__rfu_value7__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU7__rfu_value7_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dc_combophytxregs1_dispdec
+-//DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK 0x00000100L
+-//DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0
+-#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0__txmarg_sel_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0__deemph_sel_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0__tx_margin_en_MASK 0x00000020L
+-//DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x1
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT 0xa
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT 0xc
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT 0xd
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT 0xe
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT 0xf
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT 0x10
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT 0x14
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT 0x16
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x00000006L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0x000000E0L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK 0x00000300L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK 0x00000C00L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK 0x00001000L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK 0x00002000L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK 0x00004000L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK 0x00008000L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK 0x000F0000L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK 0x00100000L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK 0x00C00000L
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0__rfu_value0__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0__rfu_value0_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0__rfu_value1__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0__rfu_value1_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0__rfu_value2__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0__rfu_value2_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0__rfu_value3__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0__rfu_value3_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0__rfu_value4__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0__rfu_value4_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0__rfu_value5__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0__rfu_value5_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0__rfu_value6__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0__rfu_value6_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0__rfu_value7__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0__rfu_value7_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0__rfu_value8__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0__rfu_value8_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0__rfu_value9__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0__rfu_value9_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0__rfu_value10__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0__rfu_value10_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0__rfu_value11__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0__rfu_value11_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0__rfu_value12__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0__rfu_value12_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK 0x00000100L
+-//DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1
+-#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1__txmarg_sel_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1__deemph_sel_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1__tx_margin_en_MASK 0x00000020L
+-//DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x1
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT 0xa
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT 0xc
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT 0xd
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT 0xe
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT 0xf
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT 0x10
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT 0x14
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT 0x16
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x00000006L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0x000000E0L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK 0x00000300L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK 0x00000C00L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK 0x00001000L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK 0x00002000L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK 0x00004000L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK 0x00008000L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK 0x000F0000L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK 0x00100000L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK 0x00C00000L
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1__rfu_value0__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1__rfu_value0_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1__rfu_value1__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1__rfu_value1_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1__rfu_value2__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1__rfu_value2_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1__rfu_value3__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1__rfu_value3_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1__rfu_value4__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1__rfu_value4_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1__rfu_value5__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1__rfu_value5_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1__rfu_value6__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1__rfu_value6_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1__rfu_value7__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1__rfu_value7_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1__rfu_value8__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1__rfu_value8_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1__rfu_value9__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1__rfu_value9_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1__rfu_value10__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1__rfu_value10_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1__rfu_value11__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1__rfu_value11_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1__rfu_value12__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1__rfu_value12_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK 0x00000100L
+-//DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2
+-#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2__txmarg_sel_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2__deemph_sel_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2__tx_margin_en_MASK 0x00000020L
+-//DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x1
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT 0xa
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT 0xc
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT 0xd
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT 0xe
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT 0xf
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT 0x10
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT 0x14
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT 0x16
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x00000006L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0x000000E0L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK 0x00000300L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK 0x00000C00L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK 0x00001000L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK 0x00002000L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK 0x00004000L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK 0x00008000L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK 0x000F0000L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK 0x00100000L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK 0x00C00000L
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2__rfu_value0__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2__rfu_value0_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2__rfu_value1__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2__rfu_value1_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2__rfu_value2__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2__rfu_value2_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2__rfu_value3__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2__rfu_value3_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2__rfu_value4__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2__rfu_value4_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2__rfu_value5__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2__rfu_value5_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2__rfu_value6__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2__rfu_value6_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2__rfu_value7__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2__rfu_value7_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2__rfu_value8__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2__rfu_value8_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2__rfu_value9__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2__rfu_value9_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2__rfu_value10__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2__rfu_value10_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2__rfu_value11__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2__rfu_value11_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2__rfu_value12__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2__rfu_value12_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK 0x00000100L
+-//DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3
+-#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3__txmarg_sel_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3__deemph_sel_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3__tx_margin_en_MASK 0x00000020L
+-//DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x1
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT 0xa
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT 0xc
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT 0xd
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT 0xe
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT 0xf
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT 0x10
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT 0x14
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT 0x16
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x00000006L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0x000000E0L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK 0x00000300L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK 0x00000C00L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK 0x00001000L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK 0x00002000L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK 0x00004000L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK 0x00008000L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK 0x000F0000L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK 0x00100000L
+-#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK 0x00C00000L
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3__rfu_value0__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3__rfu_value0_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3__rfu_value1__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3__rfu_value1_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3__rfu_value2__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3__rfu_value2_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3__rfu_value3__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3__rfu_value3_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3__rfu_value4__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3__rfu_value4_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3__rfu_value5__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3__rfu_value5_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3__rfu_value6__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3__rfu_value6_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3__rfu_value7__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3__rfu_value7_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3__rfu_value8__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3__rfu_value8_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3__rfu_value9__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3__rfu_value9_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3__rfu_value10__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3__rfu_value10_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3__rfu_value11__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3__rfu_value11_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3__rfu_value12__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3__rfu_value12_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dc_combophypllregs1_dispdec
+-//DC_COMBOPHYPLLREGS1_FREQ_CTRL0
+-#define DC_COMBOPHYPLLREGS1_FREQ_CTRL0__fcw0_frac__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS1_FREQ_CTRL0__fcw0_int__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS1_FREQ_CTRL0__fcw0_frac_MASK 0x0000FFFFL
+-#define DC_COMBOPHYPLLREGS1_FREQ_CTRL0__fcw0_int_MASK 0x01FF0000L
+-//DC_COMBOPHYPLLREGS1_FREQ_CTRL1
+-#define DC_COMBOPHYPLLREGS1_FREQ_CTRL1__fcw1_frac__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS1_FREQ_CTRL1__fcw1_int__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS1_FREQ_CTRL1__fcw1_frac_MASK 0x0000FFFFL
+-#define DC_COMBOPHYPLLREGS1_FREQ_CTRL1__fcw1_int_MASK 0x01FF0000L
+-//DC_COMBOPHYPLLREGS1_FREQ_CTRL2
+-#define DC_COMBOPHYPLLREGS1_FREQ_CTRL2__fcw_denom__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS1_FREQ_CTRL2__fcw_slew_frac__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS1_FREQ_CTRL2__fcw_denom_MASK 0x0000FFFFL
+-#define DC_COMBOPHYPLLREGS1_FREQ_CTRL2__fcw_slew_frac_MASK 0xFFFF0000L
+-//DC_COMBOPHYPLLREGS1_FREQ_CTRL3
+-#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__refclk_div__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__vco_pre_div__SHIFT 0x3
+-#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__fracn_en__SHIFT 0x6
+-#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__ssc_en__SHIFT 0x8
+-#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__fcw_sel__SHIFT 0xa
+-#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__freq_jump_en__SHIFT 0xc
+-#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__tdc_resolution__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__dpll_cfg_1__SHIFT 0x18
+-#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__refclk_div_MASK 0x00000003L
+-#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__vco_pre_div_MASK 0x00000018L
+-#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__fracn_en_MASK 0x00000040L
+-#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__ssc_en_MASK 0x00000100L
+-#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__fcw_sel_MASK 0x00000400L
+-#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__freq_jump_en_MASK 0x00001000L
+-#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__tdc_resolution_MASK 0x00FF0000L
+-#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__dpll_cfg_1_MASK 0xFF000000L
+-//DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE
+-#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gi_coarse_mant__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gi_coarse_exp__SHIFT 0x2
+-#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gp_coarse_mant__SHIFT 0x7
+-#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gp_coarse_exp__SHIFT 0xc
+-#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__nctl_coarse_res__SHIFT 0x11
+-#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT 0x18
+-#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gi_coarse_mant_MASK 0x00000003L
+-#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gi_coarse_exp_MASK 0x0000003CL
+-#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gp_coarse_mant_MASK 0x00000780L
+-#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gp_coarse_exp_MASK 0x0000F000L
+-#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__nctl_coarse_res_MASK 0x007E0000L
+-#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__nctl_coarse_frac_res_MASK 0x03000000L
+-//DC_COMBOPHYPLLREGS1_BW_CTRL_FINE
+-#define DC_COMBOPHYPLLREGS1_BW_CTRL_FINE__dpll_cfg_3__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS1_BW_CTRL_FINE__dpll_cfg_3_MASK 0x000003FFL
+-//DC_COMBOPHYPLLREGS1_CAL_CTRL
+-#define DC_COMBOPHYPLLREGS1_CAL_CTRL__bypass_freq_lock__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS1_CAL_CTRL__tdc_cal_en__SHIFT 0x1
+-#define DC_COMBOPHYPLLREGS1_CAL_CTRL__tdc_cal_ctrl__SHIFT 0x3
+-#define DC_COMBOPHYPLLREGS1_CAL_CTRL__meas_win_sel__SHIFT 0x9
+-#define DC_COMBOPHYPLLREGS1_CAL_CTRL__kdco_cal_dis__SHIFT 0xb
+-#define DC_COMBOPHYPLLREGS1_CAL_CTRL__kdco_ratio__SHIFT 0xd
+-#define DC_COMBOPHYPLLREGS1_CAL_CTRL__kdco_incr_cal_dis__SHIFT 0x16
+-#define DC_COMBOPHYPLLREGS1_CAL_CTRL__nctl_adj_dis__SHIFT 0x17
+-#define DC_COMBOPHYPLLREGS1_CAL_CTRL__refclk_rate__SHIFT 0x18
+-#define DC_COMBOPHYPLLREGS1_CAL_CTRL__bypass_freq_lock_MASK 0x00000001L
+-#define DC_COMBOPHYPLLREGS1_CAL_CTRL__tdc_cal_en_MASK 0x00000002L
+-#define DC_COMBOPHYPLLREGS1_CAL_CTRL__tdc_cal_ctrl_MASK 0x000001F8L
+-#define DC_COMBOPHYPLLREGS1_CAL_CTRL__meas_win_sel_MASK 0x00000600L
+-#define DC_COMBOPHYPLLREGS1_CAL_CTRL__kdco_cal_dis_MASK 0x00000800L
+-#define DC_COMBOPHYPLLREGS1_CAL_CTRL__kdco_ratio_MASK 0x001FE000L
+-#define DC_COMBOPHYPLLREGS1_CAL_CTRL__kdco_incr_cal_dis_MASK 0x00400000L
+-#define DC_COMBOPHYPLLREGS1_CAL_CTRL__nctl_adj_dis_MASK 0x00800000L
+-#define DC_COMBOPHYPLLREGS1_CAL_CTRL__refclk_rate_MASK 0xFF000000L
+-//DC_COMBOPHYPLLREGS1_LOOP_CTRL
+-#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__fbdiv_mask_en__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__fb_slip_dis__SHIFT 0x2
+-#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__clk_tdc_sel__SHIFT 0x4
+-#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__clk_nctl_sel__SHIFT 0x7
+-#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__sig_del_patt_sel__SHIFT 0xa
+-#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__nctl_sig_del_dis__SHIFT 0xc
+-#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__fbclk_track_refclk__SHIFT 0xe
+-#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__prbs_en__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__tdc_clk_gate_en__SHIFT 0x12
+-#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__phase_offset__SHIFT 0x14
+-#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__fbdiv_mask_en_MASK 0x00000001L
+-#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__fb_slip_dis_MASK 0x00000004L
+-#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__clk_tdc_sel_MASK 0x00000030L
+-#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__clk_nctl_sel_MASK 0x00000180L
+-#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__sig_del_patt_sel_MASK 0x00000400L
+-#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__nctl_sig_del_dis_MASK 0x00001000L
+-#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__fbclk_track_refclk_MASK 0x00004000L
+-#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__prbs_en_MASK 0x00010000L
+-#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__tdc_clk_gate_en_MASK 0x00040000L
+-#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__phase_offset_MASK 0x07F00000L
+-//DC_COMBOPHYPLLREGS1_VREG_CFG
+-#define DC_COMBOPHYPLLREGS1_VREG_CFG__bleeder_ac__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS1_VREG_CFG__bleeder_en__SHIFT 0x1
+-#define DC_COMBOPHYPLLREGS1_VREG_CFG__is_1p2__SHIFT 0x2
+-#define DC_COMBOPHYPLLREGS1_VREG_CFG__reg_obs_sel__SHIFT 0x3
+-#define DC_COMBOPHYPLLREGS1_VREG_CFG__reg_on_mode__SHIFT 0x5
+-#define DC_COMBOPHYPLLREGS1_VREG_CFG__rlad_tap_sel__SHIFT 0x7
+-#define DC_COMBOPHYPLLREGS1_VREG_CFG__reg_off_hi__SHIFT 0xb
+-#define DC_COMBOPHYPLLREGS1_VREG_CFG__reg_off_lo__SHIFT 0xc
+-#define DC_COMBOPHYPLLREGS1_VREG_CFG__scale_driver__SHIFT 0xd
+-#define DC_COMBOPHYPLLREGS1_VREG_CFG__sel_bump__SHIFT 0xf
+-#define DC_COMBOPHYPLLREGS1_VREG_CFG__sel_rladder_x__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS1_VREG_CFG__short_rc_filt_x__SHIFT 0x11
+-#define DC_COMBOPHYPLLREGS1_VREG_CFG__vref_pwr_on__SHIFT 0x12
+-#define DC_COMBOPHYPLLREGS1_VREG_CFG__dpll_cfg_2__SHIFT 0x14
+-#define DC_COMBOPHYPLLREGS1_VREG_CFG__bleeder_ac_MASK 0x00000001L
+-#define DC_COMBOPHYPLLREGS1_VREG_CFG__bleeder_en_MASK 0x00000002L
+-#define DC_COMBOPHYPLLREGS1_VREG_CFG__is_1p2_MASK 0x00000004L
+-#define DC_COMBOPHYPLLREGS1_VREG_CFG__reg_obs_sel_MASK 0x00000018L
+-#define DC_COMBOPHYPLLREGS1_VREG_CFG__reg_on_mode_MASK 0x00000060L
+-#define DC_COMBOPHYPLLREGS1_VREG_CFG__rlad_tap_sel_MASK 0x00000780L
+-#define DC_COMBOPHYPLLREGS1_VREG_CFG__reg_off_hi_MASK 0x00000800L
+-#define DC_COMBOPHYPLLREGS1_VREG_CFG__reg_off_lo_MASK 0x00001000L
+-#define DC_COMBOPHYPLLREGS1_VREG_CFG__scale_driver_MASK 0x00006000L
+-#define DC_COMBOPHYPLLREGS1_VREG_CFG__sel_bump_MASK 0x00008000L
+-#define DC_COMBOPHYPLLREGS1_VREG_CFG__sel_rladder_x_MASK 0x00010000L
+-#define DC_COMBOPHYPLLREGS1_VREG_CFG__short_rc_filt_x_MASK 0x00020000L
+-#define DC_COMBOPHYPLLREGS1_VREG_CFG__vref_pwr_on_MASK 0x00040000L
+-#define DC_COMBOPHYPLLREGS1_VREG_CFG__dpll_cfg_2_MASK 0x0FF00000L
+-//DC_COMBOPHYPLLREGS1_OBSERVE0
+-#define DC_COMBOPHYPLLREGS1_OBSERVE0__lock_det_tdc_steps__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS1_OBSERVE0__clear_sticky_lock__SHIFT 0x6
+-#define DC_COMBOPHYPLLREGS1_OBSERVE0__lock_det_dis__SHIFT 0x8
+-#define DC_COMBOPHYPLLREGS1_OBSERVE0__dco_cfg__SHIFT 0xa
+-#define DC_COMBOPHYPLLREGS1_OBSERVE0__anaobs_sel__SHIFT 0x15
+-#define DC_COMBOPHYPLLREGS1_OBSERVE0__lock_det_tdc_steps_MASK 0x0000001FL
+-#define DC_COMBOPHYPLLREGS1_OBSERVE0__clear_sticky_lock_MASK 0x00000040L
+-#define DC_COMBOPHYPLLREGS1_OBSERVE0__lock_det_dis_MASK 0x00000100L
+-#define DC_COMBOPHYPLLREGS1_OBSERVE0__dco_cfg_MASK 0x0003FC00L
+-#define DC_COMBOPHYPLLREGS1_OBSERVE0__anaobs_sel_MASK 0x00E00000L
+-//DC_COMBOPHYPLLREGS1_OBSERVE1
+-#define DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_sel__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_trig_sel__SHIFT 0x5
+-#define DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_div__SHIFT 0xa
+-#define DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_trig_div__SHIFT 0xd
+-#define DC_COMBOPHYPLLREGS1_OBSERVE1__lock_timer__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_sel_MASK 0x0000000FL
+-#define DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_trig_sel_MASK 0x000001E0L
+-#define DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_div_MASK 0x00000C00L
+-#define DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_trig_div_MASK 0x00006000L
+-#define DC_COMBOPHYPLLREGS1_OBSERVE1__lock_timer_MASK 0x3FFF0000L
+-//DC_COMBOPHYPLLREGS1_DFT_OUT
+-#define DC_COMBOPHYPLLREGS1_DFT_OUT__dft_data__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS1_DFT_OUT__dft_data_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dcio_uniphy2_dispdec
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dc_combophycmregs2_dispdec
+-//DC_COMBOPHYCMREGS2_COMMON_FUSE1
+-#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_valid__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated0__SHIFT 0x1
+-#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_ron_override_val__SHIFT 0x3
+-#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated1__SHIFT 0x9
+-#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0xa
+-#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated2__SHIFT 0xc
+-#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_rtt_override_val__SHIFT 0xd
+-#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated3__SHIFT 0x13
+-#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0x14
+-#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_refresh_cal_en__SHIFT 0x16
+-#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_spare__SHIFT 0x17
+-#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_valid_MASK 0x00000001L
+-#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated0_MASK 0x00000006L
+-#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_ron_override_val_MASK 0x000001F8L
+-#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated1_MASK 0x00000200L
+-#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x00000C00L
+-#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated2_MASK 0x00001000L
+-#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_rtt_override_val_MASK 0x0007E000L
+-#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated3_MASK 0x00080000L
+-#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x00300000L
+-#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_refresh_cal_en_MASK 0x00400000L
+-#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_spare_MASK 0xFF800000L
+-//DC_COMBOPHYCMREGS2_COMMON_FUSE2
+-#define DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_valid__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_unpopulated__SHIFT 0x1
+-#define DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_tx_fifo_ptr__SHIFT 0x9
+-#define DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_spare__SHIFT 0xe
+-#define DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_valid_MASK 0x00000001L
+-#define DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_unpopulated_MASK 0x000001FEL
+-#define DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_tx_fifo_ptr_MASK 0x00003E00L
+-#define DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_spare_MASK 0xFFFFC000L
+-//DC_COMBOPHYCMREGS2_COMMON_FUSE3
+-#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_valid__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_unpopulated__SHIFT 0x1
+-#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_ei_det_thresh_sel__SHIFT 0xa
+-#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d
+-#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_valid_MASK 0x00000001L
+-#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_unpopulated_MASK 0x000003FEL
+-#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_ei_det_thresh_sel_MASK 0x00001C00L
+-#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_spare_MASK 0xE0000000L
+-//DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM
+-#define DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8
+-#define DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10
+-#define DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18
+-#define DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0x000000FFL
+-#define DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0x0000FF00L
+-#define DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0x00FF0000L
+-#define DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xFF000000L
+-//DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT
+-#define DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4
+-#define DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT__vprot_en__SHIFT 0xb
+-#define DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT__pgdelay_MASK 0x0000000FL
+-#define DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT__pgmask_MASK 0x000003F0L
+-#define DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT__vprot_en_MASK 0x00000800L
+-//DC_COMBOPHYCMREGS2_COMMON_TXCNTRL
+-#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__clkgate_dis__SHIFT 0x5
+-#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT 0x6
+-#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT 0x9
+-#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT 0xc
+-#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__dual_dvi_mstr_en__SHIFT 0xf
+-#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__dual_dvi_en__SHIFT 0x10
+-#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK 0x0000001FL
+-#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__clkgate_dis_MASK 0x00000020L
+-#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK 0x000001C0L
+-#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK 0x00000E00L
+-#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK 0x00007000L
+-#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__dual_dvi_mstr_en_MASK 0x00008000L
+-#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__dual_dvi_en_MASK 0x00010000L
+-//DC_COMBOPHYCMREGS2_COMMON_TMDP
+-#define DC_COMBOPHYCMREGS2_COMMON_TMDP__tmdp_spare__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS2_COMMON_TMDP__tmdp_spare_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS
+-#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_0_reset_l__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_1_reset_l__SHIFT 0x1
+-#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_2_reset_l__SHIFT 0x2
+-#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_3_reset_l__SHIFT 0x3
+-#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_4_reset_l__SHIFT 0x4
+-#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_5_reset_l__SHIFT 0x5
+-#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_6_reset_l__SHIFT 0x6
+-#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_7_reset_l__SHIFT 0x7
+-#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_0_reset_l_MASK 0x00000001L
+-#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_1_reset_l_MASK 0x00000002L
+-#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_2_reset_l_MASK 0x00000004L
+-#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_3_reset_l_MASK 0x00000008L
+-#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_4_reset_l_MASK 0x00000010L
+-#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_5_reset_l_MASK 0x00000020L
+-#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_6_reset_l_MASK 0x00000040L
+-#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_7_reset_l_MASK 0x00000080L
+-//DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL
+-#define DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT 0x1
+-#define DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT 0x15
+-#define DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__zcalcode_override_MASK 0x00000001L
+-#define DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK 0x0000003EL
+-#define DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK 0x00200000L
+-//DC_COMBOPHYCMREGS2_COMMON_DISP_RFU1
+-#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU1__rfu_value1__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU1__rfu_value1_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS2_COMMON_DISP_RFU2
+-#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU2__rfu_value2__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU2__rfu_value2_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS2_COMMON_DISP_RFU3
+-#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU3__rfu_value3__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU3__rfu_value3_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS2_COMMON_DISP_RFU4
+-#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU4__rfu_value4__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU4__rfu_value4_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS2_COMMON_DISP_RFU5
+-#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU5__rfu_value5__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU5__rfu_value5_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS2_COMMON_DISP_RFU6
+-#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU6__rfu_value6__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU6__rfu_value6_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS2_COMMON_DISP_RFU7
+-#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU7__rfu_value7__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU7__rfu_value7_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dc_combophytxregs2_dispdec
+-//DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK 0x00000100L
+-//DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0
+-#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0__txmarg_sel_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0__deemph_sel_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0__tx_margin_en_MASK 0x00000020L
+-//DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x1
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT 0xa
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT 0xc
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT 0xd
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT 0xe
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT 0xf
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT 0x10
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT 0x14
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT 0x16
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x00000006L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0x000000E0L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK 0x00000300L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK 0x00000C00L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK 0x00001000L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK 0x00002000L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK 0x00004000L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK 0x00008000L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK 0x000F0000L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK 0x00100000L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK 0x00C00000L
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0__rfu_value0__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0__rfu_value0_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0__rfu_value1__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0__rfu_value1_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0__rfu_value2__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0__rfu_value2_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0__rfu_value3__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0__rfu_value3_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0__rfu_value4__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0__rfu_value4_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0__rfu_value5__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0__rfu_value5_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0__rfu_value6__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0__rfu_value6_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0__rfu_value7__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0__rfu_value7_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0__rfu_value8__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0__rfu_value8_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0__rfu_value9__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0__rfu_value9_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0__rfu_value10__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0__rfu_value10_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0__rfu_value11__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0__rfu_value11_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0__rfu_value12__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0__rfu_value12_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK 0x00000100L
+-//DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1
+-#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1__txmarg_sel_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1__deemph_sel_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1__tx_margin_en_MASK 0x00000020L
+-//DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x1
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT 0xa
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT 0xc
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT 0xd
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT 0xe
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT 0xf
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT 0x10
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT 0x14
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT 0x16
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x00000006L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0x000000E0L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK 0x00000300L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK 0x00000C00L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK 0x00001000L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK 0x00002000L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK 0x00004000L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK 0x00008000L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK 0x000F0000L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK 0x00100000L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK 0x00C00000L
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1__rfu_value0__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1__rfu_value0_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1__rfu_value1__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1__rfu_value1_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1__rfu_value2__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1__rfu_value2_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1__rfu_value3__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1__rfu_value3_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1__rfu_value4__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1__rfu_value4_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1__rfu_value5__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1__rfu_value5_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1__rfu_value6__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1__rfu_value6_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1__rfu_value7__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1__rfu_value7_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1__rfu_value8__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1__rfu_value8_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1__rfu_value9__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1__rfu_value9_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1__rfu_value10__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1__rfu_value10_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1__rfu_value11__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1__rfu_value11_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1__rfu_value12__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1__rfu_value12_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK 0x00000100L
+-//DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2
+-#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2__txmarg_sel_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2__deemph_sel_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2__tx_margin_en_MASK 0x00000020L
+-//DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x1
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT 0xa
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT 0xc
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT 0xd
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT 0xe
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT 0xf
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT 0x10
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT 0x14
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT 0x16
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x00000006L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0x000000E0L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK 0x00000300L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK 0x00000C00L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK 0x00001000L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK 0x00002000L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK 0x00004000L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK 0x00008000L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK 0x000F0000L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK 0x00100000L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK 0x00C00000L
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2__rfu_value0__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2__rfu_value0_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2__rfu_value1__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2__rfu_value1_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2__rfu_value2__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2__rfu_value2_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2__rfu_value3__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2__rfu_value3_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2__rfu_value4__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2__rfu_value4_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2__rfu_value5__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2__rfu_value5_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2__rfu_value6__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2__rfu_value6_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2__rfu_value7__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2__rfu_value7_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2__rfu_value8__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2__rfu_value8_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2__rfu_value9__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2__rfu_value9_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2__rfu_value10__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2__rfu_value10_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2__rfu_value11__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2__rfu_value11_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2__rfu_value12__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2__rfu_value12_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK 0x00000100L
+-//DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3
+-#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3__txmarg_sel_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3__deemph_sel_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3__tx_margin_en_MASK 0x00000020L
+-//DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x1
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT 0xa
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT 0xc
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT 0xd
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT 0xe
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT 0xf
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT 0x10
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT 0x14
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT 0x16
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x00000006L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0x000000E0L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK 0x00000300L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK 0x00000C00L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK 0x00001000L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK 0x00002000L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK 0x00004000L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK 0x00008000L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK 0x000F0000L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK 0x00100000L
+-#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK 0x00C00000L
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3__rfu_value0__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3__rfu_value0_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3__rfu_value1__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3__rfu_value1_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3__rfu_value2__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3__rfu_value2_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3__rfu_value3__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3__rfu_value3_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3__rfu_value4__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3__rfu_value4_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3__rfu_value5__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3__rfu_value5_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3__rfu_value6__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3__rfu_value6_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3__rfu_value7__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3__rfu_value7_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3__rfu_value8__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3__rfu_value8_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3__rfu_value9__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3__rfu_value9_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3__rfu_value10__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3__rfu_value10_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3__rfu_value11__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3__rfu_value11_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3__rfu_value12__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3__rfu_value12_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dc_combophypllregs2_dispdec
+-//DC_COMBOPHYPLLREGS2_FREQ_CTRL0
+-#define DC_COMBOPHYPLLREGS2_FREQ_CTRL0__fcw0_frac__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS2_FREQ_CTRL0__fcw0_int__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS2_FREQ_CTRL0__fcw0_frac_MASK 0x0000FFFFL
+-#define DC_COMBOPHYPLLREGS2_FREQ_CTRL0__fcw0_int_MASK 0x01FF0000L
+-//DC_COMBOPHYPLLREGS2_FREQ_CTRL1
+-#define DC_COMBOPHYPLLREGS2_FREQ_CTRL1__fcw1_frac__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS2_FREQ_CTRL1__fcw1_int__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS2_FREQ_CTRL1__fcw1_frac_MASK 0x0000FFFFL
+-#define DC_COMBOPHYPLLREGS2_FREQ_CTRL1__fcw1_int_MASK 0x01FF0000L
+-//DC_COMBOPHYPLLREGS2_FREQ_CTRL2
+-#define DC_COMBOPHYPLLREGS2_FREQ_CTRL2__fcw_denom__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS2_FREQ_CTRL2__fcw_slew_frac__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS2_FREQ_CTRL2__fcw_denom_MASK 0x0000FFFFL
+-#define DC_COMBOPHYPLLREGS2_FREQ_CTRL2__fcw_slew_frac_MASK 0xFFFF0000L
+-//DC_COMBOPHYPLLREGS2_FREQ_CTRL3
+-#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__refclk_div__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__vco_pre_div__SHIFT 0x3
+-#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__fracn_en__SHIFT 0x6
+-#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__ssc_en__SHIFT 0x8
+-#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__fcw_sel__SHIFT 0xa
+-#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__freq_jump_en__SHIFT 0xc
+-#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__tdc_resolution__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__dpll_cfg_1__SHIFT 0x18
+-#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__refclk_div_MASK 0x00000003L
+-#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__vco_pre_div_MASK 0x00000018L
+-#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__fracn_en_MASK 0x00000040L
+-#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__ssc_en_MASK 0x00000100L
+-#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__fcw_sel_MASK 0x00000400L
+-#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__freq_jump_en_MASK 0x00001000L
+-#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__tdc_resolution_MASK 0x00FF0000L
+-#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__dpll_cfg_1_MASK 0xFF000000L
+-//DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE
+-#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gi_coarse_mant__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gi_coarse_exp__SHIFT 0x2
+-#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gp_coarse_mant__SHIFT 0x7
+-#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gp_coarse_exp__SHIFT 0xc
+-#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__nctl_coarse_res__SHIFT 0x11
+-#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT 0x18
+-#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gi_coarse_mant_MASK 0x00000003L
+-#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gi_coarse_exp_MASK 0x0000003CL
+-#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gp_coarse_mant_MASK 0x00000780L
+-#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gp_coarse_exp_MASK 0x0000F000L
+-#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__nctl_coarse_res_MASK 0x007E0000L
+-#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__nctl_coarse_frac_res_MASK 0x03000000L
+-//DC_COMBOPHYPLLREGS2_BW_CTRL_FINE
+-#define DC_COMBOPHYPLLREGS2_BW_CTRL_FINE__dpll_cfg_3__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS2_BW_CTRL_FINE__dpll_cfg_3_MASK 0x000003FFL
+-//DC_COMBOPHYPLLREGS2_CAL_CTRL
+-#define DC_COMBOPHYPLLREGS2_CAL_CTRL__bypass_freq_lock__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS2_CAL_CTRL__tdc_cal_en__SHIFT 0x1
+-#define DC_COMBOPHYPLLREGS2_CAL_CTRL__tdc_cal_ctrl__SHIFT 0x3
+-#define DC_COMBOPHYPLLREGS2_CAL_CTRL__meas_win_sel__SHIFT 0x9
+-#define DC_COMBOPHYPLLREGS2_CAL_CTRL__kdco_cal_dis__SHIFT 0xb
+-#define DC_COMBOPHYPLLREGS2_CAL_CTRL__kdco_ratio__SHIFT 0xd
+-#define DC_COMBOPHYPLLREGS2_CAL_CTRL__kdco_incr_cal_dis__SHIFT 0x16
+-#define DC_COMBOPHYPLLREGS2_CAL_CTRL__nctl_adj_dis__SHIFT 0x17
+-#define DC_COMBOPHYPLLREGS2_CAL_CTRL__refclk_rate__SHIFT 0x18
+-#define DC_COMBOPHYPLLREGS2_CAL_CTRL__bypass_freq_lock_MASK 0x00000001L
+-#define DC_COMBOPHYPLLREGS2_CAL_CTRL__tdc_cal_en_MASK 0x00000002L
+-#define DC_COMBOPHYPLLREGS2_CAL_CTRL__tdc_cal_ctrl_MASK 0x000001F8L
+-#define DC_COMBOPHYPLLREGS2_CAL_CTRL__meas_win_sel_MASK 0x00000600L
+-#define DC_COMBOPHYPLLREGS2_CAL_CTRL__kdco_cal_dis_MASK 0x00000800L
+-#define DC_COMBOPHYPLLREGS2_CAL_CTRL__kdco_ratio_MASK 0x001FE000L
+-#define DC_COMBOPHYPLLREGS2_CAL_CTRL__kdco_incr_cal_dis_MASK 0x00400000L
+-#define DC_COMBOPHYPLLREGS2_CAL_CTRL__nctl_adj_dis_MASK 0x00800000L
+-#define DC_COMBOPHYPLLREGS2_CAL_CTRL__refclk_rate_MASK 0xFF000000L
+-//DC_COMBOPHYPLLREGS2_LOOP_CTRL
+-#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__fbdiv_mask_en__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__fb_slip_dis__SHIFT 0x2
+-#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__clk_tdc_sel__SHIFT 0x4
+-#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__clk_nctl_sel__SHIFT 0x7
+-#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__sig_del_patt_sel__SHIFT 0xa
+-#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__nctl_sig_del_dis__SHIFT 0xc
+-#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__fbclk_track_refclk__SHIFT 0xe
+-#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__prbs_en__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__tdc_clk_gate_en__SHIFT 0x12
+-#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__phase_offset__SHIFT 0x14
+-#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__fbdiv_mask_en_MASK 0x00000001L
+-#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__fb_slip_dis_MASK 0x00000004L
+-#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__clk_tdc_sel_MASK 0x00000030L
+-#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__clk_nctl_sel_MASK 0x00000180L
+-#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__sig_del_patt_sel_MASK 0x00000400L
+-#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__nctl_sig_del_dis_MASK 0x00001000L
+-#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__fbclk_track_refclk_MASK 0x00004000L
+-#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__prbs_en_MASK 0x00010000L
+-#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__tdc_clk_gate_en_MASK 0x00040000L
+-#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__phase_offset_MASK 0x07F00000L
+-//DC_COMBOPHYPLLREGS2_VREG_CFG
+-#define DC_COMBOPHYPLLREGS2_VREG_CFG__bleeder_ac__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS2_VREG_CFG__bleeder_en__SHIFT 0x1
+-#define DC_COMBOPHYPLLREGS2_VREG_CFG__is_1p2__SHIFT 0x2
+-#define DC_COMBOPHYPLLREGS2_VREG_CFG__reg_obs_sel__SHIFT 0x3
+-#define DC_COMBOPHYPLLREGS2_VREG_CFG__reg_on_mode__SHIFT 0x5
+-#define DC_COMBOPHYPLLREGS2_VREG_CFG__rlad_tap_sel__SHIFT 0x7
+-#define DC_COMBOPHYPLLREGS2_VREG_CFG__reg_off_hi__SHIFT 0xb
+-#define DC_COMBOPHYPLLREGS2_VREG_CFG__reg_off_lo__SHIFT 0xc
+-#define DC_COMBOPHYPLLREGS2_VREG_CFG__scale_driver__SHIFT 0xd
+-#define DC_COMBOPHYPLLREGS2_VREG_CFG__sel_bump__SHIFT 0xf
+-#define DC_COMBOPHYPLLREGS2_VREG_CFG__sel_rladder_x__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS2_VREG_CFG__short_rc_filt_x__SHIFT 0x11
+-#define DC_COMBOPHYPLLREGS2_VREG_CFG__vref_pwr_on__SHIFT 0x12
+-#define DC_COMBOPHYPLLREGS2_VREG_CFG__dpll_cfg_2__SHIFT 0x14
+-#define DC_COMBOPHYPLLREGS2_VREG_CFG__bleeder_ac_MASK 0x00000001L
+-#define DC_COMBOPHYPLLREGS2_VREG_CFG__bleeder_en_MASK 0x00000002L
+-#define DC_COMBOPHYPLLREGS2_VREG_CFG__is_1p2_MASK 0x00000004L
+-#define DC_COMBOPHYPLLREGS2_VREG_CFG__reg_obs_sel_MASK 0x00000018L
+-#define DC_COMBOPHYPLLREGS2_VREG_CFG__reg_on_mode_MASK 0x00000060L
+-#define DC_COMBOPHYPLLREGS2_VREG_CFG__rlad_tap_sel_MASK 0x00000780L
+-#define DC_COMBOPHYPLLREGS2_VREG_CFG__reg_off_hi_MASK 0x00000800L
+-#define DC_COMBOPHYPLLREGS2_VREG_CFG__reg_off_lo_MASK 0x00001000L
+-#define DC_COMBOPHYPLLREGS2_VREG_CFG__scale_driver_MASK 0x00006000L
+-#define DC_COMBOPHYPLLREGS2_VREG_CFG__sel_bump_MASK 0x00008000L
+-#define DC_COMBOPHYPLLREGS2_VREG_CFG__sel_rladder_x_MASK 0x00010000L
+-#define DC_COMBOPHYPLLREGS2_VREG_CFG__short_rc_filt_x_MASK 0x00020000L
+-#define DC_COMBOPHYPLLREGS2_VREG_CFG__vref_pwr_on_MASK 0x00040000L
+-#define DC_COMBOPHYPLLREGS2_VREG_CFG__dpll_cfg_2_MASK 0x0FF00000L
+-//DC_COMBOPHYPLLREGS2_OBSERVE0
+-#define DC_COMBOPHYPLLREGS2_OBSERVE0__lock_det_tdc_steps__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS2_OBSERVE0__clear_sticky_lock__SHIFT 0x6
+-#define DC_COMBOPHYPLLREGS2_OBSERVE0__lock_det_dis__SHIFT 0x8
+-#define DC_COMBOPHYPLLREGS2_OBSERVE0__dco_cfg__SHIFT 0xa
+-#define DC_COMBOPHYPLLREGS2_OBSERVE0__anaobs_sel__SHIFT 0x15
+-#define DC_COMBOPHYPLLREGS2_OBSERVE0__lock_det_tdc_steps_MASK 0x0000001FL
+-#define DC_COMBOPHYPLLREGS2_OBSERVE0__clear_sticky_lock_MASK 0x00000040L
+-#define DC_COMBOPHYPLLREGS2_OBSERVE0__lock_det_dis_MASK 0x00000100L
+-#define DC_COMBOPHYPLLREGS2_OBSERVE0__dco_cfg_MASK 0x0003FC00L
+-#define DC_COMBOPHYPLLREGS2_OBSERVE0__anaobs_sel_MASK 0x00E00000L
+-//DC_COMBOPHYPLLREGS2_OBSERVE1
+-#define DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_sel__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_trig_sel__SHIFT 0x5
+-#define DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_div__SHIFT 0xa
+-#define DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_trig_div__SHIFT 0xd
+-#define DC_COMBOPHYPLLREGS2_OBSERVE1__lock_timer__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_sel_MASK 0x0000000FL
+-#define DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_trig_sel_MASK 0x000001E0L
+-#define DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_div_MASK 0x00000C00L
+-#define DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_trig_div_MASK 0x00006000L
+-#define DC_COMBOPHYPLLREGS2_OBSERVE1__lock_timer_MASK 0x3FFF0000L
+-//DC_COMBOPHYPLLREGS2_DFT_OUT
+-#define DC_COMBOPHYPLLREGS2_DFT_OUT__dft_data__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS2_DFT_OUT__dft_data_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dcio_uniphy3_dispdec
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dc_combophycmregs3_dispdec
+-//DC_COMBOPHYCMREGS3_COMMON_FUSE1
+-#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_valid__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated0__SHIFT 0x1
+-#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_ron_override_val__SHIFT 0x3
+-#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated1__SHIFT 0x9
+-#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0xa
+-#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated2__SHIFT 0xc
+-#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_rtt_override_val__SHIFT 0xd
+-#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated3__SHIFT 0x13
+-#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0x14
+-#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_refresh_cal_en__SHIFT 0x16
+-#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_spare__SHIFT 0x17
+-#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_valid_MASK 0x00000001L
+-#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated0_MASK 0x00000006L
+-#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_ron_override_val_MASK 0x000001F8L
+-#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated1_MASK 0x00000200L
+-#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x00000C00L
+-#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated2_MASK 0x00001000L
+-#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_rtt_override_val_MASK 0x0007E000L
+-#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated3_MASK 0x00080000L
+-#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x00300000L
+-#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_refresh_cal_en_MASK 0x00400000L
+-#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_spare_MASK 0xFF800000L
+-//DC_COMBOPHYCMREGS3_COMMON_FUSE2
+-#define DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_valid__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_unpopulated__SHIFT 0x1
+-#define DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_tx_fifo_ptr__SHIFT 0x9
+-#define DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_spare__SHIFT 0xe
+-#define DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_valid_MASK 0x00000001L
+-#define DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_unpopulated_MASK 0x000001FEL
+-#define DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_tx_fifo_ptr_MASK 0x00003E00L
+-#define DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_spare_MASK 0xFFFFC000L
+-//DC_COMBOPHYCMREGS3_COMMON_FUSE3
+-#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_valid__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_unpopulated__SHIFT 0x1
+-#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_ei_det_thresh_sel__SHIFT 0xa
+-#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d
+-#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_valid_MASK 0x00000001L
+-#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_unpopulated_MASK 0x000003FEL
+-#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_ei_det_thresh_sel_MASK 0x00001C00L
+-#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_spare_MASK 0xE0000000L
+-//DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM
+-#define DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8
+-#define DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10
+-#define DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18
+-#define DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0x000000FFL
+-#define DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0x0000FF00L
+-#define DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0x00FF0000L
+-#define DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xFF000000L
+-//DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT
+-#define DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4
+-#define DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT__vprot_en__SHIFT 0xb
+-#define DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT__pgdelay_MASK 0x0000000FL
+-#define DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT__pgmask_MASK 0x000003F0L
+-#define DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT__vprot_en_MASK 0x00000800L
+-//DC_COMBOPHYCMREGS3_COMMON_TXCNTRL
+-#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__clkgate_dis__SHIFT 0x5
+-#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT 0x6
+-#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT 0x9
+-#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT 0xc
+-#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__dual_dvi_mstr_en__SHIFT 0xf
+-#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__dual_dvi_en__SHIFT 0x10
+-#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK 0x0000001FL
+-#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__clkgate_dis_MASK 0x00000020L
+-#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK 0x000001C0L
+-#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK 0x00000E00L
+-#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK 0x00007000L
+-#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__dual_dvi_mstr_en_MASK 0x00008000L
+-#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__dual_dvi_en_MASK 0x00010000L
+-//DC_COMBOPHYCMREGS3_COMMON_TMDP
+-#define DC_COMBOPHYCMREGS3_COMMON_TMDP__tmdp_spare__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS3_COMMON_TMDP__tmdp_spare_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS
+-#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_0_reset_l__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_1_reset_l__SHIFT 0x1
+-#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_2_reset_l__SHIFT 0x2
+-#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_3_reset_l__SHIFT 0x3
+-#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_4_reset_l__SHIFT 0x4
+-#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_5_reset_l__SHIFT 0x5
+-#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_6_reset_l__SHIFT 0x6
+-#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_7_reset_l__SHIFT 0x7
+-#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_0_reset_l_MASK 0x00000001L
+-#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_1_reset_l_MASK 0x00000002L
+-#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_2_reset_l_MASK 0x00000004L
+-#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_3_reset_l_MASK 0x00000008L
+-#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_4_reset_l_MASK 0x00000010L
+-#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_5_reset_l_MASK 0x00000020L
+-#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_6_reset_l_MASK 0x00000040L
+-#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_7_reset_l_MASK 0x00000080L
+-//DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL
+-#define DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT 0x1
+-#define DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT 0x15
+-#define DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__zcalcode_override_MASK 0x00000001L
+-#define DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK 0x0000003EL
+-#define DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK 0x00200000L
+-//DC_COMBOPHYCMREGS3_COMMON_DISP_RFU1
+-#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU1__rfu_value1__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU1__rfu_value1_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS3_COMMON_DISP_RFU2
+-#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU2__rfu_value2__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU2__rfu_value2_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS3_COMMON_DISP_RFU3
+-#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU3__rfu_value3__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU3__rfu_value3_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS3_COMMON_DISP_RFU4
+-#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU4__rfu_value4__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU4__rfu_value4_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS3_COMMON_DISP_RFU5
+-#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU5__rfu_value5__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU5__rfu_value5_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS3_COMMON_DISP_RFU6
+-#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU6__rfu_value6__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU6__rfu_value6_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS3_COMMON_DISP_RFU7
+-#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU7__rfu_value7__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU7__rfu_value7_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dc_combophytxregs3_dispdec
+-//DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK 0x00000100L
+-//DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0
+-#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0__txmarg_sel_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0__deemph_sel_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0__tx_margin_en_MASK 0x00000020L
+-//DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x1
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT 0xa
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT 0xc
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT 0xd
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT 0xe
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT 0xf
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT 0x10
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT 0x14
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT 0x16
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x00000006L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0x000000E0L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK 0x00000300L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK 0x00000C00L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK 0x00001000L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK 0x00002000L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK 0x00004000L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK 0x00008000L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK 0x000F0000L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK 0x00100000L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK 0x00C00000L
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0__rfu_value0__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0__rfu_value0_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0__rfu_value1__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0__rfu_value1_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0__rfu_value2__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0__rfu_value2_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0__rfu_value3__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0__rfu_value3_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0__rfu_value4__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0__rfu_value4_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0__rfu_value5__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0__rfu_value5_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0__rfu_value6__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0__rfu_value6_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0__rfu_value7__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0__rfu_value7_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0__rfu_value8__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0__rfu_value8_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0__rfu_value9__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0__rfu_value9_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0__rfu_value10__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0__rfu_value10_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0__rfu_value11__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0__rfu_value11_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0__rfu_value12__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0__rfu_value12_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK 0x00000100L
+-//DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1
+-#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1__txmarg_sel_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1__deemph_sel_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1__tx_margin_en_MASK 0x00000020L
+-//DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x1
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT 0xa
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT 0xc
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT 0xd
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT 0xe
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT 0xf
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT 0x10
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT 0x14
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT 0x16
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x00000006L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0x000000E0L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK 0x00000300L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK 0x00000C00L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK 0x00001000L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK 0x00002000L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK 0x00004000L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK 0x00008000L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK 0x000F0000L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK 0x00100000L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK 0x00C00000L
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1__rfu_value0__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1__rfu_value0_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1__rfu_value1__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1__rfu_value1_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1__rfu_value2__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1__rfu_value2_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1__rfu_value3__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1__rfu_value3_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1__rfu_value4__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1__rfu_value4_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1__rfu_value5__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1__rfu_value5_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1__rfu_value6__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1__rfu_value6_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1__rfu_value7__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1__rfu_value7_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1__rfu_value8__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1__rfu_value8_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1__rfu_value9__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1__rfu_value9_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1__rfu_value10__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1__rfu_value10_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1__rfu_value11__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1__rfu_value11_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1__rfu_value12__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1__rfu_value12_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK 0x00000100L
+-//DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2
+-#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2__txmarg_sel_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2__deemph_sel_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2__tx_margin_en_MASK 0x00000020L
+-//DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x1
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT 0xa
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT 0xc
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT 0xd
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT 0xe
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT 0xf
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT 0x10
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT 0x14
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT 0x16
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x00000006L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0x000000E0L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK 0x00000300L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK 0x00000C00L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK 0x00001000L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK 0x00002000L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK 0x00004000L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK 0x00008000L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK 0x000F0000L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK 0x00100000L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK 0x00C00000L
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2__rfu_value0__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2__rfu_value0_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2__rfu_value1__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2__rfu_value1_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2__rfu_value2__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2__rfu_value2_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2__rfu_value3__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2__rfu_value3_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2__rfu_value4__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2__rfu_value4_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2__rfu_value5__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2__rfu_value5_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2__rfu_value6__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2__rfu_value6_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2__rfu_value7__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2__rfu_value7_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2__rfu_value8__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2__rfu_value8_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2__rfu_value9__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2__rfu_value9_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2__rfu_value10__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2__rfu_value10_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2__rfu_value11__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2__rfu_value11_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2__rfu_value12__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2__rfu_value12_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK 0x00000100L
+-//DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3
+-#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3__txmarg_sel_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3__deemph_sel_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3__tx_margin_en_MASK 0x00000020L
+-//DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x1
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT 0xa
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT 0xc
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT 0xd
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT 0xe
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT 0xf
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT 0x10
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT 0x14
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT 0x16
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x00000006L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0x000000E0L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK 0x00000300L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK 0x00000C00L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK 0x00001000L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK 0x00002000L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK 0x00004000L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK 0x00008000L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK 0x000F0000L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK 0x00100000L
+-#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK 0x00C00000L
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3__rfu_value0__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3__rfu_value0_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3__rfu_value1__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3__rfu_value1_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3__rfu_value2__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3__rfu_value2_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3__rfu_value3__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3__rfu_value3_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3__rfu_value4__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3__rfu_value4_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3__rfu_value5__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3__rfu_value5_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3__rfu_value6__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3__rfu_value6_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3__rfu_value7__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3__rfu_value7_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3__rfu_value8__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3__rfu_value8_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3__rfu_value9__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3__rfu_value9_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3__rfu_value10__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3__rfu_value10_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3__rfu_value11__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3__rfu_value11_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3__rfu_value12__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3__rfu_value12_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dc_combophypllregs3_dispdec
+-//DC_COMBOPHYPLLREGS3_FREQ_CTRL0
+-#define DC_COMBOPHYPLLREGS3_FREQ_CTRL0__fcw0_frac__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS3_FREQ_CTRL0__fcw0_int__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS3_FREQ_CTRL0__fcw0_frac_MASK 0x0000FFFFL
+-#define DC_COMBOPHYPLLREGS3_FREQ_CTRL0__fcw0_int_MASK 0x01FF0000L
+-//DC_COMBOPHYPLLREGS3_FREQ_CTRL1
+-#define DC_COMBOPHYPLLREGS3_FREQ_CTRL1__fcw1_frac__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS3_FREQ_CTRL1__fcw1_int__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS3_FREQ_CTRL1__fcw1_frac_MASK 0x0000FFFFL
+-#define DC_COMBOPHYPLLREGS3_FREQ_CTRL1__fcw1_int_MASK 0x01FF0000L
+-//DC_COMBOPHYPLLREGS3_FREQ_CTRL2
+-#define DC_COMBOPHYPLLREGS3_FREQ_CTRL2__fcw_denom__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS3_FREQ_CTRL2__fcw_slew_frac__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS3_FREQ_CTRL2__fcw_denom_MASK 0x0000FFFFL
+-#define DC_COMBOPHYPLLREGS3_FREQ_CTRL2__fcw_slew_frac_MASK 0xFFFF0000L
+-//DC_COMBOPHYPLLREGS3_FREQ_CTRL3
+-#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__refclk_div__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__vco_pre_div__SHIFT 0x3
+-#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__fracn_en__SHIFT 0x6
+-#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__ssc_en__SHIFT 0x8
+-#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__fcw_sel__SHIFT 0xa
+-#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__freq_jump_en__SHIFT 0xc
+-#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__tdc_resolution__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__dpll_cfg_1__SHIFT 0x18
+-#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__refclk_div_MASK 0x00000003L
+-#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__vco_pre_div_MASK 0x00000018L
+-#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__fracn_en_MASK 0x00000040L
+-#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__ssc_en_MASK 0x00000100L
+-#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__fcw_sel_MASK 0x00000400L
+-#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__freq_jump_en_MASK 0x00001000L
+-#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__tdc_resolution_MASK 0x00FF0000L
+-#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__dpll_cfg_1_MASK 0xFF000000L
+-//DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE
+-#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gi_coarse_mant__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gi_coarse_exp__SHIFT 0x2
+-#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gp_coarse_mant__SHIFT 0x7
+-#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gp_coarse_exp__SHIFT 0xc
+-#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__nctl_coarse_res__SHIFT 0x11
+-#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT 0x18
+-#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gi_coarse_mant_MASK 0x00000003L
+-#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gi_coarse_exp_MASK 0x0000003CL
+-#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gp_coarse_mant_MASK 0x00000780L
+-#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gp_coarse_exp_MASK 0x0000F000L
+-#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__nctl_coarse_res_MASK 0x007E0000L
+-#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__nctl_coarse_frac_res_MASK 0x03000000L
+-//DC_COMBOPHYPLLREGS3_BW_CTRL_FINE
+-#define DC_COMBOPHYPLLREGS3_BW_CTRL_FINE__dpll_cfg_3__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS3_BW_CTRL_FINE__dpll_cfg_3_MASK 0x000003FFL
+-//DC_COMBOPHYPLLREGS3_CAL_CTRL
+-#define DC_COMBOPHYPLLREGS3_CAL_CTRL__bypass_freq_lock__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS3_CAL_CTRL__tdc_cal_en__SHIFT 0x1
+-#define DC_COMBOPHYPLLREGS3_CAL_CTRL__tdc_cal_ctrl__SHIFT 0x3
+-#define DC_COMBOPHYPLLREGS3_CAL_CTRL__meas_win_sel__SHIFT 0x9
+-#define DC_COMBOPHYPLLREGS3_CAL_CTRL__kdco_cal_dis__SHIFT 0xb
+-#define DC_COMBOPHYPLLREGS3_CAL_CTRL__kdco_ratio__SHIFT 0xd
+-#define DC_COMBOPHYPLLREGS3_CAL_CTRL__kdco_incr_cal_dis__SHIFT 0x16
+-#define DC_COMBOPHYPLLREGS3_CAL_CTRL__nctl_adj_dis__SHIFT 0x17
+-#define DC_COMBOPHYPLLREGS3_CAL_CTRL__refclk_rate__SHIFT 0x18
+-#define DC_COMBOPHYPLLREGS3_CAL_CTRL__bypass_freq_lock_MASK 0x00000001L
+-#define DC_COMBOPHYPLLREGS3_CAL_CTRL__tdc_cal_en_MASK 0x00000002L
+-#define DC_COMBOPHYPLLREGS3_CAL_CTRL__tdc_cal_ctrl_MASK 0x000001F8L
+-#define DC_COMBOPHYPLLREGS3_CAL_CTRL__meas_win_sel_MASK 0x00000600L
+-#define DC_COMBOPHYPLLREGS3_CAL_CTRL__kdco_cal_dis_MASK 0x00000800L
+-#define DC_COMBOPHYPLLREGS3_CAL_CTRL__kdco_ratio_MASK 0x001FE000L
+-#define DC_COMBOPHYPLLREGS3_CAL_CTRL__kdco_incr_cal_dis_MASK 0x00400000L
+-#define DC_COMBOPHYPLLREGS3_CAL_CTRL__nctl_adj_dis_MASK 0x00800000L
+-#define DC_COMBOPHYPLLREGS3_CAL_CTRL__refclk_rate_MASK 0xFF000000L
+-//DC_COMBOPHYPLLREGS3_LOOP_CTRL
+-#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__fbdiv_mask_en__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__fb_slip_dis__SHIFT 0x2
+-#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__clk_tdc_sel__SHIFT 0x4
+-#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__clk_nctl_sel__SHIFT 0x7
+-#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__sig_del_patt_sel__SHIFT 0xa
+-#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__nctl_sig_del_dis__SHIFT 0xc
+-#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__fbclk_track_refclk__SHIFT 0xe
+-#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__prbs_en__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__tdc_clk_gate_en__SHIFT 0x12
+-#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__phase_offset__SHIFT 0x14
+-#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__fbdiv_mask_en_MASK 0x00000001L
+-#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__fb_slip_dis_MASK 0x00000004L
+-#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__clk_tdc_sel_MASK 0x00000030L
+-#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__clk_nctl_sel_MASK 0x00000180L
+-#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__sig_del_patt_sel_MASK 0x00000400L
+-#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__nctl_sig_del_dis_MASK 0x00001000L
+-#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__fbclk_track_refclk_MASK 0x00004000L
+-#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__prbs_en_MASK 0x00010000L
+-#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__tdc_clk_gate_en_MASK 0x00040000L
+-#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__phase_offset_MASK 0x07F00000L
+-//DC_COMBOPHYPLLREGS3_VREG_CFG
+-#define DC_COMBOPHYPLLREGS3_VREG_CFG__bleeder_ac__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS3_VREG_CFG__bleeder_en__SHIFT 0x1
+-#define DC_COMBOPHYPLLREGS3_VREG_CFG__is_1p2__SHIFT 0x2
+-#define DC_COMBOPHYPLLREGS3_VREG_CFG__reg_obs_sel__SHIFT 0x3
+-#define DC_COMBOPHYPLLREGS3_VREG_CFG__reg_on_mode__SHIFT 0x5
+-#define DC_COMBOPHYPLLREGS3_VREG_CFG__rlad_tap_sel__SHIFT 0x7
+-#define DC_COMBOPHYPLLREGS3_VREG_CFG__reg_off_hi__SHIFT 0xb
+-#define DC_COMBOPHYPLLREGS3_VREG_CFG__reg_off_lo__SHIFT 0xc
+-#define DC_COMBOPHYPLLREGS3_VREG_CFG__scale_driver__SHIFT 0xd
+-#define DC_COMBOPHYPLLREGS3_VREG_CFG__sel_bump__SHIFT 0xf
+-#define DC_COMBOPHYPLLREGS3_VREG_CFG__sel_rladder_x__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS3_VREG_CFG__short_rc_filt_x__SHIFT 0x11
+-#define DC_COMBOPHYPLLREGS3_VREG_CFG__vref_pwr_on__SHIFT 0x12
+-#define DC_COMBOPHYPLLREGS3_VREG_CFG__dpll_cfg_2__SHIFT 0x14
+-#define DC_COMBOPHYPLLREGS3_VREG_CFG__bleeder_ac_MASK 0x00000001L
+-#define DC_COMBOPHYPLLREGS3_VREG_CFG__bleeder_en_MASK 0x00000002L
+-#define DC_COMBOPHYPLLREGS3_VREG_CFG__is_1p2_MASK 0x00000004L
+-#define DC_COMBOPHYPLLREGS3_VREG_CFG__reg_obs_sel_MASK 0x00000018L
+-#define DC_COMBOPHYPLLREGS3_VREG_CFG__reg_on_mode_MASK 0x00000060L
+-#define DC_COMBOPHYPLLREGS3_VREG_CFG__rlad_tap_sel_MASK 0x00000780L
+-#define DC_COMBOPHYPLLREGS3_VREG_CFG__reg_off_hi_MASK 0x00000800L
+-#define DC_COMBOPHYPLLREGS3_VREG_CFG__reg_off_lo_MASK 0x00001000L
+-#define DC_COMBOPHYPLLREGS3_VREG_CFG__scale_driver_MASK 0x00006000L
+-#define DC_COMBOPHYPLLREGS3_VREG_CFG__sel_bump_MASK 0x00008000L
+-#define DC_COMBOPHYPLLREGS3_VREG_CFG__sel_rladder_x_MASK 0x00010000L
+-#define DC_COMBOPHYPLLREGS3_VREG_CFG__short_rc_filt_x_MASK 0x00020000L
+-#define DC_COMBOPHYPLLREGS3_VREG_CFG__vref_pwr_on_MASK 0x00040000L
+-#define DC_COMBOPHYPLLREGS3_VREG_CFG__dpll_cfg_2_MASK 0x0FF00000L
+-//DC_COMBOPHYPLLREGS3_OBSERVE0
+-#define DC_COMBOPHYPLLREGS3_OBSERVE0__lock_det_tdc_steps__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS3_OBSERVE0__clear_sticky_lock__SHIFT 0x6
+-#define DC_COMBOPHYPLLREGS3_OBSERVE0__lock_det_dis__SHIFT 0x8
+-#define DC_COMBOPHYPLLREGS3_OBSERVE0__dco_cfg__SHIFT 0xa
+-#define DC_COMBOPHYPLLREGS3_OBSERVE0__anaobs_sel__SHIFT 0x15
+-#define DC_COMBOPHYPLLREGS3_OBSERVE0__lock_det_tdc_steps_MASK 0x0000001FL
+-#define DC_COMBOPHYPLLREGS3_OBSERVE0__clear_sticky_lock_MASK 0x00000040L
+-#define DC_COMBOPHYPLLREGS3_OBSERVE0__lock_det_dis_MASK 0x00000100L
+-#define DC_COMBOPHYPLLREGS3_OBSERVE0__dco_cfg_MASK 0x0003FC00L
+-#define DC_COMBOPHYPLLREGS3_OBSERVE0__anaobs_sel_MASK 0x00E00000L
+-//DC_COMBOPHYPLLREGS3_OBSERVE1
+-#define DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_sel__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_trig_sel__SHIFT 0x5
+-#define DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_div__SHIFT 0xa
+-#define DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_trig_div__SHIFT 0xd
+-#define DC_COMBOPHYPLLREGS3_OBSERVE1__lock_timer__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_sel_MASK 0x0000000FL
+-#define DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_trig_sel_MASK 0x000001E0L
+-#define DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_div_MASK 0x00000C00L
+-#define DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_trig_div_MASK 0x00006000L
+-#define DC_COMBOPHYPLLREGS3_OBSERVE1__lock_timer_MASK 0x3FFF0000L
+-//DC_COMBOPHYPLLREGS3_DFT_OUT
+-#define DC_COMBOPHYPLLREGS3_DFT_OUT__dft_data__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS3_DFT_OUT__dft_data_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dcio_uniphy4_dispdec
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dc_combophycmregs4_dispdec
+-//DC_COMBOPHYCMREGS4_COMMON_FUSE1
+-#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_valid__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_unpopulated0__SHIFT 0x1
+-#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_ron_override_val__SHIFT 0x3
+-#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_unpopulated1__SHIFT 0x9
+-#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0xa
+-#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_unpopulated2__SHIFT 0xc
+-#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_rtt_override_val__SHIFT 0xd
+-#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_unpopulated3__SHIFT 0x13
+-#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0x14
+-#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_refresh_cal_en__SHIFT 0x16
+-#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_spare__SHIFT 0x17
+-#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_valid_MASK 0x00000001L
+-#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_unpopulated0_MASK 0x00000006L
+-#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_ron_override_val_MASK 0x000001F8L
+-#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_unpopulated1_MASK 0x00000200L
+-#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x00000C00L
+-#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_unpopulated2_MASK 0x00001000L
+-#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_rtt_override_val_MASK 0x0007E000L
+-#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_unpopulated3_MASK 0x00080000L
+-#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x00300000L
+-#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_refresh_cal_en_MASK 0x00400000L
+-#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_spare_MASK 0xFF800000L
+-//DC_COMBOPHYCMREGS4_COMMON_FUSE2
+-#define DC_COMBOPHYCMREGS4_COMMON_FUSE2__fuse2_valid__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS4_COMMON_FUSE2__fuse2_unpopulated__SHIFT 0x1
+-#define DC_COMBOPHYCMREGS4_COMMON_FUSE2__fuse2_tx_fifo_ptr__SHIFT 0x9
+-#define DC_COMBOPHYCMREGS4_COMMON_FUSE2__fuse2_spare__SHIFT 0xe
+-#define DC_COMBOPHYCMREGS4_COMMON_FUSE2__fuse2_valid_MASK 0x00000001L
+-#define DC_COMBOPHYCMREGS4_COMMON_FUSE2__fuse2_unpopulated_MASK 0x000001FEL
+-#define DC_COMBOPHYCMREGS4_COMMON_FUSE2__fuse2_tx_fifo_ptr_MASK 0x00003E00L
+-#define DC_COMBOPHYCMREGS4_COMMON_FUSE2__fuse2_spare_MASK 0xFFFFC000L
+-//DC_COMBOPHYCMREGS4_COMMON_FUSE3
+-#define DC_COMBOPHYCMREGS4_COMMON_FUSE3__fuse3_valid__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS4_COMMON_FUSE3__fuse3_unpopulated__SHIFT 0x1
+-#define DC_COMBOPHYCMREGS4_COMMON_FUSE3__fuse3_ei_det_thresh_sel__SHIFT 0xa
+-#define DC_COMBOPHYCMREGS4_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d
+-#define DC_COMBOPHYCMREGS4_COMMON_FUSE3__fuse3_valid_MASK 0x00000001L
+-#define DC_COMBOPHYCMREGS4_COMMON_FUSE3__fuse3_unpopulated_MASK 0x000003FEL
+-#define DC_COMBOPHYCMREGS4_COMMON_FUSE3__fuse3_ei_det_thresh_sel_MASK 0x00001C00L
+-#define DC_COMBOPHYCMREGS4_COMMON_FUSE3__fuse3_spare_MASK 0xE0000000L
+-//DC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM
+-#define DC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8
+-#define DC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10
+-#define DC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18
+-#define DC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0x000000FFL
+-#define DC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0x0000FF00L
+-#define DC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0x00FF0000L
+-#define DC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xFF000000L
+-//DC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT
+-#define DC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4
+-#define DC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT__vprot_en__SHIFT 0xb
+-#define DC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT__pgdelay_MASK 0x0000000FL
+-#define DC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT__pgmask_MASK 0x000003F0L
+-#define DC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT__vprot_en_MASK 0x00000800L
+-//DC_COMBOPHYCMREGS4_COMMON_TXCNTRL
+-#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__clkgate_dis__SHIFT 0x5
+-#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT 0x6
+-#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT 0x9
+-#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT 0xc
+-#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__dual_dvi_mstr_en__SHIFT 0xf
+-#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__dual_dvi_en__SHIFT 0x10
+-#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK 0x0000001FL
+-#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__clkgate_dis_MASK 0x00000020L
+-#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK 0x000001C0L
+-#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK 0x00000E00L
+-#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK 0x00007000L
+-#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__dual_dvi_mstr_en_MASK 0x00008000L
+-#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__dual_dvi_en_MASK 0x00010000L
+-//DC_COMBOPHYCMREGS4_COMMON_TMDP
+-#define DC_COMBOPHYCMREGS4_COMMON_TMDP__tmdp_spare__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS4_COMMON_TMDP__tmdp_spare_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS
+-#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_0_reset_l__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_1_reset_l__SHIFT 0x1
+-#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_2_reset_l__SHIFT 0x2
+-#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_3_reset_l__SHIFT 0x3
+-#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_4_reset_l__SHIFT 0x4
+-#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_5_reset_l__SHIFT 0x5
+-#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_6_reset_l__SHIFT 0x6
+-#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_7_reset_l__SHIFT 0x7
+-#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_0_reset_l_MASK 0x00000001L
+-#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_1_reset_l_MASK 0x00000002L
+-#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_2_reset_l_MASK 0x00000004L
+-#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_3_reset_l_MASK 0x00000008L
+-#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_4_reset_l_MASK 0x00000010L
+-#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_5_reset_l_MASK 0x00000020L
+-#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_6_reset_l_MASK 0x00000040L
+-#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_7_reset_l_MASK 0x00000080L
+-//DC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL
+-#define DC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT 0x1
+-#define DC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT 0x15
+-#define DC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL__zcalcode_override_MASK 0x00000001L
+-#define DC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK 0x0000003EL
+-#define DC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK 0x00200000L
+-//DC_COMBOPHYCMREGS4_COMMON_DISP_RFU1
+-#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU1__rfu_value1__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU1__rfu_value1_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS4_COMMON_DISP_RFU2
+-#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU2__rfu_value2__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU2__rfu_value2_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS4_COMMON_DISP_RFU3
+-#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU3__rfu_value3__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU3__rfu_value3_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS4_COMMON_DISP_RFU4
+-#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU4__rfu_value4__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU4__rfu_value4_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS4_COMMON_DISP_RFU5
+-#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU5__rfu_value5__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU5__rfu_value5_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS4_COMMON_DISP_RFU6
+-#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU6__rfu_value6__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU6__rfu_value6_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS4_COMMON_DISP_RFU7
+-#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU7__rfu_value7__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU7__rfu_value7_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dc_combophytxregs4_dispdec
+-//DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK 0x00000100L
+-//DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0
+-#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0__txmarg_sel_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0__deemph_sel_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0__tx_margin_en_MASK 0x00000020L
+-//DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x1
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT 0xa
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT 0xc
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT 0xd
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT 0xe
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT 0xf
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT 0x10
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT 0x14
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT 0x16
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x00000006L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0x000000E0L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK 0x00000300L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK 0x00000C00L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK 0x00001000L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK 0x00002000L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK 0x00004000L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK 0x00008000L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK 0x000F0000L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK 0x00100000L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK 0x00C00000L
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0__rfu_value0__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0__rfu_value0_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0__rfu_value1__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0__rfu_value1_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0__rfu_value2__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0__rfu_value2_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0__rfu_value3__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0__rfu_value3_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0__rfu_value4__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0__rfu_value4_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0__rfu_value5__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0__rfu_value5_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0__rfu_value6__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0__rfu_value6_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0__rfu_value7__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0__rfu_value7_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0__rfu_value8__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0__rfu_value8_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0__rfu_value9__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0__rfu_value9_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0__rfu_value10__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0__rfu_value10_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0__rfu_value11__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0__rfu_value11_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0__rfu_value12__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0__rfu_value12_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK 0x00000100L
+-//DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1
+-#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1__txmarg_sel_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1__deemph_sel_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1__tx_margin_en_MASK 0x00000020L
+-//DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x1
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT 0xa
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT 0xc
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT 0xd
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT 0xe
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT 0xf
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT 0x10
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT 0x14
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT 0x16
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x00000006L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0x000000E0L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK 0x00000300L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK 0x00000C00L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK 0x00001000L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK 0x00002000L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK 0x00004000L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK 0x00008000L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK 0x000F0000L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK 0x00100000L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK 0x00C00000L
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1__rfu_value0__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1__rfu_value0_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1__rfu_value1__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1__rfu_value1_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1__rfu_value2__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1__rfu_value2_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1__rfu_value3__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1__rfu_value3_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1__rfu_value4__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1__rfu_value4_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1__rfu_value5__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1__rfu_value5_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1__rfu_value6__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1__rfu_value6_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1__rfu_value7__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1__rfu_value7_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1__rfu_value8__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1__rfu_value8_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1__rfu_value9__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1__rfu_value9_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1__rfu_value10__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1__rfu_value10_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1__rfu_value11__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1__rfu_value11_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1__rfu_value12__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1__rfu_value12_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK 0x00000100L
+-//DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2
+-#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2__txmarg_sel_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2__deemph_sel_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2__tx_margin_en_MASK 0x00000020L
+-//DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x1
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT 0xa
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT 0xc
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT 0xd
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT 0xe
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT 0xf
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT 0x10
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT 0x14
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT 0x16
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x00000006L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0x000000E0L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK 0x00000300L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK 0x00000C00L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK 0x00001000L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK 0x00002000L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK 0x00004000L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK 0x00008000L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK 0x000F0000L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK 0x00100000L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK 0x00C00000L
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2__rfu_value0__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2__rfu_value0_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2__rfu_value1__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2__rfu_value1_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2__rfu_value2__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2__rfu_value2_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2__rfu_value3__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2__rfu_value3_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2__rfu_value4__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2__rfu_value4_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2__rfu_value5__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2__rfu_value5_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2__rfu_value6__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2__rfu_value6_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2__rfu_value7__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2__rfu_value7_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2__rfu_value8__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2__rfu_value8_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2__rfu_value9__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2__rfu_value9_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2__rfu_value10__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2__rfu_value10_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2__rfu_value11__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2__rfu_value11_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2__rfu_value12__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2__rfu_value12_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK 0x00000100L
+-//DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3
+-#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3__txmarg_sel_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3__deemph_sel_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3__tx_margin_en_MASK 0x00000020L
+-//DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x1
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT 0xa
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT 0xc
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT 0xd
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT 0xe
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT 0xf
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT 0x10
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT 0x14
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT 0x16
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x00000006L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0x000000E0L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK 0x00000300L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK 0x00000C00L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK 0x00001000L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK 0x00002000L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK 0x00004000L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK 0x00008000L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK 0x000F0000L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK 0x00100000L
+-#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK 0x00C00000L
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3__rfu_value0__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3__rfu_value0_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3__rfu_value1__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3__rfu_value1_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3__rfu_value2__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3__rfu_value2_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3__rfu_value3__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3__rfu_value3_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3__rfu_value4__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3__rfu_value4_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3__rfu_value5__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3__rfu_value5_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3__rfu_value6__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3__rfu_value6_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3__rfu_value7__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3__rfu_value7_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3__rfu_value8__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3__rfu_value8_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3__rfu_value9__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3__rfu_value9_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3__rfu_value10__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3__rfu_value10_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3__rfu_value11__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3__rfu_value11_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3__rfu_value12__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3__rfu_value12_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dc_combophypllregs4_dispdec
+-//DC_COMBOPHYPLLREGS4_FREQ_CTRL0
+-#define DC_COMBOPHYPLLREGS4_FREQ_CTRL0__fcw0_frac__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS4_FREQ_CTRL0__fcw0_int__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS4_FREQ_CTRL0__fcw0_frac_MASK 0x0000FFFFL
+-#define DC_COMBOPHYPLLREGS4_FREQ_CTRL0__fcw0_int_MASK 0x01FF0000L
+-//DC_COMBOPHYPLLREGS4_FREQ_CTRL1
+-#define DC_COMBOPHYPLLREGS4_FREQ_CTRL1__fcw1_frac__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS4_FREQ_CTRL1__fcw1_int__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS4_FREQ_CTRL1__fcw1_frac_MASK 0x0000FFFFL
+-#define DC_COMBOPHYPLLREGS4_FREQ_CTRL1__fcw1_int_MASK 0x01FF0000L
+-//DC_COMBOPHYPLLREGS4_FREQ_CTRL2
+-#define DC_COMBOPHYPLLREGS4_FREQ_CTRL2__fcw_denom__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS4_FREQ_CTRL2__fcw_slew_frac__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS4_FREQ_CTRL2__fcw_denom_MASK 0x0000FFFFL
+-#define DC_COMBOPHYPLLREGS4_FREQ_CTRL2__fcw_slew_frac_MASK 0xFFFF0000L
+-//DC_COMBOPHYPLLREGS4_FREQ_CTRL3
+-#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__refclk_div__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__vco_pre_div__SHIFT 0x3
+-#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__fracn_en__SHIFT 0x6
+-#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__ssc_en__SHIFT 0x8
+-#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__fcw_sel__SHIFT 0xa
+-#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__freq_jump_en__SHIFT 0xc
+-#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__tdc_resolution__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__dpll_cfg_1__SHIFT 0x18
+-#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__refclk_div_MASK 0x00000003L
+-#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__vco_pre_div_MASK 0x00000018L
+-#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__fracn_en_MASK 0x00000040L
+-#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__ssc_en_MASK 0x00000100L
+-#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__fcw_sel_MASK 0x00000400L
+-#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__freq_jump_en_MASK 0x00001000L
+-#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__tdc_resolution_MASK 0x00FF0000L
+-#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__dpll_cfg_1_MASK 0xFF000000L
+-//DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE
+-#define DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__gi_coarse_mant__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__gi_coarse_exp__SHIFT 0x2
+-#define DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__gp_coarse_mant__SHIFT 0x7
+-#define DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__gp_coarse_exp__SHIFT 0xc
+-#define DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__nctl_coarse_res__SHIFT 0x11
+-#define DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT 0x18
+-#define DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__gi_coarse_mant_MASK 0x00000003L
+-#define DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__gi_coarse_exp_MASK 0x0000003CL
+-#define DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__gp_coarse_mant_MASK 0x00000780L
+-#define DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__gp_coarse_exp_MASK 0x0000F000L
+-#define DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__nctl_coarse_res_MASK 0x007E0000L
+-#define DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__nctl_coarse_frac_res_MASK 0x03000000L
+-//DC_COMBOPHYPLLREGS4_BW_CTRL_FINE
+-#define DC_COMBOPHYPLLREGS4_BW_CTRL_FINE__dpll_cfg_3__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS4_BW_CTRL_FINE__dpll_cfg_3_MASK 0x000003FFL
+-//DC_COMBOPHYPLLREGS4_CAL_CTRL
+-#define DC_COMBOPHYPLLREGS4_CAL_CTRL__bypass_freq_lock__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS4_CAL_CTRL__tdc_cal_en__SHIFT 0x1
+-#define DC_COMBOPHYPLLREGS4_CAL_CTRL__tdc_cal_ctrl__SHIFT 0x3
+-#define DC_COMBOPHYPLLREGS4_CAL_CTRL__meas_win_sel__SHIFT 0x9
+-#define DC_COMBOPHYPLLREGS4_CAL_CTRL__kdco_cal_dis__SHIFT 0xb
+-#define DC_COMBOPHYPLLREGS4_CAL_CTRL__kdco_ratio__SHIFT 0xd
+-#define DC_COMBOPHYPLLREGS4_CAL_CTRL__kdco_incr_cal_dis__SHIFT 0x16
+-#define DC_COMBOPHYPLLREGS4_CAL_CTRL__nctl_adj_dis__SHIFT 0x17
+-#define DC_COMBOPHYPLLREGS4_CAL_CTRL__refclk_rate__SHIFT 0x18
+-#define DC_COMBOPHYPLLREGS4_CAL_CTRL__bypass_freq_lock_MASK 0x00000001L
+-#define DC_COMBOPHYPLLREGS4_CAL_CTRL__tdc_cal_en_MASK 0x00000002L
+-#define DC_COMBOPHYPLLREGS4_CAL_CTRL__tdc_cal_ctrl_MASK 0x000001F8L
+-#define DC_COMBOPHYPLLREGS4_CAL_CTRL__meas_win_sel_MASK 0x00000600L
+-#define DC_COMBOPHYPLLREGS4_CAL_CTRL__kdco_cal_dis_MASK 0x00000800L
+-#define DC_COMBOPHYPLLREGS4_CAL_CTRL__kdco_ratio_MASK 0x001FE000L
+-#define DC_COMBOPHYPLLREGS4_CAL_CTRL__kdco_incr_cal_dis_MASK 0x00400000L
+-#define DC_COMBOPHYPLLREGS4_CAL_CTRL__nctl_adj_dis_MASK 0x00800000L
+-#define DC_COMBOPHYPLLREGS4_CAL_CTRL__refclk_rate_MASK 0xFF000000L
+-//DC_COMBOPHYPLLREGS4_LOOP_CTRL
+-#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__fbdiv_mask_en__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__fb_slip_dis__SHIFT 0x2
+-#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__clk_tdc_sel__SHIFT 0x4
+-#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__clk_nctl_sel__SHIFT 0x7
+-#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__sig_del_patt_sel__SHIFT 0xa
+-#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__nctl_sig_del_dis__SHIFT 0xc
+-#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__fbclk_track_refclk__SHIFT 0xe
+-#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__prbs_en__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__tdc_clk_gate_en__SHIFT 0x12
+-#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__phase_offset__SHIFT 0x14
+-#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__fbdiv_mask_en_MASK 0x00000001L
+-#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__fb_slip_dis_MASK 0x00000004L
+-#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__clk_tdc_sel_MASK 0x00000030L
+-#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__clk_nctl_sel_MASK 0x00000180L
+-#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__sig_del_patt_sel_MASK 0x00000400L
+-#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__nctl_sig_del_dis_MASK 0x00001000L
+-#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__fbclk_track_refclk_MASK 0x00004000L
+-#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__prbs_en_MASK 0x00010000L
+-#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__tdc_clk_gate_en_MASK 0x00040000L
+-#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__phase_offset_MASK 0x07F00000L
+-//DC_COMBOPHYPLLREGS4_VREG_CFG
+-#define DC_COMBOPHYPLLREGS4_VREG_CFG__bleeder_ac__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS4_VREG_CFG__bleeder_en__SHIFT 0x1
+-#define DC_COMBOPHYPLLREGS4_VREG_CFG__is_1p2__SHIFT 0x2
+-#define DC_COMBOPHYPLLREGS4_VREG_CFG__reg_obs_sel__SHIFT 0x3
+-#define DC_COMBOPHYPLLREGS4_VREG_CFG__reg_on_mode__SHIFT 0x5
+-#define DC_COMBOPHYPLLREGS4_VREG_CFG__rlad_tap_sel__SHIFT 0x7
+-#define DC_COMBOPHYPLLREGS4_VREG_CFG__reg_off_hi__SHIFT 0xb
+-#define DC_COMBOPHYPLLREGS4_VREG_CFG__reg_off_lo__SHIFT 0xc
+-#define DC_COMBOPHYPLLREGS4_VREG_CFG__scale_driver__SHIFT 0xd
+-#define DC_COMBOPHYPLLREGS4_VREG_CFG__sel_bump__SHIFT 0xf
+-#define DC_COMBOPHYPLLREGS4_VREG_CFG__sel_rladder_x__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS4_VREG_CFG__short_rc_filt_x__SHIFT 0x11
+-#define DC_COMBOPHYPLLREGS4_VREG_CFG__vref_pwr_on__SHIFT 0x12
+-#define DC_COMBOPHYPLLREGS4_VREG_CFG__dpll_cfg_2__SHIFT 0x14
+-#define DC_COMBOPHYPLLREGS4_VREG_CFG__bleeder_ac_MASK 0x00000001L
+-#define DC_COMBOPHYPLLREGS4_VREG_CFG__bleeder_en_MASK 0x00000002L
+-#define DC_COMBOPHYPLLREGS4_VREG_CFG__is_1p2_MASK 0x00000004L
+-#define DC_COMBOPHYPLLREGS4_VREG_CFG__reg_obs_sel_MASK 0x00000018L
+-#define DC_COMBOPHYPLLREGS4_VREG_CFG__reg_on_mode_MASK 0x00000060L
+-#define DC_COMBOPHYPLLREGS4_VREG_CFG__rlad_tap_sel_MASK 0x00000780L
+-#define DC_COMBOPHYPLLREGS4_VREG_CFG__reg_off_hi_MASK 0x00000800L
+-#define DC_COMBOPHYPLLREGS4_VREG_CFG__reg_off_lo_MASK 0x00001000L
+-#define DC_COMBOPHYPLLREGS4_VREG_CFG__scale_driver_MASK 0x00006000L
+-#define DC_COMBOPHYPLLREGS4_VREG_CFG__sel_bump_MASK 0x00008000L
+-#define DC_COMBOPHYPLLREGS4_VREG_CFG__sel_rladder_x_MASK 0x00010000L
+-#define DC_COMBOPHYPLLREGS4_VREG_CFG__short_rc_filt_x_MASK 0x00020000L
+-#define DC_COMBOPHYPLLREGS4_VREG_CFG__vref_pwr_on_MASK 0x00040000L
+-#define DC_COMBOPHYPLLREGS4_VREG_CFG__dpll_cfg_2_MASK 0x0FF00000L
+-//DC_COMBOPHYPLLREGS4_OBSERVE0
+-#define DC_COMBOPHYPLLREGS4_OBSERVE0__lock_det_tdc_steps__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS4_OBSERVE0__clear_sticky_lock__SHIFT 0x6
+-#define DC_COMBOPHYPLLREGS4_OBSERVE0__lock_det_dis__SHIFT 0x8
+-#define DC_COMBOPHYPLLREGS4_OBSERVE0__dco_cfg__SHIFT 0xa
+-#define DC_COMBOPHYPLLREGS4_OBSERVE0__anaobs_sel__SHIFT 0x15
+-#define DC_COMBOPHYPLLREGS4_OBSERVE0__lock_det_tdc_steps_MASK 0x0000001FL
+-#define DC_COMBOPHYPLLREGS4_OBSERVE0__clear_sticky_lock_MASK 0x00000040L
+-#define DC_COMBOPHYPLLREGS4_OBSERVE0__lock_det_dis_MASK 0x00000100L
+-#define DC_COMBOPHYPLLREGS4_OBSERVE0__dco_cfg_MASK 0x0003FC00L
+-#define DC_COMBOPHYPLLREGS4_OBSERVE0__anaobs_sel_MASK 0x00E00000L
+-//DC_COMBOPHYPLLREGS4_OBSERVE1
+-#define DC_COMBOPHYPLLREGS4_OBSERVE1__digobs_sel__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS4_OBSERVE1__digobs_trig_sel__SHIFT 0x5
+-#define DC_COMBOPHYPLLREGS4_OBSERVE1__digobs_div__SHIFT 0xa
+-#define DC_COMBOPHYPLLREGS4_OBSERVE1__digobs_trig_div__SHIFT 0xd
+-#define DC_COMBOPHYPLLREGS4_OBSERVE1__lock_timer__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS4_OBSERVE1__digobs_sel_MASK 0x0000000FL
+-#define DC_COMBOPHYPLLREGS4_OBSERVE1__digobs_trig_sel_MASK 0x000001E0L
+-#define DC_COMBOPHYPLLREGS4_OBSERVE1__digobs_div_MASK 0x00000C00L
+-#define DC_COMBOPHYPLLREGS4_OBSERVE1__digobs_trig_div_MASK 0x00006000L
+-#define DC_COMBOPHYPLLREGS4_OBSERVE1__lock_timer_MASK 0x3FFF0000L
+-//DC_COMBOPHYPLLREGS4_DFT_OUT
+-#define DC_COMBOPHYPLLREGS4_DFT_OUT__dft_data__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS4_DFT_OUT__dft_data_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dcio_uniphy5_dispdec
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dc_combophycmregs5_dispdec
+-//DC_COMBOPHYCMREGS5_COMMON_FUSE1
+-#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_valid__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_unpopulated0__SHIFT 0x1
+-#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_ron_override_val__SHIFT 0x3
+-#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_unpopulated1__SHIFT 0x9
+-#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0xa
+-#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_unpopulated2__SHIFT 0xc
+-#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_rtt_override_val__SHIFT 0xd
+-#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_unpopulated3__SHIFT 0x13
+-#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0x14
+-#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_refresh_cal_en__SHIFT 0x16
+-#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_spare__SHIFT 0x17
+-#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_valid_MASK 0x00000001L
+-#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_unpopulated0_MASK 0x00000006L
+-#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_ron_override_val_MASK 0x000001F8L
+-#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_unpopulated1_MASK 0x00000200L
+-#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x00000C00L
+-#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_unpopulated2_MASK 0x00001000L
+-#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_rtt_override_val_MASK 0x0007E000L
+-#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_unpopulated3_MASK 0x00080000L
+-#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x00300000L
+-#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_refresh_cal_en_MASK 0x00400000L
+-#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_spare_MASK 0xFF800000L
+-//DC_COMBOPHYCMREGS5_COMMON_FUSE2
+-#define DC_COMBOPHYCMREGS5_COMMON_FUSE2__fuse2_valid__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS5_COMMON_FUSE2__fuse2_unpopulated__SHIFT 0x1
+-#define DC_COMBOPHYCMREGS5_COMMON_FUSE2__fuse2_tx_fifo_ptr__SHIFT 0x9
+-#define DC_COMBOPHYCMREGS5_COMMON_FUSE2__fuse2_spare__SHIFT 0xe
+-#define DC_COMBOPHYCMREGS5_COMMON_FUSE2__fuse2_valid_MASK 0x00000001L
+-#define DC_COMBOPHYCMREGS5_COMMON_FUSE2__fuse2_unpopulated_MASK 0x000001FEL
+-#define DC_COMBOPHYCMREGS5_COMMON_FUSE2__fuse2_tx_fifo_ptr_MASK 0x00003E00L
+-#define DC_COMBOPHYCMREGS5_COMMON_FUSE2__fuse2_spare_MASK 0xFFFFC000L
+-//DC_COMBOPHYCMREGS5_COMMON_FUSE3
+-#define DC_COMBOPHYCMREGS5_COMMON_FUSE3__fuse3_valid__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS5_COMMON_FUSE3__fuse3_unpopulated__SHIFT 0x1
+-#define DC_COMBOPHYCMREGS5_COMMON_FUSE3__fuse3_ei_det_thresh_sel__SHIFT 0xa
+-#define DC_COMBOPHYCMREGS5_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d
+-#define DC_COMBOPHYCMREGS5_COMMON_FUSE3__fuse3_valid_MASK 0x00000001L
+-#define DC_COMBOPHYCMREGS5_COMMON_FUSE3__fuse3_unpopulated_MASK 0x000003FEL
+-#define DC_COMBOPHYCMREGS5_COMMON_FUSE3__fuse3_ei_det_thresh_sel_MASK 0x00001C00L
+-#define DC_COMBOPHYCMREGS5_COMMON_FUSE3__fuse3_spare_MASK 0xE0000000L
+-//DC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM
+-#define DC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8
+-#define DC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10
+-#define DC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18
+-#define DC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0x000000FFL
+-#define DC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0x0000FF00L
+-#define DC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0x00FF0000L
+-#define DC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xFF000000L
+-//DC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT
+-#define DC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4
+-#define DC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT__vprot_en__SHIFT 0xb
+-#define DC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT__pgdelay_MASK 0x0000000FL
+-#define DC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT__pgmask_MASK 0x000003F0L
+-#define DC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT__vprot_en_MASK 0x00000800L
+-//DC_COMBOPHYCMREGS5_COMMON_TXCNTRL
+-#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__clkgate_dis__SHIFT 0x5
+-#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT 0x6
+-#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT 0x9
+-#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT 0xc
+-#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__dual_dvi_mstr_en__SHIFT 0xf
+-#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__dual_dvi_en__SHIFT 0x10
+-#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK 0x0000001FL
+-#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__clkgate_dis_MASK 0x00000020L
+-#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK 0x000001C0L
+-#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK 0x00000E00L
+-#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK 0x00007000L
+-#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__dual_dvi_mstr_en_MASK 0x00008000L
+-#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__dual_dvi_en_MASK 0x00010000L
+-//DC_COMBOPHYCMREGS5_COMMON_TMDP
+-#define DC_COMBOPHYCMREGS5_COMMON_TMDP__tmdp_spare__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS5_COMMON_TMDP__tmdp_spare_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS
+-#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_0_reset_l__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_1_reset_l__SHIFT 0x1
+-#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_2_reset_l__SHIFT 0x2
+-#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_3_reset_l__SHIFT 0x3
+-#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_4_reset_l__SHIFT 0x4
+-#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_5_reset_l__SHIFT 0x5
+-#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_6_reset_l__SHIFT 0x6
+-#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_7_reset_l__SHIFT 0x7
+-#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_0_reset_l_MASK 0x00000001L
+-#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_1_reset_l_MASK 0x00000002L
+-#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_2_reset_l_MASK 0x00000004L
+-#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_3_reset_l_MASK 0x00000008L
+-#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_4_reset_l_MASK 0x00000010L
+-#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_5_reset_l_MASK 0x00000020L
+-#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_6_reset_l_MASK 0x00000040L
+-#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_7_reset_l_MASK 0x00000080L
+-//DC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL
+-#define DC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT 0x1
+-#define DC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT 0x15
+-#define DC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL__zcalcode_override_MASK 0x00000001L
+-#define DC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK 0x0000003EL
+-#define DC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK 0x00200000L
+-//DC_COMBOPHYCMREGS5_COMMON_DISP_RFU1
+-#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU1__rfu_value1__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU1__rfu_value1_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS5_COMMON_DISP_RFU2
+-#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU2__rfu_value2__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU2__rfu_value2_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS5_COMMON_DISP_RFU3
+-#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU3__rfu_value3__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU3__rfu_value3_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS5_COMMON_DISP_RFU4
+-#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU4__rfu_value4__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU4__rfu_value4_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS5_COMMON_DISP_RFU5
+-#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU5__rfu_value5__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU5__rfu_value5_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS5_COMMON_DISP_RFU6
+-#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU6__rfu_value6__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU6__rfu_value6_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS5_COMMON_DISP_RFU7
+-#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU7__rfu_value7__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU7__rfu_value7_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dc_combophytxregs5_dispdec
+-//DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK 0x00000100L
+-//DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0
+-#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0__txmarg_sel_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0__deemph_sel_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0__tx_margin_en_MASK 0x00000020L
+-//DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x1
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT 0xa
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT 0xc
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT 0xd
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT 0xe
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT 0xf
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT 0x10
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT 0x14
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT 0x16
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x00000006L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0x000000E0L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK 0x00000300L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK 0x00000C00L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK 0x00001000L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK 0x00002000L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK 0x00004000L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK 0x00008000L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK 0x000F0000L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK 0x00100000L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK 0x00C00000L
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0__rfu_value0__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0__rfu_value0_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0__rfu_value1__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0__rfu_value1_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0__rfu_value2__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0__rfu_value2_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0__rfu_value3__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0__rfu_value3_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0__rfu_value4__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0__rfu_value4_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0__rfu_value5__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0__rfu_value5_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0__rfu_value6__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0__rfu_value6_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0__rfu_value7__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0__rfu_value7_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0__rfu_value8__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0__rfu_value8_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0__rfu_value9__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0__rfu_value9_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0__rfu_value10__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0__rfu_value10_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0__rfu_value11__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0__rfu_value11_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0__rfu_value12__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0__rfu_value12_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK 0x00000100L
+-//DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1
+-#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1__txmarg_sel_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1__deemph_sel_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1__tx_margin_en_MASK 0x00000020L
+-//DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x1
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT 0xa
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT 0xc
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT 0xd
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT 0xe
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT 0xf
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT 0x10
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT 0x14
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT 0x16
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x00000006L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0x000000E0L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK 0x00000300L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK 0x00000C00L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK 0x00001000L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK 0x00002000L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK 0x00004000L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK 0x00008000L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK 0x000F0000L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK 0x00100000L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK 0x00C00000L
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1__rfu_value0__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1__rfu_value0_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1__rfu_value1__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1__rfu_value1_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1__rfu_value2__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1__rfu_value2_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1__rfu_value3__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1__rfu_value3_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1__rfu_value4__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1__rfu_value4_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1__rfu_value5__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1__rfu_value5_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1__rfu_value6__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1__rfu_value6_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1__rfu_value7__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1__rfu_value7_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1__rfu_value8__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1__rfu_value8_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1__rfu_value9__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1__rfu_value9_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1__rfu_value10__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1__rfu_value10_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1__rfu_value11__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1__rfu_value11_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1__rfu_value12__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1__rfu_value12_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK 0x00000100L
+-//DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2
+-#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2__txmarg_sel_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2__deemph_sel_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2__tx_margin_en_MASK 0x00000020L
+-//DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x1
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT 0xa
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT 0xc
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT 0xd
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT 0xe
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT 0xf
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT 0x10
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT 0x14
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT 0x16
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x00000006L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0x000000E0L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK 0x00000300L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK 0x00000C00L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK 0x00001000L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK 0x00002000L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK 0x00004000L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK 0x00008000L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK 0x000F0000L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK 0x00100000L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK 0x00C00000L
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2__rfu_value0__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2__rfu_value0_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2__rfu_value1__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2__rfu_value1_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2__rfu_value2__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2__rfu_value2_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2__rfu_value3__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2__rfu_value3_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2__rfu_value4__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2__rfu_value4_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2__rfu_value5__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2__rfu_value5_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2__rfu_value6__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2__rfu_value6_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2__rfu_value7__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2__rfu_value7_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2__rfu_value8__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2__rfu_value8_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2__rfu_value9__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2__rfu_value9_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2__rfu_value10__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2__rfu_value10_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2__rfu_value11__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2__rfu_value11_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2__rfu_value12__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2__rfu_value12_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK 0x00000100L
+-//DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3
+-#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3__txmarg_sel_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3__deemph_sel_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3__tx_margin_en_MASK 0x00000020L
+-//DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x1
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT 0xa
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT 0xc
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT 0xd
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT 0xe
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT 0xf
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT 0x10
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT 0x14
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT 0x16
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x00000006L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0x000000E0L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK 0x00000300L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK 0x00000C00L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK 0x00001000L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK 0x00002000L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK 0x00004000L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK 0x00008000L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK 0x000F0000L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK 0x00100000L
+-#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK 0x00C00000L
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3__rfu_value0__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3__rfu_value0_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3__rfu_value1__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3__rfu_value1_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3__rfu_value2__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3__rfu_value2_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3__rfu_value3__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3__rfu_value3_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3__rfu_value4__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3__rfu_value4_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3__rfu_value5__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3__rfu_value5_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3__rfu_value6__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3__rfu_value6_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3__rfu_value7__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3__rfu_value7_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3__rfu_value8__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3__rfu_value8_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3__rfu_value9__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3__rfu_value9_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3__rfu_value10__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3__rfu_value10_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3__rfu_value11__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3__rfu_value11_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3__rfu_value12__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3__rfu_value12_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dc_combophypllregs5_dispdec
+-//DC_COMBOPHYPLLREGS5_FREQ_CTRL0
+-#define DC_COMBOPHYPLLREGS5_FREQ_CTRL0__fcw0_frac__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS5_FREQ_CTRL0__fcw0_int__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS5_FREQ_CTRL0__fcw0_frac_MASK 0x0000FFFFL
+-#define DC_COMBOPHYPLLREGS5_FREQ_CTRL0__fcw0_int_MASK 0x01FF0000L
+-//DC_COMBOPHYPLLREGS5_FREQ_CTRL1
+-#define DC_COMBOPHYPLLREGS5_FREQ_CTRL1__fcw1_frac__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS5_FREQ_CTRL1__fcw1_int__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS5_FREQ_CTRL1__fcw1_frac_MASK 0x0000FFFFL
+-#define DC_COMBOPHYPLLREGS5_FREQ_CTRL1__fcw1_int_MASK 0x01FF0000L
+-//DC_COMBOPHYPLLREGS5_FREQ_CTRL2
+-#define DC_COMBOPHYPLLREGS5_FREQ_CTRL2__fcw_denom__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS5_FREQ_CTRL2__fcw_slew_frac__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS5_FREQ_CTRL2__fcw_denom_MASK 0x0000FFFFL
+-#define DC_COMBOPHYPLLREGS5_FREQ_CTRL2__fcw_slew_frac_MASK 0xFFFF0000L
+-//DC_COMBOPHYPLLREGS5_FREQ_CTRL3
+-#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__refclk_div__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__vco_pre_div__SHIFT 0x3
+-#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__fracn_en__SHIFT 0x6
+-#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__ssc_en__SHIFT 0x8
+-#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__fcw_sel__SHIFT 0xa
+-#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__freq_jump_en__SHIFT 0xc
+-#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__tdc_resolution__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__dpll_cfg_1__SHIFT 0x18
+-#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__refclk_div_MASK 0x00000003L
+-#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__vco_pre_div_MASK 0x00000018L
+-#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__fracn_en_MASK 0x00000040L
+-#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__ssc_en_MASK 0x00000100L
+-#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__fcw_sel_MASK 0x00000400L
+-#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__freq_jump_en_MASK 0x00001000L
+-#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__tdc_resolution_MASK 0x00FF0000L
+-#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__dpll_cfg_1_MASK 0xFF000000L
+-//DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE
+-#define DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__gi_coarse_mant__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__gi_coarse_exp__SHIFT 0x2
+-#define DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__gp_coarse_mant__SHIFT 0x7
+-#define DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__gp_coarse_exp__SHIFT 0xc
+-#define DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__nctl_coarse_res__SHIFT 0x11
+-#define DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT 0x18
+-#define DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__gi_coarse_mant_MASK 0x00000003L
+-#define DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__gi_coarse_exp_MASK 0x0000003CL
+-#define DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__gp_coarse_mant_MASK 0x00000780L
+-#define DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__gp_coarse_exp_MASK 0x0000F000L
+-#define DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__nctl_coarse_res_MASK 0x007E0000L
+-#define DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__nctl_coarse_frac_res_MASK 0x03000000L
+-//DC_COMBOPHYPLLREGS5_BW_CTRL_FINE
+-#define DC_COMBOPHYPLLREGS5_BW_CTRL_FINE__dpll_cfg_3__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS5_BW_CTRL_FINE__dpll_cfg_3_MASK 0x000003FFL
+-//DC_COMBOPHYPLLREGS5_CAL_CTRL
+-#define DC_COMBOPHYPLLREGS5_CAL_CTRL__bypass_freq_lock__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS5_CAL_CTRL__tdc_cal_en__SHIFT 0x1
+-#define DC_COMBOPHYPLLREGS5_CAL_CTRL__tdc_cal_ctrl__SHIFT 0x3
+-#define DC_COMBOPHYPLLREGS5_CAL_CTRL__meas_win_sel__SHIFT 0x9
+-#define DC_COMBOPHYPLLREGS5_CAL_CTRL__kdco_cal_dis__SHIFT 0xb
+-#define DC_COMBOPHYPLLREGS5_CAL_CTRL__kdco_ratio__SHIFT 0xd
+-#define DC_COMBOPHYPLLREGS5_CAL_CTRL__kdco_incr_cal_dis__SHIFT 0x16
+-#define DC_COMBOPHYPLLREGS5_CAL_CTRL__nctl_adj_dis__SHIFT 0x17
+-#define DC_COMBOPHYPLLREGS5_CAL_CTRL__refclk_rate__SHIFT 0x18
+-#define DC_COMBOPHYPLLREGS5_CAL_CTRL__bypass_freq_lock_MASK 0x00000001L
+-#define DC_COMBOPHYPLLREGS5_CAL_CTRL__tdc_cal_en_MASK 0x00000002L
+-#define DC_COMBOPHYPLLREGS5_CAL_CTRL__tdc_cal_ctrl_MASK 0x000001F8L
+-#define DC_COMBOPHYPLLREGS5_CAL_CTRL__meas_win_sel_MASK 0x00000600L
+-#define DC_COMBOPHYPLLREGS5_CAL_CTRL__kdco_cal_dis_MASK 0x00000800L
+-#define DC_COMBOPHYPLLREGS5_CAL_CTRL__kdco_ratio_MASK 0x001FE000L
+-#define DC_COMBOPHYPLLREGS5_CAL_CTRL__kdco_incr_cal_dis_MASK 0x00400000L
+-#define DC_COMBOPHYPLLREGS5_CAL_CTRL__nctl_adj_dis_MASK 0x00800000L
+-#define DC_COMBOPHYPLLREGS5_CAL_CTRL__refclk_rate_MASK 0xFF000000L
+-//DC_COMBOPHYPLLREGS5_LOOP_CTRL
+-#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__fbdiv_mask_en__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__fb_slip_dis__SHIFT 0x2
+-#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__clk_tdc_sel__SHIFT 0x4
+-#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__clk_nctl_sel__SHIFT 0x7
+-#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__sig_del_patt_sel__SHIFT 0xa
+-#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__nctl_sig_del_dis__SHIFT 0xc
+-#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__fbclk_track_refclk__SHIFT 0xe
+-#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__prbs_en__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__tdc_clk_gate_en__SHIFT 0x12
+-#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__phase_offset__SHIFT 0x14
+-#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__fbdiv_mask_en_MASK 0x00000001L
+-#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__fb_slip_dis_MASK 0x00000004L
+-#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__clk_tdc_sel_MASK 0x00000030L
+-#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__clk_nctl_sel_MASK 0x00000180L
+-#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__sig_del_patt_sel_MASK 0x00000400L
+-#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__nctl_sig_del_dis_MASK 0x00001000L
+-#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__fbclk_track_refclk_MASK 0x00004000L
+-#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__prbs_en_MASK 0x00010000L
+-#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__tdc_clk_gate_en_MASK 0x00040000L
+-#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__phase_offset_MASK 0x07F00000L
+-//DC_COMBOPHYPLLREGS5_VREG_CFG
+-#define DC_COMBOPHYPLLREGS5_VREG_CFG__bleeder_ac__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS5_VREG_CFG__bleeder_en__SHIFT 0x1
+-#define DC_COMBOPHYPLLREGS5_VREG_CFG__is_1p2__SHIFT 0x2
+-#define DC_COMBOPHYPLLREGS5_VREG_CFG__reg_obs_sel__SHIFT 0x3
+-#define DC_COMBOPHYPLLREGS5_VREG_CFG__reg_on_mode__SHIFT 0x5
+-#define DC_COMBOPHYPLLREGS5_VREG_CFG__rlad_tap_sel__SHIFT 0x7
+-#define DC_COMBOPHYPLLREGS5_VREG_CFG__reg_off_hi__SHIFT 0xb
+-#define DC_COMBOPHYPLLREGS5_VREG_CFG__reg_off_lo__SHIFT 0xc
+-#define DC_COMBOPHYPLLREGS5_VREG_CFG__scale_driver__SHIFT 0xd
+-#define DC_COMBOPHYPLLREGS5_VREG_CFG__sel_bump__SHIFT 0xf
+-#define DC_COMBOPHYPLLREGS5_VREG_CFG__sel_rladder_x__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS5_VREG_CFG__short_rc_filt_x__SHIFT 0x11
+-#define DC_COMBOPHYPLLREGS5_VREG_CFG__vref_pwr_on__SHIFT 0x12
+-#define DC_COMBOPHYPLLREGS5_VREG_CFG__dpll_cfg_2__SHIFT 0x14
+-#define DC_COMBOPHYPLLREGS5_VREG_CFG__bleeder_ac_MASK 0x00000001L
+-#define DC_COMBOPHYPLLREGS5_VREG_CFG__bleeder_en_MASK 0x00000002L
+-#define DC_COMBOPHYPLLREGS5_VREG_CFG__is_1p2_MASK 0x00000004L
+-#define DC_COMBOPHYPLLREGS5_VREG_CFG__reg_obs_sel_MASK 0x00000018L
+-#define DC_COMBOPHYPLLREGS5_VREG_CFG__reg_on_mode_MASK 0x00000060L
+-#define DC_COMBOPHYPLLREGS5_VREG_CFG__rlad_tap_sel_MASK 0x00000780L
+-#define DC_COMBOPHYPLLREGS5_VREG_CFG__reg_off_hi_MASK 0x00000800L
+-#define DC_COMBOPHYPLLREGS5_VREG_CFG__reg_off_lo_MASK 0x00001000L
+-#define DC_COMBOPHYPLLREGS5_VREG_CFG__scale_driver_MASK 0x00006000L
+-#define DC_COMBOPHYPLLREGS5_VREG_CFG__sel_bump_MASK 0x00008000L
+-#define DC_COMBOPHYPLLREGS5_VREG_CFG__sel_rladder_x_MASK 0x00010000L
+-#define DC_COMBOPHYPLLREGS5_VREG_CFG__short_rc_filt_x_MASK 0x00020000L
+-#define DC_COMBOPHYPLLREGS5_VREG_CFG__vref_pwr_on_MASK 0x00040000L
+-#define DC_COMBOPHYPLLREGS5_VREG_CFG__dpll_cfg_2_MASK 0x0FF00000L
+-//DC_COMBOPHYPLLREGS5_OBSERVE0
+-#define DC_COMBOPHYPLLREGS5_OBSERVE0__lock_det_tdc_steps__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS5_OBSERVE0__clear_sticky_lock__SHIFT 0x6
+-#define DC_COMBOPHYPLLREGS5_OBSERVE0__lock_det_dis__SHIFT 0x8
+-#define DC_COMBOPHYPLLREGS5_OBSERVE0__dco_cfg__SHIFT 0xa
+-#define DC_COMBOPHYPLLREGS5_OBSERVE0__anaobs_sel__SHIFT 0x15
+-#define DC_COMBOPHYPLLREGS5_OBSERVE0__lock_det_tdc_steps_MASK 0x0000001FL
+-#define DC_COMBOPHYPLLREGS5_OBSERVE0__clear_sticky_lock_MASK 0x00000040L
+-#define DC_COMBOPHYPLLREGS5_OBSERVE0__lock_det_dis_MASK 0x00000100L
+-#define DC_COMBOPHYPLLREGS5_OBSERVE0__dco_cfg_MASK 0x0003FC00L
+-#define DC_COMBOPHYPLLREGS5_OBSERVE0__anaobs_sel_MASK 0x00E00000L
+-//DC_COMBOPHYPLLREGS5_OBSERVE1
+-#define DC_COMBOPHYPLLREGS5_OBSERVE1__digobs_sel__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS5_OBSERVE1__digobs_trig_sel__SHIFT 0x5
+-#define DC_COMBOPHYPLLREGS5_OBSERVE1__digobs_div__SHIFT 0xa
+-#define DC_COMBOPHYPLLREGS5_OBSERVE1__digobs_trig_div__SHIFT 0xd
+-#define DC_COMBOPHYPLLREGS5_OBSERVE1__lock_timer__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS5_OBSERVE1__digobs_sel_MASK 0x0000000FL
+-#define DC_COMBOPHYPLLREGS5_OBSERVE1__digobs_trig_sel_MASK 0x000001E0L
+-#define DC_COMBOPHYPLLREGS5_OBSERVE1__digobs_div_MASK 0x00000C00L
+-#define DC_COMBOPHYPLLREGS5_OBSERVE1__digobs_trig_div_MASK 0x00006000L
+-#define DC_COMBOPHYPLLREGS5_OBSERVE1__lock_timer_MASK 0x3FFF0000L
+-//DC_COMBOPHYPLLREGS5_DFT_OUT
+-#define DC_COMBOPHYPLLREGS5_DFT_OUT__dft_data__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS5_DFT_OUT__dft_data_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dcio_uniphy6_dispdec
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED58
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED59
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED60
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED61
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED62
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED63
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED64
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED65
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED66
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED67
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED68
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED69
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED70
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED71
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED72
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED73
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED74
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED75
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED76
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED77
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED78
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED79
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED80
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED81
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED82
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED83
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED84
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED85
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED86
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED87
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED88
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED89
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED90
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED91
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED92
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED93
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED94
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED95
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED96
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED97
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED98
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED99
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED100
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED101
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED102
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED103
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED104
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED105
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED106
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED107
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED108
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED109
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED110
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED111
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED112
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED113
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED114
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED115
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED116
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED117
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED118
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED119
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED120
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED121
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED122
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED123
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED124
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED125
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED126
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED127
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED128
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED129
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED130
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED131
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED132
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED133
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED134
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED135
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED136
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED137
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED138
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED139
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED140
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED141
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED142
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED143
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED144
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED145
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED146
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED147
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED148
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED149
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED150
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED151
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED152
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED153
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED154
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED155
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED156
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED157
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED158
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED159
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dc_combophycmregs6_dispdec
+-//DC_COMBOPHYCMREGS6_COMMON_FUSE1
+-#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_valid__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_unpopulated0__SHIFT 0x1
+-#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_ron_override_val__SHIFT 0x3
+-#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_unpopulated1__SHIFT 0x9
+-#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0xa
+-#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_unpopulated2__SHIFT 0xc
+-#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_rtt_override_val__SHIFT 0xd
+-#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_unpopulated3__SHIFT 0x13
+-#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0x14
+-#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_refresh_cal_en__SHIFT 0x16
+-#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_spare__SHIFT 0x17
+-#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_valid_MASK 0x00000001L
+-#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_unpopulated0_MASK 0x00000006L
+-#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_ron_override_val_MASK 0x000001F8L
+-#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_unpopulated1_MASK 0x00000200L
+-#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x00000C00L
+-#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_unpopulated2_MASK 0x00001000L
+-#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_rtt_override_val_MASK 0x0007E000L
+-#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_unpopulated3_MASK 0x00080000L
+-#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x00300000L
+-#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_refresh_cal_en_MASK 0x00400000L
+-#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_spare_MASK 0xFF800000L
+-//DC_COMBOPHYCMREGS6_COMMON_FUSE2
+-#define DC_COMBOPHYCMREGS6_COMMON_FUSE2__fuse2_valid__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS6_COMMON_FUSE2__fuse2_unpopulated__SHIFT 0x1
+-#define DC_COMBOPHYCMREGS6_COMMON_FUSE2__fuse2_tx_fifo_ptr__SHIFT 0x9
+-#define DC_COMBOPHYCMREGS6_COMMON_FUSE2__fuse2_spare__SHIFT 0xe
+-#define DC_COMBOPHYCMREGS6_COMMON_FUSE2__fuse2_valid_MASK 0x00000001L
+-#define DC_COMBOPHYCMREGS6_COMMON_FUSE2__fuse2_unpopulated_MASK 0x000001FEL
+-#define DC_COMBOPHYCMREGS6_COMMON_FUSE2__fuse2_tx_fifo_ptr_MASK 0x00003E00L
+-#define DC_COMBOPHYCMREGS6_COMMON_FUSE2__fuse2_spare_MASK 0xFFFFC000L
+-//DC_COMBOPHYCMREGS6_COMMON_FUSE3
+-#define DC_COMBOPHYCMREGS6_COMMON_FUSE3__fuse3_valid__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS6_COMMON_FUSE3__fuse3_unpopulated__SHIFT 0x1
+-#define DC_COMBOPHYCMREGS6_COMMON_FUSE3__fuse3_ei_det_thresh_sel__SHIFT 0xa
+-#define DC_COMBOPHYCMREGS6_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d
+-#define DC_COMBOPHYCMREGS6_COMMON_FUSE3__fuse3_valid_MASK 0x00000001L
+-#define DC_COMBOPHYCMREGS6_COMMON_FUSE3__fuse3_unpopulated_MASK 0x000003FEL
+-#define DC_COMBOPHYCMREGS6_COMMON_FUSE3__fuse3_ei_det_thresh_sel_MASK 0x00001C00L
+-#define DC_COMBOPHYCMREGS6_COMMON_FUSE3__fuse3_spare_MASK 0xE0000000L
+-//DC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM
+-#define DC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8
+-#define DC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10
+-#define DC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18
+-#define DC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0x000000FFL
+-#define DC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0x0000FF00L
+-#define DC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0x00FF0000L
+-#define DC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xFF000000L
+-//DC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT
+-#define DC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4
+-#define DC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT__vprot_en__SHIFT 0xb
+-#define DC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT__pgdelay_MASK 0x0000000FL
+-#define DC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT__pgmask_MASK 0x000003F0L
+-#define DC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT__vprot_en_MASK 0x00000800L
+-//DC_COMBOPHYCMREGS6_COMMON_TXCNTRL
+-#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__clkgate_dis__SHIFT 0x5
+-#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT 0x6
+-#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT 0x9
+-#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT 0xc
+-#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__dual_dvi_mstr_en__SHIFT 0xf
+-#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__dual_dvi_en__SHIFT 0x10
+-#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK 0x0000001FL
+-#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__clkgate_dis_MASK 0x00000020L
+-#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK 0x000001C0L
+-#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK 0x00000E00L
+-#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK 0x00007000L
+-#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__dual_dvi_mstr_en_MASK 0x00008000L
+-#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__dual_dvi_en_MASK 0x00010000L
+-//DC_COMBOPHYCMREGS6_COMMON_TMDP
+-#define DC_COMBOPHYCMREGS6_COMMON_TMDP__tmdp_spare__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS6_COMMON_TMDP__tmdp_spare_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS
+-#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_0_reset_l__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_1_reset_l__SHIFT 0x1
+-#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_2_reset_l__SHIFT 0x2
+-#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_3_reset_l__SHIFT 0x3
+-#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_4_reset_l__SHIFT 0x4
+-#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_5_reset_l__SHIFT 0x5
+-#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_6_reset_l__SHIFT 0x6
+-#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_7_reset_l__SHIFT 0x7
+-#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_0_reset_l_MASK 0x00000001L
+-#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_1_reset_l_MASK 0x00000002L
+-#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_2_reset_l_MASK 0x00000004L
+-#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_3_reset_l_MASK 0x00000008L
+-#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_4_reset_l_MASK 0x00000010L
+-#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_5_reset_l_MASK 0x00000020L
+-#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_6_reset_l_MASK 0x00000040L
+-#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_7_reset_l_MASK 0x00000080L
+-//DC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL
+-#define DC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT 0x1
+-#define DC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT 0x15
+-#define DC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL__zcalcode_override_MASK 0x00000001L
+-#define DC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK 0x0000003EL
+-#define DC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK 0x00200000L
+-//DC_COMBOPHYCMREGS6_COMMON_DISP_RFU1
+-#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU1__rfu_value1__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU1__rfu_value1_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS6_COMMON_DISP_RFU2
+-#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU2__rfu_value2__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU2__rfu_value2_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS6_COMMON_DISP_RFU3
+-#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU3__rfu_value3__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU3__rfu_value3_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS6_COMMON_DISP_RFU4
+-#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU4__rfu_value4__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU4__rfu_value4_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS6_COMMON_DISP_RFU5
+-#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU5__rfu_value5__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU5__rfu_value5_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS6_COMMON_DISP_RFU6
+-#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU6__rfu_value6__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU6__rfu_value6_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS6_COMMON_DISP_RFU7
+-#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU7__rfu_value7__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU7__rfu_value7_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dc_combophytxregs6_dispdec
+-//DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK 0x00000100L
+-//DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0
+-#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0__txmarg_sel_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0__deemph_sel_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0__tx_margin_en_MASK 0x00000020L
+-//DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x1
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT 0xa
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT 0xc
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT 0xd
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT 0xe
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT 0xf
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT 0x10
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT 0x14
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT 0x16
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x00000006L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0x000000E0L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK 0x00000300L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK 0x00000C00L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK 0x00001000L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK 0x00002000L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK 0x00004000L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK 0x00008000L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK 0x000F0000L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK 0x00100000L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK 0x00C00000L
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE0__rfu_value0__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE0__rfu_value0_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE0__rfu_value1__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE0__rfu_value1_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE0__rfu_value2__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE0__rfu_value2_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE0__rfu_value3__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE0__rfu_value3_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE0__rfu_value4__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE0__rfu_value4_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE0__rfu_value5__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE0__rfu_value5_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE0__rfu_value6__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE0__rfu_value6_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE0__rfu_value7__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE0__rfu_value7_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE0__rfu_value8__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE0__rfu_value8_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE0__rfu_value9__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE0__rfu_value9_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE0__rfu_value10__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE0__rfu_value10_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE0__rfu_value11__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE0__rfu_value11_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE0__rfu_value12__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE0__rfu_value12_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK 0x00000100L
+-//DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1
+-#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1__txmarg_sel_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1__deemph_sel_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1__tx_margin_en_MASK 0x00000020L
+-//DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x1
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT 0xa
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT 0xc
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT 0xd
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT 0xe
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT 0xf
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT 0x10
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT 0x14
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT 0x16
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x00000006L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0x000000E0L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK 0x00000300L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK 0x00000C00L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK 0x00001000L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK 0x00002000L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK 0x00004000L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK 0x00008000L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK 0x000F0000L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK 0x00100000L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK 0x00C00000L
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE1
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE1__rfu_value0__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE1__rfu_value0_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE1
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE1__rfu_value1__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE1__rfu_value1_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE1
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE1__rfu_value2__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE1__rfu_value2_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE1
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE1__rfu_value3__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE1__rfu_value3_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE1
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE1__rfu_value4__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE1__rfu_value4_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE1
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE1__rfu_value5__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE1__rfu_value5_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE1
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE1__rfu_value6__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE1__rfu_value6_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE1
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE1__rfu_value7__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE1__rfu_value7_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE1
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE1__rfu_value8__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE1__rfu_value8_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE1
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE1__rfu_value9__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE1__rfu_value9_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE1
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE1__rfu_value10__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE1__rfu_value10_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE1
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE1__rfu_value11__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE1__rfu_value11_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE1
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE1__rfu_value12__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE1__rfu_value12_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK 0x00000100L
+-//DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2
+-#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2__txmarg_sel_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2__deemph_sel_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2__tx_margin_en_MASK 0x00000020L
+-//DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x1
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT 0xa
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT 0xc
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT 0xd
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT 0xe
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT 0xf
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT 0x10
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT 0x14
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT 0x16
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x00000006L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0x000000E0L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK 0x00000300L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK 0x00000C00L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK 0x00001000L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK 0x00002000L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK 0x00004000L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK 0x00008000L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK 0x000F0000L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK 0x00100000L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK 0x00C00000L
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE2
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE2__rfu_value0__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE2__rfu_value0_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE2
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE2__rfu_value1__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE2__rfu_value1_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE2
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE2__rfu_value2__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE2__rfu_value2_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE2
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE2__rfu_value3__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE2__rfu_value3_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE2
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE2__rfu_value4__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE2__rfu_value4_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE2
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE2__rfu_value5__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE2__rfu_value5_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE2
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE2__rfu_value6__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE2__rfu_value6_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE2
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE2__rfu_value7__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE2__rfu_value7_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE2
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE2__rfu_value8__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE2__rfu_value8_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE2
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE2__rfu_value9__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE2__rfu_value9_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE2
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE2__rfu_value10__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE2__rfu_value10_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE2
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE2__rfu_value11__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE2__rfu_value11_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE2
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE2__rfu_value12__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE2__rfu_value12_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK 0x00000100L
+-//DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3
+-#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3__txmarg_sel_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3__deemph_sel_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3__tx_margin_en_MASK 0x00000020L
+-//DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x1
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT 0xa
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT 0xc
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT 0xd
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT 0xe
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT 0xf
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT 0x10
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT 0x14
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT 0x16
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x00000006L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0x000000E0L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK 0x00000300L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK 0x00000C00L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK 0x00001000L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK 0x00002000L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK 0x00004000L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK 0x00008000L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK 0x000F0000L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK 0x00100000L
+-#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK 0x00C00000L
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE3
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE3__rfu_value0__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE3__rfu_value0_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE3
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE3__rfu_value1__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE3__rfu_value1_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE3
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE3__rfu_value2__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE3__rfu_value2_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE3
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE3__rfu_value3__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE3__rfu_value3_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE3
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE3__rfu_value4__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE3__rfu_value4_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE3
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE3__rfu_value5__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE3__rfu_value5_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE3
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE3__rfu_value6__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE3__rfu_value6_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE3
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE3__rfu_value7__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE3__rfu_value7_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE3
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE3__rfu_value8__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE3__rfu_value8_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE3
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE3__rfu_value9__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE3__rfu_value9_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE3
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE3__rfu_value10__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE3__rfu_value10_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE3
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE3__rfu_value11__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE3__rfu_value11_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE3
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE3__rfu_value12__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE3__rfu_value12_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dc_combophypllregs6_dispdec
+-//DC_COMBOPHYPLLREGS6_FREQ_CTRL0
+-#define DC_COMBOPHYPLLREGS6_FREQ_CTRL0__fcw0_frac__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS6_FREQ_CTRL0__fcw0_int__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS6_FREQ_CTRL0__fcw0_frac_MASK 0x0000FFFFL
+-#define DC_COMBOPHYPLLREGS6_FREQ_CTRL0__fcw0_int_MASK 0x01FF0000L
+-//DC_COMBOPHYPLLREGS6_FREQ_CTRL1
+-#define DC_COMBOPHYPLLREGS6_FREQ_CTRL1__fcw1_frac__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS6_FREQ_CTRL1__fcw1_int__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS6_FREQ_CTRL1__fcw1_frac_MASK 0x0000FFFFL
+-#define DC_COMBOPHYPLLREGS6_FREQ_CTRL1__fcw1_int_MASK 0x01FF0000L
+-//DC_COMBOPHYPLLREGS6_FREQ_CTRL2
+-#define DC_COMBOPHYPLLREGS6_FREQ_CTRL2__fcw_denom__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS6_FREQ_CTRL2__fcw_slew_frac__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS6_FREQ_CTRL2__fcw_denom_MASK 0x0000FFFFL
+-#define DC_COMBOPHYPLLREGS6_FREQ_CTRL2__fcw_slew_frac_MASK 0xFFFF0000L
+-//DC_COMBOPHYPLLREGS6_FREQ_CTRL3
+-#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__refclk_div__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__vco_pre_div__SHIFT 0x3
+-#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__fracn_en__SHIFT 0x6
+-#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__ssc_en__SHIFT 0x8
+-#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__fcw_sel__SHIFT 0xa
+-#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__freq_jump_en__SHIFT 0xc
+-#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__tdc_resolution__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__dpll_cfg_1__SHIFT 0x18
+-#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__refclk_div_MASK 0x00000003L
+-#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__vco_pre_div_MASK 0x00000018L
+-#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__fracn_en_MASK 0x00000040L
+-#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__ssc_en_MASK 0x00000100L
+-#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__fcw_sel_MASK 0x00000400L
+-#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__freq_jump_en_MASK 0x00001000L
+-#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__tdc_resolution_MASK 0x00FF0000L
+-#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__dpll_cfg_1_MASK 0xFF000000L
+-//DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE
+-#define DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__gi_coarse_mant__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__gi_coarse_exp__SHIFT 0x2
+-#define DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__gp_coarse_mant__SHIFT 0x7
+-#define DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__gp_coarse_exp__SHIFT 0xc
+-#define DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__nctl_coarse_res__SHIFT 0x11
+-#define DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT 0x18
+-#define DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__gi_coarse_mant_MASK 0x00000003L
+-#define DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__gi_coarse_exp_MASK 0x0000003CL
+-#define DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__gp_coarse_mant_MASK 0x00000780L
+-#define DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__gp_coarse_exp_MASK 0x0000F000L
+-#define DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__nctl_coarse_res_MASK 0x007E0000L
+-#define DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__nctl_coarse_frac_res_MASK 0x03000000L
+-//DC_COMBOPHYPLLREGS6_BW_CTRL_FINE
+-#define DC_COMBOPHYPLLREGS6_BW_CTRL_FINE__dpll_cfg_3__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS6_BW_CTRL_FINE__dpll_cfg_3_MASK 0x000003FFL
+-//DC_COMBOPHYPLLREGS6_CAL_CTRL
+-#define DC_COMBOPHYPLLREGS6_CAL_CTRL__bypass_freq_lock__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS6_CAL_CTRL__tdc_cal_en__SHIFT 0x1
+-#define DC_COMBOPHYPLLREGS6_CAL_CTRL__tdc_cal_ctrl__SHIFT 0x3
+-#define DC_COMBOPHYPLLREGS6_CAL_CTRL__meas_win_sel__SHIFT 0x9
+-#define DC_COMBOPHYPLLREGS6_CAL_CTRL__kdco_cal_dis__SHIFT 0xb
+-#define DC_COMBOPHYPLLREGS6_CAL_CTRL__kdco_ratio__SHIFT 0xd
+-#define DC_COMBOPHYPLLREGS6_CAL_CTRL__kdco_incr_cal_dis__SHIFT 0x16
+-#define DC_COMBOPHYPLLREGS6_CAL_CTRL__nctl_adj_dis__SHIFT 0x17
+-#define DC_COMBOPHYPLLREGS6_CAL_CTRL__refclk_rate__SHIFT 0x18
+-#define DC_COMBOPHYPLLREGS6_CAL_CTRL__bypass_freq_lock_MASK 0x00000001L
+-#define DC_COMBOPHYPLLREGS6_CAL_CTRL__tdc_cal_en_MASK 0x00000002L
+-#define DC_COMBOPHYPLLREGS6_CAL_CTRL__tdc_cal_ctrl_MASK 0x000001F8L
+-#define DC_COMBOPHYPLLREGS6_CAL_CTRL__meas_win_sel_MASK 0x00000600L
+-#define DC_COMBOPHYPLLREGS6_CAL_CTRL__kdco_cal_dis_MASK 0x00000800L
+-#define DC_COMBOPHYPLLREGS6_CAL_CTRL__kdco_ratio_MASK 0x001FE000L
+-#define DC_COMBOPHYPLLREGS6_CAL_CTRL__kdco_incr_cal_dis_MASK 0x00400000L
+-#define DC_COMBOPHYPLLREGS6_CAL_CTRL__nctl_adj_dis_MASK 0x00800000L
+-#define DC_COMBOPHYPLLREGS6_CAL_CTRL__refclk_rate_MASK 0xFF000000L
+-//DC_COMBOPHYPLLREGS6_LOOP_CTRL
+-#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__fbdiv_mask_en__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__fb_slip_dis__SHIFT 0x2
+-#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__clk_tdc_sel__SHIFT 0x4
+-#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__clk_nctl_sel__SHIFT 0x7
+-#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__sig_del_patt_sel__SHIFT 0xa
+-#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__nctl_sig_del_dis__SHIFT 0xc
+-#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__fbclk_track_refclk__SHIFT 0xe
+-#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__prbs_en__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__tdc_clk_gate_en__SHIFT 0x12
+-#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__phase_offset__SHIFT 0x14
+-#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__fbdiv_mask_en_MASK 0x00000001L
+-#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__fb_slip_dis_MASK 0x00000004L
+-#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__clk_tdc_sel_MASK 0x00000030L
+-#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__clk_nctl_sel_MASK 0x00000180L
+-#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__sig_del_patt_sel_MASK 0x00000400L
+-#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__nctl_sig_del_dis_MASK 0x00001000L
+-#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__fbclk_track_refclk_MASK 0x00004000L
+-#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__prbs_en_MASK 0x00010000L
+-#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__tdc_clk_gate_en_MASK 0x00040000L
+-#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__phase_offset_MASK 0x07F00000L
+-//DC_COMBOPHYPLLREGS6_VREG_CFG
+-#define DC_COMBOPHYPLLREGS6_VREG_CFG__bleeder_ac__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS6_VREG_CFG__bleeder_en__SHIFT 0x1
+-#define DC_COMBOPHYPLLREGS6_VREG_CFG__is_1p2__SHIFT 0x2
+-#define DC_COMBOPHYPLLREGS6_VREG_CFG__reg_obs_sel__SHIFT 0x3
+-#define DC_COMBOPHYPLLREGS6_VREG_CFG__reg_on_mode__SHIFT 0x5
+-#define DC_COMBOPHYPLLREGS6_VREG_CFG__rlad_tap_sel__SHIFT 0x7
+-#define DC_COMBOPHYPLLREGS6_VREG_CFG__reg_off_hi__SHIFT 0xb
+-#define DC_COMBOPHYPLLREGS6_VREG_CFG__reg_off_lo__SHIFT 0xc
+-#define DC_COMBOPHYPLLREGS6_VREG_CFG__scale_driver__SHIFT 0xd
+-#define DC_COMBOPHYPLLREGS6_VREG_CFG__sel_bump__SHIFT 0xf
+-#define DC_COMBOPHYPLLREGS6_VREG_CFG__sel_rladder_x__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS6_VREG_CFG__short_rc_filt_x__SHIFT 0x11
+-#define DC_COMBOPHYPLLREGS6_VREG_CFG__vref_pwr_on__SHIFT 0x12
+-#define DC_COMBOPHYPLLREGS6_VREG_CFG__dpll_cfg_2__SHIFT 0x14
+-#define DC_COMBOPHYPLLREGS6_VREG_CFG__bleeder_ac_MASK 0x00000001L
+-#define DC_COMBOPHYPLLREGS6_VREG_CFG__bleeder_en_MASK 0x00000002L
+-#define DC_COMBOPHYPLLREGS6_VREG_CFG__is_1p2_MASK 0x00000004L
+-#define DC_COMBOPHYPLLREGS6_VREG_CFG__reg_obs_sel_MASK 0x00000018L
+-#define DC_COMBOPHYPLLREGS6_VREG_CFG__reg_on_mode_MASK 0x00000060L
+-#define DC_COMBOPHYPLLREGS6_VREG_CFG__rlad_tap_sel_MASK 0x00000780L
+-#define DC_COMBOPHYPLLREGS6_VREG_CFG__reg_off_hi_MASK 0x00000800L
+-#define DC_COMBOPHYPLLREGS6_VREG_CFG__reg_off_lo_MASK 0x00001000L
+-#define DC_COMBOPHYPLLREGS6_VREG_CFG__scale_driver_MASK 0x00006000L
+-#define DC_COMBOPHYPLLREGS6_VREG_CFG__sel_bump_MASK 0x00008000L
+-#define DC_COMBOPHYPLLREGS6_VREG_CFG__sel_rladder_x_MASK 0x00010000L
+-#define DC_COMBOPHYPLLREGS6_VREG_CFG__short_rc_filt_x_MASK 0x00020000L
+-#define DC_COMBOPHYPLLREGS6_VREG_CFG__vref_pwr_on_MASK 0x00040000L
+-#define DC_COMBOPHYPLLREGS6_VREG_CFG__dpll_cfg_2_MASK 0x0FF00000L
+-//DC_COMBOPHYPLLREGS6_OBSERVE0
+-#define DC_COMBOPHYPLLREGS6_OBSERVE0__lock_det_tdc_steps__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS6_OBSERVE0__clear_sticky_lock__SHIFT 0x6
+-#define DC_COMBOPHYPLLREGS6_OBSERVE0__lock_det_dis__SHIFT 0x8
+-#define DC_COMBOPHYPLLREGS6_OBSERVE0__dco_cfg__SHIFT 0xa
+-#define DC_COMBOPHYPLLREGS6_OBSERVE0__anaobs_sel__SHIFT 0x15
+-#define DC_COMBOPHYPLLREGS6_OBSERVE0__lock_det_tdc_steps_MASK 0x0000001FL
+-#define DC_COMBOPHYPLLREGS6_OBSERVE0__clear_sticky_lock_MASK 0x00000040L
+-#define DC_COMBOPHYPLLREGS6_OBSERVE0__lock_det_dis_MASK 0x00000100L
+-#define DC_COMBOPHYPLLREGS6_OBSERVE0__dco_cfg_MASK 0x0003FC00L
+-#define DC_COMBOPHYPLLREGS6_OBSERVE0__anaobs_sel_MASK 0x00E00000L
+-//DC_COMBOPHYPLLREGS6_OBSERVE1
+-#define DC_COMBOPHYPLLREGS6_OBSERVE1__digobs_sel__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS6_OBSERVE1__digobs_trig_sel__SHIFT 0x5
+-#define DC_COMBOPHYPLLREGS6_OBSERVE1__digobs_div__SHIFT 0xa
+-#define DC_COMBOPHYPLLREGS6_OBSERVE1__digobs_trig_div__SHIFT 0xd
+-#define DC_COMBOPHYPLLREGS6_OBSERVE1__lock_timer__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS6_OBSERVE1__digobs_sel_MASK 0x0000000FL
+-#define DC_COMBOPHYPLLREGS6_OBSERVE1__digobs_trig_sel_MASK 0x000001E0L
+-#define DC_COMBOPHYPLLREGS6_OBSERVE1__digobs_div_MASK 0x00000C00L
+-#define DC_COMBOPHYPLLREGS6_OBSERVE1__digobs_trig_div_MASK 0x00006000L
+-#define DC_COMBOPHYPLLREGS6_OBSERVE1__lock_timer_MASK 0x3FFF0000L
+-//DC_COMBOPHYPLLREGS6_DFT_OUT
+-#define DC_COMBOPHYPLLREGS6_DFT_OUT__dft_data__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS6_DFT_OUT__dft_data_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dcio_uniphy8_dispdec
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED32
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED33
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED34
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED35
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED36
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED37
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED38
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED39
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED40
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED41
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED42
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED43
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED44
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED45
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED46
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED47
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED48
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED49
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED50
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED51
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED52
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED53
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED54
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED55
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED56
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED57
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED58
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED59
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED60
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED61
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED62
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED63
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED64
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED65
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED66
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED67
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED68
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED69
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED70
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED71
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED72
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED73
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED74
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED75
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED76
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED77
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED78
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED79
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED80
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED81
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED82
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED83
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED84
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED85
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED86
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED87
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED88
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED89
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED90
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED91
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED92
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED93
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED94
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED95
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED96
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED97
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED98
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED99
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED100
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED101
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED102
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED103
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED104
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED105
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED106
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED107
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED108
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED109
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED110
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED111
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED112
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED113
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED114
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED115
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED116
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED117
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED118
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED119
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED120
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED121
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED122
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED123
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED124
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED125
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED126
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED127
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED128
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED129
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED130
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED131
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED132
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED133
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED134
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED135
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED136
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED137
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED138
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED139
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED140
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED141
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED142
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED143
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED144
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED145
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED146
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED147
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED148
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED149
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED150
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED151
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED152
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED153
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED154
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED155
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED156
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED157
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED158
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED159
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+-#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dc_combophycmregs8_dispdec
+-//DC_COMBOPHYCMREGS8_COMMON_FUSE1
+-#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_valid__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_unpopulated0__SHIFT 0x1
+-#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_ron_override_val__SHIFT 0x3
+-#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_unpopulated1__SHIFT 0x9
+-#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0xa
+-#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_unpopulated2__SHIFT 0xc
+-#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_rtt_override_val__SHIFT 0xd
+-#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_unpopulated3__SHIFT 0x13
+-#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0x14
+-#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_refresh_cal_en__SHIFT 0x16
+-#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_spare__SHIFT 0x17
+-#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_valid_MASK 0x00000001L
+-#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_unpopulated0_MASK 0x00000006L
+-#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_ron_override_val_MASK 0x000001F8L
+-#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_unpopulated1_MASK 0x00000200L
+-#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x00000C00L
+-#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_unpopulated2_MASK 0x00001000L
+-#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_rtt_override_val_MASK 0x0007E000L
+-#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_unpopulated3_MASK 0x00080000L
+-#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x00300000L
+-#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_refresh_cal_en_MASK 0x00400000L
+-#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_spare_MASK 0xFF800000L
+-//DC_COMBOPHYCMREGS8_COMMON_FUSE2
+-#define DC_COMBOPHYCMREGS8_COMMON_FUSE2__fuse2_valid__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS8_COMMON_FUSE2__fuse2_unpopulated__SHIFT 0x1
+-#define DC_COMBOPHYCMREGS8_COMMON_FUSE2__fuse2_tx_fifo_ptr__SHIFT 0x9
+-#define DC_COMBOPHYCMREGS8_COMMON_FUSE2__fuse2_spare__SHIFT 0xe
+-#define DC_COMBOPHYCMREGS8_COMMON_FUSE2__fuse2_valid_MASK 0x00000001L
+-#define DC_COMBOPHYCMREGS8_COMMON_FUSE2__fuse2_unpopulated_MASK 0x000001FEL
+-#define DC_COMBOPHYCMREGS8_COMMON_FUSE2__fuse2_tx_fifo_ptr_MASK 0x00003E00L
+-#define DC_COMBOPHYCMREGS8_COMMON_FUSE2__fuse2_spare_MASK 0xFFFFC000L
+-//DC_COMBOPHYCMREGS8_COMMON_FUSE3
+-#define DC_COMBOPHYCMREGS8_COMMON_FUSE3__fuse3_valid__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS8_COMMON_FUSE3__fuse3_unpopulated__SHIFT 0x1
+-#define DC_COMBOPHYCMREGS8_COMMON_FUSE3__fuse3_ei_det_thresh_sel__SHIFT 0xa
+-#define DC_COMBOPHYCMREGS8_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d
+-#define DC_COMBOPHYCMREGS8_COMMON_FUSE3__fuse3_valid_MASK 0x00000001L
+-#define DC_COMBOPHYCMREGS8_COMMON_FUSE3__fuse3_unpopulated_MASK 0x000003FEL
+-#define DC_COMBOPHYCMREGS8_COMMON_FUSE3__fuse3_ei_det_thresh_sel_MASK 0x00001C00L
+-#define DC_COMBOPHYCMREGS8_COMMON_FUSE3__fuse3_spare_MASK 0xE0000000L
+-//DC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM
+-#define DC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8
+-#define DC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10
+-#define DC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18
+-#define DC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0x000000FFL
+-#define DC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0x0000FF00L
+-#define DC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0x00FF0000L
+-#define DC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xFF000000L
+-//DC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT
+-#define DC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4
+-#define DC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT__vprot_en__SHIFT 0xb
+-#define DC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT__pgdelay_MASK 0x0000000FL
+-#define DC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT__pgmask_MASK 0x000003F0L
+-#define DC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT__vprot_en_MASK 0x00000800L
+-//DC_COMBOPHYCMREGS8_COMMON_TXCNTRL
+-#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__clkgate_dis__SHIFT 0x5
+-#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT 0x6
+-#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT 0x9
+-#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT 0xc
+-#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__dual_dvi_mstr_en__SHIFT 0xf
+-#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__dual_dvi_en__SHIFT 0x10
+-#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK 0x0000001FL
+-#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__clkgate_dis_MASK 0x00000020L
+-#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK 0x000001C0L
+-#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK 0x00000E00L
+-#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK 0x00007000L
+-#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__dual_dvi_mstr_en_MASK 0x00008000L
+-#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__dual_dvi_en_MASK 0x00010000L
+-//DC_COMBOPHYCMREGS8_COMMON_TMDP
+-#define DC_COMBOPHYCMREGS8_COMMON_TMDP__tmdp_spare__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS8_COMMON_TMDP__tmdp_spare_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS
+-#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_0_reset_l__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_1_reset_l__SHIFT 0x1
+-#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_2_reset_l__SHIFT 0x2
+-#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_3_reset_l__SHIFT 0x3
+-#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_4_reset_l__SHIFT 0x4
+-#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_5_reset_l__SHIFT 0x5
+-#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_6_reset_l__SHIFT 0x6
+-#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_7_reset_l__SHIFT 0x7
+-#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_0_reset_l_MASK 0x00000001L
+-#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_1_reset_l_MASK 0x00000002L
+-#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_2_reset_l_MASK 0x00000004L
+-#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_3_reset_l_MASK 0x00000008L
+-#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_4_reset_l_MASK 0x00000010L
+-#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_5_reset_l_MASK 0x00000020L
+-#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_6_reset_l_MASK 0x00000040L
+-#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_7_reset_l_MASK 0x00000080L
+-//DC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL
+-#define DC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT 0x1
+-#define DC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT 0x15
+-#define DC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL__zcalcode_override_MASK 0x00000001L
+-#define DC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK 0x0000003EL
+-#define DC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK 0x00200000L
+-//DC_COMBOPHYCMREGS8_COMMON_DISP_RFU1
+-#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU1__rfu_value1__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU1__rfu_value1_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS8_COMMON_DISP_RFU2
+-#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU2__rfu_value2__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU2__rfu_value2_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS8_COMMON_DISP_RFU3
+-#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU3__rfu_value3__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU3__rfu_value3_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS8_COMMON_DISP_RFU4
+-#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU4__rfu_value4__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU4__rfu_value4_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS8_COMMON_DISP_RFU5
+-#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU5__rfu_value5__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU5__rfu_value5_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS8_COMMON_DISP_RFU6
+-#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU6__rfu_value6__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU6__rfu_value6_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYCMREGS8_COMMON_DISP_RFU7
+-#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU7__rfu_value7__SHIFT 0x0
+-#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU7__rfu_value7_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dc_combophytxregs8_dispdec
+-//DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK 0x00000100L
+-//DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0
+-#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0__txmarg_sel_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0__deemph_sel_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0__tx_margin_en_MASK 0x00000020L
+-//DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x1
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT 0xa
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT 0xc
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT 0xd
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT 0xe
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT 0xf
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT 0x10
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT 0x14
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT 0x16
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x00000006L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0x000000E0L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK 0x00000300L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK 0x00000C00L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK 0x00001000L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK 0x00002000L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK 0x00004000L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK 0x00008000L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK 0x000F0000L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK 0x00100000L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK 0x00C00000L
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE0__rfu_value0__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE0__rfu_value0_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE0__rfu_value1__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE0__rfu_value1_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE0__rfu_value2__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE0__rfu_value2_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE0__rfu_value3__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE0__rfu_value3_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE0__rfu_value4__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE0__rfu_value4_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE0__rfu_value5__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE0__rfu_value5_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE0__rfu_value6__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE0__rfu_value6_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE0__rfu_value7__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE0__rfu_value7_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE0__rfu_value8__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE0__rfu_value8_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE0__rfu_value9__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE0__rfu_value9_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE0__rfu_value10__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE0__rfu_value10_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE0__rfu_value11__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE0__rfu_value11_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE0__rfu_value12__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE0__rfu_value12_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK 0x00000100L
+-//DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1
+-#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1__txmarg_sel_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1__deemph_sel_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1__tx_margin_en_MASK 0x00000020L
+-//DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x1
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT 0xa
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT 0xc
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT 0xd
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT 0xe
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT 0xf
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT 0x10
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT 0x14
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT 0x16
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x00000006L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0x000000E0L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK 0x00000300L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK 0x00000C00L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK 0x00001000L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK 0x00002000L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK 0x00004000L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK 0x00008000L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK 0x000F0000L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK 0x00100000L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK 0x00C00000L
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE1
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE1__rfu_value0__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE1__rfu_value0_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE1
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE1__rfu_value1__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE1__rfu_value1_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE1
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE1__rfu_value2__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE1__rfu_value2_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE1
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE1__rfu_value3__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE1__rfu_value3_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE1
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE1__rfu_value4__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE1__rfu_value4_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE1
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE1__rfu_value5__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE1__rfu_value5_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE1
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE1__rfu_value6__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE1__rfu_value6_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE1
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE1__rfu_value7__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE1__rfu_value7_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE1
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE1__rfu_value8__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE1__rfu_value8_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE1
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE1__rfu_value9__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE1__rfu_value9_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE1
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE1__rfu_value10__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE1__rfu_value10_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE1
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE1__rfu_value11__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE1__rfu_value11_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE1
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE1__rfu_value12__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE1__rfu_value12_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK 0x00000100L
+-//DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2
+-#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2__txmarg_sel_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2__deemph_sel_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2__tx_margin_en_MASK 0x00000020L
+-//DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x1
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT 0xa
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT 0xc
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT 0xd
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT 0xe
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT 0xf
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT 0x10
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT 0x14
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT 0x16
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x00000006L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0x000000E0L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK 0x00000300L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK 0x00000C00L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK 0x00001000L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK 0x00002000L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK 0x00004000L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK 0x00008000L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK 0x000F0000L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK 0x00100000L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK 0x00C00000L
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE2
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE2__rfu_value0__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE2__rfu_value0_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE2
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE2__rfu_value1__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE2__rfu_value1_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE2
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE2__rfu_value2__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE2__rfu_value2_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE2
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE2__rfu_value3__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE2__rfu_value3_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE2
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE2__rfu_value4__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE2__rfu_value4_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE2
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE2__rfu_value5__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE2__rfu_value5_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE2
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE2__rfu_value6__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE2__rfu_value6_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE2
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE2__rfu_value7__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE2__rfu_value7_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE2
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE2__rfu_value8__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE2__rfu_value8_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE2
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE2__rfu_value9__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE2__rfu_value9_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE2
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE2__rfu_value10__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE2__rfu_value10_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE2
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE2__rfu_value11__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE2__rfu_value11_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE2
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE2__rfu_value12__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE2__rfu_value12_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK 0x00000100L
+-//DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3
+-#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3__txmarg_sel_MASK 0x00000007L
+-#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3__deemph_sel_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3__tx_margin_en_MASK 0x00000020L
+-//DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x1
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x3
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT 0x8
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT 0xa
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT 0xc
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT 0xd
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT 0xe
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT 0xf
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT 0x10
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT 0x14
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT 0x16
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x00000006L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x00000018L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0x000000E0L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK 0x00000300L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK 0x00000C00L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK 0x00001000L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK 0x00002000L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK 0x00004000L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK 0x00008000L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK 0x000F0000L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK 0x00100000L
+-#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK 0x00C00000L
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE3
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE3__rfu_value0__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE3__rfu_value0_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE3
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE3__rfu_value1__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE3__rfu_value1_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE3
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE3__rfu_value2__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE3__rfu_value2_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE3
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE3__rfu_value3__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE3__rfu_value3_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE3
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE3__rfu_value4__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE3__rfu_value4_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE3
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE3__rfu_value5__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE3__rfu_value5_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE3
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE3__rfu_value6__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE3__rfu_value6_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE3
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE3__rfu_value7__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE3__rfu_value7_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE3
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE3__rfu_value8__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE3__rfu_value8_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE3
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE3__rfu_value9__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE3__rfu_value9_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE3
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE3__rfu_value10__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE3__rfu_value10_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE3
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE3__rfu_value11__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE3__rfu_value11_MASK 0xFFFFFFFFL
+-//DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE3
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE3__rfu_value12__SHIFT 0x0
+-#define DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE3__rfu_value12_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dc_combophypllregs8_dispdec
+-//DC_COMBOPHYPLLREGS8_FREQ_CTRL0
+-#define DC_COMBOPHYPLLREGS8_FREQ_CTRL0__fcw0_frac__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS8_FREQ_CTRL0__fcw0_int__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS8_FREQ_CTRL0__fcw0_frac_MASK 0x0000FFFFL
+-#define DC_COMBOPHYPLLREGS8_FREQ_CTRL0__fcw0_int_MASK 0x01FF0000L
+-//DC_COMBOPHYPLLREGS8_FREQ_CTRL1
+-#define DC_COMBOPHYPLLREGS8_FREQ_CTRL1__fcw1_frac__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS8_FREQ_CTRL1__fcw1_int__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS8_FREQ_CTRL1__fcw1_frac_MASK 0x0000FFFFL
+-#define DC_COMBOPHYPLLREGS8_FREQ_CTRL1__fcw1_int_MASK 0x01FF0000L
+-//DC_COMBOPHYPLLREGS8_FREQ_CTRL2
+-#define DC_COMBOPHYPLLREGS8_FREQ_CTRL2__fcw_denom__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS8_FREQ_CTRL2__fcw_slew_frac__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS8_FREQ_CTRL2__fcw_denom_MASK 0x0000FFFFL
+-#define DC_COMBOPHYPLLREGS8_FREQ_CTRL2__fcw_slew_frac_MASK 0xFFFF0000L
+-//DC_COMBOPHYPLLREGS8_FREQ_CTRL3
+-#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__refclk_div__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__vco_pre_div__SHIFT 0x3
+-#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__fracn_en__SHIFT 0x6
+-#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__ssc_en__SHIFT 0x8
+-#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__fcw_sel__SHIFT 0xa
+-#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__freq_jump_en__SHIFT 0xc
+-#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__tdc_resolution__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__dpll_cfg_1__SHIFT 0x18
+-#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__refclk_div_MASK 0x00000003L
+-#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__vco_pre_div_MASK 0x00000018L
+-#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__fracn_en_MASK 0x00000040L
+-#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__ssc_en_MASK 0x00000100L
+-#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__fcw_sel_MASK 0x00000400L
+-#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__freq_jump_en_MASK 0x00001000L
+-#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__tdc_resolution_MASK 0x00FF0000L
+-#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__dpll_cfg_1_MASK 0xFF000000L
+-//DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE
+-#define DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__gi_coarse_mant__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__gi_coarse_exp__SHIFT 0x2
+-#define DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__gp_coarse_mant__SHIFT 0x7
+-#define DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__gp_coarse_exp__SHIFT 0xc
+-#define DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__nctl_coarse_res__SHIFT 0x11
+-#define DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT 0x18
+-#define DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__gi_coarse_mant_MASK 0x00000003L
+-#define DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__gi_coarse_exp_MASK 0x0000003CL
+-#define DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__gp_coarse_mant_MASK 0x00000780L
+-#define DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__gp_coarse_exp_MASK 0x0000F000L
+-#define DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__nctl_coarse_res_MASK 0x007E0000L
+-#define DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__nctl_coarse_frac_res_MASK 0x03000000L
+-//DC_COMBOPHYPLLREGS8_BW_CTRL_FINE
+-#define DC_COMBOPHYPLLREGS8_BW_CTRL_FINE__dpll_cfg_3__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS8_BW_CTRL_FINE__dpll_cfg_3_MASK 0x000003FFL
+-//DC_COMBOPHYPLLREGS8_CAL_CTRL
+-#define DC_COMBOPHYPLLREGS8_CAL_CTRL__bypass_freq_lock__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS8_CAL_CTRL__tdc_cal_en__SHIFT 0x1
+-#define DC_COMBOPHYPLLREGS8_CAL_CTRL__tdc_cal_ctrl__SHIFT 0x3
+-#define DC_COMBOPHYPLLREGS8_CAL_CTRL__meas_win_sel__SHIFT 0x9
+-#define DC_COMBOPHYPLLREGS8_CAL_CTRL__kdco_cal_dis__SHIFT 0xb
+-#define DC_COMBOPHYPLLREGS8_CAL_CTRL__kdco_ratio__SHIFT 0xd
+-#define DC_COMBOPHYPLLREGS8_CAL_CTRL__kdco_incr_cal_dis__SHIFT 0x16
+-#define DC_COMBOPHYPLLREGS8_CAL_CTRL__nctl_adj_dis__SHIFT 0x17
+-#define DC_COMBOPHYPLLREGS8_CAL_CTRL__refclk_rate__SHIFT 0x18
+-#define DC_COMBOPHYPLLREGS8_CAL_CTRL__bypass_freq_lock_MASK 0x00000001L
+-#define DC_COMBOPHYPLLREGS8_CAL_CTRL__tdc_cal_en_MASK 0x00000002L
+-#define DC_COMBOPHYPLLREGS8_CAL_CTRL__tdc_cal_ctrl_MASK 0x000001F8L
+-#define DC_COMBOPHYPLLREGS8_CAL_CTRL__meas_win_sel_MASK 0x00000600L
+-#define DC_COMBOPHYPLLREGS8_CAL_CTRL__kdco_cal_dis_MASK 0x00000800L
+-#define DC_COMBOPHYPLLREGS8_CAL_CTRL__kdco_ratio_MASK 0x001FE000L
+-#define DC_COMBOPHYPLLREGS8_CAL_CTRL__kdco_incr_cal_dis_MASK 0x00400000L
+-#define DC_COMBOPHYPLLREGS8_CAL_CTRL__nctl_adj_dis_MASK 0x00800000L
+-#define DC_COMBOPHYPLLREGS8_CAL_CTRL__refclk_rate_MASK 0xFF000000L
+-//DC_COMBOPHYPLLREGS8_LOOP_CTRL
+-#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__fbdiv_mask_en__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__fb_slip_dis__SHIFT 0x2
+-#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__clk_tdc_sel__SHIFT 0x4
+-#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__clk_nctl_sel__SHIFT 0x7
+-#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__sig_del_patt_sel__SHIFT 0xa
+-#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__nctl_sig_del_dis__SHIFT 0xc
+-#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__fbclk_track_refclk__SHIFT 0xe
+-#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__prbs_en__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__tdc_clk_gate_en__SHIFT 0x12
+-#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__phase_offset__SHIFT 0x14
+-#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__fbdiv_mask_en_MASK 0x00000001L
+-#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__fb_slip_dis_MASK 0x00000004L
+-#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__clk_tdc_sel_MASK 0x00000030L
+-#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__clk_nctl_sel_MASK 0x00000180L
+-#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__sig_del_patt_sel_MASK 0x00000400L
+-#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__nctl_sig_del_dis_MASK 0x00001000L
+-#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__fbclk_track_refclk_MASK 0x00004000L
+-#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__prbs_en_MASK 0x00010000L
+-#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__tdc_clk_gate_en_MASK 0x00040000L
+-#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__phase_offset_MASK 0x07F00000L
+-//DC_COMBOPHYPLLREGS8_VREG_CFG
+-#define DC_COMBOPHYPLLREGS8_VREG_CFG__bleeder_ac__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS8_VREG_CFG__bleeder_en__SHIFT 0x1
+-#define DC_COMBOPHYPLLREGS8_VREG_CFG__is_1p2__SHIFT 0x2
+-#define DC_COMBOPHYPLLREGS8_VREG_CFG__reg_obs_sel__SHIFT 0x3
+-#define DC_COMBOPHYPLLREGS8_VREG_CFG__reg_on_mode__SHIFT 0x5
+-#define DC_COMBOPHYPLLREGS8_VREG_CFG__rlad_tap_sel__SHIFT 0x7
+-#define DC_COMBOPHYPLLREGS8_VREG_CFG__reg_off_hi__SHIFT 0xb
+-#define DC_COMBOPHYPLLREGS8_VREG_CFG__reg_off_lo__SHIFT 0xc
+-#define DC_COMBOPHYPLLREGS8_VREG_CFG__scale_driver__SHIFT 0xd
+-#define DC_COMBOPHYPLLREGS8_VREG_CFG__sel_bump__SHIFT 0xf
+-#define DC_COMBOPHYPLLREGS8_VREG_CFG__sel_rladder_x__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS8_VREG_CFG__short_rc_filt_x__SHIFT 0x11
+-#define DC_COMBOPHYPLLREGS8_VREG_CFG__vref_pwr_on__SHIFT 0x12
+-#define DC_COMBOPHYPLLREGS8_VREG_CFG__dpll_cfg_2__SHIFT 0x14
+-#define DC_COMBOPHYPLLREGS8_VREG_CFG__bleeder_ac_MASK 0x00000001L
+-#define DC_COMBOPHYPLLREGS8_VREG_CFG__bleeder_en_MASK 0x00000002L
+-#define DC_COMBOPHYPLLREGS8_VREG_CFG__is_1p2_MASK 0x00000004L
+-#define DC_COMBOPHYPLLREGS8_VREG_CFG__reg_obs_sel_MASK 0x00000018L
+-#define DC_COMBOPHYPLLREGS8_VREG_CFG__reg_on_mode_MASK 0x00000060L
+-#define DC_COMBOPHYPLLREGS8_VREG_CFG__rlad_tap_sel_MASK 0x00000780L
+-#define DC_COMBOPHYPLLREGS8_VREG_CFG__reg_off_hi_MASK 0x00000800L
+-#define DC_COMBOPHYPLLREGS8_VREG_CFG__reg_off_lo_MASK 0x00001000L
+-#define DC_COMBOPHYPLLREGS8_VREG_CFG__scale_driver_MASK 0x00006000L
+-#define DC_COMBOPHYPLLREGS8_VREG_CFG__sel_bump_MASK 0x00008000L
+-#define DC_COMBOPHYPLLREGS8_VREG_CFG__sel_rladder_x_MASK 0x00010000L
+-#define DC_COMBOPHYPLLREGS8_VREG_CFG__short_rc_filt_x_MASK 0x00020000L
+-#define DC_COMBOPHYPLLREGS8_VREG_CFG__vref_pwr_on_MASK 0x00040000L
+-#define DC_COMBOPHYPLLREGS8_VREG_CFG__dpll_cfg_2_MASK 0x0FF00000L
+-//DC_COMBOPHYPLLREGS8_OBSERVE0
+-#define DC_COMBOPHYPLLREGS8_OBSERVE0__lock_det_tdc_steps__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS8_OBSERVE0__clear_sticky_lock__SHIFT 0x6
+-#define DC_COMBOPHYPLLREGS8_OBSERVE0__lock_det_dis__SHIFT 0x8
+-#define DC_COMBOPHYPLLREGS8_OBSERVE0__dco_cfg__SHIFT 0xa
+-#define DC_COMBOPHYPLLREGS8_OBSERVE0__anaobs_sel__SHIFT 0x15
+-#define DC_COMBOPHYPLLREGS8_OBSERVE0__lock_det_tdc_steps_MASK 0x0000001FL
+-#define DC_COMBOPHYPLLREGS8_OBSERVE0__clear_sticky_lock_MASK 0x00000040L
+-#define DC_COMBOPHYPLLREGS8_OBSERVE0__lock_det_dis_MASK 0x00000100L
+-#define DC_COMBOPHYPLLREGS8_OBSERVE0__dco_cfg_MASK 0x0003FC00L
+-#define DC_COMBOPHYPLLREGS8_OBSERVE0__anaobs_sel_MASK 0x00E00000L
+-//DC_COMBOPHYPLLREGS8_OBSERVE1
+-#define DC_COMBOPHYPLLREGS8_OBSERVE1__digobs_sel__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS8_OBSERVE1__digobs_trig_sel__SHIFT 0x5
+-#define DC_COMBOPHYPLLREGS8_OBSERVE1__digobs_div__SHIFT 0xa
+-#define DC_COMBOPHYPLLREGS8_OBSERVE1__digobs_trig_div__SHIFT 0xd
+-#define DC_COMBOPHYPLLREGS8_OBSERVE1__lock_timer__SHIFT 0x10
+-#define DC_COMBOPHYPLLREGS8_OBSERVE1__digobs_sel_MASK 0x0000000FL
+-#define DC_COMBOPHYPLLREGS8_OBSERVE1__digobs_trig_sel_MASK 0x000001E0L
+-#define DC_COMBOPHYPLLREGS8_OBSERVE1__digobs_div_MASK 0x00000C00L
+-#define DC_COMBOPHYPLLREGS8_OBSERVE1__digobs_trig_div_MASK 0x00006000L
+-#define DC_COMBOPHYPLLREGS8_OBSERVE1__lock_timer_MASK 0x3FFF0000L
+-//DC_COMBOPHYPLLREGS8_DFT_OUT
+-#define DC_COMBOPHYPLLREGS8_DFT_OUT__dft_data__SHIFT 0x0
+-#define DC_COMBOPHYPLLREGS8_DFT_OUT__dft_data_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dsi0_dispdec
+-//DSI0_DISP_DSI_CTRL
+-#define DSI0_DISP_DSI_CTRL__DSI_EN__SHIFT 0x0
+-#define DSI0_DISP_DSI_CTRL__VIDEO_MODE_EN__SHIFT 0x1
+-#define DSI0_DISP_DSI_CTRL__CMD_MODE_EN__SHIFT 0x2
+-#define DSI0_DISP_DSI_CTRL__DLN0_EN__SHIFT 0x4
+-#define DSI0_DISP_DSI_CTRL__DLN1_EN__SHIFT 0x5
+-#define DSI0_DISP_DSI_CTRL__DLN2_EN__SHIFT 0x6
+-#define DSI0_DISP_DSI_CTRL__DLN3_EN__SHIFT 0x7
+-#define DSI0_DISP_DSI_CTRL__CLKLN_EN__SHIFT 0x8
+-#define DSI0_DISP_DSI_CTRL__DLN0_PHY_EN__SHIFT 0xc
+-#define DSI0_DISP_DSI_CTRL__DLN1_PHY_EN__SHIFT 0xd
+-#define DSI0_DISP_DSI_CTRL__DLN2_PHY_EN__SHIFT 0xe
+-#define DSI0_DISP_DSI_CTRL__DLN3_PHY_EN__SHIFT 0xf
+-#define DSI0_DISP_DSI_CTRL__RESET_DISPCLK__SHIFT 0x10
+-#define DSI0_DISP_DSI_CTRL__RESET_DSICLK__SHIFT 0x11
+-#define DSI0_DISP_DSI_CTRL__RESET_BYTECLK__SHIFT 0x12
+-#define DSI0_DISP_DSI_CTRL__RESET_ESCCLK__SHIFT 0x13
+-#define DSI0_DISP_DSI_CTRL__CRTC_SEL__SHIFT 0x14
+-#define DSI0_DISP_DSI_CTRL__ECC_CHK_EN__SHIFT 0x18
+-#define DSI0_DISP_DSI_CTRL__CRC_CHK_EN__SHIFT 0x19
+-#define DSI0_DISP_DSI_CTRL__PACKET_BYTE_MSB_LSB_FLIP__SHIFT 0x1c
+-#define DSI0_DISP_DSI_CTRL__PRE_TRIGGER_EN__SHIFT 0x1d
+-#define DSI0_DISP_DSI_CTRL__NEW_INTERLEAVE_MODE_EN__SHIFT 0x1e
+-#define DSI0_DISP_DSI_CTRL__DSI_EN_MASK 0x00000001L
+-#define DSI0_DISP_DSI_CTRL__VIDEO_MODE_EN_MASK 0x00000002L
+-#define DSI0_DISP_DSI_CTRL__CMD_MODE_EN_MASK 0x00000004L
+-#define DSI0_DISP_DSI_CTRL__DLN0_EN_MASK 0x00000010L
+-#define DSI0_DISP_DSI_CTRL__DLN1_EN_MASK 0x00000020L
+-#define DSI0_DISP_DSI_CTRL__DLN2_EN_MASK 0x00000040L
+-#define DSI0_DISP_DSI_CTRL__DLN3_EN_MASK 0x00000080L
+-#define DSI0_DISP_DSI_CTRL__CLKLN_EN_MASK 0x00000100L
+-#define DSI0_DISP_DSI_CTRL__DLN0_PHY_EN_MASK 0x00001000L
+-#define DSI0_DISP_DSI_CTRL__DLN1_PHY_EN_MASK 0x00002000L
+-#define DSI0_DISP_DSI_CTRL__DLN2_PHY_EN_MASK 0x00004000L
+-#define DSI0_DISP_DSI_CTRL__DLN3_PHY_EN_MASK 0x00008000L
+-#define DSI0_DISP_DSI_CTRL__RESET_DISPCLK_MASK 0x00010000L
+-#define DSI0_DISP_DSI_CTRL__RESET_DSICLK_MASK 0x00020000L
+-#define DSI0_DISP_DSI_CTRL__RESET_BYTECLK_MASK 0x00040000L
+-#define DSI0_DISP_DSI_CTRL__RESET_ESCCLK_MASK 0x00080000L
+-#define DSI0_DISP_DSI_CTRL__CRTC_SEL_MASK 0x00700000L
+-#define DSI0_DISP_DSI_CTRL__ECC_CHK_EN_MASK 0x01000000L
+-#define DSI0_DISP_DSI_CTRL__CRC_CHK_EN_MASK 0x02000000L
+-#define DSI0_DISP_DSI_CTRL__PACKET_BYTE_MSB_LSB_FLIP_MASK 0x10000000L
+-#define DSI0_DISP_DSI_CTRL__PRE_TRIGGER_EN_MASK 0x20000000L
+-#define DSI0_DISP_DSI_CTRL__NEW_INTERLEAVE_MODE_EN_MASK 0x40000000L
+-//DSI0_DISP_DSI_STATUS
+-#define DSI0_DISP_DSI_STATUS__CMD_MODE_ENGINE_BUSY__SHIFT 0x0
+-#define DSI0_DISP_DSI_STATUS__CMD_MODE_DMA_BUSY__SHIFT 0x1
+-#define DSI0_DISP_DSI_STATUS__CMD_MODE_DENG_BUSY__SHIFT 0x2
+-#define DSI0_DISP_DSI_STATUS__VIDEO_MODE_ENGINE_BUSY__SHIFT 0x3
+-#define DSI0_DISP_DSI_STATUS__BTA_BUSY__SHIFT 0x4
+-#define DSI0_DISP_DSI_STATUS__GENERIC_TRIGGER_BUSY__SHIFT 0x5
+-#define DSI0_DISP_DSI_STATUS__PHY_RESET_BUSY__SHIFT 0x6
+-#define DSI0_DISP_DSI_STATUS__DLN0_HS_FIFO_EMPTY__SHIFT 0x8
+-#define DSI0_DISP_DSI_STATUS__DLN0_HS_FIFO_FULL__SHIFT 0x9
+-#define DSI0_DISP_DSI_STATUS__DLN1_HS_FIFO_EMPTY__SHIFT 0xa
+-#define DSI0_DISP_DSI_STATUS__DLN1_HS_FIFO_FULL__SHIFT 0xb
+-#define DSI0_DISP_DSI_STATUS__DLN2_HS_FIFO_EMPTY__SHIFT 0xc
+-#define DSI0_DISP_DSI_STATUS__DLN2_HS_FIFO_FULL__SHIFT 0xd
+-#define DSI0_DISP_DSI_STATUS__DLN3_HS_FIFO_EMPTY__SHIFT 0xe
+-#define DSI0_DISP_DSI_STATUS__DLN3_HS_FIFO_FULL__SHIFT 0xf
+-#define DSI0_DISP_DSI_STATUS__DLN0_HS_FIFO_OVERFLOW__SHIFT 0x10
+-#define DSI0_DISP_DSI_STATUS__DLN0_HS_FIFO_OVERFLOW_CLR__SHIFT 0x10
+-#define DSI0_DISP_DSI_STATUS__DLN1_HS_FIFO_OVERFLOW__SHIFT 0x11
+-#define DSI0_DISP_DSI_STATUS__DLN1_HS_FIFO_OVERFLOW_CLR__SHIFT 0x11
+-#define DSI0_DISP_DSI_STATUS__DLN2_HS_FIFO_OVERFLOW__SHIFT 0x12
+-#define DSI0_DISP_DSI_STATUS__DLN2_HS_FIFO_OVERFLOW_CLR__SHIFT 0x12
+-#define DSI0_DISP_DSI_STATUS__DLN3_HS_FIFO_OVERFLOW__SHIFT 0x13
+-#define DSI0_DISP_DSI_STATUS__DLN3_HS_FIFO_OVERFLOW_CLR__SHIFT 0x13
+-#define DSI0_DISP_DSI_STATUS__DLN0_LP_FIFO_EMPTY__SHIFT 0x14
+-#define DSI0_DISP_DSI_STATUS__DLN0_LP_FIFO_FULL__SHIFT 0x15
+-#define DSI0_DISP_DSI_STATUS__DLN0_LP_FIFO_OVERFLOW__SHIFT 0x16
+-#define DSI0_DISP_DSI_STATUS__DLN0_LP_FIFO_OVERFLOW_CLR__SHIFT 0x16
+-#define DSI0_DISP_DSI_STATUS__CMDFIFO_UNDERFLOW__SHIFT 0x17
+-#define DSI0_DISP_DSI_STATUS__CMDFIFO_UNDERFLOW_CLR__SHIFT 0x17
+-#define DSI0_DISP_DSI_STATUS__INTERLEAVE_PACKET_BLOCK__SHIFT 0x18
+-#define DSI0_DISP_DSI_STATUS__INTERLEAVE_PACKET_BLOCK_CLR__SHIFT 0x18
+-#define DSI0_DISP_DSI_STATUS__TE_ABORT__SHIFT 0x19
+-#define DSI0_DISP_DSI_STATUS__TE_ABORT_CLR__SHIFT 0x19
+-#define DSI0_DISP_DSI_STATUS__DMAFIFO_RD_WATERMARK_REACH__SHIFT 0x1c
+-#define DSI0_DISP_DSI_STATUS__DMAFIFO_RD_WATERMARK_REACH_CLR__SHIFT 0x1c
+-#define DSI0_DISP_DSI_STATUS__DMAFIFO_WR_WATERMARK_REACH__SHIFT 0x1d
+-#define DSI0_DISP_DSI_STATUS__DMAFIFO_WR_WATERMARK_REACH_CLR__SHIFT 0x1d
+-#define DSI0_DISP_DSI_STATUS__DMAFIFO_UNDERFLOW__SHIFT 0x1e
+-#define DSI0_DISP_DSI_STATUS__DMAFIFO_UNDERFLOW_CLR__SHIFT 0x1e
+-#define DSI0_DISP_DSI_STATUS__INTERLEAVE_OP_CONTENTION__SHIFT 0x1f
+-#define DSI0_DISP_DSI_STATUS__INTERLEAVE_OP_CONTENTION_CLR__SHIFT 0x1f
+-#define DSI0_DISP_DSI_STATUS__CMD_MODE_ENGINE_BUSY_MASK 0x00000001L
+-#define DSI0_DISP_DSI_STATUS__CMD_MODE_DMA_BUSY_MASK 0x00000002L
+-#define DSI0_DISP_DSI_STATUS__CMD_MODE_DENG_BUSY_MASK 0x00000004L
+-#define DSI0_DISP_DSI_STATUS__VIDEO_MODE_ENGINE_BUSY_MASK 0x00000008L
+-#define DSI0_DISP_DSI_STATUS__BTA_BUSY_MASK 0x00000010L
+-#define DSI0_DISP_DSI_STATUS__GENERIC_TRIGGER_BUSY_MASK 0x00000020L
+-#define DSI0_DISP_DSI_STATUS__PHY_RESET_BUSY_MASK 0x00000040L
+-#define DSI0_DISP_DSI_STATUS__DLN0_HS_FIFO_EMPTY_MASK 0x00000100L
+-#define DSI0_DISP_DSI_STATUS__DLN0_HS_FIFO_FULL_MASK 0x00000200L
+-#define DSI0_DISP_DSI_STATUS__DLN1_HS_FIFO_EMPTY_MASK 0x00000400L
+-#define DSI0_DISP_DSI_STATUS__DLN1_HS_FIFO_FULL_MASK 0x00000800L
+-#define DSI0_DISP_DSI_STATUS__DLN2_HS_FIFO_EMPTY_MASK 0x00001000L
+-#define DSI0_DISP_DSI_STATUS__DLN2_HS_FIFO_FULL_MASK 0x00002000L
+-#define DSI0_DISP_DSI_STATUS__DLN3_HS_FIFO_EMPTY_MASK 0x00004000L
+-#define DSI0_DISP_DSI_STATUS__DLN3_HS_FIFO_FULL_MASK 0x00008000L
+-#define DSI0_DISP_DSI_STATUS__DLN0_HS_FIFO_OVERFLOW_MASK 0x00010000L
+-#define DSI0_DISP_DSI_STATUS__DLN0_HS_FIFO_OVERFLOW_CLR_MASK 0x00010000L
+-#define DSI0_DISP_DSI_STATUS__DLN1_HS_FIFO_OVERFLOW_MASK 0x00020000L
+-#define DSI0_DISP_DSI_STATUS__DLN1_HS_FIFO_OVERFLOW_CLR_MASK 0x00020000L
+-#define DSI0_DISP_DSI_STATUS__DLN2_HS_FIFO_OVERFLOW_MASK 0x00040000L
+-#define DSI0_DISP_DSI_STATUS__DLN2_HS_FIFO_OVERFLOW_CLR_MASK 0x00040000L
+-#define DSI0_DISP_DSI_STATUS__DLN3_HS_FIFO_OVERFLOW_MASK 0x00080000L
+-#define DSI0_DISP_DSI_STATUS__DLN3_HS_FIFO_OVERFLOW_CLR_MASK 0x00080000L
+-#define DSI0_DISP_DSI_STATUS__DLN0_LP_FIFO_EMPTY_MASK 0x00100000L
+-#define DSI0_DISP_DSI_STATUS__DLN0_LP_FIFO_FULL_MASK 0x00200000L
+-#define DSI0_DISP_DSI_STATUS__DLN0_LP_FIFO_OVERFLOW_MASK 0x00400000L
+-#define DSI0_DISP_DSI_STATUS__DLN0_LP_FIFO_OVERFLOW_CLR_MASK 0x00400000L
+-#define DSI0_DISP_DSI_STATUS__CMDFIFO_UNDERFLOW_MASK 0x00800000L
+-#define DSI0_DISP_DSI_STATUS__CMDFIFO_UNDERFLOW_CLR_MASK 0x00800000L
+-#define DSI0_DISP_DSI_STATUS__INTERLEAVE_PACKET_BLOCK_MASK 0x01000000L
+-#define DSI0_DISP_DSI_STATUS__INTERLEAVE_PACKET_BLOCK_CLR_MASK 0x01000000L
+-#define DSI0_DISP_DSI_STATUS__TE_ABORT_MASK 0x02000000L
+-#define DSI0_DISP_DSI_STATUS__TE_ABORT_CLR_MASK 0x02000000L
+-#define DSI0_DISP_DSI_STATUS__DMAFIFO_RD_WATERMARK_REACH_MASK 0x10000000L
+-#define DSI0_DISP_DSI_STATUS__DMAFIFO_RD_WATERMARK_REACH_CLR_MASK 0x10000000L
+-#define DSI0_DISP_DSI_STATUS__DMAFIFO_WR_WATERMARK_REACH_MASK 0x20000000L
+-#define DSI0_DISP_DSI_STATUS__DMAFIFO_WR_WATERMARK_REACH_CLR_MASK 0x20000000L
+-#define DSI0_DISP_DSI_STATUS__DMAFIFO_UNDERFLOW_MASK 0x40000000L
+-#define DSI0_DISP_DSI_STATUS__DMAFIFO_UNDERFLOW_CLR_MASK 0x40000000L
+-#define DSI0_DISP_DSI_STATUS__INTERLEAVE_OP_CONTENTION_MASK 0x80000000L
+-#define DSI0_DISP_DSI_STATUS__INTERLEAVE_OP_CONTENTION_CLR_MASK 0x80000000L
+-//DSI0_DISP_DSI_VIDEO_MODE_CTRL
+-#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__VC__SHIFT 0x0
+-#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__DST_FORMAT__SHIFT 0x4
+-#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__TRAFFIC_MODE__SHIFT 0x8
+-#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__BLLP_PWR_MODE__SHIFT 0xc
+-#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__EOF_BLLP_PWR_MODE__SHIFT 0xf
+-#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__HSA_PWR_MODE__SHIFT 0x10
+-#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__HBP_PWR_MODE__SHIFT 0x14
+-#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__HFP_PWR_MODE__SHIFT 0x18
+-#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__PULSE_MODE_OPT__SHIFT 0x1c
+-#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__VC_MASK 0x00000003L
+-#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__DST_FORMAT_MASK 0x00000030L
+-#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__TRAFFIC_MODE_MASK 0x00000300L
+-#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__BLLP_PWR_MODE_MASK 0x00001000L
+-#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__EOF_BLLP_PWR_MODE_MASK 0x00008000L
+-#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__HSA_PWR_MODE_MASK 0x00010000L
+-#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__HBP_PWR_MODE_MASK 0x00100000L
+-#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__HFP_PWR_MODE_MASK 0x01000000L
+-#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__PULSE_MODE_OPT_MASK 0x10000000L
+-//DSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE
+-#define DSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__VS__SHIFT 0x0
+-#define DSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__VE__SHIFT 0x8
+-#define DSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__HS__SHIFT 0x10
+-#define DSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__HE__SHIFT 0x18
+-#define DSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__VS_MASK 0x0000003FL
+-#define DSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__VE_MASK 0x00003F00L
+-#define DSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__HS_MASK 0x003F0000L
+-#define DSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__HE_MASK 0x3F000000L
+-//DSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD
+-#define DSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD__VS_PAYLOAD__SHIFT 0x0
+-#define DSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD__VE_PAYLOAD__SHIFT 0x10
+-#define DSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD__VS_PAYLOAD_MASK 0x0000FFFFL
+-#define DSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD__VE_PAYLOAD_MASK 0xFFFF0000L
+-//DSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD
+-#define DSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD__HS_PAYLOAD__SHIFT 0x0
+-#define DSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD__HE_PAYLOAD__SHIFT 0x10
+-#define DSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD__HS_PAYLOAD_MASK 0x0000FFFFL
+-#define DSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD__HE_PAYLOAD_MASK 0xFFFF0000L
+-//DSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE
+-#define DSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB565__SHIFT 0x0
+-#define DSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB666_PACKED__SHIFT 0x8
+-#define DSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB666__SHIFT 0x10
+-#define DSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB888__SHIFT 0x18
+-#define DSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB565_MASK 0x0000003FL
+-#define DSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB666_PACKED_MASK 0x00003F00L
+-#define DSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB666_MASK 0x003F0000L
+-#define DSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB888_MASK 0x3F000000L
+-//DSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE
+-#define DSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE__BLANK_PKT_DATA__SHIFT 0x0
+-#define DSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE__BLANK_PKT_DATATYPE__SHIFT 0x8
+-#define DSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE__BLANK_PKT_DATA_MASK 0x000000FFL
+-#define DSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE__BLANK_PKT_DATATYPE_MASK 0x00003F00L
+-//DSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL
+-#define DSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL__R_SEL__SHIFT 0x0
+-#define DSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL__G_SEL__SHIFT 0x4
+-#define DSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL__B_SEL__SHIFT 0x8
+-#define DSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL__RGB_SWAP__SHIFT 0xc
+-#define DSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL__R_SEL_MASK 0x00000001L
+-#define DSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL__G_SEL_MASK 0x00000010L
+-#define DSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL__B_SEL_MASK 0x00000100L
+-#define DSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL__RGB_SWAP_MASK 0x00007000L
+-//DSI0_DISP_DSI_COMMAND_MODE_CTRL
+-#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__WC__SHIFT 0x0
+-#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__DT__SHIFT 0x10
+-#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__VC__SHIFT 0x16
+-#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__PACKET_TYPE__SHIFT 0x18
+-#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__POWER_MODE__SHIFT 0x1a
+-#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__EMBEDDED_MODE__SHIFT 0x1c
+-#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__CMD_DATA_ORDER__SHIFT 0x1f
+-#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__WC_MASK 0x0000FFFFL
+-#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__DT_MASK 0x003F0000L
+-#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__VC_MASK 0x00C00000L
+-#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__PACKET_TYPE_MASK 0x01000000L
+-#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__POWER_MODE_MASK 0x04000000L
+-#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__EMBEDDED_MODE_MASK 0x10000000L
+-#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__CMD_DATA_ORDER_MASK 0x80000000L
+-//DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL
+-#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__SRC_FORMAT__SHIFT 0x0
+-#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__DST_FORMAT__SHIFT 0x4
+-#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__DATA_BUFFER_ID__SHIFT 0x8
+-#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__SHADOW_DATA_BUFFER_ID__SHIFT 0xc
+-#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__R_SEL__SHIFT 0x10
+-#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__G_SEL__SHIFT 0x11
+-#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__B_SEL__SHIFT 0x12
+-#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__RGB_SWAP__SHIFT 0x14
+-#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__DWORD_BYTE_SWAP__SHIFT 0x18
+-#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__SRC_FORMAT_MASK 0x0000000FL
+-#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__DST_FORMAT_MASK 0x000000F0L
+-#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__DATA_BUFFER_ID_MASK 0x00000100L
+-#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__SHADOW_DATA_BUFFER_ID_MASK 0x00001000L
+-#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__R_SEL_MASK 0x00010000L
+-#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__G_SEL_MASK 0x00020000L
+-#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__B_SEL_MASK 0x00040000L
+-#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__RGB_SWAP_MASK 0x00700000L
+-#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__DWORD_BYTE_SWAP_MASK 0x03000000L
+-//DSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL
+-#define DSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__WR_MEM_START__SHIFT 0x0
+-#define DSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__WR_MEM_CONTINUE__SHIFT 0x8
+-#define DSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__INSERT_DCS_COMMAND__SHIFT 0x10
+-#define DSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__WR_MEM_START_MASK 0x000000FFL
+-#define DSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__WR_MEM_CONTINUE_MASK 0x0000FF00L
+-#define DSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__INSERT_DCS_COMMAND_MASK 0x00010000L
+-//DSI0_DISP_DSI_DMA_CMD_OFFSET
+-#define DSI0_DISP_DSI_DMA_CMD_OFFSET__CMD_OFFSET__SHIFT 0x0
+-#define DSI0_DISP_DSI_DMA_CMD_OFFSET__CMD_OFFSET_MASK 0xFFFFFFFFL
+-//DSI0_DISP_DSI_DMA_CMD_LENGTH
+-#define DSI0_DISP_DSI_DMA_CMD_LENGTH__CMD_LENGTH__SHIFT 0x0
+-#define DSI0_DISP_DSI_DMA_CMD_LENGTH__CMD_LENGTH_MASK 0x00FFFFFFL
+-//DSI0_DISP_DSI_DMA_DATA_OFFSET_0
+-#define DSI0_DISP_DSI_DMA_DATA_OFFSET_0__DATA_SRC_OFFSET0__SHIFT 0x0
+-#define DSI0_DISP_DSI_DMA_DATA_OFFSET_0__DATA_SRC_OFFSET0_MASK 0xFFFFFFFFL
+-//DSI0_DISP_DSI_DMA_DATA_OFFSET_1
+-#define DSI0_DISP_DSI_DMA_DATA_OFFSET_1__DATA_SRC_OFFSET1__SHIFT 0x0
+-#define DSI0_DISP_DSI_DMA_DATA_OFFSET_1__DATA_SRC_OFFSET1_MASK 0xFFFFFFFFL
+-//DSI0_DISP_DSI_DMA_DATA_PITCH
+-#define DSI0_DISP_DSI_DMA_DATA_PITCH__DATA_SRC_PITCH__SHIFT 0x0
+-#define DSI0_DISP_DSI_DMA_DATA_PITCH__DATA_SRC_PITCH_MASK 0x00007FFFL
+-//DSI0_DISP_DSI_DMA_DATA_WIDTH
+-#define DSI0_DISP_DSI_DMA_DATA_WIDTH__DATA_SRC_WIDTH__SHIFT 0x0
+-#define DSI0_DISP_DSI_DMA_DATA_WIDTH__DATA_SRC_WIDTH_ALIGN__SHIFT 0x18
+-#define DSI0_DISP_DSI_DMA_DATA_WIDTH__DATA_SRC_WIDTH_MASK 0x000FFFFFL
+-#define DSI0_DISP_DSI_DMA_DATA_WIDTH__DATA_SRC_WIDTH_ALIGN_MASK 0x07000000L
+-//DSI0_DISP_DSI_DMA_DATA_HEIGHT
+-#define DSI0_DISP_DSI_DMA_DATA_HEIGHT__DATA_SRC_HEIGHT__SHIFT 0x0
+-#define DSI0_DISP_DSI_DMA_DATA_HEIGHT__DATA_SRC_HEIGHT_MASK 0x00000FFFL
+-//DSI0_DISP_DSI_DMA_FIFO_CTRL
+-#define DSI0_DISP_DSI_DMA_FIFO_CTRL__WRITE_WATERMARK__SHIFT 0x0
+-#define DSI0_DISP_DSI_DMA_FIFO_CTRL__READ_WATERMARK__SHIFT 0x4
+-#define DSI0_DISP_DSI_DMA_FIFO_CTRL__WRITE_WATERMARK_MASK 0x00000003L
+-#define DSI0_DISP_DSI_DMA_FIFO_CTRL__READ_WATERMARK_MASK 0x00000030L
+-//DSI0_DISP_DSI_DMA_NULL_PACKET_DATA
+-#define DSI0_DISP_DSI_DMA_NULL_PACKET_DATA__NULL_DATA__SHIFT 0x0
+-#define DSI0_DISP_DSI_DMA_NULL_PACKET_DATA__NULL_DATATYPE__SHIFT 0x8
+-#define DSI0_DISP_DSI_DMA_NULL_PACKET_DATA__NULL_DATA_MASK 0x000000FFL
+-#define DSI0_DISP_DSI_DMA_NULL_PACKET_DATA__NULL_DATATYPE_MASK 0x00003F00L
+-//DSI0_DISP_DSI_DENG_DATA_LENGTH
+-#define DSI0_DISP_DSI_DENG_DATA_LENGTH__DENG_LENGTH__SHIFT 0x0
+-#define DSI0_DISP_DSI_DENG_DATA_LENGTH__USE_DENG_LENGTH__SHIFT 0x1f
+-#define DSI0_DISP_DSI_DENG_DATA_LENGTH__DENG_LENGTH_MASK 0x00FFFFFFL
+-#define DSI0_DISP_DSI_DENG_DATA_LENGTH__USE_DENG_LENGTH_MASK 0x80000000L
+-//DSI0_DISP_DSI_ACK_ERROR_REPORT
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__SOT_ERR__SHIFT 0x0
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__SOT_ERR_CLR__SHIFT 0x0
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__SOT_SYNC_ERR__SHIFT 0x1
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__SOT_SYNC_ERR_CLR__SHIFT 0x1
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__EOT_ERR__SHIFT 0x2
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__EOT_ERR_CLR__SHIFT 0x2
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ESC_ERR__SHIFT 0x3
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ESC_ERR_CLR__SHIFT 0x3
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__LP_ERR__SHIFT 0x4
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__LP_ERR_CLR__SHIFT 0x4
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__HRX_TO__SHIFT 0x5
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__HRX_TO_CLR__SHIFT 0x5
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__FALSE_CTRL_ERR__SHIFT 0x6
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__FALSE_CTRL_ERR_CLR__SHIFT 0x6
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__CONTENTION_ERR__SHIFT 0x7
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__CONTENTION_ERR_CLR__SHIFT 0x7
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ECC_ERR__SHIFT 0x8
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ECC_ERR_CLR__SHIFT 0x8
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__MULTI_ECC_ERR__SHIFT 0x9
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__MULTI_ECC_ERR_CLR__SHIFT 0x9
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__CRC_ERR__SHIFT 0xa
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__CRC_ERR_CLR__SHIFT 0xa
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__DT_ERR__SHIFT 0xb
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__DT_ERR_CLR__SHIFT 0xb
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__VC_ERR__SHIFT 0xc
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__VC_ERR_CLR__SHIFT 0xc
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__PROTOCOL_VIOLATION__SHIFT 0xd
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__PROTOCOL_VIOLATION_CLR__SHIFT 0xd
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__PANEL_SPECIFIC_ERR__SHIFT 0xf
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__PANEL_SPECIFIC_ERR_CLR__SHIFT 0xf
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_ECC_ERR__SHIFT 0x10
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_ECC_ERR_CLR__SHIFT 0x10
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_MULTI_ECC_ERR__SHIFT 0x11
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_MULTI_ECC_ERR_CLR__SHIFT 0x11
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_CRC_ERR__SHIFT 0x14
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_CRC_ERR_CLR__SHIFT 0x14
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_INCOMPLETE_PACKET_ERR__SHIFT 0x17
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_INCOMPLETE_PACKET_ERR_CLR__SHIFT 0x17
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ERROR__SHIFT 0x18
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ERROR_CLR__SHIFT 0x18
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ACK__SHIFT 0x1c
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ACK_CLR__SHIFT 0x1c
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__SOT_ERR_MASK 0x00000001L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__SOT_ERR_CLR_MASK 0x00000001L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__SOT_SYNC_ERR_MASK 0x00000002L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__SOT_SYNC_ERR_CLR_MASK 0x00000002L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__EOT_ERR_MASK 0x00000004L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__EOT_ERR_CLR_MASK 0x00000004L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ESC_ERR_MASK 0x00000008L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ESC_ERR_CLR_MASK 0x00000008L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__LP_ERR_MASK 0x00000010L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__LP_ERR_CLR_MASK 0x00000010L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__HRX_TO_MASK 0x00000020L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__HRX_TO_CLR_MASK 0x00000020L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__FALSE_CTRL_ERR_MASK 0x00000040L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__FALSE_CTRL_ERR_CLR_MASK 0x00000040L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__CONTENTION_ERR_MASK 0x00000080L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__CONTENTION_ERR_CLR_MASK 0x00000080L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ECC_ERR_MASK 0x00000100L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ECC_ERR_CLR_MASK 0x00000100L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__MULTI_ECC_ERR_MASK 0x00000200L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__MULTI_ECC_ERR_CLR_MASK 0x00000200L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__CRC_ERR_MASK 0x00000400L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__CRC_ERR_CLR_MASK 0x00000400L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__DT_ERR_MASK 0x00000800L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__DT_ERR_CLR_MASK 0x00000800L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__VC_ERR_MASK 0x00001000L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__VC_ERR_CLR_MASK 0x00001000L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__PROTOCOL_VIOLATION_MASK 0x00002000L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__PROTOCOL_VIOLATION_CLR_MASK 0x00002000L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__PANEL_SPECIFIC_ERR_MASK 0x00008000L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__PANEL_SPECIFIC_ERR_CLR_MASK 0x00008000L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_ECC_ERR_MASK 0x00010000L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_ECC_ERR_CLR_MASK 0x00010000L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_MULTI_ECC_ERR_MASK 0x00020000L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_MULTI_ECC_ERR_CLR_MASK 0x00020000L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_CRC_ERR_MASK 0x00100000L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_CRC_ERR_CLR_MASK 0x00100000L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_INCOMPLETE_PACKET_ERR_MASK 0x00800000L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_INCOMPLETE_PACKET_ERR_CLR_MASK 0x00800000L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ERROR_MASK 0x01000000L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ERROR_CLR_MASK 0x01000000L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ACK_MASK 0x10000000L
+-#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ACK_CLR_MASK 0x10000000L
+-//DSI0_DISP_DSI_RDBK_DATA0
+-#define DSI0_DISP_DSI_RDBK_DATA0__RD_DATA0__SHIFT 0x0
+-#define DSI0_DISP_DSI_RDBK_DATA0__RD_DATA0_MASK 0xFFFFFFFFL
+-//DSI0_DISP_DSI_RDBK_DATA1
+-#define DSI0_DISP_DSI_RDBK_DATA1__RD_DATA1__SHIFT 0x0
+-#define DSI0_DISP_DSI_RDBK_DATA1__RD_DATA1_MASK 0xFFFFFFFFL
+-//DSI0_DISP_DSI_RDBK_DATA2
+-#define DSI0_DISP_DSI_RDBK_DATA2__RD_DATA2__SHIFT 0x0
+-#define DSI0_DISP_DSI_RDBK_DATA2__RD_DATA2_MASK 0xFFFFFFFFL
+-//DSI0_DISP_DSI_RDBK_DATA3
+-#define DSI0_DISP_DSI_RDBK_DATA3__RD_DATA3__SHIFT 0x0
+-#define DSI0_DISP_DSI_RDBK_DATA3__RD_DATA3_MASK 0xFFFFFFFFL
+-//DSI0_DISP_DSI_RDBK_DATATYPE0
+-#define DSI0_DISP_DSI_RDBK_DATATYPE0__GENERIC_SHORT_RD_1_BYTE__SHIFT 0x0
+-#define DSI0_DISP_DSI_RDBK_DATATYPE0__GENERIC_SHORT_RD_2_BYTE__SHIFT 0x8
+-#define DSI0_DISP_DSI_RDBK_DATATYPE0__DCS_SHORT_RD_1_BYTE__SHIFT 0x10
+-#define DSI0_DISP_DSI_RDBK_DATATYPE0__DCS_SHORT_RD_2_BYTE__SHIFT 0x18
+-#define DSI0_DISP_DSI_RDBK_DATATYPE0__GENERIC_SHORT_RD_1_BYTE_MASK 0x0000003FL
+-#define DSI0_DISP_DSI_RDBK_DATATYPE0__GENERIC_SHORT_RD_2_BYTE_MASK 0x00003F00L
+-#define DSI0_DISP_DSI_RDBK_DATATYPE0__DCS_SHORT_RD_1_BYTE_MASK 0x003F0000L
+-#define DSI0_DISP_DSI_RDBK_DATATYPE0__DCS_SHORT_RD_2_BYTE_MASK 0x3F000000L
+-//DSI0_DISP_DSI_RDBK_DATATYPE1
+-#define DSI0_DISP_DSI_RDBK_DATATYPE1__ERROR_REPORT__SHIFT 0x0
+-#define DSI0_DISP_DSI_RDBK_DATATYPE1__GENERIC_LONG_RD__SHIFT 0x8
+-#define DSI0_DISP_DSI_RDBK_DATATYPE1__DCS_LONG_RD__SHIFT 0x10
+-#define DSI0_DISP_DSI_RDBK_DATATYPE1__ERROR_REPORT_MASK 0x0000003FL
+-#define DSI0_DISP_DSI_RDBK_DATATYPE1__GENERIC_LONG_RD_MASK 0x00003F00L
+-#define DSI0_DISP_DSI_RDBK_DATATYPE1__DCS_LONG_RD_MASK 0x003F0000L
+-//DSI0_DISP_DSI_TRIG_CTRL
+-#define DSI0_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_TRIGGER_MODE__SHIFT 0x0
+-#define DSI0_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_TRIGGER_SEL__SHIFT 0x4
+-#define DSI0_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DENG_TRIGGER_MODE__SHIFT 0x10
+-#define DSI0_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DENG_TRIGGER_SEL__SHIFT 0x14
+-#define DSI0_DISP_DSI_TRIG_CTRL__HW_SOURCE_SEL__SHIFT 0x18
+-#define DSI0_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_DENG_ORDER__SHIFT 0x1c
+-#define DSI0_DISP_DSI_TRIG_CTRL__TE_SEL__SHIFT 0x1f
+-#define DSI0_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_TRIGGER_MODE_MASK 0x00000001L
+-#define DSI0_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_TRIGGER_SEL_MASK 0x00000030L
+-#define DSI0_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DENG_TRIGGER_MODE_MASK 0x00010000L
+-#define DSI0_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DENG_TRIGGER_SEL_MASK 0x00300000L
+-#define DSI0_DISP_DSI_TRIG_CTRL__HW_SOURCE_SEL_MASK 0x0F000000L
+-#define DSI0_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_DENG_ORDER_MASK 0x10000000L
+-#define DSI0_DISP_DSI_TRIG_CTRL__TE_SEL_MASK 0x80000000L
+-//DSI0_DISP_DSI_EXT_MUX
+-#define DSI0_DISP_DSI_EXT_MUX__EXT_TE_MUX__SHIFT 0x0
+-#define DSI0_DISP_DSI_EXT_MUX__EXT_TE_MODE__SHIFT 0x4
+-#define DSI0_DISP_DSI_EXT_MUX__EXT_RESET_POL__SHIFT 0x6
+-#define DSI0_DISP_DSI_EXT_MUX__EXT_TE_POL__SHIFT 0x7
+-#define DSI0_DISP_DSI_EXT_MUX__EXT_TE_HSYNC_TRIG_CNT__SHIFT 0x8
+-#define DSI0_DISP_DSI_EXT_MUX__EXT_TE_HSYNC_TOTAL__SHIFT 0x14
+-#define DSI0_DISP_DSI_EXT_MUX__EXT_TE_MUX_MASK 0x0000000FL
+-#define DSI0_DISP_DSI_EXT_MUX__EXT_TE_MODE_MASK 0x00000030L
+-#define DSI0_DISP_DSI_EXT_MUX__EXT_RESET_POL_MASK 0x00000040L
+-#define DSI0_DISP_DSI_EXT_MUX__EXT_TE_POL_MASK 0x00000080L
+-#define DSI0_DISP_DSI_EXT_MUX__EXT_TE_HSYNC_TRIG_CNT_MASK 0x000FFF00L
+-#define DSI0_DISP_DSI_EXT_MUX__EXT_TE_HSYNC_TOTAL_MASK 0xFFF00000L
+-//DSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL
+-#define DSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL__TE_HSYNC_MAX_WIDTH__SHIFT 0x0
+-#define DSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL__TE_VSYNC_MIN_WIDTH__SHIFT 0x10
+-#define DSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL__TE_HSYNC_MAX_WIDTH_MASK 0x0000FFFFL
+-#define DSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL__TE_VSYNC_MIN_WIDTH_MASK 0xFFFF0000L
+-//DSI0_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER
+-#define DSI0_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER__SW_TRIGGER__SHIFT 0x0
+-#define DSI0_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER__SW_TRIGGER_MASK 0x00000001L
+-//DSI0_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER
+-#define DSI0_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER__SW_TRIGGER__SHIFT 0x0
+-#define DSI0_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER__SW_TRIGGER_MASK 0x00000001L
+-//DSI0_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER
+-#define DSI0_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER__SW_TRIGGER__SHIFT 0x0
+-#define DSI0_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER__SW_TRIGGER_MASK 0x00000001L
+-//DSI0_DISP_DSI_RESET_SW_TRIGGER
+-#define DSI0_DISP_DSI_RESET_SW_TRIGGER__SW_TRIGGER__SHIFT 0x0
+-#define DSI0_DISP_DSI_RESET_SW_TRIGGER__SW_TRIGGER_MASK 0x00000001L
+-//DSI0_DISP_DSI_EXT_RESET
+-#define DSI0_DISP_DSI_EXT_RESET__RESET_PANEL__SHIFT 0x0
+-#define DSI0_DISP_DSI_EXT_RESET__RESET_PANEL_MASK 0x00000001L
+-//DSI0_DISP_DSI_LANE_CRC_HS_MODE
+-#define DSI0_DISP_DSI_LANE_CRC_HS_MODE__DLN0_HS_CRC__SHIFT 0x0
+-#define DSI0_DISP_DSI_LANE_CRC_HS_MODE__DLN1_HS_CRC__SHIFT 0x8
+-#define DSI0_DISP_DSI_LANE_CRC_HS_MODE__DLN2_HS_CRC__SHIFT 0x10
+-#define DSI0_DISP_DSI_LANE_CRC_HS_MODE__DLN3_HS_CRC__SHIFT 0x18
+-#define DSI0_DISP_DSI_LANE_CRC_HS_MODE__DLN0_HS_CRC_MASK 0x000000FFL
+-#define DSI0_DISP_DSI_LANE_CRC_HS_MODE__DLN1_HS_CRC_MASK 0x0000FF00L
+-#define DSI0_DISP_DSI_LANE_CRC_HS_MODE__DLN2_HS_CRC_MASK 0x00FF0000L
+-#define DSI0_DISP_DSI_LANE_CRC_HS_MODE__DLN3_HS_CRC_MASK 0xFF000000L
+-//DSI0_DISP_DSI_LANE_CRC_LP_MODE
+-#define DSI0_DISP_DSI_LANE_CRC_LP_MODE__DLN0_LP_CRC__SHIFT 0x0
+-#define DSI0_DISP_DSI_LANE_CRC_LP_MODE__DLN0_LP_CRC_MASK 0x000000FFL
+-//DSI0_DISP_DSI_LANE_CRC_CTRL
+-#define DSI0_DISP_DSI_LANE_CRC_CTRL__CRC_MAX_HS_DONE_COUNT__SHIFT 0x0
+-#define DSI0_DISP_DSI_LANE_CRC_CTRL__CRC_MAX_LP_DONE_COUNT__SHIFT 0x8
+-#define DSI0_DISP_DSI_LANE_CRC_CTRL__CRC_ENABLE__SHIFT 0x10
+-#define DSI0_DISP_DSI_LANE_CRC_CTRL__CRC_DONE_HS__SHIFT 0x14
+-#define DSI0_DISP_DSI_LANE_CRC_CTRL__CRC_DONE_LP__SHIFT 0x18
+-#define DSI0_DISP_DSI_LANE_CRC_CTRL__CRC_MAX_HS_DONE_COUNT_MASK 0x000000FFL
+-#define DSI0_DISP_DSI_LANE_CRC_CTRL__CRC_MAX_LP_DONE_COUNT_MASK 0x0000FF00L
+-#define DSI0_DISP_DSI_LANE_CRC_CTRL__CRC_ENABLE_MASK 0x00010000L
+-#define DSI0_DISP_DSI_LANE_CRC_CTRL__CRC_DONE_HS_MASK 0x00100000L
+-#define DSI0_DISP_DSI_LANE_CRC_CTRL__CRC_DONE_LP_MASK 0x01000000L
+-//DSI0_DISP_DSI_PIXEL_CRC_CTRL
+-#define DSI0_DISP_DSI_PIXEL_CRC_CTRL__CRC_MAX_PIXEL_COUNT__SHIFT 0x0
+-#define DSI0_DISP_DSI_PIXEL_CRC_CTRL__PIXEL_CRC__SHIFT 0x8
+-#define DSI0_DISP_DSI_PIXEL_CRC_CTRL__CRC_DONE_PIXEL__SHIFT 0x10
+-#define DSI0_DISP_DSI_PIXEL_CRC_CTRL__CRC_MAX_PIXEL_COUNT_MASK 0x000000FFL
+-#define DSI0_DISP_DSI_PIXEL_CRC_CTRL__PIXEL_CRC_MASK 0x0000FF00L
+-#define DSI0_DISP_DSI_PIXEL_CRC_CTRL__CRC_DONE_PIXEL_MASK 0x00010000L
+-//DSI0_DISP_DSI_LANE_CTRL
+-#define DSI0_DISP_DSI_LANE_CTRL__DLN0_ULPS_REQUEST__SHIFT 0x0
+-#define DSI0_DISP_DSI_LANE_CTRL__DLN1_ULPS_REQUEST__SHIFT 0x1
+-#define DSI0_DISP_DSI_LANE_CTRL__DLN2_ULPS_REQUEST__SHIFT 0x2
+-#define DSI0_DISP_DSI_LANE_CTRL__DLN3_ULPS_REQUEST__SHIFT 0x3
+-#define DSI0_DISP_DSI_LANE_CTRL__DLN0_ULPS_EXIT__SHIFT 0x4
+-#define DSI0_DISP_DSI_LANE_CTRL__DLN1_ULPS_EXIT__SHIFT 0x5
+-#define DSI0_DISP_DSI_LANE_CTRL__DLN2_ULPS_EXIT__SHIFT 0x6
+-#define DSI0_DISP_DSI_LANE_CTRL__DLN3_ULPS_EXIT__SHIFT 0x7
+-#define DSI0_DISP_DSI_LANE_CTRL__DLN0_FORCE_TX_STOP__SHIFT 0x8
+-#define DSI0_DISP_DSI_LANE_CTRL__DLN1_FORCE_TX_STOP__SHIFT 0x9
+-#define DSI0_DISP_DSI_LANE_CTRL__DLN2_FORCE_TX_STOP__SHIFT 0xa
+-#define DSI0_DISP_DSI_LANE_CTRL__DLN3_FORCE_TX_STOP__SHIFT 0xb
+-#define DSI0_DISP_DSI_LANE_CTRL__CLKLN_ULPS_REQUEST__SHIFT 0xc
+-#define DSI0_DISP_DSI_LANE_CTRL__CLKLN_ULPS_EXIT__SHIFT 0x10
+-#define DSI0_DISP_DSI_LANE_CTRL__CLKLN_FORCE_TX_STOP__SHIFT 0x14
+-#define DSI0_DISP_DSI_LANE_CTRL__CLKLN_HS_FORCE_REQUEST__SHIFT 0x18
+-#define DSI0_DISP_DSI_LANE_CTRL__DLN0_ULPS_REQUEST_MASK 0x00000001L
+-#define DSI0_DISP_DSI_LANE_CTRL__DLN1_ULPS_REQUEST_MASK 0x00000002L
+-#define DSI0_DISP_DSI_LANE_CTRL__DLN2_ULPS_REQUEST_MASK 0x00000004L
+-#define DSI0_DISP_DSI_LANE_CTRL__DLN3_ULPS_REQUEST_MASK 0x00000008L
+-#define DSI0_DISP_DSI_LANE_CTRL__DLN0_ULPS_EXIT_MASK 0x00000010L
+-#define DSI0_DISP_DSI_LANE_CTRL__DLN1_ULPS_EXIT_MASK 0x00000020L
+-#define DSI0_DISP_DSI_LANE_CTRL__DLN2_ULPS_EXIT_MASK 0x00000040L
+-#define DSI0_DISP_DSI_LANE_CTRL__DLN3_ULPS_EXIT_MASK 0x00000080L
+-#define DSI0_DISP_DSI_LANE_CTRL__DLN0_FORCE_TX_STOP_MASK 0x00000100L
+-#define DSI0_DISP_DSI_LANE_CTRL__DLN1_FORCE_TX_STOP_MASK 0x00000200L
+-#define DSI0_DISP_DSI_LANE_CTRL__DLN2_FORCE_TX_STOP_MASK 0x00000400L
+-#define DSI0_DISP_DSI_LANE_CTRL__DLN3_FORCE_TX_STOP_MASK 0x00000800L
+-#define DSI0_DISP_DSI_LANE_CTRL__CLKLN_ULPS_REQUEST_MASK 0x00001000L
+-#define DSI0_DISP_DSI_LANE_CTRL__CLKLN_ULPS_EXIT_MASK 0x00010000L
+-#define DSI0_DISP_DSI_LANE_CTRL__CLKLN_FORCE_TX_STOP_MASK 0x00100000L
+-#define DSI0_DISP_DSI_LANE_CTRL__CLKLN_HS_FORCE_REQUEST_MASK 0x01000000L
+-//DSI0_DISP_DSI_DLN0_PHY_ERROR
+-#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC__SHIFT 0x0
+-#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC_CLR__SHIFT 0x0
+-#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC_MASK__SHIFT 0x3
+-#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC__SHIFT 0x4
+-#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC_CLR__SHIFT 0x4
+-#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC_MASK__SHIFT 0x7
+-#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL__SHIFT 0x8
+-#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL_CLR__SHIFT 0x8
+-#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL_MASK__SHIFT 0xb
+-#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0__SHIFT 0xc
+-#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0_CLR__SHIFT 0xc
+-#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0_MASK__SHIFT 0xf
+-#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1__SHIFT 0x10
+-#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1_CLR__SHIFT 0x10
+-#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1_MASK__SHIFT 0x13
+-#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC_MASK 0x00000001L
+-#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC_CLR_MASK 0x00000001L
+-#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC_MASK_MASK 0x00000008L
+-#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC_MASK 0x00000010L
+-#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC_CLR_MASK 0x00000010L
+-#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC_MASK_MASK 0x00000080L
+-#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL_MASK 0x00000100L
+-#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL_CLR_MASK 0x00000100L
+-#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL_MASK_MASK 0x00000800L
+-#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0_MASK 0x00001000L
+-#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0_CLR_MASK 0x00001000L
+-#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0_MASK_MASK 0x00008000L
+-#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1_MASK 0x00010000L
+-#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1_CLR_MASK 0x00010000L
+-#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1_MASK_MASK 0x00080000L
+-//DSI0_DISP_DSI_LP_TIMER_CTRL
+-#define DSI0_DISP_DSI_LP_TIMER_CTRL__LP_RX_TO__SHIFT 0x0
+-#define DSI0_DISP_DSI_LP_TIMER_CTRL__BTA_TO__SHIFT 0x10
+-#define DSI0_DISP_DSI_LP_TIMER_CTRL__LP_RX_TO_MASK 0x0000FFFFL
+-#define DSI0_DISP_DSI_LP_TIMER_CTRL__BTA_TO_MASK 0xFFFF0000L
+-//DSI0_DISP_DSI_HS_TIMER_CTRL
+-#define DSI0_DISP_DSI_HS_TIMER_CTRL__HS_TX_TO__SHIFT 0x0
+-#define DSI0_DISP_DSI_HS_TIMER_CTRL__HS_TX_TO_MASK 0x0000FFFFL
+-//DSI0_DISP_DSI_TIMEOUT_STATUS
+-#define DSI0_DISP_DSI_TIMEOUT_STATUS__HS_TX_TIMEOUT__SHIFT 0x0
+-#define DSI0_DISP_DSI_TIMEOUT_STATUS__HS_TX_TIMEOUT_CLR__SHIFT 0x0
+-#define DSI0_DISP_DSI_TIMEOUT_STATUS__LP_RX_TIMEOUT__SHIFT 0x4
+-#define DSI0_DISP_DSI_TIMEOUT_STATUS__LP_RX_TIMEOUT_CLR__SHIFT 0x4
+-#define DSI0_DISP_DSI_TIMEOUT_STATUS__BTA_TIMEOUT__SHIFT 0x8
+-#define DSI0_DISP_DSI_TIMEOUT_STATUS__BTA_TIMEOUT_CLR__SHIFT 0x8
+-#define DSI0_DISP_DSI_TIMEOUT_STATUS__HS_TX_TIMEOUT_MASK 0x00000001L
+-#define DSI0_DISP_DSI_TIMEOUT_STATUS__HS_TX_TIMEOUT_CLR_MASK 0x00000001L
+-#define DSI0_DISP_DSI_TIMEOUT_STATUS__LP_RX_TIMEOUT_MASK 0x00000010L
+-#define DSI0_DISP_DSI_TIMEOUT_STATUS__LP_RX_TIMEOUT_CLR_MASK 0x00000010L
+-#define DSI0_DISP_DSI_TIMEOUT_STATUS__BTA_TIMEOUT_MASK 0x00000100L
+-#define DSI0_DISP_DSI_TIMEOUT_STATUS__BTA_TIMEOUT_CLR_MASK 0x00000100L
+-//DSI0_DISP_DSI_PHY_CLK_TIMING_CTRL
+-#define DSI0_DISP_DSI_PHY_CLK_TIMING_CTRL__T_CLK_PRE__SHIFT 0x0
+-#define DSI0_DISP_DSI_PHY_CLK_TIMING_CTRL__T_CLK_POST__SHIFT 0x8
+-#define DSI0_DISP_DSI_PHY_CLK_TIMING_CTRL__T_CLK_PRE_MASK 0x000000FFL
+-#define DSI0_DISP_DSI_PHY_CLK_TIMING_CTRL__T_CLK_POST_MASK 0x00003F00L
+-//DSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2
+-#define DSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2__T_PRE_TRIGGER__SHIFT 0x0
+-#define DSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2__T_INTER_STOP__SHIFT 0x10
+-#define DSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2__T_PRE_TRIGGER_MASK 0x000007FFL
+-#define DSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2__T_INTER_STOP_MASK 0xFFFF0000L
+-//DSI0_DISP_DSI_EOT_PACKET
+-#define DSI0_DISP_DSI_EOT_PACKET__DI__SHIFT 0x0
+-#define DSI0_DISP_DSI_EOT_PACKET__WC__SHIFT 0x8
+-#define DSI0_DISP_DSI_EOT_PACKET__ECC__SHIFT 0x18
+-#define DSI0_DISP_DSI_EOT_PACKET__DI_MASK 0x000000FFL
+-#define DSI0_DISP_DSI_EOT_PACKET__WC_MASK 0x00FFFF00L
+-#define DSI0_DISP_DSI_EOT_PACKET__ECC_MASK 0xFF000000L
+-//DSI0_DISP_DSI_EOT_PACKET_CTRL
+-#define DSI0_DISP_DSI_EOT_PACKET_CTRL__TX_EOT_APPEND__SHIFT 0x0
+-#define DSI0_DISP_DSI_EOT_PACKET_CTRL__RX_EOT_IGNORE__SHIFT 0x4
+-#define DSI0_DISP_DSI_EOT_PACKET_CTRL__TX_EOT_APPEND_MASK 0x00000001L
+-#define DSI0_DISP_DSI_EOT_PACKET_CTRL__RX_EOT_IGNORE_MASK 0x00000010L
+-//DSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER
+-#define DSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER__SW_TRIGGER__SHIFT 0x0
+-#define DSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER__ENTRY_COMMAND__SHIFT 0x10
+-#define DSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER__SW_TRIGGER_MASK 0x00000001L
+-#define DSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER__ENTRY_COMMAND_MASK 0x00FF0000L
+-//DSI0_DISP_DSI_MIPI_BIST_CTRL
+-#define DSI0_DISP_DSI_MIPI_BIST_CTRL__MIPI_BIST_RESET__SHIFT 0x0
+-#define DSI0_DISP_DSI_MIPI_BIST_CTRL__MIPI_BIST_EN__SHIFT 0x1
+-#define DSI0_DISP_DSI_MIPI_BIST_CTRL__MIPI_BIST_RESET_MASK 0x00000001L
+-#define DSI0_DISP_DSI_MIPI_BIST_CTRL__MIPI_BIST_EN_MASK 0x00000002L
+-//DSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE
+-#define DSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE__MIPI_H_SIZE__SHIFT 0x0
+-#define DSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE__MIPI_V_SIZE__SHIFT 0x10
+-#define DSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE__MIPI_H_SIZE_MASK 0x0000FFFFL
+-#define DSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE__MIPI_V_SIZE_MASK 0xFFFF0000L
+-//DSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE
+-#define DSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE__MIPI_H_SIZE__SHIFT 0x0
+-#define DSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE__MIPI_V_SIZE__SHIFT 0x8
+-#define DSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE__MIPI_H_SIZE_MASK 0x000000FFL
+-#define DSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE__MIPI_V_SIZE_MASK 0x0000FF00L
+-//DSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG
+-#define DSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_BLANKING_CYCLES__SHIFT 0x0
+-#define DSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_FRAME_REPEAT__SHIFT 0x10
+-#define DSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_BIST_VIDEO_FRMT__SHIFT 0x18
+-#define DSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_BLANKING_CYCLES_MASK 0x0000FFFFL
+-#define DSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_FRAME_REPEAT_MASK 0x00FF0000L
+-#define DSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_BIST_VIDEO_FRMT_MASK 0x01000000L
+-//DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL
+-#define DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_Y_LSFR_POLYNOMIAL__SHIFT 0x0
+-#define DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_U_LSFR_POLYNOMIAL__SHIFT 0x8
+-#define DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_V_LSFR_POLYNOMIAL__SHIFT 0x10
+-#define DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_Y_LSFR_EN__SHIFT 0x18
+-#define DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_U_LSFR_EN__SHIFT 0x19
+-#define DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_V_LSFR_EN__SHIFT 0x1a
+-#define DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_Y_LSFR_POLYNOMIAL_MASK 0x000000FFL
+-#define DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_U_LSFR_POLYNOMIAL_MASK 0x0000FF00L
+-#define DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_V_LSFR_POLYNOMIAL_MASK 0x00FF0000L
+-#define DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_Y_LSFR_EN_MASK 0x01000000L
+-#define DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_U_LSFR_EN_MASK 0x02000000L
+-#define DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_V_LSFR_EN_MASK 0x04000000L
+-//DSI0_DISP_DSI_MIPI_BIST_LSFR_INIT
+-#define DSI0_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_Y_INIT_LSFR_VAL__SHIFT 0x0
+-#define DSI0_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_U_INIT_LSFR_VAL__SHIFT 0x8
+-#define DSI0_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_V_INIT_LSFR_VAL__SHIFT 0x10
+-#define DSI0_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_Y_INIT_LSFR_VAL_MASK 0x000000FFL
+-#define DSI0_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_U_INIT_LSFR_VAL_MASK 0x0000FF00L
+-#define DSI0_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_V_INIT_LSFR_VAL_MASK 0x00FF0000L
+-//DSI0_DISP_DSI_MIPI_BIST_START
+-#define DSI0_DISP_DSI_MIPI_BIST_START__MIPI_BIST_START__SHIFT 0x0
+-#define DSI0_DISP_DSI_MIPI_BIST_START__MIPI_BIST_START_MASK 0x00000001L
+-//DSI0_DISP_DSI_MIPI_BIST_STATUS
+-#define DSI0_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_STATUS_BUSY__SHIFT 0x0
+-#define DSI0_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_DONE__SHIFT 0x4
+-#define DSI0_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_DONE_CLR__SHIFT 0x4
+-#define DSI0_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_STATUS_BUSY_MASK 0x00000001L
+-#define DSI0_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_DONE_MASK 0x00000010L
+-#define DSI0_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_DONE_CLR_MASK 0x00000010L
+-//DSI0_DISP_DSI_ERROR_INTERRUPT_MASK
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_ECC_ERR_MASK__SHIFT 0x0
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_MULTI_ECC_ERR_MASK__SHIFT 0x1
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_CRC_ERR_MASK__SHIFT 0x2
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_INCOMPLETE_PACKET_ERR_MASK__SHIFT 0x3
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__ERROR_PACKET_MASK__SHIFT 0x4
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__INTERLEAVE_PACKET_BLOCK_MASK__SHIFT 0x5
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__TE_ABORT_MASK__SHIFT 0x6
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_ESC_MASK__SHIFT 0x8
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_SYNC_ESC_MASK__SHIFT 0x9
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTROL_MASK__SHIFT 0xa
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTENTION_LP0_MASK__SHIFT 0xc
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTENTION_LP1_MASK__SHIFT 0xd
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__LP_RX_TO_MASK__SHIFT 0x10
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__HS_TX_TO_MASK__SHIFT 0x11
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__BTA_TO_MASK__SHIFT 0x12
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DMAFIFO_UNDERFLOW_MASK__SHIFT 0x14
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__CMDFIFO_UNDERFLOW_MASK__SHIFT 0x15
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DENGFIFO_OVERFLOW_UNDERFLOW_MASK__SHIFT 0x18
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_HS_FIFO_OVERFLOW_MASK__SHIFT 0x1a
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN1_HS_FIFO_OVERFLOW_MASK__SHIFT 0x1b
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN2_HS_FIFO_OVERFLOW_MASK__SHIFT 0x1c
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN3_HS_FIFO_OVERFLOW_MASK__SHIFT 0x1d
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_LP_FIFO_OVERFLOW_MASK__SHIFT 0x1e
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__INTERLEAVE_OP_CONTENTION_MASK__SHIFT 0x1f
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_ECC_ERR_MASK_MASK 0x00000001L
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_MULTI_ECC_ERR_MASK_MASK 0x00000002L
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_CRC_ERR_MASK_MASK 0x00000004L
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_INCOMPLETE_PACKET_ERR_MASK_MASK 0x00000008L
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__ERROR_PACKET_MASK_MASK 0x00000010L
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__INTERLEAVE_PACKET_BLOCK_MASK_MASK 0x00000020L
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__TE_ABORT_MASK_MASK 0x00000040L
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_ESC_MASK_MASK 0x00000100L
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_SYNC_ESC_MASK_MASK 0x00000200L
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTROL_MASK_MASK 0x00000400L
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTENTION_LP0_MASK_MASK 0x00001000L
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTENTION_LP1_MASK_MASK 0x00002000L
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__LP_RX_TO_MASK_MASK 0x00010000L
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__HS_TX_TO_MASK_MASK 0x00020000L
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__BTA_TO_MASK_MASK 0x00040000L
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DMAFIFO_UNDERFLOW_MASK_MASK 0x00100000L
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__CMDFIFO_UNDERFLOW_MASK_MASK 0x00200000L
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DENGFIFO_OVERFLOW_UNDERFLOW_MASK_MASK 0x01000000L
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_HS_FIFO_OVERFLOW_MASK_MASK 0x04000000L
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN1_HS_FIFO_OVERFLOW_MASK_MASK 0x08000000L
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN2_HS_FIFO_OVERFLOW_MASK_MASK 0x10000000L
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN3_HS_FIFO_OVERFLOW_MASK_MASK 0x20000000L
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_LP_FIFO_OVERFLOW_MASK_MASK 0x40000000L
+-#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__INTERLEAVE_OP_CONTENTION_MASK_MASK 0x80000000L
+-//DSI0_DISP_DSI_INTERRUPT_CTRL
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_STAT__SHIFT 0x0
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_AK__SHIFT 0x0
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_MASK__SHIFT 0x1
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_STAT__SHIFT 0x4
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_AK__SHIFT 0x4
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_MASK__SHIFT 0x5
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_STAT__SHIFT 0x8
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_AK__SHIFT 0x8
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_MASK__SHIFT 0x9
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_STAT__SHIFT 0xc
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_AK__SHIFT 0xc
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_MASK__SHIFT 0xd
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_STAT__SHIFT 0x10
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_AK__SHIFT 0x10
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_MASK__SHIFT 0x11
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_STAT__SHIFT 0x14
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_AK__SHIFT 0x14
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_MASK__SHIFT 0x15
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_STAT__SHIFT 0x18
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_AK__SHIFT 0x18
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_MASK__SHIFT 0x19
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_STAT_MASK 0x00000001L
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_AK_MASK 0x00000001L
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_MASK_MASK 0x00000002L
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_STAT_MASK 0x00000010L
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_AK_MASK 0x00000010L
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_MASK_MASK 0x00000020L
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_STAT_MASK 0x00000100L
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_AK_MASK 0x00000100L
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_MASK_MASK 0x00000200L
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_STAT_MASK 0x00001000L
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_AK_MASK 0x00001000L
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_MASK_MASK 0x00002000L
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_STAT_MASK 0x00010000L
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_AK_MASK 0x00010000L
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_MASK_MASK 0x00020000L
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_STAT_MASK 0x00100000L
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_AK_MASK 0x00100000L
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_MASK_MASK 0x00200000L
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_STAT_MASK 0x01000000L
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_AK_MASK 0x01000000L
+-#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_MASK_MASK 0x02000000L
+-//DSI0_DISP_DSI_CLK_CTRL
+-#define DSI0_DISP_DSI_CLK_CTRL__DISPCLK_G_ON__SHIFT 0x0
+-#define DSI0_DISP_DSI_CLK_CTRL__DISPCLK_R_ON__SHIFT 0x1
+-#define DSI0_DISP_DSI_CLK_CTRL__DSICLK_G_ON__SHIFT 0x4
+-#define DSI0_DISP_DSI_CLK_CTRL__DSICLK_R_ON__SHIFT 0x5
+-#define DSI0_DISP_DSI_CLK_CTRL__DSICLK_TRN_ON__SHIFT 0x6
+-#define DSI0_DISP_DSI_CLK_CTRL__BYTECLK_G_ON__SHIFT 0x8
+-#define DSI0_DISP_DSI_CLK_CTRL__ESCCLK_G_ON__SHIFT 0x10
+-#define DSI0_DISP_DSI_CLK_CTRL__TEST_CLK_SEL__SHIFT 0x18
+-#define DSI0_DISP_DSI_CLK_CTRL__DISPCLK_G_ON_MASK 0x00000001L
+-#define DSI0_DISP_DSI_CLK_CTRL__DISPCLK_R_ON_MASK 0x00000002L
+-#define DSI0_DISP_DSI_CLK_CTRL__DSICLK_G_ON_MASK 0x00000010L
+-#define DSI0_DISP_DSI_CLK_CTRL__DSICLK_R_ON_MASK 0x00000020L
+-#define DSI0_DISP_DSI_CLK_CTRL__DSICLK_TRN_ON_MASK 0x00000040L
+-#define DSI0_DISP_DSI_CLK_CTRL__BYTECLK_G_ON_MASK 0x00000100L
+-#define DSI0_DISP_DSI_CLK_CTRL__ESCCLK_G_ON_MASK 0x00010000L
+-#define DSI0_DISP_DSI_CLK_CTRL__TEST_CLK_SEL_MASK 0x0F000000L
+-//DSI0_DISP_DSI_CLK_STATUS
+-#define DSI0_DISP_DSI_CLK_STATUS__DISPCLK_R_ACTIVE__SHIFT 0x0
+-#define DSI0_DISP_DSI_CLK_STATUS__DISPCLK_G_ACTIVE__SHIFT 0x1
+-#define DSI0_DISP_DSI_CLK_STATUS__DSICLK_R_ACTIVE__SHIFT 0x4
+-#define DSI0_DISP_DSI_CLK_STATUS__DSICLK_G_ACTIVE__SHIFT 0x5
+-#define DSI0_DISP_DSI_CLK_STATUS__DSICLK_TRN_ACTIVE__SHIFT 0x6
+-#define DSI0_DISP_DSI_CLK_STATUS__BYTECLK_G_ACTIVE__SHIFT 0x8
+-#define DSI0_DISP_DSI_CLK_STATUS__ESCCLK_G_ACTIVE__SHIFT 0x10
+-#define DSI0_DISP_DSI_CLK_STATUS__DISPCLK_R_ACTIVE_MASK 0x00000001L
+-#define DSI0_DISP_DSI_CLK_STATUS__DISPCLK_G_ACTIVE_MASK 0x00000002L
+-#define DSI0_DISP_DSI_CLK_STATUS__DSICLK_R_ACTIVE_MASK 0x00000010L
+-#define DSI0_DISP_DSI_CLK_STATUS__DSICLK_G_ACTIVE_MASK 0x00000020L
+-#define DSI0_DISP_DSI_CLK_STATUS__DSICLK_TRN_ACTIVE_MASK 0x00000040L
+-#define DSI0_DISP_DSI_CLK_STATUS__BYTECLK_G_ACTIVE_MASK 0x00000100L
+-#define DSI0_DISP_DSI_CLK_STATUS__ESCCLK_G_ACTIVE_MASK 0x00010000L
+-//DSI0_DISP_DSI_DENG_FIFO_STATUS
+-#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_LEVEL_ERROR__SHIFT 0x0
+-#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
+-#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
+-#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_ERROR_ACK__SHIFT 0x9
+-#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
+-#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_MAXIMUM_LEVEL__SHIFT 0x11
+-#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_MINIMUM_LEVEL__SHIFT 0x17
+-#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_CALIBRATED__SHIFT 0x1d
+-#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
+-#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
+-#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_LEVEL_ERROR_MASK 0x00000001L
+-#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L
+-#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_OVERWRITE_LEVEL_MASK 0x000001FCL
+-#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_ERROR_ACK_MASK 0x00000200L
+-#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0001FC00L
+-#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_MAXIMUM_LEVEL_MASK 0x007E0000L
+-#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_MINIMUM_LEVEL_MASK 0x0F800000L
+-#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_CALIBRATED_MASK 0x20000000L
+-#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L
+-#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L
+-//DSI0_DISP_DSI_DENG_FIFO_CTRL
+-#define DSI0_DISP_DSI_DENG_FIFO_CTRL__DENG_FIFO_EN__SHIFT 0x0
+-#define DSI0_DISP_DSI_DENG_FIFO_CTRL__DENG_FIFO_START__SHIFT 0x4
+-#define DSI0_DISP_DSI_DENG_FIFO_CTRL__DENG_DSICLK_ON__SHIFT 0x8
+-#define DSI0_DISP_DSI_DENG_FIFO_CTRL__DENG_FIFO_EN_MASK 0x00000001L
+-#define DSI0_DISP_DSI_DENG_FIFO_CTRL__DENG_FIFO_START_MASK 0x00000010L
+-#define DSI0_DISP_DSI_DENG_FIFO_CTRL__DENG_DSICLK_ON_MASK 0x00000100L
+-//DSI0_DISP_DSI_CMD_FIFO_DATA
+-#define DSI0_DISP_DSI_CMD_FIFO_DATA__CMDFIFO_DATA__SHIFT 0x0
+-#define DSI0_DISP_DSI_CMD_FIFO_DATA__CMDFIFO_DATA_MASK 0xFFFFFFFFL
+-//DSI0_DISP_DSI_CMD_FIFO_CTRL
+-#define DSI0_DISP_DSI_CMD_FIFO_CTRL__USE_CMDFIFO__SHIFT 0x0
+-#define DSI0_DISP_DSI_CMD_FIFO_CTRL__CMDFIFO_DW_LEVEL__SHIFT 0x4
+-#define DSI0_DISP_DSI_CMD_FIFO_CTRL__USE_CMDFIFO_MASK 0x00000001L
+-#define DSI0_DISP_DSI_CMD_FIFO_CTRL__CMDFIFO_DW_LEVEL_MASK 0x000007F0L
+-//DSI0_DISP_DSI_TE_CTRL
+-#define DSI0_DISP_DSI_TE_CTRL__FREEZE_CRTC_HYSTERESIS__SHIFT 0x0
+-#define DSI0_DISP_DSI_TE_CTRL__DISABLE_CRTC_FREEZE__SHIFT 0x10
+-#define DSI0_DISP_DSI_TE_CTRL__DISABLE_CRTC_FORCE__SHIFT 0x14
+-#define DSI0_DISP_DSI_TE_CTRL__CRTC_FREEZE__SHIFT 0x18
+-#define DSI0_DISP_DSI_TE_CTRL__CRTC_FREEZE_TRIG__SHIFT 0x18
+-#define DSI0_DISP_DSI_TE_CTRL__FREEZE_CRTC_HYSTERESIS_MASK 0x00000FFFL
+-#define DSI0_DISP_DSI_TE_CTRL__DISABLE_CRTC_FREEZE_MASK 0x00010000L
+-#define DSI0_DISP_DSI_TE_CTRL__DISABLE_CRTC_FORCE_MASK 0x00100000L
+-#define DSI0_DISP_DSI_TE_CTRL__CRTC_FREEZE_MASK 0x01000000L
+-#define DSI0_DISP_DSI_TE_CTRL__CRTC_FREEZE_TRIG_MASK 0x01000000L
+-//DSI0_DISP_DSI_LANE_STATUS
+-#define DSI0_DISP_DSI_LANE_STATUS__DLN0_STOPSTATE__SHIFT 0x0
+-#define DSI0_DISP_DSI_LANE_STATUS__DLN1_STOPSTATE__SHIFT 0x1
+-#define DSI0_DISP_DSI_LANE_STATUS__DLN2_STOPSTATE__SHIFT 0x2
+-#define DSI0_DISP_DSI_LANE_STATUS__DLN3_STOPSTATE__SHIFT 0x3
+-#define DSI0_DISP_DSI_LANE_STATUS__DLN0_ULPS_ACTIVE_NOT__SHIFT 0x4
+-#define DSI0_DISP_DSI_LANE_STATUS__DLN1_ULPS_ACTIVE_NOT__SHIFT 0x5
+-#define DSI0_DISP_DSI_LANE_STATUS__DLN2_ULPS_ACTIVE_NOT__SHIFT 0x6
+-#define DSI0_DISP_DSI_LANE_STATUS__DLN3_ULPS_ACTIVE_NOT__SHIFT 0x7
+-#define DSI0_DISP_DSI_LANE_STATUS__DLN0_DIRECTION__SHIFT 0x8
+-#define DSI0_DISP_DSI_LANE_STATUS__CLKLN_STOPSTATE__SHIFT 0x18
+-#define DSI0_DISP_DSI_LANE_STATUS__CLKLN_ULPS_ACTIVE_NOT__SHIFT 0x1c
+-#define DSI0_DISP_DSI_LANE_STATUS__DLN0_STOPSTATE_MASK 0x00000001L
+-#define DSI0_DISP_DSI_LANE_STATUS__DLN1_STOPSTATE_MASK 0x00000002L
+-#define DSI0_DISP_DSI_LANE_STATUS__DLN2_STOPSTATE_MASK 0x00000004L
+-#define DSI0_DISP_DSI_LANE_STATUS__DLN3_STOPSTATE_MASK 0x00000008L
+-#define DSI0_DISP_DSI_LANE_STATUS__DLN0_ULPS_ACTIVE_NOT_MASK 0x00000010L
+-#define DSI0_DISP_DSI_LANE_STATUS__DLN1_ULPS_ACTIVE_NOT_MASK 0x00000020L
+-#define DSI0_DISP_DSI_LANE_STATUS__DLN2_ULPS_ACTIVE_NOT_MASK 0x00000040L
+-#define DSI0_DISP_DSI_LANE_STATUS__DLN3_ULPS_ACTIVE_NOT_MASK 0x00000080L
+-#define DSI0_DISP_DSI_LANE_STATUS__DLN0_DIRECTION_MASK 0x00000100L
+-#define DSI0_DISP_DSI_LANE_STATUS__CLKLN_STOPSTATE_MASK 0x01000000L
+-#define DSI0_DISP_DSI_LANE_STATUS__CLKLN_ULPS_ACTIVE_NOT_MASK 0x10000000L
+-//DSI0_DISP_DSI_PERF_CTRL
+-#define DSI0_DISP_DSI_PERF_CTRL__PERF_LP_HS_LATENCY_SEL__SHIFT 0x0
+-#define DSI0_DISP_DSI_PERF_CTRL__PERF_HS_LP_LATENCY_SEL__SHIFT 0x4
+-#define DSI0_DISP_DSI_PERF_CTRL__PERF_LP_HS_LATENCY_SEL_MASK 0x00000003L
+-#define DSI0_DISP_DSI_PERF_CTRL__PERF_HS_LP_LATENCY_SEL_MASK 0x00000030L
+-//DSI0_DISP_DSI_HSYNC_LENGTH
+-#define DSI0_DISP_DSI_HSYNC_LENGTH__HSYNC_LENGTH_MAX__SHIFT 0x0
+-#define DSI0_DISP_DSI_HSYNC_LENGTH__HSYNC_LENGTH_MIN__SHIFT 0x10
+-#define DSI0_DISP_DSI_HSYNC_LENGTH__HSYNC_LENGTH_MAX_MASK 0x0000FFFFL
+-#define DSI0_DISP_DSI_HSYNC_LENGTH__HSYNC_LENGTH_MIN_MASK 0xFFFF0000L
+-//DSI0_DISP_DSI_RDBK_NUM
+-#define DSI0_DISP_DSI_RDBK_NUM__RD_NUM__SHIFT 0x0
+-#define DSI0_DISP_DSI_RDBK_NUM__ALL_NUM__SHIFT 0x10
+-#define DSI0_DISP_DSI_RDBK_NUM__RD_NUM_MASK 0x0000FFFFL
+-#define DSI0_DISP_DSI_RDBK_NUM__ALL_NUM_MASK 0xFFFF0000L
+-//DSI0_DISP_DSI_CMD_MEM_PWR_CTRL
+-#define DSI0_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_DIS__SHIFT 0x0
+-#define DSI0_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_FORCE__SHIFT 0x4
+-#define DSI0_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_STATE__SHIFT 0x8
+-#define DSI0_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_MODE_SEL__SHIFT 0xc
+-#define DSI0_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_DIS_MASK 0x00000001L
+-#define DSI0_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_FORCE_MASK 0x00000030L
+-#define DSI0_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_STATE_MASK 0x00000300L
+-#define DSI0_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_MODE_SEL_MASK 0x00003000L
+-
+-
+-// addressBlock: dce_dc_dsi1_dispdec
+-//DSI1_DISP_DSI_CTRL
+-#define DSI1_DISP_DSI_CTRL__DSI_EN__SHIFT 0x0
+-#define DSI1_DISP_DSI_CTRL__VIDEO_MODE_EN__SHIFT 0x1
+-#define DSI1_DISP_DSI_CTRL__CMD_MODE_EN__SHIFT 0x2
+-#define DSI1_DISP_DSI_CTRL__DLN0_EN__SHIFT 0x4
+-#define DSI1_DISP_DSI_CTRL__DLN1_EN__SHIFT 0x5
+-#define DSI1_DISP_DSI_CTRL__DLN2_EN__SHIFT 0x6
+-#define DSI1_DISP_DSI_CTRL__DLN3_EN__SHIFT 0x7
+-#define DSI1_DISP_DSI_CTRL__CLKLN_EN__SHIFT 0x8
+-#define DSI1_DISP_DSI_CTRL__DLN0_PHY_EN__SHIFT 0xc
+-#define DSI1_DISP_DSI_CTRL__DLN1_PHY_EN__SHIFT 0xd
+-#define DSI1_DISP_DSI_CTRL__DLN2_PHY_EN__SHIFT 0xe
+-#define DSI1_DISP_DSI_CTRL__DLN3_PHY_EN__SHIFT 0xf
+-#define DSI1_DISP_DSI_CTRL__RESET_DISPCLK__SHIFT 0x10
+-#define DSI1_DISP_DSI_CTRL__RESET_DSICLK__SHIFT 0x11
+-#define DSI1_DISP_DSI_CTRL__RESET_BYTECLK__SHIFT 0x12
+-#define DSI1_DISP_DSI_CTRL__RESET_ESCCLK__SHIFT 0x13
+-#define DSI1_DISP_DSI_CTRL__CRTC_SEL__SHIFT 0x14
+-#define DSI1_DISP_DSI_CTRL__ECC_CHK_EN__SHIFT 0x18
+-#define DSI1_DISP_DSI_CTRL__CRC_CHK_EN__SHIFT 0x19
+-#define DSI1_DISP_DSI_CTRL__PACKET_BYTE_MSB_LSB_FLIP__SHIFT 0x1c
+-#define DSI1_DISP_DSI_CTRL__PRE_TRIGGER_EN__SHIFT 0x1d
+-#define DSI1_DISP_DSI_CTRL__NEW_INTERLEAVE_MODE_EN__SHIFT 0x1e
+-#define DSI1_DISP_DSI_CTRL__DSI_EN_MASK 0x00000001L
+-#define DSI1_DISP_DSI_CTRL__VIDEO_MODE_EN_MASK 0x00000002L
+-#define DSI1_DISP_DSI_CTRL__CMD_MODE_EN_MASK 0x00000004L
+-#define DSI1_DISP_DSI_CTRL__DLN0_EN_MASK 0x00000010L
+-#define DSI1_DISP_DSI_CTRL__DLN1_EN_MASK 0x00000020L
+-#define DSI1_DISP_DSI_CTRL__DLN2_EN_MASK 0x00000040L
+-#define DSI1_DISP_DSI_CTRL__DLN3_EN_MASK 0x00000080L
+-#define DSI1_DISP_DSI_CTRL__CLKLN_EN_MASK 0x00000100L
+-#define DSI1_DISP_DSI_CTRL__DLN0_PHY_EN_MASK 0x00001000L
+-#define DSI1_DISP_DSI_CTRL__DLN1_PHY_EN_MASK 0x00002000L
+-#define DSI1_DISP_DSI_CTRL__DLN2_PHY_EN_MASK 0x00004000L
+-#define DSI1_DISP_DSI_CTRL__DLN3_PHY_EN_MASK 0x00008000L
+-#define DSI1_DISP_DSI_CTRL__RESET_DISPCLK_MASK 0x00010000L
+-#define DSI1_DISP_DSI_CTRL__RESET_DSICLK_MASK 0x00020000L
+-#define DSI1_DISP_DSI_CTRL__RESET_BYTECLK_MASK 0x00040000L
+-#define DSI1_DISP_DSI_CTRL__RESET_ESCCLK_MASK 0x00080000L
+-#define DSI1_DISP_DSI_CTRL__CRTC_SEL_MASK 0x00700000L
+-#define DSI1_DISP_DSI_CTRL__ECC_CHK_EN_MASK 0x01000000L
+-#define DSI1_DISP_DSI_CTRL__CRC_CHK_EN_MASK 0x02000000L
+-#define DSI1_DISP_DSI_CTRL__PACKET_BYTE_MSB_LSB_FLIP_MASK 0x10000000L
+-#define DSI1_DISP_DSI_CTRL__PRE_TRIGGER_EN_MASK 0x20000000L
+-#define DSI1_DISP_DSI_CTRL__NEW_INTERLEAVE_MODE_EN_MASK 0x40000000L
+-//DSI1_DISP_DSI_STATUS
+-#define DSI1_DISP_DSI_STATUS__CMD_MODE_ENGINE_BUSY__SHIFT 0x0
+-#define DSI1_DISP_DSI_STATUS__CMD_MODE_DMA_BUSY__SHIFT 0x1
+-#define DSI1_DISP_DSI_STATUS__CMD_MODE_DENG_BUSY__SHIFT 0x2
+-#define DSI1_DISP_DSI_STATUS__VIDEO_MODE_ENGINE_BUSY__SHIFT 0x3
+-#define DSI1_DISP_DSI_STATUS__BTA_BUSY__SHIFT 0x4
+-#define DSI1_DISP_DSI_STATUS__GENERIC_TRIGGER_BUSY__SHIFT 0x5
+-#define DSI1_DISP_DSI_STATUS__PHY_RESET_BUSY__SHIFT 0x6
+-#define DSI1_DISP_DSI_STATUS__DLN0_HS_FIFO_EMPTY__SHIFT 0x8
+-#define DSI1_DISP_DSI_STATUS__DLN0_HS_FIFO_FULL__SHIFT 0x9
+-#define DSI1_DISP_DSI_STATUS__DLN1_HS_FIFO_EMPTY__SHIFT 0xa
+-#define DSI1_DISP_DSI_STATUS__DLN1_HS_FIFO_FULL__SHIFT 0xb
+-#define DSI1_DISP_DSI_STATUS__DLN2_HS_FIFO_EMPTY__SHIFT 0xc
+-#define DSI1_DISP_DSI_STATUS__DLN2_HS_FIFO_FULL__SHIFT 0xd
+-#define DSI1_DISP_DSI_STATUS__DLN3_HS_FIFO_EMPTY__SHIFT 0xe
+-#define DSI1_DISP_DSI_STATUS__DLN3_HS_FIFO_FULL__SHIFT 0xf
+-#define DSI1_DISP_DSI_STATUS__DLN0_HS_FIFO_OVERFLOW__SHIFT 0x10
+-#define DSI1_DISP_DSI_STATUS__DLN0_HS_FIFO_OVERFLOW_CLR__SHIFT 0x10
+-#define DSI1_DISP_DSI_STATUS__DLN1_HS_FIFO_OVERFLOW__SHIFT 0x11
+-#define DSI1_DISP_DSI_STATUS__DLN1_HS_FIFO_OVERFLOW_CLR__SHIFT 0x11
+-#define DSI1_DISP_DSI_STATUS__DLN2_HS_FIFO_OVERFLOW__SHIFT 0x12
+-#define DSI1_DISP_DSI_STATUS__DLN2_HS_FIFO_OVERFLOW_CLR__SHIFT 0x12
+-#define DSI1_DISP_DSI_STATUS__DLN3_HS_FIFO_OVERFLOW__SHIFT 0x13
+-#define DSI1_DISP_DSI_STATUS__DLN3_HS_FIFO_OVERFLOW_CLR__SHIFT 0x13
+-#define DSI1_DISP_DSI_STATUS__DLN0_LP_FIFO_EMPTY__SHIFT 0x14
+-#define DSI1_DISP_DSI_STATUS__DLN0_LP_FIFO_FULL__SHIFT 0x15
+-#define DSI1_DISP_DSI_STATUS__DLN0_LP_FIFO_OVERFLOW__SHIFT 0x16
+-#define DSI1_DISP_DSI_STATUS__DLN0_LP_FIFO_OVERFLOW_CLR__SHIFT 0x16
+-#define DSI1_DISP_DSI_STATUS__CMDFIFO_UNDERFLOW__SHIFT 0x17
+-#define DSI1_DISP_DSI_STATUS__CMDFIFO_UNDERFLOW_CLR__SHIFT 0x17
+-#define DSI1_DISP_DSI_STATUS__INTERLEAVE_PACKET_BLOCK__SHIFT 0x18
+-#define DSI1_DISP_DSI_STATUS__INTERLEAVE_PACKET_BLOCK_CLR__SHIFT 0x18
+-#define DSI1_DISP_DSI_STATUS__TE_ABORT__SHIFT 0x19
+-#define DSI1_DISP_DSI_STATUS__TE_ABORT_CLR__SHIFT 0x19
+-#define DSI1_DISP_DSI_STATUS__DMAFIFO_RD_WATERMARK_REACH__SHIFT 0x1c
+-#define DSI1_DISP_DSI_STATUS__DMAFIFO_RD_WATERMARK_REACH_CLR__SHIFT 0x1c
+-#define DSI1_DISP_DSI_STATUS__DMAFIFO_WR_WATERMARK_REACH__SHIFT 0x1d
+-#define DSI1_DISP_DSI_STATUS__DMAFIFO_WR_WATERMARK_REACH_CLR__SHIFT 0x1d
+-#define DSI1_DISP_DSI_STATUS__DMAFIFO_UNDERFLOW__SHIFT 0x1e
+-#define DSI1_DISP_DSI_STATUS__DMAFIFO_UNDERFLOW_CLR__SHIFT 0x1e
+-#define DSI1_DISP_DSI_STATUS__INTERLEAVE_OP_CONTENTION__SHIFT 0x1f
+-#define DSI1_DISP_DSI_STATUS__INTERLEAVE_OP_CONTENTION_CLR__SHIFT 0x1f
+-#define DSI1_DISP_DSI_STATUS__CMD_MODE_ENGINE_BUSY_MASK 0x00000001L
+-#define DSI1_DISP_DSI_STATUS__CMD_MODE_DMA_BUSY_MASK 0x00000002L
+-#define DSI1_DISP_DSI_STATUS__CMD_MODE_DENG_BUSY_MASK 0x00000004L
+-#define DSI1_DISP_DSI_STATUS__VIDEO_MODE_ENGINE_BUSY_MASK 0x00000008L
+-#define DSI1_DISP_DSI_STATUS__BTA_BUSY_MASK 0x00000010L
+-#define DSI1_DISP_DSI_STATUS__GENERIC_TRIGGER_BUSY_MASK 0x00000020L
+-#define DSI1_DISP_DSI_STATUS__PHY_RESET_BUSY_MASK 0x00000040L
+-#define DSI1_DISP_DSI_STATUS__DLN0_HS_FIFO_EMPTY_MASK 0x00000100L
+-#define DSI1_DISP_DSI_STATUS__DLN0_HS_FIFO_FULL_MASK 0x00000200L
+-#define DSI1_DISP_DSI_STATUS__DLN1_HS_FIFO_EMPTY_MASK 0x00000400L
+-#define DSI1_DISP_DSI_STATUS__DLN1_HS_FIFO_FULL_MASK 0x00000800L
+-#define DSI1_DISP_DSI_STATUS__DLN2_HS_FIFO_EMPTY_MASK 0x00001000L
+-#define DSI1_DISP_DSI_STATUS__DLN2_HS_FIFO_FULL_MASK 0x00002000L
+-#define DSI1_DISP_DSI_STATUS__DLN3_HS_FIFO_EMPTY_MASK 0x00004000L
+-#define DSI1_DISP_DSI_STATUS__DLN3_HS_FIFO_FULL_MASK 0x00008000L
+-#define DSI1_DISP_DSI_STATUS__DLN0_HS_FIFO_OVERFLOW_MASK 0x00010000L
+-#define DSI1_DISP_DSI_STATUS__DLN0_HS_FIFO_OVERFLOW_CLR_MASK 0x00010000L
+-#define DSI1_DISP_DSI_STATUS__DLN1_HS_FIFO_OVERFLOW_MASK 0x00020000L
+-#define DSI1_DISP_DSI_STATUS__DLN1_HS_FIFO_OVERFLOW_CLR_MASK 0x00020000L
+-#define DSI1_DISP_DSI_STATUS__DLN2_HS_FIFO_OVERFLOW_MASK 0x00040000L
+-#define DSI1_DISP_DSI_STATUS__DLN2_HS_FIFO_OVERFLOW_CLR_MASK 0x00040000L
+-#define DSI1_DISP_DSI_STATUS__DLN3_HS_FIFO_OVERFLOW_MASK 0x00080000L
+-#define DSI1_DISP_DSI_STATUS__DLN3_HS_FIFO_OVERFLOW_CLR_MASK 0x00080000L
+-#define DSI1_DISP_DSI_STATUS__DLN0_LP_FIFO_EMPTY_MASK 0x00100000L
+-#define DSI1_DISP_DSI_STATUS__DLN0_LP_FIFO_FULL_MASK 0x00200000L
+-#define DSI1_DISP_DSI_STATUS__DLN0_LP_FIFO_OVERFLOW_MASK 0x00400000L
+-#define DSI1_DISP_DSI_STATUS__DLN0_LP_FIFO_OVERFLOW_CLR_MASK 0x00400000L
+-#define DSI1_DISP_DSI_STATUS__CMDFIFO_UNDERFLOW_MASK 0x00800000L
+-#define DSI1_DISP_DSI_STATUS__CMDFIFO_UNDERFLOW_CLR_MASK 0x00800000L
+-#define DSI1_DISP_DSI_STATUS__INTERLEAVE_PACKET_BLOCK_MASK 0x01000000L
+-#define DSI1_DISP_DSI_STATUS__INTERLEAVE_PACKET_BLOCK_CLR_MASK 0x01000000L
+-#define DSI1_DISP_DSI_STATUS__TE_ABORT_MASK 0x02000000L
+-#define DSI1_DISP_DSI_STATUS__TE_ABORT_CLR_MASK 0x02000000L
+-#define DSI1_DISP_DSI_STATUS__DMAFIFO_RD_WATERMARK_REACH_MASK 0x10000000L
+-#define DSI1_DISP_DSI_STATUS__DMAFIFO_RD_WATERMARK_REACH_CLR_MASK 0x10000000L
+-#define DSI1_DISP_DSI_STATUS__DMAFIFO_WR_WATERMARK_REACH_MASK 0x20000000L
+-#define DSI1_DISP_DSI_STATUS__DMAFIFO_WR_WATERMARK_REACH_CLR_MASK 0x20000000L
+-#define DSI1_DISP_DSI_STATUS__DMAFIFO_UNDERFLOW_MASK 0x40000000L
+-#define DSI1_DISP_DSI_STATUS__DMAFIFO_UNDERFLOW_CLR_MASK 0x40000000L
+-#define DSI1_DISP_DSI_STATUS__INTERLEAVE_OP_CONTENTION_MASK 0x80000000L
+-#define DSI1_DISP_DSI_STATUS__INTERLEAVE_OP_CONTENTION_CLR_MASK 0x80000000L
+-//DSI1_DISP_DSI_VIDEO_MODE_CTRL
+-#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__VC__SHIFT 0x0
+-#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__DST_FORMAT__SHIFT 0x4
+-#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__TRAFFIC_MODE__SHIFT 0x8
+-#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__BLLP_PWR_MODE__SHIFT 0xc
+-#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__EOF_BLLP_PWR_MODE__SHIFT 0xf
+-#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__HSA_PWR_MODE__SHIFT 0x10
+-#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__HBP_PWR_MODE__SHIFT 0x14
+-#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__HFP_PWR_MODE__SHIFT 0x18
+-#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__PULSE_MODE_OPT__SHIFT 0x1c
+-#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__VC_MASK 0x00000003L
+-#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__DST_FORMAT_MASK 0x00000030L
+-#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__TRAFFIC_MODE_MASK 0x00000300L
+-#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__BLLP_PWR_MODE_MASK 0x00001000L
+-#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__EOF_BLLP_PWR_MODE_MASK 0x00008000L
+-#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__HSA_PWR_MODE_MASK 0x00010000L
+-#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__HBP_PWR_MODE_MASK 0x00100000L
+-#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__HFP_PWR_MODE_MASK 0x01000000L
+-#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__PULSE_MODE_OPT_MASK 0x10000000L
+-//DSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE
+-#define DSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__VS__SHIFT 0x0
+-#define DSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__VE__SHIFT 0x8
+-#define DSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__HS__SHIFT 0x10
+-#define DSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__HE__SHIFT 0x18
+-#define DSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__VS_MASK 0x0000003FL
+-#define DSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__VE_MASK 0x00003F00L
+-#define DSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__HS_MASK 0x003F0000L
+-#define DSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__HE_MASK 0x3F000000L
+-//DSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD
+-#define DSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD__VS_PAYLOAD__SHIFT 0x0
+-#define DSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD__VE_PAYLOAD__SHIFT 0x10
+-#define DSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD__VS_PAYLOAD_MASK 0x0000FFFFL
+-#define DSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD__VE_PAYLOAD_MASK 0xFFFF0000L
+-//DSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD
+-#define DSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD__HS_PAYLOAD__SHIFT 0x0
+-#define DSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD__HE_PAYLOAD__SHIFT 0x10
+-#define DSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD__HS_PAYLOAD_MASK 0x0000FFFFL
+-#define DSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD__HE_PAYLOAD_MASK 0xFFFF0000L
+-//DSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE
+-#define DSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB565__SHIFT 0x0
+-#define DSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB666_PACKED__SHIFT 0x8
+-#define DSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB666__SHIFT 0x10
+-#define DSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB888__SHIFT 0x18
+-#define DSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB565_MASK 0x0000003FL
+-#define DSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB666_PACKED_MASK 0x00003F00L
+-#define DSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB666_MASK 0x003F0000L
+-#define DSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB888_MASK 0x3F000000L
+-//DSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE
+-#define DSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE__BLANK_PKT_DATA__SHIFT 0x0
+-#define DSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE__BLANK_PKT_DATATYPE__SHIFT 0x8
+-#define DSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE__BLANK_PKT_DATA_MASK 0x000000FFL
+-#define DSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE__BLANK_PKT_DATATYPE_MASK 0x00003F00L
+-//DSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL
+-#define DSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL__R_SEL__SHIFT 0x0
+-#define DSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL__G_SEL__SHIFT 0x4
+-#define DSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL__B_SEL__SHIFT 0x8
+-#define DSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL__RGB_SWAP__SHIFT 0xc
+-#define DSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL__R_SEL_MASK 0x00000001L
+-#define DSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL__G_SEL_MASK 0x00000010L
+-#define DSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL__B_SEL_MASK 0x00000100L
+-#define DSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL__RGB_SWAP_MASK 0x00007000L
+-//DSI1_DISP_DSI_COMMAND_MODE_CTRL
+-#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__WC__SHIFT 0x0
+-#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__DT__SHIFT 0x10
+-#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__VC__SHIFT 0x16
+-#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__PACKET_TYPE__SHIFT 0x18
+-#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__POWER_MODE__SHIFT 0x1a
+-#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__EMBEDDED_MODE__SHIFT 0x1c
+-#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__CMD_DATA_ORDER__SHIFT 0x1f
+-#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__WC_MASK 0x0000FFFFL
+-#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__DT_MASK 0x003F0000L
+-#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__VC_MASK 0x00C00000L
+-#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__PACKET_TYPE_MASK 0x01000000L
+-#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__POWER_MODE_MASK 0x04000000L
+-#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__EMBEDDED_MODE_MASK 0x10000000L
+-#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__CMD_DATA_ORDER_MASK 0x80000000L
+-//DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL
+-#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__SRC_FORMAT__SHIFT 0x0
+-#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__DST_FORMAT__SHIFT 0x4
+-#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__DATA_BUFFER_ID__SHIFT 0x8
+-#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__SHADOW_DATA_BUFFER_ID__SHIFT 0xc
+-#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__R_SEL__SHIFT 0x10
+-#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__G_SEL__SHIFT 0x11
+-#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__B_SEL__SHIFT 0x12
+-#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__RGB_SWAP__SHIFT 0x14
+-#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__DWORD_BYTE_SWAP__SHIFT 0x18
+-#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__SRC_FORMAT_MASK 0x0000000FL
+-#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__DST_FORMAT_MASK 0x000000F0L
+-#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__DATA_BUFFER_ID_MASK 0x00000100L
+-#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__SHADOW_DATA_BUFFER_ID_MASK 0x00001000L
+-#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__R_SEL_MASK 0x00010000L
+-#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__G_SEL_MASK 0x00020000L
+-#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__B_SEL_MASK 0x00040000L
+-#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__RGB_SWAP_MASK 0x00700000L
+-#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__DWORD_BYTE_SWAP_MASK 0x03000000L
+-//DSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL
+-#define DSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__WR_MEM_START__SHIFT 0x0
+-#define DSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__WR_MEM_CONTINUE__SHIFT 0x8
+-#define DSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__INSERT_DCS_COMMAND__SHIFT 0x10
+-#define DSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__WR_MEM_START_MASK 0x000000FFL
+-#define DSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__WR_MEM_CONTINUE_MASK 0x0000FF00L
+-#define DSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__INSERT_DCS_COMMAND_MASK 0x00010000L
+-//DSI1_DISP_DSI_DMA_CMD_OFFSET
+-#define DSI1_DISP_DSI_DMA_CMD_OFFSET__CMD_OFFSET__SHIFT 0x0
+-#define DSI1_DISP_DSI_DMA_CMD_OFFSET__CMD_OFFSET_MASK 0xFFFFFFFFL
+-//DSI1_DISP_DSI_DMA_CMD_LENGTH
+-#define DSI1_DISP_DSI_DMA_CMD_LENGTH__CMD_LENGTH__SHIFT 0x0
+-#define DSI1_DISP_DSI_DMA_CMD_LENGTH__CMD_LENGTH_MASK 0x00FFFFFFL
+-//DSI1_DISP_DSI_DMA_DATA_OFFSET_0
+-#define DSI1_DISP_DSI_DMA_DATA_OFFSET_0__DATA_SRC_OFFSET0__SHIFT 0x0
+-#define DSI1_DISP_DSI_DMA_DATA_OFFSET_0__DATA_SRC_OFFSET0_MASK 0xFFFFFFFFL
+-//DSI1_DISP_DSI_DMA_DATA_OFFSET_1
+-#define DSI1_DISP_DSI_DMA_DATA_OFFSET_1__DATA_SRC_OFFSET1__SHIFT 0x0
+-#define DSI1_DISP_DSI_DMA_DATA_OFFSET_1__DATA_SRC_OFFSET1_MASK 0xFFFFFFFFL
+-//DSI1_DISP_DSI_DMA_DATA_PITCH
+-#define DSI1_DISP_DSI_DMA_DATA_PITCH__DATA_SRC_PITCH__SHIFT 0x0
+-#define DSI1_DISP_DSI_DMA_DATA_PITCH__DATA_SRC_PITCH_MASK 0x00007FFFL
+-//DSI1_DISP_DSI_DMA_DATA_WIDTH
+-#define DSI1_DISP_DSI_DMA_DATA_WIDTH__DATA_SRC_WIDTH__SHIFT 0x0
+-#define DSI1_DISP_DSI_DMA_DATA_WIDTH__DATA_SRC_WIDTH_ALIGN__SHIFT 0x18
+-#define DSI1_DISP_DSI_DMA_DATA_WIDTH__DATA_SRC_WIDTH_MASK 0x000FFFFFL
+-#define DSI1_DISP_DSI_DMA_DATA_WIDTH__DATA_SRC_WIDTH_ALIGN_MASK 0x07000000L
+-//DSI1_DISP_DSI_DMA_DATA_HEIGHT
+-#define DSI1_DISP_DSI_DMA_DATA_HEIGHT__DATA_SRC_HEIGHT__SHIFT 0x0
+-#define DSI1_DISP_DSI_DMA_DATA_HEIGHT__DATA_SRC_HEIGHT_MASK 0x00000FFFL
+-//DSI1_DISP_DSI_DMA_FIFO_CTRL
+-#define DSI1_DISP_DSI_DMA_FIFO_CTRL__WRITE_WATERMARK__SHIFT 0x0
+-#define DSI1_DISP_DSI_DMA_FIFO_CTRL__READ_WATERMARK__SHIFT 0x4
+-#define DSI1_DISP_DSI_DMA_FIFO_CTRL__WRITE_WATERMARK_MASK 0x00000003L
+-#define DSI1_DISP_DSI_DMA_FIFO_CTRL__READ_WATERMARK_MASK 0x00000030L
+-//DSI1_DISP_DSI_DMA_NULL_PACKET_DATA
+-#define DSI1_DISP_DSI_DMA_NULL_PACKET_DATA__NULL_DATA__SHIFT 0x0
+-#define DSI1_DISP_DSI_DMA_NULL_PACKET_DATA__NULL_DATATYPE__SHIFT 0x8
+-#define DSI1_DISP_DSI_DMA_NULL_PACKET_DATA__NULL_DATA_MASK 0x000000FFL
+-#define DSI1_DISP_DSI_DMA_NULL_PACKET_DATA__NULL_DATATYPE_MASK 0x00003F00L
+-//DSI1_DISP_DSI_DENG_DATA_LENGTH
+-#define DSI1_DISP_DSI_DENG_DATA_LENGTH__DENG_LENGTH__SHIFT 0x0
+-#define DSI1_DISP_DSI_DENG_DATA_LENGTH__USE_DENG_LENGTH__SHIFT 0x1f
+-#define DSI1_DISP_DSI_DENG_DATA_LENGTH__DENG_LENGTH_MASK 0x00FFFFFFL
+-#define DSI1_DISP_DSI_DENG_DATA_LENGTH__USE_DENG_LENGTH_MASK 0x80000000L
+-//DSI1_DISP_DSI_ACK_ERROR_REPORT
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__SOT_ERR__SHIFT 0x0
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__SOT_ERR_CLR__SHIFT 0x0
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__SOT_SYNC_ERR__SHIFT 0x1
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__SOT_SYNC_ERR_CLR__SHIFT 0x1
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__EOT_ERR__SHIFT 0x2
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__EOT_ERR_CLR__SHIFT 0x2
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ESC_ERR__SHIFT 0x3
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ESC_ERR_CLR__SHIFT 0x3
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__LP_ERR__SHIFT 0x4
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__LP_ERR_CLR__SHIFT 0x4
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__HRX_TO__SHIFT 0x5
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__HRX_TO_CLR__SHIFT 0x5
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__FALSE_CTRL_ERR__SHIFT 0x6
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__FALSE_CTRL_ERR_CLR__SHIFT 0x6
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__CONTENTION_ERR__SHIFT 0x7
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__CONTENTION_ERR_CLR__SHIFT 0x7
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ECC_ERR__SHIFT 0x8
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ECC_ERR_CLR__SHIFT 0x8
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__MULTI_ECC_ERR__SHIFT 0x9
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__MULTI_ECC_ERR_CLR__SHIFT 0x9
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__CRC_ERR__SHIFT 0xa
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__CRC_ERR_CLR__SHIFT 0xa
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__DT_ERR__SHIFT 0xb
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__DT_ERR_CLR__SHIFT 0xb
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__VC_ERR__SHIFT 0xc
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__VC_ERR_CLR__SHIFT 0xc
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__PROTOCOL_VIOLATION__SHIFT 0xd
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__PROTOCOL_VIOLATION_CLR__SHIFT 0xd
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__PANEL_SPECIFIC_ERR__SHIFT 0xf
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__PANEL_SPECIFIC_ERR_CLR__SHIFT 0xf
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_ECC_ERR__SHIFT 0x10
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_ECC_ERR_CLR__SHIFT 0x10
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_MULTI_ECC_ERR__SHIFT 0x11
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_MULTI_ECC_ERR_CLR__SHIFT 0x11
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_CRC_ERR__SHIFT 0x14
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_CRC_ERR_CLR__SHIFT 0x14
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_INCOMPLETE_PACKET_ERR__SHIFT 0x17
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_INCOMPLETE_PACKET_ERR_CLR__SHIFT 0x17
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ERROR__SHIFT 0x18
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ERROR_CLR__SHIFT 0x18
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ACK__SHIFT 0x1c
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ACK_CLR__SHIFT 0x1c
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__SOT_ERR_MASK 0x00000001L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__SOT_ERR_CLR_MASK 0x00000001L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__SOT_SYNC_ERR_MASK 0x00000002L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__SOT_SYNC_ERR_CLR_MASK 0x00000002L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__EOT_ERR_MASK 0x00000004L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__EOT_ERR_CLR_MASK 0x00000004L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ESC_ERR_MASK 0x00000008L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ESC_ERR_CLR_MASK 0x00000008L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__LP_ERR_MASK 0x00000010L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__LP_ERR_CLR_MASK 0x00000010L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__HRX_TO_MASK 0x00000020L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__HRX_TO_CLR_MASK 0x00000020L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__FALSE_CTRL_ERR_MASK 0x00000040L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__FALSE_CTRL_ERR_CLR_MASK 0x00000040L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__CONTENTION_ERR_MASK 0x00000080L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__CONTENTION_ERR_CLR_MASK 0x00000080L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ECC_ERR_MASK 0x00000100L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ECC_ERR_CLR_MASK 0x00000100L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__MULTI_ECC_ERR_MASK 0x00000200L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__MULTI_ECC_ERR_CLR_MASK 0x00000200L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__CRC_ERR_MASK 0x00000400L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__CRC_ERR_CLR_MASK 0x00000400L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__DT_ERR_MASK 0x00000800L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__DT_ERR_CLR_MASK 0x00000800L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__VC_ERR_MASK 0x00001000L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__VC_ERR_CLR_MASK 0x00001000L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__PROTOCOL_VIOLATION_MASK 0x00002000L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__PROTOCOL_VIOLATION_CLR_MASK 0x00002000L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__PANEL_SPECIFIC_ERR_MASK 0x00008000L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__PANEL_SPECIFIC_ERR_CLR_MASK 0x00008000L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_ECC_ERR_MASK 0x00010000L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_ECC_ERR_CLR_MASK 0x00010000L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_MULTI_ECC_ERR_MASK 0x00020000L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_MULTI_ECC_ERR_CLR_MASK 0x00020000L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_CRC_ERR_MASK 0x00100000L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_CRC_ERR_CLR_MASK 0x00100000L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_INCOMPLETE_PACKET_ERR_MASK 0x00800000L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_INCOMPLETE_PACKET_ERR_CLR_MASK 0x00800000L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ERROR_MASK 0x01000000L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ERROR_CLR_MASK 0x01000000L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ACK_MASK 0x10000000L
+-#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ACK_CLR_MASK 0x10000000L
+-//DSI1_DISP_DSI_RDBK_DATA0
+-#define DSI1_DISP_DSI_RDBK_DATA0__RD_DATA0__SHIFT 0x0
+-#define DSI1_DISP_DSI_RDBK_DATA0__RD_DATA0_MASK 0xFFFFFFFFL
+-//DSI1_DISP_DSI_RDBK_DATA1
+-#define DSI1_DISP_DSI_RDBK_DATA1__RD_DATA1__SHIFT 0x0
+-#define DSI1_DISP_DSI_RDBK_DATA1__RD_DATA1_MASK 0xFFFFFFFFL
+-//DSI1_DISP_DSI_RDBK_DATA2
+-#define DSI1_DISP_DSI_RDBK_DATA2__RD_DATA2__SHIFT 0x0
+-#define DSI1_DISP_DSI_RDBK_DATA2__RD_DATA2_MASK 0xFFFFFFFFL
+-//DSI1_DISP_DSI_RDBK_DATA3
+-#define DSI1_DISP_DSI_RDBK_DATA3__RD_DATA3__SHIFT 0x0
+-#define DSI1_DISP_DSI_RDBK_DATA3__RD_DATA3_MASK 0xFFFFFFFFL
+-//DSI1_DISP_DSI_RDBK_DATATYPE0
+-#define DSI1_DISP_DSI_RDBK_DATATYPE0__GENERIC_SHORT_RD_1_BYTE__SHIFT 0x0
+-#define DSI1_DISP_DSI_RDBK_DATATYPE0__GENERIC_SHORT_RD_2_BYTE__SHIFT 0x8
+-#define DSI1_DISP_DSI_RDBK_DATATYPE0__DCS_SHORT_RD_1_BYTE__SHIFT 0x10
+-#define DSI1_DISP_DSI_RDBK_DATATYPE0__DCS_SHORT_RD_2_BYTE__SHIFT 0x18
+-#define DSI1_DISP_DSI_RDBK_DATATYPE0__GENERIC_SHORT_RD_1_BYTE_MASK 0x0000003FL
+-#define DSI1_DISP_DSI_RDBK_DATATYPE0__GENERIC_SHORT_RD_2_BYTE_MASK 0x00003F00L
+-#define DSI1_DISP_DSI_RDBK_DATATYPE0__DCS_SHORT_RD_1_BYTE_MASK 0x003F0000L
+-#define DSI1_DISP_DSI_RDBK_DATATYPE0__DCS_SHORT_RD_2_BYTE_MASK 0x3F000000L
+-//DSI1_DISP_DSI_RDBK_DATATYPE1
+-#define DSI1_DISP_DSI_RDBK_DATATYPE1__ERROR_REPORT__SHIFT 0x0
+-#define DSI1_DISP_DSI_RDBK_DATATYPE1__GENERIC_LONG_RD__SHIFT 0x8
+-#define DSI1_DISP_DSI_RDBK_DATATYPE1__DCS_LONG_RD__SHIFT 0x10
+-#define DSI1_DISP_DSI_RDBK_DATATYPE1__ERROR_REPORT_MASK 0x0000003FL
+-#define DSI1_DISP_DSI_RDBK_DATATYPE1__GENERIC_LONG_RD_MASK 0x00003F00L
+-#define DSI1_DISP_DSI_RDBK_DATATYPE1__DCS_LONG_RD_MASK 0x003F0000L
+-//DSI1_DISP_DSI_TRIG_CTRL
+-#define DSI1_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_TRIGGER_MODE__SHIFT 0x0
+-#define DSI1_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_TRIGGER_SEL__SHIFT 0x4
+-#define DSI1_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DENG_TRIGGER_MODE__SHIFT 0x10
+-#define DSI1_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DENG_TRIGGER_SEL__SHIFT 0x14
+-#define DSI1_DISP_DSI_TRIG_CTRL__HW_SOURCE_SEL__SHIFT 0x18
+-#define DSI1_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_DENG_ORDER__SHIFT 0x1c
+-#define DSI1_DISP_DSI_TRIG_CTRL__TE_SEL__SHIFT 0x1f
+-#define DSI1_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_TRIGGER_MODE_MASK 0x00000001L
+-#define DSI1_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_TRIGGER_SEL_MASK 0x00000030L
+-#define DSI1_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DENG_TRIGGER_MODE_MASK 0x00010000L
+-#define DSI1_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DENG_TRIGGER_SEL_MASK 0x00300000L
+-#define DSI1_DISP_DSI_TRIG_CTRL__HW_SOURCE_SEL_MASK 0x0F000000L
+-#define DSI1_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_DENG_ORDER_MASK 0x10000000L
+-#define DSI1_DISP_DSI_TRIG_CTRL__TE_SEL_MASK 0x80000000L
+-//DSI1_DISP_DSI_EXT_MUX
+-#define DSI1_DISP_DSI_EXT_MUX__EXT_TE_MUX__SHIFT 0x0
+-#define DSI1_DISP_DSI_EXT_MUX__EXT_TE_MODE__SHIFT 0x4
+-#define DSI1_DISP_DSI_EXT_MUX__EXT_RESET_POL__SHIFT 0x6
+-#define DSI1_DISP_DSI_EXT_MUX__EXT_TE_POL__SHIFT 0x7
+-#define DSI1_DISP_DSI_EXT_MUX__EXT_TE_HSYNC_TRIG_CNT__SHIFT 0x8
+-#define DSI1_DISP_DSI_EXT_MUX__EXT_TE_HSYNC_TOTAL__SHIFT 0x14
+-#define DSI1_DISP_DSI_EXT_MUX__EXT_TE_MUX_MASK 0x0000000FL
+-#define DSI1_DISP_DSI_EXT_MUX__EXT_TE_MODE_MASK 0x00000030L
+-#define DSI1_DISP_DSI_EXT_MUX__EXT_RESET_POL_MASK 0x00000040L
+-#define DSI1_DISP_DSI_EXT_MUX__EXT_TE_POL_MASK 0x00000080L
+-#define DSI1_DISP_DSI_EXT_MUX__EXT_TE_HSYNC_TRIG_CNT_MASK 0x000FFF00L
+-#define DSI1_DISP_DSI_EXT_MUX__EXT_TE_HSYNC_TOTAL_MASK 0xFFF00000L
+-//DSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL
+-#define DSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL__TE_HSYNC_MAX_WIDTH__SHIFT 0x0
+-#define DSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL__TE_VSYNC_MIN_WIDTH__SHIFT 0x10
+-#define DSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL__TE_HSYNC_MAX_WIDTH_MASK 0x0000FFFFL
+-#define DSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL__TE_VSYNC_MIN_WIDTH_MASK 0xFFFF0000L
+-//DSI1_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER
+-#define DSI1_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER__SW_TRIGGER__SHIFT 0x0
+-#define DSI1_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER__SW_TRIGGER_MASK 0x00000001L
+-//DSI1_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER
+-#define DSI1_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER__SW_TRIGGER__SHIFT 0x0
+-#define DSI1_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER__SW_TRIGGER_MASK 0x00000001L
+-//DSI1_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER
+-#define DSI1_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER__SW_TRIGGER__SHIFT 0x0
+-#define DSI1_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER__SW_TRIGGER_MASK 0x00000001L
+-//DSI1_DISP_DSI_RESET_SW_TRIGGER
+-#define DSI1_DISP_DSI_RESET_SW_TRIGGER__SW_TRIGGER__SHIFT 0x0
+-#define DSI1_DISP_DSI_RESET_SW_TRIGGER__SW_TRIGGER_MASK 0x00000001L
+-//DSI1_DISP_DSI_EXT_RESET
+-#define DSI1_DISP_DSI_EXT_RESET__RESET_PANEL__SHIFT 0x0
+-#define DSI1_DISP_DSI_EXT_RESET__RESET_PANEL_MASK 0x00000001L
+-//DSI1_DISP_DSI_LANE_CRC_HS_MODE
+-#define DSI1_DISP_DSI_LANE_CRC_HS_MODE__DLN0_HS_CRC__SHIFT 0x0
+-#define DSI1_DISP_DSI_LANE_CRC_HS_MODE__DLN1_HS_CRC__SHIFT 0x8
+-#define DSI1_DISP_DSI_LANE_CRC_HS_MODE__DLN2_HS_CRC__SHIFT 0x10
+-#define DSI1_DISP_DSI_LANE_CRC_HS_MODE__DLN3_HS_CRC__SHIFT 0x18
+-#define DSI1_DISP_DSI_LANE_CRC_HS_MODE__DLN0_HS_CRC_MASK 0x000000FFL
+-#define DSI1_DISP_DSI_LANE_CRC_HS_MODE__DLN1_HS_CRC_MASK 0x0000FF00L
+-#define DSI1_DISP_DSI_LANE_CRC_HS_MODE__DLN2_HS_CRC_MASK 0x00FF0000L
+-#define DSI1_DISP_DSI_LANE_CRC_HS_MODE__DLN3_HS_CRC_MASK 0xFF000000L
+-//DSI1_DISP_DSI_LANE_CRC_LP_MODE
+-#define DSI1_DISP_DSI_LANE_CRC_LP_MODE__DLN0_LP_CRC__SHIFT 0x0
+-#define DSI1_DISP_DSI_LANE_CRC_LP_MODE__DLN0_LP_CRC_MASK 0x000000FFL
+-//DSI1_DISP_DSI_LANE_CRC_CTRL
+-#define DSI1_DISP_DSI_LANE_CRC_CTRL__CRC_MAX_HS_DONE_COUNT__SHIFT 0x0
+-#define DSI1_DISP_DSI_LANE_CRC_CTRL__CRC_MAX_LP_DONE_COUNT__SHIFT 0x8
+-#define DSI1_DISP_DSI_LANE_CRC_CTRL__CRC_ENABLE__SHIFT 0x10
+-#define DSI1_DISP_DSI_LANE_CRC_CTRL__CRC_DONE_HS__SHIFT 0x14
+-#define DSI1_DISP_DSI_LANE_CRC_CTRL__CRC_DONE_LP__SHIFT 0x18
+-#define DSI1_DISP_DSI_LANE_CRC_CTRL__CRC_MAX_HS_DONE_COUNT_MASK 0x000000FFL
+-#define DSI1_DISP_DSI_LANE_CRC_CTRL__CRC_MAX_LP_DONE_COUNT_MASK 0x0000FF00L
+-#define DSI1_DISP_DSI_LANE_CRC_CTRL__CRC_ENABLE_MASK 0x00010000L
+-#define DSI1_DISP_DSI_LANE_CRC_CTRL__CRC_DONE_HS_MASK 0x00100000L
+-#define DSI1_DISP_DSI_LANE_CRC_CTRL__CRC_DONE_LP_MASK 0x01000000L
+-//DSI1_DISP_DSI_PIXEL_CRC_CTRL
+-#define DSI1_DISP_DSI_PIXEL_CRC_CTRL__CRC_MAX_PIXEL_COUNT__SHIFT 0x0
+-#define DSI1_DISP_DSI_PIXEL_CRC_CTRL__PIXEL_CRC__SHIFT 0x8
+-#define DSI1_DISP_DSI_PIXEL_CRC_CTRL__CRC_DONE_PIXEL__SHIFT 0x10
+-#define DSI1_DISP_DSI_PIXEL_CRC_CTRL__CRC_MAX_PIXEL_COUNT_MASK 0x000000FFL
+-#define DSI1_DISP_DSI_PIXEL_CRC_CTRL__PIXEL_CRC_MASK 0x0000FF00L
+-#define DSI1_DISP_DSI_PIXEL_CRC_CTRL__CRC_DONE_PIXEL_MASK 0x00010000L
+-//DSI1_DISP_DSI_LANE_CTRL
+-#define DSI1_DISP_DSI_LANE_CTRL__DLN0_ULPS_REQUEST__SHIFT 0x0
+-#define DSI1_DISP_DSI_LANE_CTRL__DLN1_ULPS_REQUEST__SHIFT 0x1
+-#define DSI1_DISP_DSI_LANE_CTRL__DLN2_ULPS_REQUEST__SHIFT 0x2
+-#define DSI1_DISP_DSI_LANE_CTRL__DLN3_ULPS_REQUEST__SHIFT 0x3
+-#define DSI1_DISP_DSI_LANE_CTRL__DLN0_ULPS_EXIT__SHIFT 0x4
+-#define DSI1_DISP_DSI_LANE_CTRL__DLN1_ULPS_EXIT__SHIFT 0x5
+-#define DSI1_DISP_DSI_LANE_CTRL__DLN2_ULPS_EXIT__SHIFT 0x6
+-#define DSI1_DISP_DSI_LANE_CTRL__DLN3_ULPS_EXIT__SHIFT 0x7
+-#define DSI1_DISP_DSI_LANE_CTRL__DLN0_FORCE_TX_STOP__SHIFT 0x8
+-#define DSI1_DISP_DSI_LANE_CTRL__DLN1_FORCE_TX_STOP__SHIFT 0x9
+-#define DSI1_DISP_DSI_LANE_CTRL__DLN2_FORCE_TX_STOP__SHIFT 0xa
+-#define DSI1_DISP_DSI_LANE_CTRL__DLN3_FORCE_TX_STOP__SHIFT 0xb
+-#define DSI1_DISP_DSI_LANE_CTRL__CLKLN_ULPS_REQUEST__SHIFT 0xc
+-#define DSI1_DISP_DSI_LANE_CTRL__CLKLN_ULPS_EXIT__SHIFT 0x10
+-#define DSI1_DISP_DSI_LANE_CTRL__CLKLN_FORCE_TX_STOP__SHIFT 0x14
+-#define DSI1_DISP_DSI_LANE_CTRL__CLKLN_HS_FORCE_REQUEST__SHIFT 0x18
+-#define DSI1_DISP_DSI_LANE_CTRL__DLN0_ULPS_REQUEST_MASK 0x00000001L
+-#define DSI1_DISP_DSI_LANE_CTRL__DLN1_ULPS_REQUEST_MASK 0x00000002L
+-#define DSI1_DISP_DSI_LANE_CTRL__DLN2_ULPS_REQUEST_MASK 0x00000004L
+-#define DSI1_DISP_DSI_LANE_CTRL__DLN3_ULPS_REQUEST_MASK 0x00000008L
+-#define DSI1_DISP_DSI_LANE_CTRL__DLN0_ULPS_EXIT_MASK 0x00000010L
+-#define DSI1_DISP_DSI_LANE_CTRL__DLN1_ULPS_EXIT_MASK 0x00000020L
+-#define DSI1_DISP_DSI_LANE_CTRL__DLN2_ULPS_EXIT_MASK 0x00000040L
+-#define DSI1_DISP_DSI_LANE_CTRL__DLN3_ULPS_EXIT_MASK 0x00000080L
+-#define DSI1_DISP_DSI_LANE_CTRL__DLN0_FORCE_TX_STOP_MASK 0x00000100L
+-#define DSI1_DISP_DSI_LANE_CTRL__DLN1_FORCE_TX_STOP_MASK 0x00000200L
+-#define DSI1_DISP_DSI_LANE_CTRL__DLN2_FORCE_TX_STOP_MASK 0x00000400L
+-#define DSI1_DISP_DSI_LANE_CTRL__DLN3_FORCE_TX_STOP_MASK 0x00000800L
+-#define DSI1_DISP_DSI_LANE_CTRL__CLKLN_ULPS_REQUEST_MASK 0x00001000L
+-#define DSI1_DISP_DSI_LANE_CTRL__CLKLN_ULPS_EXIT_MASK 0x00010000L
+-#define DSI1_DISP_DSI_LANE_CTRL__CLKLN_FORCE_TX_STOP_MASK 0x00100000L
+-#define DSI1_DISP_DSI_LANE_CTRL__CLKLN_HS_FORCE_REQUEST_MASK 0x01000000L
+-//DSI1_DISP_DSI_DLN0_PHY_ERROR
+-#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC__SHIFT 0x0
+-#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC_CLR__SHIFT 0x0
+-#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC_MASK__SHIFT 0x3
+-#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC__SHIFT 0x4
+-#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC_CLR__SHIFT 0x4
+-#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC_MASK__SHIFT 0x7
+-#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL__SHIFT 0x8
+-#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL_CLR__SHIFT 0x8
+-#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL_MASK__SHIFT 0xb
+-#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0__SHIFT 0xc
+-#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0_CLR__SHIFT 0xc
+-#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0_MASK__SHIFT 0xf
+-#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1__SHIFT 0x10
+-#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1_CLR__SHIFT 0x10
+-#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1_MASK__SHIFT 0x13
+-#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC_MASK 0x00000001L
+-#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC_CLR_MASK 0x00000001L
+-#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC_MASK_MASK 0x00000008L
+-#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC_MASK 0x00000010L
+-#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC_CLR_MASK 0x00000010L
+-#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC_MASK_MASK 0x00000080L
+-#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL_MASK 0x00000100L
+-#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL_CLR_MASK 0x00000100L
+-#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL_MASK_MASK 0x00000800L
+-#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0_MASK 0x00001000L
+-#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0_CLR_MASK 0x00001000L
+-#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0_MASK_MASK 0x00008000L
+-#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1_MASK 0x00010000L
+-#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1_CLR_MASK 0x00010000L
+-#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1_MASK_MASK 0x00080000L
+-//DSI1_DISP_DSI_LP_TIMER_CTRL
+-#define DSI1_DISP_DSI_LP_TIMER_CTRL__LP_RX_TO__SHIFT 0x0
+-#define DSI1_DISP_DSI_LP_TIMER_CTRL__BTA_TO__SHIFT 0x10
+-#define DSI1_DISP_DSI_LP_TIMER_CTRL__LP_RX_TO_MASK 0x0000FFFFL
+-#define DSI1_DISP_DSI_LP_TIMER_CTRL__BTA_TO_MASK 0xFFFF0000L
+-//DSI1_DISP_DSI_HS_TIMER_CTRL
+-#define DSI1_DISP_DSI_HS_TIMER_CTRL__HS_TX_TO__SHIFT 0x0
+-#define DSI1_DISP_DSI_HS_TIMER_CTRL__HS_TX_TO_MASK 0x0000FFFFL
+-//DSI1_DISP_DSI_TIMEOUT_STATUS
+-#define DSI1_DISP_DSI_TIMEOUT_STATUS__HS_TX_TIMEOUT__SHIFT 0x0
+-#define DSI1_DISP_DSI_TIMEOUT_STATUS__HS_TX_TIMEOUT_CLR__SHIFT 0x0
+-#define DSI1_DISP_DSI_TIMEOUT_STATUS__LP_RX_TIMEOUT__SHIFT 0x4
+-#define DSI1_DISP_DSI_TIMEOUT_STATUS__LP_RX_TIMEOUT_CLR__SHIFT 0x4
+-#define DSI1_DISP_DSI_TIMEOUT_STATUS__BTA_TIMEOUT__SHIFT 0x8
+-#define DSI1_DISP_DSI_TIMEOUT_STATUS__BTA_TIMEOUT_CLR__SHIFT 0x8
+-#define DSI1_DISP_DSI_TIMEOUT_STATUS__HS_TX_TIMEOUT_MASK 0x00000001L
+-#define DSI1_DISP_DSI_TIMEOUT_STATUS__HS_TX_TIMEOUT_CLR_MASK 0x00000001L
+-#define DSI1_DISP_DSI_TIMEOUT_STATUS__LP_RX_TIMEOUT_MASK 0x00000010L
+-#define DSI1_DISP_DSI_TIMEOUT_STATUS__LP_RX_TIMEOUT_CLR_MASK 0x00000010L
+-#define DSI1_DISP_DSI_TIMEOUT_STATUS__BTA_TIMEOUT_MASK 0x00000100L
+-#define DSI1_DISP_DSI_TIMEOUT_STATUS__BTA_TIMEOUT_CLR_MASK 0x00000100L
+-//DSI1_DISP_DSI_PHY_CLK_TIMING_CTRL
+-#define DSI1_DISP_DSI_PHY_CLK_TIMING_CTRL__T_CLK_PRE__SHIFT 0x0
+-#define DSI1_DISP_DSI_PHY_CLK_TIMING_CTRL__T_CLK_POST__SHIFT 0x8
+-#define DSI1_DISP_DSI_PHY_CLK_TIMING_CTRL__T_CLK_PRE_MASK 0x000000FFL
+-#define DSI1_DISP_DSI_PHY_CLK_TIMING_CTRL__T_CLK_POST_MASK 0x00003F00L
+-//DSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2
+-#define DSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2__T_PRE_TRIGGER__SHIFT 0x0
+-#define DSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2__T_INTER_STOP__SHIFT 0x10
+-#define DSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2__T_PRE_TRIGGER_MASK 0x000007FFL
+-#define DSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2__T_INTER_STOP_MASK 0xFFFF0000L
+-//DSI1_DISP_DSI_EOT_PACKET
+-#define DSI1_DISP_DSI_EOT_PACKET__DI__SHIFT 0x0
+-#define DSI1_DISP_DSI_EOT_PACKET__WC__SHIFT 0x8
+-#define DSI1_DISP_DSI_EOT_PACKET__ECC__SHIFT 0x18
+-#define DSI1_DISP_DSI_EOT_PACKET__DI_MASK 0x000000FFL
+-#define DSI1_DISP_DSI_EOT_PACKET__WC_MASK 0x00FFFF00L
+-#define DSI1_DISP_DSI_EOT_PACKET__ECC_MASK 0xFF000000L
+-//DSI1_DISP_DSI_EOT_PACKET_CTRL
+-#define DSI1_DISP_DSI_EOT_PACKET_CTRL__TX_EOT_APPEND__SHIFT 0x0
+-#define DSI1_DISP_DSI_EOT_PACKET_CTRL__RX_EOT_IGNORE__SHIFT 0x4
+-#define DSI1_DISP_DSI_EOT_PACKET_CTRL__TX_EOT_APPEND_MASK 0x00000001L
+-#define DSI1_DISP_DSI_EOT_PACKET_CTRL__RX_EOT_IGNORE_MASK 0x00000010L
+-//DSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER
+-#define DSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER__SW_TRIGGER__SHIFT 0x0
+-#define DSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER__ENTRY_COMMAND__SHIFT 0x10
+-#define DSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER__SW_TRIGGER_MASK 0x00000001L
+-#define DSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER__ENTRY_COMMAND_MASK 0x00FF0000L
+-//DSI1_DISP_DSI_MIPI_BIST_CTRL
+-#define DSI1_DISP_DSI_MIPI_BIST_CTRL__MIPI_BIST_RESET__SHIFT 0x0
+-#define DSI1_DISP_DSI_MIPI_BIST_CTRL__MIPI_BIST_EN__SHIFT 0x1
+-#define DSI1_DISP_DSI_MIPI_BIST_CTRL__MIPI_BIST_RESET_MASK 0x00000001L
+-#define DSI1_DISP_DSI_MIPI_BIST_CTRL__MIPI_BIST_EN_MASK 0x00000002L
+-//DSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE
+-#define DSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE__MIPI_H_SIZE__SHIFT 0x0
+-#define DSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE__MIPI_V_SIZE__SHIFT 0x10
+-#define DSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE__MIPI_H_SIZE_MASK 0x0000FFFFL
+-#define DSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE__MIPI_V_SIZE_MASK 0xFFFF0000L
+-//DSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE
+-#define DSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE__MIPI_H_SIZE__SHIFT 0x0
+-#define DSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE__MIPI_V_SIZE__SHIFT 0x8
+-#define DSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE__MIPI_H_SIZE_MASK 0x000000FFL
+-#define DSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE__MIPI_V_SIZE_MASK 0x0000FF00L
+-//DSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG
+-#define DSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_BLANKING_CYCLES__SHIFT 0x0
+-#define DSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_FRAME_REPEAT__SHIFT 0x10
+-#define DSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_BIST_VIDEO_FRMT__SHIFT 0x18
+-#define DSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_BLANKING_CYCLES_MASK 0x0000FFFFL
+-#define DSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_FRAME_REPEAT_MASK 0x00FF0000L
+-#define DSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_BIST_VIDEO_FRMT_MASK 0x01000000L
+-//DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL
+-#define DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_Y_LSFR_POLYNOMIAL__SHIFT 0x0
+-#define DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_U_LSFR_POLYNOMIAL__SHIFT 0x8
+-#define DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_V_LSFR_POLYNOMIAL__SHIFT 0x10
+-#define DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_Y_LSFR_EN__SHIFT 0x18
+-#define DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_U_LSFR_EN__SHIFT 0x19
+-#define DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_V_LSFR_EN__SHIFT 0x1a
+-#define DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_Y_LSFR_POLYNOMIAL_MASK 0x000000FFL
+-#define DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_U_LSFR_POLYNOMIAL_MASK 0x0000FF00L
+-#define DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_V_LSFR_POLYNOMIAL_MASK 0x00FF0000L
+-#define DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_Y_LSFR_EN_MASK 0x01000000L
+-#define DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_U_LSFR_EN_MASK 0x02000000L
+-#define DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_V_LSFR_EN_MASK 0x04000000L
+-//DSI1_DISP_DSI_MIPI_BIST_LSFR_INIT
+-#define DSI1_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_Y_INIT_LSFR_VAL__SHIFT 0x0
+-#define DSI1_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_U_INIT_LSFR_VAL__SHIFT 0x8
+-#define DSI1_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_V_INIT_LSFR_VAL__SHIFT 0x10
+-#define DSI1_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_Y_INIT_LSFR_VAL_MASK 0x000000FFL
+-#define DSI1_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_U_INIT_LSFR_VAL_MASK 0x0000FF00L
+-#define DSI1_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_V_INIT_LSFR_VAL_MASK 0x00FF0000L
+-//DSI1_DISP_DSI_MIPI_BIST_START
+-#define DSI1_DISP_DSI_MIPI_BIST_START__MIPI_BIST_START__SHIFT 0x0
+-#define DSI1_DISP_DSI_MIPI_BIST_START__MIPI_BIST_START_MASK 0x00000001L
+-//DSI1_DISP_DSI_MIPI_BIST_STATUS
+-#define DSI1_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_STATUS_BUSY__SHIFT 0x0
+-#define DSI1_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_DONE__SHIFT 0x4
+-#define DSI1_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_DONE_CLR__SHIFT 0x4
+-#define DSI1_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_STATUS_BUSY_MASK 0x00000001L
+-#define DSI1_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_DONE_MASK 0x00000010L
+-#define DSI1_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_DONE_CLR_MASK 0x00000010L
+-//DSI1_DISP_DSI_ERROR_INTERRUPT_MASK
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_ECC_ERR_MASK__SHIFT 0x0
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_MULTI_ECC_ERR_MASK__SHIFT 0x1
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_CRC_ERR_MASK__SHIFT 0x2
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_INCOMPLETE_PACKET_ERR_MASK__SHIFT 0x3
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__ERROR_PACKET_MASK__SHIFT 0x4
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__INTERLEAVE_PACKET_BLOCK_MASK__SHIFT 0x5
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__TE_ABORT_MASK__SHIFT 0x6
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_ESC_MASK__SHIFT 0x8
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_SYNC_ESC_MASK__SHIFT 0x9
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTROL_MASK__SHIFT 0xa
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTENTION_LP0_MASK__SHIFT 0xc
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTENTION_LP1_MASK__SHIFT 0xd
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__LP_RX_TO_MASK__SHIFT 0x10
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__HS_TX_TO_MASK__SHIFT 0x11
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__BTA_TO_MASK__SHIFT 0x12
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DMAFIFO_UNDERFLOW_MASK__SHIFT 0x14
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__CMDFIFO_UNDERFLOW_MASK__SHIFT 0x15
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DENGFIFO_OVERFLOW_UNDERFLOW_MASK__SHIFT 0x18
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_HS_FIFO_OVERFLOW_MASK__SHIFT 0x1a
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN1_HS_FIFO_OVERFLOW_MASK__SHIFT 0x1b
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN2_HS_FIFO_OVERFLOW_MASK__SHIFT 0x1c
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN3_HS_FIFO_OVERFLOW_MASK__SHIFT 0x1d
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_LP_FIFO_OVERFLOW_MASK__SHIFT 0x1e
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__INTERLEAVE_OP_CONTENTION_MASK__SHIFT 0x1f
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_ECC_ERR_MASK_MASK 0x00000001L
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_MULTI_ECC_ERR_MASK_MASK 0x00000002L
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_CRC_ERR_MASK_MASK 0x00000004L
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_INCOMPLETE_PACKET_ERR_MASK_MASK 0x00000008L
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__ERROR_PACKET_MASK_MASK 0x00000010L
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__INTERLEAVE_PACKET_BLOCK_MASK_MASK 0x00000020L
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__TE_ABORT_MASK_MASK 0x00000040L
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_ESC_MASK_MASK 0x00000100L
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_SYNC_ESC_MASK_MASK 0x00000200L
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTROL_MASK_MASK 0x00000400L
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTENTION_LP0_MASK_MASK 0x00001000L
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTENTION_LP1_MASK_MASK 0x00002000L
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__LP_RX_TO_MASK_MASK 0x00010000L
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__HS_TX_TO_MASK_MASK 0x00020000L
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__BTA_TO_MASK_MASK 0x00040000L
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DMAFIFO_UNDERFLOW_MASK_MASK 0x00100000L
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__CMDFIFO_UNDERFLOW_MASK_MASK 0x00200000L
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DENGFIFO_OVERFLOW_UNDERFLOW_MASK_MASK 0x01000000L
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_HS_FIFO_OVERFLOW_MASK_MASK 0x04000000L
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN1_HS_FIFO_OVERFLOW_MASK_MASK 0x08000000L
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN2_HS_FIFO_OVERFLOW_MASK_MASK 0x10000000L
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN3_HS_FIFO_OVERFLOW_MASK_MASK 0x20000000L
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_LP_FIFO_OVERFLOW_MASK_MASK 0x40000000L
+-#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__INTERLEAVE_OP_CONTENTION_MASK_MASK 0x80000000L
+-//DSI1_DISP_DSI_INTERRUPT_CTRL
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_STAT__SHIFT 0x0
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_AK__SHIFT 0x0
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_MASK__SHIFT 0x1
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_STAT__SHIFT 0x4
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_AK__SHIFT 0x4
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_MASK__SHIFT 0x5
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_STAT__SHIFT 0x8
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_AK__SHIFT 0x8
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_MASK__SHIFT 0x9
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_STAT__SHIFT 0xc
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_AK__SHIFT 0xc
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_MASK__SHIFT 0xd
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_STAT__SHIFT 0x10
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_AK__SHIFT 0x10
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_MASK__SHIFT 0x11
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_STAT__SHIFT 0x14
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_AK__SHIFT 0x14
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_MASK__SHIFT 0x15
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_STAT__SHIFT 0x18
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_AK__SHIFT 0x18
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_MASK__SHIFT 0x19
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_STAT_MASK 0x00000001L
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_AK_MASK 0x00000001L
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_MASK_MASK 0x00000002L
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_STAT_MASK 0x00000010L
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_AK_MASK 0x00000010L
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_MASK_MASK 0x00000020L
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_STAT_MASK 0x00000100L
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_AK_MASK 0x00000100L
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_MASK_MASK 0x00000200L
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_STAT_MASK 0x00001000L
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_AK_MASK 0x00001000L
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_MASK_MASK 0x00002000L
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_STAT_MASK 0x00010000L
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_AK_MASK 0x00010000L
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_MASK_MASK 0x00020000L
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_STAT_MASK 0x00100000L
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_AK_MASK 0x00100000L
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_MASK_MASK 0x00200000L
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_STAT_MASK 0x01000000L
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_AK_MASK 0x01000000L
+-#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_MASK_MASK 0x02000000L
+-//DSI1_DISP_DSI_CLK_CTRL
+-#define DSI1_DISP_DSI_CLK_CTRL__DISPCLK_G_ON__SHIFT 0x0
+-#define DSI1_DISP_DSI_CLK_CTRL__DISPCLK_R_ON__SHIFT 0x1
+-#define DSI1_DISP_DSI_CLK_CTRL__DSICLK_G_ON__SHIFT 0x4
+-#define DSI1_DISP_DSI_CLK_CTRL__DSICLK_R_ON__SHIFT 0x5
+-#define DSI1_DISP_DSI_CLK_CTRL__DSICLK_TRN_ON__SHIFT 0x6
+-#define DSI1_DISP_DSI_CLK_CTRL__BYTECLK_G_ON__SHIFT 0x8
+-#define DSI1_DISP_DSI_CLK_CTRL__ESCCLK_G_ON__SHIFT 0x10
+-#define DSI1_DISP_DSI_CLK_CTRL__TEST_CLK_SEL__SHIFT 0x18
+-#define DSI1_DISP_DSI_CLK_CTRL__DISPCLK_G_ON_MASK 0x00000001L
+-#define DSI1_DISP_DSI_CLK_CTRL__DISPCLK_R_ON_MASK 0x00000002L
+-#define DSI1_DISP_DSI_CLK_CTRL__DSICLK_G_ON_MASK 0x00000010L
+-#define DSI1_DISP_DSI_CLK_CTRL__DSICLK_R_ON_MASK 0x00000020L
+-#define DSI1_DISP_DSI_CLK_CTRL__DSICLK_TRN_ON_MASK 0x00000040L
+-#define DSI1_DISP_DSI_CLK_CTRL__BYTECLK_G_ON_MASK 0x00000100L
+-#define DSI1_DISP_DSI_CLK_CTRL__ESCCLK_G_ON_MASK 0x00010000L
+-#define DSI1_DISP_DSI_CLK_CTRL__TEST_CLK_SEL_MASK 0x0F000000L
+-//DSI1_DISP_DSI_CLK_STATUS
+-#define DSI1_DISP_DSI_CLK_STATUS__DISPCLK_R_ACTIVE__SHIFT 0x0
+-#define DSI1_DISP_DSI_CLK_STATUS__DISPCLK_G_ACTIVE__SHIFT 0x1
+-#define DSI1_DISP_DSI_CLK_STATUS__DSICLK_R_ACTIVE__SHIFT 0x4
+-#define DSI1_DISP_DSI_CLK_STATUS__DSICLK_G_ACTIVE__SHIFT 0x5
+-#define DSI1_DISP_DSI_CLK_STATUS__DSICLK_TRN_ACTIVE__SHIFT 0x6
+-#define DSI1_DISP_DSI_CLK_STATUS__BYTECLK_G_ACTIVE__SHIFT 0x8
+-#define DSI1_DISP_DSI_CLK_STATUS__ESCCLK_G_ACTIVE__SHIFT 0x10
+-#define DSI1_DISP_DSI_CLK_STATUS__DISPCLK_R_ACTIVE_MASK 0x00000001L
+-#define DSI1_DISP_DSI_CLK_STATUS__DISPCLK_G_ACTIVE_MASK 0x00000002L
+-#define DSI1_DISP_DSI_CLK_STATUS__DSICLK_R_ACTIVE_MASK 0x00000010L
+-#define DSI1_DISP_DSI_CLK_STATUS__DSICLK_G_ACTIVE_MASK 0x00000020L
+-#define DSI1_DISP_DSI_CLK_STATUS__DSICLK_TRN_ACTIVE_MASK 0x00000040L
+-#define DSI1_DISP_DSI_CLK_STATUS__BYTECLK_G_ACTIVE_MASK 0x00000100L
+-#define DSI1_DISP_DSI_CLK_STATUS__ESCCLK_G_ACTIVE_MASK 0x00010000L
+-//DSI1_DISP_DSI_DENG_FIFO_STATUS
+-#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_LEVEL_ERROR__SHIFT 0x0
+-#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
+-#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
+-#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_ERROR_ACK__SHIFT 0x9
+-#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
+-#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_MAXIMUM_LEVEL__SHIFT 0x11
+-#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_MINIMUM_LEVEL__SHIFT 0x17
+-#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_CALIBRATED__SHIFT 0x1d
+-#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
+-#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
+-#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_LEVEL_ERROR_MASK 0x00000001L
+-#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L
+-#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_OVERWRITE_LEVEL_MASK 0x000001FCL
+-#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_ERROR_ACK_MASK 0x00000200L
+-#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0001FC00L
+-#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_MAXIMUM_LEVEL_MASK 0x007E0000L
+-#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_MINIMUM_LEVEL_MASK 0x0F800000L
+-#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_CALIBRATED_MASK 0x20000000L
+-#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L
+-#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L
+-//DSI1_DISP_DSI_DENG_FIFO_CTRL
+-#define DSI1_DISP_DSI_DENG_FIFO_CTRL__DENG_FIFO_EN__SHIFT 0x0
+-#define DSI1_DISP_DSI_DENG_FIFO_CTRL__DENG_FIFO_START__SHIFT 0x4
+-#define DSI1_DISP_DSI_DENG_FIFO_CTRL__DENG_DSICLK_ON__SHIFT 0x8
+-#define DSI1_DISP_DSI_DENG_FIFO_CTRL__DENG_FIFO_EN_MASK 0x00000001L
+-#define DSI1_DISP_DSI_DENG_FIFO_CTRL__DENG_FIFO_START_MASK 0x00000010L
+-#define DSI1_DISP_DSI_DENG_FIFO_CTRL__DENG_DSICLK_ON_MASK 0x00000100L
+-//DSI1_DISP_DSI_CMD_FIFO_DATA
+-#define DSI1_DISP_DSI_CMD_FIFO_DATA__CMDFIFO_DATA__SHIFT 0x0
+-#define DSI1_DISP_DSI_CMD_FIFO_DATA__CMDFIFO_DATA_MASK 0xFFFFFFFFL
+-//DSI1_DISP_DSI_CMD_FIFO_CTRL
+-#define DSI1_DISP_DSI_CMD_FIFO_CTRL__USE_CMDFIFO__SHIFT 0x0
+-#define DSI1_DISP_DSI_CMD_FIFO_CTRL__CMDFIFO_DW_LEVEL__SHIFT 0x4
+-#define DSI1_DISP_DSI_CMD_FIFO_CTRL__USE_CMDFIFO_MASK 0x00000001L
+-#define DSI1_DISP_DSI_CMD_FIFO_CTRL__CMDFIFO_DW_LEVEL_MASK 0x000007F0L
+-//DSI1_DISP_DSI_TE_CTRL
+-#define DSI1_DISP_DSI_TE_CTRL__FREEZE_CRTC_HYSTERESIS__SHIFT 0x0
+-#define DSI1_DISP_DSI_TE_CTRL__DISABLE_CRTC_FREEZE__SHIFT 0x10
+-#define DSI1_DISP_DSI_TE_CTRL__DISABLE_CRTC_FORCE__SHIFT 0x14
+-#define DSI1_DISP_DSI_TE_CTRL__CRTC_FREEZE__SHIFT 0x18
+-#define DSI1_DISP_DSI_TE_CTRL__CRTC_FREEZE_TRIG__SHIFT 0x18
+-#define DSI1_DISP_DSI_TE_CTRL__FREEZE_CRTC_HYSTERESIS_MASK 0x00000FFFL
+-#define DSI1_DISP_DSI_TE_CTRL__DISABLE_CRTC_FREEZE_MASK 0x00010000L
+-#define DSI1_DISP_DSI_TE_CTRL__DISABLE_CRTC_FORCE_MASK 0x00100000L
+-#define DSI1_DISP_DSI_TE_CTRL__CRTC_FREEZE_MASK 0x01000000L
+-#define DSI1_DISP_DSI_TE_CTRL__CRTC_FREEZE_TRIG_MASK 0x01000000L
+-//DSI1_DISP_DSI_LANE_STATUS
+-#define DSI1_DISP_DSI_LANE_STATUS__DLN0_STOPSTATE__SHIFT 0x0
+-#define DSI1_DISP_DSI_LANE_STATUS__DLN1_STOPSTATE__SHIFT 0x1
+-#define DSI1_DISP_DSI_LANE_STATUS__DLN2_STOPSTATE__SHIFT 0x2
+-#define DSI1_DISP_DSI_LANE_STATUS__DLN3_STOPSTATE__SHIFT 0x3
+-#define DSI1_DISP_DSI_LANE_STATUS__DLN0_ULPS_ACTIVE_NOT__SHIFT 0x4
+-#define DSI1_DISP_DSI_LANE_STATUS__DLN1_ULPS_ACTIVE_NOT__SHIFT 0x5
+-#define DSI1_DISP_DSI_LANE_STATUS__DLN2_ULPS_ACTIVE_NOT__SHIFT 0x6
+-#define DSI1_DISP_DSI_LANE_STATUS__DLN3_ULPS_ACTIVE_NOT__SHIFT 0x7
+-#define DSI1_DISP_DSI_LANE_STATUS__DLN0_DIRECTION__SHIFT 0x8
+-#define DSI1_DISP_DSI_LANE_STATUS__CLKLN_STOPSTATE__SHIFT 0x18
+-#define DSI1_DISP_DSI_LANE_STATUS__CLKLN_ULPS_ACTIVE_NOT__SHIFT 0x1c
+-#define DSI1_DISP_DSI_LANE_STATUS__DLN0_STOPSTATE_MASK 0x00000001L
+-#define DSI1_DISP_DSI_LANE_STATUS__DLN1_STOPSTATE_MASK 0x00000002L
+-#define DSI1_DISP_DSI_LANE_STATUS__DLN2_STOPSTATE_MASK 0x00000004L
+-#define DSI1_DISP_DSI_LANE_STATUS__DLN3_STOPSTATE_MASK 0x00000008L
+-#define DSI1_DISP_DSI_LANE_STATUS__DLN0_ULPS_ACTIVE_NOT_MASK 0x00000010L
+-#define DSI1_DISP_DSI_LANE_STATUS__DLN1_ULPS_ACTIVE_NOT_MASK 0x00000020L
+-#define DSI1_DISP_DSI_LANE_STATUS__DLN2_ULPS_ACTIVE_NOT_MASK 0x00000040L
+-#define DSI1_DISP_DSI_LANE_STATUS__DLN3_ULPS_ACTIVE_NOT_MASK 0x00000080L
+-#define DSI1_DISP_DSI_LANE_STATUS__DLN0_DIRECTION_MASK 0x00000100L
+-#define DSI1_DISP_DSI_LANE_STATUS__CLKLN_STOPSTATE_MASK 0x01000000L
+-#define DSI1_DISP_DSI_LANE_STATUS__CLKLN_ULPS_ACTIVE_NOT_MASK 0x10000000L
+-//DSI1_DISP_DSI_PERF_CTRL
+-#define DSI1_DISP_DSI_PERF_CTRL__PERF_LP_HS_LATENCY_SEL__SHIFT 0x0
+-#define DSI1_DISP_DSI_PERF_CTRL__PERF_HS_LP_LATENCY_SEL__SHIFT 0x4
+-#define DSI1_DISP_DSI_PERF_CTRL__PERF_LP_HS_LATENCY_SEL_MASK 0x00000003L
+-#define DSI1_DISP_DSI_PERF_CTRL__PERF_HS_LP_LATENCY_SEL_MASK 0x00000030L
+-//DSI1_DISP_DSI_HSYNC_LENGTH
+-#define DSI1_DISP_DSI_HSYNC_LENGTH__HSYNC_LENGTH_MAX__SHIFT 0x0
+-#define DSI1_DISP_DSI_HSYNC_LENGTH__HSYNC_LENGTH_MIN__SHIFT 0x10
+-#define DSI1_DISP_DSI_HSYNC_LENGTH__HSYNC_LENGTH_MAX_MASK 0x0000FFFFL
+-#define DSI1_DISP_DSI_HSYNC_LENGTH__HSYNC_LENGTH_MIN_MASK 0xFFFF0000L
+-//DSI1_DISP_DSI_RDBK_NUM
+-#define DSI1_DISP_DSI_RDBK_NUM__RD_NUM__SHIFT 0x0
+-#define DSI1_DISP_DSI_RDBK_NUM__ALL_NUM__SHIFT 0x10
+-#define DSI1_DISP_DSI_RDBK_NUM__RD_NUM_MASK 0x0000FFFFL
+-#define DSI1_DISP_DSI_RDBK_NUM__ALL_NUM_MASK 0xFFFF0000L
+-//DSI1_DISP_DSI_CMD_MEM_PWR_CTRL
+-#define DSI1_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_DIS__SHIFT 0x0
+-#define DSI1_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_FORCE__SHIFT 0x4
+-#define DSI1_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_STATE__SHIFT 0x8
+-#define DSI1_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_MODE_SEL__SHIFT 0xc
+-#define DSI1_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_DIS_MASK 0x00000001L
+-#define DSI1_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_FORCE_MASK 0x00000030L
+-#define DSI1_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_STATE_MASK 0x00000300L
+-#define DSI1_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_MODE_SEL_MASK 0x00003000L
+-
+-
+-// addressBlock: dce_dc_dprx_sd0_dispdec
+-//DPRX_SD0_DPRX_SD_CONTROL
+-#define DPRX_SD0_DPRX_SD_CONTROL__SD_ENABLE__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_CONTROL__SD_RESET__SHIFT 0x4
+-#define DPRX_SD0_DPRX_SD_CONTROL__SD_CLOCK_ENABLE__SHIFT 0x8
+-#define DPRX_SD0_DPRX_SD_CONTROL__SD_CLOCK_ON__SHIFT 0xc
+-#define DPRX_SD0_DPRX_SD_CONTROL__SD_ENABLE_MASK 0x00000001L
+-#define DPRX_SD0_DPRX_SD_CONTROL__SD_RESET_MASK 0x00000010L
+-#define DPRX_SD0_DPRX_SD_CONTROL__SD_CLOCK_ENABLE_MASK 0x00000100L
+-#define DPRX_SD0_DPRX_SD_CONTROL__SD_CLOCK_ON_MASK 0x00001000L
+-//DPRX_SD0_DPRX_SD_STREAM_ENABLE
+-#define DPRX_SD0_DPRX_SD_STREAM_ENABLE__VID_STREAM_ENABLE__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_STREAM_ENABLE__VID_STREAM_STATUS__SHIFT 0x8
+-#define DPRX_SD0_DPRX_SD_STREAM_ENABLE__VID_STREAM_ENABLE_MASK 0x00000001L
+-#define DPRX_SD0_DPRX_SD_STREAM_ENABLE__VID_STREAM_STATUS_MASK 0x00000100L
+-//DPRX_SD0_DPRX_SD_MSA0
+-#define DPRX_SD0_DPRX_SD_MSA0__MSA0__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_MSA0__MSA0_MASK 0xFFFFFFFFL
+-//DPRX_SD0_DPRX_SD_MSA1
+-#define DPRX_SD0_DPRX_SD_MSA1__MSA1__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_MSA1__MSA1_MASK 0xFFFFFFFFL
+-//DPRX_SD0_DPRX_SD_MSA2
+-#define DPRX_SD0_DPRX_SD_MSA2__MSA2__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_MSA2__MSA2_MASK 0xFFFFFFFFL
+-//DPRX_SD0_DPRX_SD_MSA3
+-#define DPRX_SD0_DPRX_SD_MSA3__MSA3__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_MSA3__MSA3_MASK 0xFFFFFFFFL
+-//DPRX_SD0_DPRX_SD_MSA4
+-#define DPRX_SD0_DPRX_SD_MSA4__MSA4__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_MSA4__MSA4_MASK 0xFFFFFFFFL
+-//DPRX_SD0_DPRX_SD_MSA5
+-#define DPRX_SD0_DPRX_SD_MSA5__MSA5__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_MSA5__MSA5_MASK 0xFFFFFFFFL
+-//DPRX_SD0_DPRX_SD_MSA6
+-#define DPRX_SD0_DPRX_SD_MSA6__MSA6__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_MSA6__MSA6_MASK 0xFFFFFFFFL
+-//DPRX_SD0_DPRX_SD_MSA7
+-#define DPRX_SD0_DPRX_SD_MSA7__MSA7__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_MSA7__MSA7_MASK 0xFFFFFFFFL
+-//DPRX_SD0_DPRX_SD_MSA8
+-#define DPRX_SD0_DPRX_SD_MSA8__MSA8__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_MSA8__MSA8_MASK 0xFFFFFFFFL
+-//DPRX_SD0_DPRX_SD_VBID
+-#define DPRX_SD0_DPRX_SD_VBID__VBID__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_VBID__VBID_MASK 0x000000FFL
+-//DPRX_SD0_DPRX_SD_CURRENT_LINE
+-#define DPRX_SD0_DPRX_SD_CURRENT_LINE__CURRENT_LINE__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_CURRENT_LINE__CURRENT_FRAME__SHIFT 0x10
+-#define DPRX_SD0_DPRX_SD_CURRENT_LINE__CURRENT_LINE_MASK 0x0000FFFFL
+-#define DPRX_SD0_DPRX_SD_CURRENT_LINE__CURRENT_FRAME_MASK 0x00FF0000L
+-//DPRX_SD0_DPRX_SD_DISPLAY_TIMER_SNAPSHOT
+-#define DPRX_SD0_DPRX_SD_DISPLAY_TIMER_SNAPSHOT__DISPLAY_TIMER_SNAPSHOT__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_DISPLAY_TIMER_SNAPSHOT__DISPLAY_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+-//DPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE
+-#define DPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE__DISPLAY_TIMER_MODE__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE__DISPLAY_TIMER_UPDATE_LOCKED__SHIFT 0x8
+-#define DPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE__DISPLAY_TIMER_MODE_MASK 0x00000001L
+-#define DPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE__DISPLAY_TIMER_UPDATE_LOCKED_MASK 0x00000100L
+-//DPRX_SD0_DPRX_SD_MSE_SAT
+-#define DPRX_SD0_DPRX_SD_MSE_SAT__MSE_SAT_SLOT_START__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_MSE_SAT__MSE_SAT_SLOT_END__SHIFT 0x8
+-#define DPRX_SD0_DPRX_SD_MSE_SAT__MSE_SAT_SLOT_START_MASK 0x0000003FL
+-#define DPRX_SD0_DPRX_SD_MSE_SAT__MSE_SAT_SLOT_END_MASK 0x00003F00L
+-//DPRX_SD0_DPRX_SD_MSE_FORCE_UPDATE
+-#define DPRX_SD0_DPRX_SD_MSE_FORCE_UPDATE__MSE_SAT_FORCE_UPDATE__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_MSE_FORCE_UPDATE__MSE_SAT_FORCE_UPDATE_MASK 0x00000001L
+-//DPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE
+-#define DPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE__MSE_SAT_SLOT_START_ACTIVE__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE__MSE_SAT_SLOT_END_ACTIVE__SHIFT 0x8
+-#define DPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE__MSE_SAT_SLOT_START_ACTIVE_MASK 0x0000003FL
+-#define DPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE__MSE_SAT_SLOT_END_ACTIVE_MASK 0x00003F00L
+-//DPRX_SD0_DPRX_SD_V_PARAMETER
+-#define DPRX_SD0_DPRX_SD_V_PARAMETER__V_BLANK_HEIGHT__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_V_PARAMETER__V_BLANK_HEIGHT_MASK 0x0000FFFFL
+-//DPRX_SD0_DPRX_SD_PIXEL_FORMAT
+-#define DPRX_SD0_DPRX_SD_PIXEL_FORMAT__PIXEL_ENCODING__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_PIXEL_FORMAT__COMPONENT_DEPTH__SHIFT 0x8
+-#define DPRX_SD0_DPRX_SD_PIXEL_FORMAT__PIXEL_ENCODING_MASK 0x00000003L
+-#define DPRX_SD0_DPRX_SD_PIXEL_FORMAT__COMPONENT_DEPTH_MASK 0x00000700L
+-//DPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS
+-#define DPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_FLAG__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_ACK__SHIFT 0x4
+-#define DPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_MASK__SHIFT 0x8
+-#define DPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_FLAG_MASK 0x00000001L
+-#define DPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_ACK_MASK 0x00000010L
+-#define DPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_MASK_MASK 0x00000100L
+-//DPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED
+-#define DPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_FLAG__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_ACK__SHIFT 0x4
+-#define DPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_MASK__SHIFT 0x8
+-#define DPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_FLAG_MASK 0x00000001L
+-#define DPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_ACK_MASK 0x00000010L
+-#define DPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_MASK_MASK 0x00000100L
+-//DPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS
+-#define DPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_FLAG__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_ACK__SHIFT 0x4
+-#define DPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_MASK__SHIFT 0x8
+-#define DPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_TYPE__SHIFT 0xc
+-#define DPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_FLAG_MASK 0x00000001L
+-#define DPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_ACK_MASK 0x00000010L
+-#define DPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_MASK_MASK 0x00000100L
+-#define DPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_TYPE_MASK 0x00001000L
+-//DPRX_SD0_DPRX_SD_LINE_NUMBER0_CONTROL
+-#define DPRX_SD0_DPRX_SD_LINE_NUMBER0_CONTROL__LINE_NUMBER0_INTERRUPT__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_LINE_NUMBER0_CONTROL__LINE_NUMBER0_INTERRUPT_MASK 0x0000FFFFL
+-//DPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS
+-#define DPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_FLAG__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_ACK__SHIFT 0x4
+-#define DPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_MASK__SHIFT 0x8
+-#define DPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_TYPE__SHIFT 0xc
+-#define DPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_FLAG_MASK 0x00000001L
+-#define DPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_ACK_MASK 0x00000010L
+-#define DPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_MASK_MASK 0x00000100L
+-#define DPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_TYPE_MASK 0x00001000L
+-//DPRX_SD0_DPRX_SD_LINE_NUMBER1_CONTROL
+-#define DPRX_SD0_DPRX_SD_LINE_NUMBER1_CONTROL__LINE_NUMBER1_INTERRUPT__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_LINE_NUMBER1_CONTROL__LINE_NUMBER1_INTERRUPT_MASK 0x0000FFFFL
+-//DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR
+-#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__BS1_ERROR__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__VBID_ERROR__SHIFT 0x1
+-#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__MVID_ERROR__SHIFT 0x2
+-#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__MAUD_ERROR__SHIFT 0x3
+-#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__IDLE_ERROR__SHIFT 0x4
+-#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__BE_BS_ERROR__SHIFT 0x5
+-#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__BE_OTHER_ERROR__SHIFT 0x6
+-#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__PIX_ERROR__SHIFT 0x7
+-#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FS_BS_ERROR__SHIFT 0x8
+-#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FS_OTHER_ERROR__SHIFT 0x9
+-#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FILL_BS_ERROR__SHIFT 0xa
+-#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FILL_OTHER_ERROR__SHIFT 0xb
+-#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FE_BS_ERROR__SHIFT 0xc
+-#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FE_OTHER_ERROR__SHIFT 0xd
+-#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FILTER_BE_ERROR__SHIFT 0xe
+-#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__BS1_ERROR_MASK 0x00000001L
+-#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__VBID_ERROR_MASK 0x00000002L
+-#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__MVID_ERROR_MASK 0x00000004L
+-#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__MAUD_ERROR_MASK 0x00000008L
+-#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__IDLE_ERROR_MASK 0x00000010L
+-#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__BE_BS_ERROR_MASK 0x00000020L
+-#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__BE_OTHER_ERROR_MASK 0x00000040L
+-#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__PIX_ERROR_MASK 0x00000080L
+-#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FS_BS_ERROR_MASK 0x00000100L
+-#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FS_OTHER_ERROR_MASK 0x00000200L
+-#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FILL_BS_ERROR_MASK 0x00000400L
+-#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FILL_OTHER_ERROR_MASK 0x00000800L
+-#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FE_BS_ERROR_MASK 0x00001000L
+-#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FE_OTHER_ERROR_MASK 0x00002000L
+-#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FILTER_BE_ERROR_MASK 0x00004000L
+-//DPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE
+-#define DPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_1_ERROR__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_2_ERROR__SHIFT 0x1
+-#define DPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_FAIL__SHIFT 0x2
+-#define DPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_1_ERROR_MASK 0x00000001L
+-#define DPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_2_ERROR_MASK 0x00000002L
+-#define DPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_FAIL_MASK 0x00000004L
+-//DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR
+-#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_MSA_SS0_ERROR__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_MSA_SS1_ERROR__SHIFT 0x1
+-#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_MSA_DATA_ERROR__SHIFT 0x2
+-#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_EXPIRE_ERROR__SHIFT 0x4
+-#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_SE_ILLEGAL_SE_ERROR__SHIFT 0x5
+-#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_ERROR__SHIFT 0x6
+-#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SS1_ERROR__SHIFT 0x8
+-#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SS2_ERROR__SHIFT 0x9
+-#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_DATA_ERROR__SHIFT 0xa
+-#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_EXPIRE_ERROR__SHIFT 0xb
+-#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_ILLEGAL_SE_ERROR__SHIFT 0xc
+-#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_ERROR__SHIFT 0xd
+-#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_MSA_SS0_ERROR_MASK 0x00000001L
+-#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_MSA_SS1_ERROR_MASK 0x00000002L
+-#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_MSA_DATA_ERROR_MASK 0x00000004L
+-#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_EXPIRE_ERROR_MASK 0x00000010L
+-#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_SE_ILLEGAL_SE_ERROR_MASK 0x00000020L
+-#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_ERROR_MASK 0x00000040L
+-#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SS1_ERROR_MASK 0x00000100L
+-#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SS2_ERROR_MASK 0x00000200L
+-#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_DATA_ERROR_MASK 0x00000400L
+-#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_EXPIRE_ERROR_MASK 0x00000800L
+-#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_ILLEGAL_SE_ERROR_MASK 0x00001000L
+-#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_ERROR_MASK 0x00002000L
+-//DPRX_SD0_DPRX_SD_VCPF_PHASE_LOCKED
+-#define DPRX_SD0_DPRX_SD_VCPF_PHASE_LOCKED__VCPF_PHASE_LOCKED__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_VCPF_PHASE_LOCKED__VCPF_PHASE_LOCKED_MASK 0x00000001L
+-//DPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR
+-#define DPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR__VCPF_PHASE_ERROR__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR__VCPF_1_SYMBOL_ERROR__SHIFT 0x1
+-#define DPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR__VCPF_2_SYMBOL_ERROR__SHIFT 0x2
+-#define DPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR__VCPF_PHASE_ERROR_MASK 0x00000001L
+-#define DPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR__VCPF_1_SYMBOL_ERROR_MASK 0x00000002L
+-#define DPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR__VCPF_2_SYMBOL_ERROR_MASK 0x00000004L
+-//DPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR
+-#define DPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR__CORRECTED_CONTROL_SEQUENCE_ERROR__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR__CORRECTED_DATA_SEQUENCE_ERROR__SHIFT 0x8
+-#define DPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR__CORRECTED_CONTROL_SEQUENCE_ERROR_MASK 0x00000001L
+-#define DPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR__CORRECTED_DATA_SEQUENCE_ERROR_MASK 0x00000100L
+-//DPRX_SD0_DPRX_SD_PIXEL_FIFO_ERROR
+-#define DPRX_SD0_DPRX_SD_PIXEL_FIFO_ERROR__PIXEL_FIFO_OVERFLOW_ERROR__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_PIXEL_FIFO_ERROR__PIXEL_FIFO_OVERFLOW_ERROR_MASK 0x00000001L
+-//DPRX_SD0_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH
+-#define DPRX_SD0_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH__MAXIMUM_SDP_PAYLOAD_LENGTH__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH__MAXIMUM_SDP_PAYLOAD_LENGTH_MASK 0x000003FFL
+-//DPRX_SD0_DPRX_SD_SDP_STEER
+-#define DPRX_SD0_DPRX_SD_SDP_STEER__FILTER_AUDIO_TIMESTAMP_SDP_EN__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_SDP_STEER__FILTER_AUDIO_TIMESTAMP_SDP_EN_MASK 0x00000001L
+-//DPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS
+-#define DPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_FLAG__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_ACK__SHIFT 0x4
+-#define DPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_MASK__SHIFT 0x8
+-#define DPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_FLAG_MASK 0x00000001L
+-#define DPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_ACK_MASK 0x00000010L
+-#define DPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_MASK_MASK 0x00000100L
+-//DPRX_SD0_DPRX_SD_SDP_LEVEL
+-#define DPRX_SD0_DPRX_SD_SDP_LEVEL__SDP_FIFO_LEVEL__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_SDP_LEVEL__SDP_CURRENT_SLICE__SHIFT 0x8
+-#define DPRX_SD0_DPRX_SD_SDP_LEVEL__SDP_FIFO_LEVEL_MASK 0x0000001FL
+-#define DPRX_SD0_DPRX_SD_SDP_LEVEL__SDP_CURRENT_SLICE_MASK 0x00000F00L
+-//DPRX_SD0_DPRX_SD_SDP_DATA
+-#define DPRX_SD0_DPRX_SD_SDP_DATA__SDP_DATA__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_SDP_DATA__SDP_DATA_MASK 0xFFFFFFFFL
+-//DPRX_SD0_DPRX_SD_SDP_ERROR
+-#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_FIFO_OVERFLOW_ERROR__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_HEADER_ERROR__SHIFT 0x1
+-#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_NON_AUDIO_PAYLOAD_ERROR__SHIFT 0x2
+-#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_NON_AUDIO_LENGTH_ERROR__SHIFT 0x3
+-#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_RS_CORRECTED_ERROR__SHIFT 0x4
+-#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_RS_UNCORRECTABLE_ERROR__SHIFT 0x5
+-#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_AUDIO_PAYLOAD_ERROR__SHIFT 0x6
+-#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_FIFO_OVERFLOW_ERROR_MASK 0x00000001L
+-#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_HEADER_ERROR_MASK 0x00000002L
+-#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_NON_AUDIO_PAYLOAD_ERROR_MASK 0x00000004L
+-#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_NON_AUDIO_LENGTH_ERROR_MASK 0x00000008L
+-#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_RS_CORRECTED_ERROR_MASK 0x00000010L
+-#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_RS_UNCORRECTABLE_ERROR_MASK 0x00000020L
+-#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_AUDIO_PAYLOAD_ERROR_MASK 0x00000040L
+-//DPRX_SD0_DPRX_SD_AUDIO_HEADER
+-#define DPRX_SD0_DPRX_SD_AUDIO_HEADER__AUDIO_HEADER__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_AUDIO_HEADER__AUDIO_HEADER_MASK 0xFFFFFFFFL
+-//DPRX_SD0_DPRX_SD_AUDIO_FIFO_ERROR
+-#define DPRX_SD0_DPRX_SD_AUDIO_FIFO_ERROR__AUDIO_FIFO_OVERFLOW_ERROR__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_AUDIO_FIFO_ERROR__AUDIO_FIFO_OVERFLOW_ERROR_MASK 0x00000001L
+-//DPRX_SD0_DPRX_SD_SDP_CONTROL
+-#define DPRX_SD0_DPRX_SD_SDP_CONTROL__RS_DECODER_ENABLE__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_SDP_CONTROL__RS_ERROR_CORRECTION_ENABLE__SHIFT 0x4
+-#define DPRX_SD0_DPRX_SD_SDP_CONTROL__RS_DECODER_ENABLE_MASK 0x00000001L
+-#define DPRX_SD0_DPRX_SD_SDP_CONTROL__RS_ERROR_CORRECTION_ENABLE_MASK 0x00000010L
+-//DPRX_SD0_DPRX_SD_V_TOTAL_MEASURED
+-#define DPRX_SD0_DPRX_SD_V_TOTAL_MEASURED__V_ACTIVE_LINE_TOTAL__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_V_TOTAL_MEASURED__V_LINE_TOTAL__SHIFT 0x10
+-#define DPRX_SD0_DPRX_SD_V_TOTAL_MEASURED__V_ACTIVE_LINE_TOTAL_MASK 0x0000FFFFL
+-#define DPRX_SD0_DPRX_SD_V_TOTAL_MEASURED__V_LINE_TOTAL_MASK 0xFFFF0000L
+-//DPRX_SD0_DPRX_SD_H_TOTAL_MEASURED
+-#define DPRX_SD0_DPRX_SD_H_TOTAL_MEASURED__H_ACTIVE_SYMBOL_TOTAL__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_H_TOTAL_MEASURED__H_ACTIVE_SYMBOL_TOTAL_MASK 0x0000FFFFL
+-//DPRX_SD0_DPRX_SD_BS_COUNTER
+-#define DPRX_SD0_DPRX_SD_BS_COUNTER__BS_COUNTER__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_BS_COUNTER__BS_COUNTER_MASK 0x000003FFL
+-//DPRX_SD0_DPRX_SD_MSE_ACT_HANDLED
+-#define DPRX_SD0_DPRX_SD_MSE_ACT_HANDLED__MSE_ACT_HANDLED__SHIFT 0x0
+-#define DPRX_SD0_DPRX_SD_MSE_ACT_HANDLED__MSE_ACT_HANDLED_MASK 0x00000001L
+-
+-
+-// addressBlock: dce_dc_dprx_sd1_dispdec
+-//DPRX_SD1_DPRX_SD_CONTROL
+-#define DPRX_SD1_DPRX_SD_CONTROL__SD_ENABLE__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_CONTROL__SD_RESET__SHIFT 0x4
+-#define DPRX_SD1_DPRX_SD_CONTROL__SD_CLOCK_ENABLE__SHIFT 0x8
+-#define DPRX_SD1_DPRX_SD_CONTROL__SD_CLOCK_ON__SHIFT 0xc
+-#define DPRX_SD1_DPRX_SD_CONTROL__SD_ENABLE_MASK 0x00000001L
+-#define DPRX_SD1_DPRX_SD_CONTROL__SD_RESET_MASK 0x00000010L
+-#define DPRX_SD1_DPRX_SD_CONTROL__SD_CLOCK_ENABLE_MASK 0x00000100L
+-#define DPRX_SD1_DPRX_SD_CONTROL__SD_CLOCK_ON_MASK 0x00001000L
+-//DPRX_SD1_DPRX_SD_STREAM_ENABLE
+-#define DPRX_SD1_DPRX_SD_STREAM_ENABLE__VID_STREAM_ENABLE__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_STREAM_ENABLE__VID_STREAM_STATUS__SHIFT 0x8
+-#define DPRX_SD1_DPRX_SD_STREAM_ENABLE__VID_STREAM_ENABLE_MASK 0x00000001L
+-#define DPRX_SD1_DPRX_SD_STREAM_ENABLE__VID_STREAM_STATUS_MASK 0x00000100L
+-//DPRX_SD1_DPRX_SD_MSA0
+-#define DPRX_SD1_DPRX_SD_MSA0__MSA0__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_MSA0__MSA0_MASK 0xFFFFFFFFL
+-//DPRX_SD1_DPRX_SD_MSA1
+-#define DPRX_SD1_DPRX_SD_MSA1__MSA1__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_MSA1__MSA1_MASK 0xFFFFFFFFL
+-//DPRX_SD1_DPRX_SD_MSA2
+-#define DPRX_SD1_DPRX_SD_MSA2__MSA2__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_MSA2__MSA2_MASK 0xFFFFFFFFL
+-//DPRX_SD1_DPRX_SD_MSA3
+-#define DPRX_SD1_DPRX_SD_MSA3__MSA3__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_MSA3__MSA3_MASK 0xFFFFFFFFL
+-//DPRX_SD1_DPRX_SD_MSA4
+-#define DPRX_SD1_DPRX_SD_MSA4__MSA4__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_MSA4__MSA4_MASK 0xFFFFFFFFL
+-//DPRX_SD1_DPRX_SD_MSA5
+-#define DPRX_SD1_DPRX_SD_MSA5__MSA5__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_MSA5__MSA5_MASK 0xFFFFFFFFL
+-//DPRX_SD1_DPRX_SD_MSA6
+-#define DPRX_SD1_DPRX_SD_MSA6__MSA6__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_MSA6__MSA6_MASK 0xFFFFFFFFL
+-//DPRX_SD1_DPRX_SD_MSA7
+-#define DPRX_SD1_DPRX_SD_MSA7__MSA7__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_MSA7__MSA7_MASK 0xFFFFFFFFL
+-//DPRX_SD1_DPRX_SD_MSA8
+-#define DPRX_SD1_DPRX_SD_MSA8__MSA8__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_MSA8__MSA8_MASK 0xFFFFFFFFL
+-//DPRX_SD1_DPRX_SD_VBID
+-#define DPRX_SD1_DPRX_SD_VBID__VBID__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_VBID__VBID_MASK 0x000000FFL
+-//DPRX_SD1_DPRX_SD_CURRENT_LINE
+-#define DPRX_SD1_DPRX_SD_CURRENT_LINE__CURRENT_LINE__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_CURRENT_LINE__CURRENT_FRAME__SHIFT 0x10
+-#define DPRX_SD1_DPRX_SD_CURRENT_LINE__CURRENT_LINE_MASK 0x0000FFFFL
+-#define DPRX_SD1_DPRX_SD_CURRENT_LINE__CURRENT_FRAME_MASK 0x00FF0000L
+-//DPRX_SD1_DPRX_SD_DISPLAY_TIMER_SNAPSHOT
+-#define DPRX_SD1_DPRX_SD_DISPLAY_TIMER_SNAPSHOT__DISPLAY_TIMER_SNAPSHOT__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_DISPLAY_TIMER_SNAPSHOT__DISPLAY_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+-//DPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE
+-#define DPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE__DISPLAY_TIMER_MODE__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE__DISPLAY_TIMER_UPDATE_LOCKED__SHIFT 0x8
+-#define DPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE__DISPLAY_TIMER_MODE_MASK 0x00000001L
+-#define DPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE__DISPLAY_TIMER_UPDATE_LOCKED_MASK 0x00000100L
+-//DPRX_SD1_DPRX_SD_MSE_SAT
+-#define DPRX_SD1_DPRX_SD_MSE_SAT__MSE_SAT_SLOT_START__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_MSE_SAT__MSE_SAT_SLOT_END__SHIFT 0x8
+-#define DPRX_SD1_DPRX_SD_MSE_SAT__MSE_SAT_SLOT_START_MASK 0x0000003FL
+-#define DPRX_SD1_DPRX_SD_MSE_SAT__MSE_SAT_SLOT_END_MASK 0x00003F00L
+-//DPRX_SD1_DPRX_SD_MSE_FORCE_UPDATE
+-#define DPRX_SD1_DPRX_SD_MSE_FORCE_UPDATE__MSE_SAT_FORCE_UPDATE__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_MSE_FORCE_UPDATE__MSE_SAT_FORCE_UPDATE_MASK 0x00000001L
+-//DPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE
+-#define DPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE__MSE_SAT_SLOT_START_ACTIVE__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE__MSE_SAT_SLOT_END_ACTIVE__SHIFT 0x8
+-#define DPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE__MSE_SAT_SLOT_START_ACTIVE_MASK 0x0000003FL
+-#define DPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE__MSE_SAT_SLOT_END_ACTIVE_MASK 0x00003F00L
+-//DPRX_SD1_DPRX_SD_V_PARAMETER
+-#define DPRX_SD1_DPRX_SD_V_PARAMETER__V_BLANK_HEIGHT__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_V_PARAMETER__V_BLANK_HEIGHT_MASK 0x0000FFFFL
+-//DPRX_SD1_DPRX_SD_PIXEL_FORMAT
+-#define DPRX_SD1_DPRX_SD_PIXEL_FORMAT__PIXEL_ENCODING__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_PIXEL_FORMAT__COMPONENT_DEPTH__SHIFT 0x8
+-#define DPRX_SD1_DPRX_SD_PIXEL_FORMAT__PIXEL_ENCODING_MASK 0x00000003L
+-#define DPRX_SD1_DPRX_SD_PIXEL_FORMAT__COMPONENT_DEPTH_MASK 0x00000700L
+-//DPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS
+-#define DPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_FLAG__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_ACK__SHIFT 0x4
+-#define DPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_MASK__SHIFT 0x8
+-#define DPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_FLAG_MASK 0x00000001L
+-#define DPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_ACK_MASK 0x00000010L
+-#define DPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_MASK_MASK 0x00000100L
+-//DPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED
+-#define DPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_FLAG__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_ACK__SHIFT 0x4
+-#define DPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_MASK__SHIFT 0x8
+-#define DPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_FLAG_MASK 0x00000001L
+-#define DPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_ACK_MASK 0x00000010L
+-#define DPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_MASK_MASK 0x00000100L
+-//DPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS
+-#define DPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_FLAG__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_ACK__SHIFT 0x4
+-#define DPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_MASK__SHIFT 0x8
+-#define DPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_TYPE__SHIFT 0xc
+-#define DPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_FLAG_MASK 0x00000001L
+-#define DPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_ACK_MASK 0x00000010L
+-#define DPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_MASK_MASK 0x00000100L
+-#define DPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_TYPE_MASK 0x00001000L
+-//DPRX_SD1_DPRX_SD_LINE_NUMBER0_CONTROL
+-#define DPRX_SD1_DPRX_SD_LINE_NUMBER0_CONTROL__LINE_NUMBER0_INTERRUPT__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_LINE_NUMBER0_CONTROL__LINE_NUMBER0_INTERRUPT_MASK 0x0000FFFFL
+-//DPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS
+-#define DPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_FLAG__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_ACK__SHIFT 0x4
+-#define DPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_MASK__SHIFT 0x8
+-#define DPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_TYPE__SHIFT 0xc
+-#define DPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_FLAG_MASK 0x00000001L
+-#define DPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_ACK_MASK 0x00000010L
+-#define DPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_MASK_MASK 0x00000100L
+-#define DPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_TYPE_MASK 0x00001000L
+-//DPRX_SD1_DPRX_SD_LINE_NUMBER1_CONTROL
+-#define DPRX_SD1_DPRX_SD_LINE_NUMBER1_CONTROL__LINE_NUMBER1_INTERRUPT__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_LINE_NUMBER1_CONTROL__LINE_NUMBER1_INTERRUPT_MASK 0x0000FFFFL
+-//DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR
+-#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__BS1_ERROR__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__VBID_ERROR__SHIFT 0x1
+-#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__MVID_ERROR__SHIFT 0x2
+-#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__MAUD_ERROR__SHIFT 0x3
+-#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__IDLE_ERROR__SHIFT 0x4
+-#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__BE_BS_ERROR__SHIFT 0x5
+-#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__BE_OTHER_ERROR__SHIFT 0x6
+-#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__PIX_ERROR__SHIFT 0x7
+-#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FS_BS_ERROR__SHIFT 0x8
+-#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FS_OTHER_ERROR__SHIFT 0x9
+-#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FILL_BS_ERROR__SHIFT 0xa
+-#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FILL_OTHER_ERROR__SHIFT 0xb
+-#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FE_BS_ERROR__SHIFT 0xc
+-#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FE_OTHER_ERROR__SHIFT 0xd
+-#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FILTER_BE_ERROR__SHIFT 0xe
+-#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__BS1_ERROR_MASK 0x00000001L
+-#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__VBID_ERROR_MASK 0x00000002L
+-#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__MVID_ERROR_MASK 0x00000004L
+-#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__MAUD_ERROR_MASK 0x00000008L
+-#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__IDLE_ERROR_MASK 0x00000010L
+-#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__BE_BS_ERROR_MASK 0x00000020L
+-#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__BE_OTHER_ERROR_MASK 0x00000040L
+-#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__PIX_ERROR_MASK 0x00000080L
+-#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FS_BS_ERROR_MASK 0x00000100L
+-#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FS_OTHER_ERROR_MASK 0x00000200L
+-#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FILL_BS_ERROR_MASK 0x00000400L
+-#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FILL_OTHER_ERROR_MASK 0x00000800L
+-#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FE_BS_ERROR_MASK 0x00001000L
+-#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FE_OTHER_ERROR_MASK 0x00002000L
+-#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FILTER_BE_ERROR_MASK 0x00004000L
+-//DPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE
+-#define DPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_1_ERROR__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_2_ERROR__SHIFT 0x1
+-#define DPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_FAIL__SHIFT 0x2
+-#define DPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_1_ERROR_MASK 0x00000001L
+-#define DPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_2_ERROR_MASK 0x00000002L
+-#define DPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_FAIL_MASK 0x00000004L
+-//DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR
+-#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_MSA_SS0_ERROR__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_MSA_SS1_ERROR__SHIFT 0x1
+-#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_MSA_DATA_ERROR__SHIFT 0x2
+-#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_EXPIRE_ERROR__SHIFT 0x4
+-#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_SE_ILLEGAL_SE_ERROR__SHIFT 0x5
+-#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_ERROR__SHIFT 0x6
+-#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SS1_ERROR__SHIFT 0x8
+-#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SS2_ERROR__SHIFT 0x9
+-#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_DATA_ERROR__SHIFT 0xa
+-#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_EXPIRE_ERROR__SHIFT 0xb
+-#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_ILLEGAL_SE_ERROR__SHIFT 0xc
+-#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_ERROR__SHIFT 0xd
+-#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_MSA_SS0_ERROR_MASK 0x00000001L
+-#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_MSA_SS1_ERROR_MASK 0x00000002L
+-#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_MSA_DATA_ERROR_MASK 0x00000004L
+-#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_EXPIRE_ERROR_MASK 0x00000010L
+-#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_SE_ILLEGAL_SE_ERROR_MASK 0x00000020L
+-#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_ERROR_MASK 0x00000040L
+-#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SS1_ERROR_MASK 0x00000100L
+-#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SS2_ERROR_MASK 0x00000200L
+-#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_DATA_ERROR_MASK 0x00000400L
+-#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_EXPIRE_ERROR_MASK 0x00000800L
+-#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_ILLEGAL_SE_ERROR_MASK 0x00001000L
+-#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_ERROR_MASK 0x00002000L
+-//DPRX_SD1_DPRX_SD_VCPF_PHASE_LOCKED
+-#define DPRX_SD1_DPRX_SD_VCPF_PHASE_LOCKED__VCPF_PHASE_LOCKED__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_VCPF_PHASE_LOCKED__VCPF_PHASE_LOCKED_MASK 0x00000001L
+-//DPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR
+-#define DPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR__VCPF_PHASE_ERROR__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR__VCPF_1_SYMBOL_ERROR__SHIFT 0x1
+-#define DPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR__VCPF_2_SYMBOL_ERROR__SHIFT 0x2
+-#define DPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR__VCPF_PHASE_ERROR_MASK 0x00000001L
+-#define DPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR__VCPF_1_SYMBOL_ERROR_MASK 0x00000002L
+-#define DPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR__VCPF_2_SYMBOL_ERROR_MASK 0x00000004L
+-//DPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR
+-#define DPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR__CORRECTED_CONTROL_SEQUENCE_ERROR__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR__CORRECTED_DATA_SEQUENCE_ERROR__SHIFT 0x8
+-#define DPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR__CORRECTED_CONTROL_SEQUENCE_ERROR_MASK 0x00000001L
+-#define DPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR__CORRECTED_DATA_SEQUENCE_ERROR_MASK 0x00000100L
+-//DPRX_SD1_DPRX_SD_PIXEL_FIFO_ERROR
+-#define DPRX_SD1_DPRX_SD_PIXEL_FIFO_ERROR__PIXEL_FIFO_OVERFLOW_ERROR__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_PIXEL_FIFO_ERROR__PIXEL_FIFO_OVERFLOW_ERROR_MASK 0x00000001L
+-//DPRX_SD1_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH
+-#define DPRX_SD1_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH__MAXIMUM_SDP_PAYLOAD_LENGTH__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH__MAXIMUM_SDP_PAYLOAD_LENGTH_MASK 0x000003FFL
+-//DPRX_SD1_DPRX_SD_SDP_STEER
+-#define DPRX_SD1_DPRX_SD_SDP_STEER__FILTER_AUDIO_TIMESTAMP_SDP_EN__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_SDP_STEER__FILTER_AUDIO_TIMESTAMP_SDP_EN_MASK 0x00000001L
+-//DPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS
+-#define DPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_FLAG__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_ACK__SHIFT 0x4
+-#define DPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_MASK__SHIFT 0x8
+-#define DPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_FLAG_MASK 0x00000001L
+-#define DPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_ACK_MASK 0x00000010L
+-#define DPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_MASK_MASK 0x00000100L
+-//DPRX_SD1_DPRX_SD_SDP_LEVEL
+-#define DPRX_SD1_DPRX_SD_SDP_LEVEL__SDP_FIFO_LEVEL__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_SDP_LEVEL__SDP_CURRENT_SLICE__SHIFT 0x8
+-#define DPRX_SD1_DPRX_SD_SDP_LEVEL__SDP_FIFO_LEVEL_MASK 0x0000001FL
+-#define DPRX_SD1_DPRX_SD_SDP_LEVEL__SDP_CURRENT_SLICE_MASK 0x00000F00L
+-//DPRX_SD1_DPRX_SD_SDP_DATA
+-#define DPRX_SD1_DPRX_SD_SDP_DATA__SDP_DATA__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_SDP_DATA__SDP_DATA_MASK 0xFFFFFFFFL
+-//DPRX_SD1_DPRX_SD_SDP_ERROR
+-#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_FIFO_OVERFLOW_ERROR__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_HEADER_ERROR__SHIFT 0x1
+-#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_NON_AUDIO_PAYLOAD_ERROR__SHIFT 0x2
+-#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_NON_AUDIO_LENGTH_ERROR__SHIFT 0x3
+-#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_RS_CORRECTED_ERROR__SHIFT 0x4
+-#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_RS_UNCORRECTABLE_ERROR__SHIFT 0x5
+-#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_AUDIO_PAYLOAD_ERROR__SHIFT 0x6
+-#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_FIFO_OVERFLOW_ERROR_MASK 0x00000001L
+-#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_HEADER_ERROR_MASK 0x00000002L
+-#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_NON_AUDIO_PAYLOAD_ERROR_MASK 0x00000004L
+-#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_NON_AUDIO_LENGTH_ERROR_MASK 0x00000008L
+-#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_RS_CORRECTED_ERROR_MASK 0x00000010L
+-#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_RS_UNCORRECTABLE_ERROR_MASK 0x00000020L
+-#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_AUDIO_PAYLOAD_ERROR_MASK 0x00000040L
+-//DPRX_SD1_DPRX_SD_AUDIO_HEADER
+-#define DPRX_SD1_DPRX_SD_AUDIO_HEADER__AUDIO_HEADER__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_AUDIO_HEADER__AUDIO_HEADER_MASK 0xFFFFFFFFL
+-//DPRX_SD1_DPRX_SD_AUDIO_FIFO_ERROR
+-#define DPRX_SD1_DPRX_SD_AUDIO_FIFO_ERROR__AUDIO_FIFO_OVERFLOW_ERROR__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_AUDIO_FIFO_ERROR__AUDIO_FIFO_OVERFLOW_ERROR_MASK 0x00000001L
+-//DPRX_SD1_DPRX_SD_SDP_CONTROL
+-#define DPRX_SD1_DPRX_SD_SDP_CONTROL__RS_DECODER_ENABLE__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_SDP_CONTROL__RS_ERROR_CORRECTION_ENABLE__SHIFT 0x4
+-#define DPRX_SD1_DPRX_SD_SDP_CONTROL__RS_DECODER_ENABLE_MASK 0x00000001L
+-#define DPRX_SD1_DPRX_SD_SDP_CONTROL__RS_ERROR_CORRECTION_ENABLE_MASK 0x00000010L
+-//DPRX_SD1_DPRX_SD_V_TOTAL_MEASURED
+-#define DPRX_SD1_DPRX_SD_V_TOTAL_MEASURED__V_ACTIVE_LINE_TOTAL__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_V_TOTAL_MEASURED__V_LINE_TOTAL__SHIFT 0x10
+-#define DPRX_SD1_DPRX_SD_V_TOTAL_MEASURED__V_ACTIVE_LINE_TOTAL_MASK 0x0000FFFFL
+-#define DPRX_SD1_DPRX_SD_V_TOTAL_MEASURED__V_LINE_TOTAL_MASK 0xFFFF0000L
+-//DPRX_SD1_DPRX_SD_H_TOTAL_MEASURED
+-#define DPRX_SD1_DPRX_SD_H_TOTAL_MEASURED__H_ACTIVE_SYMBOL_TOTAL__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_H_TOTAL_MEASURED__H_ACTIVE_SYMBOL_TOTAL_MASK 0x0000FFFFL
+-//DPRX_SD1_DPRX_SD_BS_COUNTER
+-#define DPRX_SD1_DPRX_SD_BS_COUNTER__BS_COUNTER__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_BS_COUNTER__BS_COUNTER_MASK 0x000003FFL
+-//DPRX_SD1_DPRX_SD_MSE_ACT_HANDLED
+-#define DPRX_SD1_DPRX_SD_MSE_ACT_HANDLED__MSE_ACT_HANDLED__SHIFT 0x0
+-#define DPRX_SD1_DPRX_SD_MSE_ACT_HANDLED__MSE_ACT_HANDLED_MASK 0x00000001L
+-
+-
+-// addressBlock: dce_dc_dc_perfmon10_dispdec
+-//DC_PERFMON10_PERFCOUNTER_CNTL
+-#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+-#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+-#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+-#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+-#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+-#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
+-#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+-#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+-#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+-#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+-#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+-#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
+-#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+-#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+-#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+-#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+-#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+-#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+-#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
+-#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+-#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+-#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+-#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+-#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+-#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
+-#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+-//DC_PERFMON10_PERFCOUNTER_CNTL2
+-#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+-#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+-#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+-#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+-#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+-#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+-#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+-#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+-//DC_PERFMON10_PERFCOUNTER_STATE
+-#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+-#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+-#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+-#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+-#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+-#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+-#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+-#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+-#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+-#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+-#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+-#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+-#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+-#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+-#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+-#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+-#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+-#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+-#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+-#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+-#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+-#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+-#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+-#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+-#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+-#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+-#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+-#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+-#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+-#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+-#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+-#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+-//DC_PERFMON10_PERFMON_CNTL
+-#define DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+-#define DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+-#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+-#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+-#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+-#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+-#define DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+-#define DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+-#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+-#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+-#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+-#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+-//DC_PERFMON10_PERFMON_CNTL2
+-#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+-#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+-#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+-#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+-#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+-#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+-#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+-#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+-//DC_PERFMON10_PERFMON_CVALUE_INT_MISC
+-#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+-#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+-#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+-#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+-#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+-#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+-#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+-#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+-#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+-#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+-#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+-#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+-#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+-#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+-#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+-#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+-#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+-#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+-#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+-#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+-#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+-#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+-#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+-#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+-#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+-#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+-#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+-#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+-#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+-#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+-#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+-#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+-#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+-#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+-//DC_PERFMON10_PERFMON_CVALUE_LOW
+-#define DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+-#define DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+-//DC_PERFMON10_PERFMON_HI
+-#define DC_PERFMON10_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+-#define DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+-#define DC_PERFMON10_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+-#define DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+-//DC_PERFMON10_PERFMON_LOW
+-#define DC_PERFMON10_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+-#define DC_PERFMON10_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_dc_zcalregs_dispdec
+-//COMP_EN_CTL
+-#define COMP_EN_CTL__comp_en__SHIFT 0x0
+-#define COMP_EN_CTL__comp_en_override__SHIFT 0x2
+-#define COMP_EN_CTL__comp_done__SHIFT 0x4
+-#define COMP_EN_CTL__zcal_code_override__SHIFT 0x6
+-#define COMP_EN_CTL__zcal_cal_rtt__SHIFT 0x7
+-#define COMP_EN_CTL__zcal_base_en__SHIFT 0x8
+-#define COMP_EN_CTL__zcal_ht_rtt_sel__SHIFT 0x9
+-#define COMP_EN_CTL__zcal_code__SHIFT 0xa
+-#define COMP_EN_CTL__zcal_ron_cal_mode__SHIFT 0x10
+-#define COMP_EN_CTL__zcal_ana_dbg_sel__SHIFT 0x11
+-#define COMP_EN_CTL__cfg_cml_cmos_sel__SHIFT 0x13
+-#define COMP_EN_CTL__dsm_sel__SHIFT 0x14
+-#define COMP_EN_CTL__comp_en_MASK 0x00000001L
+-#define COMP_EN_CTL__comp_en_override_MASK 0x00000004L
+-#define COMP_EN_CTL__comp_done_MASK 0x00000010L
+-#define COMP_EN_CTL__zcal_code_override_MASK 0x00000040L
+-#define COMP_EN_CTL__zcal_cal_rtt_MASK 0x00000080L
+-#define COMP_EN_CTL__zcal_base_en_MASK 0x00000100L
+-#define COMP_EN_CTL__zcal_ht_rtt_sel_MASK 0x00000200L
+-#define COMP_EN_CTL__zcal_code_MASK 0x00007C00L
+-#define COMP_EN_CTL__zcal_ron_cal_mode_MASK 0x00010000L
+-#define COMP_EN_CTL__zcal_ana_dbg_sel_MASK 0x00060000L
+-#define COMP_EN_CTL__cfg_cml_cmos_sel_MASK 0x00080000L
+-#define COMP_EN_CTL__dsm_sel_MASK 0x00F00000L
+-//COMP_EN_DFX
+-#define COMP_EN_DFX__autocal_ron_code__SHIFT 0x0
+-#define COMP_EN_DFX__autocal_rtt_code__SHIFT 0x5
+-#define COMP_EN_DFX__pre_fused_ron_code__SHIFT 0xb
+-#define COMP_EN_DFX__pre_fused_rtt_code__SHIFT 0x10
+-#define COMP_EN_DFX__broadcast_ron_code__SHIFT 0x16
+-#define COMP_EN_DFX__broadcast_rtt_code__SHIFT 0x1b
+-#define COMP_EN_DFX__autocal_ron_code_MASK 0x0000001FL
+-#define COMP_EN_DFX__autocal_rtt_code_MASK 0x000003E0L
+-#define COMP_EN_DFX__pre_fused_ron_code_MASK 0x0000F800L
+-#define COMP_EN_DFX__pre_fused_rtt_code_MASK 0x001F0000L
+-#define COMP_EN_DFX__broadcast_ron_code_MASK 0x07C00000L
+-#define COMP_EN_DFX__broadcast_rtt_code_MASK 0xF8000000L
+-//ZCAL_FUSES
+-#define ZCAL_FUSES__fuse_valid__SHIFT 0x0
+-#define ZCAL_FUSES__fuse_ron_override_val__SHIFT 0x3
+-#define ZCAL_FUSES__fuse_ron_ctl__SHIFT 0xa
+-#define ZCAL_FUSES__fuse_rtt_override_val__SHIFT 0xd
+-#define ZCAL_FUSES__fuse_rtt_ctl__SHIFT 0x14
+-#define ZCAL_FUSES__fuse_refresh_cal_en__SHIFT 0x16
+-#define ZCAL_FUSES__fuse_spare__SHIFT 0x17
+-#define ZCAL_FUSES__fuse_valid_MASK 0x00000001L
+-#define ZCAL_FUSES__fuse_ron_override_val_MASK 0x000001F8L
+-#define ZCAL_FUSES__fuse_ron_ctl_MASK 0x00000C00L
+-#define ZCAL_FUSES__fuse_rtt_override_val_MASK 0x0007E000L
+-#define ZCAL_FUSES__fuse_rtt_ctl_MASK 0x00300000L
+-#define ZCAL_FUSES__fuse_refresh_cal_en_MASK 0x00400000L
+-#define ZCAL_FUSES__fuse_spare_MASK 0xFF800000L
+-
+-
+-// addressBlock: dce_dc_dispdec_VGA_MEM_WRITE_PAGE_ADDR
+-
+-
+-// addressBlock: dce_dc_dispdec_VGA_MEM_READ_PAGE_ADDR
+-
+-
+-// addressBlock: dce_dc_dispdec[948..986]
+-
+-
+-// addressBlock: dce_dc_azdec
+-//CORB_WRITE_POINTER
+-#define CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT 0x0
+-#define CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK 0x00FFL
+-//CORB_READ_POINTER
+-#define CORB_READ_POINTER__CORB_READ_POINTER__SHIFT 0x0
+-#define CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT 0xf
+-#define CORB_READ_POINTER__CORB_READ_POINTER_MASK 0x00FFL
+-#define CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK 0x8000L
+-//CORB_CONTROL
+-#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT 0x0
+-#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT 0x1
+-#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x01L
+-#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK 0x02L
+-//CORB_STATUS
+-#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT 0x0
+-#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK 0x01L
+-//CORB_SIZE
+-#define CORB_SIZE__CORB_SIZE__SHIFT 0x0
+-#define CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT 0x4
+-#define CORB_SIZE__CORB_SIZE_MASK 0x0003L
+-#define CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 0x00F0L
+-//RIRB_LOWER_BASE_ADDRESS
+-#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0
+-#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT 0x7
+-#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x0000007FL
+-#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L
+-//RIRB_UPPER_BASE_ADDRESS
+-#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT 0x0
+-#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL
+-//RIRB_WRITE_POINTER
+-#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT 0x0
+-#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT 0xf
+-#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK 0x00FFL
+-#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK 0x8000L
+-//RESPONSE_INTERRUPT_COUNT
+-#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT 0x0
+-#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK 0x00FFL
+-//RIRB_CONTROL
+-#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT 0x0
+-#define RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 0x1
+-#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT 0x2
+-#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK 0x01L
+-#define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x02L
+-#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK 0x04L
+-//RIRB_STATUS
+-#define RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 0x0
+-#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT 0x2
+-#define RIRB_STATUS__RESPONSE_INTERRUPT_MASK 0x01L
+-#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK 0x04L
+-//RIRB_SIZE
+-#define RIRB_SIZE__RIRB_SIZE__SHIFT 0x0
+-#define RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 0x4
+-#define RIRB_SIZE__RIRB_SIZE_MASK 0x0003L
+-#define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 0x00F0L
+-//AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA
+-#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+-#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL
+-//AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX
+-#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+-#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL
+-//AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA
+-#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+-#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL
+-//AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX
+-#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+-#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL
+-//AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA
+-#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+-#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL
+-//AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX
+-#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+-#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL
+-//IMMEDIATE_COMMAND_OUTPUT_INTERFACE
+-#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT 0x0
+-#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT 0x1c
+-#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK 0x0FFFFFFFL
+-#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK 0xF0000000L
+-//IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA
+-#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+-#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL
+-//IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX
+-#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+-#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0000FFFFL
+-//IMMEDIATE_RESPONSE_INPUT_INTERFACE
+-#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT 0x0
+-#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK 0xFFFFFFFFL
+-//IMMEDIATE_COMMAND_STATUS
+-#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT 0x0
+-#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT 0x1
+-#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK 0x00000001L
+-#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK 0x00000002L
+-//DMA_POSITION_LOWER_BASE_ADDRESS
+-#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT 0x0
+-#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x1
+-#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT 0x7
+-#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK 0x00000001L
+-#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x0000007EL
+-#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L
+-//DMA_POSITION_UPPER_BASE_ADDRESS
+-#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT 0x0
+-#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL
+-//WALL_CLOCK_COUNTER_ALIAS
+-#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT 0x0
+-#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_azstream0_azdec
+-//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L
+-//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL
+-//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL
+-//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL
+-//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL
+-//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L
+-//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L
+-//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL
+-//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0
+-#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_azstream1_azdec
+-//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L
+-//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL
+-//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL
+-//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL
+-//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL
+-//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L
+-//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L
+-//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL
+-//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0
+-#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_azstream2_azdec
+-//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L
+-//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL
+-//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL
+-//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL
+-//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL
+-//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L
+-//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L
+-//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL
+-//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0
+-#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_azstream3_azdec
+-//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L
+-//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL
+-//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL
+-//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL
+-//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL
+-//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L
+-//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L
+-//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL
+-//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0
+-#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_azstream4_azdec
+-//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L
+-//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL
+-//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL
+-//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL
+-//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL
+-//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L
+-//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L
+-//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL
+-//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0
+-#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_azstream5_azdec
+-//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L
+-//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL
+-//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL
+-//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL
+-//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL
+-//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L
+-//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L
+-//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL
+-//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0
+-#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_azstream6_azdec
+-//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L
+-//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL
+-//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL
+-//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL
+-//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL
+-//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L
+-//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L
+-//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL
+-//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0
+-#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: dce_dc_azstream7_azdec
+-//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L
+-//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL
+-//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL
+-//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL
+-//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL
+-//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L
+-//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L
+-//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL
+-//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0
+-#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: azf0stream0_streamind
+-//AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL
+-#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+-#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+-#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+-#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+-#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+-#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+-//AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL
+-#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+-#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+-//AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT
+-#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+-#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+-//AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT
+-#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+-#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+-//AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT
+-#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+-#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: azf0stream1_streamind
+-//AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL
+-#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+-#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+-#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+-#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+-#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+-#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+-//AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL
+-#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+-#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+-//AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT
+-#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+-#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+-//AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT
+-#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+-#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+-//AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT
+-#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+-#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: azf0stream2_streamind
+-//AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL
+-#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+-#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+-#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+-#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+-#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+-#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+-//AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL
+-#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+-#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+-//AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT
+-#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+-#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+-//AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT
+-#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+-#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+-//AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT
+-#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+-#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: azf0stream3_streamind
+-//AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL
+-#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+-#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+-#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+-#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+-#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+-#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+-//AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL
+-#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+-#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+-//AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT
+-#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+-#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+-//AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT
+-#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+-#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+-//AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT
+-#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+-#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: azf0stream4_streamind
+-//AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL
+-#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+-#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+-#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+-#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+-#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+-#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+-//AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL
+-#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+-#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+-//AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT
+-#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+-#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+-//AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT
+-#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+-#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+-//AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT
+-#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+-#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: azf0stream5_streamind
+-//AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL
+-#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+-#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+-#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+-#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+-#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+-#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+-//AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL
+-#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+-#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+-//AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT
+-#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+-#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+-//AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT
+-#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+-#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+-//AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT
+-#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+-#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: azf0stream6_streamind
+-//AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL
+-#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+-#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+-#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+-#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+-#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+-#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+-//AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL
+-#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+-#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+-//AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT
+-#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+-#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+-//AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT
+-#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+-#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+-//AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT
+-#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+-#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: azf0stream7_streamind
+-//AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL
+-#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+-#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+-#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+-#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+-#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+-#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+-//AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL
+-#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+-#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+-//AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT
+-#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+-#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+-//AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT
+-#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+-#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+-//AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT
+-#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+-#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: azf0stream8_streamind
+-//AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL
+-#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+-#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+-#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+-#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+-#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+-#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+-//AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL
+-#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+-#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+-//AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT
+-#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+-#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+-//AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT
+-#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+-#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+-//AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT
+-#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+-#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: azf0stream9_streamind
+-//AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL
+-#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+-#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+-#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+-#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+-#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+-#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+-//AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL
+-#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+-#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+-//AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT
+-#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+-#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+-//AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT
+-#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+-#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+-//AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT
+-#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+-#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: azf0stream10_streamind
+-//AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL
+-#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+-#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+-#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+-#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+-#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+-#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+-//AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL
+-#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+-#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+-//AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT
+-#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+-#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+-//AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT
+-#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+-#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+-//AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT
+-#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+-#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: azf0stream11_streamind
+-//AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL
+-#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+-#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+-#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+-#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+-#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+-#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+-//AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL
+-#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+-#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+-//AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT
+-#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+-#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+-//AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT
+-#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+-#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+-//AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT
+-#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+-#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: azf0stream12_streamind
+-//AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL
+-#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+-#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+-#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+-#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+-#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+-#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+-//AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL
+-#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+-#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+-//AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT
+-#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+-#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+-//AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT
+-#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+-#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+-//AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT
+-#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+-#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: azf0stream13_streamind
+-//AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL
+-#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+-#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+-#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+-#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+-#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+-#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+-//AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL
+-#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+-#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+-//AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT
+-#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+-#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+-//AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT
+-#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+-#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+-//AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT
+-#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+-#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: azf0stream14_streamind
+-//AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL
+-#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+-#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+-#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+-#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+-#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+-#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+-//AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL
+-#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+-#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+-//AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT
+-#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+-#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+-//AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT
+-#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+-#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+-//AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT
+-#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+-#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: azf0stream15_streamind
+-//AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL
+-#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+-#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+-#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+-#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+-#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+-#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+-//AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL
+-#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+-#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+-//AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT
+-#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+-#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+-//AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT
+-#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+-#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+-//AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT
+-#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+-#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: azf0endpoint0_endpointind
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L
+-//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL
+-//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L
+-//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L
+-//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L
+-//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L
+-//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L
+-//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+-//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L
+-//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL
+-#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L
+-//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L
+-//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS
+-#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L
+-//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+-#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4
+-#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8
+-#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L
+-#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L
+-#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L
+-//AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+-#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4
+-#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8
+-#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L
+-#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L
+-#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L
+-//AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+-#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0
+-#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4
+-#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8
+-#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L
+-#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L
+-#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L
+-
+-
+-// addressBlock: azf0endpoint1_endpointind
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L
+-//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL
+-//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L
+-//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L
+-//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L
+-//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L
+-//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L
+-//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+-//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L
+-//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL
+-#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L
+-//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L
+-//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS
+-#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L
+-//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+-#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4
+-#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8
+-#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L
+-#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L
+-#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L
+-//AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+-#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4
+-#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8
+-#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L
+-#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L
+-#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L
+-//AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+-#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0
+-#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4
+-#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8
+-#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L
+-#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L
+-#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L
+-
+-
+-// addressBlock: azf0endpoint2_endpointind
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L
+-//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL
+-//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L
+-//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L
+-//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L
+-//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L
+-//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L
+-//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+-//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L
+-//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL
+-#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L
+-//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L
+-//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS
+-#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L
+-//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+-#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4
+-#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8
+-#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L
+-#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L
+-#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L
+-//AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+-#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4
+-#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8
+-#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L
+-#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L
+-#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L
+-//AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+-#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0
+-#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4
+-#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8
+-#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L
+-#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L
+-#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L
+-
+-
+-// addressBlock: azf0endpoint3_endpointind
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L
+-//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL
+-//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L
+-//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L
+-//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L
+-//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L
+-//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L
+-//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+-//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L
+-//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL
+-#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L
+-//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L
+-//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS
+-#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L
+-//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+-#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4
+-#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8
+-#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L
+-#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L
+-#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L
+-//AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+-#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4
+-#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8
+-#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L
+-#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L
+-#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L
+-//AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+-#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0
+-#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4
+-#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8
+-#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L
+-#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L
+-#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L
+-
+-
+-// addressBlock: azf0endpoint4_endpointind
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L
+-//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL
+-//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L
+-//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L
+-//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L
+-//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L
+-//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L
+-//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+-//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L
+-//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL
+-#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L
+-//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L
+-//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS
+-#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L
+-//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+-#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4
+-#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8
+-#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L
+-#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L
+-#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L
+-//AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+-#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4
+-#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8
+-#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L
+-#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L
+-#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L
+-//AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+-#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0
+-#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4
+-#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8
+-#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L
+-#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L
+-#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L
+-
+-
+-// addressBlock: azf0endpoint5_endpointind
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L
+-//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL
+-//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L
+-//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L
+-//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L
+-//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L
+-//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L
+-//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+-//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L
+-//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL
+-#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L
+-//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L
+-//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS
+-#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L
+-//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+-#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4
+-#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8
+-#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L
+-#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L
+-#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L
+-//AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+-#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4
+-#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8
+-#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L
+-#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L
+-#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L
+-//AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+-#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0
+-#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4
+-#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8
+-#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L
+-#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L
+-#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L
+-
+-
+-// addressBlock: azf0endpoint6_endpointind
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L
+-//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL
+-//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L
+-//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L
+-//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L
+-//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L
+-//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L
+-//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+-//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L
+-//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL
+-#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L
+-//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L
+-//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS
+-#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L
+-//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+-#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4
+-#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8
+-#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L
+-#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L
+-#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L
+-//AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+-#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4
+-#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8
+-#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L
+-#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L
+-#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L
+-//AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+-#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0
+-#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4
+-#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8
+-#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L
+-#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L
+-#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L
+-
+-
+-// addressBlock: azf0endpoint7_endpointind
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L
+-//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL
+-//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L
+-//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L
+-//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L
+-//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L
+-//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L
+-//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+-//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L
+-//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL
+-#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L
+-//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L
+-#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L
+-//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS
+-#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L
+-//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+-#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4
+-#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8
+-#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L
+-#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L
+-#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L
+-//AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+-#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4
+-#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8
+-#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L
+-#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L
+-#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L
+-//AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+-#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0
+-#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4
+-#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8
+-#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L
+-#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L
+-#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L
+-
+-
+-// addressBlock: azf0inputendpoint0_inputendpointind
+-//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+-//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+-//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+-//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+-//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+-//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+-//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+-//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+-//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+-//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
+-//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L
+-//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L
+-//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+-//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+-//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL
+-//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+-//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+-//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+-//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+-//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+-//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+-//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L
+-//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L
+-#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L
+-
+-
+-// addressBlock: azf0inputendpoint1_inputendpointind
+-//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+-//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+-//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+-//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+-//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+-//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+-//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+-//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+-//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+-//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
+-//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L
+-//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L
+-//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+-//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+-//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL
+-//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+-//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+-//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+-//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+-//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+-//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+-//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L
+-//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L
+-#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L
+-
+-
+-// addressBlock: azf0inputendpoint2_inputendpointind
+-//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+-//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+-//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+-//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+-//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+-//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+-//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+-//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+-//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+-//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
+-//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L
+-//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L
+-//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+-//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+-//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL
+-//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+-//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+-//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+-//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+-//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+-//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+-//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L
+-//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L
+-#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L
+-
+-
+-// addressBlock: azf0inputendpoint3_inputendpointind
+-//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+-//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+-//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+-//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+-//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+-//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+-//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+-//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+-//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+-//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
+-//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L
+-//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L
+-//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+-//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+-//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL
+-//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+-//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+-//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+-//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+-//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+-//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+-//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L
+-//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L
+-#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L
+-
+-
+-// addressBlock: azf0inputendpoint4_inputendpointind
+-//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+-//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+-//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+-//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+-//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+-//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+-//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+-//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+-//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+-//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
+-//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L
+-//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L
+-//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+-//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+-//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL
+-//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+-//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+-//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+-//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+-//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+-//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+-//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L
+-//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L
+-#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L
+-
+-
+-// addressBlock: azf0inputendpoint5_inputendpointind
+-//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+-//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+-//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+-//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+-//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+-//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+-//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+-//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+-//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+-//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
+-//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L
+-//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L
+-//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+-//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+-//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL
+-//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+-//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+-//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+-//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+-//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+-//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+-//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L
+-//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L
+-#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L
+-
+-
+-// addressBlock: azf0inputendpoint6_inputendpointind
+-//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+-//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+-//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+-//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+-//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+-//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+-//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+-//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+-//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+-//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
+-//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L
+-//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L
+-//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+-//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+-//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL
+-//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+-//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+-//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+-//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+-//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+-//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+-//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L
+-//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L
+-#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L
+-
+-
+-// addressBlock: azf0inputendpoint7_inputendpointind
+-//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+-//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+-//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+-//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+-//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+-//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+-//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+-//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+-//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+-//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
+-//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L
+-//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L
+-//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+-//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+-//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL
+-//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+-//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+-//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+-//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+-//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+-//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+-//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L
+-//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L
+-#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L
+-
+-
+-// addressBlock: f2codecind
+-//AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID
+-#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0
+-#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xFFFFFFFFL
+-//AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID
+-#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0
+-#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xFFFFFFFFL
+-//AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT
+-#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0
+-#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xFFFFFFFFL
+-//AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE
+-#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0
+-#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4
+-#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9
+-#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa
+-#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000FL
+-#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000F0L
+-#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L
+-#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L
+-//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID
+-#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0
+-#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8
+-#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10
+-#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18
+-#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000FFL
+-#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000FF00L
+-#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00FF0000L
+-#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xFF000000L
+-//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2
+-#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT 0x0
+-#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK 0x000000FFL
+-//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3
+-#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT 0x0
+-#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK 0x000000FFL
+-//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4
+-#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT 0x0
+-#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK 0x000000FFL
+-//AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION
+-#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0
+-#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x000000FFL
+-//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET
+-#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0
+-#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L
+-//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT
+-#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0
+-#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xFFFFFFFFL
+-//AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE
+-#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0
+-#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xFFFFFFFFL
+-//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
+-#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+-#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+-#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+-#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+-//AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
+-#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0
+-#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xFFFFFFFFL
+-//AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES
+-#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0
+-#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e
+-#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f
+-#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3FFFFFFFL
+-#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L
+-#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L
+-//AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT 0xf
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK 0x00008000L
+-//AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+-//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+-//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT 0x0
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK 0x0000007FL
+-//AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL
+-#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
+-#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
+-#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L
+-#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L
+-//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT 0x7
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK 0x00000080L
+-//AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL
+-//AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L
+-#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L
+-//AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+-#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+-#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+-#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+-#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+-#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+-#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+-#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+-#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+-#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+-#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+-#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+-#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+-#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+-#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+-#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+-#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+-#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+-#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+-#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+-#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+-#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+-#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+-#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+-#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+-#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+-#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+-#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+-#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+-//AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+-#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+-#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+-#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+-#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+-//AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+-#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+-#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+-//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK 0xFFFFFFFFL
+-//AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL
+-#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
+-#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L
+-//AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+-#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+-#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+-#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+-//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
+-//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+-//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0x0000000FL
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0x000000F0L
+-//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0x0000000FL
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0x000000F0L
+-//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x0000003FL
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0x000000C0L
+-//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT 0x8
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT 0x9
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT 0xa
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK 0x0000007FL
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK 0x00000100L
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK 0x00000200L
+-#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK 0x0000FC00L
+-//AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION
+-#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL
+-//AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO
+-#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT 0x3
+-#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT 0x7
+-#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL_MASK 0x00000003L
+-#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK 0x00000078L
+-#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK 0x00000080L
+-//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR
+-#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT 0x3
+-#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+-#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK 0x00000007L
+-#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK 0x00000078L
+-#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+-//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA
+-#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK 0xFFFFFFFFL
+-//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L
+-//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x1
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x4
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000001L
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000002L
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x000000F0L
+-//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x1
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x4
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00000001L
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00000002L
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x000000F0L
+-//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x1
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x4
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x00000001L
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK 0x00000002L
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0x000000F0L
+-//AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC
+-#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
+-#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL
+-#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L
+-//AZALIA_F2_CODEC_PIN_CONTROL_HBR
+-#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4
+-#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x00000001L
+-#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x00000010L
+-//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX
+-#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK 0x000000FFL
+-//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA
+-#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK 0xFFFFFFFFL
+-//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000001L
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000002L
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L
+-//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x00000001L
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x00000002L
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0x000000F0L
+-//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x00000001L
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x00000002L
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0x000000F0L
+-//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x00000001L
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x00000002L
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0x000000F0L
+-//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L
+-//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL
+-//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L
+-//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L
+-//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L
+-//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L
+-//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L
+-//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+-//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L
+-//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL
+-#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L
+-//AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO
+-#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL
+-//AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+-#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L
+-//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+-#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+-#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+-#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+-//AZALIA_F2_CODEC_PIN_CONTROL_LPIB
+-#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+-//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+-#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+-//AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE
+-#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL
+-//AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED
+-#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
+-#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
+-#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
+-#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L
+-#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L
+-#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L
+-#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L
+-//AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+-#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L
+-//AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+-#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
+-#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L
+-#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L
+-//AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+-//AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+-//AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK 0xFFFFFFFFL
+-//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+-//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+-//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+-//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+-//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+-//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+-#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+-//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L
+-//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+-//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
+-//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+-//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0x0000000FL
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0x000000F0L
+-//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0x0000000FL
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0x000000F0L
+-//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x0000003FL
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0x000000C0L
+-//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL
+-//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L
+-//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x0
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x1
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x4
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00000001L
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00000002L
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x000000F0L
+-//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE__SHIFT 0x0
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE__SHIFT 0x1
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE_MASK 0x00000001L
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE_MASK 0x00000002L
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L
+-//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE__SHIFT 0x0
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE__SHIFT 0x1
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x4
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE_MASK 0x00000001L
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE_MASK 0x00000002L
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID_MASK 0x000000F0L
+-//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x00000001L
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x00000010L
+-//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000001L
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000002L
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L
+-//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x00000001L
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x00000002L
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0x000000F0L
+-//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x00000001L
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x00000002L
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0x000000F0L
+-//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x00000001L
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x00000002L
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0x000000F0L
+-//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+-//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+-//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+-//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L
+-//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L
+-//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L__SHIFT 0x0
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L_MASK 0xFFFFFFFFL
+-//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H__SHIFT 0x0
+-#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H_MASK 0xFFFFFFFFL
+-//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+-//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+-#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+-
+-
+-// addressBlock: descriptorind
+-//AUDIO_DESCRIPTOR0
+-#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
+-#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+-#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L
+-#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+-//AUDIO_DESCRIPTOR1
+-#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
+-#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+-#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L
+-#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+-//AUDIO_DESCRIPTOR2
+-#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
+-#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+-#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L
+-#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+-//AUDIO_DESCRIPTOR3
+-#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
+-#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+-#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L
+-#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+-//AUDIO_DESCRIPTOR4
+-#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
+-#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+-#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L
+-#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+-//AUDIO_DESCRIPTOR5
+-#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
+-#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+-#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L
+-#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+-//AUDIO_DESCRIPTOR6
+-#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
+-#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+-#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L
+-#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+-//AUDIO_DESCRIPTOR7
+-#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
+-#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+-#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L
+-#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+-//AUDIO_DESCRIPTOR8
+-#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
+-#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+-#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L
+-#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+-//AUDIO_DESCRIPTOR9
+-#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
+-#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+-#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L
+-#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+-//AUDIO_DESCRIPTOR10
+-#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
+-#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+-#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L
+-#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+-//AUDIO_DESCRIPTOR11
+-#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
+-#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+-#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L
+-#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+-//AUDIO_DESCRIPTOR12
+-#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
+-#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+-#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L
+-#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+-//AUDIO_DESCRIPTOR13
+-#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
+-#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
+-#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
+-#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+-#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L
+-#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+-#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+-#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+-
+-
+-// addressBlock: sinkinfoind
+-//AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK 0x0000FFFFL
+-//AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID
+-#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK 0x0000FFFFL
+-//AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN
+-#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK 0x000000FFL
+-//AZALIA_F2_CODEC_PIN_CONTROL_PORTID0
+-#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK 0xFFFFFFFFL
+-//AZALIA_F2_CODEC_PIN_CONTROL_PORTID1
+-#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT 0x0
+-#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK 0xFFFFFFFFL
+-//SINK_DESCRIPTION0
+-#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT 0x0
+-#define SINK_DESCRIPTION0__DESCRIPTION_MASK 0x000000FFL
+-//SINK_DESCRIPTION1
+-#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT 0x0
+-#define SINK_DESCRIPTION1__DESCRIPTION_MASK 0x000000FFL
+-//SINK_DESCRIPTION2
+-#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT 0x0
+-#define SINK_DESCRIPTION2__DESCRIPTION_MASK 0x000000FFL
+-//SINK_DESCRIPTION3
+-#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT 0x0
+-#define SINK_DESCRIPTION3__DESCRIPTION_MASK 0x000000FFL
+-//SINK_DESCRIPTION4
+-#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT 0x0
+-#define SINK_DESCRIPTION4__DESCRIPTION_MASK 0x000000FFL
+-//SINK_DESCRIPTION5
+-#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT 0x0
+-#define SINK_DESCRIPTION5__DESCRIPTION_MASK 0x000000FFL
+-//SINK_DESCRIPTION6
+-#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT 0x0
+-#define SINK_DESCRIPTION6__DESCRIPTION_MASK 0x000000FFL
+-//SINK_DESCRIPTION7
+-#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT 0x0
+-#define SINK_DESCRIPTION7__DESCRIPTION_MASK 0x000000FFL
+-//SINK_DESCRIPTION8
+-#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT 0x0
+-#define SINK_DESCRIPTION8__DESCRIPTION_MASK 0x000000FFL
+-//SINK_DESCRIPTION9
+-#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT 0x0
+-#define SINK_DESCRIPTION9__DESCRIPTION_MASK 0x000000FFL
+-//SINK_DESCRIPTION10
+-#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT 0x0
+-#define SINK_DESCRIPTION10__DESCRIPTION_MASK 0x000000FFL
+-//SINK_DESCRIPTION11
+-#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT 0x0
+-#define SINK_DESCRIPTION11__DESCRIPTION_MASK 0x000000FFL
+-//SINK_DESCRIPTION12
+-#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT 0x0
+-#define SINK_DESCRIPTION12__DESCRIPTION_MASK 0x000000FFL
+-//SINK_DESCRIPTION13
+-#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT 0x0
+-#define SINK_DESCRIPTION13__DESCRIPTION_MASK 0x000000FFL
+-//SINK_DESCRIPTION14
+-#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT 0x0
+-#define SINK_DESCRIPTION14__DESCRIPTION_MASK 0x000000FFL
+-//SINK_DESCRIPTION15
+-#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT 0x0
+-#define SINK_DESCRIPTION15__DESCRIPTION_MASK 0x000000FFL
+-//SINK_DESCRIPTION16
+-#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT 0x0
+-#define SINK_DESCRIPTION16__DESCRIPTION_MASK 0x000000FFL
+-//SINK_DESCRIPTION17
+-#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT 0x0
+-#define SINK_DESCRIPTION17__DESCRIPTION_MASK 0x000000FFL
+-
+-
+-// addressBlock: azinputcrc0resultind
+-//AZALIA_INPUT_CRC0_CHANNEL0
+-#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0
+-#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xFFFFFFFFL
+-//AZALIA_INPUT_CRC0_CHANNEL1
+-#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0
+-#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xFFFFFFFFL
+-//AZALIA_INPUT_CRC0_CHANNEL2
+-#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0
+-#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xFFFFFFFFL
+-//AZALIA_INPUT_CRC0_CHANNEL3
+-#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0
+-#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xFFFFFFFFL
+-//AZALIA_INPUT_CRC0_CHANNEL4
+-#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0
+-#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xFFFFFFFFL
+-//AZALIA_INPUT_CRC0_CHANNEL5
+-#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0
+-#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xFFFFFFFFL
+-//AZALIA_INPUT_CRC0_CHANNEL6
+-#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0
+-#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xFFFFFFFFL
+-//AZALIA_INPUT_CRC0_CHANNEL7
+-#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0
+-#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: azinputcrc1resultind
+-//AZALIA_INPUT_CRC1_CHANNEL0
+-#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0
+-#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xFFFFFFFFL
+-//AZALIA_INPUT_CRC1_CHANNEL1
+-#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0
+-#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xFFFFFFFFL
+-//AZALIA_INPUT_CRC1_CHANNEL2
+-#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0
+-#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xFFFFFFFFL
+-//AZALIA_INPUT_CRC1_CHANNEL3
+-#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0
+-#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xFFFFFFFFL
+-//AZALIA_INPUT_CRC1_CHANNEL4
+-#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0
+-#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xFFFFFFFFL
+-//AZALIA_INPUT_CRC1_CHANNEL5
+-#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0
+-#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xFFFFFFFFL
+-//AZALIA_INPUT_CRC1_CHANNEL6
+-#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0
+-#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xFFFFFFFFL
+-//AZALIA_INPUT_CRC1_CHANNEL7
+-#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0
+-#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: azcrc0resultind
+-//AZALIA_CRC0_CHANNEL0
+-#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0
+-#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK 0xFFFFFFFFL
+-//AZALIA_CRC0_CHANNEL1
+-#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0
+-#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK 0xFFFFFFFFL
+-//AZALIA_CRC0_CHANNEL2
+-#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0
+-#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK 0xFFFFFFFFL
+-//AZALIA_CRC0_CHANNEL3
+-#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0
+-#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK 0xFFFFFFFFL
+-//AZALIA_CRC0_CHANNEL4
+-#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0
+-#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK 0xFFFFFFFFL
+-//AZALIA_CRC0_CHANNEL5
+-#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0
+-#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK 0xFFFFFFFFL
+-//AZALIA_CRC0_CHANNEL6
+-#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0
+-#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK 0xFFFFFFFFL
+-//AZALIA_CRC0_CHANNEL7
+-#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0
+-#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: azcrc1resultind
+-//AZALIA_CRC1_CHANNEL0
+-#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0
+-#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK 0xFFFFFFFFL
+-//AZALIA_CRC1_CHANNEL1
+-#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0
+-#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK 0xFFFFFFFFL
+-//AZALIA_CRC1_CHANNEL2
+-#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0
+-#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK 0xFFFFFFFFL
+-//AZALIA_CRC1_CHANNEL3
+-#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0
+-#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK 0xFFFFFFFFL
+-//AZALIA_CRC1_CHANNEL4
+-#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0
+-#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK 0xFFFFFFFFL
+-//AZALIA_CRC1_CHANNEL5
+-#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0
+-#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK 0xFFFFFFFFL
+-//AZALIA_CRC1_CHANNEL6
+-#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0
+-#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK 0xFFFFFFFFL
+-//AZALIA_CRC1_CHANNEL7
+-#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0
+-#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: vgaseqind
+-//SEQ00
+-#define SEQ00__SEQ_RST0B__SHIFT 0x0
+-#define SEQ00__SEQ_RST1B__SHIFT 0x1
+-#define SEQ00__SEQ_RST0B_MASK 0x01L
+-#define SEQ00__SEQ_RST1B_MASK 0x02L
+-//SEQ01
+-#define SEQ01__SEQ_DOT8__SHIFT 0x0
+-#define SEQ01__SEQ_SHIFT2__SHIFT 0x2
+-#define SEQ01__SEQ_PCLKBY2__SHIFT 0x3
+-#define SEQ01__SEQ_SHIFT4__SHIFT 0x4
+-#define SEQ01__SEQ_MAXBW__SHIFT 0x5
+-#define SEQ01__SEQ_DOT8_MASK 0x01L
+-#define SEQ01__SEQ_SHIFT2_MASK 0x04L
+-#define SEQ01__SEQ_PCLKBY2_MASK 0x08L
+-#define SEQ01__SEQ_SHIFT4_MASK 0x10L
+-#define SEQ01__SEQ_MAXBW_MASK 0x20L
+-//SEQ02
+-#define SEQ02__SEQ_MAP0_EN__SHIFT 0x0
+-#define SEQ02__SEQ_MAP1_EN__SHIFT 0x1
+-#define SEQ02__SEQ_MAP2_EN__SHIFT 0x2
+-#define SEQ02__SEQ_MAP3_EN__SHIFT 0x3
+-#define SEQ02__SEQ_MAP0_EN_MASK 0x01L
+-#define SEQ02__SEQ_MAP1_EN_MASK 0x02L
+-#define SEQ02__SEQ_MAP2_EN_MASK 0x04L
+-#define SEQ02__SEQ_MAP3_EN_MASK 0x08L
+-//SEQ03
+-#define SEQ03__SEQ_FONT_B1__SHIFT 0x0
+-#define SEQ03__SEQ_FONT_B2__SHIFT 0x1
+-#define SEQ03__SEQ_FONT_A1__SHIFT 0x2
+-#define SEQ03__SEQ_FONT_A2__SHIFT 0x3
+-#define SEQ03__SEQ_FONT_B0__SHIFT 0x4
+-#define SEQ03__SEQ_FONT_A0__SHIFT 0x5
+-#define SEQ03__SEQ_FONT_B1_MASK 0x01L
+-#define SEQ03__SEQ_FONT_B2_MASK 0x02L
+-#define SEQ03__SEQ_FONT_A1_MASK 0x04L
+-#define SEQ03__SEQ_FONT_A2_MASK 0x08L
+-#define SEQ03__SEQ_FONT_B0_MASK 0x10L
+-#define SEQ03__SEQ_FONT_A0_MASK 0x20L
+-//SEQ04
+-#define SEQ04__SEQ_256K__SHIFT 0x1
+-#define SEQ04__SEQ_ODDEVEN__SHIFT 0x2
+-#define SEQ04__SEQ_CHAIN__SHIFT 0x3
+-#define SEQ04__SEQ_256K_MASK 0x02L
+-#define SEQ04__SEQ_ODDEVEN_MASK 0x04L
+-#define SEQ04__SEQ_CHAIN_MASK 0x08L
+-
+-
+-// addressBlock: vgacrtind
+-//CRT00
+-#define CRT00__H_TOTAL__SHIFT 0x0
+-#define CRT00__H_TOTAL_MASK 0xFFL
+-//CRT01
+-#define CRT01__H_DISP_END__SHIFT 0x0
+-#define CRT01__H_DISP_END_MASK 0xFFL
+-//CRT02
+-#define CRT02__H_BLANK_START__SHIFT 0x0
+-#define CRT02__H_BLANK_START_MASK 0xFFL
+-//CRT03
+-#define CRT03__H_BLANK_END__SHIFT 0x0
+-#define CRT03__H_DE_SKEW__SHIFT 0x5
+-#define CRT03__CR10CR11_R_DIS_B__SHIFT 0x7
+-#define CRT03__H_BLANK_END_MASK 0x1FL
+-#define CRT03__H_DE_SKEW_MASK 0x60L
+-#define CRT03__CR10CR11_R_DIS_B_MASK 0x80L
+-//CRT04
+-#define CRT04__H_SYNC_START__SHIFT 0x0
+-#define CRT04__H_SYNC_START_MASK 0xFFL
+-//CRT05
+-#define CRT05__H_SYNC_END__SHIFT 0x0
+-#define CRT05__H_SYNC_SKEW__SHIFT 0x5
+-#define CRT05__H_BLANK_END_B5__SHIFT 0x7
+-#define CRT05__H_SYNC_END_MASK 0x1FL
+-#define CRT05__H_SYNC_SKEW_MASK 0x60L
+-#define CRT05__H_BLANK_END_B5_MASK 0x80L
+-//CRT06
+-#define CRT06__V_TOTAL__SHIFT 0x0
+-#define CRT06__V_TOTAL_MASK 0xFFL
+-//CRT07
+-#define CRT07__V_TOTAL_B8__SHIFT 0x0
+-#define CRT07__V_DISP_END_B8__SHIFT 0x1
+-#define CRT07__V_SYNC_START_B8__SHIFT 0x2
+-#define CRT07__V_BLANK_START_B8__SHIFT 0x3
+-#define CRT07__LINE_CMP_B8__SHIFT 0x4
+-#define CRT07__V_TOTAL_B9__SHIFT 0x5
+-#define CRT07__V_DISP_END_B9__SHIFT 0x6
+-#define CRT07__V_SYNC_START_B9__SHIFT 0x7
+-#define CRT07__V_TOTAL_B8_MASK 0x01L
+-#define CRT07__V_DISP_END_B8_MASK 0x02L
+-#define CRT07__V_SYNC_START_B8_MASK 0x04L
+-#define CRT07__V_BLANK_START_B8_MASK 0x08L
+-#define CRT07__LINE_CMP_B8_MASK 0x10L
+-#define CRT07__V_TOTAL_B9_MASK 0x20L
+-#define CRT07__V_DISP_END_B9_MASK 0x40L
+-#define CRT07__V_SYNC_START_B9_MASK 0x80L
+-//CRT08
+-#define CRT08__ROW_SCAN_START__SHIFT 0x0
+-#define CRT08__BYTE_PAN__SHIFT 0x5
+-#define CRT08__ROW_SCAN_START_MASK 0x1FL
+-#define CRT08__BYTE_PAN_MASK 0x60L
+-//CRT09
+-#define CRT09__MAX_ROW_SCAN__SHIFT 0x0
+-#define CRT09__V_BLANK_START_B9__SHIFT 0x5
+-#define CRT09__LINE_CMP_B9__SHIFT 0x6
+-#define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT 0x7
+-#define CRT09__MAX_ROW_SCAN_MASK 0x1FL
+-#define CRT09__V_BLANK_START_B9_MASK 0x20L
+-#define CRT09__LINE_CMP_B9_MASK 0x40L
+-#define CRT09__DOUBLE_CHAR_HEIGHT_MASK 0x80L
+-//CRT0A
+-#define CRT0A__CURSOR_START__SHIFT 0x0
+-#define CRT0A__CURSOR_DISABLE__SHIFT 0x5
+-#define CRT0A__CURSOR_START_MASK 0x1FL
+-#define CRT0A__CURSOR_DISABLE_MASK 0x20L
+-//CRT0B
+-#define CRT0B__CURSOR_END__SHIFT 0x0
+-#define CRT0B__CURSOR_SKEW__SHIFT 0x5
+-#define CRT0B__CURSOR_END_MASK 0x1FL
+-#define CRT0B__CURSOR_SKEW_MASK 0x60L
+-//CRT0C
+-#define CRT0C__DISP_START__SHIFT 0x0
+-#define CRT0C__DISP_START_MASK 0xFFL
+-//CRT0D
+-#define CRT0D__DISP_START__SHIFT 0x0
+-#define CRT0D__DISP_START_MASK 0xFFL
+-//CRT0E
+-#define CRT0E__CURSOR_LOC_HI__SHIFT 0x0
+-#define CRT0E__CURSOR_LOC_HI_MASK 0xFFL
+-//CRT0F
+-#define CRT0F__CURSOR_LOC_LO__SHIFT 0x0
+-#define CRT0F__CURSOR_LOC_LO_MASK 0xFFL
+-//CRT10
+-#define CRT10__V_SYNC_START__SHIFT 0x0
+-#define CRT10__V_SYNC_START_MASK 0xFFL
+-//CRT11
+-#define CRT11__V_SYNC_END__SHIFT 0x0
+-#define CRT11__V_INTR_CLR__SHIFT 0x4
+-#define CRT11__V_INTR_EN__SHIFT 0x5
+-#define CRT11__SEL5_REFRESH_CYC__SHIFT 0x6
+-#define CRT11__C0T7_WR_ONLY__SHIFT 0x7
+-#define CRT11__V_SYNC_END_MASK 0x0FL
+-#define CRT11__V_INTR_CLR_MASK 0x10L
+-#define CRT11__V_INTR_EN_MASK 0x20L
+-#define CRT11__SEL5_REFRESH_CYC_MASK 0x40L
+-#define CRT11__C0T7_WR_ONLY_MASK 0x80L
+-//CRT12
+-#define CRT12__V_DISP_END__SHIFT 0x0
+-#define CRT12__V_DISP_END_MASK 0xFFL
+-//CRT13
+-#define CRT13__DISP_PITCH__SHIFT 0x0
+-#define CRT13__DISP_PITCH_MASK 0xFFL
+-//CRT14
+-#define CRT14__UNDRLN_LOC__SHIFT 0x0
+-#define CRT14__ADDR_CNT_BY4__SHIFT 0x5
+-#define CRT14__DOUBLE_WORD__SHIFT 0x6
+-#define CRT14__UNDRLN_LOC_MASK 0x1FL
+-#define CRT14__ADDR_CNT_BY4_MASK 0x20L
+-#define CRT14__DOUBLE_WORD_MASK 0x40L
+-//CRT15
+-#define CRT15__V_BLANK_START__SHIFT 0x0
+-#define CRT15__V_BLANK_START_MASK 0xFFL
+-//CRT16
+-#define CRT16__V_BLANK_END__SHIFT 0x0
+-#define CRT16__V_BLANK_END_MASK 0xFFL
+-//CRT17
+-#define CRT17__RA0_AS_A13B__SHIFT 0x0
+-#define CRT17__RA1_AS_A14B__SHIFT 0x1
+-#define CRT17__VCOUNT_BY2__SHIFT 0x2
+-#define CRT17__ADDR_CNT_BY2__SHIFT 0x3
+-#define CRT17__WRAP_A15TOA0__SHIFT 0x5
+-#define CRT17__BYTE_MODE__SHIFT 0x6
+-#define CRT17__CRTC_SYNC_EN__SHIFT 0x7
+-#define CRT17__RA0_AS_A13B_MASK 0x01L
+-#define CRT17__RA1_AS_A14B_MASK 0x02L
+-#define CRT17__VCOUNT_BY2_MASK 0x04L
+-#define CRT17__ADDR_CNT_BY2_MASK 0x08L
+-#define CRT17__WRAP_A15TOA0_MASK 0x20L
+-#define CRT17__BYTE_MODE_MASK 0x40L
+-#define CRT17__CRTC_SYNC_EN_MASK 0x80L
+-//CRT18
+-#define CRT18__LINE_CMP__SHIFT 0x0
+-#define CRT18__LINE_CMP_MASK 0xFFL
+-//CRT1E
+-#define CRT1E__GRPH_DEC_RD1__SHIFT 0x1
+-#define CRT1E__GRPH_DEC_RD1_MASK 0x02L
+-//CRT1F
+-#define CRT1F__GRPH_DEC_RD0__SHIFT 0x0
+-#define CRT1F__GRPH_DEC_RD0_MASK 0xFFL
+-//CRT22
+-#define CRT22__GRPH_LATCH_DATA__SHIFT 0x0
+-#define CRT22__GRPH_LATCH_DATA_MASK 0xFFL
+-
+-
+-// addressBlock: vgagrphind
+-//GRA00
+-#define GRA00__GRPH_SET_RESET0__SHIFT 0x0
+-#define GRA00__GRPH_SET_RESET1__SHIFT 0x1
+-#define GRA00__GRPH_SET_RESET2__SHIFT 0x2
+-#define GRA00__GRPH_SET_RESET3__SHIFT 0x3
+-#define GRA00__GRPH_SET_RESET0_MASK 0x01L
+-#define GRA00__GRPH_SET_RESET1_MASK 0x02L
+-#define GRA00__GRPH_SET_RESET2_MASK 0x04L
+-#define GRA00__GRPH_SET_RESET3_MASK 0x08L
+-//GRA01
+-#define GRA01__GRPH_SET_RESET_ENA0__SHIFT 0x0
+-#define GRA01__GRPH_SET_RESET_ENA1__SHIFT 0x1
+-#define GRA01__GRPH_SET_RESET_ENA2__SHIFT 0x2
+-#define GRA01__GRPH_SET_RESET_ENA3__SHIFT 0x3
+-#define GRA01__GRPH_SET_RESET_ENA0_MASK 0x01L
+-#define GRA01__GRPH_SET_RESET_ENA1_MASK 0x02L
+-#define GRA01__GRPH_SET_RESET_ENA2_MASK 0x04L
+-#define GRA01__GRPH_SET_RESET_ENA3_MASK 0x08L
+-//GRA02
+-#define GRA02__GRPH_CCOMP__SHIFT 0x0
+-#define GRA02__GRPH_CCOMP_MASK 0x0FL
+-//GRA03
+-#define GRA03__GRPH_ROTATE__SHIFT 0x0
+-#define GRA03__GRPH_FN_SEL__SHIFT 0x3
+-#define GRA03__GRPH_ROTATE_MASK 0x07L
+-#define GRA03__GRPH_FN_SEL_MASK 0x18L
+-//GRA04
+-#define GRA04__GRPH_RMAP__SHIFT 0x0
+-#define GRA04__GRPH_RMAP_MASK 0x03L
+-//GRA05
+-#define GRA05__GRPH_WRITE_MODE__SHIFT 0x0
+-#define GRA05__GRPH_READ1__SHIFT 0x3
+-#define GRA05__CGA_ODDEVEN__SHIFT 0x4
+-#define GRA05__GRPH_OES__SHIFT 0x5
+-#define GRA05__GRPH_PACK__SHIFT 0x6
+-#define GRA05__GRPH_WRITE_MODE_MASK 0x03L
+-#define GRA05__GRPH_READ1_MASK 0x08L
+-#define GRA05__CGA_ODDEVEN_MASK 0x10L
+-#define GRA05__GRPH_OES_MASK 0x20L
+-#define GRA05__GRPH_PACK_MASK 0x40L
+-//GRA06
+-#define GRA06__GRPH_GRAPHICS__SHIFT 0x0
+-#define GRA06__GRPH_ODDEVEN__SHIFT 0x1
+-#define GRA06__GRPH_ADRSEL__SHIFT 0x2
+-#define GRA06__GRPH_GRAPHICS_MASK 0x01L
+-#define GRA06__GRPH_ODDEVEN_MASK 0x02L
+-#define GRA06__GRPH_ADRSEL_MASK 0x0CL
+-//GRA07
+-#define GRA07__GRPH_XCARE0__SHIFT 0x0
+-#define GRA07__GRPH_XCARE1__SHIFT 0x1
+-#define GRA07__GRPH_XCARE2__SHIFT 0x2
+-#define GRA07__GRPH_XCARE3__SHIFT 0x3
+-#define GRA07__GRPH_XCARE0_MASK 0x01L
+-#define GRA07__GRPH_XCARE1_MASK 0x02L
+-#define GRA07__GRPH_XCARE2_MASK 0x04L
+-#define GRA07__GRPH_XCARE3_MASK 0x08L
+-//GRA08
+-#define GRA08__GRPH_BMSK__SHIFT 0x0
+-#define GRA08__GRPH_BMSK_MASK 0xFFL
+-
+-
+-// addressBlock: vgaattrind
+-//ATTR00
+-#define ATTR00__ATTR_PAL__SHIFT 0x0
+-#define ATTR00__ATTR_PAL_MASK 0x3FL
+-//ATTR01
+-#define ATTR01__ATTR_PAL__SHIFT 0x0
+-#define ATTR01__ATTR_PAL_MASK 0x3FL
+-//ATTR02
+-#define ATTR02__ATTR_PAL__SHIFT 0x0
+-#define ATTR02__ATTR_PAL_MASK 0x3FL
+-//ATTR03
+-#define ATTR03__ATTR_PAL__SHIFT 0x0
+-#define ATTR03__ATTR_PAL_MASK 0x3FL
+-//ATTR04
+-#define ATTR04__ATTR_PAL__SHIFT 0x0
+-#define ATTR04__ATTR_PAL_MASK 0x3FL
+-//ATTR05
+-#define ATTR05__ATTR_PAL__SHIFT 0x0
+-#define ATTR05__ATTR_PAL_MASK 0x3FL
+-//ATTR06
+-#define ATTR06__ATTR_PAL__SHIFT 0x0
+-#define ATTR06__ATTR_PAL_MASK 0x3FL
+-//ATTR07
+-#define ATTR07__ATTR_PAL__SHIFT 0x0
+-#define ATTR07__ATTR_PAL_MASK 0x3FL
+-//ATTR08
+-#define ATTR08__ATTR_PAL__SHIFT 0x0
+-#define ATTR08__ATTR_PAL_MASK 0x3FL
+-//ATTR09
+-#define ATTR09__ATTR_PAL__SHIFT 0x0
+-#define ATTR09__ATTR_PAL_MASK 0x3FL
+-//ATTR0A
+-#define ATTR0A__ATTR_PAL__SHIFT 0x0
+-#define ATTR0A__ATTR_PAL_MASK 0x3FL
+-//ATTR0B
+-#define ATTR0B__ATTR_PAL__SHIFT 0x0
+-#define ATTR0B__ATTR_PAL_MASK 0x3FL
+-//ATTR0C
+-#define ATTR0C__ATTR_PAL__SHIFT 0x0
+-#define ATTR0C__ATTR_PAL_MASK 0x3FL
+-//ATTR0D
+-#define ATTR0D__ATTR_PAL__SHIFT 0x0
+-#define ATTR0D__ATTR_PAL_MASK 0x3FL
+-//ATTR0E
+-#define ATTR0E__ATTR_PAL__SHIFT 0x0
+-#define ATTR0E__ATTR_PAL_MASK 0x3FL
+-//ATTR0F
+-#define ATTR0F__ATTR_PAL__SHIFT 0x0
+-#define ATTR0F__ATTR_PAL_MASK 0x3FL
+-//ATTR10
+-#define ATTR10__ATTR_GRPH_MODE__SHIFT 0x0
+-#define ATTR10__ATTR_MONO_EN__SHIFT 0x1
+-#define ATTR10__ATTR_LGRPH_EN__SHIFT 0x2
+-#define ATTR10__ATTR_BLINK_EN__SHIFT 0x3
+-#define ATTR10__ATTR_PANTOPONLY__SHIFT 0x5
+-#define ATTR10__ATTR_PCLKBY2__SHIFT 0x6
+-#define ATTR10__ATTR_CSEL_EN__SHIFT 0x7
+-#define ATTR10__ATTR_GRPH_MODE_MASK 0x01L
+-#define ATTR10__ATTR_MONO_EN_MASK 0x02L
+-#define ATTR10__ATTR_LGRPH_EN_MASK 0x04L
+-#define ATTR10__ATTR_BLINK_EN_MASK 0x08L
+-#define ATTR10__ATTR_PANTOPONLY_MASK 0x20L
+-#define ATTR10__ATTR_PCLKBY2_MASK 0x40L
+-#define ATTR10__ATTR_CSEL_EN_MASK 0x80L
+-//ATTR11
+-#define ATTR11__ATTR_OVSC__SHIFT 0x0
+-#define ATTR11__ATTR_OVSC_MASK 0xFFL
+-//ATTR12
+-#define ATTR12__ATTR_MAP_EN__SHIFT 0x0
+-#define ATTR12__ATTR_VSMUX__SHIFT 0x4
+-#define ATTR12__ATTR_MAP_EN_MASK 0x0FL
+-#define ATTR12__ATTR_VSMUX_MASK 0x30L
+-//ATTR13
+-#define ATTR13__ATTR_PPAN__SHIFT 0x0
+-#define ATTR13__ATTR_PPAN_MASK 0x0FL
+-//ATTR14
+-#define ATTR14__ATTR_CSEL1__SHIFT 0x0
+-#define ATTR14__ATTR_CSEL2__SHIFT 0x2
+-#define ATTR14__ATTR_CSEL1_MASK 0x03L
+-#define ATTR14__ATTR_CSEL2_MASK 0x0CL
+-
+-
+-#endif
+--
+2.7.4
+
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-05-01 08:20:50 +0000